1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 IsWin64 = Subtarget->isTargetWin64();
49 StackAlign = TM.getFrameInfo()->getStackAlignment();
61 // getDwarfRegNum - This function maps LLVM register identifiers to the
62 // Dwarf specific numbering, used in debug info and exception tables.
64 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
65 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
66 unsigned Flavour = DWARFFlavour::X86_64;
67 if (!Subtarget->is64Bit()) {
68 if (Subtarget->isTargetDarwin()) {
70 Flavour = DWARFFlavour::X86_32_DarwinEH;
72 Flavour = DWARFFlavour::X86_32_Generic;
73 } else if (Subtarget->isTargetCygMing()) {
74 // Unsupported by now, just quick fallback
75 Flavour = DWARFFlavour::X86_32_Generic;
77 Flavour = DWARFFlavour::X86_32_Generic;
81 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84 // getX86RegNum - This function maps LLVM register identifiers to their X86
85 // specific numbering, which is used in various places encoding instructions.
87 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
89 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
90 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
91 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
92 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
93 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
95 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
97 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
99 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
106 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
108 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
110 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
112 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
114 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
120 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
121 return RegNo-X86::ST0;
123 case X86::XMM0: case X86::XMM8: case X86::MM0:
125 case X86::XMM1: case X86::XMM9: case X86::MM1:
127 case X86::XMM2: case X86::XMM10: case X86::MM2:
129 case X86::XMM3: case X86::XMM11: case X86::MM3:
131 case X86::XMM4: case X86::XMM12: case X86::MM4:
133 case X86::XMM5: case X86::XMM13: case X86::MM5:
135 case X86::XMM6: case X86::XMM14: case X86::MM6:
137 case X86::XMM7: case X86::XMM15: case X86::MM7:
141 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
142 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
147 const TargetRegisterClass *
148 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
149 if (RC == &X86::CCRRegClass) {
151 return &X86::GR64RegClass;
153 return &X86::GR32RegClass;
159 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
160 static const unsigned CalleeSavedRegs32Bit[] = {
161 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
164 static const unsigned CalleeSavedRegs32EHRet[] = {
165 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
168 static const unsigned CalleeSavedRegs64Bit[] = {
169 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
172 static const unsigned CalleeSavedRegsWin64[] = {
173 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
174 X86::R12, X86::R13, X86::R14, X86::R15, 0
179 return CalleeSavedRegsWin64;
181 return CalleeSavedRegs64Bit;
184 MachineFrameInfo *MFI = MF->getFrameInfo();
185 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
186 if (MMI && MMI->callsEHReturn())
187 return CalleeSavedRegs32EHRet;
189 return CalleeSavedRegs32Bit;
193 const TargetRegisterClass* const*
194 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
195 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
196 &X86::GR32RegClass, &X86::GR32RegClass,
197 &X86::GR32RegClass, &X86::GR32RegClass, 0
199 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
200 &X86::GR32RegClass, &X86::GR32RegClass,
201 &X86::GR32RegClass, &X86::GR32RegClass,
202 &X86::GR32RegClass, &X86::GR32RegClass, 0
204 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
205 &X86::GR64RegClass, &X86::GR64RegClass,
206 &X86::GR64RegClass, &X86::GR64RegClass,
207 &X86::GR64RegClass, &X86::GR64RegClass, 0
209 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
210 &X86::GR64RegClass, &X86::GR64RegClass,
211 &X86::GR64RegClass, &X86::GR64RegClass,
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass, 0
218 return CalleeSavedRegClassesWin64;
220 return CalleeSavedRegClasses64Bit;
223 MachineFrameInfo *MFI = MF->getFrameInfo();
224 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 if (MMI && MMI->callsEHReturn())
226 return CalleeSavedRegClasses32EHRet;
228 return CalleeSavedRegClasses32Bit;
233 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
234 BitVector Reserved(getNumRegs());
235 Reserved.set(X86::RSP);
236 Reserved.set(X86::ESP);
237 Reserved.set(X86::SP);
238 Reserved.set(X86::SPL);
240 Reserved.set(X86::RBP);
241 Reserved.set(X86::EBP);
242 Reserved.set(X86::BP);
243 Reserved.set(X86::BPL);
248 //===----------------------------------------------------------------------===//
249 // Stack Frame Processing methods
250 //===----------------------------------------------------------------------===//
252 // hasFP - Return true if the specified function should have a dedicated frame
253 // pointer register. This is true if the function has variable sized allocas or
254 // if frame pointer elimination is disabled.
256 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
257 MachineFrameInfo *MFI = MF.getFrameInfo();
258 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
260 return (NoFramePointerElim ||
261 needsStackRealignment(MF) ||
262 MFI->hasVarSizedObjects() ||
263 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
264 (MMI && MMI->callsUnwindInit()));
267 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
268 MachineFrameInfo *MFI = MF.getFrameInfo();;
270 // FIXME: Currently we don't support stack realignment for functions with
271 // variable-sized allocas
272 return (RealignStack &&
273 (MFI->getMaxAlignment() > StackAlign &&
274 !MFI->hasVarSizedObjects()));
277 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
278 return !MF.getFrameInfo()->hasVarSizedObjects();
282 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
283 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
285 return Offset + MF.getFrameInfo()->getStackSize();
287 // Skip the saved EBP
290 // Skip the RETADDR move area
291 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
292 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
293 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
297 void X86RegisterInfo::
298 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
299 MachineBasicBlock::iterator I) const {
300 if (!hasReservedCallFrame(MF)) {
301 // If the stack pointer can be changed after prologue, turn the
302 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
303 // adjcallstackdown instruction into 'add ESP, <amt>'
304 // TODO: consider using push / pop instead of sub + store / add
305 MachineInstr *Old = I;
306 uint64_t Amount = Old->getOperand(0).getImm();
308 // We need to keep the stack aligned properly. To do this, we round the
309 // amount of space needed for the outgoing arguments up to the next
310 // alignment boundary.
311 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
313 MachineInstr *New = 0;
314 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
315 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
316 .addReg(StackPtr).addImm(Amount);
318 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
319 // factor out the amount the callee already popped.
320 uint64_t CalleeAmt = Old->getOperand(1).getImm();
323 unsigned Opc = (Amount < 128) ?
324 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
325 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
326 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
330 // Replace the pseudo instruction with a new instruction...
331 if (New) MBB.insert(I, New);
333 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
334 // If we are performing frame pointer elimination and if the callee pops
335 // something off the stack pointer, add it back. We do this until we have
336 // more advanced stack pointer tracking ability.
337 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
338 unsigned Opc = (CalleeAmt < 128) ?
339 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
340 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
342 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
350 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
351 int SPAdj, RegScavenger *RS) const{
352 assert(SPAdj == 0 && "Unexpected");
355 MachineInstr &MI = *II;
356 MachineFunction &MF = *MI.getParent()->getParent();
357 while (!MI.getOperand(i).isFrameIndex()) {
359 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
362 int FrameIndex = MI.getOperand(i).getIndex();
363 // This must be part of a four operand memory reference. Replace the
364 // FrameIndex with base register with EBP. Add an offset to the offset.
365 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
367 // Now add the frame object offset to the offset from EBP.
368 int64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
369 MI.getOperand(i+3).getImm();
371 MI.getOperand(i+3).ChangeToImmediate(Offset);
375 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
376 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
377 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
378 if (TailCallReturnAddrDelta < 0) {
379 // create RETURNADDR area
389 CreateFixedObject(-TailCallReturnAddrDelta,
390 (-1*SlotSize)+TailCallReturnAddrDelta);
393 assert((TailCallReturnAddrDelta <= 0) &&
394 "The Delta should always be zero or negative");
395 // Create a frame entry for the EBP register that must be saved.
396 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
398 TailCallReturnAddrDelta);
399 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
400 "Slot for EBP register must be last in order to be found!");
404 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
405 /// stack pointer by a constant value.
407 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
408 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
409 const TargetInstrInfo &TII) {
410 bool isSub = NumBytes < 0;
411 uint64_t Offset = isSub ? -NumBytes : NumBytes;
414 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
415 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
417 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
418 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
419 uint64_t Chunk = (1LL << 31) - 1;
422 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
423 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
428 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
430 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
431 unsigned StackPtr, uint64_t *NumBytes = NULL) {
432 if (MBBI == MBB.begin()) return;
434 MachineBasicBlock::iterator PI = prior(MBBI);
435 unsigned Opc = PI->getOpcode();
436 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
437 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
438 PI->getOperand(0).getReg() == StackPtr) {
440 *NumBytes += PI->getOperand(2).getImm();
442 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
443 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
444 PI->getOperand(0).getReg() == StackPtr) {
446 *NumBytes -= PI->getOperand(2).getImm();
451 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
453 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
454 MachineBasicBlock::iterator &MBBI,
455 unsigned StackPtr, uint64_t *NumBytes = NULL) {
458 if (MBBI == MBB.end()) return;
460 MachineBasicBlock::iterator NI = next(MBBI);
461 if (NI == MBB.end()) return;
463 unsigned Opc = NI->getOpcode();
464 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
465 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
466 NI->getOperand(0).getReg() == StackPtr) {
468 *NumBytes -= NI->getOperand(2).getImm();
471 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
472 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
473 NI->getOperand(0).getReg() == StackPtr) {
475 *NumBytes += NI->getOperand(2).getImm();
481 /// mergeSPUpdates - Checks the instruction before/after the passed
482 /// instruction. If it is an ADD/SUB instruction it is deleted
483 /// argument and the stack adjustment is returned as a positive value for ADD
484 /// and a negative for SUB.
485 static int mergeSPUpdates(MachineBasicBlock &MBB,
486 MachineBasicBlock::iterator &MBBI,
488 bool doMergeWithPrevious) {
490 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
491 (!doMergeWithPrevious && MBBI == MBB.end()))
496 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
497 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
498 unsigned Opc = PI->getOpcode();
499 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
500 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
501 PI->getOperand(0).getReg() == StackPtr){
502 Offset += PI->getOperand(2).getImm();
504 if (!doMergeWithPrevious) MBBI = NI;
505 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
506 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
507 PI->getOperand(0).getReg() == StackPtr) {
508 Offset -= PI->getOperand(2).getImm();
510 if (!doMergeWithPrevious) MBBI = NI;
516 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
517 unsigned FrameLabelId,
518 unsigned ReadyLabelId) const {
519 MachineFrameInfo *MFI = MF.getFrameInfo();
520 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
524 uint64_t StackSize = MFI->getStackSize();
525 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
526 const TargetData *TD = MF.getTarget().getTargetData();
528 // Calculate amount of bytes used for return address storing
530 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
531 TargetFrameInfo::StackGrowsUp ?
532 TD->getPointerSize() : -TD->getPointerSize());
535 // Show update of SP.
538 MachineLocation SPDst(MachineLocation::VirtualFP);
539 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
540 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
542 MachineLocation SPDst(MachineLocation::VirtualFP);
543 MachineLocation SPSrc(MachineLocation::VirtualFP,
544 -StackSize+stackGrowth);
545 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
548 //FIXME: Verify & implement for FP
549 MachineLocation SPDst(StackPtr);
550 MachineLocation SPSrc(StackPtr, stackGrowth);
551 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
554 // Add callee saved registers to move list.
555 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
557 // FIXME: This is dirty hack. The code itself is pretty mess right now.
558 // It should be rewritten from scratch and generalized sometimes.
560 // Determine maximum offset (minumum due to stack growth)
561 int64_t MaxOffset = 0;
562 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
563 MaxOffset = std::min(MaxOffset,
564 MFI->getObjectOffset(CSI[I].getFrameIdx()));
567 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
568 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
569 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
570 unsigned Reg = CSI[I].getReg();
571 Offset = (MaxOffset-Offset+saveAreaOffset);
572 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
573 MachineLocation CSSrc(Reg);
574 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
579 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
580 MachineLocation FPSrc(FramePtr);
581 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
584 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
585 MachineLocation FPSrc(MachineLocation::VirtualFP);
586 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
590 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
591 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
592 MachineFrameInfo *MFI = MF.getFrameInfo();
593 const Function* Fn = MF.getFunction();
594 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
595 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
596 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
597 MachineBasicBlock::iterator MBBI = MBB.begin();
598 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
599 !Fn->doesNotThrow() ||
600 UnwindTablesMandatory;
601 // Prepare for frame info.
602 unsigned FrameLabelId = 0;
604 // Get the number of bytes to allocate from the FrameInfo.
605 uint64_t StackSize = MFI->getStackSize();
606 // Add RETADDR move area to callee saved frame size.
607 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
608 if (TailCallReturnAddrDelta < 0)
609 X86FI->setCalleeSavedFrameSize(
610 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
611 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
613 // Insert stack pointer adjustment for later moving of return addr. Only
614 // applies to tail call optimized functions where the callee argument stack
615 // size is bigger than the callers.
616 if (TailCallReturnAddrDelta < 0) {
617 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
618 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
622 // Get the offset of the stack slot for the EBP register... which is
623 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
624 // Update the frame offset adjustment.
625 MFI->setOffsetAdjustment(SlotSize-NumBytes);
627 // Save EBP into the appropriate stack slot...
628 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
630 NumBytes -= SlotSize;
632 if (needsFrameMoves) {
633 // Mark effective beginning of when frame pointer becomes valid.
634 FrameLabelId = MMI->NextLabelID();
635 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
638 // Update EBP with the new base value...
639 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
643 unsigned ReadyLabelId = 0;
644 if (needsFrameMoves) {
645 // Mark effective beginning of when frame pointer is ready.
646 ReadyLabelId = MMI->NextLabelID();
647 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
650 // Skip the callee-saved push instructions.
651 while (MBBI != MBB.end() &&
652 (MBBI->getOpcode() == X86::PUSH32r ||
653 MBBI->getOpcode() == X86::PUSH64r))
656 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
657 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
658 // Check, whether EAX is livein for this function
659 bool isEAXAlive = false;
660 for (MachineRegisterInfo::livein_iterator
661 II = MF.getRegInfo().livein_begin(),
662 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
663 unsigned Reg = II->first;
664 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
665 Reg == X86::AH || Reg == X86::AL);
668 // Function prologue calls _alloca to probe the stack when allocating
669 // more than 4k bytes in one go. Touching the stack at 4K increments is
670 // necessary to ensure that the guard pages used by the OS virtual memory
671 // manager are allocated in correct sequence.
673 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
674 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
675 .addExternalSymbol("_alloca");
678 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
679 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
680 // allocated bytes for EAX.
681 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
682 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
683 .addExternalSymbol("_alloca");
685 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
686 StackPtr, NumBytes-4);
687 MBB.insert(MBBI, MI);
690 // If there is an SUB32ri of ESP immediately before this instruction,
691 // merge the two. This can be the case when tail call elimination is
692 // enabled and the callee has more arguments then the caller.
693 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
694 // If there is an ADD32ri or SUB32ri of ESP immediately after this
695 // instruction, merge the two instructions.
696 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
699 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
704 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
706 // If it's main() on Cygwin\Mingw32 we should align stack as well
707 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
708 Subtarget->isTargetCygMing()) {
709 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
710 .addReg(X86::ESP).addImm(-StackAlign);
713 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
714 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
718 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
719 MachineBasicBlock &MBB) const {
720 const MachineFrameInfo *MFI = MF.getFrameInfo();
721 const Function* Fn = MF.getFunction();
722 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
723 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
724 MachineBasicBlock::iterator MBBI = prior(MBB.end());
725 unsigned RetOpcode = MBBI->getOpcode();
730 case X86::TCRETURNdi:
731 case X86::TCRETURNri:
732 case X86::TCRETURNri64:
733 case X86::TCRETURNdi64:
737 case X86::TAILJMPm: break; // These are ok
739 assert(0 && "Can only insert epilog into returning blocks");
742 // Get the number of bytes to allocate from the FrameInfo
743 uint64_t StackSize = MFI->getStackSize();
744 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
745 uint64_t NumBytes = StackSize - CSSize;
749 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
750 NumBytes -= SlotSize;
753 // Skip the callee-saved pop instructions.
754 while (MBBI != MBB.begin()) {
755 MachineBasicBlock::iterator PI = prior(MBBI);
756 unsigned Opc = PI->getOpcode();
757 if (Opc != X86::POP32r && Opc != X86::POP64r &&
758 !PI->getDesc().isTerminator())
763 // If there is an ADD32ri or SUB32ri of ESP immediately before this
764 // instruction, merge the two instructions.
765 if (NumBytes || MFI->hasVarSizedObjects())
766 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
768 // If dynamic alloca is used, then reset esp to point to the last callee-saved
769 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
770 // aligned stack in the prologue, - revert stack changes back. Note: we're
771 // assuming, that frame pointer was forced for main()
772 if (MFI->hasVarSizedObjects() ||
773 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
774 Subtarget->isTargetCygMing())) {
775 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
777 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
779 MBB.insert(MBBI, MI);
781 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
787 // adjust stack pointer back: ESP += numbytes
789 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
791 // We're returning from function via eh_return.
792 if (RetOpcode == X86::EH_RETURN) {
793 MBBI = prior(MBB.end());
794 MachineOperand &DestAddr = MBBI->getOperand(0);
795 assert(DestAddr.isRegister() && "Offset should be in register!");
796 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
797 addReg(DestAddr.getReg());
798 // Tail call return: adjust the stack pointer and jump to callee
799 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
800 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
801 MBBI = prior(MBB.end());
802 MachineOperand &JumpTarget = MBBI->getOperand(0);
803 MachineOperand &StackAdjust = MBBI->getOperand(1);
804 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
806 // Adjust stack pointer.
807 int StackAdj = StackAdjust.getImm();
808 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
810 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
811 // Incoporate the retaddr area.
812 Offset = StackAdj-MaxTCDelta;
813 assert(Offset >= 0 && "Offset should never be negative");
815 // Check for possible merge with preceeding ADD instruction.
816 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
817 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
819 // Jump to label or value in register.
820 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
821 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
822 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
823 else if (RetOpcode== X86::TCRETURNri64) {
824 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
826 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
827 // Delete the pseudo instruction TCRETURN.
829 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
830 (X86FI->getTCReturnAddrDelta() < 0)) {
831 // Add the return addr area delta back since we are not tail calling.
832 int delta = -1*X86FI->getTCReturnAddrDelta();
833 MBBI = prior(MBB.end());
834 // Check for possible merge with preceeding ADD instruction.
835 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
836 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
840 unsigned X86RegisterInfo::getRARegister() const {
842 return X86::RIP; // Should have dwarf #16
844 return X86::EIP; // Should have dwarf #8
847 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
848 return hasFP(MF) ? FramePtr : StackPtr;
851 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
853 // Calculate amount of bytes used for return address storing
854 int stackGrowth = (Is64Bit ? -8 : -4);
856 // Initial state of the frame pointer is esp+4.
857 MachineLocation Dst(MachineLocation::VirtualFP);
858 MachineLocation Src(StackPtr, stackGrowth);
859 Moves.push_back(MachineMove(0, Dst, Src));
861 // Add return address to move list
862 MachineLocation CSDst(StackPtr, stackGrowth);
863 MachineLocation CSSrc(getRARegister());
864 Moves.push_back(MachineMove(0, CSDst, CSSrc));
867 unsigned X86RegisterInfo::getEHExceptionRegister() const {
868 assert(0 && "What is the exception register");
872 unsigned X86RegisterInfo::getEHHandlerRegister() const {
873 assert(0 && "What is the exception handler register");
878 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
885 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
887 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
889 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
891 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
897 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
899 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
901 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
903 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
905 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
907 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
909 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
911 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
913 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
915 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
917 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
919 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
921 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
923 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
925 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
927 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
934 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
936 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
938 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
940 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
942 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
944 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
946 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
948 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
950 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
952 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
954 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
956 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
958 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
960 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
962 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
964 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
970 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
972 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
974 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
976 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
978 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
980 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
982 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
984 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
986 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
988 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
990 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
992 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
994 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
996 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
998 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1000 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1005 default: return Reg;
1006 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1008 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1010 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1012 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1014 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1016 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1018 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1020 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1022 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1024 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1026 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1028 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1030 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1032 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1034 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1036 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1045 #include "X86GenRegisterInfo.inc"