1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
43 #define DEBUG_TYPE "x86-instr-info"
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
49 NoFusing("disable-spill-fusing",
50 cl::desc("Disable fusing of spill code into instructions"));
52 PrintFailedFusing("print-failed-fuse-candidates",
53 cl::desc("Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
57 ReMatPICStubLoad("remat-pic-stub-load",
58 cl::desc("Re-materialize load from stub in PIC mode"),
59 cl::init(false), cl::Hidden);
62 // Select which memory operand is being unfolded.
63 // (stored in bits 0 - 3)
71 // Do not insert the reverse map (MemOp -> RegOp) into the table.
72 // This may be needed because there is a many -> one mapping.
73 TB_NO_REVERSE = 1 << 4,
75 // Do not insert the forward map (RegOp -> MemOp) into the table.
76 // This is needed for Native Client, which prohibits branch
77 // instructions from using a memory operand.
78 TB_NO_FORWARD = 1 << 5,
80 TB_FOLDED_LOAD = 1 << 6,
81 TB_FOLDED_STORE = 1 << 7,
83 // Minimum alignment required for load/store.
84 // Used for RegOp->MemOp conversion.
85 // (stored in bits 8 - 15)
87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
94 struct X86MemoryFoldTableEntry {
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
107 Subtarget(STI), RI(STI.getTargetTriple()) {
109 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
149 { X86::DEC64r, X86::DEC64m, 0 },
150 { X86::DEC8r, X86::DEC8m, 0 },
151 { X86::INC16r, X86::INC16m, 0 },
152 { X86::INC32r, X86::INC32m, 0 },
153 { X86::INC64r, X86::INC64m, 0 },
154 { X86::INC8r, X86::INC8m, 0 },
155 { X86::NEG16r, X86::NEG16m, 0 },
156 { X86::NEG32r, X86::NEG32m, 0 },
157 { X86::NEG64r, X86::NEG64m, 0 },
158 { X86::NEG8r, X86::NEG8m, 0 },
159 { X86::NOT16r, X86::NOT16m, 0 },
160 { X86::NOT32r, X86::NOT32m, 0 },
161 { X86::NOT64r, X86::NOT64m, 0 },
162 { X86::NOT8r, X86::NOT8m, 0 },
163 { X86::OR16ri, X86::OR16mi, 0 },
164 { X86::OR16ri8, X86::OR16mi8, 0 },
165 { X86::OR16rr, X86::OR16mr, 0 },
166 { X86::OR32ri, X86::OR32mi, 0 },
167 { X86::OR32ri8, X86::OR32mi8, 0 },
168 { X86::OR32rr, X86::OR32mr, 0 },
169 { X86::OR64ri32, X86::OR64mi32, 0 },
170 { X86::OR64ri8, X86::OR64mi8, 0 },
171 { X86::OR64rr, X86::OR64mr, 0 },
172 { X86::OR8ri, X86::OR8mi, 0 },
173 { X86::OR8rr, X86::OR8mr, 0 },
174 { X86::ROL16r1, X86::ROL16m1, 0 },
175 { X86::ROL16rCL, X86::ROL16mCL, 0 },
176 { X86::ROL16ri, X86::ROL16mi, 0 },
177 { X86::ROL32r1, X86::ROL32m1, 0 },
178 { X86::ROL32rCL, X86::ROL32mCL, 0 },
179 { X86::ROL32ri, X86::ROL32mi, 0 },
180 { X86::ROL64r1, X86::ROL64m1, 0 },
181 { X86::ROL64rCL, X86::ROL64mCL, 0 },
182 { X86::ROL64ri, X86::ROL64mi, 0 },
183 { X86::ROL8r1, X86::ROL8m1, 0 },
184 { X86::ROL8rCL, X86::ROL8mCL, 0 },
185 { X86::ROL8ri, X86::ROL8mi, 0 },
186 { X86::ROR16r1, X86::ROR16m1, 0 },
187 { X86::ROR16rCL, X86::ROR16mCL, 0 },
188 { X86::ROR16ri, X86::ROR16mi, 0 },
189 { X86::ROR32r1, X86::ROR32m1, 0 },
190 { X86::ROR32rCL, X86::ROR32mCL, 0 },
191 { X86::ROR32ri, X86::ROR32mi, 0 },
192 { X86::ROR64r1, X86::ROR64m1, 0 },
193 { X86::ROR64rCL, X86::ROR64mCL, 0 },
194 { X86::ROR64ri, X86::ROR64mi, 0 },
195 { X86::ROR8r1, X86::ROR8m1, 0 },
196 { X86::ROR8rCL, X86::ROR8mCL, 0 },
197 { X86::ROR8ri, X86::ROR8mi, 0 },
198 { X86::SAR16r1, X86::SAR16m1, 0 },
199 { X86::SAR16rCL, X86::SAR16mCL, 0 },
200 { X86::SAR16ri, X86::SAR16mi, 0 },
201 { X86::SAR32r1, X86::SAR32m1, 0 },
202 { X86::SAR32rCL, X86::SAR32mCL, 0 },
203 { X86::SAR32ri, X86::SAR32mi, 0 },
204 { X86::SAR64r1, X86::SAR64m1, 0 },
205 { X86::SAR64rCL, X86::SAR64mCL, 0 },
206 { X86::SAR64ri, X86::SAR64mi, 0 },
207 { X86::SAR8r1, X86::SAR8m1, 0 },
208 { X86::SAR8rCL, X86::SAR8mCL, 0 },
209 { X86::SAR8ri, X86::SAR8mi, 0 },
210 { X86::SBB32ri, X86::SBB32mi, 0 },
211 { X86::SBB32ri8, X86::SBB32mi8, 0 },
212 { X86::SBB32rr, X86::SBB32mr, 0 },
213 { X86::SBB64ri32, X86::SBB64mi32, 0 },
214 { X86::SBB64ri8, X86::SBB64mi8, 0 },
215 { X86::SBB64rr, X86::SBB64mr, 0 },
216 { X86::SHL16rCL, X86::SHL16mCL, 0 },
217 { X86::SHL16ri, X86::SHL16mi, 0 },
218 { X86::SHL32rCL, X86::SHL32mCL, 0 },
219 { X86::SHL32ri, X86::SHL32mi, 0 },
220 { X86::SHL64rCL, X86::SHL64mCL, 0 },
221 { X86::SHL64ri, X86::SHL64mi, 0 },
222 { X86::SHL8rCL, X86::SHL8mCL, 0 },
223 { X86::SHL8ri, X86::SHL8mi, 0 },
224 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
225 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
226 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
227 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
228 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
229 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
230 { X86::SHR16r1, X86::SHR16m1, 0 },
231 { X86::SHR16rCL, X86::SHR16mCL, 0 },
232 { X86::SHR16ri, X86::SHR16mi, 0 },
233 { X86::SHR32r1, X86::SHR32m1, 0 },
234 { X86::SHR32rCL, X86::SHR32mCL, 0 },
235 { X86::SHR32ri, X86::SHR32mi, 0 },
236 { X86::SHR64r1, X86::SHR64m1, 0 },
237 { X86::SHR64rCL, X86::SHR64mCL, 0 },
238 { X86::SHR64ri, X86::SHR64mi, 0 },
239 { X86::SHR8r1, X86::SHR8m1, 0 },
240 { X86::SHR8rCL, X86::SHR8mCL, 0 },
241 { X86::SHR8ri, X86::SHR8mi, 0 },
242 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
243 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
244 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
245 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
246 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
247 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
248 { X86::SUB16ri, X86::SUB16mi, 0 },
249 { X86::SUB16ri8, X86::SUB16mi8, 0 },
250 { X86::SUB16rr, X86::SUB16mr, 0 },
251 { X86::SUB32ri, X86::SUB32mi, 0 },
252 { X86::SUB32ri8, X86::SUB32mi8, 0 },
253 { X86::SUB32rr, X86::SUB32mr, 0 },
254 { X86::SUB64ri32, X86::SUB64mi32, 0 },
255 { X86::SUB64ri8, X86::SUB64mi8, 0 },
256 { X86::SUB64rr, X86::SUB64mr, 0 },
257 { X86::SUB8ri, X86::SUB8mi, 0 },
258 { X86::SUB8rr, X86::SUB8mr, 0 },
259 { X86::XOR16ri, X86::XOR16mi, 0 },
260 { X86::XOR16ri8, X86::XOR16mi8, 0 },
261 { X86::XOR16rr, X86::XOR16mr, 0 },
262 { X86::XOR32ri, X86::XOR32mi, 0 },
263 { X86::XOR32ri8, X86::XOR32mi8, 0 },
264 { X86::XOR32rr, X86::XOR32mr, 0 },
265 { X86::XOR64ri32, X86::XOR64mi32, 0 },
266 { X86::XOR64ri8, X86::XOR64mi8, 0 },
267 { X86::XOR64rr, X86::XOR64mr, 0 },
268 { X86::XOR8ri, X86::XOR8mi, 0 },
269 { X86::XOR8rr, X86::XOR8mr, 0 }
272 for (unsigned i = 0, e = array_lengthof(MemoryFoldTable2Addr); i != e; ++i) {
273 unsigned RegOp = MemoryFoldTable2Addr[i].RegOp;
274 unsigned MemOp = MemoryFoldTable2Addr[i].MemOp;
275 unsigned Flags = MemoryFoldTable2Addr[i].Flags;
276 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
278 // Index 0, folded load and store, no alignment requirement.
279 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
282 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
283 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
284 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
285 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
286 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
287 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
288 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
289 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
290 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
291 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
292 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
293 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
294 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
295 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
296 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
297 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
298 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
299 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
300 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
301 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
302 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
303 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
304 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
305 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
306 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
307 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
308 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
309 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
310 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
311 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
312 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
313 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
314 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
315 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
316 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
317 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
318 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
319 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
320 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
321 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
322 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
326 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
327 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
328 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
329 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
330 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
331 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
332 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
333 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
334 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
335 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
336 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
337 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
338 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
339 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
340 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
341 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
342 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
343 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
344 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
345 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
346 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
347 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
348 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
349 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
350 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
351 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
352 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
353 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
354 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
355 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
356 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
357 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
358 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
359 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
360 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
362 // AVX 128-bit versions of foldable instructions
363 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
364 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
368 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
369 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
371 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
372 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
373 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
374 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
375 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
377 // AVX 256-bit foldable instructions
378 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
379 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
380 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
381 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
382 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
383 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
385 // AVX-512 foldable instructions
386 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
387 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
388 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
389 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
390 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
391 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
392 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
393 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
394 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
395 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
396 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
398 // AVX-512 foldable instructions (256-bit versions)
399 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
400 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
401 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
402 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
403 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
404 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
405 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
406 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
407 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
408 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
410 // AVX-512 foldable instructions (128-bit versions)
411 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
412 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
413 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
414 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
415 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
416 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
417 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
418 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
419 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
422 // F16C foldable instructions
423 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
424 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
427 for (unsigned i = 0, e = array_lengthof(MemoryFoldTable0); i != e; ++i) {
428 unsigned RegOp = MemoryFoldTable0[i].RegOp;
429 unsigned MemOp = MemoryFoldTable0[i].MemOp;
430 unsigned Flags = MemoryFoldTable0[i].Flags;
431 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
432 RegOp, MemOp, TB_INDEX_0 | Flags);
435 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
436 { X86::BSF16rr, X86::BSF16rm, 0 },
437 { X86::BSF32rr, X86::BSF32rm, 0 },
438 { X86::BSF64rr, X86::BSF64rm, 0 },
439 { X86::BSR16rr, X86::BSR16rm, 0 },
440 { X86::BSR32rr, X86::BSR32rm, 0 },
441 { X86::BSR64rr, X86::BSR64rm, 0 },
442 { X86::CMP16rr, X86::CMP16rm, 0 },
443 { X86::CMP32rr, X86::CMP32rm, 0 },
444 { X86::CMP64rr, X86::CMP64rm, 0 },
445 { X86::CMP8rr, X86::CMP8rm, 0 },
446 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
447 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
448 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
449 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
450 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
451 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
452 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
453 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
454 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
455 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
456 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
457 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
458 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
459 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
460 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
461 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
462 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
463 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
464 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
465 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
466 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
467 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
468 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
469 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
470 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
471 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
472 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
473 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
474 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
475 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
476 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
477 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
478 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
479 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
480 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
481 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
482 { X86::MOV16rr, X86::MOV16rm, 0 },
483 { X86::MOV32rr, X86::MOV32rm, 0 },
484 { X86::MOV64rr, X86::MOV64rm, 0 },
485 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
486 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
487 { X86::MOV8rr, X86::MOV8rm, 0 },
488 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
489 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
490 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
491 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
492 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
493 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
494 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
495 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
496 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
497 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
498 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
499 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
500 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
501 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
502 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
503 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
504 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
505 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
506 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
507 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
508 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
509 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
510 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
511 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
512 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
513 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
514 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
515 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
516 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
517 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
518 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
519 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
520 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
521 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
522 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
523 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
524 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
525 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
526 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
527 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
528 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
529 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
530 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
531 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
532 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
533 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
534 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
535 { X86::RCPSSr, X86::RCPSSm, 0 },
536 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
537 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
538 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
539 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
540 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
541 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
542 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
543 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
544 { X86::SQRTSDr, X86::SQRTSDm, 0 },
545 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
546 { X86::SQRTSSr, X86::SQRTSSm, 0 },
547 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
548 { X86::TEST16rr, X86::TEST16rm, 0 },
549 { X86::TEST32rr, X86::TEST32rm, 0 },
550 { X86::TEST64rr, X86::TEST64rm, 0 },
551 { X86::TEST8rr, X86::TEST8rm, 0 },
552 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
553 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
554 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
556 // MMX version of foldable instructions
557 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
558 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
559 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
560 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
561 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
562 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
563 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
564 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
565 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
566 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
568 // 3DNow! version of foldable instructions
569 { X86::PF2IDrr, X86::PF2IDrm, 0 },
570 { X86::PF2IWrr, X86::PF2IWrm, 0 },
571 { X86::PFRCPrr, X86::PFRCPrm, 0 },
572 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
573 { X86::PI2FDrr, X86::PI2FDrm, 0 },
574 { X86::PI2FWrr, X86::PI2FWrm, 0 },
575 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
577 // AVX 128-bit versions of foldable instructions
578 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
579 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
580 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
581 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
582 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
583 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
584 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
585 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
586 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
587 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
588 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
589 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
590 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
591 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
592 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
593 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
594 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
595 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
596 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
597 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
598 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
599 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
600 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
601 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
602 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
603 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
604 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
605 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
606 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
607 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
608 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
609 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
610 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
611 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
612 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
613 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
614 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
615 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
616 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
617 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
618 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
619 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
620 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
621 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
622 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
623 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
624 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
625 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
626 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
627 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
628 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
629 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
630 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
631 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
632 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
633 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
634 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
635 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
636 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
637 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
638 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
639 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
640 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
641 { X86::VPTESTrr, X86::VPTESTrm, 0 },
642 { X86::VRCPPSr, X86::VRCPPSm, 0 },
643 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
644 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
645 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
646 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
647 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
648 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
649 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
650 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
651 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
653 // AVX 256-bit foldable instructions
654 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
655 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
656 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
657 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
658 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
659 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
660 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
661 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
662 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
663 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
664 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
665 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
666 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
667 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
668 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
669 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
670 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
671 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
672 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
673 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
674 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
675 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
676 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
677 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
678 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
679 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
680 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
682 // AVX2 foldable instructions
684 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
685 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
686 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
687 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
688 // so they don't need an equivalent limitation.
689 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
690 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
691 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
692 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
693 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
694 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
695 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
696 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
697 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
698 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
699 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
700 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
701 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
702 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
703 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
704 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
705 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
706 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
707 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
708 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
709 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
710 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
711 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
712 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
713 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
714 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
715 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
716 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
717 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
718 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
719 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
721 // XOP foldable instructions
722 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
723 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
724 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
725 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
726 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
727 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
728 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
729 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
730 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
731 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
732 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
733 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
734 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
735 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
736 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
737 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
738 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
739 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
740 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
741 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
742 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
743 { X86::VPROTBri, X86::VPROTBmi, 0 },
744 { X86::VPROTBrr, X86::VPROTBmr, 0 },
745 { X86::VPROTDri, X86::VPROTDmi, 0 },
746 { X86::VPROTDrr, X86::VPROTDmr, 0 },
747 { X86::VPROTQri, X86::VPROTQmi, 0 },
748 { X86::VPROTQrr, X86::VPROTQmr, 0 },
749 { X86::VPROTWri, X86::VPROTWmi, 0 },
750 { X86::VPROTWrr, X86::VPROTWmr, 0 },
751 { X86::VPSHABrr, X86::VPSHABmr, 0 },
752 { X86::VPSHADrr, X86::VPSHADmr, 0 },
753 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
754 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
755 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
756 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
757 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
758 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
760 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
761 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
762 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
763 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
764 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
765 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
766 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
767 { X86::BLCI32rr, X86::BLCI32rm, 0 },
768 { X86::BLCI64rr, X86::BLCI64rm, 0 },
769 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
770 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
771 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
772 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
773 { X86::BLCS32rr, X86::BLCS32rm, 0 },
774 { X86::BLCS64rr, X86::BLCS64rm, 0 },
775 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
776 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
777 { X86::BLSI32rr, X86::BLSI32rm, 0 },
778 { X86::BLSI64rr, X86::BLSI64rm, 0 },
779 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
780 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
781 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
782 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
783 { X86::BLSR32rr, X86::BLSR32rm, 0 },
784 { X86::BLSR64rr, X86::BLSR64rm, 0 },
785 { X86::BZHI32rr, X86::BZHI32rm, 0 },
786 { X86::BZHI64rr, X86::BZHI64rm, 0 },
787 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
788 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
789 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
790 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
791 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
792 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
793 { X86::RORX32ri, X86::RORX32mi, 0 },
794 { X86::RORX64ri, X86::RORX64mi, 0 },
795 { X86::SARX32rr, X86::SARX32rm, 0 },
796 { X86::SARX64rr, X86::SARX64rm, 0 },
797 { X86::SHRX32rr, X86::SHRX32rm, 0 },
798 { X86::SHRX64rr, X86::SHRX64rm, 0 },
799 { X86::SHLX32rr, X86::SHLX32rm, 0 },
800 { X86::SHLX64rr, X86::SHLX64rm, 0 },
801 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
802 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
803 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
804 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
805 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
806 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
807 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
809 // AVX-512 foldable instructions
810 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
811 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
812 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
813 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
814 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
815 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
816 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
817 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
818 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
819 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
820 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
821 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
822 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
823 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
824 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
825 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
827 // AVX-512 foldable instructions (256-bit versions)
828 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
829 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
830 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
831 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
832 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
833 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
834 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
835 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
836 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
837 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
838 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
839 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
841 // AVX-512 foldable instructions (256-bit versions)
842 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
843 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
844 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
845 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
846 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
847 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
848 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
849 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
850 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
851 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
852 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
854 // F16C foldable instructions
855 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
856 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
858 // AES foldable instructions
859 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
860 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
861 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
862 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
865 for (unsigned i = 0, e = array_lengthof(MemoryFoldTable1); i != e; ++i) {
866 unsigned RegOp = MemoryFoldTable1[i].RegOp;
867 unsigned MemOp = MemoryFoldTable1[i].MemOp;
868 unsigned Flags = MemoryFoldTable1[i].Flags;
869 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
871 // Index 1, folded load
872 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
875 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
876 { X86::ADC32rr, X86::ADC32rm, 0 },
877 { X86::ADC64rr, X86::ADC64rm, 0 },
878 { X86::ADD16rr, X86::ADD16rm, 0 },
879 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
880 { X86::ADD32rr, X86::ADD32rm, 0 },
881 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
882 { X86::ADD64rr, X86::ADD64rm, 0 },
883 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
884 { X86::ADD8rr, X86::ADD8rm, 0 },
885 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
886 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
887 { X86::ADDSDrr, X86::ADDSDrm, 0 },
888 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
889 { X86::ADDSSrr, X86::ADDSSrm, 0 },
890 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
891 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
892 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
893 { X86::AND16rr, X86::AND16rm, 0 },
894 { X86::AND32rr, X86::AND32rm, 0 },
895 { X86::AND64rr, X86::AND64rm, 0 },
896 { X86::AND8rr, X86::AND8rm, 0 },
897 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
898 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
899 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
900 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
901 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
902 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
903 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
904 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
905 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
906 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
907 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
908 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
909 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
910 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
911 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
912 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
913 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
914 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
915 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
916 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
917 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
918 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
919 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
920 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
921 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
922 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
923 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
924 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
925 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
926 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
927 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
928 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
929 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
930 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
931 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
932 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
933 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
934 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
935 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
936 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
937 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
938 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
939 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
940 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
941 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
942 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
943 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
944 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
945 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
946 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
947 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
948 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
949 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
950 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
951 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
952 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
953 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
954 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
955 { X86::CMPSDrr, X86::CMPSDrm, 0 },
956 { X86::CMPSSrr, X86::CMPSSrm, 0 },
957 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
958 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
959 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
960 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
961 { X86::DIVSDrr, X86::DIVSDrm, 0 },
962 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
963 { X86::DIVSSrr, X86::DIVSSrm, 0 },
964 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
965 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
966 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
968 // FIXME: We should not be folding Fs* scalar loads into vector
969 // instructions because the vector instructions require vector-sized
970 // loads. Lowering should create vector-sized instructions (the Fv*
971 // variants below) to allow load folding.
972 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
973 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
974 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
975 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
976 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
977 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
978 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
979 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
981 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
982 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
983 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
984 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
985 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
986 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
987 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
988 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
989 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
990 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
991 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
992 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
993 { X86::IMUL16rr, X86::IMUL16rm, 0 },
994 { X86::IMUL32rr, X86::IMUL32rm, 0 },
995 { X86::IMUL64rr, X86::IMUL64rm, 0 },
996 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
997 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
998 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
999 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
1000 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
1001 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
1002 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
1003 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
1004 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
1005 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
1006 { X86::MAXSDrr, X86::MAXSDrm, 0 },
1007 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
1008 { X86::MAXSSrr, X86::MAXSSrm, 0 },
1009 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
1010 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
1011 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
1012 { X86::MINSDrr, X86::MINSDrm, 0 },
1013 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
1014 { X86::MINSSrr, X86::MINSSrm, 0 },
1015 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
1016 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
1017 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1018 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1019 { X86::MULSDrr, X86::MULSDrm, 0 },
1020 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
1021 { X86::MULSSrr, X86::MULSSrm, 0 },
1022 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
1023 { X86::OR16rr, X86::OR16rm, 0 },
1024 { X86::OR32rr, X86::OR32rm, 0 },
1025 { X86::OR64rr, X86::OR64rm, 0 },
1026 { X86::OR8rr, X86::OR8rm, 0 },
1027 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1028 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1029 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1030 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
1031 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
1032 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1033 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1034 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1035 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1036 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1037 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
1038 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1039 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
1040 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
1041 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
1042 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1043 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1044 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1045 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
1046 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
1047 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
1048 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
1049 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1050 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
1051 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
1052 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1053 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1054 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
1055 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
1056 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
1057 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1058 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
1059 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
1060 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
1061 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
1062 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
1063 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1064 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1065 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1066 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
1067 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
1068 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1069 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1070 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1071 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1072 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
1073 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1074 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1075 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1076 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1077 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1078 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1079 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1080 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
1081 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
1082 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
1083 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1084 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1085 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1086 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1087 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1088 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1089 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
1090 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
1091 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
1092 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
1093 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
1094 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1095 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1096 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1097 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1098 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1099 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1100 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1101 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1102 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1103 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
1104 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
1105 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1106 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
1107 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1108 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
1109 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1110 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1111 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1112 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1113 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1114 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1115 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1116 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1117 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1118 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
1119 { X86::SBB32rr, X86::SBB32rm, 0 },
1120 { X86::SBB64rr, X86::SBB64rm, 0 },
1121 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1122 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1123 { X86::SUB16rr, X86::SUB16rm, 0 },
1124 { X86::SUB32rr, X86::SUB32rm, 0 },
1125 { X86::SUB64rr, X86::SUB64rm, 0 },
1126 { X86::SUB8rr, X86::SUB8rm, 0 },
1127 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1128 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1129 { X86::SUBSDrr, X86::SUBSDrm, 0 },
1130 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
1131 { X86::SUBSSrr, X86::SUBSSrm, 0 },
1132 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
1133 // FIXME: TEST*rr -> swapped operand of TEST*mr.
1134 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1135 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1136 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1137 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1138 { X86::XOR16rr, X86::XOR16rm, 0 },
1139 { X86::XOR32rr, X86::XOR32rm, 0 },
1140 { X86::XOR64rr, X86::XOR64rm, 0 },
1141 { X86::XOR8rr, X86::XOR8rm, 0 },
1142 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
1143 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
1145 // MMX version of foldable instructions
1146 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1147 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1148 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1149 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1150 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1151 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1152 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1153 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1154 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1155 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1156 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1157 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1158 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1159 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1160 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1161 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1162 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1163 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1164 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1165 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1166 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1167 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1168 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1169 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1170 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1171 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1172 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1173 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1174 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1175 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1176 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1177 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1178 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1179 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1180 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1181 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1182 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1183 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1184 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1185 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1186 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1187 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1188 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1189 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1190 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1191 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1192 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1193 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1194 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1195 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1196 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1197 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1198 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1199 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1200 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1201 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1202 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1203 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1204 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1205 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1206 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1207 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1208 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1209 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1210 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1211 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1212 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1213 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1214 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1215 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1217 // 3DNow! version of foldable instructions
1218 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1219 { X86::PFACCrr, X86::PFACCrm, 0 },
1220 { X86::PFADDrr, X86::PFADDrm, 0 },
1221 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1222 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1223 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1224 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1225 { X86::PFMINrr, X86::PFMINrm, 0 },
1226 { X86::PFMULrr, X86::PFMULrm, 0 },
1227 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1228 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1229 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1230 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1231 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1232 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1233 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1234 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1236 // AVX 128-bit versions of foldable instructions
1237 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1238 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1239 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1240 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1241 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1242 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1243 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1244 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1245 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1246 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
1247 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1248 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
1249 { X86::VRCPSSr, X86::VRCPSSm, 0 },
1250 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
1251 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1252 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
1253 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1254 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
1255 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
1256 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
1257 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1258 { X86::VADDPSrr, X86::VADDPSrm, 0 },
1259 { X86::VADDSDrr, X86::VADDSDrm, 0 },
1260 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
1261 { X86::VADDSSrr, X86::VADDSSrm, 0 },
1262 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
1263 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1264 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1265 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1266 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1267 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1268 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1269 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1270 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1271 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1272 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1273 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1274 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
1275 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1276 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
1277 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1278 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
1279 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
1280 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
1281 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
1282 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1283 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1284 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
1285 // Do not fold VFs* loads because there are no scalar load variants for
1286 // these instructions. When folded, the load is required to be 128-bits, so
1287 // the load size would not match.
1288 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1289 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1290 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1291 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1292 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1293 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1294 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1295 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
1296 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1297 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1298 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1299 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
1300 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1301 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
1302 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
1303 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
1304 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
1305 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
1306 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
1307 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
1308 { X86::VMINPDrr, X86::VMINPDrm, 0 },
1309 { X86::VMINPSrr, X86::VMINPSrm, 0 },
1310 { X86::VMINSDrr, X86::VMINSDrm, 0 },
1311 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
1312 { X86::VMINSSrr, X86::VMINSSrm, 0 },
1313 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
1314 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1315 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1316 { X86::VMULPSrr, X86::VMULPSrm, 0 },
1317 { X86::VMULSDrr, X86::VMULSDrm, 0 },
1318 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
1319 { X86::VMULSSrr, X86::VMULSSrm, 0 },
1320 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
1321 { X86::VORPDrr, X86::VORPDrm, 0 },
1322 { X86::VORPSrr, X86::VORPSrm, 0 },
1323 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1324 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1325 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1326 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1327 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1328 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1329 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1330 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1331 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1332 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1333 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1334 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1335 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1336 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1337 { X86::VPANDrr, X86::VPANDrm, 0 },
1338 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1339 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
1340 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
1341 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
1342 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
1343 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1344 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1345 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1346 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1347 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1348 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1349 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1350 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1351 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1352 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1353 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1354 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1355 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1356 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1357 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1358 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
1359 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1360 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1361 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
1362 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1363 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1364 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1365 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1366 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1367 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1368 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1369 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1370 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1371 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1372 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1373 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1374 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1375 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1376 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1377 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1378 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1379 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1380 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1381 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1382 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1383 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1384 { X86::VPORrr, X86::VPORrm, 0 },
1385 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1386 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1387 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1388 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1389 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1390 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1391 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1392 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1393 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1394 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1395 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1396 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1397 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1398 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1399 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1400 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
1401 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1402 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1403 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1404 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
1405 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1406 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1407 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1408 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1409 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1410 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1411 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1412 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1413 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1414 { X86::VPXORrr, X86::VPXORrm, 0 },
1415 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1416 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1417 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1418 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1419 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1420 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
1421 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1422 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
1423 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1424 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1425 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1426 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1427 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1428 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1430 // AVX 256-bit foldable instructions
1431 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1432 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1433 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1434 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1435 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1436 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1437 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1438 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1439 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1440 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1441 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1442 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1443 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1444 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1445 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1446 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1447 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
1448 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1449 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1450 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1451 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1452 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1453 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1454 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1455 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1456 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1457 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1458 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1459 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1460 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1461 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1462 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1463 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1464 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1465 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1466 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1467 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1468 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1469 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1470 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1471 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1472 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1473 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1475 // AVX2 foldable instructions
1476 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1477 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1478 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1479 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1480 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1481 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1482 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1483 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1484 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1485 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1486 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1487 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1488 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1489 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1490 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1491 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1492 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1493 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1494 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1495 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1496 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
1497 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1498 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1499 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1500 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1501 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1502 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1503 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1504 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1505 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1506 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1507 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1508 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1509 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1510 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1511 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1512 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1513 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1514 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1515 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1516 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1517 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1518 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1519 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1520 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1521 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1522 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1523 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1524 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1525 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1526 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1527 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1528 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1529 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1530 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1531 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1532 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1533 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1534 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1535 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1536 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1537 { X86::VPORYrr, X86::VPORYrm, 0 },
1538 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1539 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1540 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1541 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1542 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1543 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1544 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1545 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1546 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1547 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1548 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1549 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1550 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1551 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1552 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1553 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1554 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1555 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1556 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1557 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1558 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1559 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1560 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1561 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1562 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1563 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
1564 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1565 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1566 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1567 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
1568 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1569 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1570 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1571 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1572 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1573 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1574 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1575 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1576 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1577 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1579 // FMA4 foldable patterns
1580 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1581 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
1582 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, 0 },
1583 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, 0 },
1584 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, 0 },
1585 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, 0 },
1586 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1587 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
1588 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, 0 },
1589 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, 0 },
1590 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, 0 },
1591 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, 0 },
1592 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1593 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
1594 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, 0 },
1595 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, 0 },
1596 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, 0 },
1597 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, 0 },
1598 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1599 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
1600 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, 0 },
1601 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, 0 },
1602 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, 0 },
1603 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, 0 },
1604 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, 0 },
1605 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, 0 },
1606 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, 0 },
1607 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, 0 },
1608 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, 0 },
1609 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, 0 },
1610 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, 0 },
1611 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, 0 },
1613 // XOP foldable instructions
1614 { X86::VPCMOVrr, X86::VPCMOVmr, 0 },
1615 { X86::VPCMOVrrY, X86::VPCMOVmrY, 0 },
1616 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1617 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1618 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1619 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1620 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1621 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1622 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1623 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1624 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1625 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1626 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1627 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1628 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1629 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1630 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1631 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1632 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1633 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1634 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1635 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1636 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1637 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1638 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1639 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1640 { X86::VPPERMrr, X86::VPPERMmr, 0 },
1641 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1642 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1643 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1644 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1645 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1646 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1647 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1648 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1649 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1650 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1651 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1652 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1654 // BMI/BMI2 foldable instructions
1655 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1656 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1657 { X86::MULX32rr, X86::MULX32rm, 0 },
1658 { X86::MULX64rr, X86::MULX64rm, 0 },
1659 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1660 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1661 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1662 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1664 // AVX-512 foldable instructions
1665 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1666 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1667 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1668 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1669 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1670 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1671 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1672 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1673 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1674 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1675 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1676 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1677 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1678 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1679 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1680 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1681 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1682 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1683 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1684 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1685 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1686 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1687 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1688 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1689 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1690 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1691 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1692 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1693 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1694 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1695 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1696 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1697 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1698 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1699 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1700 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
1701 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1702 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1703 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1705 // AVX-512{F,VL} foldable instructions
1706 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1707 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1708 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
1710 // AVX-512{F,VL} foldable instructions
1711 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1712 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1713 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1714 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1716 // AES foldable instructions
1717 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1718 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1719 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1720 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
1721 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1722 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1723 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1724 { X86::VAESENCrr, X86::VAESENCrm, 0 },
1726 // SHA foldable instructions
1727 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1728 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1729 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1730 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1731 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1732 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
1733 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
1736 for (unsigned i = 0, e = array_lengthof(MemoryFoldTable2); i != e; ++i) {
1737 unsigned RegOp = MemoryFoldTable2[i].RegOp;
1738 unsigned MemOp = MemoryFoldTable2[i].MemOp;
1739 unsigned Flags = MemoryFoldTable2[i].Flags;
1740 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1742 // Index 2, folded load
1743 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1746 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1747 // FMA foldable instructions
1748 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1749 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1750 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1751 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1752 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1753 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
1755 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1756 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1757 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1758 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1759 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1760 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1761 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1762 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1763 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1764 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1765 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1766 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
1768 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1769 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1770 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1771 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1772 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1773 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
1775 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1776 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1777 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1778 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1779 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1780 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1781 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1782 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1783 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1784 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1785 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1786 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
1788 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1789 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1790 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1791 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1792 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1793 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
1795 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1796 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1797 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1798 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1799 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1800 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1801 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1802 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1803 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1804 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1805 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1806 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
1808 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1809 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1810 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1811 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1812 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1813 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
1815 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1816 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1817 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1818 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1819 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1820 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1821 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1822 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1823 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1824 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1825 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1826 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
1828 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1829 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1830 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1831 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1832 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1833 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1834 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1835 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1836 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1837 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1838 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1839 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
1841 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1842 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1843 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1844 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1845 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1846 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1847 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1848 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1849 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1850 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1851 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1852 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
1854 // FMA4 foldable patterns
1855 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1856 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
1857 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1858 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1859 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1860 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
1861 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1862 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
1863 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1864 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1865 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1866 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
1867 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1868 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
1869 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1870 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1871 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1872 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
1873 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1874 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
1875 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1876 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1877 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1878 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1879 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1880 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1881 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1882 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1883 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1884 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1885 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1886 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
1888 // XOP foldable instructions
1889 { X86::VPCMOVrr, X86::VPCMOVrm, 0 },
1890 { X86::VPCMOVrrY, X86::VPCMOVrmY, 0 },
1891 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1892 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1893 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1894 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
1895 { X86::VPPERMrr, X86::VPPERMrm, 0 },
1897 // AVX-512 VPERMI instructions with 3 source operands.
1898 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1899 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1900 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1901 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
1902 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1903 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1904 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
1905 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1906 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1907 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1908 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1909 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
1910 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1911 // AVX-512 arithmetic instructions
1912 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1913 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1914 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1915 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1916 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1917 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1918 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1919 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1920 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1921 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1922 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1923 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1924 // AVX-512{F,VL} arithmetic instructions 256-bit
1925 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1926 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1927 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1928 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1929 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1930 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1931 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1932 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1933 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1934 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1935 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1936 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1937 // AVX-512{F,VL} arithmetic instructions 128-bit
1938 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1939 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1940 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1941 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1942 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1943 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1944 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1945 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1946 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1947 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1948 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1949 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
1952 for (unsigned i = 0, e = array_lengthof(MemoryFoldTable3); i != e; ++i) {
1953 unsigned RegOp = MemoryFoldTable3[i].RegOp;
1954 unsigned MemOp = MemoryFoldTable3[i].MemOp;
1955 unsigned Flags = MemoryFoldTable3[i].Flags;
1956 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1958 // Index 3, folded load
1959 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1962 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1963 // AVX-512 foldable instructions
1964 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1965 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1966 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1967 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1968 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1969 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1970 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1971 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1972 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1973 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1974 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1975 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1976 // AVX-512{F,VL} foldable instructions 256-bit
1977 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1978 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1979 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1980 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1981 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1982 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1983 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1984 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1985 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
1986 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
1987 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
1988 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
1989 // AVX-512{F,VL} foldable instructions 128-bit
1990 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
1991 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
1992 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
1993 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
1994 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
1995 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
1996 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
1997 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
1998 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
1999 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2000 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2001 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
2004 for (unsigned i = 0, e = array_lengthof(MemoryFoldTable4); i != e; ++i) {
2005 unsigned RegOp = MemoryFoldTable4[i].RegOp;
2006 unsigned MemOp = MemoryFoldTable4[i].MemOp;
2007 unsigned Flags = MemoryFoldTable4[i].Flags;
2008 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2010 // Index 4, folded load
2011 Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2016 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2017 MemOp2RegOpTableType &M2RTable,
2018 unsigned RegOp, unsigned MemOp, unsigned Flags) {
2019 if ((Flags & TB_NO_FORWARD) == 0) {
2020 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2021 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2023 if ((Flags & TB_NO_REVERSE) == 0) {
2024 assert(!M2RTable.count(MemOp) &&
2025 "Duplicated entries in unfolding maps?");
2026 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2031 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2032 unsigned &SrcReg, unsigned &DstReg,
2033 unsigned &SubIdx) const {
2034 switch (MI.getOpcode()) {
2036 case X86::MOVSX16rr8:
2037 case X86::MOVZX16rr8:
2038 case X86::MOVSX32rr8:
2039 case X86::MOVZX32rr8:
2040 case X86::MOVSX64rr8:
2041 if (!Subtarget.is64Bit())
2042 // It's not always legal to reference the low 8-bit of the larger
2043 // register in 32-bit mode.
2045 case X86::MOVSX32rr16:
2046 case X86::MOVZX32rr16:
2047 case X86::MOVSX64rr16:
2048 case X86::MOVSX64rr32: {
2049 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2052 SrcReg = MI.getOperand(1).getReg();
2053 DstReg = MI.getOperand(0).getReg();
2054 switch (MI.getOpcode()) {
2055 default: llvm_unreachable("Unreachable!");
2056 case X86::MOVSX16rr8:
2057 case X86::MOVZX16rr8:
2058 case X86::MOVSX32rr8:
2059 case X86::MOVZX32rr8:
2060 case X86::MOVSX64rr8:
2061 SubIdx = X86::sub_8bit;
2063 case X86::MOVSX32rr16:
2064 case X86::MOVZX32rr16:
2065 case X86::MOVSX64rr16:
2066 SubIdx = X86::sub_16bit;
2068 case X86::MOVSX64rr32:
2069 SubIdx = X86::sub_32bit;
2078 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2079 const MachineFunction *MF = MI->getParent()->getParent();
2080 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2082 if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2083 MI->getOpcode() == getCallFrameDestroyOpcode()) {
2084 unsigned StackAlign = TFI->getStackAlignment();
2085 int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2088 SPAdj -= MI->getOperand(1).getImm();
2090 if (MI->getOpcode() == getCallFrameSetupOpcode())
2096 // To know whether a call adjusts the stack, we need information
2097 // that is bound to the following ADJCALLSTACKUP pseudo.
2098 // Look for the next ADJCALLSTACKUP that follows the call.
2100 const MachineBasicBlock* MBB = MI->getParent();
2101 auto I = ++MachineBasicBlock::const_iterator(MI);
2102 for (auto E = MBB->end(); I != E; ++I) {
2103 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2108 // If we could not find a frame destroy opcode, then it has already
2109 // been simplified, so we don't care.
2110 if (I->getOpcode() != getCallFrameDestroyOpcode())
2113 return -(I->getOperand(1).getImm());
2116 // Currently handle only PUSHes we can reasonably expect to see
2117 // in call sequences
2118 switch (MI->getOpcode()) {
2123 case X86::PUSH32rmm:
2124 case X86::PUSH32rmr:
2130 /// Return true and the FrameIndex if the specified
2131 /// operand and follow operands form a reference to the stack frame.
2132 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2133 int &FrameIndex) const {
2134 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2135 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2136 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2137 MI->getOperand(Op+X86::AddrDisp).isImm() &&
2138 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2139 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2140 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2141 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2147 static bool isFrameLoadOpcode(int Opcode) {
2163 case X86::VMOVAPSrm:
2164 case X86::VMOVAPDrm:
2165 case X86::VMOVDQArm:
2166 case X86::VMOVUPSYrm:
2167 case X86::VMOVAPSYrm:
2168 case X86::VMOVUPDYrm:
2169 case X86::VMOVAPDYrm:
2170 case X86::VMOVDQUYrm:
2171 case X86::VMOVDQAYrm:
2172 case X86::MMX_MOVD64rm:
2173 case X86::MMX_MOVQ64rm:
2174 case X86::VMOVAPSZrm:
2175 case X86::VMOVUPSZrm:
2180 static bool isFrameStoreOpcode(int Opcode) {
2187 case X86::ST_FpP64m:
2195 case X86::VMOVAPSmr:
2196 case X86::VMOVAPDmr:
2197 case X86::VMOVDQAmr:
2198 case X86::VMOVUPSYmr:
2199 case X86::VMOVAPSYmr:
2200 case X86::VMOVUPDYmr:
2201 case X86::VMOVAPDYmr:
2202 case X86::VMOVDQUYmr:
2203 case X86::VMOVDQAYmr:
2204 case X86::VMOVUPSZmr:
2205 case X86::VMOVAPSZmr:
2206 case X86::MMX_MOVD64mr:
2207 case X86::MMX_MOVQ64mr:
2208 case X86::MMX_MOVNTQmr:
2214 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2215 int &FrameIndex) const {
2216 if (isFrameLoadOpcode(MI->getOpcode()))
2217 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2218 return MI->getOperand(0).getReg();
2222 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2223 int &FrameIndex) const {
2224 if (isFrameLoadOpcode(MI->getOpcode())) {
2226 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2228 // Check for post-frame index elimination operations
2229 const MachineMemOperand *Dummy;
2230 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2235 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2236 int &FrameIndex) const {
2237 if (isFrameStoreOpcode(MI->getOpcode()))
2238 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2239 isFrameOperand(MI, 0, FrameIndex))
2240 return MI->getOperand(X86::AddrNumOperands).getReg();
2244 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2245 int &FrameIndex) const {
2246 if (isFrameStoreOpcode(MI->getOpcode())) {
2248 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2250 // Check for post-frame index elimination operations
2251 const MachineMemOperand *Dummy;
2252 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2257 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2258 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2259 // Don't waste compile time scanning use-def chains of physregs.
2260 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2262 bool isPICBase = false;
2263 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2264 E = MRI.def_instr_end(); I != E; ++I) {
2265 MachineInstr *DefMI = &*I;
2266 if (DefMI->getOpcode() != X86::MOVPC32r)
2268 assert(!isPICBase && "More than one PIC base?");
2275 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2276 AliasAnalysis *AA) const {
2277 switch (MI->getOpcode()) {
2293 case X86::VMOVAPSrm:
2294 case X86::VMOVUPSrm:
2295 case X86::VMOVAPDrm:
2296 case X86::VMOVDQArm:
2297 case X86::VMOVDQUrm:
2298 case X86::VMOVAPSYrm:
2299 case X86::VMOVUPSYrm:
2300 case X86::VMOVAPDYrm:
2301 case X86::VMOVDQAYrm:
2302 case X86::VMOVDQUYrm:
2303 case X86::MMX_MOVD64rm:
2304 case X86::MMX_MOVQ64rm:
2305 case X86::FsVMOVAPSrm:
2306 case X86::FsVMOVAPDrm:
2307 case X86::FsMOVAPSrm:
2308 case X86::FsMOVAPDrm: {
2309 // Loads from constant pools are trivially rematerializable.
2310 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2311 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2312 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2313 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2314 MI->isInvariantLoad(AA)) {
2315 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2316 if (BaseReg == 0 || BaseReg == X86::RIP)
2318 // Allow re-materialization of PIC load.
2319 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2321 const MachineFunction &MF = *MI->getParent()->getParent();
2322 const MachineRegisterInfo &MRI = MF.getRegInfo();
2323 return regIsPICBase(BaseReg, MRI);
2330 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2331 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2332 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2333 !MI->getOperand(1+X86::AddrDisp).isReg()) {
2334 // lea fi#, lea GV, etc. are all rematerializable.
2335 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2337 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2340 // Allow re-materialization of lea PICBase + x.
2341 const MachineFunction &MF = *MI->getParent()->getParent();
2342 const MachineRegisterInfo &MRI = MF.getRegInfo();
2343 return regIsPICBase(BaseReg, MRI);
2349 // All other instructions marked M_REMATERIALIZABLE are always trivially
2350 // rematerializable.
2354 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2355 MachineBasicBlock::iterator I) const {
2356 MachineBasicBlock::iterator E = MBB.end();
2358 // For compile time consideration, if we are not able to determine the
2359 // safety after visiting 4 instructions in each direction, we will assume
2361 MachineBasicBlock::iterator Iter = I;
2362 for (unsigned i = 0; Iter != E && i < 4; ++i) {
2363 bool SeenDef = false;
2364 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2365 MachineOperand &MO = Iter->getOperand(j);
2366 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2370 if (MO.getReg() == X86::EFLAGS) {
2378 // This instruction defines EFLAGS, no need to look any further.
2381 // Skip over DBG_VALUE.
2382 while (Iter != E && Iter->isDebugValue())
2386 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2389 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2390 SE = MBB.succ_end(); SI != SE; ++SI)
2391 if ((*SI)->isLiveIn(X86::EFLAGS))
2396 MachineBasicBlock::iterator B = MBB.begin();
2398 for (unsigned i = 0; i < 4; ++i) {
2399 // If we make it to the beginning of the block, it's safe to clobber
2400 // EFLAGS iff EFLAGS is not live-in.
2402 return !MBB.isLiveIn(X86::EFLAGS);
2405 // Skip over DBG_VALUE.
2406 while (Iter != B && Iter->isDebugValue())
2409 bool SawKill = false;
2410 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2411 MachineOperand &MO = Iter->getOperand(j);
2412 // A register mask may clobber EFLAGS, but we should still look for a
2414 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2416 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2417 if (MO.isDef()) return MO.isDead();
2418 if (MO.isKill()) SawKill = true;
2423 // This instruction kills EFLAGS and doesn't redefine it, so
2424 // there's no need to look further.
2428 // Conservative answer.
2432 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2433 MachineBasicBlock::iterator I,
2434 unsigned DestReg, unsigned SubIdx,
2435 const MachineInstr *Orig,
2436 const TargetRegisterInfo &TRI) const {
2437 // MOV32r0 is implemented with a xor which clobbers condition code.
2438 // Re-materialize it as movri instructions to avoid side effects.
2439 unsigned Opc = Orig->getOpcode();
2440 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2441 DebugLoc DL = Orig->getDebugLoc();
2442 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2445 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2449 MachineInstr *NewMI = std::prev(I);
2450 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2453 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2454 static bool hasLiveCondCodeDef(MachineInstr *MI) {
2455 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2456 MachineOperand &MO = MI->getOperand(i);
2457 if (MO.isReg() && MO.isDef() &&
2458 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2465 /// Check whether the shift count for a machine operand is non-zero.
2466 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2467 unsigned ShiftAmtOperandIdx) {
2468 // The shift count is six bits with the REX.W prefix and five bits without.
2469 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2470 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2471 return Imm & ShiftCountMask;
2474 /// Check whether the given shift count is appropriate
2475 /// can be represented by a LEA instruction.
2476 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2477 // Left shift instructions can be transformed into load-effective-address
2478 // instructions if we can encode them appropriately.
2479 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2480 // The SIB.scale field is two bits wide which means that we can encode any
2481 // shift amount less than 4.
2482 return ShAmt < 4 && ShAmt > 0;
2485 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2486 unsigned Opc, bool AllowSP,
2487 unsigned &NewSrc, bool &isKill, bool &isUndef,
2488 MachineOperand &ImplicitOp) const {
2489 MachineFunction &MF = *MI->getParent()->getParent();
2490 const TargetRegisterClass *RC;
2492 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2494 RC = Opc != X86::LEA32r ?
2495 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2497 unsigned SrcReg = Src.getReg();
2499 // For both LEA64 and LEA32 the register already has essentially the right
2500 // type (32-bit or 64-bit) we may just need to forbid SP.
2501 if (Opc != X86::LEA64_32r) {
2503 isKill = Src.isKill();
2504 isUndef = Src.isUndef();
2506 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2507 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2513 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2514 // another we need to add 64-bit registers to the final MI.
2515 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2517 ImplicitOp.setImplicit();
2519 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2520 MachineBasicBlock::LivenessQueryResult LQR =
2521 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2524 case MachineBasicBlock::LQR_Unknown:
2525 // We can't give sane liveness flags to the instruction, abandon LEA
2528 case MachineBasicBlock::LQR_Live:
2529 isKill = MI->killsRegister(SrcReg);
2533 // The physreg itself is dead, so we have to use it as an <undef>.
2539 // Virtual register of the wrong class, we have to create a temporary 64-bit
2540 // vreg to feed into the LEA.
2541 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2542 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2543 get(TargetOpcode::COPY))
2544 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2547 // Which is obviously going to be dead after we're done with it.
2552 // We've set all the parameters without issue.
2556 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2557 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2558 /// truncating back down to a 16-bit subregister.
2560 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2561 MachineFunction::iterator &MFI,
2562 MachineBasicBlock::iterator &MBBI,
2563 LiveVariables *LV) const {
2564 MachineInstr *MI = MBBI;
2565 unsigned Dest = MI->getOperand(0).getReg();
2566 unsigned Src = MI->getOperand(1).getReg();
2567 bool isDead = MI->getOperand(0).isDead();
2568 bool isKill = MI->getOperand(1).isKill();
2570 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2571 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2572 unsigned Opc, leaInReg;
2573 if (Subtarget.is64Bit()) {
2574 Opc = X86::LEA64_32r;
2575 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2578 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2581 // Build and insert into an implicit UNDEF value. This is OK because
2582 // well be shifting and then extracting the lower 16-bits.
2583 // This has the potential to cause partial register stall. e.g.
2584 // movw (%rbp,%rcx,2), %dx
2585 // leal -65(%rdx), %esi
2586 // But testing has shown this *does* help performance in 64-bit mode (at
2587 // least on modern x86 machines).
2588 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2589 MachineInstr *InsMI =
2590 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2591 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2592 .addReg(Src, getKillRegState(isKill));
2594 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2595 get(Opc), leaOutReg);
2597 default: llvm_unreachable("Unreachable!");
2598 case X86::SHL16ri: {
2599 unsigned ShAmt = MI->getOperand(2).getImm();
2600 MIB.addReg(0).addImm(1 << ShAmt)
2601 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2605 addRegOffset(MIB, leaInReg, true, 1);
2608 addRegOffset(MIB, leaInReg, true, -1);
2612 case X86::ADD16ri_DB:
2613 case X86::ADD16ri8_DB:
2614 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2617 case X86::ADD16rr_DB: {
2618 unsigned Src2 = MI->getOperand(2).getReg();
2619 bool isKill2 = MI->getOperand(2).isKill();
2620 unsigned leaInReg2 = 0;
2621 MachineInstr *InsMI2 = nullptr;
2623 // ADD16rr %reg1028<kill>, %reg1028
2624 // just a single insert_subreg.
2625 addRegReg(MIB, leaInReg, true, leaInReg, false);
2627 if (Subtarget.is64Bit())
2628 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2630 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2631 // Build and insert into an implicit UNDEF value. This is OK because
2632 // well be shifting and then extracting the lower 16-bits.
2633 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2635 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2636 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2637 .addReg(Src2, getKillRegState(isKill2));
2638 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2640 if (LV && isKill2 && InsMI2)
2641 LV->replaceKillInstruction(Src2, MI, InsMI2);
2646 MachineInstr *NewMI = MIB;
2647 MachineInstr *ExtMI =
2648 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2649 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2650 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2653 // Update live variables
2654 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2655 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2657 LV->replaceKillInstruction(Src, MI, InsMI);
2659 LV->replaceKillInstruction(Dest, MI, ExtMI);
2665 /// This method must be implemented by targets that
2666 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2667 /// may be able to convert a two-address instruction into a true
2668 /// three-address instruction on demand. This allows the X86 target (for
2669 /// example) to convert ADD and SHL instructions into LEA instructions if they
2670 /// would require register copies due to two-addressness.
2672 /// This method returns a null pointer if the transformation cannot be
2673 /// performed, otherwise it returns the new instruction.
2676 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2677 MachineBasicBlock::iterator &MBBI,
2678 LiveVariables *LV) const {
2679 MachineInstr *MI = MBBI;
2681 // The following opcodes also sets the condition code register(s). Only
2682 // convert them to equivalent lea if the condition code register def's
2684 if (hasLiveCondCodeDef(MI))
2687 MachineFunction &MF = *MI->getParent()->getParent();
2688 // All instructions input are two-addr instructions. Get the known operands.
2689 const MachineOperand &Dest = MI->getOperand(0);
2690 const MachineOperand &Src = MI->getOperand(1);
2692 MachineInstr *NewMI = nullptr;
2693 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
2694 // we have better subtarget support, enable the 16-bit LEA generation here.
2695 // 16-bit LEA is also slow on Core2.
2696 bool DisableLEA16 = true;
2697 bool is64Bit = Subtarget.is64Bit();
2699 unsigned MIOpc = MI->getOpcode();
2701 default: return nullptr;
2702 case X86::SHL64ri: {
2703 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2704 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2705 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2707 // LEA can't handle RSP.
2708 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2709 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2710 &X86::GR64_NOSPRegClass))
2713 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2715 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2718 case X86::SHL32ri: {
2719 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2720 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2721 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2723 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2725 // LEA can't handle ESP.
2726 bool isKill, isUndef;
2728 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2729 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2730 SrcReg, isKill, isUndef, ImplicitOp))
2733 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2735 .addReg(0).addImm(1 << ShAmt)
2736 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2737 .addImm(0).addReg(0);
2738 if (ImplicitOp.getReg() != 0)
2739 MIB.addOperand(ImplicitOp);
2744 case X86::SHL16ri: {
2745 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2746 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2747 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2750 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2751 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2753 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2758 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2759 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2760 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2761 bool isKill, isUndef;
2763 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2764 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2765 SrcReg, isKill, isUndef, ImplicitOp))
2768 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2770 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2771 if (ImplicitOp.getReg() != 0)
2772 MIB.addOperand(ImplicitOp);
2774 NewMI = addOffset(MIB, 1);
2779 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2781 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2782 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2783 .addOperand(Dest).addOperand(Src), 1);
2787 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2788 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2789 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2791 bool isKill, isUndef;
2793 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2794 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2795 SrcReg, isKill, isUndef, ImplicitOp))
2798 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2800 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2801 if (ImplicitOp.getReg() != 0)
2802 MIB.addOperand(ImplicitOp);
2804 NewMI = addOffset(MIB, -1);
2810 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2812 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2813 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2814 .addOperand(Dest).addOperand(Src), -1);
2817 case X86::ADD64rr_DB:
2819 case X86::ADD32rr_DB: {
2820 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2822 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2825 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2827 bool isKill, isUndef;
2829 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2830 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2831 SrcReg, isKill, isUndef, ImplicitOp))
2834 const MachineOperand &Src2 = MI->getOperand(2);
2835 bool isKill2, isUndef2;
2837 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2838 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2839 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2842 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2844 if (ImplicitOp.getReg() != 0)
2845 MIB.addOperand(ImplicitOp);
2846 if (ImplicitOp2.getReg() != 0)
2847 MIB.addOperand(ImplicitOp2);
2849 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2851 // Preserve undefness of the operands.
2852 NewMI->getOperand(1).setIsUndef(isUndef);
2853 NewMI->getOperand(3).setIsUndef(isUndef2);
2855 if (LV && Src2.isKill())
2856 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2860 case X86::ADD16rr_DB: {
2862 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2864 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2865 unsigned Src2 = MI->getOperand(2).getReg();
2866 bool isKill2 = MI->getOperand(2).isKill();
2867 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2869 Src.getReg(), Src.isKill(), Src2, isKill2);
2871 // Preserve undefness of the operands.
2872 bool isUndef = MI->getOperand(1).isUndef();
2873 bool isUndef2 = MI->getOperand(2).isUndef();
2874 NewMI->getOperand(1).setIsUndef(isUndef);
2875 NewMI->getOperand(3).setIsUndef(isUndef2);
2878 LV->replaceKillInstruction(Src2, MI, NewMI);
2881 case X86::ADD64ri32:
2883 case X86::ADD64ri32_DB:
2884 case X86::ADD64ri8_DB:
2885 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2886 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2887 .addOperand(Dest).addOperand(Src),
2888 MI->getOperand(2).getImm());
2892 case X86::ADD32ri_DB:
2893 case X86::ADD32ri8_DB: {
2894 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2895 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2897 bool isKill, isUndef;
2899 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2900 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2901 SrcReg, isKill, isUndef, ImplicitOp))
2904 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2906 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2907 if (ImplicitOp.getReg() != 0)
2908 MIB.addOperand(ImplicitOp);
2910 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2915 case X86::ADD16ri_DB:
2916 case X86::ADD16ri8_DB:
2918 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2920 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2921 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2922 .addOperand(Dest).addOperand(Src),
2923 MI->getOperand(2).getImm());
2927 if (!NewMI) return nullptr;
2929 if (LV) { // Update live variables
2931 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2933 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2936 MFI->insert(MBBI, NewMI); // Insert the new inst
2940 /// We have a few instructions that must be hacked on to commute them.
2943 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2944 switch (MI->getOpcode()) {
2945 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2946 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2947 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2948 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2949 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2950 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2953 switch (MI->getOpcode()) {
2954 default: llvm_unreachable("Unreachable!");
2955 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2956 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2957 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2958 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2959 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2960 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2962 unsigned Amt = MI->getOperand(3).getImm();
2964 MachineFunction &MF = *MI->getParent()->getParent();
2965 MI = MF.CloneMachineInstr(MI);
2968 MI->setDesc(get(Opc));
2969 MI->getOperand(3).setImm(Size-Amt);
2970 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2972 case X86::BLENDPDrri:
2973 case X86::BLENDPSrri:
2974 case X86::PBLENDWrri:
2975 case X86::VBLENDPDrri:
2976 case X86::VBLENDPSrri:
2977 case X86::VBLENDPDYrri:
2978 case X86::VBLENDPSYrri:
2979 case X86::VPBLENDDrri:
2980 case X86::VPBLENDWrri:
2981 case X86::VPBLENDDYrri:
2982 case X86::VPBLENDWYrri:{
2984 switch (MI->getOpcode()) {
2985 default: llvm_unreachable("Unreachable!");
2986 case X86::BLENDPDrri: Mask = 0x03; break;
2987 case X86::BLENDPSrri: Mask = 0x0F; break;
2988 case X86::PBLENDWrri: Mask = 0xFF; break;
2989 case X86::VBLENDPDrri: Mask = 0x03; break;
2990 case X86::VBLENDPSrri: Mask = 0x0F; break;
2991 case X86::VBLENDPDYrri: Mask = 0x0F; break;
2992 case X86::VBLENDPSYrri: Mask = 0xFF; break;
2993 case X86::VPBLENDDrri: Mask = 0x0F; break;
2994 case X86::VPBLENDWrri: Mask = 0xFF; break;
2995 case X86::VPBLENDDYrri: Mask = 0xFF; break;
2996 case X86::VPBLENDWYrri: Mask = 0xFF; break;
2998 // Only the least significant bits of Imm are used.
2999 unsigned Imm = MI->getOperand(3).getImm() & Mask;
3001 MachineFunction &MF = *MI->getParent()->getParent();
3002 MI = MF.CloneMachineInstr(MI);
3005 MI->getOperand(3).setImm(Mask ^ Imm);
3006 return TargetInstrInfo::commuteInstruction(MI, NewMI);
3008 case X86::PCLMULQDQrr:
3009 case X86::VPCLMULQDQrr:{
3010 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3011 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3012 unsigned Imm = MI->getOperand(3).getImm();
3013 unsigned Src1Hi = Imm & 0x01;
3014 unsigned Src2Hi = Imm & 0x10;
3016 MachineFunction &MF = *MI->getParent()->getParent();
3017 MI = MF.CloneMachineInstr(MI);
3020 MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3021 return TargetInstrInfo::commuteInstruction(MI, NewMI);
3025 case X86::VCMPPDrri:
3026 case X86::VCMPPSrri:
3027 case X86::VCMPPDYrri:
3028 case X86::VCMPPSYrri: {
3029 // Float comparison can be safely commuted for
3030 // Ordered/Unordered/Equal/NotEqual tests
3031 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3034 case 0x03: // UNORDERED
3035 case 0x04: // NOT EQUAL
3036 case 0x07: // ORDERED
3038 MachineFunction &MF = *MI->getParent()->getParent();
3039 MI = MF.CloneMachineInstr(MI);
3042 return TargetInstrInfo::commuteInstruction(MI, NewMI);
3047 case X86::VPCOMBri: case X86::VPCOMUBri:
3048 case X86::VPCOMDri: case X86::VPCOMUDri:
3049 case X86::VPCOMQri: case X86::VPCOMUQri:
3050 case X86::VPCOMWri: case X86::VPCOMUWri: {
3051 // Flip comparison mode immediate (if necessary).
3052 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3054 case 0x00: Imm = 0x02; break; // LT -> GT
3055 case 0x01: Imm = 0x03; break; // LE -> GE
3056 case 0x02: Imm = 0x00; break; // GT -> LT
3057 case 0x03: Imm = 0x01; break; // GE -> LE
3066 MachineFunction &MF = *MI->getParent()->getParent();
3067 MI = MF.CloneMachineInstr(MI);
3070 MI->getOperand(3).setImm(Imm);
3071 return TargetInstrInfo::commuteInstruction(MI, NewMI);
3073 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3074 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3075 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3076 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3077 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3078 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3079 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3080 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3081 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3082 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3083 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3084 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3085 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3086 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3087 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3088 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3090 switch (MI->getOpcode()) {
3091 default: llvm_unreachable("Unreachable!");
3092 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3093 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3094 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3095 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3096 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3097 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3098 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3099 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3100 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3101 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3102 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3103 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3104 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3105 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3106 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3107 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3108 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3109 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
3110 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3111 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3112 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3113 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3114 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3115 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3116 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3117 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3118 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3119 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3120 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3121 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3122 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3123 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
3124 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
3125 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3126 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3127 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3128 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3129 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
3130 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
3131 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3132 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3133 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3134 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3135 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
3136 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
3137 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3138 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3139 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3142 MachineFunction &MF = *MI->getParent()->getParent();
3143 MI = MF.CloneMachineInstr(MI);
3146 MI->setDesc(get(Opc));
3147 // Fallthrough intended.
3150 return TargetInstrInfo::commuteInstruction(MI, NewMI);
3154 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
3155 unsigned &SrcOpIdx2) const {
3156 switch (MI->getOpcode()) {
3159 case X86::VCMPPDrri:
3160 case X86::VCMPPSrri:
3161 case X86::VCMPPDYrri:
3162 case X86::VCMPPSYrri: {
3163 // Float comparison can be safely commuted for
3164 // Ordered/Unordered/Equal/NotEqual tests
3165 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3168 case 0x03: // UNORDERED
3169 case 0x04: // NOT EQUAL
3170 case 0x07: // ORDERED
3177 case X86::VFMADDPDr231r:
3178 case X86::VFMADDPSr231r:
3179 case X86::VFMADDSDr231r:
3180 case X86::VFMADDSSr231r:
3181 case X86::VFMSUBPDr231r:
3182 case X86::VFMSUBPSr231r:
3183 case X86::VFMSUBSDr231r:
3184 case X86::VFMSUBSSr231r:
3185 case X86::VFNMADDPDr231r:
3186 case X86::VFNMADDPSr231r:
3187 case X86::VFNMADDSDr231r:
3188 case X86::VFNMADDSSr231r:
3189 case X86::VFNMSUBPDr231r:
3190 case X86::VFNMSUBPSr231r:
3191 case X86::VFNMSUBSDr231r:
3192 case X86::VFNMSUBSSr231r:
3193 case X86::VFMADDPDr231rY:
3194 case X86::VFMADDPSr231rY:
3195 case X86::VFMSUBPDr231rY:
3196 case X86::VFMSUBPSr231rY:
3197 case X86::VFNMADDPDr231rY:
3198 case X86::VFNMADDPSr231rY:
3199 case X86::VFNMSUBPDr231rY:
3200 case X86::VFNMSUBPSr231rY:
3205 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3209 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3211 default: return X86::COND_INVALID;
3212 case X86::JE_1: return X86::COND_E;
3213 case X86::JNE_1: return X86::COND_NE;
3214 case X86::JL_1: return X86::COND_L;
3215 case X86::JLE_1: return X86::COND_LE;
3216 case X86::JG_1: return X86::COND_G;
3217 case X86::JGE_1: return X86::COND_GE;
3218 case X86::JB_1: return X86::COND_B;
3219 case X86::JBE_1: return X86::COND_BE;
3220 case X86::JA_1: return X86::COND_A;
3221 case X86::JAE_1: return X86::COND_AE;
3222 case X86::JS_1: return X86::COND_S;
3223 case X86::JNS_1: return X86::COND_NS;
3224 case X86::JP_1: return X86::COND_P;
3225 case X86::JNP_1: return X86::COND_NP;
3226 case X86::JO_1: return X86::COND_O;
3227 case X86::JNO_1: return X86::COND_NO;
3231 /// Return condition code of a SET opcode.
3232 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3234 default: return X86::COND_INVALID;
3235 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3236 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3237 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3238 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3239 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3240 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3241 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3242 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3243 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3244 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3245 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3246 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3247 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3248 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3249 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3250 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3254 /// Return condition code of a CMov opcode.
3255 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3257 default: return X86::COND_INVALID;
3258 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3259 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3261 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3262 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3263 return X86::COND_AE;
3264 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3265 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3267 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3268 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3269 return X86::COND_BE;
3270 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3271 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3273 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3274 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3276 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3277 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3278 return X86::COND_GE;
3279 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3280 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3282 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3283 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3284 return X86::COND_LE;
3285 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3286 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3287 return X86::COND_NE;
3288 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3289 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3290 return X86::COND_NO;
3291 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3292 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3293 return X86::COND_NP;
3294 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3295 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3296 return X86::COND_NS;
3297 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3298 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3300 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3301 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3303 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3304 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3309 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3311 default: llvm_unreachable("Illegal condition code!");
3312 case X86::COND_E: return X86::JE_1;
3313 case X86::COND_NE: return X86::JNE_1;
3314 case X86::COND_L: return X86::JL_1;
3315 case X86::COND_LE: return X86::JLE_1;
3316 case X86::COND_G: return X86::JG_1;
3317 case X86::COND_GE: return X86::JGE_1;
3318 case X86::COND_B: return X86::JB_1;
3319 case X86::COND_BE: return X86::JBE_1;
3320 case X86::COND_A: return X86::JA_1;
3321 case X86::COND_AE: return X86::JAE_1;
3322 case X86::COND_S: return X86::JS_1;
3323 case X86::COND_NS: return X86::JNS_1;
3324 case X86::COND_P: return X86::JP_1;
3325 case X86::COND_NP: return X86::JNP_1;
3326 case X86::COND_O: return X86::JO_1;
3327 case X86::COND_NO: return X86::JNO_1;
3331 /// Return the inverse of the specified condition,
3332 /// e.g. turning COND_E to COND_NE.
3333 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3335 default: llvm_unreachable("Illegal condition code!");
3336 case X86::COND_E: return X86::COND_NE;
3337 case X86::COND_NE: return X86::COND_E;
3338 case X86::COND_L: return X86::COND_GE;
3339 case X86::COND_LE: return X86::COND_G;
3340 case X86::COND_G: return X86::COND_LE;
3341 case X86::COND_GE: return X86::COND_L;
3342 case X86::COND_B: return X86::COND_AE;
3343 case X86::COND_BE: return X86::COND_A;
3344 case X86::COND_A: return X86::COND_BE;
3345 case X86::COND_AE: return X86::COND_B;
3346 case X86::COND_S: return X86::COND_NS;
3347 case X86::COND_NS: return X86::COND_S;
3348 case X86::COND_P: return X86::COND_NP;
3349 case X86::COND_NP: return X86::COND_P;
3350 case X86::COND_O: return X86::COND_NO;
3351 case X86::COND_NO: return X86::COND_O;
3355 /// Assuming the flags are set by MI(a,b), return the condition code if we
3356 /// modify the instructions such that flags are set by MI(b,a).
3357 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3359 default: return X86::COND_INVALID;
3360 case X86::COND_E: return X86::COND_E;
3361 case X86::COND_NE: return X86::COND_NE;
3362 case X86::COND_L: return X86::COND_G;
3363 case X86::COND_LE: return X86::COND_GE;
3364 case X86::COND_G: return X86::COND_L;
3365 case X86::COND_GE: return X86::COND_LE;
3366 case X86::COND_B: return X86::COND_A;
3367 case X86::COND_BE: return X86::COND_AE;
3368 case X86::COND_A: return X86::COND_B;
3369 case X86::COND_AE: return X86::COND_BE;
3373 /// Return a set opcode for the given condition and
3374 /// whether it has memory operand.
3375 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3376 static const uint16_t Opc[16][2] = {
3377 { X86::SETAr, X86::SETAm },
3378 { X86::SETAEr, X86::SETAEm },
3379 { X86::SETBr, X86::SETBm },
3380 { X86::SETBEr, X86::SETBEm },
3381 { X86::SETEr, X86::SETEm },
3382 { X86::SETGr, X86::SETGm },
3383 { X86::SETGEr, X86::SETGEm },
3384 { X86::SETLr, X86::SETLm },
3385 { X86::SETLEr, X86::SETLEm },
3386 { X86::SETNEr, X86::SETNEm },
3387 { X86::SETNOr, X86::SETNOm },
3388 { X86::SETNPr, X86::SETNPm },
3389 { X86::SETNSr, X86::SETNSm },
3390 { X86::SETOr, X86::SETOm },
3391 { X86::SETPr, X86::SETPm },
3392 { X86::SETSr, X86::SETSm }
3395 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3396 return Opc[CC][HasMemoryOperand ? 1 : 0];
3399 /// Return a cmov opcode for the given condition,
3400 /// register size in bytes, and operand type.
3401 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3402 bool HasMemoryOperand) {
3403 static const uint16_t Opc[32][3] = {
3404 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3405 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3406 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3407 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3408 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3409 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3410 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3411 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3412 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3413 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3414 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3415 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3416 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3417 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3418 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
3419 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3420 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3421 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3422 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3423 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3424 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3425 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3426 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3427 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3428 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3429 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3430 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3431 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3432 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3433 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3434 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3435 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
3438 assert(CC < 16 && "Can only handle standard cond codes");
3439 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3441 default: llvm_unreachable("Illegal register size!");
3442 case 2: return Opc[Idx][0];
3443 case 4: return Opc[Idx][1];
3444 case 8: return Opc[Idx][2];
3448 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3449 if (!MI->isTerminator()) return false;
3451 // Conditional branch is a special case.
3452 if (MI->isBranch() && !MI->isBarrier())
3454 if (!MI->isPredicable())
3456 return !isPredicated(MI);
3459 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
3460 MachineBasicBlock *&TBB,
3461 MachineBasicBlock *&FBB,
3462 SmallVectorImpl<MachineOperand> &Cond,
3463 bool AllowModify) const {
3464 // Start from the bottom of the block and work up, examining the
3465 // terminator instructions.
3466 MachineBasicBlock::iterator I = MBB.end();
3467 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3468 while (I != MBB.begin()) {
3470 if (I->isDebugValue())
3473 // Working from the bottom, when we see a non-terminator instruction, we're
3475 if (!isUnpredicatedTerminator(I))
3478 // A terminator that isn't a branch can't easily be handled by this
3483 // Handle unconditional branches.
3484 if (I->getOpcode() == X86::JMP_1) {
3488 TBB = I->getOperand(0).getMBB();
3492 // If the block has any instructions after a JMP, delete them.
3493 while (std::next(I) != MBB.end())
3494 std::next(I)->eraseFromParent();
3499 // Delete the JMP if it's equivalent to a fall-through.
3500 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3502 I->eraseFromParent();
3504 UnCondBrIter = MBB.end();
3508 // TBB is used to indicate the unconditional destination.
3509 TBB = I->getOperand(0).getMBB();
3513 // Handle conditional branches.
3514 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3515 if (BranchCode == X86::COND_INVALID)
3516 return true; // Can't handle indirect branch.
3518 // Working from the bottom, handle the first conditional branch.
3520 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3521 if (AllowModify && UnCondBrIter != MBB.end() &&
3522 MBB.isLayoutSuccessor(TargetBB)) {
3523 // If we can modify the code and it ends in something like:
3531 // Then we can change this to:
3538 // Which is a bit more efficient.
3539 // We conditionally jump to the fall-through block.
3540 BranchCode = GetOppositeBranchCondition(BranchCode);
3541 unsigned JNCC = GetCondBranchFromCond(BranchCode);
3542 MachineBasicBlock::iterator OldInst = I;
3544 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3545 .addMBB(UnCondBrIter->getOperand(0).getMBB());
3546 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3549 OldInst->eraseFromParent();
3550 UnCondBrIter->eraseFromParent();
3552 // Restart the analysis.
3553 UnCondBrIter = MBB.end();
3559 TBB = I->getOperand(0).getMBB();
3560 Cond.push_back(MachineOperand::CreateImm(BranchCode));
3564 // Handle subsequent conditional branches. Only handle the case where all
3565 // conditional branches branch to the same destination and their condition
3566 // opcodes fit one of the special multi-branch idioms.
3567 assert(Cond.size() == 1);
3570 // Only handle the case where all conditional branches branch to the same
3572 if (TBB != I->getOperand(0).getMBB())
3575 // If the conditions are the same, we can leave them alone.
3576 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3577 if (OldBranchCode == BranchCode)
3580 // If they differ, see if they fit one of the known patterns. Theoretically,
3581 // we could handle more patterns here, but we shouldn't expect to see them
3582 // if instruction selection has done a reasonable job.
3583 if ((OldBranchCode == X86::COND_NP &&
3584 BranchCode == X86::COND_E) ||
3585 (OldBranchCode == X86::COND_E &&
3586 BranchCode == X86::COND_NP))
3587 BranchCode = X86::COND_NP_OR_E;
3588 else if ((OldBranchCode == X86::COND_P &&
3589 BranchCode == X86::COND_NE) ||
3590 (OldBranchCode == X86::COND_NE &&
3591 BranchCode == X86::COND_P))
3592 BranchCode = X86::COND_NE_OR_P;
3596 // Update the MachineOperand.
3597 Cond[0].setImm(BranchCode);
3603 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
3604 MachineBasicBlock::iterator I = MBB.end();
3607 while (I != MBB.begin()) {
3609 if (I->isDebugValue())
3611 if (I->getOpcode() != X86::JMP_1 &&
3612 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3614 // Remove the branch.
3615 I->eraseFromParent();
3624 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3625 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
3626 DebugLoc DL) const {
3627 // Shouldn't be a fall through.
3628 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
3629 assert((Cond.size() == 1 || Cond.size() == 0) &&
3630 "X86 branch conditions have one component!");
3633 // Unconditional branch?
3634 assert(!FBB && "Unconditional branch with multiple successors!");
3635 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3639 // Conditional branch.
3641 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3643 case X86::COND_NP_OR_E:
3644 // Synthesize NP_OR_E with two branches.
3645 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
3647 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
3650 case X86::COND_NE_OR_P:
3651 // Synthesize NE_OR_P with two branches.
3652 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
3654 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
3658 unsigned Opc = GetCondBranchFromCond(CC);
3659 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
3664 // Two-way Conditional branch. Insert the second branch.
3665 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3672 canInsertSelect(const MachineBasicBlock &MBB,
3673 ArrayRef<MachineOperand> Cond,
3674 unsigned TrueReg, unsigned FalseReg,
3675 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3676 // Not all subtargets have cmov instructions.
3677 if (!Subtarget.hasCMov())
3679 if (Cond.size() != 1)
3681 // We cannot do the composite conditions, at least not in SSA form.
3682 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3685 // Check register classes.
3686 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3687 const TargetRegisterClass *RC =
3688 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3692 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3693 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3694 X86::GR32RegClass.hasSubClassEq(RC) ||
3695 X86::GR64RegClass.hasSubClassEq(RC)) {
3696 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3697 // Bridge. Probably Ivy Bridge as well.
3704 // Can't do vectors.
3708 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3709 MachineBasicBlock::iterator I, DebugLoc DL,
3710 unsigned DstReg, ArrayRef<MachineOperand> Cond,
3711 unsigned TrueReg, unsigned FalseReg) const {
3712 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3713 assert(Cond.size() == 1 && "Invalid Cond array");
3714 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3715 MRI.getRegClass(DstReg)->getSize(),
3716 false/*HasMemoryOperand*/);
3717 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3720 /// Test if the given register is a physical h register.
3721 static bool isHReg(unsigned Reg) {
3722 return X86::GR8_ABCD_HRegClass.contains(Reg);
3725 // Try and copy between VR128/VR64 and GR64 registers.
3726 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3727 const X86Subtarget &Subtarget) {
3729 // SrcReg(VR128) -> DestReg(GR64)
3730 // SrcReg(VR64) -> DestReg(GR64)
3731 // SrcReg(GR64) -> DestReg(VR128)
3732 // SrcReg(GR64) -> DestReg(VR64)
3734 bool HasAVX = Subtarget.hasAVX();
3735 bool HasAVX512 = Subtarget.hasAVX512();
3736 if (X86::GR64RegClass.contains(DestReg)) {
3737 if (X86::VR128XRegClass.contains(SrcReg))
3738 // Copy from a VR128 register to a GR64 register.
3739 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3741 if (X86::VR64RegClass.contains(SrcReg))
3742 // Copy from a VR64 register to a GR64 register.
3743 return X86::MOVSDto64rr;
3744 } else if (X86::GR64RegClass.contains(SrcReg)) {
3745 // Copy from a GR64 register to a VR128 register.
3746 if (X86::VR128XRegClass.contains(DestReg))
3747 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3749 // Copy from a GR64 register to a VR64 register.
3750 if (X86::VR64RegClass.contains(DestReg))
3751 return X86::MOV64toSDrr;
3754 // SrcReg(FR32) -> DestReg(GR32)
3755 // SrcReg(GR32) -> DestReg(FR32)
3757 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3758 // Copy from a FR32 register to a GR32 register.
3759 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3761 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3762 // Copy from a GR32 register to a FR32 register.
3763 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3767 inline static bool MaskRegClassContains(unsigned Reg) {
3768 return X86::VK8RegClass.contains(Reg) ||
3769 X86::VK16RegClass.contains(Reg) ||
3770 X86::VK32RegClass.contains(Reg) ||
3771 X86::VK64RegClass.contains(Reg) ||
3772 X86::VK1RegClass.contains(Reg);
3775 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3776 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3777 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3778 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3779 DestReg = get512BitSuperRegister(DestReg);
3780 SrcReg = get512BitSuperRegister(SrcReg);
3781 return X86::VMOVAPSZrr;
3783 if (MaskRegClassContains(DestReg) &&
3784 MaskRegClassContains(SrcReg))
3785 return X86::KMOVWkk;
3786 if (MaskRegClassContains(DestReg) &&
3787 (X86::GR32RegClass.contains(SrcReg) ||
3788 X86::GR16RegClass.contains(SrcReg) ||
3789 X86::GR8RegClass.contains(SrcReg))) {
3790 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3791 return X86::KMOVWkr;
3793 if ((X86::GR32RegClass.contains(DestReg) ||
3794 X86::GR16RegClass.contains(DestReg) ||
3795 X86::GR8RegClass.contains(DestReg)) &&
3796 MaskRegClassContains(SrcReg)) {
3797 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3798 return X86::KMOVWrk;
3803 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3804 MachineBasicBlock::iterator MI, DebugLoc DL,
3805 unsigned DestReg, unsigned SrcReg,
3806 bool KillSrc) const {
3807 // First deal with the normal symmetric copies.
3808 bool HasAVX = Subtarget.hasAVX();
3809 bool HasAVX512 = Subtarget.hasAVX512();
3811 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3813 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3815 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3817 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3818 // Copying to or from a physical H register on x86-64 requires a NOREX
3819 // move. Otherwise use a normal move.
3820 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3821 Subtarget.is64Bit()) {
3822 Opc = X86::MOV8rr_NOREX;
3823 // Both operands must be encodable without an REX prefix.
3824 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3825 "8-bit H register can not be copied outside GR8_NOREX");
3829 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3830 Opc = X86::MMX_MOVQ64rr;
3832 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3833 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3834 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3835 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3836 Opc = X86::VMOVAPSYrr;
3838 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3841 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3842 .addReg(SrcReg, getKillRegState(KillSrc));
3846 // Moving EFLAGS to / from another register requires a push and a pop.
3847 // Notice that we have to adjust the stack if we don't want to clobber the
3848 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3849 if (SrcReg == X86::EFLAGS) {
3850 if (X86::GR64RegClass.contains(DestReg)) {
3851 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3852 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3855 if (X86::GR32RegClass.contains(DestReg)) {
3856 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3857 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3861 if (DestReg == X86::EFLAGS) {
3862 if (X86::GR64RegClass.contains(SrcReg)) {
3863 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3864 .addReg(SrcReg, getKillRegState(KillSrc));
3865 BuildMI(MBB, MI, DL, get(X86::POPF64));
3868 if (X86::GR32RegClass.contains(SrcReg)) {
3869 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3870 .addReg(SrcReg, getKillRegState(KillSrc));
3871 BuildMI(MBB, MI, DL, get(X86::POPF32));
3876 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3877 << " to " << RI.getName(DestReg) << '\n');
3878 llvm_unreachable("Cannot emit physreg copy instruction");
3881 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3882 const TargetRegisterClass *RC,
3883 bool isStackAligned,
3884 const X86Subtarget &STI,
3886 if (STI.hasAVX512()) {
3887 if (X86::VK8RegClass.hasSubClassEq(RC) ||
3888 X86::VK16RegClass.hasSubClassEq(RC))
3889 return load ? X86::KMOVWkm : X86::KMOVWmk;
3890 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3891 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3892 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3893 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3894 if (X86::VR512RegClass.hasSubClassEq(RC))
3895 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3898 bool HasAVX = STI.hasAVX();
3899 switch (RC->getSize()) {
3901 llvm_unreachable("Unknown spill size");
3903 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3905 // Copying to or from a physical H register on x86-64 requires a NOREX
3906 // move. Otherwise use a normal move.
3907 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3908 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3909 return load ? X86::MOV8rm : X86::MOV8mr;
3911 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3912 return load ? X86::MOV16rm : X86::MOV16mr;
3914 if (X86::GR32RegClass.hasSubClassEq(RC))
3915 return load ? X86::MOV32rm : X86::MOV32mr;
3916 if (X86::FR32RegClass.hasSubClassEq(RC))
3918 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3919 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3920 if (X86::RFP32RegClass.hasSubClassEq(RC))
3921 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3922 llvm_unreachable("Unknown 4-byte regclass");
3924 if (X86::GR64RegClass.hasSubClassEq(RC))
3925 return load ? X86::MOV64rm : X86::MOV64mr;
3926 if (X86::FR64RegClass.hasSubClassEq(RC))
3928 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3929 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3930 if (X86::VR64RegClass.hasSubClassEq(RC))
3931 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3932 if (X86::RFP64RegClass.hasSubClassEq(RC))
3933 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3934 llvm_unreachable("Unknown 8-byte regclass");
3936 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3937 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3939 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3940 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3941 // If stack is realigned we can use aligned stores.
3944 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3945 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3948 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3949 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3952 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3953 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3954 // If stack is realigned we can use aligned stores.
3956 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3958 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3960 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3962 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3964 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3968 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
3970 const TargetRegisterInfo *TRI) const {
3971 const MCInstrDesc &Desc = MemOp->getDesc();
3972 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode());
3973 if (MemRefBegin < 0)
3976 MemRefBegin += X86II::getOperandBias(Desc);
3978 BaseReg = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg).getReg();
3979 if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3982 if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3986 const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
3988 // Displacement can be symbolic
3989 if (!DispMO.isImm())
3992 Offset = DispMO.getImm();
3994 return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
3998 static unsigned getStoreRegOpcode(unsigned SrcReg,
3999 const TargetRegisterClass *RC,
4000 bool isStackAligned,
4001 const X86Subtarget &STI) {
4002 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4006 static unsigned getLoadRegOpcode(unsigned DestReg,
4007 const TargetRegisterClass *RC,
4008 bool isStackAligned,
4009 const X86Subtarget &STI) {
4010 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4013 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4014 MachineBasicBlock::iterator MI,
4015 unsigned SrcReg, bool isKill, int FrameIdx,
4016 const TargetRegisterClass *RC,
4017 const TargetRegisterInfo *TRI) const {
4018 const MachineFunction &MF = *MBB.getParent();
4019 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4020 "Stack slot too small for store");
4021 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4023 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4024 RI.canRealignStack(MF);
4025 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4026 DebugLoc DL = MBB.findDebugLoc(MI);
4027 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4028 .addReg(SrcReg, getKillRegState(isKill));
4031 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4033 SmallVectorImpl<MachineOperand> &Addr,
4034 const TargetRegisterClass *RC,
4035 MachineInstr::mmo_iterator MMOBegin,
4036 MachineInstr::mmo_iterator MMOEnd,
4037 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4038 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4039 bool isAligned = MMOBegin != MMOEnd &&
4040 (*MMOBegin)->getAlignment() >= Alignment;
4041 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4043 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4044 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4045 MIB.addOperand(Addr[i]);
4046 MIB.addReg(SrcReg, getKillRegState(isKill));
4047 (*MIB).setMemRefs(MMOBegin, MMOEnd);
4048 NewMIs.push_back(MIB);
4052 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4053 MachineBasicBlock::iterator MI,
4054 unsigned DestReg, int FrameIdx,
4055 const TargetRegisterClass *RC,
4056 const TargetRegisterInfo *TRI) const {
4057 const MachineFunction &MF = *MBB.getParent();
4058 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4060 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4061 RI.canRealignStack(MF);
4062 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4063 DebugLoc DL = MBB.findDebugLoc(MI);
4064 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4067 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4068 SmallVectorImpl<MachineOperand> &Addr,
4069 const TargetRegisterClass *RC,
4070 MachineInstr::mmo_iterator MMOBegin,
4071 MachineInstr::mmo_iterator MMOEnd,
4072 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4073 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4074 bool isAligned = MMOBegin != MMOEnd &&
4075 (*MMOBegin)->getAlignment() >= Alignment;
4076 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4078 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4079 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4080 MIB.addOperand(Addr[i]);
4081 (*MIB).setMemRefs(MMOBegin, MMOEnd);
4082 NewMIs.push_back(MIB);
4086 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4087 int &CmpMask, int &CmpValue) const {
4088 switch (MI->getOpcode()) {
4090 case X86::CMP64ri32:
4097 SrcReg = MI->getOperand(0).getReg();
4100 CmpValue = MI->getOperand(1).getImm();
4102 // A SUB can be used to perform comparison.
4107 SrcReg = MI->getOperand(1).getReg();
4116 SrcReg = MI->getOperand(1).getReg();
4117 SrcReg2 = MI->getOperand(2).getReg();
4121 case X86::SUB64ri32:
4128 SrcReg = MI->getOperand(1).getReg();
4131 CmpValue = MI->getOperand(2).getImm();
4137 SrcReg = MI->getOperand(0).getReg();
4138 SrcReg2 = MI->getOperand(1).getReg();
4146 SrcReg = MI->getOperand(0).getReg();
4147 if (MI->getOperand(1).getReg() != SrcReg) return false;
4148 // Compare against zero.
4157 /// Check whether the first instruction, whose only
4158 /// purpose is to update flags, can be made redundant.
4159 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4160 /// This function can be extended later on.
4161 /// SrcReg, SrcRegs: register operands for FlagI.
4162 /// ImmValue: immediate for FlagI if it takes an immediate.
4163 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4164 unsigned SrcReg2, int ImmValue,
4166 if (((FlagI->getOpcode() == X86::CMP64rr &&
4167 OI->getOpcode() == X86::SUB64rr) ||
4168 (FlagI->getOpcode() == X86::CMP32rr &&
4169 OI->getOpcode() == X86::SUB32rr)||
4170 (FlagI->getOpcode() == X86::CMP16rr &&
4171 OI->getOpcode() == X86::SUB16rr)||
4172 (FlagI->getOpcode() == X86::CMP8rr &&
4173 OI->getOpcode() == X86::SUB8rr)) &&
4174 ((OI->getOperand(1).getReg() == SrcReg &&
4175 OI->getOperand(2).getReg() == SrcReg2) ||
4176 (OI->getOperand(1).getReg() == SrcReg2 &&
4177 OI->getOperand(2).getReg() == SrcReg)))
4180 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4181 OI->getOpcode() == X86::SUB64ri32) ||
4182 (FlagI->getOpcode() == X86::CMP64ri8 &&
4183 OI->getOpcode() == X86::SUB64ri8) ||
4184 (FlagI->getOpcode() == X86::CMP32ri &&
4185 OI->getOpcode() == X86::SUB32ri) ||
4186 (FlagI->getOpcode() == X86::CMP32ri8 &&
4187 OI->getOpcode() == X86::SUB32ri8) ||
4188 (FlagI->getOpcode() == X86::CMP16ri &&
4189 OI->getOpcode() == X86::SUB16ri) ||
4190 (FlagI->getOpcode() == X86::CMP16ri8 &&
4191 OI->getOpcode() == X86::SUB16ri8) ||
4192 (FlagI->getOpcode() == X86::CMP8ri &&
4193 OI->getOpcode() == X86::SUB8ri)) &&
4194 OI->getOperand(1).getReg() == SrcReg &&
4195 OI->getOperand(2).getImm() == ImmValue)
4200 /// Check whether the definition can be converted
4201 /// to remove a comparison against zero.
4202 inline static bool isDefConvertible(MachineInstr *MI) {
4203 switch (MI->getOpcode()) {
4204 default: return false;
4206 // The shift instructions only modify ZF if their shift count is non-zero.
4207 // N.B.: The processor truncates the shift count depending on the encoding.
4208 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4209 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4210 return getTruncatedShiftCount(MI, 2) != 0;
4212 // Some left shift instructions can be turned into LEA instructions but only
4213 // if their flags aren't used. Avoid transforming such instructions.
4214 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4215 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4216 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4220 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4221 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4222 return getTruncatedShiftCount(MI, 3) != 0;
4224 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4225 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4226 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4227 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4228 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
4229 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
4230 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4231 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4232 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4233 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4234 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
4235 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
4236 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4237 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4238 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4239 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4240 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4241 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4242 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4243 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4244 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4245 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4246 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4247 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4248 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4249 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4250 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
4251 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4252 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4253 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4254 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4255 case X86::ADC32ri: case X86::ADC32ri8:
4256 case X86::ADC32rr: case X86::ADC64ri32:
4257 case X86::ADC64ri8: case X86::ADC64rr:
4258 case X86::SBB32ri: case X86::SBB32ri8:
4259 case X86::SBB32rr: case X86::SBB64ri32:
4260 case X86::SBB64ri8: case X86::SBB64rr:
4261 case X86::ANDN32rr: case X86::ANDN32rm:
4262 case X86::ANDN64rr: case X86::ANDN64rm:
4263 case X86::BEXTR32rr: case X86::BEXTR64rr:
4264 case X86::BEXTR32rm: case X86::BEXTR64rm:
4265 case X86::BLSI32rr: case X86::BLSI32rm:
4266 case X86::BLSI64rr: case X86::BLSI64rm:
4267 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4268 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4269 case X86::BLSR32rr: case X86::BLSR32rm:
4270 case X86::BLSR64rr: case X86::BLSR64rm:
4271 case X86::BZHI32rr: case X86::BZHI32rm:
4272 case X86::BZHI64rr: case X86::BZHI64rm:
4273 case X86::LZCNT16rr: case X86::LZCNT16rm:
4274 case X86::LZCNT32rr: case X86::LZCNT32rm:
4275 case X86::LZCNT64rr: case X86::LZCNT64rm:
4276 case X86::POPCNT16rr:case X86::POPCNT16rm:
4277 case X86::POPCNT32rr:case X86::POPCNT32rm:
4278 case X86::POPCNT64rr:case X86::POPCNT64rm:
4279 case X86::TZCNT16rr: case X86::TZCNT16rm:
4280 case X86::TZCNT32rr: case X86::TZCNT32rm:
4281 case X86::TZCNT64rr: case X86::TZCNT64rm:
4286 /// Check whether the use can be converted to remove a comparison against zero.
4287 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4288 switch (MI->getOpcode()) {
4289 default: return X86::COND_INVALID;
4290 case X86::LZCNT16rr: case X86::LZCNT16rm:
4291 case X86::LZCNT32rr: case X86::LZCNT32rm:
4292 case X86::LZCNT64rr: case X86::LZCNT64rm:
4294 case X86::POPCNT16rr:case X86::POPCNT16rm:
4295 case X86::POPCNT32rr:case X86::POPCNT32rm:
4296 case X86::POPCNT64rr:case X86::POPCNT64rm:
4298 case X86::TZCNT16rr: case X86::TZCNT16rm:
4299 case X86::TZCNT32rr: case X86::TZCNT32rm:
4300 case X86::TZCNT64rr: case X86::TZCNT64rm:
4305 /// Check if there exists an earlier instruction that
4306 /// operates on the same source operands and sets flags in the same way as
4307 /// Compare; remove Compare if possible.
4309 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4310 int CmpMask, int CmpValue,
4311 const MachineRegisterInfo *MRI) const {
4312 // Check whether we can replace SUB with CMP.
4313 unsigned NewOpcode = 0;
4314 switch (CmpInstr->getOpcode()) {
4316 case X86::SUB64ri32:
4331 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4333 // There is no use of the destination register, we can replace SUB with CMP.
4334 switch (CmpInstr->getOpcode()) {
4335 default: llvm_unreachable("Unreachable!");
4336 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4337 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4338 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4339 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4340 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4341 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4342 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4343 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4344 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4345 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
4346 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
4347 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
4348 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
4349 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
4350 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
4352 CmpInstr->setDesc(get(NewOpcode));
4353 CmpInstr->RemoveOperand(0);
4354 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4355 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4356 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4361 // Get the unique definition of SrcReg.
4362 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4363 if (!MI) return false;
4365 // CmpInstr is the first instruction of the BB.
4366 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4368 // If we are comparing against zero, check whether we can use MI to update
4369 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4370 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
4371 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
4374 // If we have a use of the source register between the def and our compare
4375 // instruction we can eliminate the compare iff the use sets EFLAGS in the
4377 bool ShouldUpdateCC = false;
4378 X86::CondCode NewCC = X86::COND_INVALID;
4379 if (IsCmpZero && !isDefConvertible(MI)) {
4380 // Scan forward from the use until we hit the use we're looking for or the
4381 // compare instruction.
4382 for (MachineBasicBlock::iterator J = MI;; ++J) {
4383 // Do we have a convertible instruction?
4384 NewCC = isUseDefConvertible(J);
4385 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4386 J->getOperand(1).getReg() == SrcReg) {
4387 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4388 ShouldUpdateCC = true; // Update CC later on.
4389 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4390 // with the new def.
4400 // We are searching for an earlier instruction that can make CmpInstr
4401 // redundant and that instruction will be saved in Sub.
4402 MachineInstr *Sub = nullptr;
4403 const TargetRegisterInfo *TRI = &getRegisterInfo();
4405 // We iterate backward, starting from the instruction before CmpInstr and
4406 // stop when reaching the definition of a source register or done with the BB.
4407 // RI points to the instruction before CmpInstr.
4408 // If the definition is in this basic block, RE points to the definition;
4409 // otherwise, RE is the rend of the basic block.
4410 MachineBasicBlock::reverse_iterator
4411 RI = MachineBasicBlock::reverse_iterator(I),
4412 RE = CmpInstr->getParent() == MI->getParent() ?
4413 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
4414 CmpInstr->getParent()->rend();
4415 MachineInstr *Movr0Inst = nullptr;
4416 for (; RI != RE; ++RI) {
4417 MachineInstr *Instr = &*RI;
4418 // Check whether CmpInstr can be made redundant by the current instruction.
4420 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
4425 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
4426 Instr->readsRegister(X86::EFLAGS, TRI)) {
4427 // This instruction modifies or uses EFLAGS.
4429 // MOV32r0 etc. are implemented with xor which clobbers condition code.
4430 // They are safe to move up, if the definition to EFLAGS is dead and
4431 // earlier instructions do not read or write EFLAGS.
4432 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
4433 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4438 // We can't remove CmpInstr.
4443 // Return false if no candidates exist.
4444 if (!IsCmpZero && !Sub)
4447 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4448 Sub->getOperand(2).getReg() == SrcReg);
4450 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4451 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4452 // If we are done with the basic block, we need to check whether EFLAGS is
4454 bool IsSafe = false;
4455 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4456 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4457 for (++I; I != E; ++I) {
4458 const MachineInstr &Instr = *I;
4459 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4460 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4461 // We should check the usage if this instruction uses and updates EFLAGS.
4462 if (!UseEFLAGS && ModifyEFLAGS) {
4463 // It is safe to remove CmpInstr if EFLAGS is updated again.
4467 if (!UseEFLAGS && !ModifyEFLAGS)
4470 // EFLAGS is used by this instruction.
4471 X86::CondCode OldCC = X86::COND_INVALID;
4472 bool OpcIsSET = false;
4473 if (IsCmpZero || IsSwapped) {
4474 // We decode the condition code from opcode.
4475 if (Instr.isBranch())
4476 OldCC = getCondFromBranchOpc(Instr.getOpcode());
4478 OldCC = getCondFromSETOpc(Instr.getOpcode());
4479 if (OldCC != X86::COND_INVALID)
4482 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
4484 if (OldCC == X86::COND_INVALID) return false;
4489 case X86::COND_A: case X86::COND_AE:
4490 case X86::COND_B: case X86::COND_BE:
4491 case X86::COND_G: case X86::COND_GE:
4492 case X86::COND_L: case X86::COND_LE:
4493 case X86::COND_O: case X86::COND_NO:
4494 // CF and OF are used, we can't perform this optimization.
4498 // If we're updating the condition code check if we have to reverse the
4507 NewCC = GetOppositeBranchCondition(NewCC);
4510 } else if (IsSwapped) {
4511 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4512 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4513 // We swap the condition code and synthesize the new opcode.
4514 NewCC = getSwappedCondition(OldCC);
4515 if (NewCC == X86::COND_INVALID) return false;
4518 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
4519 // Synthesize the new opcode.
4520 bool HasMemoryOperand = Instr.hasOneMemOperand();
4522 if (Instr.isBranch())
4523 NewOpc = GetCondBranchFromCond(NewCC);
4525 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4527 unsigned DstReg = Instr.getOperand(0).getReg();
4528 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4532 // Push the MachineInstr to OpsToUpdate.
4533 // If it is safe to remove CmpInstr, the condition code of these
4534 // instructions will be modified.
4535 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4537 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4538 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4544 // If EFLAGS is not killed nor re-defined, we should check whether it is
4545 // live-out. If it is live-out, do not optimize.
4546 if ((IsCmpZero || IsSwapped) && !IsSafe) {
4547 MachineBasicBlock *MBB = CmpInstr->getParent();
4548 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4549 SE = MBB->succ_end(); SI != SE; ++SI)
4550 if ((*SI)->isLiveIn(X86::EFLAGS))
4554 // The instruction to be updated is either Sub or MI.
4555 Sub = IsCmpZero ? MI : Sub;
4556 // Move Movr0Inst to the appropriate place before Sub.
4558 // Look backwards until we find a def that doesn't use the current EFLAGS.
4560 MachineBasicBlock::reverse_iterator
4561 InsertI = MachineBasicBlock::reverse_iterator(++Def),
4562 InsertE = Sub->getParent()->rend();
4563 for (; InsertI != InsertE; ++InsertI) {
4564 MachineInstr *Instr = &*InsertI;
4565 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4566 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4567 Sub->getParent()->remove(Movr0Inst);
4568 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4573 if (InsertI == InsertE)
4577 // Make sure Sub instruction defines EFLAGS and mark the def live.
4578 unsigned i = 0, e = Sub->getNumOperands();
4579 for (; i != e; ++i) {
4580 MachineOperand &MO = Sub->getOperand(i);
4581 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4582 MO.setIsDead(false);
4586 assert(i != e && "Unable to locate a def EFLAGS operand");
4588 CmpInstr->eraseFromParent();
4590 // Modify the condition code of instructions in OpsToUpdate.
4591 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4592 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4596 /// Try to remove the load by folding it to a register
4597 /// operand at the use. We fold the load instructions if load defines a virtual
4598 /// register, the virtual register is used once in the same BB, and the
4599 /// instructions in-between do not load or store, and have no side effects.
4600 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4601 const MachineRegisterInfo *MRI,
4602 unsigned &FoldAsLoadDefReg,
4603 MachineInstr *&DefMI) const {
4604 if (FoldAsLoadDefReg == 0)
4606 // To be conservative, if there exists another load, clear the load candidate.
4607 if (MI->mayLoad()) {
4608 FoldAsLoadDefReg = 0;
4612 // Check whether we can move DefMI here.
4613 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4615 bool SawStore = false;
4616 if (!DefMI->isSafeToMove(nullptr, SawStore))
4619 // Collect information about virtual register operands of MI.
4620 unsigned SrcOperandId = 0;
4621 bool FoundSrcOperand = false;
4622 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4623 MachineOperand &MO = MI->getOperand(i);
4626 unsigned Reg = MO.getReg();
4627 if (Reg != FoldAsLoadDefReg)
4629 // Do not fold if we have a subreg use or a def or multiple uses.
4630 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
4634 FoundSrcOperand = true;
4636 if (!FoundSrcOperand)
4639 // Check whether we can fold the def into SrcOperandId.
4640 MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI);
4642 FoldAsLoadDefReg = 0;
4649 /// Expand a single-def pseudo instruction to a two-addr
4650 /// instruction with two undef reads of the register being defined.
4651 /// This is used for mapping:
4654 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4656 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4657 const MCInstrDesc &Desc) {
4658 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4659 unsigned Reg = MIB->getOperand(0).getReg();
4662 // MachineInstr::addOperand() will insert explicit operands before any
4663 // implicit operands.
4664 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4665 // But we don't trust that.
4666 assert(MIB->getOperand(1).getReg() == Reg &&
4667 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
4671 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4672 // code sequence is needed for other targets.
4673 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4674 const TargetInstrInfo &TII) {
4675 MachineBasicBlock &MBB = *MIB->getParent();
4676 DebugLoc DL = MIB->getDebugLoc();
4677 unsigned Reg = MIB->getOperand(0).getReg();
4678 const GlobalValue *GV =
4679 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4680 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4681 MachineMemOperand *MMO = MBB.getParent()->
4682 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
4683 MachineBasicBlock::iterator I = MIB.getInstr();
4685 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4686 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4687 .addMemOperand(MMO);
4688 MIB->setDebugLoc(DL);
4689 MIB->setDesc(TII.get(X86::MOV64rm));
4690 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4693 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4694 bool HasAVX = Subtarget.hasAVX();
4695 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4696 switch (MI->getOpcode()) {
4698 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4700 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4701 case X86::SETB_C16r:
4702 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4703 case X86::SETB_C32r:
4704 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4705 case X86::SETB_C64r:
4706 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4710 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4712 assert(HasAVX && "AVX not supported");
4713 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4714 case X86::AVX512_512_SET0:
4715 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4716 case X86::V_SETALLONES:
4717 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4718 case X86::AVX2_SETALLONES:
4719 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4720 case X86::TEST8ri_NOREX:
4721 MI->setDesc(get(X86::TEST8ri));
4724 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4726 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4727 case TargetOpcode::LOAD_STACK_GUARD:
4728 expandLoadStackGuard(MIB, *this);
4734 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs) {
4735 unsigned NumAddrOps = MOs.size();
4736 for (unsigned i = 0; i != NumAddrOps; ++i)
4737 MIB.addOperand(MOs[i]);
4738 if (NumAddrOps < 4) // FrameIndex only
4742 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4743 ArrayRef<MachineOperand> MOs,
4744 MachineBasicBlock::iterator InsertPt,
4746 const TargetInstrInfo &TII) {
4747 // Create the base instruction with the memory operand as the first part.
4748 // Omit the implicit operands, something BuildMI can't do.
4749 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4750 MI->getDebugLoc(), true);
4751 MachineInstrBuilder MIB(MF, NewMI);
4752 addOperands(MIB, MOs);
4754 // Loop over the rest of the ri operands, converting them over.
4755 unsigned NumOps = MI->getDesc().getNumOperands()-2;
4756 for (unsigned i = 0; i != NumOps; ++i) {
4757 MachineOperand &MO = MI->getOperand(i+2);
4760 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4761 MachineOperand &MO = MI->getOperand(i);
4765 MachineBasicBlock *MBB = InsertPt->getParent();
4766 MBB->insert(InsertPt, NewMI);
4771 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4772 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4773 MachineBasicBlock::iterator InsertPt,
4774 MachineInstr *MI, const TargetInstrInfo &TII) {
4775 // Omit the implicit operands, something BuildMI can't do.
4776 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4777 MI->getDebugLoc(), true);
4778 MachineInstrBuilder MIB(MF, NewMI);
4780 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4781 MachineOperand &MO = MI->getOperand(i);
4783 assert(MO.isReg() && "Expected to fold into reg operand!");
4784 addOperands(MIB, MOs);
4790 MachineBasicBlock *MBB = InsertPt->getParent();
4791 MBB->insert(InsertPt, NewMI);
4796 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4797 ArrayRef<MachineOperand> MOs,
4798 MachineBasicBlock::iterator InsertPt,
4800 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4801 MI->getDebugLoc(), TII.get(Opcode));
4802 addOperands(MIB, MOs);
4803 return MIB.addImm(0);
4806 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4807 MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
4808 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4809 unsigned Size, unsigned Align, bool AllowCommute) const {
4810 const DenseMap<unsigned,
4811 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4812 bool isCallRegIndirect = Subtarget.callRegIndirect();
4813 bool isTwoAddrFold = false;
4815 // For CPUs that favor the register form of a call,
4816 // do not fold loads into calls.
4817 if (isCallRegIndirect &&
4818 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r))
4821 unsigned NumOps = MI->getDesc().getNumOperands();
4822 bool isTwoAddr = NumOps > 1 &&
4823 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4825 // FIXME: AsmPrinter doesn't know how to handle
4826 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4827 if (MI->getOpcode() == X86::ADD32ri &&
4828 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4831 MachineInstr *NewMI = nullptr;
4832 // Folding a memory location into the two-address part of a two-address
4833 // instruction is different than folding it other places. It requires
4834 // replacing the *two* registers with the memory location.
4835 if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
4836 MI->getOperand(0).isReg() &&
4837 MI->getOperand(1).isReg() &&
4838 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4839 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4840 isTwoAddrFold = true;
4841 } else if (OpNum == 0) {
4842 if (MI->getOpcode() == X86::MOV32r0) {
4843 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4848 OpcodeTablePtr = &RegOp2MemOpTable0;
4849 } else if (OpNum == 1) {
4850 OpcodeTablePtr = &RegOp2MemOpTable1;
4851 } else if (OpNum == 2) {
4852 OpcodeTablePtr = &RegOp2MemOpTable2;
4853 } else if (OpNum == 3) {
4854 OpcodeTablePtr = &RegOp2MemOpTable3;
4855 } else if (OpNum == 4) {
4856 OpcodeTablePtr = &RegOp2MemOpTable4;
4859 // If table selected...
4860 if (OpcodeTablePtr) {
4861 // Find the Opcode to fuse
4862 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4863 OpcodeTablePtr->find(MI->getOpcode());
4864 if (I != OpcodeTablePtr->end()) {
4865 unsigned Opcode = I->second.first;
4866 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4867 if (Align < MinAlign)
4869 bool NarrowToMOV32rm = false;
4871 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
4872 if (Size < RCSize) {
4873 // Check if it's safe to fold the load. If the size of the object is
4874 // narrower than the load width, then it's not.
4875 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4877 // If this is a 64-bit load, but the spill slot is 32, then we can do
4878 // a 32-bit load which is implicitly zero-extended. This likely is
4879 // due to live interval analysis remat'ing a load from stack slot.
4880 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4882 Opcode = X86::MOV32rm;
4883 NarrowToMOV32rm = true;
4888 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4890 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4892 if (NarrowToMOV32rm) {
4893 // If this is the special case where we use a MOV32rm to load a 32-bit
4894 // value and zero-extend the top bits. Change the destination register
4896 unsigned DstReg = NewMI->getOperand(0).getReg();
4897 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4898 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4900 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4906 // If the instruction and target operand are commutable, commute the
4907 // instruction and try again.
4909 unsigned OriginalOpIdx = OpNum, CommuteOpIdx1, CommuteOpIdx2;
4910 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4911 bool HasDef = MI->getDesc().getNumDefs();
4912 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4913 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4914 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4916 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4918 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4920 // If either of the commutable operands are tied to the destination
4921 // then we can not commute + fold.
4922 if ((HasDef && Reg0 == Reg1 && Tied0) ||
4923 (HasDef && Reg0 == Reg2 && Tied1))
4926 if ((CommuteOpIdx1 == OriginalOpIdx) ||
4927 (CommuteOpIdx2 == OriginalOpIdx)) {
4928 MachineInstr *CommutedMI = commuteInstruction(MI, false);
4930 // Unable to commute.
4933 if (CommutedMI != MI) {
4934 // New instruction. We can't fold from this.
4935 CommutedMI->eraseFromParent();
4939 // Attempt to fold with the commuted version of the instruction.
4940 unsigned CommuteOp =
4941 (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4943 foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, InsertPt, Size, Align,
4944 /*AllowCommute=*/false);
4948 // Folding failed again - undo the commute before returning.
4949 MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4950 if (!UncommutedMI) {
4951 // Unable to commute.
4954 if (UncommutedMI != MI) {
4955 // New instruction. It doesn't need to be kept.
4956 UncommutedMI->eraseFromParent();
4960 // Return here to prevent duplicate fuse failure report.
4967 if (PrintFailedFusing && !MI->isCopy())
4968 dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
4972 /// Return true for all instructions that only update
4973 /// the first 32 or 64-bits of the destination register and leave the rest
4974 /// unmodified. This can be used to avoid folding loads if the instructions
4975 /// only update part of the destination register, and the non-updated part is
4976 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4977 /// instructions breaks the partial register dependency and it can improve
4978 /// performance. e.g.:
4980 /// movss (%rdi), %xmm0
4981 /// cvtss2sd %xmm0, %xmm0
4984 /// cvtss2sd (%rdi), %xmm0
4986 /// FIXME: This should be turned into a TSFlags.
4988 static bool hasPartialRegUpdate(unsigned Opcode) {
4990 case X86::CVTSI2SSrr:
4991 case X86::CVTSI2SSrm:
4992 case X86::CVTSI2SS64rr:
4993 case X86::CVTSI2SS64rm:
4994 case X86::CVTSI2SDrr:
4995 case X86::CVTSI2SDrm:
4996 case X86::CVTSI2SD64rr:
4997 case X86::CVTSI2SD64rm:
4998 case X86::CVTSD2SSrr:
4999 case X86::CVTSD2SSrm:
5000 case X86::Int_CVTSD2SSrr:
5001 case X86::Int_CVTSD2SSrm:
5002 case X86::CVTSS2SDrr:
5003 case X86::CVTSS2SDrm:
5004 case X86::Int_CVTSS2SDrr:
5005 case X86::Int_CVTSS2SDrm:
5008 case X86::RCPSSr_Int:
5009 case X86::RCPSSm_Int:
5012 case X86::ROUNDSDr_Int:
5015 case X86::ROUNDSSr_Int:
5018 case X86::RSQRTSSr_Int:
5019 case X86::RSQRTSSm_Int:
5022 case X86::SQRTSSr_Int:
5023 case X86::SQRTSSm_Int:
5026 case X86::SQRTSDr_Int:
5027 case X86::SQRTSDm_Int:
5034 /// Inform the ExeDepsFix pass how many idle
5035 /// instructions we would like before a partial register update.
5036 unsigned X86InstrInfo::
5037 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5038 const TargetRegisterInfo *TRI) const {
5039 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5042 // If MI is marked as reading Reg, the partial register update is wanted.
5043 const MachineOperand &MO = MI->getOperand(0);
5044 unsigned Reg = MO.getReg();
5045 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5046 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5049 if (MI->readsRegister(Reg, TRI))
5053 // If any of the preceding 16 instructions are reading Reg, insert a
5054 // dependency breaking instruction. The magic number is based on a few
5055 // Nehalem experiments.
5059 // Return true for any instruction the copies the high bits of the first source
5060 // operand into the unused high bits of the destination operand.
5061 static bool hasUndefRegUpdate(unsigned Opcode) {
5063 case X86::VCVTSI2SSrr:
5064 case X86::VCVTSI2SSrm:
5065 case X86::Int_VCVTSI2SSrr:
5066 case X86::Int_VCVTSI2SSrm:
5067 case X86::VCVTSI2SS64rr:
5068 case X86::VCVTSI2SS64rm:
5069 case X86::Int_VCVTSI2SS64rr:
5070 case X86::Int_VCVTSI2SS64rm:
5071 case X86::VCVTSI2SDrr:
5072 case X86::VCVTSI2SDrm:
5073 case X86::Int_VCVTSI2SDrr:
5074 case X86::Int_VCVTSI2SDrm:
5075 case X86::VCVTSI2SD64rr:
5076 case X86::VCVTSI2SD64rm:
5077 case X86::Int_VCVTSI2SD64rr:
5078 case X86::Int_VCVTSI2SD64rm:
5079 case X86::VCVTSD2SSrr:
5080 case X86::VCVTSD2SSrm:
5081 case X86::Int_VCVTSD2SSrr:
5082 case X86::Int_VCVTSD2SSrm:
5083 case X86::VCVTSS2SDrr:
5084 case X86::VCVTSS2SDrm:
5085 case X86::Int_VCVTSS2SDrr:
5086 case X86::Int_VCVTSS2SDrm:
5089 case X86::VRCPSSm_Int:
5090 case X86::VROUNDSDr:
5091 case X86::VROUNDSDm:
5092 case X86::VROUNDSDr_Int:
5093 case X86::VROUNDSSr:
5094 case X86::VROUNDSSm:
5095 case X86::VROUNDSSr_Int:
5096 case X86::VRSQRTSSr:
5097 case X86::VRSQRTSSm:
5098 case X86::VRSQRTSSm_Int:
5101 case X86::VSQRTSSm_Int:
5104 case X86::VSQRTSDm_Int:
5106 case X86::VCVTSD2SSZrr:
5107 case X86::VCVTSD2SSZrm:
5108 case X86::VCVTSS2SDZrr:
5109 case X86::VCVTSS2SDZrm:
5116 /// Inform the ExeDepsFix pass how many idle instructions we would like before
5117 /// certain undef register reads.
5119 /// This catches the VCVTSI2SD family of instructions:
5121 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
5123 /// We should to be careful *not* to catch VXOR idioms which are presumably
5124 /// handled specially in the pipeline:
5126 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
5128 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5129 /// high bits that are passed-through are not live.
5130 unsigned X86InstrInfo::
5131 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
5132 const TargetRegisterInfo *TRI) const {
5133 if (!hasUndefRegUpdate(MI->getOpcode()))
5136 // Set the OpNum parameter to the first source operand.
5139 const MachineOperand &MO = MI->getOperand(OpNum);
5140 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
5141 // Use the same magic number as getPartialRegUpdateClearance.
5148 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
5149 const TargetRegisterInfo *TRI) const {
5150 unsigned Reg = MI->getOperand(OpNum).getReg();
5151 // If MI kills this register, the false dependence is already broken.
5152 if (MI->killsRegister(Reg, TRI))
5154 if (X86::VR128RegClass.contains(Reg)) {
5155 // These instructions are all floating point domain, so xorps is the best
5157 bool HasAVX = Subtarget.hasAVX();
5158 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5159 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5160 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5161 } else if (X86::VR256RegClass.contains(Reg)) {
5162 // Use vxorps to clear the full ymm register.
5163 // It wants to read and write the xmm sub-register.
5164 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5165 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5166 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5167 .addReg(Reg, RegState::ImplicitDefine);
5170 MI->addRegisterKilled(Reg, TRI, true);
5173 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5174 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5175 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
5176 // Check switch flag
5177 if (NoFusing) return nullptr;
5179 // Unless optimizing for size, don't fold to avoid partial
5180 // register update stalls
5181 if (!MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
5182 hasPartialRegUpdate(MI->getOpcode()))
5185 const MachineFrameInfo *MFI = MF.getFrameInfo();
5186 unsigned Size = MFI->getObjectSize(FrameIndex);
5187 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
5188 // If the function stack isn't realigned we don't want to fold instructions
5189 // that need increased alignment.
5190 if (!RI.needsStackRealignment(MF))
5192 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5193 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5194 unsigned NewOpc = 0;
5195 unsigned RCSize = 0;
5196 switch (MI->getOpcode()) {
5197 default: return nullptr;
5198 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
5199 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5200 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5201 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5203 // Check if it's safe to fold the load. If the size of the object is
5204 // narrower than the load width, then it's not.
5207 // Change to CMPXXri r, 0 first.
5208 MI->setDesc(get(NewOpc));
5209 MI->getOperand(1).ChangeToImmediate(0);
5210 } else if (Ops.size() != 1)
5213 return foldMemoryOperandImpl(MF, MI, Ops[0],
5214 MachineOperand::CreateFI(FrameIndex), InsertPt,
5215 Size, Alignment, /*AllowCommute=*/true);
5218 static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
5219 const MachineFunction &MF) {
5220 unsigned Opc = LoadMI.getOpcode();
5222 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5224 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
5225 // These instructions only load 32 bits, we can't fold them if the
5226 // destination register is wider than 32 bits (4 bytes).
5229 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
5230 // These instructions only load 64 bits, we can't fold them if the
5231 // destination register is wider than 64 bits (8 bytes).
5237 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5238 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5239 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
5240 // If loading from a FrameIndex, fold directly from the FrameIndex.
5241 unsigned NumOps = LoadMI->getDesc().getNumOperands();
5243 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5244 if (isPartialRegisterLoad(*LoadMI, MF))
5246 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
5249 // Check switch flag
5250 if (NoFusing) return nullptr;
5252 // Unless optimizing for size, don't fold to avoid partial
5253 // register update stalls
5254 if (!MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
5255 hasPartialRegUpdate(MI->getOpcode()))
5258 // Determine the alignment of the load.
5259 unsigned Alignment = 0;
5260 if (LoadMI->hasOneMemOperand())
5261 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
5263 switch (LoadMI->getOpcode()) {
5264 case X86::AVX2_SETALLONES:
5269 case X86::V_SETALLONES:
5281 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5282 unsigned NewOpc = 0;
5283 switch (MI->getOpcode()) {
5284 default: return nullptr;
5285 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5286 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5287 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5288 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5290 // Change to CMPXXri r, 0 first.
5291 MI->setDesc(get(NewOpc));
5292 MI->getOperand(1).ChangeToImmediate(0);
5293 } else if (Ops.size() != 1)
5296 // Make sure the subregisters match.
5297 // Otherwise we risk changing the size of the load.
5298 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
5301 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5302 switch (LoadMI->getOpcode()) {
5304 case X86::V_SETALLONES:
5305 case X86::AVX2_SETALLONES:
5308 case X86::FsFLD0SS: {
5309 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5310 // Create a constant-pool entry and operands to load from it.
5312 // Medium and large mode can't fold loads this way.
5313 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5314 MF.getTarget().getCodeModel() != CodeModel::Kernel)
5317 // x86-32 PIC requires a PIC base register for constant pools.
5318 unsigned PICBase = 0;
5319 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
5320 if (Subtarget.is64Bit())
5323 // FIXME: PICBase = getGlobalBaseReg(&MF);
5324 // This doesn't work for several reasons.
5325 // 1. GlobalBaseReg may have been spilled.
5326 // 2. It may not be live at MI.
5330 // Create a constant-pool entry.
5331 MachineConstantPool &MCP = *MF.getConstantPool();
5333 unsigned Opc = LoadMI->getOpcode();
5334 if (Opc == X86::FsFLD0SS)
5335 Ty = Type::getFloatTy(MF.getFunction()->getContext());
5336 else if (Opc == X86::FsFLD0SD)
5337 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
5338 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
5339 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
5341 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
5343 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
5344 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5345 Constant::getNullValue(Ty);
5346 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5348 // Create operands to load from the constant pool entry.
5349 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5350 MOs.push_back(MachineOperand::CreateImm(1));
5351 MOs.push_back(MachineOperand::CreateReg(0, false));
5352 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5353 MOs.push_back(MachineOperand::CreateReg(0, false));
5357 if (isPartialRegisterLoad(*LoadMI, MF))
5360 // Folding a normal load. Just copy the load's address operands.
5361 MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
5362 LoadMI->operands_begin() + NumOps);
5366 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5367 /*Size=*/0, Alignment, /*AllowCommute=*/true);
5370 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
5371 ArrayRef<unsigned> Ops) const {
5372 // Check switch flag
5373 if (NoFusing) return 0;
5375 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5376 switch (MI->getOpcode()) {
5377 default: return false;
5384 // FIXME: AsmPrinter doesn't know how to handle
5385 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5386 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5392 if (Ops.size() != 1)
5395 unsigned OpNum = Ops[0];
5396 unsigned Opc = MI->getOpcode();
5397 unsigned NumOps = MI->getDesc().getNumOperands();
5398 bool isTwoAddr = NumOps > 1 &&
5399 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5401 // Folding a memory location into the two-address part of a two-address
5402 // instruction is different than folding it other places. It requires
5403 // replacing the *two* registers with the memory location.
5404 const DenseMap<unsigned,
5405 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
5406 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
5407 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5408 } else if (OpNum == 0) {
5409 if (Opc == X86::MOV32r0)
5412 OpcodeTablePtr = &RegOp2MemOpTable0;
5413 } else if (OpNum == 1) {
5414 OpcodeTablePtr = &RegOp2MemOpTable1;
5415 } else if (OpNum == 2) {
5416 OpcodeTablePtr = &RegOp2MemOpTable2;
5417 } else if (OpNum == 3) {
5418 OpcodeTablePtr = &RegOp2MemOpTable3;
5421 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
5423 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
5426 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5427 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
5428 SmallVectorImpl<MachineInstr*> &NewMIs) const {
5429 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5430 MemOp2RegOpTable.find(MI->getOpcode());
5431 if (I == MemOp2RegOpTable.end())
5433 unsigned Opc = I->second.first;
5434 unsigned Index = I->second.second & TB_INDEX_MASK;
5435 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5436 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5437 if (UnfoldLoad && !FoldedLoad)
5439 UnfoldLoad &= FoldedLoad;
5440 if (UnfoldStore && !FoldedStore)
5442 UnfoldStore &= FoldedStore;
5444 const MCInstrDesc &MCID = get(Opc);
5445 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5446 if (!MI->hasOneMemOperand() &&
5447 RC == &X86::VR128RegClass &&
5448 !Subtarget.isUnalignedMemAccessFast())
5449 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5450 // conservatively assume the address is unaligned. That's bad for
5453 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5454 SmallVector<MachineOperand,2> BeforeOps;
5455 SmallVector<MachineOperand,2> AfterOps;
5456 SmallVector<MachineOperand,4> ImpOps;
5457 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5458 MachineOperand &Op = MI->getOperand(i);
5459 if (i >= Index && i < Index + X86::AddrNumOperands)
5460 AddrOps.push_back(Op);
5461 else if (Op.isReg() && Op.isImplicit())
5462 ImpOps.push_back(Op);
5464 BeforeOps.push_back(Op);
5466 AfterOps.push_back(Op);
5469 // Emit the load instruction.
5471 std::pair<MachineInstr::mmo_iterator,
5472 MachineInstr::mmo_iterator> MMOs =
5473 MF.extractLoadMemRefs(MI->memoperands_begin(),
5474 MI->memoperands_end());
5475 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
5477 // Address operands cannot be marked isKill.
5478 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5479 MachineOperand &MO = NewMIs[0]->getOperand(i);
5481 MO.setIsKill(false);
5486 // Emit the data processing instruction.
5487 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
5488 MachineInstrBuilder MIB(MF, DataMI);
5491 MIB.addReg(Reg, RegState::Define);
5492 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
5493 MIB.addOperand(BeforeOps[i]);
5496 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
5497 MIB.addOperand(AfterOps[i]);
5498 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5499 MachineOperand &MO = ImpOps[i];
5500 MIB.addReg(MO.getReg(),
5501 getDefRegState(MO.isDef()) |
5502 RegState::Implicit |
5503 getKillRegState(MO.isKill()) |
5504 getDeadRegState(MO.isDead()) |
5505 getUndefRegState(MO.isUndef()));
5507 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5508 switch (DataMI->getOpcode()) {
5510 case X86::CMP64ri32:
5517 MachineOperand &MO0 = DataMI->getOperand(0);
5518 MachineOperand &MO1 = DataMI->getOperand(1);
5519 if (MO1.getImm() == 0) {
5521 switch (DataMI->getOpcode()) {
5522 default: llvm_unreachable("Unreachable!");
5524 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5526 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5528 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5529 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5531 DataMI->setDesc(get(NewOpc));
5532 MO1.ChangeToRegister(MO0.getReg(), false);
5536 NewMIs.push_back(DataMI);
5538 // Emit the store instruction.
5540 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5541 std::pair<MachineInstr::mmo_iterator,
5542 MachineInstr::mmo_iterator> MMOs =
5543 MF.extractStoreMemRefs(MI->memoperands_begin(),
5544 MI->memoperands_end());
5545 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
5552 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5553 SmallVectorImpl<SDNode*> &NewNodes) const {
5554 if (!N->isMachineOpcode())
5557 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5558 MemOp2RegOpTable.find(N->getMachineOpcode());
5559 if (I == MemOp2RegOpTable.end())
5561 unsigned Opc = I->second.first;
5562 unsigned Index = I->second.second & TB_INDEX_MASK;
5563 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5564 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5565 const MCInstrDesc &MCID = get(Opc);
5566 MachineFunction &MF = DAG.getMachineFunction();
5567 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5568 unsigned NumDefs = MCID.NumDefs;
5569 std::vector<SDValue> AddrOps;
5570 std::vector<SDValue> BeforeOps;
5571 std::vector<SDValue> AfterOps;
5573 unsigned NumOps = N->getNumOperands();
5574 for (unsigned i = 0; i != NumOps-1; ++i) {
5575 SDValue Op = N->getOperand(i);
5576 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5577 AddrOps.push_back(Op);
5578 else if (i < Index-NumDefs)
5579 BeforeOps.push_back(Op);
5580 else if (i > Index-NumDefs)
5581 AfterOps.push_back(Op);
5583 SDValue Chain = N->getOperand(NumOps-1);
5584 AddrOps.push_back(Chain);
5586 // Emit the load instruction.
5587 SDNode *Load = nullptr;
5589 EVT VT = *RC->vt_begin();
5590 std::pair<MachineInstr::mmo_iterator,
5591 MachineInstr::mmo_iterator> MMOs =
5592 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5593 cast<MachineSDNode>(N)->memoperands_end());
5594 if (!(*MMOs.first) &&
5595 RC == &X86::VR128RegClass &&
5596 !Subtarget.isUnalignedMemAccessFast())
5597 // Do not introduce a slow unaligned load.
5599 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5600 bool isAligned = (*MMOs.first) &&
5601 (*MMOs.first)->getAlignment() >= Alignment;
5602 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5603 VT, MVT::Other, AddrOps);
5604 NewNodes.push_back(Load);
5606 // Preserve memory reference information.
5607 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5610 // Emit the data processing instruction.
5611 std::vector<EVT> VTs;
5612 const TargetRegisterClass *DstRC = nullptr;
5613 if (MCID.getNumDefs() > 0) {
5614 DstRC = getRegClass(MCID, 0, &RI, MF);
5615 VTs.push_back(*DstRC->vt_begin());
5617 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5618 EVT VT = N->getValueType(i);
5619 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5623 BeforeOps.push_back(SDValue(Load, 0));
5624 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5625 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5626 NewNodes.push_back(NewNode);
5628 // Emit the store instruction.
5631 AddrOps.push_back(SDValue(NewNode, 0));
5632 AddrOps.push_back(Chain);
5633 std::pair<MachineInstr::mmo_iterator,
5634 MachineInstr::mmo_iterator> MMOs =
5635 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5636 cast<MachineSDNode>(N)->memoperands_end());
5637 if (!(*MMOs.first) &&
5638 RC == &X86::VR128RegClass &&
5639 !Subtarget.isUnalignedMemAccessFast())
5640 // Do not introduce a slow unaligned store.
5642 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5643 bool isAligned = (*MMOs.first) &&
5644 (*MMOs.first)->getAlignment() >= Alignment;
5646 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5647 dl, MVT::Other, AddrOps);
5648 NewNodes.push_back(Store);
5650 // Preserve memory reference information.
5651 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
5657 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5658 bool UnfoldLoad, bool UnfoldStore,
5659 unsigned *LoadRegIndex) const {
5660 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5661 MemOp2RegOpTable.find(Opc);
5662 if (I == MemOp2RegOpTable.end())
5664 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5665 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5666 if (UnfoldLoad && !FoldedLoad)
5668 if (UnfoldStore && !FoldedStore)
5671 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
5672 return I->second.first;
5676 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5677 int64_t &Offset1, int64_t &Offset2) const {
5678 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5680 unsigned Opc1 = Load1->getMachineOpcode();
5681 unsigned Opc2 = Load2->getMachineOpcode();
5683 default: return false;
5693 case X86::MMX_MOVD64rm:
5694 case X86::MMX_MOVQ64rm:
5695 case X86::FsMOVAPSrm:
5696 case X86::FsMOVAPDrm:
5702 // AVX load instructions
5705 case X86::FsVMOVAPSrm:
5706 case X86::FsVMOVAPDrm:
5707 case X86::VMOVAPSrm:
5708 case X86::VMOVUPSrm:
5709 case X86::VMOVAPDrm:
5710 case X86::VMOVDQArm:
5711 case X86::VMOVDQUrm:
5712 case X86::VMOVAPSYrm:
5713 case X86::VMOVUPSYrm:
5714 case X86::VMOVAPDYrm:
5715 case X86::VMOVDQAYrm:
5716 case X86::VMOVDQUYrm:
5720 default: return false;
5730 case X86::MMX_MOVD64rm:
5731 case X86::MMX_MOVQ64rm:
5732 case X86::FsMOVAPSrm:
5733 case X86::FsMOVAPDrm:
5739 // AVX load instructions
5742 case X86::FsVMOVAPSrm:
5743 case X86::FsVMOVAPDrm:
5744 case X86::VMOVAPSrm:
5745 case X86::VMOVUPSrm:
5746 case X86::VMOVAPDrm:
5747 case X86::VMOVDQArm:
5748 case X86::VMOVDQUrm:
5749 case X86::VMOVAPSYrm:
5750 case X86::VMOVUPSYrm:
5751 case X86::VMOVAPDYrm:
5752 case X86::VMOVDQAYrm:
5753 case X86::VMOVDQUYrm:
5757 // Check if chain operands and base addresses match.
5758 if (Load1->getOperand(0) != Load2->getOperand(0) ||
5759 Load1->getOperand(5) != Load2->getOperand(5))
5761 // Segment operands should match as well.
5762 if (Load1->getOperand(4) != Load2->getOperand(4))
5764 // Scale should be 1, Index should be Reg0.
5765 if (Load1->getOperand(1) == Load2->getOperand(1) &&
5766 Load1->getOperand(2) == Load2->getOperand(2)) {
5767 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5770 // Now let's examine the displacements.
5771 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5772 isa<ConstantSDNode>(Load2->getOperand(3))) {
5773 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5774 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5781 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5782 int64_t Offset1, int64_t Offset2,
5783 unsigned NumLoads) const {
5784 assert(Offset2 > Offset1);
5785 if ((Offset2 - Offset1) / 8 > 64)
5788 unsigned Opc1 = Load1->getMachineOpcode();
5789 unsigned Opc2 = Load2->getMachineOpcode();
5791 return false; // FIXME: overly conservative?
5798 case X86::MMX_MOVD64rm:
5799 case X86::MMX_MOVQ64rm:
5803 EVT VT = Load1->getValueType(0);
5804 switch (VT.getSimpleVT().SimpleTy) {
5806 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5807 // have 16 of them to play with.
5808 if (Subtarget.is64Bit()) {
5811 } else if (NumLoads) {
5829 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5830 MachineInstr *Second) const {
5831 // Check if this processor supports macro-fusion. Since this is a minor
5832 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5833 // proxy for SandyBridge+.
5834 if (!Subtarget.hasAVX())
5843 switch(Second->getOpcode()) {
5866 FuseKind = FuseTest;
5869 switch (First->getOpcode()) {
5879 case X86::TEST32i32:
5880 case X86::TEST64i32:
5881 case X86::TEST64ri32:
5886 case X86::TEST8ri_NOREX:
5898 case X86::AND64ri32:
5918 case X86::CMP64ri32:
5929 case X86::ADD16ri8_DB:
5930 case X86::ADD16ri_DB:
5933 case X86::ADD16rr_DB:
5937 case X86::ADD32ri8_DB:
5938 case X86::ADD32ri_DB:
5941 case X86::ADD32rr_DB:
5943 case X86::ADD64ri32:
5944 case X86::ADD64ri32_DB:
5946 case X86::ADD64ri8_DB:
5949 case X86::ADD64rr_DB:
5967 case X86::SUB64ri32:
5975 return FuseKind == FuseCmp || FuseKind == FuseInc;
5984 return FuseKind == FuseInc;
5989 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5990 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5991 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5992 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5994 Cond[0].setImm(GetOppositeBranchCondition(CC));
5999 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6000 // FIXME: Return false for x87 stack register classes for now. We can't
6001 // allow any loads of these registers before FpGet_ST0_80.
6002 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6003 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6006 /// Return a virtual register initialized with the
6007 /// the global base register value. Output instructions required to
6008 /// initialize the register in the function entry block, if necessary.
6010 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6012 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6013 assert(!Subtarget.is64Bit() &&
6014 "X86-64 PIC uses RIP relative addressing");
6016 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6017 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6018 if (GlobalBaseReg != 0)
6019 return GlobalBaseReg;
6021 // Create the register. The code to initialize it is inserted
6022 // later, by the CGBR pass (below).
6023 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6024 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6025 X86FI->setGlobalBaseReg(GlobalBaseReg);
6026 return GlobalBaseReg;
6029 // These are the replaceable SSE instructions. Some of these have Int variants
6030 // that we don't include here. We don't want to replace instructions selected
6032 static const uint16_t ReplaceableInstrs[][3] = {
6033 //PackedSingle PackedDouble PackedInt
6034 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6035 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6036 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6037 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6038 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
6039 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
6040 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6041 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6042 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6043 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6044 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6045 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6046 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6047 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6048 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
6049 // AVX 128-bit support
6050 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6051 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6052 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6053 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6054 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
6055 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
6056 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6057 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6058 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6059 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6060 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6061 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6062 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
6063 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6064 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
6065 // AVX 256-bit support
6066 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6067 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
6068 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
6069 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
6070 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
6071 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
6074 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6075 //PackedSingle PackedDouble PackedInt
6076 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6077 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6078 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6079 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6080 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6081 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6082 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
6083 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6084 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6085 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6086 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6087 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6088 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
6089 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6090 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6091 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6092 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6093 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6094 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6095 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
6098 // FIXME: Some shuffle and unpack instructions have equivalents in different
6099 // domains, but they require a bit more work than just switching opcodes.
6101 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
6102 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
6103 if (ReplaceableInstrs[i][domain-1] == opcode)
6104 return ReplaceableInstrs[i];
6108 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
6109 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
6110 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
6111 return ReplaceableInstrsAVX2[i];
6115 std::pair<uint16_t, uint16_t>
6116 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
6117 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6118 bool hasAVX2 = Subtarget.hasAVX2();
6119 uint16_t validDomains = 0;
6120 if (domain && lookup(MI->getOpcode(), domain))
6122 else if (domain && lookupAVX2(MI->getOpcode(), domain))
6123 validDomains = hasAVX2 ? 0xe : 0x6;
6124 return std::make_pair(domain, validDomains);
6127 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
6128 assert(Domain>0 && Domain<4 && "Invalid execution domain");
6129 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6130 assert(dom && "Not an SSE instruction");
6131 const uint16_t *table = lookup(MI->getOpcode(), dom);
6132 if (!table) { // try the other table
6133 assert((Subtarget.hasAVX2() || Domain < 3) &&
6134 "256-bit vector operations only available in AVX2");
6135 table = lookupAVX2(MI->getOpcode(), dom);
6137 assert(table && "Cannot change domain");
6138 MI->setDesc(get(table[Domain-1]));
6141 /// Return the noop instruction to use for a noop.
6142 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
6143 NopInst.setOpcode(X86::NOOP);
6146 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6147 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6148 // on the encoding lengths of the instructions generated by
6149 // getUnconditionalBranch and getTrap.
6150 void X86InstrInfo::getUnconditionalBranch(
6151 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
6152 Branch.setOpcode(X86::JMP_1);
6153 Branch.addOperand(MCOperand::createExpr(BranchTarget));
6156 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6157 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6158 // on the encoding lengths of the instructions generated by
6159 // getUnconditionalBranch and getTrap.
6160 void X86InstrInfo::getTrap(MCInst &MI) const {
6161 MI.setOpcode(X86::TRAP);
6164 // See getTrap and getUnconditionalBranch for conditions on the value returned
6165 // by this function.
6166 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6167 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6168 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6172 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6174 default: return false;
6176 case X86::DIVSDrm_Int:
6178 case X86::DIVSDrr_Int:
6180 case X86::DIVSSrm_Int:
6182 case X86::DIVSSrr_Int:
6188 case X86::SQRTSDm_Int:
6190 case X86::SQRTSDr_Int:
6192 case X86::SQRTSSm_Int:
6194 case X86::SQRTSSr_Int:
6195 // AVX instructions with high latency
6197 case X86::VDIVSDrm_Int:
6199 case X86::VDIVSDrr_Int:
6201 case X86::VDIVSSrm_Int:
6203 case X86::VDIVSSrr_Int:
6209 case X86::VSQRTSDm_Int:
6212 case X86::VSQRTSSm_Int:
6214 case X86::VSQRTPDZm:
6215 case X86::VSQRTPDZr:
6216 case X86::VSQRTPSZm:
6217 case X86::VSQRTPSZr:
6218 case X86::VSQRTSDZm:
6219 case X86::VSQRTSDZm_Int:
6220 case X86::VSQRTSDZr:
6221 case X86::VSQRTSSZm_Int:
6222 case X86::VSQRTSSZr:
6223 case X86::VSQRTSSZm:
6224 case X86::VDIVSDZrm:
6225 case X86::VDIVSDZrr:
6226 case X86::VDIVSSZrm:
6227 case X86::VDIVSSZrr:
6229 case X86::VGATHERQPSZrm:
6230 case X86::VGATHERQPDZrm:
6231 case X86::VGATHERDPDZrm:
6232 case X86::VGATHERDPSZrm:
6233 case X86::VPGATHERQDZrm:
6234 case X86::VPGATHERQQZrm:
6235 case X86::VPGATHERDDZrm:
6236 case X86::VPGATHERDQZrm:
6237 case X86::VSCATTERQPDZmr:
6238 case X86::VSCATTERQPSZmr:
6239 case X86::VSCATTERDPDZmr:
6240 case X86::VSCATTERDPSZmr:
6241 case X86::VPSCATTERQDZmr:
6242 case X86::VPSCATTERQQZmr:
6243 case X86::VPSCATTERDDZmr:
6244 case X86::VPSCATTERDQZmr:
6250 hasHighOperandLatency(const TargetSchedModel &SchedModel,
6251 const MachineRegisterInfo *MRI,
6252 const MachineInstr *DefMI, unsigned DefIdx,
6253 const MachineInstr *UseMI, unsigned UseIdx) const {
6254 return isHighLatencyDef(DefMI->getOpcode());
6257 /// If the input instruction is part of a chain of dependent ops that are
6258 /// suitable for reassociation, return the earlier instruction in the sequence
6259 /// that defines its first operand, otherwise return a nullptr.
6260 /// If the instruction's operands must be commuted to be considered a
6261 /// reassociation candidate, Commuted will be set to true.
6262 static MachineInstr *isReassocCandidate(const MachineInstr &Inst,
6263 unsigned AssocOpcode,
6264 bool checkPrevOneUse,
6266 if (Inst.getOpcode() != AssocOpcode)
6269 MachineOperand Op1 = Inst.getOperand(1);
6270 MachineOperand Op2 = Inst.getOperand(2);
6272 const MachineBasicBlock *MBB = Inst.getParent();
6273 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
6275 // We need virtual register definitions.
6276 MachineInstr *MI1 = nullptr;
6277 MachineInstr *MI2 = nullptr;
6278 if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
6279 MI1 = MRI.getUniqueVRegDef(Op1.getReg());
6280 if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
6281 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
6283 // And they need to be in the trace (otherwise, they won't have a depth).
6284 if (!MI1 || !MI2 || MI1->getParent() != MBB || MI2->getParent() != MBB)
6288 if (MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode) {
6289 std::swap(MI1, MI2);
6293 // Avoid reassociating operands when it won't provide any benefit. If both
6294 // operands are produced by instructions of this type, we may already
6295 // have the optimal sequence.
6296 if (MI2->getOpcode() == AssocOpcode)
6299 // The instruction must only be used by the other instruction that we
6300 // reassociate with.
6301 if (checkPrevOneUse && !MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()))
6304 // We must match a simple chain of dependent ops.
6305 // TODO: This check is not necessary for the earliest instruction in the
6306 // sequence. Instead of a sequence of 3 dependent instructions with the same
6307 // opcode, we only need to find a sequence of 2 dependent instructions with
6308 // the same opcode plus 1 other instruction that adds to the height of the
6310 if (MI1->getOpcode() != AssocOpcode)
6316 /// Select a pattern based on how the operands of each associative operation
6317 /// need to be commuted.
6318 static MachineCombinerPattern::MC_PATTERN getPattern(bool CommutePrev,
6322 return MachineCombinerPattern::MC_REASSOC_XA_YB;
6323 return MachineCombinerPattern::MC_REASSOC_XA_BY;
6326 return MachineCombinerPattern::MC_REASSOC_AX_YB;
6327 return MachineCombinerPattern::MC_REASSOC_AX_BY;
6331 bool X86InstrInfo::hasPattern(MachineInstr &Root,
6332 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
6333 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
6336 // TODO: There are many more associative instruction types to match:
6337 // 1. Other forms of scalar FP add (non-AVX)
6338 // 2. Other data types (double, integer, vectors)
6339 // 3. Other math / logic operations (mul, and, or)
6340 unsigned AssocOpcode = X86::VADDSSrr;
6342 // TODO: There is nothing x86-specific here except the instruction type.
6343 // This logic could be hoisted into the machine combiner pass itself.
6345 if (MachineInstr *Prev = isReassocCandidate(Root, AssocOpcode, true,
6348 if (isReassocCandidate(*Prev, AssocOpcode, false, CommutePrev)) {
6349 // We found a sequence of instructions that may be suitable for a
6350 // reassociation of operands to increase ILP.
6351 Pattern.push_back(getPattern(CommutePrev, CommuteRoot));
6359 /// Attempt the following reassociation to reduce critical path length:
6360 /// B = A op X (Prev)
6361 /// C = B op Y (Root)
6365 static void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
6366 MachineCombinerPattern::MC_PATTERN Pattern,
6367 SmallVectorImpl<MachineInstr *> &InsInstrs,
6368 SmallVectorImpl<MachineInstr *> &DelInstrs,
6369 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
6370 MachineFunction *MF = Root.getParent()->getParent();
6371 MachineRegisterInfo &MRI = MF->getRegInfo();
6372 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
6373 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
6374 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
6376 // This array encodes the operand index for each parameter because the
6377 // operands may be commuted. Each row corresponds to a pattern value,
6378 // and each column specifies the index of A, B, X, Y.
6379 unsigned OpIdx[4][4] = {
6386 MachineOperand &OpA = Prev.getOperand(OpIdx[Pattern][0]);
6387 MachineOperand &OpB = Root.getOperand(OpIdx[Pattern][1]);
6388 MachineOperand &OpX = Prev.getOperand(OpIdx[Pattern][2]);
6389 MachineOperand &OpY = Root.getOperand(OpIdx[Pattern][3]);
6390 MachineOperand &OpC = Root.getOperand(0);
6392 unsigned RegA = OpA.getReg();
6393 unsigned RegB = OpB.getReg();
6394 unsigned RegX = OpX.getReg();
6395 unsigned RegY = OpY.getReg();
6396 unsigned RegC = OpC.getReg();
6398 if (TargetRegisterInfo::isVirtualRegister(RegA))
6399 MRI.constrainRegClass(RegA, RC);
6400 if (TargetRegisterInfo::isVirtualRegister(RegB))
6401 MRI.constrainRegClass(RegB, RC);
6402 if (TargetRegisterInfo::isVirtualRegister(RegX))
6403 MRI.constrainRegClass(RegX, RC);
6404 if (TargetRegisterInfo::isVirtualRegister(RegY))
6405 MRI.constrainRegClass(RegY, RC);
6406 if (TargetRegisterInfo::isVirtualRegister(RegC))
6407 MRI.constrainRegClass(RegC, RC);
6409 // Create a new virtual register for the result of (X op Y) instead of
6410 // recycling RegB because the MachineCombiner's computation of the critical
6411 // path requires a new register definition rather than an existing one.
6412 unsigned NewVR = MRI.createVirtualRegister(RC);
6413 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
6415 unsigned Opcode = Root.getOpcode();
6416 bool KillA = OpA.isKill();
6417 bool KillX = OpX.isKill();
6418 bool KillY = OpY.isKill();
6420 // Create new instructions for insertion.
6421 MachineInstrBuilder MIB1 =
6422 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
6423 .addReg(RegX, getKillRegState(KillX))
6424 .addReg(RegY, getKillRegState(KillY));
6425 InsInstrs.push_back(MIB1);
6427 MachineInstrBuilder MIB2 =
6428 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
6429 .addReg(RegA, getKillRegState(KillA))
6430 .addReg(NewVR, getKillRegState(true));
6431 InsInstrs.push_back(MIB2);
6433 // Record old instructions for deletion.
6434 DelInstrs.push_back(&Prev);
6435 DelInstrs.push_back(&Root);
6438 void X86InstrInfo::genAlternativeCodeSequence(
6440 MachineCombinerPattern::MC_PATTERN Pattern,
6441 SmallVectorImpl<MachineInstr *> &InsInstrs,
6442 SmallVectorImpl<MachineInstr *> &DelInstrs,
6443 DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
6444 MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
6446 // Select the previous instruction in the sequence based on the input pattern.
6447 MachineInstr *Prev = nullptr;
6448 if (Pattern == MachineCombinerPattern::MC_REASSOC_AX_BY ||
6449 Pattern == MachineCombinerPattern::MC_REASSOC_XA_BY)
6450 Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
6451 else if (Pattern == MachineCombinerPattern::MC_REASSOC_AX_YB ||
6452 Pattern == MachineCombinerPattern::MC_REASSOC_XA_YB)
6453 Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
6455 llvm_unreachable("Unknown pattern for machine combiner");
6457 reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
6462 /// Create Global Base Reg pass. This initializes the PIC
6463 /// global base register for x86-32.
6464 struct CGBR : public MachineFunctionPass {
6466 CGBR() : MachineFunctionPass(ID) {}
6468 bool runOnMachineFunction(MachineFunction &MF) override {
6469 const X86TargetMachine *TM =
6470 static_cast<const X86TargetMachine *>(&MF.getTarget());
6471 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
6473 // Don't do anything if this is 64-bit as 64-bit PIC
6474 // uses RIP relative addressing.
6478 // Only emit a global base reg in PIC mode.
6479 if (TM->getRelocationModel() != Reloc::PIC_)
6482 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
6483 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6485 // If we didn't need a GlobalBaseReg, don't insert code.
6486 if (GlobalBaseReg == 0)
6489 // Insert the set of GlobalBaseReg into the first MBB of the function
6490 MachineBasicBlock &FirstMBB = MF.front();
6491 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
6492 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
6493 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6494 const X86InstrInfo *TII = STI.getInstrInfo();
6497 if (STI.isPICStyleGOT())
6498 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
6502 // Operand of MovePCtoStack is completely ignored by asm printer. It's
6503 // only used in JIT code emission as displacement to pc.
6504 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
6506 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
6507 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
6508 if (STI.isPICStyleGOT()) {
6509 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
6510 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
6511 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
6512 X86II::MO_GOT_ABSOLUTE_ADDRESS);
6518 const char *getPassName() const override {
6519 return "X86 PIC Global Base Reg Initialization";
6522 void getAnalysisUsage(AnalysisUsage &AU) const override {
6523 AU.setPreservesCFG();
6524 MachineFunctionPass::getAnalysisUsage(AU);
6531 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
6534 struct LDTLSCleanup : public MachineFunctionPass {
6536 LDTLSCleanup() : MachineFunctionPass(ID) {}
6538 bool runOnMachineFunction(MachineFunction &MF) override {
6539 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
6540 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
6541 // No point folding accesses if there isn't at least two.
6545 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
6546 return VisitNode(DT->getRootNode(), 0);
6549 // Visit the dominator subtree rooted at Node in pre-order.
6550 // If TLSBaseAddrReg is non-null, then use that to replace any
6551 // TLS_base_addr instructions. Otherwise, create the register
6552 // when the first such instruction is seen, and then use it
6553 // as we encounter more instructions.
6554 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
6555 MachineBasicBlock *BB = Node->getBlock();
6556 bool Changed = false;
6558 // Traverse the current block.
6559 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
6561 switch (I->getOpcode()) {
6562 case X86::TLS_base_addr32:
6563 case X86::TLS_base_addr64:
6565 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
6567 I = SetRegister(I, &TLSBaseAddrReg);
6575 // Visit the children of this block in the dominator tree.
6576 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
6578 Changed |= VisitNode(*I, TLSBaseAddrReg);
6584 // Replace the TLS_base_addr instruction I with a copy from
6585 // TLSBaseAddrReg, returning the new instruction.
6586 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
6587 unsigned TLSBaseAddrReg) {
6588 MachineFunction *MF = I->getParent()->getParent();
6589 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6590 const bool is64Bit = STI.is64Bit();
6591 const X86InstrInfo *TII = STI.getInstrInfo();
6593 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
6594 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
6595 TII->get(TargetOpcode::COPY),
6596 is64Bit ? X86::RAX : X86::EAX)
6597 .addReg(TLSBaseAddrReg);
6599 // Erase the TLS_base_addr instruction.
6600 I->eraseFromParent();
6605 // Create a virtal register in *TLSBaseAddrReg, and populate it by
6606 // inserting a copy instruction after I. Returns the new instruction.
6607 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
6608 MachineFunction *MF = I->getParent()->getParent();
6609 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6610 const bool is64Bit = STI.is64Bit();
6611 const X86InstrInfo *TII = STI.getInstrInfo();
6613 // Create a virtual register for the TLS base address.
6614 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6615 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
6616 ? &X86::GR64RegClass
6617 : &X86::GR32RegClass);
6619 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
6620 MachineInstr *Next = I->getNextNode();
6621 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
6622 TII->get(TargetOpcode::COPY),
6624 .addReg(is64Bit ? X86::RAX : X86::EAX);
6629 const char *getPassName() const override {
6630 return "Local Dynamic TLS Access Clean-up";
6633 void getAnalysisUsage(AnalysisUsage &AU) const override {
6634 AU.setPreservesCFG();
6635 AU.addRequired<MachineDominatorTree>();
6636 MachineFunctionPass::getAnalysisUsage(AU);
6641 char LDTLSCleanup::ID = 0;
6643 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
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