1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
41 def SDTX86CmpTestSae : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
42 SDTCisSameAs<1, 2>, SDTCisInt<3>]>;
44 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
45 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
47 // Commutative and Associative FMIN and FMAX.
48 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
50 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
51 [SDNPCommutative, SDNPAssociative]>;
53 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
60 [SDNPCommutative, SDNPAssociative]>;
61 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
62 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
63 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>;
64 def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>;
65 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
66 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
67 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
68 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
69 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
70 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
71 def X86comiSae : SDNode<"X86ISD::COMI", SDTX86CmpTestSae>;
72 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
73 def X86ucomiSae: SDNode<"X86ISD::UCOMI", SDTX86CmpTestSae>;
74 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
75 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
76 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
77 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
78 SDTCisVT<1, v4i32>]>>;
79 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
80 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
81 SDTCisVT<1, v4i32>]>>;
82 def X86pshufb : SDNode<"X86ISD::PSHUFB",
83 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
85 def X86psadbw : SDNode<"X86ISD::PSADBW",
86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
89 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
90 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
91 def X86andnp : SDNode<"X86ISD::ANDNP",
92 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
94 def X86psign : SDNode<"X86ISD::PSIGN",
95 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
97 def X86pextrb : SDNode<"X86ISD::PEXTRB",
98 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
99 def X86pextrw : SDNode<"X86ISD::PEXTRW",
100 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
101 def X86pinsrb : SDNode<"X86ISD::PINSRB",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
103 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
104 def X86pinsrw : SDNode<"X86ISD::PINSRW",
105 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
106 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
107 def X86insertps : SDNode<"X86ISD::INSERTPS",
108 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
109 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
110 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
111 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
113 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
114 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
116 def X86vzext : SDNode<"X86ISD::VZEXT",
117 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
118 SDTCisInt<0>, SDTCisInt<1>,
119 SDTCisOpSmallerThanOp<1, 0>]>>;
121 def X86vsext : SDNode<"X86ISD::VSEXT",
122 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
123 SDTCisInt<0>, SDTCisInt<1>,
124 SDTCisOpSmallerThanOp<1, 0>]>>;
126 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
127 SDTCisInt<0>, SDTCisInt<1>,
128 SDTCisOpSmallerThanOp<0, 1>]>;
130 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
131 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
132 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
134 def X86trunc : SDNode<"X86ISD::TRUNC",
135 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
136 SDTCisOpSmallerThanOp<0, 1>]>>;
137 def X86vfpext : SDNode<"X86ISD::VFPEXT",
138 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
139 SDTCisFP<0>, SDTCisFP<1>,
140 SDTCisOpSmallerThanOp<1, 0>]>>;
141 def X86vfpround: SDNode<"X86ISD::VFPROUND",
142 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
143 SDTCisFP<0>, SDTCisFP<1>,
144 SDTCisOpSmallerThanOp<0, 1>]>>;
146 def X86fround: SDNode<"X86ISD::VFPROUND",
147 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
148 SDTCVecEltisVT<0, f32>,
149 SDTCVecEltisVT<1, f64>,
150 SDTCVecEltisVT<2, f64>,
151 SDTCisOpSmallerThanOp<0, 1>]>>;
152 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
153 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
154 SDTCVecEltisVT<0, f32>,
155 SDTCVecEltisVT<1, f64>,
156 SDTCVecEltisVT<2, f64>,
157 SDTCisOpSmallerThanOp<0, 1>,
160 def X86fpext : SDNode<"X86ISD::VFPEXT",
161 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
162 SDTCVecEltisVT<0, f64>,
163 SDTCVecEltisVT<1, f32>,
164 SDTCVecEltisVT<2, f32>,
165 SDTCisOpSmallerThanOp<1, 0>]>>;
167 def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
168 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
169 SDTCVecEltisVT<0, f64>,
170 SDTCVecEltisVT<1, f32>,
171 SDTCVecEltisVT<2, f32>,
172 SDTCisOpSmallerThanOp<1, 0>,
175 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
176 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
177 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
178 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
179 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
181 def X86IntCmpMask : SDTypeProfile<1, 2,
182 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
183 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
184 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
187 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
188 SDTCisVec<1>, SDTCisSameAs<2, 1>,
189 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
190 def X86CmpMaskCCRound :
191 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
192 SDTCisVec<1>, SDTCisSameAs<2, 1>,
193 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
195 def X86CmpMaskCCScalar :
196 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
198 def X86CmpMaskCCScalarRound :
199 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
202 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
203 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
204 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
205 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
206 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalarRound>;
208 def X86vshl : SDNode<"X86ISD::VSHL",
209 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
211 def X86vsrl : SDNode<"X86ISD::VSRL",
212 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 def X86vsra : SDNode<"X86ISD::VSRA",
215 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
218 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
219 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
220 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
222 def X86vprot : SDNode<"X86ISD::VPROT",
223 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
225 def X86vproti : SDNode<"X86ISD::VPROTI",
226 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
229 def X86vpshl : SDNode<"X86ISD::VPSHL",
230 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
232 def X86vpsha : SDNode<"X86ISD::VPSHA",
233 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
236 def X86vpcom : SDNode<"X86ISD::VPCOM",
237 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
238 SDTCisVec<2>, SDTCisVT<3, i8>]>>;
239 def X86vpcomu : SDNode<"X86ISD::VPCOMU",
240 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
241 SDTCisVec<2>, SDTCisVT<3, i8>]>>;
243 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
245 SDTCisSameAs<2, 1>]>;
246 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
247 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
248 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
249 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
250 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
251 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
252 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
253 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
254 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
255 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
256 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
257 SDTCisVec<1>, SDTCisSameAs<2, 1>,
258 SDTCVecEltisVT<0, i1>,
259 SDTCisSameNumEltsAs<0, 1>]>>;
260 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
261 SDTCisVec<1>, SDTCisSameAs<2, 1>,
262 SDTCVecEltisVT<0, i1>,
263 SDTCisSameNumEltsAs<0, 1>]>>;
264 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
266 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
267 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
268 SDTCisSameAs<1,2>]>>;
269 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
270 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
271 SDTCisSameAs<1,2>]>>;
273 def X86extrqi : SDNode<"X86ISD::EXTRQI",
274 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
275 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
276 def X86insertqi : SDNode<"X86ISD::INSERTQI",
277 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
278 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
281 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
282 // translated into one of the target nodes below during lowering.
283 // Note: this is a work in progress...
284 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
285 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
287 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
288 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
290 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
292 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
293 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
294 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
295 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
296 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
297 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
298 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
299 SDTCisInt<2>, SDTCisInt<3>]>;
301 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
302 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
304 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
305 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
307 def SDTTernlog : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
308 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
311 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
312 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
314 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
315 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
317 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
318 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
319 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
320 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
321 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
322 SDTCisVec<0>, SDTCisInt<2>]>;
323 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
324 SDTCisVec<0>, SDTCisInt<3>]>;
325 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
326 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
328 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
329 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
331 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
332 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
334 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
335 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
336 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
338 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
339 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
341 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
342 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
343 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
345 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
346 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
348 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
349 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
350 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
352 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
353 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
355 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
356 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
357 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
359 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
360 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
362 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
363 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
365 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
366 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
367 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
368 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
369 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
370 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
371 def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
373 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
375 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
376 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
377 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
378 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
379 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
380 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
381 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
382 SDTCisVec<1>, SDTCisInt<2>]>, []>;
383 def X86Vfpclasss : SDNode<"X86ISD::VFPCLASS", SDTypeProfile<1, 2, [SDTCisInt<0>,
384 SDTCisFP<1>, SDTCisInt<2>]>,[]>;
386 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
387 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
388 SDTCisSubVecOfVec<1, 0>]>, []>;
389 // SDTCisSubVecOfVec restriction cannot be applied for 128 bit version of VBROADCASTI32x2.
390 def X86SubV32x2Broadcast : SDNode<"X86ISD::SUBV_BROADCAST",
391 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>, []>;
393 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
394 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
395 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
396 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
397 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
399 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
401 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
403 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
404 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
405 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
406 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
407 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
408 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
409 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
410 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
411 def X86fsqrtRnds : SDNode<"X86ISD::FSQRT_RND", STDFp2SrcRm>;
412 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
413 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
415 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
416 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
417 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
418 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
419 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
420 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
422 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
423 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
424 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
425 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
426 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
427 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
429 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
430 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
431 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
433 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
434 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
435 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
436 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
437 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
439 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
440 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
442 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
443 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
444 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
447 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
448 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
450 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
451 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
452 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
453 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
455 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
456 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
458 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
459 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
460 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
461 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
463 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
464 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
465 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
466 SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
467 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
468 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
469 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
470 SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
471 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
472 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
474 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
475 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
478 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
479 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
481 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
482 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
486 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
487 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
489 def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
490 def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
491 def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
492 def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
493 // Vector with rounding mode
495 // cvtt fp-to-int staff
496 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
497 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
498 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
499 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
501 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
502 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
503 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
504 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
506 // cvt fp-to-int staff
507 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
508 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
509 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
510 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
512 // Vector without rounding mode
513 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
514 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
515 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
516 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
518 def X86cvtph2ps : SDNode<"ISD::FP16_TO_FP",
519 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
520 SDTCVecEltisVT<0, f32>,
521 SDTCVecEltisVT<1, i16>,
522 SDTCisFP<0>, SDTCisInt<2>]> >;
524 def X86cvtps2ph : SDNode<"ISD::FP_TO_FP16",
525 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
526 SDTCVecEltisVT<0, i16>,
527 SDTCVecEltisVT<1, f32>,
528 SDTCisFP<1>, SDTCisInt<2>, SDTCisInt<3>]> >;
529 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
530 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
531 SDTCisFP<0>, SDTCisFP<1>,
532 SDTCisOpSmallerThanOp<1, 0>,
534 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
535 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
536 SDTCisFP<0>, SDTCisFP<1>,
537 SDTCVecEltisVT<0, f32>,
538 SDTCVecEltisVT<1, f64>,
541 //===----------------------------------------------------------------------===//
542 // SSE Complex Patterns
543 //===----------------------------------------------------------------------===//
545 // These are 'extloads' from a scalar to the low element of a vector, zeroing
546 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
548 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
549 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
551 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
552 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
555 def ssmem : Operand<v4f32> {
556 let PrintMethod = "printf32mem";
557 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
558 let ParserMatchClass = X86Mem32AsmOperand;
559 let OperandType = "OPERAND_MEMORY";
561 def sdmem : Operand<v2f64> {
562 let PrintMethod = "printf64mem";
563 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
564 let ParserMatchClass = X86Mem64AsmOperand;
565 let OperandType = "OPERAND_MEMORY";
568 //===----------------------------------------------------------------------===//
569 // SSE pattern fragments
570 //===----------------------------------------------------------------------===//
572 // 128-bit load pattern fragments
573 // NOTE: all 128-bit integer vector loads are promoted to v2i64
574 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
575 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
576 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
578 // 256-bit load pattern fragments
579 // NOTE: all 256-bit integer vector loads are promoted to v4i64
580 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
581 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
582 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
584 // 512-bit load pattern fragments
585 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
586 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
587 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
588 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
589 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
590 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
592 // 128-/256-/512-bit extload pattern fragments
593 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
594 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
595 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
597 // These are needed to match a scalar load that is used in a vector-only
598 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
599 // The memory operand is required to be a 128-bit load, so it must be converted
600 // from a vector to a scalar.
601 def loadf32_128 : PatFrag<(ops node:$ptr),
602 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
603 def loadf64_128 : PatFrag<(ops node:$ptr),
604 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
606 // Like 'store', but always requires 128-bit vector alignment.
607 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
608 (store node:$val, node:$ptr), [{
609 return cast<StoreSDNode>(N)->getAlignment() >= 16;
612 // Like 'store', but always requires 256-bit vector alignment.
613 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
614 (store node:$val, node:$ptr), [{
615 return cast<StoreSDNode>(N)->getAlignment() >= 32;
618 // Like 'store', but always requires 512-bit vector alignment.
619 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
620 (store node:$val, node:$ptr), [{
621 return cast<StoreSDNode>(N)->getAlignment() >= 64;
624 // Like 'load', but always requires 128-bit vector alignment.
625 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
626 return cast<LoadSDNode>(N)->getAlignment() >= 16;
629 // Like 'X86vzload', but always requires 128-bit vector alignment.
630 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
631 return cast<MemSDNode>(N)->getAlignment() >= 16;
634 // Like 'load', but always requires 256-bit vector alignment.
635 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
636 return cast<LoadSDNode>(N)->getAlignment() >= 32;
639 // Like 'load', but always requires 512-bit vector alignment.
640 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
641 return cast<LoadSDNode>(N)->getAlignment() >= 64;
644 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
645 (f32 (alignedload node:$ptr))>;
646 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
647 (f64 (alignedload node:$ptr))>;
649 // 128-bit aligned load pattern fragments
650 // NOTE: all 128-bit integer vector loads are promoted to v2i64
651 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
652 (v4f32 (alignedload node:$ptr))>;
653 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
654 (v2f64 (alignedload node:$ptr))>;
655 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
656 (v2i64 (alignedload node:$ptr))>;
658 // 256-bit aligned load pattern fragments
659 // NOTE: all 256-bit integer vector loads are promoted to v4i64
660 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
661 (v8f32 (alignedload256 node:$ptr))>;
662 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
663 (v4f64 (alignedload256 node:$ptr))>;
664 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
665 (v4i64 (alignedload256 node:$ptr))>;
667 // 512-bit aligned load pattern fragments
668 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
669 (v16f32 (alignedload512 node:$ptr))>;
670 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
671 (v16i32 (alignedload512 node:$ptr))>;
672 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
673 (v8f64 (alignedload512 node:$ptr))>;
674 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
675 (v8i64 (alignedload512 node:$ptr))>;
677 // Like 'load', but uses special alignment checks suitable for use in
678 // memory operands in most SSE instructions, which are required to
679 // be naturally aligned on some targets but not on others. If the subtarget
680 // allows unaligned accesses, match any load, though this may require
681 // setting a feature bit in the processor (on startup, for example).
682 // Opteron 10h and later implement such a feature.
683 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
684 return Subtarget->hasSSEUnalignedMem()
685 || cast<LoadSDNode>(N)->getAlignment() >= 16;
688 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
689 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
691 // 128-bit memop pattern fragments
692 // NOTE: all 128-bit integer vector loads are promoted to v2i64
693 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
694 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
695 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
697 // These are needed to match a scalar memop that is used in a vector-only
698 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
699 // The memory operand is required to be a 128-bit load, so it must be converted
700 // from a vector to a scalar.
701 def memopfsf32_128 : PatFrag<(ops node:$ptr),
702 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
703 def memopfsf64_128 : PatFrag<(ops node:$ptr),
704 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
707 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
709 // FIXME: 8 byte alignment for mmx reads is not required
710 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
711 return cast<LoadSDNode>(N)->getAlignment() >= 8;
714 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
716 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
717 (masked_gather node:$src1, node:$src2, node:$src3) , [{
718 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
719 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
720 Mgt->getBasePtr().getValueType() == MVT::v4i32);
724 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
725 (masked_gather node:$src1, node:$src2, node:$src3) , [{
726 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
727 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
728 Mgt->getBasePtr().getValueType() == MVT::v8i32);
732 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
733 (masked_gather node:$src1, node:$src2, node:$src3) , [{
734 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
735 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
736 Mgt->getBasePtr().getValueType() == MVT::v2i64);
739 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
740 (masked_gather node:$src1, node:$src2, node:$src3) , [{
741 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
742 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
743 Mgt->getBasePtr().getValueType() == MVT::v4i64);
746 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
747 (masked_gather node:$src1, node:$src2, node:$src3) , [{
748 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
749 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
750 Mgt->getBasePtr().getValueType() == MVT::v8i64);
753 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
754 (masked_gather node:$src1, node:$src2, node:$src3) , [{
755 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
756 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
757 Mgt->getBasePtr().getValueType() == MVT::v16i32);
761 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
762 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
763 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
764 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
765 Sc->getBasePtr().getValueType() == MVT::v2i64);
769 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
770 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
771 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
772 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
773 Sc->getBasePtr().getValueType() == MVT::v4i32);
777 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
778 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
779 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
780 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
781 Sc->getBasePtr().getValueType() == MVT::v4i64);
785 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
786 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
787 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
788 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
789 Sc->getBasePtr().getValueType() == MVT::v8i32);
793 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
794 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
795 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
796 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
797 Sc->getBasePtr().getValueType() == MVT::v8i64);
800 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
801 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
802 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
803 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
804 Sc->getBasePtr().getValueType() == MVT::v16i32);
808 // 128-bit bitconvert pattern fragments
809 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
810 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
811 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
812 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
813 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
814 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
816 // 256-bit bitconvert pattern fragments
817 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
818 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
819 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
820 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
821 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
823 // 512-bit bitconvert pattern fragments
824 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
825 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
826 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
827 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
829 def vzmovl_v2i64 : PatFrag<(ops node:$src),
830 (bitconvert (v2i64 (X86vzmovl
831 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
832 def vzmovl_v4i32 : PatFrag<(ops node:$src),
833 (bitconvert (v4i32 (X86vzmovl
834 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
836 def vzload_v2i64 : PatFrag<(ops node:$src),
837 (bitconvert (v2i64 (X86vzload node:$src)))>;
840 def fp32imm0 : PatLeaf<(f32 fpimm), [{
841 return N->isExactlyValue(+0.0);
844 def I8Imm : SDNodeXForm<imm, [{
845 // Transformation function: get the low 8 bits.
846 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
849 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
850 def FROUND_CURRENT : ImmLeaf<i32, [{
851 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
854 // BYTE_imm - Transform bit immediates into byte immediates.
855 def BYTE_imm : SDNodeXForm<imm, [{
856 // Transformation function: imm >> 3
857 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
860 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
861 // to VEXTRACTF128/VEXTRACTI128 imm.
862 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
863 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
866 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
867 // VINSERTF128/VINSERTI128 imm.
868 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
869 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
872 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
873 // to VEXTRACTF64x4 imm.
874 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
875 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
878 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
880 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
881 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
884 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
885 (extract_subvector node:$bigvec,
887 return X86::isVEXTRACT128Index(N);
888 }], EXTRACT_get_vextract128_imm>;
890 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
892 (insert_subvector node:$bigvec, node:$smallvec,
894 return X86::isVINSERT128Index(N);
895 }], INSERT_get_vinsert128_imm>;
898 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
899 (extract_subvector node:$bigvec,
901 return X86::isVEXTRACT256Index(N);
902 }], EXTRACT_get_vextract256_imm>;
904 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
906 (insert_subvector node:$bigvec, node:$smallvec,
908 return X86::isVINSERT256Index(N);
909 }], INSERT_get_vinsert256_imm>;
911 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
912 (masked_load node:$src1, node:$src2, node:$src3), [{
913 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
914 return Load->getAlignment() >= 16;
918 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
919 (masked_load node:$src1, node:$src2, node:$src3), [{
920 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
921 return Load->getAlignment() >= 32;
925 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
926 (masked_load node:$src1, node:$src2, node:$src3), [{
927 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
928 return Load->getAlignment() >= 64;
932 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
933 (masked_load node:$src1, node:$src2, node:$src3), [{
934 return isa<MaskedLoadSDNode>(N);
937 // masked store fragments.
938 // X86mstore can't be implemented in core DAG files because some targets
939 // doesn't support vector type ( llvm-tblgen will fail)
940 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
941 (masked_store node:$src1, node:$src2, node:$src3), [{
942 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
945 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
946 (X86mstore node:$src1, node:$src2, node:$src3), [{
947 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
948 return Store->getAlignment() >= 16;
952 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
953 (X86mstore node:$src1, node:$src2, node:$src3), [{
954 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
955 return Store->getAlignment() >= 32;
959 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
960 (X86mstore node:$src1, node:$src2, node:$src3), [{
961 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
962 return Store->getAlignment() >= 64;
966 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
967 (X86mstore node:$src1, node:$src2, node:$src3), [{
968 return isa<MaskedStoreSDNode>(N);
971 // masked truncstore fragments
972 // X86mtruncstore can't be implemented in core DAG files because some targets
973 // doesn't support vector type ( llvm-tblgen will fail)
974 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
975 (masked_store node:$src1, node:$src2, node:$src3), [{
976 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
978 def masked_truncstorevi8 :
979 PatFrag<(ops node:$src1, node:$src2, node:$src3),
980 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
981 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
983 def masked_truncstorevi16 :
984 PatFrag<(ops node:$src1, node:$src2, node:$src3),
985 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
986 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
988 def masked_truncstorevi32 :
989 PatFrag<(ops node:$src1, node:$src2, node:$src3),
990 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
991 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;