1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
62 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
63 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
64 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
65 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
66 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
67 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
68 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
69 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
70 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
71 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
72 SDTCisVT<1, v4i32>]>>;
73 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
74 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
75 SDTCisVT<1, v4i32>]>>;
76 def X86pshufb : SDNode<"X86ISD::PSHUFB",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
79 def X86psadbw : SDNode<"X86ISD::PSADBW",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
83 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
84 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
85 def X86andnp : SDNode<"X86ISD::ANDNP",
86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def X86psign : SDNode<"X86ISD::PSIGN",
89 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def X86pextrb : SDNode<"X86ISD::PEXTRB",
92 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
93 def X86pextrw : SDNode<"X86ISD::PEXTRW",
94 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
95 def X86pinsrb : SDNode<"X86ISD::PINSRB",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
97 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
98 def X86pinsrw : SDNode<"X86ISD::PINSRW",
99 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
100 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
101 def X86insertps : SDNode<"X86ISD::INSERTPS",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
103 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
104 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
105 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
107 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
108 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
110 def X86vzext : SDNode<"X86ISD::VZEXT",
111 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
112 SDTCisInt<0>, SDTCisInt<1>,
113 SDTCisOpSmallerThanOp<1, 0>]>>;
115 def X86vsext : SDNode<"X86ISD::VSEXT",
116 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
117 SDTCisInt<0>, SDTCisInt<1>,
118 SDTCisOpSmallerThanOp<1, 0>]>>;
120 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
121 SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>;
124 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
125 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
126 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
128 def X86trunc : SDNode<"X86ISD::TRUNC",
129 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
130 SDTCisOpSmallerThanOp<0, 1>]>>;
131 def X86vfpext : SDNode<"X86ISD::VFPEXT",
132 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
133 SDTCisFP<0>, SDTCisFP<1>,
134 SDTCisOpSmallerThanOp<1, 0>]>>;
135 def X86vfpround: SDNode<"X86ISD::VFPROUND",
136 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
137 SDTCisFP<0>, SDTCisFP<1>,
138 SDTCisOpSmallerThanOp<0, 1>]>>;
140 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
141 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
142 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
143 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
144 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
146 def X86IntCmpMask : SDTypeProfile<1, 2,
147 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
148 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
149 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
152 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
153 SDTCisVec<1>, SDTCisSameAs<2, 1>,
154 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
155 def X86CmpMaskCCRound :
156 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
157 SDTCisVec<1>, SDTCisSameAs<2, 1>,
158 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
160 def X86CmpMaskCCScalar :
161 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
163 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
164 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
165 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
166 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
168 def X86vshl : SDNode<"X86ISD::VSHL",
169 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
171 def X86vsrl : SDNode<"X86ISD::VSRL",
172 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
174 def X86vsra : SDNode<"X86ISD::VSRA",
175 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
178 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
179 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
180 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
182 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
184 SDTCisSameAs<2, 1>]>;
185 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
186 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
187 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
188 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
189 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
190 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
191 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
192 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
193 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
194 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
195 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
196 SDTCisVec<1>, SDTCisSameAs<2, 1>,
197 SDTCVecEltisVT<0, i1>,
198 SDTCisSameNumEltsAs<0, 1>]>>;
199 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
200 SDTCisVec<1>, SDTCisSameAs<2, 1>,
201 SDTCVecEltisVT<0, i1>,
202 SDTCisSameNumEltsAs<0, 1>]>>;
203 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
205 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
206 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
207 SDTCisSameAs<1,2>]>>;
208 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
209 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
210 SDTCisSameAs<1,2>]>>;
212 def X86extrqi : SDNode<"X86ISD::EXTRQI",
213 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
214 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
215 def X86insertqi : SDNode<"X86ISD::INSERTQI",
216 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
217 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
220 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
221 // translated into one of the target nodes below during lowering.
222 // Note: this is a work in progress...
223 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
224 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
226 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
227 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
229 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
231 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
232 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
233 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
234 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
235 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
236 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
237 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
238 SDTCisInt<2>, SDTCisInt<3>]>;
240 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
241 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
243 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
244 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
246 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
247 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
249 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
250 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
252 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
253 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
254 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
255 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
256 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
257 SDTCisVec<0>, SDTCisInt<2>]>;
258 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
259 SDTCisVec<0>, SDTCisInt<3>]>;
260 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
261 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
263 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
264 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
265 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
267 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
268 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
269 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
271 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
272 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
274 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
275 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
276 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
278 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
279 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
281 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
282 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
283 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
285 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
286 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
288 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
289 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
290 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
292 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
293 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
295 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
296 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
298 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
299 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
300 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
301 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
302 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
303 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
305 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
307 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
308 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
309 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
310 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
311 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
313 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
314 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
315 SDTCisSubVecOfVec<1, 0>]>, []>;
316 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
317 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
318 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
319 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
320 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
322 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
324 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
326 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
327 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
328 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
329 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
330 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
331 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
332 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
333 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
334 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
335 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
337 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
338 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
339 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
340 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
341 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
342 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
344 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
345 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
346 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
347 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
348 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
349 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
351 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
352 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
353 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
355 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
356 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
357 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
358 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
359 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
361 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
362 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
364 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
365 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
366 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
369 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
370 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
372 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
373 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
374 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
375 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
377 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
378 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
380 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
381 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
382 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
383 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
385 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
386 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
387 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
388 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
390 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
391 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
393 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
394 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
397 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
398 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
400 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
401 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
405 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
406 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
408 // Vector with rounding mode
410 // cvtt fp-to-int staff
411 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
412 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
413 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
414 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
416 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
417 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
418 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
419 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
421 // cvt fp-to-int staff
422 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
423 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
424 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
425 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
427 // Vector without rounding mode
428 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
429 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
430 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
431 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
433 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
434 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
435 SDTCisFP<0>, SDTCisFP<1>,
436 SDTCisOpSmallerThanOp<1, 0>,
438 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
439 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
440 SDTCisFP<0>, SDTCisFP<1>,
441 SDTCVecEltisVT<0, f32>,
442 SDTCVecEltisVT<1, f64>,
445 //===----------------------------------------------------------------------===//
446 // SSE Complex Patterns
447 //===----------------------------------------------------------------------===//
449 // These are 'extloads' from a scalar to the low element of a vector, zeroing
450 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
452 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
453 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
455 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
456 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
459 def ssmem : Operand<v4f32> {
460 let PrintMethod = "printf32mem";
461 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
462 let ParserMatchClass = X86Mem32AsmOperand;
463 let OperandType = "OPERAND_MEMORY";
465 def sdmem : Operand<v2f64> {
466 let PrintMethod = "printf64mem";
467 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
468 let ParserMatchClass = X86Mem64AsmOperand;
469 let OperandType = "OPERAND_MEMORY";
472 //===----------------------------------------------------------------------===//
473 // SSE pattern fragments
474 //===----------------------------------------------------------------------===//
476 // 128-bit load pattern fragments
477 // NOTE: all 128-bit integer vector loads are promoted to v2i64
478 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
479 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
480 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
482 // 256-bit load pattern fragments
483 // NOTE: all 256-bit integer vector loads are promoted to v4i64
484 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
485 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
486 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
488 // 512-bit load pattern fragments
489 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
490 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
491 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
492 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
493 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
494 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
496 // 128-/256-/512-bit extload pattern fragments
497 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
498 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
499 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
501 // These are needed to match a scalar load that is used in a vector-only
502 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
503 // The memory operand is required to be a 128-bit load, so it must be converted
504 // from a vector to a scalar.
505 def loadf32_128 : PatFrag<(ops node:$ptr),
506 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
507 def loadf64_128 : PatFrag<(ops node:$ptr),
508 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
510 // Like 'store', but always requires 128-bit vector alignment.
511 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
512 (store node:$val, node:$ptr), [{
513 return cast<StoreSDNode>(N)->getAlignment() >= 16;
516 // Like 'store', but always requires 256-bit vector alignment.
517 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
518 (store node:$val, node:$ptr), [{
519 return cast<StoreSDNode>(N)->getAlignment() >= 32;
522 // Like 'store', but always requires 512-bit vector alignment.
523 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
524 (store node:$val, node:$ptr), [{
525 return cast<StoreSDNode>(N)->getAlignment() >= 64;
528 // Like 'load', but always requires 128-bit vector alignment.
529 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
530 return cast<LoadSDNode>(N)->getAlignment() >= 16;
533 // Like 'X86vzload', but always requires 128-bit vector alignment.
534 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
535 return cast<MemSDNode>(N)->getAlignment() >= 16;
538 // Like 'load', but always requires 256-bit vector alignment.
539 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
540 return cast<LoadSDNode>(N)->getAlignment() >= 32;
543 // Like 'load', but always requires 512-bit vector alignment.
544 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
545 return cast<LoadSDNode>(N)->getAlignment() >= 64;
548 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
549 (f32 (alignedload node:$ptr))>;
550 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
551 (f64 (alignedload node:$ptr))>;
553 // 128-bit aligned load pattern fragments
554 // NOTE: all 128-bit integer vector loads are promoted to v2i64
555 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
556 (v4f32 (alignedload node:$ptr))>;
557 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
558 (v2f64 (alignedload node:$ptr))>;
559 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
560 (v2i64 (alignedload node:$ptr))>;
562 // 256-bit aligned load pattern fragments
563 // NOTE: all 256-bit integer vector loads are promoted to v4i64
564 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
565 (v8f32 (alignedload256 node:$ptr))>;
566 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
567 (v4f64 (alignedload256 node:$ptr))>;
568 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
569 (v4i64 (alignedload256 node:$ptr))>;
571 // 512-bit aligned load pattern fragments
572 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
573 (v16f32 (alignedload512 node:$ptr))>;
574 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
575 (v16i32 (alignedload512 node:$ptr))>;
576 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
577 (v8f64 (alignedload512 node:$ptr))>;
578 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
579 (v8i64 (alignedload512 node:$ptr))>;
581 // Like 'load', but uses special alignment checks suitable for use in
582 // memory operands in most SSE instructions, which are required to
583 // be naturally aligned on some targets but not on others. If the subtarget
584 // allows unaligned accesses, match any load, though this may require
585 // setting a feature bit in the processor (on startup, for example).
586 // Opteron 10h and later implement such a feature.
587 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
588 return Subtarget->hasSSEUnalignedMem()
589 || cast<LoadSDNode>(N)->getAlignment() >= 16;
592 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
593 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
595 // 128-bit memop pattern fragments
596 // NOTE: all 128-bit integer vector loads are promoted to v2i64
597 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
598 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
599 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
601 // These are needed to match a scalar memop that is used in a vector-only
602 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
603 // The memory operand is required to be a 128-bit load, so it must be converted
604 // from a vector to a scalar.
605 def memopfsf32_128 : PatFrag<(ops node:$ptr),
606 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
607 def memopfsf64_128 : PatFrag<(ops node:$ptr),
608 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
611 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
613 // FIXME: 8 byte alignment for mmx reads is not required
614 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
615 return cast<LoadSDNode>(N)->getAlignment() >= 8;
618 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
621 // Like 'store', but requires the non-temporal bit to be set
622 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
623 (store node:$val, node:$ptr), [{
624 return cast<StoreSDNode>(N)->isNonTemporal();
627 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
628 (nontemporalstore node:$val, node:$ptr), [{
629 return cast<StoreSDNode>(N)->getAlignment() >= 16;
632 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
633 (nontemporalstore node:$val, node:$ptr), [{
634 return cast<StoreSDNode>(N)->getAlignment() < 16;
637 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
638 (masked_gather node:$src1, node:$src2, node:$src3) , [{
639 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
640 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
641 Mgt->getBasePtr().getValueType() == MVT::v4i32);
645 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
646 (masked_gather node:$src1, node:$src2, node:$src3) , [{
647 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
648 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
649 Mgt->getBasePtr().getValueType() == MVT::v8i32);
653 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
654 (masked_gather node:$src1, node:$src2, node:$src3) , [{
655 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
656 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
657 Mgt->getBasePtr().getValueType() == MVT::v2i64);
660 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
661 (masked_gather node:$src1, node:$src2, node:$src3) , [{
662 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
663 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
664 Mgt->getBasePtr().getValueType() == MVT::v4i64);
667 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
668 (masked_gather node:$src1, node:$src2, node:$src3) , [{
669 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
670 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
671 Mgt->getBasePtr().getValueType() == MVT::v8i64);
674 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
675 (masked_gather node:$src1, node:$src2, node:$src3) , [{
676 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
677 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
678 Mgt->getBasePtr().getValueType() == MVT::v16i32);
682 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
683 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
684 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
685 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
686 Sc->getBasePtr().getValueType() == MVT::v2i64);
690 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
691 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
692 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
693 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
694 Sc->getBasePtr().getValueType() == MVT::v4i32);
698 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
699 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
700 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
701 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
702 Sc->getBasePtr().getValueType() == MVT::v4i64);
706 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
707 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
708 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
709 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
710 Sc->getBasePtr().getValueType() == MVT::v8i32);
714 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
715 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
716 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
717 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
718 Sc->getBasePtr().getValueType() == MVT::v8i64);
721 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
722 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
723 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
724 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
725 Sc->getBasePtr().getValueType() == MVT::v16i32);
729 // 128-bit bitconvert pattern fragments
730 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
731 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
732 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
733 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
734 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
735 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
737 // 256-bit bitconvert pattern fragments
738 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
739 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
740 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
741 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
742 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
744 // 512-bit bitconvert pattern fragments
745 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
746 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
747 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
748 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
750 def vzmovl_v2i64 : PatFrag<(ops node:$src),
751 (bitconvert (v2i64 (X86vzmovl
752 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
753 def vzmovl_v4i32 : PatFrag<(ops node:$src),
754 (bitconvert (v4i32 (X86vzmovl
755 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
757 def vzload_v2i64 : PatFrag<(ops node:$src),
758 (bitconvert (v2i64 (X86vzload node:$src)))>;
761 def fp32imm0 : PatLeaf<(f32 fpimm), [{
762 return N->isExactlyValue(+0.0);
765 def I8Imm : SDNodeXForm<imm, [{
766 // Transformation function: get the low 8 bits.
767 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
770 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
771 def FROUND_CURRENT : ImmLeaf<i32, [{
772 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
775 // BYTE_imm - Transform bit immediates into byte immediates.
776 def BYTE_imm : SDNodeXForm<imm, [{
777 // Transformation function: imm >> 3
778 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
781 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
782 // to VEXTRACTF128/VEXTRACTI128 imm.
783 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
784 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
787 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
788 // VINSERTF128/VINSERTI128 imm.
789 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
790 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
793 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
794 // to VEXTRACTF64x4 imm.
795 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
796 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
799 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
801 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
802 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
805 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
806 (extract_subvector node:$bigvec,
808 return X86::isVEXTRACT128Index(N);
809 }], EXTRACT_get_vextract128_imm>;
811 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
813 (insert_subvector node:$bigvec, node:$smallvec,
815 return X86::isVINSERT128Index(N);
816 }], INSERT_get_vinsert128_imm>;
819 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
820 (extract_subvector node:$bigvec,
822 return X86::isVEXTRACT256Index(N);
823 }], EXTRACT_get_vextract256_imm>;
825 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
827 (insert_subvector node:$bigvec, node:$smallvec,
829 return X86::isVINSERT256Index(N);
830 }], INSERT_get_vinsert256_imm>;
832 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
833 (masked_load node:$src1, node:$src2, node:$src3), [{
834 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
835 return Load->getAlignment() >= 16;
839 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
840 (masked_load node:$src1, node:$src2, node:$src3), [{
841 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
842 return Load->getAlignment() >= 32;
846 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
847 (masked_load node:$src1, node:$src2, node:$src3), [{
848 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
849 return Load->getAlignment() >= 64;
853 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
854 (masked_load node:$src1, node:$src2, node:$src3), [{
855 return isa<MaskedLoadSDNode>(N);
858 // masked store fragments.
859 // X86mstore can't be implemented in core DAG files because some targets
860 // doesn't support vector type ( llvm-tblgen will fail)
861 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
862 (masked_store node:$src1, node:$src2, node:$src3), [{
863 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
866 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
867 (X86mstore node:$src1, node:$src2, node:$src3), [{
868 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
869 return Store->getAlignment() >= 16;
873 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
874 (X86mstore node:$src1, node:$src2, node:$src3), [{
875 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
876 return Store->getAlignment() >= 32;
880 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
881 (X86mstore node:$src1, node:$src2, node:$src3), [{
882 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
883 return Store->getAlignment() >= 64;
887 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
888 (X86mstore node:$src1, node:$src2, node:$src3), [{
889 return isa<MaskedStoreSDNode>(N);
892 // masked truncstore fragments
893 // X86mtruncstore can't be implemented in core DAG files because some targets
894 // doesn't support vector type ( llvm-tblgen will fail)
895 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
896 (masked_store node:$src1, node:$src2, node:$src3), [{
897 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
899 def masked_truncstorevi8 :
900 PatFrag<(ops node:$src1, node:$src2, node:$src3),
901 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
902 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
904 def masked_truncstorevi16 :
905 PatFrag<(ops node:$src1, node:$src2, node:$src3),
906 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
907 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
909 def masked_truncstorevi32 :
910 PatFrag<(ops node:$src1, node:$src2, node:$src3),
911 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
912 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;