1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>;
62 def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>;
63 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
64 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
65 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
66 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
67 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
68 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
69 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
70 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
71 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
72 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
73 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
74 SDTCisVT<1, v4i32>]>>;
75 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
76 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
77 SDTCisVT<1, v4i32>]>>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
81 def X86psadbw : SDNode<"X86ISD::PSADBW",
82 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
83 SDTCVecEltisVT<1, i8>,
84 SDTCisSameSizeAs<0,1>,
86 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
87 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
88 SDTCVecEltisVT<1, i8>,
89 SDTCisSameSizeAs<0,1>,
90 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
91 def X86andnp : SDNode<"X86ISD::ANDNP",
92 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
94 def X86psign : SDNode<"X86ISD::PSIGN",
95 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
97 def X86pextrb : SDNode<"X86ISD::PEXTRB",
98 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
100 def X86pextrw : SDNode<"X86ISD::PEXTRW",
101 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
103 def X86pinsrb : SDNode<"X86ISD::PINSRB",
104 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
105 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
106 def X86pinsrw : SDNode<"X86ISD::PINSRW",
107 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
108 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
109 def X86insertps : SDNode<"X86ISD::INSERTPS",
110 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
111 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
112 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
113 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
115 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
116 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
118 def X86vzext : SDNode<"X86ISD::VZEXT",
119 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
120 SDTCisInt<0>, SDTCisInt<1>,
121 SDTCisOpSmallerThanOp<1, 0>]>>;
123 def X86vsext : SDNode<"X86ISD::VSEXT",
124 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
125 SDTCisInt<0>, SDTCisInt<1>,
126 SDTCisOpSmallerThanOp<1, 0>]>>;
128 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
129 SDTCisInt<0>, SDTCisInt<1>,
130 SDTCisOpSmallerThanOp<0, 1>]>;
132 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
133 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
134 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
136 def X86trunc : SDNode<"X86ISD::TRUNC",
137 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
138 SDTCisOpSmallerThanOp<0, 1>]>>;
139 def X86vfpext : SDNode<"X86ISD::VFPEXT",
140 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
141 SDTCisFP<0>, SDTCisFP<1>,
142 SDTCisOpSmallerThanOp<1, 0>]>>;
143 def X86vfpround: SDNode<"X86ISD::VFPROUND",
144 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
145 SDTCisFP<0>, SDTCisFP<1>,
146 SDTCisOpSmallerThanOp<0, 1>]>>;
148 def X86fround: SDNode<"X86ISD::VFPROUND",
149 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
150 SDTCVecEltisVT<0, f32>,
151 SDTCVecEltisVT<1, f64>,
152 SDTCVecEltisVT<2, f64>,
153 SDTCisOpSmallerThanOp<0, 1>]>>;
154 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
155 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
156 SDTCVecEltisVT<0, f32>,
157 SDTCVecEltisVT<1, f64>,
158 SDTCVecEltisVT<2, f64>,
159 SDTCisOpSmallerThanOp<0, 1>,
162 def X86fpext : SDNode<"X86ISD::VFPEXT",
163 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
164 SDTCVecEltisVT<0, f64>,
165 SDTCVecEltisVT<1, f32>,
166 SDTCVecEltisVT<2, f32>,
167 SDTCisOpSmallerThanOp<1, 0>]>>;
169 def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
170 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
171 SDTCVecEltisVT<0, f64>,
172 SDTCVecEltisVT<1, f32>,
173 SDTCVecEltisVT<2, f32>,
174 SDTCisOpSmallerThanOp<1, 0>,
177 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
178 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
179 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
180 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
181 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
183 def X86IntCmpMask : SDTypeProfile<1, 2,
184 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
185 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
186 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
189 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
190 SDTCisVec<1>, SDTCisSameAs<2, 1>,
191 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
192 def X86CmpMaskCCRound :
193 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
194 SDTCisVec<1>, SDTCisSameAs<2, 1>,
195 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
197 def X86CmpMaskCCScalar :
198 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
200 def X86CmpMaskCCScalarRound :
201 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
204 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
205 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
206 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
207 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
208 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalarRound>;
210 def X86vshl : SDNode<"X86ISD::VSHL",
211 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
213 def X86vsrl : SDNode<"X86ISD::VSRL",
214 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
216 def X86vsra : SDNode<"X86ISD::VSRA",
217 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
220 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
221 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
222 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
224 def X86vprot : SDNode<"X86ISD::VPROT",
225 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
226 SDTCisSameAs<0,2>]>>;
227 def X86vproti : SDNode<"X86ISD::VPROTI",
228 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
231 def X86vpshl : SDNode<"X86ISD::VPSHL",
232 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
233 SDTCisSameAs<0,2>]>>;
234 def X86vpsha : SDNode<"X86ISD::VPSHA",
235 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
236 SDTCisSameAs<0,2>]>>;
238 def X86vpcom : SDNode<"X86ISD::VPCOM",
239 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
242 def X86vpcomu : SDNode<"X86ISD::VPCOMU",
243 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
247 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
249 SDTCisSameAs<2, 1>]>;
250 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
251 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
252 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
253 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
254 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
255 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
256 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
257 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
258 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
259 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
260 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
261 SDTCisVec<1>, SDTCisSameAs<2, 1>,
262 SDTCVecEltisVT<0, i1>,
263 SDTCisSameNumEltsAs<0, 1>]>>;
264 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
265 SDTCisVec<1>, SDTCisSameAs<2, 1>,
266 SDTCVecEltisVT<0, i1>,
267 SDTCisSameNumEltsAs<0, 1>]>>;
268 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
270 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
271 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
272 SDTCVecEltisVT<1, i32>,
273 SDTCisSameSizeAs<0,1>,
274 SDTCisSameAs<1,2>]>>;
275 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
276 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
277 SDTCVecEltisVT<1, i32>,
278 SDTCisSameSizeAs<0,1>,
279 SDTCisSameAs<1,2>]>>;
281 def X86extrqi : SDNode<"X86ISD::EXTRQI",
282 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
283 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
284 def X86insertqi : SDNode<"X86ISD::INSERTQI",
285 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
286 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
289 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
290 // translated into one of the target nodes below during lowering.
291 // Note: this is a work in progress...
292 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
293 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
295 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
296 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
298 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
299 SDTCisSameSizeAs<0,2>,
300 SDTCisSameNumEltsAs<0,2>]>;
301 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
302 SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
303 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
304 SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
305 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
306 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
307 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
308 SDTCisInt<2>, SDTCisInt<3>]>;
310 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
311 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
312 SDTCisInt<0>, SDTCisInt<1>]>;
314 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
315 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
317 def SDTTernlog : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
318 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
321 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
322 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
324 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
325 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
327 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
328 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
329 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
330 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
331 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
332 SDTCisVec<0>, SDTCisVT<2, i32>]>;
333 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
334 SDTCisVec<0>, SDTCisVT<3, i32>]>;
335 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
336 SDTCisVec<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
338 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
339 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
341 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
342 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
344 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
345 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
346 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
348 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
349 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
351 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
352 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
353 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
355 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
356 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
358 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
359 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
360 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
362 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
363 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
365 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
366 SDTCisSameSizeAs<0,1>,
368 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
369 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
371 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
372 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
374 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
375 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
377 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
378 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
379 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
380 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
381 def X86VPermt2Fp : SDNode<"X86ISD::VPERMV3",
382 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
383 SDTCisSameAs<0,1>, SDTCisInt<2>,
384 SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
385 SDTCisSameSizeAs<0,2>,
386 SDTCisSameAs<0,3>]>, []>;
387 def X86VPermt2Int : SDNode<"X86ISD::VPERMV3",
388 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>,
389 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>,
390 SDTCisSameAs<0,3>]>, []>;
392 def X86VPermi2X : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
393 def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
395 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
397 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
398 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
399 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
400 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
401 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
402 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
403 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
404 SDTCisVec<1>, SDTCisInt<2>]>, []>;
405 def X86Vfpclasss : SDNode<"X86ISD::VFPCLASS", SDTypeProfile<1, 2, [SDTCisInt<0>,
406 SDTCisFP<1>, SDTCisInt<2>]>,[]>;
408 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
409 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
410 SDTCisSubVecOfVec<1, 0>]>, []>;
411 // SDTCisSubVecOfVec restriction cannot be applied for 128 bit version of VBROADCASTI32x2.
412 def X86SubV32x2Broadcast : SDNode<"X86ISD::SUBV_BROADCAST",
413 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>, []>;
415 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
416 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
417 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
418 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
419 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
420 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
422 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
424 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
426 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
427 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
428 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
429 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
430 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
431 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
432 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
433 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
434 def X86fsqrtRnds : SDNode<"X86ISD::FSQRT_RND", STDFp2SrcRm>;
435 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
436 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
438 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
439 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
440 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
441 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
442 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
443 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
445 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
446 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
447 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
448 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
449 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
450 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
452 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
453 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
454 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
456 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
457 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
458 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
459 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
460 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
462 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
463 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
465 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
466 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
467 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
470 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
471 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
473 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
474 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
475 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
476 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
478 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
479 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
481 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
482 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
483 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
484 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
486 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
487 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
488 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
489 SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
490 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
491 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
492 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
493 SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
494 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
495 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
497 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
498 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
501 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
502 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
504 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
505 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
509 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
510 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
512 def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
513 def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
514 def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
515 def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
516 // Vector with rounding mode
518 // cvtt fp-to-int staff
519 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
520 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
521 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
522 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
524 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
525 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
526 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
527 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
529 // cvt fp-to-int staff
530 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
531 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
532 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
533 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
535 // Vector without rounding mode
536 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
537 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
538 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
539 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
541 def X86cvtph2ps : SDNode<"ISD::FP16_TO_FP",
542 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
543 SDTCVecEltisVT<0, f32>,
544 SDTCVecEltisVT<1, i16>,
545 SDTCisFP<0>, SDTCisInt<2>]> >;
547 def X86cvtps2ph : SDNode<"ISD::FP_TO_FP16",
548 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
549 SDTCVecEltisVT<0, i16>,
550 SDTCVecEltisVT<1, f32>,
551 SDTCisFP<1>, SDTCisInt<2>, SDTCisInt<3>]> >;
552 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
553 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
554 SDTCisFP<0>, SDTCisFP<1>,
555 SDTCisOpSmallerThanOp<1, 0>,
557 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
558 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
559 SDTCisFP<0>, SDTCisFP<1>,
560 SDTCVecEltisVT<0, f32>,
561 SDTCVecEltisVT<1, f64>,
564 //===----------------------------------------------------------------------===//
565 // SSE Complex Patterns
566 //===----------------------------------------------------------------------===//
568 // These are 'extloads' from a scalar to the low element of a vector, zeroing
569 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
571 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
572 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
574 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
575 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
578 def ssmem : Operand<v4f32> {
579 let PrintMethod = "printf32mem";
580 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
581 let ParserMatchClass = X86Mem32AsmOperand;
582 let OperandType = "OPERAND_MEMORY";
584 def sdmem : Operand<v2f64> {
585 let PrintMethod = "printf64mem";
586 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
587 let ParserMatchClass = X86Mem64AsmOperand;
588 let OperandType = "OPERAND_MEMORY";
591 //===----------------------------------------------------------------------===//
592 // SSE pattern fragments
593 //===----------------------------------------------------------------------===//
595 // 128-bit load pattern fragments
596 // NOTE: all 128-bit integer vector loads are promoted to v2i64
597 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
598 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
599 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
601 // 256-bit load pattern fragments
602 // NOTE: all 256-bit integer vector loads are promoted to v4i64
603 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
604 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
605 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
607 // 512-bit load pattern fragments
608 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
609 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
610 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
611 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
612 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
613 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
615 // 128-/256-/512-bit extload pattern fragments
616 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
617 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
618 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
620 // These are needed to match a scalar load that is used in a vector-only
621 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
622 // The memory operand is required to be a 128-bit load, so it must be converted
623 // from a vector to a scalar.
624 def loadf32_128 : PatFrag<(ops node:$ptr),
625 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
626 def loadf64_128 : PatFrag<(ops node:$ptr),
627 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
629 // Like 'store', but always requires 128-bit vector alignment.
630 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
631 (store node:$val, node:$ptr), [{
632 return cast<StoreSDNode>(N)->getAlignment() >= 16;
635 // Like 'store', but always requires 256-bit vector alignment.
636 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
637 (store node:$val, node:$ptr), [{
638 return cast<StoreSDNode>(N)->getAlignment() >= 32;
641 // Like 'store', but always requires 512-bit vector alignment.
642 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
643 (store node:$val, node:$ptr), [{
644 return cast<StoreSDNode>(N)->getAlignment() >= 64;
647 // Like 'load', but always requires 128-bit vector alignment.
648 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
649 return cast<LoadSDNode>(N)->getAlignment() >= 16;
652 // Like 'X86vzload', but always requires 128-bit vector alignment.
653 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
654 return cast<MemSDNode>(N)->getAlignment() >= 16;
657 // Like 'load', but always requires 256-bit vector alignment.
658 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
659 return cast<LoadSDNode>(N)->getAlignment() >= 32;
662 // Like 'load', but always requires 512-bit vector alignment.
663 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
664 return cast<LoadSDNode>(N)->getAlignment() >= 64;
667 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
668 (f32 (alignedload node:$ptr))>;
669 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
670 (f64 (alignedload node:$ptr))>;
672 // 128-bit aligned load pattern fragments
673 // NOTE: all 128-bit integer vector loads are promoted to v2i64
674 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
675 (v4f32 (alignedload node:$ptr))>;
676 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
677 (v2f64 (alignedload node:$ptr))>;
678 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
679 (v2i64 (alignedload node:$ptr))>;
681 // 256-bit aligned load pattern fragments
682 // NOTE: all 256-bit integer vector loads are promoted to v4i64
683 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
684 (v8f32 (alignedload256 node:$ptr))>;
685 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
686 (v4f64 (alignedload256 node:$ptr))>;
687 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
688 (v4i64 (alignedload256 node:$ptr))>;
690 // 512-bit aligned load pattern fragments
691 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
692 (v16f32 (alignedload512 node:$ptr))>;
693 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
694 (v16i32 (alignedload512 node:$ptr))>;
695 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
696 (v8f64 (alignedload512 node:$ptr))>;
697 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
698 (v8i64 (alignedload512 node:$ptr))>;
700 // Like 'load', but uses special alignment checks suitable for use in
701 // memory operands in most SSE instructions, which are required to
702 // be naturally aligned on some targets but not on others. If the subtarget
703 // allows unaligned accesses, match any load, though this may require
704 // setting a feature bit in the processor (on startup, for example).
705 // Opteron 10h and later implement such a feature.
706 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
707 return Subtarget->hasSSEUnalignedMem()
708 || cast<LoadSDNode>(N)->getAlignment() >= 16;
711 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
712 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
714 // 128-bit memop pattern fragments
715 // NOTE: all 128-bit integer vector loads are promoted to v2i64
716 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
717 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
718 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
720 // These are needed to match a scalar memop that is used in a vector-only
721 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
722 // The memory operand is required to be a 128-bit load, so it must be converted
723 // from a vector to a scalar.
724 def memopfsf32_128 : PatFrag<(ops node:$ptr),
725 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
726 def memopfsf64_128 : PatFrag<(ops node:$ptr),
727 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
730 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
732 // FIXME: 8 byte alignment for mmx reads is not required
733 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
734 return cast<LoadSDNode>(N)->getAlignment() >= 8;
737 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
739 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
740 (masked_gather node:$src1, node:$src2, node:$src3) , [{
741 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
742 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
743 Mgt->getBasePtr().getValueType() == MVT::v4i32);
747 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
748 (masked_gather node:$src1, node:$src2, node:$src3) , [{
749 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
750 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
751 Mgt->getBasePtr().getValueType() == MVT::v8i32);
755 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
756 (masked_gather node:$src1, node:$src2, node:$src3) , [{
757 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
758 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
759 Mgt->getBasePtr().getValueType() == MVT::v2i64);
762 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
763 (masked_gather node:$src1, node:$src2, node:$src3) , [{
764 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
765 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
766 Mgt->getBasePtr().getValueType() == MVT::v4i64);
769 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
770 (masked_gather node:$src1, node:$src2, node:$src3) , [{
771 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
772 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
773 Mgt->getBasePtr().getValueType() == MVT::v8i64);
776 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
777 (masked_gather node:$src1, node:$src2, node:$src3) , [{
778 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
779 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
780 Mgt->getBasePtr().getValueType() == MVT::v16i32);
784 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
785 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
786 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
787 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
788 Sc->getBasePtr().getValueType() == MVT::v2i64);
792 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
793 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
794 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
795 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
796 Sc->getBasePtr().getValueType() == MVT::v4i32);
800 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
801 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
802 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
803 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
804 Sc->getBasePtr().getValueType() == MVT::v4i64);
808 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
809 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
810 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
811 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
812 Sc->getBasePtr().getValueType() == MVT::v8i32);
816 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
817 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
818 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
819 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
820 Sc->getBasePtr().getValueType() == MVT::v8i64);
823 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
824 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
825 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
826 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
827 Sc->getBasePtr().getValueType() == MVT::v16i32);
831 // 128-bit bitconvert pattern fragments
832 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
833 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
834 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
835 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
836 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
837 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
839 // 256-bit bitconvert pattern fragments
840 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
841 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
842 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
843 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
844 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
846 // 512-bit bitconvert pattern fragments
847 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
848 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
849 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
850 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
852 def vzmovl_v2i64 : PatFrag<(ops node:$src),
853 (bitconvert (v2i64 (X86vzmovl
854 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
855 def vzmovl_v4i32 : PatFrag<(ops node:$src),
856 (bitconvert (v4i32 (X86vzmovl
857 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
859 def vzload_v2i64 : PatFrag<(ops node:$src),
860 (bitconvert (v2i64 (X86vzload node:$src)))>;
863 def fp32imm0 : PatLeaf<(f32 fpimm), [{
864 return N->isExactlyValue(+0.0);
867 def I8Imm : SDNodeXForm<imm, [{
868 // Transformation function: get the low 8 bits.
869 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
872 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
873 def FROUND_CURRENT : ImmLeaf<i32, [{
874 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
877 // BYTE_imm - Transform bit immediates into byte immediates.
878 def BYTE_imm : SDNodeXForm<imm, [{
879 // Transformation function: imm >> 3
880 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
883 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
884 // to VEXTRACTF128/VEXTRACTI128 imm.
885 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
886 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
889 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
890 // VINSERTF128/VINSERTI128 imm.
891 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
892 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
895 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
896 // to VEXTRACTF64x4 imm.
897 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
898 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
901 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
903 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
904 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
907 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
908 (extract_subvector node:$bigvec,
910 return X86::isVEXTRACT128Index(N);
911 }], EXTRACT_get_vextract128_imm>;
913 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
915 (insert_subvector node:$bigvec, node:$smallvec,
917 return X86::isVINSERT128Index(N);
918 }], INSERT_get_vinsert128_imm>;
921 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
922 (extract_subvector node:$bigvec,
924 return X86::isVEXTRACT256Index(N);
925 }], EXTRACT_get_vextract256_imm>;
927 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
929 (insert_subvector node:$bigvec, node:$smallvec,
931 return X86::isVINSERT256Index(N);
932 }], INSERT_get_vinsert256_imm>;
934 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
935 (masked_load node:$src1, node:$src2, node:$src3), [{
936 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
937 return Load->getAlignment() >= 16;
941 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
942 (masked_load node:$src1, node:$src2, node:$src3), [{
943 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
944 return Load->getAlignment() >= 32;
948 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
949 (masked_load node:$src1, node:$src2, node:$src3), [{
950 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
951 return Load->getAlignment() >= 64;
955 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
956 (masked_load node:$src1, node:$src2, node:$src3), [{
957 return isa<MaskedLoadSDNode>(N);
960 // masked store fragments.
961 // X86mstore can't be implemented in core DAG files because some targets
962 // doesn't support vector type ( llvm-tblgen will fail)
963 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
964 (masked_store node:$src1, node:$src2, node:$src3), [{
965 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
968 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
969 (X86mstore node:$src1, node:$src2, node:$src3), [{
970 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
971 return Store->getAlignment() >= 16;
975 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
976 (X86mstore node:$src1, node:$src2, node:$src3), [{
977 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
978 return Store->getAlignment() >= 32;
982 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
983 (X86mstore node:$src1, node:$src2, node:$src3), [{
984 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
985 return Store->getAlignment() >= 64;
989 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
990 (X86mstore node:$src1, node:$src2, node:$src3), [{
991 return isa<MaskedStoreSDNode>(N);
994 // masked truncstore fragments
995 // X86mtruncstore can't be implemented in core DAG files because some targets
996 // doesn't support vector type ( llvm-tblgen will fail)
997 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
998 (masked_store node:$src1, node:$src2, node:$src3), [{
999 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1001 def masked_truncstorevi8 :
1002 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1003 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1004 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1006 def masked_truncstorevi16 :
1007 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1008 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1009 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1011 def masked_truncstorevi32 :
1012 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1013 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1014 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;