1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
33 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
34 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
35 [SDNPHasChain, SDNPOutFlag]>;
36 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
38 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
39 [SDNPHasChain, SDNPInFlag]>;
40 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
42 def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
43 [SDNPHasChain, SDNPOutFlag]>;
44 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
46 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
48 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
51 //===----------------------------------------------------------------------===//
52 // FPStack pattern fragments
53 //===----------------------------------------------------------------------===//
55 def fpimm0 : PatLeaf<(fpimm), [{
56 return N->isExactlyValue(+0.0);
59 def fpimmneg0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(-0.0);
63 def fpimm1 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+1.0);
67 def fpimmneg1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-1.0);
71 // Some 'special' instructions
72 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
73 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
74 (outs), (ins i16mem:$dst, RFP32:$src),
75 "#FP32_TO_INT16_IN_MEM PSEUDO!",
76 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
77 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
78 (outs), (ins i32mem:$dst, RFP32:$src),
79 "#FP32_TO_INT32_IN_MEM PSEUDO!",
80 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
82 (outs), (ins i64mem:$dst, RFP32:$src),
83 "#FP32_TO_INT64_IN_MEM PSEUDO!",
84 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
85 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
86 (outs), (ins i16mem:$dst, RFP64:$src),
87 "#FP64_TO_INT16_IN_MEM PSEUDO!",
88 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
89 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
90 (outs), (ins i32mem:$dst, RFP64:$src),
91 "#FP64_TO_INT32_IN_MEM PSEUDO!",
92 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
94 (outs), (ins i64mem:$dst, RFP64:$src),
95 "#FP64_TO_INT64_IN_MEM PSEUDO!",
96 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
97 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
98 (outs), (ins i16mem:$dst, RFP80:$src),
99 "#FP80_TO_INT16_IN_MEM PSEUDO!",
100 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
101 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
102 (outs), (ins i32mem:$dst, RFP80:$src),
103 "#FP80_TO_INT32_IN_MEM PSEUDO!",
104 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
105 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
106 (outs), (ins i64mem:$dst, RFP80:$src),
107 "#FP80_TO_INT64_IN_MEM PSEUDO!",
108 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
111 let isTerminator = 1 in
112 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
113 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
115 // All FP Stack operations are represented with four instructions here. The
116 // first three instructions, generated by the instruction selector, use "RFP32"
117 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
118 // 64-bit or 80-bit floating point values. These sizes apply to the values,
119 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
120 // copied to each other without losing information. These instructions are all
121 // pseudo instructions and use the "_Fp" suffix.
122 // In some cases there are additional variants with a mixture of different
124 // The second instruction is defined with FPI, which is the actual instruction
125 // emitted by the assembler. These use "RST" registers, although frequently
126 // the actual register(s) used are implicit. These are always 80 bits.
127 // The FP stackifier pass converts one to the other after register allocation
130 // Note that the FpI instruction should have instruction selection info (e.g.
131 // a pattern) and the FPI instruction should have emission info (e.g. opcode
132 // encoding and asm printing info).
134 // Pseudo Instructions for FP stack return values.
135 def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
136 [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
138 def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
139 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
141 def FpGETRESULT80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP,
142 [(set RFP80:$dst, X86fpget)]>; // FPR = ST(0)
144 let Defs = [ST0] in {
145 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
146 [(X86fpset RFP32:$src)]>;// ST(0) = FPR
148 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
149 [(X86fpset RFP64:$src)]>;// ST(0) = FPR
151 def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
152 [(X86fpset RFP80:$src)]>;// ST(0) = FPR
155 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
156 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
157 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
158 // f80 instructions cannot use SSE and use neither of these.
159 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
160 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
161 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
162 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
164 // Register copies. Just copies, the shortening ones do not truncate.
165 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
166 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
167 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
168 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
169 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
170 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
171 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
172 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
173 def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
175 // Factoring for arithmetic.
176 multiclass FPBinary_rr<SDNode OpNode> {
177 // Register op register -> register
178 // These are separated out because they have no reversed form.
179 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
180 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
181 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
182 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
183 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
184 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
186 // The FopST0 series are not included here because of the irregularities
187 // in where the 'r' goes in assembly output.
188 // These instructions cannot address 80-bit memory.
189 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
190 // ST(0) = ST(0) + [mem]
191 def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
193 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
194 def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
196 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
197 def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
199 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
200 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
202 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
203 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
205 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
206 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
207 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
208 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
209 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))>;
210 // ST(0) = ST(0) + [memint]
211 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
212 [(set RFP32:$dst, (OpNode RFP32:$src1,
213 (X86fild addr:$src2, i16)))]>;
214 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
215 [(set RFP32:$dst, (OpNode RFP32:$src1,
216 (X86fild addr:$src2, i32)))]>;
217 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
218 [(set RFP64:$dst, (OpNode RFP64:$src1,
219 (X86fild addr:$src2, i16)))]>;
220 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
221 [(set RFP64:$dst, (OpNode RFP64:$src1,
222 (X86fild addr:$src2, i32)))]>;
223 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
224 [(set RFP80:$dst, (OpNode RFP80:$src1,
225 (X86fild addr:$src2, i16)))]>;
226 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
227 [(set RFP80:$dst, (OpNode RFP80:$src1,
228 (X86fild addr:$src2, i32)))]>;
229 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
230 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))>;
231 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
232 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))>;
235 defm ADD : FPBinary_rr<fadd>;
236 defm SUB : FPBinary_rr<fsub>;
237 defm MUL : FPBinary_rr<fmul>;
238 defm DIV : FPBinary_rr<fdiv>;
239 defm ADD : FPBinary<fadd, MRM0m, "add">;
240 defm SUB : FPBinary<fsub, MRM4m, "sub">;
241 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
242 defm MUL : FPBinary<fmul, MRM1m, "mul">;
243 defm DIV : FPBinary<fdiv, MRM6m, "div">;
244 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
246 class FPST0rInst<bits<8> o, string asm>
247 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
248 class FPrST0Inst<bits<8> o, string asm>
249 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
250 class FPrST0PInst<bits<8> o, string asm>
251 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
253 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
254 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
255 // we have to put some 'r's in and take them out of weird places.
256 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
257 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
258 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
259 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
260 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
261 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
262 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
263 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
264 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
265 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
266 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
267 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
268 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
269 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
270 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
271 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
272 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
273 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
276 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
277 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
278 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
279 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
280 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
281 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
282 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
283 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
286 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
287 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
288 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
289 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
290 defm COS : FPUnary<fcos, 0xFF, "fcos">;
292 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP,
294 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP,
296 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP,
298 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
300 // Floating point cmovs.
301 multiclass FPCMov<PatLeaf cc> {
302 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), CondMovFP,
303 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
305 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP,
306 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
308 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), CondMovFP,
309 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
312 let isTwoAddress = 1 in {
313 defm CMOVB : FPCMov<X86_COND_B>;
314 defm CMOVBE : FPCMov<X86_COND_BE>;
315 defm CMOVE : FPCMov<X86_COND_E>;
316 defm CMOVP : FPCMov<X86_COND_P>;
317 defm CMOVNB : FPCMov<X86_COND_AE>;
318 defm CMOVNBE: FPCMov<X86_COND_A>;
319 defm CMOVNE : FPCMov<X86_COND_NE>;
320 defm CMOVNP : FPCMov<X86_COND_NP>;
323 // These are not factored because there's no clean way to pass DA/DB.
324 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
325 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
326 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
327 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
328 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
329 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
330 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
331 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
332 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
333 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
334 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
335 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
336 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
337 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
338 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
339 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
341 // Floating point loads & stores.
343 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
344 [(set RFP32:$dst, (loadf32 addr:$src))]>;
345 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
346 [(set RFP64:$dst, (loadf64 addr:$src))]>;
347 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
348 [(set RFP80:$dst, (loadf80 addr:$src))]>;
350 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
351 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
352 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
353 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
354 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
355 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
356 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
357 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
358 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
359 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
360 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
361 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
362 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
363 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
364 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
365 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
366 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
367 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
368 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
369 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
370 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
371 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
372 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
373 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
375 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
376 [(store RFP32:$src, addr:$op)]>;
377 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
378 [(truncstoref32 RFP64:$src, addr:$op)]>;
379 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
380 [(store RFP64:$src, addr:$op)]>;
381 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
382 [(truncstoref32 RFP80:$src, addr:$op)]>;
383 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
384 [(truncstoref64 RFP80:$src, addr:$op)]>;
385 // FST does not support 80-bit memory target; FSTP must be used.
387 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
388 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
389 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
390 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
391 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
392 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
393 [(store RFP80:$src, addr:$op)]>;
394 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
395 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
396 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
397 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
398 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
399 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
400 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
401 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
402 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
404 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
405 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
406 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
407 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
408 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
409 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
410 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
411 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
412 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
413 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
414 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
415 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
416 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
417 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
418 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
419 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
421 // FISTTP requires SSE3 even though it's a FPStack op.
422 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
423 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
425 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
426 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
428 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
429 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
431 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
432 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
434 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
435 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
437 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
438 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
440 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
441 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
443 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
444 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
446 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
447 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
450 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
451 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
452 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
454 // FP Stack manipulation instructions.
455 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
456 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
457 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
458 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
460 // Floating point constant loads.
461 let isReMaterializable = 1 in {
462 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
463 [(set RFP32:$dst, fpimm0)]>;
464 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
465 [(set RFP32:$dst, fpimm1)]>;
466 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
467 [(set RFP64:$dst, fpimm0)]>;
468 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
469 [(set RFP64:$dst, fpimm1)]>;
470 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
471 [(set RFP80:$dst, fpimm0)]>;
472 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
473 [(set RFP80:$dst, fpimm1)]>;
476 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
477 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
480 // Floating point compares.
481 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
482 []>; // FPSW = cmp ST(0) with ST(i)
483 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
484 [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i)
485 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
486 []>; // FPSW = cmp ST(0) with ST(i)
487 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
488 [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i)
489 def UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
490 []>; // FPSW = cmp ST(0) with ST(i)
491 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
492 [(X86cmp RFP80:$lhs, RFP80:$rhs)]>; // CC = ST(0) cmp ST(i)
494 let Defs = [EFLAGS], Uses = [ST0] in {
495 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
496 (outs), (ins RST:$reg),
498 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
499 (outs), (ins RST:$reg),
501 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
505 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
506 (outs), (ins RST:$reg),
507 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
508 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
509 (outs), (ins RST:$reg),
510 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
513 // Floating point flag ops.
515 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
516 (outs), (ins), "fnstsw", []>, DF;
518 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
519 (outs), (ins i16mem:$dst), "fnstcw\t$dst", []>;
520 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
521 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
523 //===----------------------------------------------------------------------===//
524 // Non-Instruction Patterns
525 //===----------------------------------------------------------------------===//
527 // Required for RET of f32 / f64 / f80 values.
528 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
529 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
530 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
532 // Required for CALL which return f32 / f64 / f80 values.
533 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
534 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
535 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
536 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
537 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
538 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
540 // Floating point constant -0.0 and -1.0
541 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
542 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
543 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
544 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
545 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
546 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
548 // Used to conv. i64 to f64 since there isn't a SSE version.
549 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
551 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStackf32]>;
552 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>, Requires<[FPStackf32]>;
553 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>, Requires<[FPStackf64]>;