1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insertps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
480 X86MemOperand x86memop, PatFrag ld_frag,
483 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
484 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
486 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
488 !strconcat(OpcodeStr,
489 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
494 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
495 i128mem, loadv2i64, VK16WM>,
496 EVEX_V512, EVEX_CD8<32, CD8VT4>;
497 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
498 i256mem, loadv4i64, VK16WM>, VEX_W,
499 EVEX_V512, EVEX_CD8<64, CD8VT4>;
501 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
502 (VPBROADCASTDZrr VR128X:$src)>;
503 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
504 (VPBROADCASTQZrr VR128X:$src)>;
506 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
507 (VBROADCASTSSZrr VR128X:$src)>;
508 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
509 (VBROADCASTSDZrr VR128X:$src)>;
511 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
512 (VBROADCASTSSZrr VR128X:$src)>;
513 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
514 (VBROADCASTSDZrr VR128X:$src)>;
516 // Provide fallback in case the load node that is used in the patterns above
517 // is used by additional users, which prevents the pattern selection.
518 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
519 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
520 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
521 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
524 let Predicates = [HasAVX512] in {
525 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
527 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
528 addr:$src)), sub_ymm)>;
530 //===----------------------------------------------------------------------===//
531 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
534 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
535 RegisterClass DstRC, RegisterClass KRC,
536 ValueType OpVT, ValueType SrcVT> {
537 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
538 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
542 let Predicates = [HasCDI] in {
543 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
544 VK16, v16i32, v16i1>, EVEX_V512;
545 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
546 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
549 //===----------------------------------------------------------------------===//
552 // -- immediate form --
553 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
554 SDNode OpNode, PatFrag mem_frag,
555 X86MemOperand x86memop, ValueType OpVT> {
556 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, i8imm:$src2),
558 !strconcat(OpcodeStr,
559 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
561 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
563 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
564 (ins x86memop:$src1, i8imm:$src2),
565 !strconcat(OpcodeStr,
566 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
568 (OpVT (OpNode (mem_frag addr:$src1),
569 (i8 imm:$src2))))]>, EVEX;
572 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
573 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
574 let ExeDomain = SSEPackedDouble in
575 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
576 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 // -- VPERM - register form --
579 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
580 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2),
584 !strconcat(OpcodeStr,
585 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
587 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
589 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
590 (ins RC:$src1, x86memop:$src2),
591 !strconcat(OpcodeStr,
592 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
594 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
598 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
599 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
600 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
601 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
602 let ExeDomain = SSEPackedSingle in
603 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 let ExeDomain = SSEPackedDouble in
606 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
607 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
609 // -- VPERM2I - 3 source operands form --
610 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
611 PatFrag mem_frag, X86MemOperand x86memop,
612 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
613 let Constraints = "$src1 = $dst" in {
614 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
615 (ins RC:$src1, RC:$src2, RC:$src3),
616 !strconcat(OpcodeStr,
617 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
619 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
622 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
623 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
624 !strconcat(OpcodeStr,
625 " \t{$src3, $src2, $dst {${mask}}|"
626 "$dst {${mask}}, $src2, $src3}"),
627 [(set RC:$dst, (OpVT (vselect KRC:$mask,
628 (OpNode RC:$src1, RC:$src2,
633 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
634 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
635 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
636 !strconcat(OpcodeStr,
637 " \t{$src3, $src2, $dst {${mask}} {z} |",
638 "$dst {${mask}} {z}, $src2, $src3}"),
639 [(set RC:$dst, (OpVT (vselect KRC:$mask,
640 (OpNode RC:$src1, RC:$src2,
643 (v16i32 immAllZerosV))))))]>,
646 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
647 (ins RC:$src1, RC:$src2, x86memop:$src3),
648 !strconcat(OpcodeStr,
649 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
651 (OpVT (OpNode RC:$src1, RC:$src2,
652 (mem_frag addr:$src3))))]>, EVEX_4V;
654 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
655 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
656 !strconcat(OpcodeStr,
657 " \t{$src3, $src2, $dst {${mask}}|"
658 "$dst {${mask}}, $src2, $src3}"),
660 (OpVT (vselect KRC:$mask,
661 (OpNode RC:$src1, RC:$src2,
662 (mem_frag addr:$src3)),
666 let AddedComplexity = 10 in // Prefer over the rrkz variant
667 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
668 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
669 !strconcat(OpcodeStr,
670 " \t{$src3, $src2, $dst {${mask}} {z}|"
671 "$dst {${mask}} {z}, $src2, $src3}"),
673 (OpVT (vselect KRC:$mask,
674 (OpNode RC:$src1, RC:$src2,
675 (mem_frag addr:$src3)),
677 (v16i32 immAllZerosV))))))]>,
681 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
682 i512mem, X86VPermiv3, v16i32, VK16WM>,
683 EVEX_V512, EVEX_CD8<32, CD8VF>;
684 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
685 i512mem, X86VPermiv3, v8i64, VK8WM>,
686 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
687 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
688 i512mem, X86VPermiv3, v16f32, VK16WM>,
689 EVEX_V512, EVEX_CD8<32, CD8VF>;
690 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
691 i512mem, X86VPermiv3, v8f64, VK8WM>,
692 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
694 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
695 PatFrag mem_frag, X86MemOperand x86memop,
696 SDNode OpNode, ValueType OpVT, RegisterClass KRC> :
697 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
699 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
700 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
701 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
704 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
705 X86VPermv3, v16i32, VK16WM>, EVEX_V512, EVEX_CD8<32, CD8VF>;
706 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
707 X86VPermv3, v8i64, VK8WM>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
708 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
709 X86VPermv3, v16f32, VK16WM>, EVEX_V512, EVEX_CD8<32, CD8VF>;
710 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
711 X86VPermv3, v8f64, VK8WM>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
713 //===----------------------------------------------------------------------===//
714 // AVX-512 - BLEND using mask
716 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
717 RegisterClass KRC, RegisterClass RC,
718 X86MemOperand x86memop, PatFrag mem_frag,
719 SDNode OpNode, ValueType vt> {
720 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
721 (ins KRC:$mask, RC:$src1, RC:$src2),
722 !strconcat(OpcodeStr,
723 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
724 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
725 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
727 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
728 (ins KRC:$mask, RC:$src1, x86memop:$src2),
729 !strconcat(OpcodeStr,
730 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
731 []>, EVEX_4V, EVEX_K;
734 let ExeDomain = SSEPackedSingle in
735 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
736 VK16WM, VR512, f512mem,
737 memopv16f32, vselect, v16f32>,
738 EVEX_CD8<32, CD8VF>, EVEX_V512;
739 let ExeDomain = SSEPackedDouble in
740 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
741 VK8WM, VR512, f512mem,
742 memopv8f64, vselect, v8f64>,
743 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
745 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
746 (v16f32 VR512:$src2), (i16 GR16:$mask))),
747 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
748 VR512:$src1, VR512:$src2)>;
750 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
751 (v8f64 VR512:$src2), (i8 GR8:$mask))),
752 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
753 VR512:$src1, VR512:$src2)>;
755 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
756 VK16WM, VR512, f512mem,
757 memopv16i32, vselect, v16i32>,
758 EVEX_CD8<32, CD8VF>, EVEX_V512;
760 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
761 VK8WM, VR512, f512mem,
762 memopv8i64, vselect, v8i64>,
763 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
765 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
766 (v16i32 VR512:$src2), (i16 GR16:$mask))),
767 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
768 VR512:$src1, VR512:$src2)>;
770 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
771 (v8i64 VR512:$src2), (i8 GR8:$mask))),
772 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
773 VR512:$src1, VR512:$src2)>;
775 let Predicates = [HasAVX512] in {
776 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
777 (v8f32 VR256X:$src2))),
779 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
780 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
781 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
783 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
784 (v8i32 VR256X:$src2))),
786 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
787 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
788 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
790 //===----------------------------------------------------------------------===//
791 // Compare Instructions
792 //===----------------------------------------------------------------------===//
794 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
795 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
796 Operand CC, SDNode OpNode, ValueType VT,
797 PatFrag ld_frag, string asm, string asm_alt> {
798 def rr : AVX512Ii8<0xC2, MRMSrcReg,
799 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
800 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
801 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
802 def rm : AVX512Ii8<0xC2, MRMSrcMem,
803 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
804 [(set VK1:$dst, (OpNode (VT RC:$src1),
805 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
806 let isAsmParserOnly = 1, hasSideEffects = 0 in {
807 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
808 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
809 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
810 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
811 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
812 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
816 let Predicates = [HasAVX512] in {
817 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
818 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
819 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
821 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
822 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
823 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
827 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
828 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
829 SDNode OpNode, ValueType vt> {
830 def rr : AVX512BI<opc, MRMSrcReg,
831 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
832 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
833 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
834 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
835 def rm : AVX512BI<opc, MRMSrcMem,
836 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
837 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
838 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
839 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
842 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
843 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
845 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
846 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
847 VEX_W, EVEX_CD8<64, CD8VF>;
849 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
850 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
852 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
853 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
854 VEX_W, EVEX_CD8<64, CD8VF>;
856 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
857 (COPY_TO_REGCLASS (VPCMPGTDZrr
858 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
859 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
861 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
862 (COPY_TO_REGCLASS (VPCMPEQDZrr
863 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
864 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
866 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
867 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
868 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
869 def rri : AVX512AIi8<opc, MRMSrcReg,
870 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
871 !strconcat("vpcmp${cc}", Suffix,
872 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
873 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
874 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
875 def rmi : AVX512AIi8<opc, MRMSrcMem,
876 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
877 !strconcat("vpcmp${cc}", Suffix,
878 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
879 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
880 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
881 // Accept explicit immediate argument form instead of comparison code.
882 let isAsmParserOnly = 1, hasSideEffects = 0 in {
883 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
884 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
885 !strconcat("vpcmp", Suffix,
886 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
887 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
888 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
889 (outs KRC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
890 !strconcat("vpcmp", Suffix,
891 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
892 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
893 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
894 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
895 !strconcat("vpcmp", Suffix,
896 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
897 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
898 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
899 (outs KRC:$dst), (ins KRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
900 !strconcat("vpcmp", Suffix,
901 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
902 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
906 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
907 X86cmpm, v16i32, AVXCC, "d">,
908 EVEX_V512, EVEX_CD8<32, CD8VF>;
909 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
910 X86cmpmu, v16i32, AVXCC, "ud">,
911 EVEX_V512, EVEX_CD8<32, CD8VF>;
913 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
914 X86cmpm, v8i64, AVXCC, "q">,
915 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
916 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
917 X86cmpmu, v8i64, AVXCC, "uq">,
918 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
920 // avx512_cmp_packed - compare packed instructions
921 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
922 X86MemOperand x86memop, ValueType vt,
923 string suffix, Domain d> {
924 def rri : AVX512PIi8<0xC2, MRMSrcReg,
925 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
926 !strconcat("vcmp${cc}", suffix,
927 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
928 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
929 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
930 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
931 !strconcat("vcmp${cc}", suffix,
932 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
934 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
935 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
936 !strconcat("vcmp${cc}", suffix,
937 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
939 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
941 // Accept explicit immediate argument form instead of comparison code.
942 let isAsmParserOnly = 1, hasSideEffects = 0 in {
943 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
944 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
945 !strconcat("vcmp", suffix,
946 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
947 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
948 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
949 !strconcat("vcmp", suffix,
950 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
954 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
955 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
957 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
958 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
961 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
962 (COPY_TO_REGCLASS (VCMPPSZrri
963 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
964 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
966 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
967 (COPY_TO_REGCLASS (VPCMPDZrri
968 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
969 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
971 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
972 (COPY_TO_REGCLASS (VPCMPUDZrri
973 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
974 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
977 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
978 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
980 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
981 (I8Imm imm:$cc)), GR16)>;
983 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
984 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
986 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
987 (I8Imm imm:$cc)), GR8)>;
989 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
990 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
992 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
993 (I8Imm imm:$cc)), GR16)>;
995 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
996 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
998 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
999 (I8Imm imm:$cc)), GR8)>;
1001 // Mask register copy, including
1002 // - copy between mask registers
1003 // - load/store mask registers
1004 // - copy from GPR to mask register and vice versa
1006 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1007 string OpcodeStr, RegisterClass KRC,
1008 ValueType vt, X86MemOperand x86memop> {
1009 let hasSideEffects = 0 in {
1010 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1011 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1013 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1014 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1015 [(set KRC:$dst, (vt (load addr:$src)))]>;
1017 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1018 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1022 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1024 RegisterClass KRC, RegisterClass GRC> {
1025 let hasSideEffects = 0 in {
1026 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1027 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1028 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1029 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1033 let Predicates = [HasAVX512] in {
1034 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1036 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1040 let Predicates = [HasAVX512] in {
1041 // GR16 from/to 16-bit mask
1042 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1043 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1044 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1045 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1047 // Store kreg in memory
1048 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
1049 (KMOVWmk addr:$dst, VK16:$src)>;
1051 def : Pat<(store VK8:$src, addr:$dst),
1052 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1054 def : Pat<(i1 (load addr:$src)),
1055 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1057 def : Pat<(v8i1 (load addr:$src)),
1058 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1060 def : Pat<(i1 (trunc (i32 GR32:$src))),
1061 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1063 def : Pat<(i1 (trunc (i8 GR8:$src))),
1065 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1067 def : Pat<(i1 (trunc (i16 GR16:$src))),
1069 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1072 def : Pat<(i32 (zext VK1:$src)),
1073 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1074 def : Pat<(i8 (zext VK1:$src)),
1077 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1078 def : Pat<(i64 (zext VK1:$src)),
1079 (AND64ri8 (SUBREG_TO_REG (i64 0),
1080 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1081 def : Pat<(i16 (zext VK1:$src)),
1083 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1085 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1086 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1087 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1088 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1090 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1091 let Predicates = [HasAVX512] in {
1092 // GR from/to 8-bit mask without native support
1093 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1095 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1097 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1099 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1102 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1103 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1104 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1105 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1109 // Mask unary operation
1111 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1112 RegisterClass KRC, SDPatternOperator OpNode> {
1113 let Predicates = [HasAVX512] in
1114 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1115 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1116 [(set KRC:$dst, (OpNode KRC:$src))]>;
1119 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1120 SDPatternOperator OpNode> {
1121 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1125 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1127 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1128 let Predicates = [HasAVX512] in
1129 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1131 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1132 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1134 defm : avx512_mask_unop_int<"knot", "KNOT">;
1136 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1137 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1138 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1140 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1141 def : Pat<(not VK8:$src),
1143 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1145 // Mask binary operation
1146 // - KAND, KANDN, KOR, KXNOR, KXOR
1147 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1148 RegisterClass KRC, SDPatternOperator OpNode> {
1149 let Predicates = [HasAVX512] in
1150 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1151 !strconcat(OpcodeStr,
1152 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1153 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1156 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1157 SDPatternOperator OpNode> {
1158 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1162 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1163 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1165 let isCommutable = 1 in {
1166 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1167 let isCommutable = 0 in
1168 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1169 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1170 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1171 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1174 def : Pat<(xor VK1:$src1, VK1:$src2),
1175 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1176 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1178 def : Pat<(or VK1:$src1, VK1:$src2),
1179 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1180 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1182 def : Pat<(and VK1:$src1, VK1:$src2),
1183 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1184 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1186 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1187 let Predicates = [HasAVX512] in
1188 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1189 (i16 GR16:$src1), (i16 GR16:$src2)),
1190 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1191 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1192 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1195 defm : avx512_mask_binop_int<"kand", "KAND">;
1196 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1197 defm : avx512_mask_binop_int<"kor", "KOR">;
1198 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1199 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1201 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1202 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1203 let Predicates = [HasAVX512] in
1204 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1206 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1207 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1210 defm : avx512_binop_pat<and, KANDWrr>;
1211 defm : avx512_binop_pat<andn, KANDNWrr>;
1212 defm : avx512_binop_pat<or, KORWrr>;
1213 defm : avx512_binop_pat<xnor, KXNORWrr>;
1214 defm : avx512_binop_pat<xor, KXORWrr>;
1217 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1218 RegisterClass KRC> {
1219 let Predicates = [HasAVX512] in
1220 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1221 !strconcat(OpcodeStr,
1222 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1225 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1226 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1230 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1231 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1232 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1233 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1236 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1237 let Predicates = [HasAVX512] in
1238 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1239 (i16 GR16:$src1), (i16 GR16:$src2)),
1240 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1241 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1242 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1244 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1247 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1249 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1250 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1251 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1252 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1255 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1256 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1260 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1262 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1263 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1264 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1267 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1269 let Predicates = [HasAVX512] in
1270 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1271 !strconcat(OpcodeStr,
1272 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1273 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1276 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1278 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1282 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1283 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1285 // Mask setting all 0s or 1s
1286 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1287 let Predicates = [HasAVX512] in
1288 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1289 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1290 [(set KRC:$dst, (VT Val))]>;
1293 multiclass avx512_mask_setop_w<PatFrag Val> {
1294 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1295 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1298 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1299 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1301 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1302 let Predicates = [HasAVX512] in {
1303 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1304 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1305 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1306 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1307 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1309 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1310 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1312 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1313 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1315 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1316 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1318 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1319 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1321 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1322 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1323 //===----------------------------------------------------------------------===//
1324 // AVX-512 - Aligned and unaligned load and store
1327 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1328 X86MemOperand x86memop, PatFrag ld_frag,
1329 string asm, Domain d,
1330 ValueType vt, bit IsReMaterializable = 1> {
1331 let hasSideEffects = 0 in {
1332 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1333 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1335 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1337 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1338 [], d>, EVEX, EVEX_KZ;
1340 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1341 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1342 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1343 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1344 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1345 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1346 (ins RC:$src1, KRC:$mask, RC:$src2),
1348 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1351 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1352 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1354 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1355 [], d>, EVEX, EVEX_K;
1358 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1359 (ins KRC:$mask, x86memop:$src2),
1361 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1362 [], d>, EVEX, EVEX_KZ;
1365 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1366 X86MemOperand x86memop, PatFrag store_frag,
1367 string asm, Domain d, ValueType vt> {
1368 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1369 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1370 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1372 let Constraints = "$src1 = $dst" in
1373 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1374 (ins RC:$src1, KRC:$mask, RC:$src2),
1376 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1378 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1379 (ins KRC:$mask, RC:$src),
1381 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1382 [], d>, EVEX, EVEX_KZ;
1384 let mayStore = 1 in {
1385 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1386 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1387 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1388 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1389 (ins x86memop:$dst, KRC:$mask, RC:$src),
1391 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1392 [], d>, EVEX, EVEX_K;
1393 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1394 (ins x86memop:$dst, KRC:$mask, RC:$src),
1396 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1397 [], d>, EVEX, EVEX_KZ;
1401 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1402 "vmovaps", SSEPackedSingle, v16f32>,
1403 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1404 "vmovaps", SSEPackedSingle, v16f32>,
1405 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1406 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1407 "vmovapd", SSEPackedDouble, v8f64>,
1408 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1409 "vmovapd", SSEPackedDouble, v8f64>,
1410 PD, EVEX_V512, VEX_W,
1411 EVEX_CD8<64, CD8VF>;
1412 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1413 "vmovups", SSEPackedSingle, v16f32>,
1414 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1415 "vmovups", SSEPackedSingle, v16f32>,
1416 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1417 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1418 "vmovupd", SSEPackedDouble, v8f64, 0>,
1419 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1420 "vmovupd", SSEPackedDouble, v8f64>,
1421 PD, EVEX_V512, VEX_W,
1422 EVEX_CD8<64, CD8VF>;
1423 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1424 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1425 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1427 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1428 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1429 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1431 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1433 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1435 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1437 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1440 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1441 "vmovdqa32", SSEPackedInt, v16i32>,
1442 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1443 "vmovdqa32", SSEPackedInt, v16i32>,
1444 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1445 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1446 "vmovdqa64", SSEPackedInt, v8i64>,
1447 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1448 "vmovdqa64", SSEPackedInt, v8i64>,
1449 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1450 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1451 "vmovdqu32", SSEPackedInt, v16i32>,
1452 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1453 "vmovdqu32", SSEPackedInt, v16i32>,
1454 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1455 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1456 "vmovdqu64", SSEPackedInt, v8i64>,
1457 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1458 "vmovdqu64", SSEPackedInt, v8i64>,
1459 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1461 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1462 (v16i32 immAllZerosV), GR16:$mask)),
1463 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1465 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1466 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1467 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1469 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1471 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1473 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1475 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1478 let AddedComplexity = 20 in {
1479 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1480 (bc_v8i64 (v16i32 immAllZerosV)))),
1481 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1483 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1484 (v8i64 VR512:$src))),
1485 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1488 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1489 (v16i32 immAllZerosV))),
1490 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1492 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1493 (v16i32 VR512:$src))),
1494 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1496 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1497 (v16f32 VR512:$src2))),
1498 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1499 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1500 (v8f64 VR512:$src2))),
1501 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1502 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1503 (v16i32 VR512:$src2))),
1504 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1505 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1506 (v8i64 VR512:$src2))),
1507 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1509 // Move Int Doubleword to Packed Double Int
1511 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1512 "vmovd\t{$src, $dst|$dst, $src}",
1514 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1516 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1517 "vmovd\t{$src, $dst|$dst, $src}",
1519 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1520 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1521 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1522 "vmovq\t{$src, $dst|$dst, $src}",
1524 (v2i64 (scalar_to_vector GR64:$src)))],
1525 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1526 let isCodeGenOnly = 1 in {
1527 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1528 "vmovq\t{$src, $dst|$dst, $src}",
1529 [(set FR64:$dst, (bitconvert GR64:$src))],
1530 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1531 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1532 "vmovq\t{$src, $dst|$dst, $src}",
1533 [(set GR64:$dst, (bitconvert FR64:$src))],
1534 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1536 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1537 "vmovq\t{$src, $dst|$dst, $src}",
1538 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1539 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1540 EVEX_CD8<64, CD8VT1>;
1542 // Move Int Doubleword to Single Scalar
1544 let isCodeGenOnly = 1 in {
1545 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1546 "vmovd\t{$src, $dst|$dst, $src}",
1547 [(set FR32X:$dst, (bitconvert GR32:$src))],
1548 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1550 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1551 "vmovd\t{$src, $dst|$dst, $src}",
1552 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1553 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1556 // Move doubleword from xmm register to r/m32
1558 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1559 "vmovd\t{$src, $dst|$dst, $src}",
1560 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1561 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1563 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1564 (ins i32mem:$dst, VR128X:$src),
1565 "vmovd\t{$src, $dst|$dst, $src}",
1566 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1567 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1568 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1570 // Move quadword from xmm1 register to r/m64
1572 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1573 "vmovq\t{$src, $dst|$dst, $src}",
1574 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1576 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1577 Requires<[HasAVX512, In64BitMode]>;
1579 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1580 (ins i64mem:$dst, VR128X:$src),
1581 "vmovq\t{$src, $dst|$dst, $src}",
1582 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1583 addr:$dst)], IIC_SSE_MOVDQ>,
1584 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1585 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1587 // Move Scalar Single to Double Int
1589 let isCodeGenOnly = 1 in {
1590 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1592 "vmovd\t{$src, $dst|$dst, $src}",
1593 [(set GR32:$dst, (bitconvert FR32X:$src))],
1594 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1595 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1596 (ins i32mem:$dst, FR32X:$src),
1597 "vmovd\t{$src, $dst|$dst, $src}",
1598 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1599 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1602 // Move Quadword Int to Packed Quadword Int
1604 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1606 "vmovq\t{$src, $dst|$dst, $src}",
1608 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1609 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1611 //===----------------------------------------------------------------------===//
1612 // AVX-512 MOVSS, MOVSD
1613 //===----------------------------------------------------------------------===//
1615 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1616 SDNode OpNode, ValueType vt,
1617 X86MemOperand x86memop, PatFrag mem_pat> {
1618 let hasSideEffects = 0 in {
1619 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1620 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1621 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1622 (scalar_to_vector RC:$src2))))],
1623 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1624 let Constraints = "$src1 = $dst" in
1625 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1626 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1628 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1629 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1630 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1631 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1632 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1634 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1635 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1636 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1638 } //hasSideEffects = 0
1641 let ExeDomain = SSEPackedSingle in
1642 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1643 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1645 let ExeDomain = SSEPackedDouble in
1646 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1647 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1649 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1650 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1651 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1653 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1654 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1655 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1657 // For the disassembler
1658 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1659 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1660 (ins VR128X:$src1, FR32X:$src2),
1661 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1663 XS, EVEX_4V, VEX_LIG;
1664 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1665 (ins VR128X:$src1, FR64X:$src2),
1666 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1668 XD, EVEX_4V, VEX_LIG, VEX_W;
1671 let Predicates = [HasAVX512] in {
1672 let AddedComplexity = 15 in {
1673 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1674 // MOVS{S,D} to the lower bits.
1675 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1676 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1677 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1678 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1679 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1680 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1681 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1682 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1684 // Move low f32 and clear high bits.
1685 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1686 (SUBREG_TO_REG (i32 0),
1687 (VMOVSSZrr (v4f32 (V_SET0)),
1688 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1689 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1690 (SUBREG_TO_REG (i32 0),
1691 (VMOVSSZrr (v4i32 (V_SET0)),
1692 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1695 let AddedComplexity = 20 in {
1696 // MOVSSrm zeros the high parts of the register; represent this
1697 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1698 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1699 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1700 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1701 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1702 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1703 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1705 // MOVSDrm zeros the high parts of the register; represent this
1706 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1707 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1708 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1709 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1710 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1711 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1712 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1713 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1714 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1715 def : Pat<(v2f64 (X86vzload addr:$src)),
1716 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1718 // Represent the same patterns above but in the form they appear for
1720 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1721 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1722 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1723 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1724 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1725 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1726 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1727 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1728 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1730 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1731 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1732 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1733 FR32X:$src)), sub_xmm)>;
1734 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1735 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1736 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1737 FR64X:$src)), sub_xmm)>;
1738 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1739 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1740 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1742 // Move low f64 and clear high bits.
1743 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1744 (SUBREG_TO_REG (i32 0),
1745 (VMOVSDZrr (v2f64 (V_SET0)),
1746 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1748 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1749 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1750 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1752 // Extract and store.
1753 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1755 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1756 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1758 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1760 // Shuffle with VMOVSS
1761 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1762 (VMOVSSZrr (v4i32 VR128X:$src1),
1763 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1764 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1765 (VMOVSSZrr (v4f32 VR128X:$src1),
1766 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1769 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1770 (SUBREG_TO_REG (i32 0),
1771 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1772 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1774 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1775 (SUBREG_TO_REG (i32 0),
1776 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1777 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1780 // Shuffle with VMOVSD
1781 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1782 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1783 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1784 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1785 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1786 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1787 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1788 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1791 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1792 (SUBREG_TO_REG (i32 0),
1793 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1794 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1796 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1797 (SUBREG_TO_REG (i32 0),
1798 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1799 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1802 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1803 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1804 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1805 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1806 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1807 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1808 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1809 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1812 let AddedComplexity = 15 in
1813 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1815 "vmovq\t{$src, $dst|$dst, $src}",
1816 [(set VR128X:$dst, (v2i64 (X86vzmovl
1817 (v2i64 VR128X:$src))))],
1818 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1820 let AddedComplexity = 20 in
1821 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1823 "vmovq\t{$src, $dst|$dst, $src}",
1824 [(set VR128X:$dst, (v2i64 (X86vzmovl
1825 (loadv2i64 addr:$src))))],
1826 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1827 EVEX_CD8<8, CD8VT8>;
1829 let Predicates = [HasAVX512] in {
1830 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1831 let AddedComplexity = 20 in {
1832 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1833 (VMOVDI2PDIZrm addr:$src)>;
1834 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1835 (VMOV64toPQIZrr GR64:$src)>;
1836 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1837 (VMOVDI2PDIZrr GR32:$src)>;
1839 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1840 (VMOVDI2PDIZrm addr:$src)>;
1841 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1842 (VMOVDI2PDIZrm addr:$src)>;
1843 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1844 (VMOVZPQILo2PQIZrm addr:$src)>;
1845 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1846 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1847 def : Pat<(v2i64 (X86vzload addr:$src)),
1848 (VMOVZPQILo2PQIZrm addr:$src)>;
1851 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1852 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1853 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1854 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1855 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1856 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1857 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1860 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1861 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1863 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1864 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1866 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1867 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1869 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1870 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1872 //===----------------------------------------------------------------------===//
1873 // AVX-512 - Non-temporals
1874 //===----------------------------------------------------------------------===//
1876 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1878 "vmovntdqa\t{$src, $dst|$dst, $src}",
1880 (int_x86_avx512_movntdqa addr:$src))]>,
1881 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1883 // Prefer non-temporal over temporal versions
1884 let AddedComplexity = 400, SchedRW = [WriteStore] in {
1886 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
1887 (ins f512mem:$dst, VR512:$src),
1888 "vmovntps\t{$src, $dst|$dst, $src}",
1889 [(alignednontemporalstore (v16f32 VR512:$src),
1892 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1894 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
1895 (ins f512mem:$dst, VR512:$src),
1896 "vmovntpd\t{$src, $dst|$dst, $src}",
1897 [(alignednontemporalstore (v8f64 VR512:$src),
1900 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1903 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
1904 (ins i512mem:$dst, VR512:$src),
1905 "vmovntdq\t{$src, $dst|$dst, $src}",
1906 [(alignednontemporalstore (v8i64 VR512:$src),
1909 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1912 //===----------------------------------------------------------------------===//
1913 // AVX-512 - Integer arithmetic
1915 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1916 ValueType OpVT, RegisterClass KRC,
1917 RegisterClass RC, PatFrag memop_frag,
1918 X86MemOperand x86memop, PatFrag scalar_mfrag,
1919 X86MemOperand x86scalar_mop, string BrdcstStr,
1920 OpndItins itins, bit IsCommutable = 0> {
1921 let isCommutable = IsCommutable in
1922 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1923 (ins RC:$src1, RC:$src2),
1924 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1925 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1927 let AddedComplexity = 30 in {
1928 let Constraints = "$src0 = $dst" in
1929 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1930 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1931 !strconcat(OpcodeStr,
1932 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1933 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1934 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1936 itins.rr>, EVEX_4V, EVEX_K;
1937 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1938 (ins KRC:$mask, RC:$src1, RC:$src2),
1939 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1940 "|$dst {${mask}} {z}, $src1, $src2}"),
1941 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1942 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1943 (OpVT immAllZerosV))))],
1944 itins.rr>, EVEX_4V, EVEX_KZ;
1947 let mayLoad = 1 in {
1948 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1949 (ins RC:$src1, x86memop:$src2),
1950 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1951 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1953 let AddedComplexity = 30 in {
1954 let Constraints = "$src0 = $dst" in
1955 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1956 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1957 !strconcat(OpcodeStr,
1958 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1959 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1960 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1962 itins.rm>, EVEX_4V, EVEX_K;
1963 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1964 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1965 !strconcat(OpcodeStr,
1966 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1967 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1968 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1969 (OpVT immAllZerosV))))],
1970 itins.rm>, EVEX_4V, EVEX_KZ;
1972 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1973 (ins RC:$src1, x86scalar_mop:$src2),
1974 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1975 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1976 [(set RC:$dst, (OpNode RC:$src1,
1977 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1978 itins.rm>, EVEX_4V, EVEX_B;
1979 let AddedComplexity = 30 in {
1980 let Constraints = "$src0 = $dst" in
1981 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1982 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1983 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1984 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1986 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1987 (OpNode (OpVT RC:$src1),
1988 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1990 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1991 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1992 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1993 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1994 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1996 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1997 (OpNode (OpVT RC:$src1),
1998 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1999 (OpVT immAllZerosV))))],
2000 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2005 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2006 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2007 PatFrag memop_frag, X86MemOperand x86memop,
2008 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2009 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2010 let isCommutable = IsCommutable in
2012 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2013 (ins RC:$src1, RC:$src2),
2014 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2016 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2017 (ins KRC:$mask, RC:$src1, RC:$src2),
2018 !strconcat(OpcodeStr,
2019 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2020 [], itins.rr>, EVEX_4V, EVEX_K;
2021 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2022 (ins KRC:$mask, RC:$src1, RC:$src2),
2023 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2024 "|$dst {${mask}} {z}, $src1, $src2}"),
2025 [], itins.rr>, EVEX_4V, EVEX_KZ;
2027 let mayLoad = 1 in {
2028 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2029 (ins RC:$src1, x86memop:$src2),
2030 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2032 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2033 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2034 !strconcat(OpcodeStr,
2035 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2036 [], itins.rm>, EVEX_4V, EVEX_K;
2037 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2038 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2039 !strconcat(OpcodeStr,
2040 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2041 [], itins.rm>, EVEX_4V, EVEX_KZ;
2042 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2043 (ins RC:$src1, x86scalar_mop:$src2),
2044 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2045 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2046 [], itins.rm>, EVEX_4V, EVEX_B;
2047 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2048 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2049 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2050 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2052 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2053 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2054 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2055 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2056 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2058 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2062 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2063 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2064 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2066 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2067 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2068 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2070 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2071 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2072 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2074 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2075 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2076 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2078 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2079 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2080 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2082 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2083 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2084 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2085 EVEX_CD8<64, CD8VF>, VEX_W;
2087 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2088 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2089 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2091 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2092 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2094 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2095 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2096 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2097 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2098 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2099 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2101 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2102 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2103 SSE_INTALU_ITINS_P, 1>,
2104 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2105 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2106 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2107 SSE_INTALU_ITINS_P, 0>,
2108 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2110 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2111 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2112 SSE_INTALU_ITINS_P, 1>,
2113 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2114 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2115 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2116 SSE_INTALU_ITINS_P, 0>,
2117 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2119 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2120 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2121 SSE_INTALU_ITINS_P, 1>,
2122 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2123 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2124 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2125 SSE_INTALU_ITINS_P, 0>,
2126 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2128 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2129 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2130 SSE_INTALU_ITINS_P, 1>,
2131 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2132 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2133 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2134 SSE_INTALU_ITINS_P, 0>,
2135 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2137 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2138 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2139 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2140 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2141 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2142 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2143 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2144 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2145 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2146 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2147 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2148 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2149 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2150 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2151 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2152 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2153 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2154 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2155 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2156 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2157 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2158 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2159 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2160 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2161 //===----------------------------------------------------------------------===//
2162 // AVX-512 - Unpack Instructions
2163 //===----------------------------------------------------------------------===//
2165 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2166 PatFrag mem_frag, RegisterClass RC,
2167 X86MemOperand x86memop, string asm,
2169 def rr : AVX512PI<opc, MRMSrcReg,
2170 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2172 (vt (OpNode RC:$src1, RC:$src2)))],
2174 def rm : AVX512PI<opc, MRMSrcMem,
2175 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2177 (vt (OpNode RC:$src1,
2178 (bitconvert (mem_frag addr:$src2)))))],
2182 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2183 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2184 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2185 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2186 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2187 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2188 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2189 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2190 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2191 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2192 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2193 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2195 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2196 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2197 X86MemOperand x86memop> {
2198 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2199 (ins RC:$src1, RC:$src2),
2200 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2201 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2202 IIC_SSE_UNPCK>, EVEX_4V;
2203 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2204 (ins RC:$src1, x86memop:$src2),
2205 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2206 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2207 (bitconvert (memop_frag addr:$src2)))))],
2208 IIC_SSE_UNPCK>, EVEX_4V;
2210 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2211 VR512, memopv16i32, i512mem>, EVEX_V512,
2212 EVEX_CD8<32, CD8VF>;
2213 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2214 VR512, memopv8i64, i512mem>, EVEX_V512,
2215 VEX_W, EVEX_CD8<64, CD8VF>;
2216 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2217 VR512, memopv16i32, i512mem>, EVEX_V512,
2218 EVEX_CD8<32, CD8VF>;
2219 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2220 VR512, memopv8i64, i512mem>, EVEX_V512,
2221 VEX_W, EVEX_CD8<64, CD8VF>;
2222 //===----------------------------------------------------------------------===//
2226 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2227 SDNode OpNode, PatFrag mem_frag,
2228 X86MemOperand x86memop, ValueType OpVT> {
2229 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2230 (ins RC:$src1, i8imm:$src2),
2231 !strconcat(OpcodeStr,
2232 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2234 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2236 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2237 (ins x86memop:$src1, i8imm:$src2),
2238 !strconcat(OpcodeStr,
2239 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2241 (OpVT (OpNode (mem_frag addr:$src1),
2242 (i8 imm:$src2))))]>, EVEX;
2245 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2246 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2248 let ExeDomain = SSEPackedSingle in
2249 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2250 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2251 EVEX_CD8<32, CD8VF>;
2252 let ExeDomain = SSEPackedDouble in
2253 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2254 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2255 VEX_W, EVEX_CD8<32, CD8VF>;
2257 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2258 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2259 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2260 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2262 //===----------------------------------------------------------------------===//
2263 // AVX-512 Logical Instructions
2264 //===----------------------------------------------------------------------===//
2266 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2267 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2268 EVEX_V512, EVEX_CD8<32, CD8VF>;
2269 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2270 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2271 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2272 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2273 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2274 EVEX_V512, EVEX_CD8<32, CD8VF>;
2275 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2276 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2277 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2278 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2279 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2280 EVEX_V512, EVEX_CD8<32, CD8VF>;
2281 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2282 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2283 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2284 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2285 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2286 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2287 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2288 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2289 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2291 //===----------------------------------------------------------------------===//
2292 // AVX-512 FP arithmetic
2293 //===----------------------------------------------------------------------===//
2295 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2297 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2298 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2299 EVEX_CD8<32, CD8VT1>;
2300 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2301 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2302 EVEX_CD8<64, CD8VT1>;
2305 let isCommutable = 1 in {
2306 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2307 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2308 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2309 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2311 let isCommutable = 0 in {
2312 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2313 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2316 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2318 RegisterClass RC, ValueType vt,
2319 X86MemOperand x86memop, PatFrag mem_frag,
2320 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2322 Domain d, OpndItins itins, bit commutable> {
2323 let isCommutable = commutable in {
2324 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2325 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2326 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2329 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2330 !strconcat(OpcodeStr,
2331 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2332 [], itins.rr, d>, EVEX_4V, EVEX_K;
2334 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2335 !strconcat(OpcodeStr,
2336 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2337 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2340 let mayLoad = 1 in {
2341 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2342 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2343 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2344 itins.rm, d>, EVEX_4V;
2346 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2347 (ins RC:$src1, x86scalar_mop:$src2),
2348 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2349 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2350 [(set RC:$dst, (OpNode RC:$src1,
2351 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2352 itins.rm, d>, EVEX_4V, EVEX_B;
2354 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2355 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2356 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2357 [], itins.rm, d>, EVEX_4V, EVEX_K;
2359 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2360 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2361 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2362 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2364 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2365 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2366 " \t{${src2}", BrdcstStr,
2367 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2368 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2370 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2371 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2372 " \t{${src2}", BrdcstStr,
2373 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2375 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2379 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2380 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2381 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2383 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2384 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2385 SSE_ALU_ITINS_P.d, 1>,
2386 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2388 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2389 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2390 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2391 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2392 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2393 SSE_ALU_ITINS_P.d, 1>,
2394 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2396 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2397 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2398 SSE_ALU_ITINS_P.s, 1>,
2399 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2400 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2401 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2402 SSE_ALU_ITINS_P.s, 1>,
2403 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2405 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2406 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2407 SSE_ALU_ITINS_P.d, 1>,
2408 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2409 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2410 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2411 SSE_ALU_ITINS_P.d, 1>,
2412 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2414 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2415 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2416 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2417 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2418 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2419 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2421 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2422 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2423 SSE_ALU_ITINS_P.d, 0>,
2424 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2425 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2426 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2427 SSE_ALU_ITINS_P.d, 0>,
2428 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2430 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2431 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2432 (i16 -1), FROUND_CURRENT)),
2433 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2435 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2436 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2437 (i8 -1), FROUND_CURRENT)),
2438 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2440 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2441 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2442 (i16 -1), FROUND_CURRENT)),
2443 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2445 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2446 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2447 (i8 -1), FROUND_CURRENT)),
2448 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2449 //===----------------------------------------------------------------------===//
2450 // AVX-512 VPTESTM instructions
2451 //===----------------------------------------------------------------------===//
2453 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2454 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2455 SDNode OpNode, ValueType vt> {
2456 def rr : AVX512PI<opc, MRMSrcReg,
2457 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2458 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2459 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2460 SSEPackedInt>, EVEX_4V;
2461 def rm : AVX512PI<opc, MRMSrcMem,
2462 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2463 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2464 [(set KRC:$dst, (OpNode (vt RC:$src1),
2465 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2468 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2469 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2470 EVEX_CD8<32, CD8VF>;
2471 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2472 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2473 EVEX_CD8<64, CD8VF>;
2475 let Predicates = [HasCDI] in {
2476 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2477 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2478 EVEX_CD8<32, CD8VF>;
2479 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2480 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2481 EVEX_CD8<64, CD8VF>;
2484 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2485 (v16i32 VR512:$src2), (i16 -1))),
2486 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2488 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2489 (v8i64 VR512:$src2), (i8 -1))),
2490 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2491 //===----------------------------------------------------------------------===//
2492 // AVX-512 Shift instructions
2493 //===----------------------------------------------------------------------===//
2494 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2495 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2496 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2497 RegisterClass KRC> {
2498 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2499 (ins RC:$src1, i8imm:$src2),
2500 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2501 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2502 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2503 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2504 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2505 !strconcat(OpcodeStr,
2506 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2507 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2508 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2509 (ins x86memop:$src1, i8imm:$src2),
2510 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2511 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2512 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2513 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2514 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2515 !strconcat(OpcodeStr,
2516 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2517 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2520 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2521 RegisterClass RC, ValueType vt, ValueType SrcVT,
2522 PatFrag bc_frag, RegisterClass KRC> {
2523 // src2 is always 128-bit
2524 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2525 (ins RC:$src1, VR128X:$src2),
2526 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2527 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2528 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2529 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2530 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2531 !strconcat(OpcodeStr,
2532 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2533 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2534 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2535 (ins RC:$src1, i128mem:$src2),
2536 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2537 [(set RC:$dst, (vt (OpNode RC:$src1,
2538 (bc_frag (memopv2i64 addr:$src2)))))],
2539 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2540 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2541 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2542 !strconcat(OpcodeStr,
2543 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2544 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2547 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2548 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2549 EVEX_V512, EVEX_CD8<32, CD8VF>;
2550 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2551 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2552 EVEX_CD8<32, CD8VQ>;
2554 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2555 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2556 EVEX_CD8<64, CD8VF>, VEX_W;
2557 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2558 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2559 EVEX_CD8<64, CD8VQ>, VEX_W;
2561 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2562 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2563 EVEX_CD8<32, CD8VF>;
2564 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2565 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2566 EVEX_CD8<32, CD8VQ>;
2568 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2569 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2570 EVEX_CD8<64, CD8VF>, VEX_W;
2571 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2572 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2573 EVEX_CD8<64, CD8VQ>, VEX_W;
2575 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2576 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2577 EVEX_V512, EVEX_CD8<32, CD8VF>;
2578 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2579 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2580 EVEX_CD8<32, CD8VQ>;
2582 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2583 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2584 EVEX_CD8<64, CD8VF>, VEX_W;
2585 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2586 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2587 EVEX_CD8<64, CD8VQ>, VEX_W;
2589 //===-------------------------------------------------------------------===//
2590 // Variable Bit Shifts
2591 //===-------------------------------------------------------------------===//
2592 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2593 RegisterClass RC, ValueType vt,
2594 X86MemOperand x86memop, PatFrag mem_frag> {
2595 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2596 (ins RC:$src1, RC:$src2),
2597 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2599 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2601 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2602 (ins RC:$src1, x86memop:$src2),
2603 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2605 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2609 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2610 i512mem, memopv16i32>, EVEX_V512,
2611 EVEX_CD8<32, CD8VF>;
2612 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2613 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2614 EVEX_CD8<64, CD8VF>;
2615 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2616 i512mem, memopv16i32>, EVEX_V512,
2617 EVEX_CD8<32, CD8VF>;
2618 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2619 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2620 EVEX_CD8<64, CD8VF>;
2621 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2622 i512mem, memopv16i32>, EVEX_V512,
2623 EVEX_CD8<32, CD8VF>;
2624 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2625 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2626 EVEX_CD8<64, CD8VF>;
2628 //===----------------------------------------------------------------------===//
2629 // AVX-512 - MOVDDUP
2630 //===----------------------------------------------------------------------===//
2632 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2633 X86MemOperand x86memop, PatFrag memop_frag> {
2634 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2635 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2636 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2637 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2638 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2640 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2643 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2644 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2645 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2646 (VMOVDDUPZrm addr:$src)>;
2648 //===---------------------------------------------------------------------===//
2649 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2650 //===---------------------------------------------------------------------===//
2651 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2652 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2653 X86MemOperand x86memop> {
2654 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2655 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2656 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2658 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2659 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2660 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2663 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2664 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2665 EVEX_CD8<32, CD8VF>;
2666 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2667 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2668 EVEX_CD8<32, CD8VF>;
2670 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2671 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2672 (VMOVSHDUPZrm addr:$src)>;
2673 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2674 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2675 (VMOVSLDUPZrm addr:$src)>;
2677 //===----------------------------------------------------------------------===//
2678 // Move Low to High and High to Low packed FP Instructions
2679 //===----------------------------------------------------------------------===//
2680 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2681 (ins VR128X:$src1, VR128X:$src2),
2682 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2683 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2684 IIC_SSE_MOV_LH>, EVEX_4V;
2685 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2686 (ins VR128X:$src1, VR128X:$src2),
2687 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2688 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2689 IIC_SSE_MOV_LH>, EVEX_4V;
2691 let Predicates = [HasAVX512] in {
2693 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2694 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2695 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2696 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2699 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2700 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2703 //===----------------------------------------------------------------------===//
2704 // FMA - Fused Multiply Operations
2706 let Constraints = "$src1 = $dst" in {
2707 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2708 RegisterClass RC, X86MemOperand x86memop,
2709 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2710 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2711 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2712 (ins RC:$src1, RC:$src2, RC:$src3),
2713 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2714 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2717 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2718 (ins RC:$src1, RC:$src2, x86memop:$src3),
2719 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2720 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2721 (mem_frag addr:$src3))))]>;
2722 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2723 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2724 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2725 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2726 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2727 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2729 } // Constraints = "$src1 = $dst"
2731 let ExeDomain = SSEPackedSingle in {
2732 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2733 memopv16f32, f32mem, loadf32, "{1to16}",
2734 X86Fmadd, v16f32>, EVEX_V512,
2735 EVEX_CD8<32, CD8VF>;
2736 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2737 memopv16f32, f32mem, loadf32, "{1to16}",
2738 X86Fmsub, v16f32>, EVEX_V512,
2739 EVEX_CD8<32, CD8VF>;
2740 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2741 memopv16f32, f32mem, loadf32, "{1to16}",
2742 X86Fmaddsub, v16f32>,
2743 EVEX_V512, EVEX_CD8<32, CD8VF>;
2744 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2745 memopv16f32, f32mem, loadf32, "{1to16}",
2746 X86Fmsubadd, v16f32>,
2747 EVEX_V512, EVEX_CD8<32, CD8VF>;
2748 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2749 memopv16f32, f32mem, loadf32, "{1to16}",
2750 X86Fnmadd, v16f32>, EVEX_V512,
2751 EVEX_CD8<32, CD8VF>;
2752 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2753 memopv16f32, f32mem, loadf32, "{1to16}",
2754 X86Fnmsub, v16f32>, EVEX_V512,
2755 EVEX_CD8<32, CD8VF>;
2757 let ExeDomain = SSEPackedDouble in {
2758 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2759 memopv8f64, f64mem, loadf64, "{1to8}",
2760 X86Fmadd, v8f64>, EVEX_V512,
2761 VEX_W, EVEX_CD8<64, CD8VF>;
2762 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2763 memopv8f64, f64mem, loadf64, "{1to8}",
2764 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2765 EVEX_CD8<64, CD8VF>;
2766 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2767 memopv8f64, f64mem, loadf64, "{1to8}",
2768 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2769 EVEX_CD8<64, CD8VF>;
2770 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2771 memopv8f64, f64mem, loadf64, "{1to8}",
2772 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2773 EVEX_CD8<64, CD8VF>;
2774 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2775 memopv8f64, f64mem, loadf64, "{1to8}",
2776 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2777 EVEX_CD8<64, CD8VF>;
2778 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2779 memopv8f64, f64mem, loadf64, "{1to8}",
2780 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2781 EVEX_CD8<64, CD8VF>;
2784 let Constraints = "$src1 = $dst" in {
2785 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2786 RegisterClass RC, X86MemOperand x86memop,
2787 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2788 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2790 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2791 (ins RC:$src1, RC:$src3, x86memop:$src2),
2792 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2793 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2794 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2795 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2796 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2797 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2798 [(set RC:$dst, (OpNode RC:$src1,
2799 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2801 } // Constraints = "$src1 = $dst"
2804 let ExeDomain = SSEPackedSingle in {
2805 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2806 memopv16f32, f32mem, loadf32, "{1to16}",
2807 X86Fmadd, v16f32>, EVEX_V512,
2808 EVEX_CD8<32, CD8VF>;
2809 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2810 memopv16f32, f32mem, loadf32, "{1to16}",
2811 X86Fmsub, v16f32>, EVEX_V512,
2812 EVEX_CD8<32, CD8VF>;
2813 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2814 memopv16f32, f32mem, loadf32, "{1to16}",
2815 X86Fmaddsub, v16f32>,
2816 EVEX_V512, EVEX_CD8<32, CD8VF>;
2817 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2818 memopv16f32, f32mem, loadf32, "{1to16}",
2819 X86Fmsubadd, v16f32>,
2820 EVEX_V512, EVEX_CD8<32, CD8VF>;
2821 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2822 memopv16f32, f32mem, loadf32, "{1to16}",
2823 X86Fnmadd, v16f32>, EVEX_V512,
2824 EVEX_CD8<32, CD8VF>;
2825 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2826 memopv16f32, f32mem, loadf32, "{1to16}",
2827 X86Fnmsub, v16f32>, EVEX_V512,
2828 EVEX_CD8<32, CD8VF>;
2830 let ExeDomain = SSEPackedDouble in {
2831 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2832 memopv8f64, f64mem, loadf64, "{1to8}",
2833 X86Fmadd, v8f64>, EVEX_V512,
2834 VEX_W, EVEX_CD8<64, CD8VF>;
2835 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2836 memopv8f64, f64mem, loadf64, "{1to8}",
2837 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2838 EVEX_CD8<64, CD8VF>;
2839 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2840 memopv8f64, f64mem, loadf64, "{1to8}",
2841 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2842 EVEX_CD8<64, CD8VF>;
2843 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2844 memopv8f64, f64mem, loadf64, "{1to8}",
2845 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2846 EVEX_CD8<64, CD8VF>;
2847 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2848 memopv8f64, f64mem, loadf64, "{1to8}",
2849 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2850 EVEX_CD8<64, CD8VF>;
2851 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2852 memopv8f64, f64mem, loadf64, "{1to8}",
2853 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2854 EVEX_CD8<64, CD8VF>;
2858 let Constraints = "$src1 = $dst" in {
2859 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2860 RegisterClass RC, ValueType OpVT,
2861 X86MemOperand x86memop, Operand memop,
2863 let isCommutable = 1 in
2864 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2865 (ins RC:$src1, RC:$src2, RC:$src3),
2866 !strconcat(OpcodeStr,
2867 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2869 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2871 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2872 (ins RC:$src1, RC:$src2, f128mem:$src3),
2873 !strconcat(OpcodeStr,
2874 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2876 (OpVT (OpNode RC:$src2, RC:$src1,
2877 (mem_frag addr:$src3))))]>;
2880 } // Constraints = "$src1 = $dst"
2882 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2883 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2884 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2885 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2886 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2887 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2888 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2889 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2890 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2891 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2892 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2893 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2894 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2895 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2896 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2897 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2899 //===----------------------------------------------------------------------===//
2900 // AVX-512 Scalar convert from sign integer to float/double
2901 //===----------------------------------------------------------------------===//
2903 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2904 X86MemOperand x86memop, string asm> {
2905 let hasSideEffects = 0 in {
2906 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2907 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2910 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2911 (ins DstRC:$src1, x86memop:$src),
2912 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2914 } // hasSideEffects = 0
2916 let Predicates = [HasAVX512] in {
2917 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2918 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2919 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2920 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2921 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2922 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2923 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2924 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2926 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2927 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2928 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2929 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2930 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2931 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2932 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2933 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2935 def : Pat<(f32 (sint_to_fp GR32:$src)),
2936 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2937 def : Pat<(f32 (sint_to_fp GR64:$src)),
2938 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2939 def : Pat<(f64 (sint_to_fp GR32:$src)),
2940 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2941 def : Pat<(f64 (sint_to_fp GR64:$src)),
2942 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2944 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2945 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2946 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2947 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2948 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2949 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2950 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2951 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2953 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2954 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2955 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2956 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2957 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2958 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2959 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2960 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2962 def : Pat<(f32 (uint_to_fp GR32:$src)),
2963 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2964 def : Pat<(f32 (uint_to_fp GR64:$src)),
2965 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2966 def : Pat<(f64 (uint_to_fp GR32:$src)),
2967 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2968 def : Pat<(f64 (uint_to_fp GR64:$src)),
2969 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2972 //===----------------------------------------------------------------------===//
2973 // AVX-512 Scalar convert from float/double to integer
2974 //===----------------------------------------------------------------------===//
2975 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2976 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2978 let hasSideEffects = 0 in {
2979 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2980 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2981 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2982 Requires<[HasAVX512]>;
2984 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2985 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2986 Requires<[HasAVX512]>;
2987 } // hasSideEffects = 0
2989 let Predicates = [HasAVX512] in {
2990 // Convert float/double to signed/unsigned int 32/64
2991 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2992 ssmem, sse_load_f32, "cvtss2si">,
2993 XS, EVEX_CD8<32, CD8VT1>;
2994 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2995 ssmem, sse_load_f32, "cvtss2si">,
2996 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2997 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2998 ssmem, sse_load_f32, "cvtss2usi">,
2999 XS, EVEX_CD8<32, CD8VT1>;
3000 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3001 int_x86_avx512_cvtss2usi64, ssmem,
3002 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3003 EVEX_CD8<32, CD8VT1>;
3004 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3005 sdmem, sse_load_f64, "cvtsd2si">,
3006 XD, EVEX_CD8<64, CD8VT1>;
3007 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3008 sdmem, sse_load_f64, "cvtsd2si">,
3009 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3010 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3011 sdmem, sse_load_f64, "cvtsd2usi">,
3012 XD, EVEX_CD8<64, CD8VT1>;
3013 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3014 int_x86_avx512_cvtsd2usi64, sdmem,
3015 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3016 EVEX_CD8<64, CD8VT1>;
3018 let isCodeGenOnly = 1 in {
3019 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3020 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3021 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3022 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3023 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3024 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3025 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3026 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3027 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3028 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3029 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3030 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3032 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3033 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3034 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3035 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3036 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3037 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3038 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3039 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3040 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3041 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3042 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3043 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3044 } // isCodeGenOnly = 1
3046 // Convert float/double to signed/unsigned int 32/64 with truncation
3047 let isCodeGenOnly = 1 in {
3048 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3049 ssmem, sse_load_f32, "cvttss2si">,
3050 XS, EVEX_CD8<32, CD8VT1>;
3051 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3052 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3053 "cvttss2si">, XS, VEX_W,
3054 EVEX_CD8<32, CD8VT1>;
3055 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3056 sdmem, sse_load_f64, "cvttsd2si">, XD,
3057 EVEX_CD8<64, CD8VT1>;
3058 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3059 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3060 "cvttsd2si">, XD, VEX_W,
3061 EVEX_CD8<64, CD8VT1>;
3062 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3063 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3064 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3065 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3066 int_x86_avx512_cvttss2usi64, ssmem,
3067 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3068 EVEX_CD8<32, CD8VT1>;
3069 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3070 int_x86_avx512_cvttsd2usi,
3071 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3072 EVEX_CD8<64, CD8VT1>;
3073 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3074 int_x86_avx512_cvttsd2usi64, sdmem,
3075 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3076 EVEX_CD8<64, CD8VT1>;
3077 } // isCodeGenOnly = 1
3079 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3080 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3082 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3083 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3084 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3085 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3086 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3087 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3090 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3091 loadf32, "cvttss2si">, XS,
3092 EVEX_CD8<32, CD8VT1>;
3093 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3094 loadf32, "cvttss2usi">, XS,
3095 EVEX_CD8<32, CD8VT1>;
3096 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3097 loadf32, "cvttss2si">, XS, VEX_W,
3098 EVEX_CD8<32, CD8VT1>;
3099 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3100 loadf32, "cvttss2usi">, XS, VEX_W,
3101 EVEX_CD8<32, CD8VT1>;
3102 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3103 loadf64, "cvttsd2si">, XD,
3104 EVEX_CD8<64, CD8VT1>;
3105 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3106 loadf64, "cvttsd2usi">, XD,
3107 EVEX_CD8<64, CD8VT1>;
3108 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3109 loadf64, "cvttsd2si">, XD, VEX_W,
3110 EVEX_CD8<64, CD8VT1>;
3111 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3112 loadf64, "cvttsd2usi">, XD, VEX_W,
3113 EVEX_CD8<64, CD8VT1>;
3115 //===----------------------------------------------------------------------===//
3116 // AVX-512 Convert form float to double and back
3117 //===----------------------------------------------------------------------===//
3118 let hasSideEffects = 0 in {
3119 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3120 (ins FR32X:$src1, FR32X:$src2),
3121 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3122 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3124 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3125 (ins FR32X:$src1, f32mem:$src2),
3126 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3127 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3128 EVEX_CD8<32, CD8VT1>;
3130 // Convert scalar double to scalar single
3131 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3132 (ins FR64X:$src1, FR64X:$src2),
3133 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3134 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3136 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3137 (ins FR64X:$src1, f64mem:$src2),
3138 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3139 []>, EVEX_4V, VEX_LIG, VEX_W,
3140 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3143 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3144 Requires<[HasAVX512]>;
3145 def : Pat<(fextend (loadf32 addr:$src)),
3146 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3148 def : Pat<(extloadf32 addr:$src),
3149 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3150 Requires<[HasAVX512, OptForSize]>;
3152 def : Pat<(extloadf32 addr:$src),
3153 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3154 Requires<[HasAVX512, OptForSpeed]>;
3156 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3157 Requires<[HasAVX512]>;
3159 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3160 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3161 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3163 let hasSideEffects = 0 in {
3164 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3165 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3167 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3168 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3169 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3170 [], d>, EVEX, EVEX_B, EVEX_RC;
3172 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3173 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3175 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3176 } // hasSideEffects = 0
3179 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3180 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3181 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3183 let hasSideEffects = 0 in {
3184 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3185 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3187 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3189 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3190 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3192 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3193 } // hasSideEffects = 0
3196 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3197 memopv8f64, f512mem, v8f32, v8f64,
3198 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3199 EVEX_CD8<64, CD8VF>;
3201 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3202 memopv4f64, f256mem, v8f64, v8f32,
3203 SSEPackedDouble>, EVEX_V512, PS,
3204 EVEX_CD8<32, CD8VH>;
3205 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3206 (VCVTPS2PDZrm addr:$src)>;
3208 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3209 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3210 (VCVTPD2PSZrr VR512:$src)>;
3212 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3213 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3214 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3216 //===----------------------------------------------------------------------===//
3217 // AVX-512 Vector convert from sign integer to float/double
3218 //===----------------------------------------------------------------------===//
3220 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3221 memopv8i64, i512mem, v16f32, v16i32,
3222 SSEPackedSingle>, EVEX_V512, PS,
3223 EVEX_CD8<32, CD8VF>;
3225 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3226 memopv4i64, i256mem, v8f64, v8i32,
3227 SSEPackedDouble>, EVEX_V512, XS,
3228 EVEX_CD8<32, CD8VH>;
3230 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3231 memopv16f32, f512mem, v16i32, v16f32,
3232 SSEPackedSingle>, EVEX_V512, XS,
3233 EVEX_CD8<32, CD8VF>;
3235 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3236 memopv8f64, f512mem, v8i32, v8f64,
3237 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3238 EVEX_CD8<64, CD8VF>;
3240 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3241 memopv16f32, f512mem, v16i32, v16f32,
3242 SSEPackedSingle>, EVEX_V512, PS,
3243 EVEX_CD8<32, CD8VF>;
3245 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3246 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3247 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3248 (VCVTTPS2UDQZrr VR512:$src)>;
3250 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3251 memopv8f64, f512mem, v8i32, v8f64,
3252 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3253 EVEX_CD8<64, CD8VF>;
3255 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3256 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3257 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3258 (VCVTTPD2UDQZrr VR512:$src)>;
3260 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3261 memopv4i64, f256mem, v8f64, v8i32,
3262 SSEPackedDouble>, EVEX_V512, XS,
3263 EVEX_CD8<32, CD8VH>;
3265 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3266 memopv16i32, f512mem, v16f32, v16i32,
3267 SSEPackedSingle>, EVEX_V512, XD,
3268 EVEX_CD8<32, CD8VF>;
3270 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3271 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3272 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3274 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3275 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3276 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3278 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3279 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3280 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3282 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3283 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3284 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3286 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3287 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3288 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3290 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3291 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3292 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3293 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3294 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3295 (VCVTDQ2PDZrr VR256X:$src)>;
3296 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3297 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3298 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3299 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3300 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3301 (VCVTUDQ2PDZrr VR256X:$src)>;
3303 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3304 RegisterClass DstRC, PatFrag mem_frag,
3305 X86MemOperand x86memop, Domain d> {
3306 let hasSideEffects = 0 in {
3307 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3308 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3310 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3311 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3312 [], d>, EVEX, EVEX_B, EVEX_RC;
3314 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3315 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3317 } // hasSideEffects = 0
3320 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3321 memopv16f32, f512mem, SSEPackedSingle>, PD,
3322 EVEX_V512, EVEX_CD8<32, CD8VF>;
3323 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3324 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3325 EVEX_V512, EVEX_CD8<64, CD8VF>;
3327 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3328 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3329 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3331 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3332 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3333 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3335 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3336 memopv16f32, f512mem, SSEPackedSingle>,
3337 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3338 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3339 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3340 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3342 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3343 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3344 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3346 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3347 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3348 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3350 let Predicates = [HasAVX512] in {
3351 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3352 (VCVTPD2PSZrm addr:$src)>;
3353 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3354 (VCVTPS2PDZrm addr:$src)>;
3357 //===----------------------------------------------------------------------===//
3358 // Half precision conversion instructions
3359 //===----------------------------------------------------------------------===//
3360 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3361 X86MemOperand x86memop> {
3362 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3363 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3365 let hasSideEffects = 0, mayLoad = 1 in
3366 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3367 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3370 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3371 X86MemOperand x86memop> {
3372 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3373 (ins srcRC:$src1, i32i8imm:$src2),
3374 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3376 let hasSideEffects = 0, mayStore = 1 in
3377 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3378 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3379 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3382 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3383 EVEX_CD8<32, CD8VH>;
3384 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3385 EVEX_CD8<32, CD8VH>;
3387 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3388 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3389 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3391 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3392 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3393 (VCVTPH2PSZrr VR256X:$src)>;
3395 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3396 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3397 "ucomiss">, PS, EVEX, VEX_LIG,
3398 EVEX_CD8<32, CD8VT1>;
3399 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3400 "ucomisd">, PD, EVEX,
3401 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3402 let Pattern = []<dag> in {
3403 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3404 "comiss">, PS, EVEX, VEX_LIG,
3405 EVEX_CD8<32, CD8VT1>;
3406 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3407 "comisd">, PD, EVEX,
3408 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3410 let isCodeGenOnly = 1 in {
3411 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3412 load, "ucomiss">, PS, EVEX, VEX_LIG,
3413 EVEX_CD8<32, CD8VT1>;
3414 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3415 load, "ucomisd">, PD, EVEX,
3416 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3418 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3419 load, "comiss">, PS, EVEX, VEX_LIG,
3420 EVEX_CD8<32, CD8VT1>;
3421 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3422 load, "comisd">, PD, EVEX,
3423 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3427 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3428 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3429 X86MemOperand x86memop> {
3430 let hasSideEffects = 0 in {
3431 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3432 (ins RC:$src1, RC:$src2),
3433 !strconcat(OpcodeStr,
3434 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3435 let mayLoad = 1 in {
3436 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3437 (ins RC:$src1, x86memop:$src2),
3438 !strconcat(OpcodeStr,
3439 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3444 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3445 EVEX_CD8<32, CD8VT1>;
3446 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3447 VEX_W, EVEX_CD8<64, CD8VT1>;
3448 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3449 EVEX_CD8<32, CD8VT1>;
3450 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3451 VEX_W, EVEX_CD8<64, CD8VT1>;
3453 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3454 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3455 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3456 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3458 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3459 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3460 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3461 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3463 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3464 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3465 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3466 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3468 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3469 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3470 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3471 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3473 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3474 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3475 RegisterClass RC, X86MemOperand x86memop,
3476 PatFrag mem_frag, ValueType OpVt> {
3477 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3478 !strconcat(OpcodeStr,
3479 " \t{$src, $dst|$dst, $src}"),
3480 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3482 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3483 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3484 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3487 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3488 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3489 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3490 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3491 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3492 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3493 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3494 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3496 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3497 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3498 (VRSQRT14PSZr VR512:$src)>;
3499 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3500 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3501 (VRSQRT14PDZr VR512:$src)>;
3503 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3504 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3505 (VRCP14PSZr VR512:$src)>;
3506 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3507 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3508 (VRCP14PDZr VR512:$src)>;
3510 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3511 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3512 X86MemOperand x86memop> {
3513 let hasSideEffects = 0, Predicates = [HasERI] in {
3514 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3515 (ins RC:$src1, RC:$src2),
3516 !strconcat(OpcodeStr,
3517 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3518 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3519 (ins RC:$src1, RC:$src2),
3520 !strconcat(OpcodeStr,
3521 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3522 []>, EVEX_4V, EVEX_B;
3523 let mayLoad = 1 in {
3524 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3525 (ins RC:$src1, x86memop:$src2),
3526 !strconcat(OpcodeStr,
3527 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3532 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3533 EVEX_CD8<32, CD8VT1>;
3534 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3535 VEX_W, EVEX_CD8<64, CD8VT1>;
3536 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3537 EVEX_CD8<32, CD8VT1>;
3538 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3539 VEX_W, EVEX_CD8<64, CD8VT1>;
3541 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3542 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3544 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3545 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3547 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3548 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3550 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3551 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3553 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3554 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3556 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3557 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3559 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3560 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3562 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3563 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3565 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3566 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3567 RegisterClass RC, X86MemOperand x86memop> {
3568 let hasSideEffects = 0, Predicates = [HasERI] in {
3569 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3570 !strconcat(OpcodeStr,
3571 " \t{$src, $dst|$dst, $src}"),
3573 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3574 !strconcat(OpcodeStr,
3575 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3577 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3578 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3582 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3583 EVEX_V512, EVEX_CD8<32, CD8VF>;
3584 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3585 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3586 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3587 EVEX_V512, EVEX_CD8<32, CD8VF>;
3588 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3589 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3591 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3592 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3593 (VRSQRT28PSZrb VR512:$src)>;
3594 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3595 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3596 (VRSQRT28PDZrb VR512:$src)>;
3598 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3599 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3600 (VRCP28PSZrb VR512:$src)>;
3601 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3602 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3603 (VRCP28PDZrb VR512:$src)>;
3605 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3606 Intrinsic V16F32Int, Intrinsic V8F64Int,
3607 OpndItins itins_s, OpndItins itins_d> {
3608 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3609 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3610 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3614 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3615 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3617 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3618 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3620 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3621 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3622 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3626 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3627 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3628 [(set VR512:$dst, (OpNode
3629 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3630 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3632 let isCodeGenOnly = 1 in {
3633 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3634 !strconcat(OpcodeStr,
3635 "ps\t{$src, $dst|$dst, $src}"),
3636 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3638 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3639 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3641 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3642 EVEX_V512, EVEX_CD8<32, CD8VF>;
3643 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3644 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3645 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3646 EVEX, EVEX_V512, VEX_W;
3647 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3648 !strconcat(OpcodeStr,
3649 "pd\t{$src, $dst|$dst, $src}"),
3650 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3651 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3652 } // isCodeGenOnly = 1
3655 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3656 Intrinsic F32Int, Intrinsic F64Int,
3657 OpndItins itins_s, OpndItins itins_d> {
3658 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3659 (ins FR32X:$src1, FR32X:$src2),
3660 !strconcat(OpcodeStr,
3661 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3662 [], itins_s.rr>, XS, EVEX_4V;
3663 let isCodeGenOnly = 1 in
3664 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3665 (ins VR128X:$src1, VR128X:$src2),
3666 !strconcat(OpcodeStr,
3667 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3669 (F32Int VR128X:$src1, VR128X:$src2))],
3670 itins_s.rr>, XS, EVEX_4V;
3671 let mayLoad = 1 in {
3672 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3673 (ins FR32X:$src1, f32mem:$src2),
3674 !strconcat(OpcodeStr,
3675 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3676 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3677 let isCodeGenOnly = 1 in
3678 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3679 (ins VR128X:$src1, ssmem:$src2),
3680 !strconcat(OpcodeStr,
3681 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3683 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3684 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3686 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3687 (ins FR64X:$src1, FR64X:$src2),
3688 !strconcat(OpcodeStr,
3689 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3691 let isCodeGenOnly = 1 in
3692 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3693 (ins VR128X:$src1, VR128X:$src2),
3694 !strconcat(OpcodeStr,
3695 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3697 (F64Int VR128X:$src1, VR128X:$src2))],
3698 itins_s.rr>, XD, EVEX_4V, VEX_W;
3699 let mayLoad = 1 in {
3700 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3701 (ins FR64X:$src1, f64mem:$src2),
3702 !strconcat(OpcodeStr,
3703 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3704 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3705 let isCodeGenOnly = 1 in
3706 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3707 (ins VR128X:$src1, sdmem:$src2),
3708 !strconcat(OpcodeStr,
3709 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3711 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3712 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3717 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3718 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3719 SSE_SQRTSS, SSE_SQRTSD>,
3720 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3721 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3722 SSE_SQRTPS, SSE_SQRTPD>;
3724 let Predicates = [HasAVX512] in {
3725 def : Pat<(f32 (fsqrt FR32X:$src)),
3726 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3727 def : Pat<(f32 (fsqrt (load addr:$src))),
3728 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3729 Requires<[OptForSize]>;
3730 def : Pat<(f64 (fsqrt FR64X:$src)),
3731 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3732 def : Pat<(f64 (fsqrt (load addr:$src))),
3733 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3734 Requires<[OptForSize]>;
3736 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3737 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3738 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3739 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3740 Requires<[OptForSize]>;
3742 def : Pat<(f32 (X86frcp FR32X:$src)),
3743 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3744 def : Pat<(f32 (X86frcp (load addr:$src))),
3745 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3746 Requires<[OptForSize]>;
3748 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3749 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3750 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3752 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3753 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3755 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3756 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3757 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3759 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3760 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3764 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3765 X86MemOperand x86memop, RegisterClass RC,
3766 PatFrag mem_frag32, PatFrag mem_frag64,
3767 Intrinsic V4F32Int, Intrinsic V2F64Int,
3769 let ExeDomain = SSEPackedSingle in {
3770 // Intrinsic operation, reg.
3771 // Vector intrinsic operation, reg
3772 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3773 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3774 !strconcat(OpcodeStr,
3775 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3776 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3778 // Vector intrinsic operation, mem
3779 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3780 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3781 !strconcat(OpcodeStr,
3782 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3784 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3785 EVEX_CD8<32, VForm>;
3786 } // ExeDomain = SSEPackedSingle
3788 let ExeDomain = SSEPackedDouble in {
3789 // Vector intrinsic operation, reg
3790 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3791 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3792 !strconcat(OpcodeStr,
3793 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3794 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3796 // Vector intrinsic operation, mem
3797 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3798 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3799 !strconcat(OpcodeStr,
3800 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3802 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3803 EVEX_CD8<64, VForm>;
3804 } // ExeDomain = SSEPackedDouble
3807 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3811 let ExeDomain = GenericDomain in {
3813 let hasSideEffects = 0 in
3814 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3815 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3816 !strconcat(OpcodeStr,
3817 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3820 // Intrinsic operation, reg.
3821 let isCodeGenOnly = 1 in
3822 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3823 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3824 !strconcat(OpcodeStr,
3825 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3826 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3828 // Intrinsic operation, mem.
3829 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3830 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3831 !strconcat(OpcodeStr,
3832 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3833 [(set VR128X:$dst, (F32Int VR128X:$src1,
3834 sse_load_f32:$src2, imm:$src3))]>,
3835 EVEX_CD8<32, CD8VT1>;
3838 let hasSideEffects = 0 in
3839 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3840 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3841 !strconcat(OpcodeStr,
3842 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3845 // Intrinsic operation, reg.
3846 let isCodeGenOnly = 1 in
3847 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3848 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3849 !strconcat(OpcodeStr,
3850 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3851 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3854 // Intrinsic operation, mem.
3855 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3856 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3857 !strconcat(OpcodeStr,
3858 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3860 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3861 VEX_W, EVEX_CD8<64, CD8VT1>;
3862 } // ExeDomain = GenericDomain
3865 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3866 X86MemOperand x86memop, RegisterClass RC,
3867 PatFrag mem_frag, Domain d> {
3868 let ExeDomain = d in {
3869 // Intrinsic operation, reg.
3870 // Vector intrinsic operation, reg
3871 def r : AVX512AIi8<opc, MRMSrcReg,
3872 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3873 !strconcat(OpcodeStr,
3874 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3877 // Vector intrinsic operation, mem
3878 def m : AVX512AIi8<opc, MRMSrcMem,
3879 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3880 !strconcat(OpcodeStr,
3881 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3887 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3888 memopv16f32, SSEPackedSingle>, EVEX_V512,
3889 EVEX_CD8<32, CD8VF>;
3891 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3892 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3894 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3897 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3898 memopv8f64, SSEPackedDouble>, EVEX_V512,
3899 VEX_W, EVEX_CD8<64, CD8VF>;
3901 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3902 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3904 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3906 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3907 Operand x86memop, RegisterClass RC, Domain d> {
3908 let ExeDomain = d in {
3909 def r : AVX512AIi8<opc, MRMSrcReg,
3910 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3911 !strconcat(OpcodeStr,
3912 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3915 def m : AVX512AIi8<opc, MRMSrcMem,
3916 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3917 !strconcat(OpcodeStr,
3918 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3923 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3924 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3926 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3927 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3929 def : Pat<(ffloor FR32X:$src),
3930 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3931 def : Pat<(f64 (ffloor FR64X:$src)),
3932 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3933 def : Pat<(f32 (fnearbyint FR32X:$src)),
3934 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3935 def : Pat<(f64 (fnearbyint FR64X:$src)),
3936 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3937 def : Pat<(f32 (fceil FR32X:$src)),
3938 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3939 def : Pat<(f64 (fceil FR64X:$src)),
3940 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3941 def : Pat<(f32 (frint FR32X:$src)),
3942 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3943 def : Pat<(f64 (frint FR64X:$src)),
3944 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3945 def : Pat<(f32 (ftrunc FR32X:$src)),
3946 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3947 def : Pat<(f64 (ftrunc FR64X:$src)),
3948 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3950 def : Pat<(v16f32 (ffloor VR512:$src)),
3951 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3952 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3953 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3954 def : Pat<(v16f32 (fceil VR512:$src)),
3955 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3956 def : Pat<(v16f32 (frint VR512:$src)),
3957 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3958 def : Pat<(v16f32 (ftrunc VR512:$src)),
3959 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3961 def : Pat<(v8f64 (ffloor VR512:$src)),
3962 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3963 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3964 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3965 def : Pat<(v8f64 (fceil VR512:$src)),
3966 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3967 def : Pat<(v8f64 (frint VR512:$src)),
3968 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3969 def : Pat<(v8f64 (ftrunc VR512:$src)),
3970 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3972 //-------------------------------------------------
3973 // Integer truncate and extend operations
3974 //-------------------------------------------------
3976 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3977 RegisterClass dstRC, RegisterClass srcRC,
3978 RegisterClass KRC, X86MemOperand x86memop> {
3979 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3981 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3984 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3985 (ins KRC:$mask, srcRC:$src),
3986 !strconcat(OpcodeStr,
3987 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
3990 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3991 (ins KRC:$mask, srcRC:$src),
3992 !strconcat(OpcodeStr,
3993 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3996 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3997 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4000 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4001 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4002 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4006 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4007 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4008 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4009 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4010 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4011 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4012 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4013 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4014 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4015 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4016 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4017 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4018 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4019 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4020 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4021 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4022 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4023 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4024 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4025 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4026 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4027 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4028 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4029 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4030 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4031 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4032 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4033 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4034 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4035 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4037 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4038 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4039 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4040 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4041 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4043 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4044 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4045 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4046 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4047 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4048 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4049 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4050 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4053 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4054 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4055 PatFrag mem_frag, X86MemOperand x86memop,
4056 ValueType OpVT, ValueType InVT> {
4058 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4060 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4061 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4063 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4064 (ins KRC:$mask, SrcRC:$src),
4065 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4068 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4069 (ins KRC:$mask, SrcRC:$src),
4070 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4073 let mayLoad = 1 in {
4074 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4075 (ins x86memop:$src),
4076 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4078 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4081 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4082 (ins KRC:$mask, x86memop:$src),
4083 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4087 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4088 (ins KRC:$mask, x86memop:$src),
4089 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4095 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4096 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4098 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4099 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4101 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4102 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4103 EVEX_CD8<16, CD8VH>;
4104 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4105 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4106 EVEX_CD8<16, CD8VQ>;
4107 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4108 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4109 EVEX_CD8<32, CD8VH>;
4111 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4112 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4114 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4115 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4117 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4118 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4119 EVEX_CD8<16, CD8VH>;
4120 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4121 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4122 EVEX_CD8<16, CD8VQ>;
4123 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4124 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4125 EVEX_CD8<32, CD8VH>;
4127 //===----------------------------------------------------------------------===//
4128 // GATHER - SCATTER Operations
4130 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4131 RegisterClass RC, X86MemOperand memop> {
4133 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4134 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4135 (ins RC:$src1, KRC:$mask, memop:$src2),
4136 !strconcat(OpcodeStr,
4137 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4141 let ExeDomain = SSEPackedDouble in {
4142 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4143 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4144 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4145 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4148 let ExeDomain = SSEPackedSingle in {
4149 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4150 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4151 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4152 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4155 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4156 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4157 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4158 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4160 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4161 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4162 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4163 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4165 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4166 RegisterClass RC, X86MemOperand memop> {
4167 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4168 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4169 (ins memop:$dst, KRC:$mask, RC:$src2),
4170 !strconcat(OpcodeStr,
4171 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4175 let ExeDomain = SSEPackedDouble in {
4176 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4177 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4178 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4179 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4182 let ExeDomain = SSEPackedSingle in {
4183 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4184 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4185 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4186 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4189 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4190 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4191 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4192 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4194 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4195 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4196 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4197 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4200 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4201 RegisterClass KRC, X86MemOperand memop> {
4202 let Predicates = [HasPFI], hasSideEffects = 1 in
4203 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4204 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4208 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4209 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4211 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4212 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4214 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4215 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4217 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4218 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4220 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4221 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4223 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4224 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4226 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4227 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4229 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4230 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4232 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4233 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4235 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4236 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4238 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4239 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4241 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4242 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4244 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4245 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4247 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4248 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4250 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4251 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4253 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4254 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4255 //===----------------------------------------------------------------------===//
4256 // VSHUFPS - VSHUFPD Operations
4258 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4259 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4261 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4262 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4263 !strconcat(OpcodeStr,
4264 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4265 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4266 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4267 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4268 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4269 (ins RC:$src1, RC:$src2, i8imm:$src3),
4270 !strconcat(OpcodeStr,
4271 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4272 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4273 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4274 EVEX_4V, Sched<[WriteShuffle]>;
4277 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4278 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4279 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4280 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4282 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4283 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4284 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4285 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4286 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4288 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4289 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4290 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4291 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4292 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4294 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4295 X86MemOperand x86memop> {
4296 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4297 (ins RC:$src1, RC:$src2, i8imm:$src3),
4298 !strconcat(OpcodeStr,
4299 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4302 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4303 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4304 !strconcat(OpcodeStr,
4305 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4308 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4309 EVEX_V512, EVEX_CD8<32, CD8VF>;
4310 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4311 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4313 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4314 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4315 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4316 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4317 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4318 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4319 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4320 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4322 // Helper fragments to match sext vXi1 to vXiY.
4323 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4324 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4326 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4327 RegisterClass KRC, RegisterClass RC,
4328 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4330 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4331 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4333 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4334 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4336 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4337 !strconcat(OpcodeStr,
4338 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4340 let mayLoad = 1 in {
4341 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4342 (ins x86memop:$src),
4343 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4345 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4346 (ins KRC:$mask, x86memop:$src),
4347 !strconcat(OpcodeStr,
4348 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4350 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4351 (ins KRC:$mask, x86memop:$src),
4352 !strconcat(OpcodeStr,
4353 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4355 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4356 (ins x86scalar_mop:$src),
4357 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4358 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4360 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4361 (ins KRC:$mask, x86scalar_mop:$src),
4362 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4363 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4364 []>, EVEX, EVEX_B, EVEX_K;
4365 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4366 (ins KRC:$mask, x86scalar_mop:$src),
4367 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4368 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4370 []>, EVEX, EVEX_B, EVEX_KZ;
4374 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4375 i512mem, i32mem, "{1to16}">, EVEX_V512,
4376 EVEX_CD8<32, CD8VF>;
4377 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4378 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4379 EVEX_CD8<64, CD8VF>;
4382 (bc_v16i32 (v16i1sextv16i32)),
4383 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4384 (VPABSDZrr VR512:$src)>;
4386 (bc_v8i64 (v8i1sextv8i64)),
4387 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4388 (VPABSQZrr VR512:$src)>;
4390 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4391 (v16i32 immAllZerosV), (i16 -1))),
4392 (VPABSDZrr VR512:$src)>;
4393 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4394 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4395 (VPABSQZrr VR512:$src)>;
4397 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4398 RegisterClass RC, RegisterClass KRC,
4399 X86MemOperand x86memop,
4400 X86MemOperand x86scalar_mop, string BrdcstStr> {
4401 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4403 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4405 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4406 (ins x86memop:$src),
4407 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4409 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4410 (ins x86scalar_mop:$src),
4411 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4412 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4414 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4415 (ins KRC:$mask, RC:$src),
4416 !strconcat(OpcodeStr,
4417 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4419 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4420 (ins KRC:$mask, x86memop:$src),
4421 !strconcat(OpcodeStr,
4422 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4424 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4425 (ins KRC:$mask, x86scalar_mop:$src),
4426 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4427 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4429 []>, EVEX, EVEX_KZ, EVEX_B;
4431 let Constraints = "$src1 = $dst" in {
4432 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4433 (ins RC:$src1, KRC:$mask, RC:$src2),
4434 !strconcat(OpcodeStr,
4435 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4437 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4438 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4439 !strconcat(OpcodeStr,
4440 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4442 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4443 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4444 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4445 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4446 []>, EVEX, EVEX_K, EVEX_B;
4450 let Predicates = [HasCDI] in {
4451 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4452 i512mem, i32mem, "{1to16}">,
4453 EVEX_V512, EVEX_CD8<32, CD8VF>;
4456 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4457 i512mem, i64mem, "{1to8}">,
4458 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4462 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4464 (VPCONFLICTDrrk VR512:$src1,
4465 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4467 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4469 (VPCONFLICTQrrk VR512:$src1,
4470 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4472 let Predicates = [HasCDI] in {
4473 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4474 i512mem, i32mem, "{1to16}">,
4475 EVEX_V512, EVEX_CD8<32, CD8VF>;
4478 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4479 i512mem, i64mem, "{1to8}">,
4480 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4484 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4486 (VPLZCNTDrrk VR512:$src1,
4487 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4489 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4491 (VPLZCNTQrrk VR512:$src1,
4492 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4494 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4495 (VPLZCNTDrm addr:$src)>;
4496 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4497 (VPLZCNTDrr VR512:$src)>;
4498 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4499 (VPLZCNTQrm addr:$src)>;
4500 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4501 (VPLZCNTQrr VR512:$src)>;
4503 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4504 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4505 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4507 def : Pat<(store VK1:$src, addr:$dst),
4508 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4510 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4511 (truncstore node:$val, node:$ptr), [{
4512 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4515 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4516 (MOV8mr addr:$dst, GR8:$src)>;