1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
8 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
11 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
12 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
13 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
14 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
15 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
16 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
17 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
18 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
19 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
20 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
21 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
22 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
23 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
24 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
25 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
26 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
27 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
28 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
29 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
30 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
31 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
32 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
33 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
35 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
36 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
37 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
38 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
39 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
40 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
41 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
42 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
43 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
44 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
45 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
46 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
47 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
48 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
49 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
50 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
51 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
52 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
53 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
54 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
55 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
56 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
57 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
58 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
59 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
60 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
61 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
62 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
63 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
64 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
66 // Bitcasts between 256-bit vector types. Return the original type since
67 // no instruction is needed for the conversion
68 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
69 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
70 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
71 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
72 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
73 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
74 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
75 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
76 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
77 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
78 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
79 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
80 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
81 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
82 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
83 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
84 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
85 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
86 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
87 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
88 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
89 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
90 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
91 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
92 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
93 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
94 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
95 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
96 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
97 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
101 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
104 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
105 isPseudo = 1, Predicates = [HasAVX512] in {
106 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
107 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
110 let Predicates = [HasAVX512] in {
111 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
112 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
113 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
116 //===----------------------------------------------------------------------===//
117 // AVX-512 - VECTOR INSERT
120 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
121 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
122 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
123 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512;
126 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
127 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
128 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
129 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
132 // -- 64x4 fp form --
133 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
134 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
135 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
136 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, VEX_W;
139 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
140 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
141 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
142 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
144 // -- 32x4 integer form --
145 let hasSideEffects = 0 in {
146 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
147 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
148 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
149 []>, EVEX_4V, EVEX_V512;
151 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
152 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
153 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
154 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
157 let hasSideEffects = 0 in {
159 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
160 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
161 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
162 []>, EVEX_4V, EVEX_V512, VEX_W;
164 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
165 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
166 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
167 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
170 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
171 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
174 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
177 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
180 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
181 (INSERT_get_vinsert128_imm VR512:$ins))>;
183 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
184 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
185 (INSERT_get_vinsert128_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
187 (bc_v4i32 (loadv2i64 addr:$src2)),
188 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
189 (INSERT_get_vinsert128_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
191 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
192 (INSERT_get_vinsert128_imm VR512:$ins))>;
193 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
194 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert128_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
198 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
201 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
204 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
207 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
208 (INSERT_get_vinsert256_imm VR512:$ins))>;
210 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
211 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
212 (INSERT_get_vinsert256_imm VR512:$ins))>;
213 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
214 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
215 (INSERT_get_vinsert256_imm VR512:$ins))>;
216 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
217 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
218 (INSERT_get_vinsert256_imm VR512:$ins))>;
219 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
220 (bc_v8i32 (loadv4i64 addr:$src2)),
221 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
222 (INSERT_get_vinsert256_imm VR512:$ins))>;
224 // vinsertps - insert f32 to XMM
225 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
226 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
227 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
228 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
230 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
231 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
232 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
233 [(set VR128X:$dst, (X86insertps VR128X:$src1,
234 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
235 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
237 //===----------------------------------------------------------------------===//
238 // AVX-512 VECTOR EXTRACT
240 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
242 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
243 (ins VR512:$src1, i8imm:$src2),
244 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
245 []>, EVEX, EVEX_V512;
246 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
247 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
248 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
249 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
252 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
253 (ins VR512:$src1, i8imm:$src2),
254 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, VEX_W;
257 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
258 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
259 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
260 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
263 let hasSideEffects = 0 in {
265 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
266 (ins VR512:$src1, i8imm:$src2),
267 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
268 []>, EVEX, EVEX_V512;
269 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
270 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
271 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
272 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
275 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
276 (ins VR512:$src1, i8imm:$src2),
277 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
278 []>, EVEX, EVEX_V512, VEX_W;
280 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
281 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
282 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
283 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
286 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
288 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
290 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
291 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
292 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
294 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
296 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
298 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
300 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
303 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
304 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
305 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
307 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
308 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
309 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
311 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
312 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
313 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
315 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
316 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
317 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
319 // A 256-bit subvector extract from the first 512-bit vector position
320 // is a subregister copy that needs no instruction.
321 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
322 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
323 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
324 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
325 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
326 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
327 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
328 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
331 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
332 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
333 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
334 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
335 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
336 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
337 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
338 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
341 // A 128-bit subvector insert to the first 512-bit vector position
342 // is a subregister copy that needs no instruction.
343 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
345 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
347 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
349 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
351 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
352 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
353 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
355 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
356 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
357 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
360 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
361 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
362 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
364 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
365 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
366 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
369 // vextractps - extract 32 bits from XMM
370 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
371 (ins VR128X:$src1, u32u8imm:$src2),
372 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
373 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
376 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
377 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
378 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
379 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
380 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
382 //===---------------------------------------------------------------------===//
385 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
386 RegisterClass DestRC,
387 RegisterClass SrcRC, X86MemOperand x86memop> {
388 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
389 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
391 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
392 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
394 let ExeDomain = SSEPackedSingle in {
395 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
397 EVEX_V512, EVEX_CD8<32, CD8VT1>;
400 let ExeDomain = SSEPackedDouble in {
401 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
403 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
406 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
407 (VBROADCASTSSZrm addr:$src)>;
408 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
409 (VBROADCASTSDZrm addr:$src)>;
411 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
412 (VBROADCASTSSZrm addr:$src)>;
413 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
414 (VBROADCASTSDZrm addr:$src)>;
416 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
417 RegisterClass SrcRC, RegisterClass KRC> {
418 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
419 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
420 []>, EVEX, EVEX_V512;
421 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
422 (ins KRC:$mask, SrcRC:$src),
423 !strconcat(OpcodeStr,
424 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
425 []>, EVEX, EVEX_V512, EVEX_KZ;
428 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
429 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
432 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
433 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
435 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
436 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
438 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
439 (VPBROADCASTDrZrr GR32:$src)>;
440 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
441 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
442 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
443 (VPBROADCASTQrZrr GR64:$src)>;
444 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
445 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
447 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
448 (VPBROADCASTDrZrr GR32:$src)>;
449 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
450 (VPBROADCASTQrZrr GR64:$src)>;
452 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
453 (v16i32 immAllZerosV), (i16 GR16:$mask))),
454 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
455 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
456 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
457 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
459 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
460 X86MemOperand x86memop, PatFrag ld_frag,
461 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
463 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
464 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
466 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
467 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
469 !strconcat(OpcodeStr,
470 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
472 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
475 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
476 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
478 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
479 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
481 !strconcat(OpcodeStr,
482 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
483 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
484 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
488 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
489 loadi32, VR512, v16i32, v4i32, VK16WM>,
490 EVEX_V512, EVEX_CD8<32, CD8VT1>;
491 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
492 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
493 EVEX_CD8<64, CD8VT1>;
495 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
496 X86MemOperand x86memop, PatFrag ld_frag,
499 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
500 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
502 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
504 !strconcat(OpcodeStr,
505 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
510 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
511 i128mem, loadv2i64, VK16WM>,
512 EVEX_V512, EVEX_CD8<32, CD8VT4>;
513 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
514 i256mem, loadv4i64, VK16WM>, VEX_W,
515 EVEX_V512, EVEX_CD8<64, CD8VT4>;
517 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
518 (VPBROADCASTDZrr VR128X:$src)>;
519 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
520 (VPBROADCASTQZrr VR128X:$src)>;
522 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
523 (VBROADCASTSSZrr VR128X:$src)>;
524 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
525 (VBROADCASTSDZrr VR128X:$src)>;
527 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
528 (VBROADCASTSSZrr VR128X:$src)>;
529 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
530 (VBROADCASTSDZrr VR128X:$src)>;
532 // Provide fallback in case the load node that is used in the patterns above
533 // is used by additional users, which prevents the pattern selection.
534 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
535 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
536 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
537 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
540 let Predicates = [HasAVX512] in {
541 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
543 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
544 addr:$src)), sub_ymm)>;
546 //===----------------------------------------------------------------------===//
547 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
550 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
551 RegisterClass DstRC, RegisterClass KRC,
552 ValueType OpVT, ValueType SrcVT> {
553 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
554 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
558 let Predicates = [HasCDI] in {
559 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
560 VK16, v16i32, v16i1>, EVEX_V512;
561 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
562 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
565 //===----------------------------------------------------------------------===//
568 // -- immediate form --
569 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
570 SDNode OpNode, PatFrag mem_frag,
571 X86MemOperand x86memop, ValueType OpVT> {
572 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
573 (ins RC:$src1, i8imm:$src2),
574 !strconcat(OpcodeStr,
575 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
577 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
579 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
580 (ins x86memop:$src1, i8imm:$src2),
581 !strconcat(OpcodeStr,
582 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
584 (OpVT (OpNode (mem_frag addr:$src1),
585 (i8 imm:$src2))))]>, EVEX;
588 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
589 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
590 let ExeDomain = SSEPackedDouble in
591 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
592 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
594 // -- VPERM - register form --
595 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
596 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
598 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2),
600 !strconcat(OpcodeStr,
601 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
603 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
605 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
606 (ins RC:$src1, x86memop:$src2),
607 !strconcat(OpcodeStr,
608 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
610 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
614 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
615 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
616 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
617 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
618 let ExeDomain = SSEPackedSingle in
619 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
620 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
621 let ExeDomain = SSEPackedDouble in
622 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
623 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
625 // -- VPERM2I - 3 source operands form --
626 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
627 PatFrag mem_frag, X86MemOperand x86memop,
628 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
629 let Constraints = "$src1 = $dst" in {
630 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
631 (ins RC:$src1, RC:$src2, RC:$src3),
632 !strconcat(OpcodeStr,
633 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
635 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
638 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
639 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
640 !strconcat(OpcodeStr,
641 " \t{$src3, $src2, $dst {${mask}}|"
642 "$dst {${mask}}, $src2, $src3}"),
643 [(set RC:$dst, (OpVT (vselect KRC:$mask,
644 (OpNode RC:$src1, RC:$src2,
649 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
650 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
651 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
652 !strconcat(OpcodeStr,
653 " \t{$src3, $src2, $dst {${mask}} {z} |",
654 "$dst {${mask}} {z}, $src2, $src3}"),
655 [(set RC:$dst, (OpVT (vselect KRC:$mask,
656 (OpNode RC:$src1, RC:$src2,
659 (v16i32 immAllZerosV))))))]>,
662 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
663 (ins RC:$src1, RC:$src2, x86memop:$src3),
664 !strconcat(OpcodeStr,
665 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
667 (OpVT (OpNode RC:$src1, RC:$src2,
668 (mem_frag addr:$src3))))]>, EVEX_4V;
670 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
671 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
672 !strconcat(OpcodeStr,
673 " \t{$src3, $src2, $dst {${mask}}|"
674 "$dst {${mask}}, $src2, $src3}"),
676 (OpVT (vselect KRC:$mask,
677 (OpNode RC:$src1, RC:$src2,
678 (mem_frag addr:$src3)),
682 let AddedComplexity = 10 in // Prefer over the rrkz variant
683 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
684 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
685 !strconcat(OpcodeStr,
686 " \t{$src3, $src2, $dst {${mask}} {z}|"
687 "$dst {${mask}} {z}, $src2, $src3}"),
689 (OpVT (vselect KRC:$mask,
690 (OpNode RC:$src1, RC:$src2,
691 (mem_frag addr:$src3)),
693 (v16i32 immAllZerosV))))))]>,
697 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
698 i512mem, X86VPermiv3, v16i32, VK16WM>,
699 EVEX_V512, EVEX_CD8<32, CD8VF>;
700 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
701 i512mem, X86VPermiv3, v8i64, VK8WM>,
702 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
703 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
704 i512mem, X86VPermiv3, v16f32, VK16WM>,
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
706 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
707 i512mem, X86VPermiv3, v8f64, VK8WM>,
708 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
710 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
711 PatFrag mem_frag, X86MemOperand x86memop,
712 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
713 ValueType MaskVT, RegisterClass MRC> :
714 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
716 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
717 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
718 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
720 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
721 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
722 (!cast<Instruction>(NAME#rrk) VR512:$src1,
723 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
726 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
727 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
728 EVEX_V512, EVEX_CD8<32, CD8VF>;
729 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
730 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
731 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
732 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
733 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
734 EVEX_V512, EVEX_CD8<32, CD8VF>;
735 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
736 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
737 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
739 //===----------------------------------------------------------------------===//
740 // AVX-512 - BLEND using mask
742 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
743 RegisterClass KRC, RegisterClass RC,
744 X86MemOperand x86memop, PatFrag mem_frag,
745 SDNode OpNode, ValueType vt> {
746 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
747 (ins KRC:$mask, RC:$src1, RC:$src2),
748 !strconcat(OpcodeStr,
749 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
750 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
751 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
753 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
754 (ins KRC:$mask, RC:$src1, x86memop:$src2),
755 !strconcat(OpcodeStr,
756 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
757 []>, EVEX_4V, EVEX_K;
760 let ExeDomain = SSEPackedSingle in
761 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
762 VK16WM, VR512, f512mem,
763 memopv16f32, vselect, v16f32>,
764 EVEX_CD8<32, CD8VF>, EVEX_V512;
765 let ExeDomain = SSEPackedDouble in
766 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
767 VK8WM, VR512, f512mem,
768 memopv8f64, vselect, v8f64>,
769 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
771 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
772 (v16f32 VR512:$src2), (i16 GR16:$mask))),
773 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
774 VR512:$src1, VR512:$src2)>;
776 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
777 (v8f64 VR512:$src2), (i8 GR8:$mask))),
778 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
779 VR512:$src1, VR512:$src2)>;
781 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
782 VK16WM, VR512, f512mem,
783 memopv16i32, vselect, v16i32>,
784 EVEX_CD8<32, CD8VF>, EVEX_V512;
786 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
787 VK8WM, VR512, f512mem,
788 memopv8i64, vselect, v8i64>,
789 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
791 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
792 (v16i32 VR512:$src2), (i16 GR16:$mask))),
793 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
794 VR512:$src1, VR512:$src2)>;
796 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
797 (v8i64 VR512:$src2), (i8 GR8:$mask))),
798 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
799 VR512:$src1, VR512:$src2)>;
801 let Predicates = [HasAVX512] in {
802 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
803 (v8f32 VR256X:$src2))),
805 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
806 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
807 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
809 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
810 (v8i32 VR256X:$src2))),
812 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
814 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
816 //===----------------------------------------------------------------------===//
817 // Compare Instructions
818 //===----------------------------------------------------------------------===//
820 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
821 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
822 Operand CC, SDNode OpNode, ValueType VT,
823 PatFrag ld_frag, string asm, string asm_alt> {
824 def rr : AVX512Ii8<0xC2, MRMSrcReg,
825 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
826 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
827 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
828 def rm : AVX512Ii8<0xC2, MRMSrcMem,
829 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
830 [(set VK1:$dst, (OpNode (VT RC:$src1),
831 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
832 let isAsmParserOnly = 1, hasSideEffects = 0 in {
833 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
834 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
835 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
836 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
837 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
838 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
842 let Predicates = [HasAVX512] in {
843 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
844 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
845 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
847 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
848 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
849 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
853 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
854 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
855 SDNode OpNode, ValueType vt> {
856 def rr : AVX512BI<opc, MRMSrcReg,
857 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
858 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
859 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
860 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
861 def rm : AVX512BI<opc, MRMSrcMem,
862 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
863 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
864 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
865 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
868 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
869 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
871 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
872 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
873 VEX_W, EVEX_CD8<64, CD8VF>;
875 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
876 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
878 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
879 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
880 VEX_W, EVEX_CD8<64, CD8VF>;
882 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
883 (COPY_TO_REGCLASS (VPCMPGTDZrr
884 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
885 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
887 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
888 (COPY_TO_REGCLASS (VPCMPEQDZrr
889 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
890 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
892 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass WMRC, RegisterClass KRC,
893 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
894 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
895 def rri : AVX512AIi8<opc, MRMSrcReg,
896 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
897 !strconcat("vpcmp${cc}", Suffix,
898 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
899 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
900 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
901 def rmi : AVX512AIi8<opc, MRMSrcMem,
902 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
903 !strconcat("vpcmp${cc}", Suffix,
904 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
905 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
906 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
907 // Accept explicit immediate argument form instead of comparison code.
908 let isAsmParserOnly = 1, hasSideEffects = 0 in {
909 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
910 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
911 !strconcat("vpcmp", Suffix,
912 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
913 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
914 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
915 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
916 !strconcat("vpcmp", Suffix,
917 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
918 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
919 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
920 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
921 !strconcat("vpcmp", Suffix,
922 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
923 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
924 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
925 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
926 !strconcat("vpcmp", Suffix,
927 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
928 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
932 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16WM, VK16, VR512, i512mem, memopv16i32,
933 X86cmpm, v16i32, AVXCC, "d">,
934 EVEX_V512, EVEX_CD8<32, CD8VF>;
935 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16WM, VK16, VR512, i512mem, memopv16i32,
936 X86cmpmu, v16i32, AVXCC, "ud">,
937 EVEX_V512, EVEX_CD8<32, CD8VF>;
939 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8WM, VK8, VR512, i512mem, memopv8i64,
940 X86cmpm, v8i64, AVXCC, "q">,
941 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
942 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8WM, VK8, VR512, i512mem, memopv8i64,
943 X86cmpmu, v8i64, AVXCC, "uq">,
944 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
946 // avx512_cmp_packed - compare packed instructions
947 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
948 X86MemOperand x86memop, ValueType vt,
949 string suffix, Domain d> {
950 def rri : AVX512PIi8<0xC2, MRMSrcReg,
951 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
952 !strconcat("vcmp${cc}", suffix,
953 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
954 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
955 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
956 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
957 !strconcat("vcmp${cc}", suffix,
958 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
960 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
961 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
962 !strconcat("vcmp${cc}", suffix,
963 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
965 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
967 // Accept explicit immediate argument form instead of comparison code.
968 let isAsmParserOnly = 1, hasSideEffects = 0 in {
969 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
970 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
971 !strconcat("vcmp", suffix,
972 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
973 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
974 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
975 !strconcat("vcmp", suffix,
976 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
980 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
981 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
983 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
984 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
987 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
988 (COPY_TO_REGCLASS (VCMPPSZrri
989 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
990 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
992 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
993 (COPY_TO_REGCLASS (VPCMPDZrri
994 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
995 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
997 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
998 (COPY_TO_REGCLASS (VPCMPUDZrri
999 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1000 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1003 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1004 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1006 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1007 (I8Imm imm:$cc)), GR16)>;
1009 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1010 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1012 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1013 (I8Imm imm:$cc)), GR8)>;
1015 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1016 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1018 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1019 (I8Imm imm:$cc)), GR16)>;
1021 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1022 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1024 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1025 (I8Imm imm:$cc)), GR8)>;
1027 // Mask register copy, including
1028 // - copy between mask registers
1029 // - load/store mask registers
1030 // - copy from GPR to mask register and vice versa
1032 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1033 string OpcodeStr, RegisterClass KRC,
1034 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1035 let hasSideEffects = 0 in {
1036 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1037 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1039 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1040 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1041 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1043 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1044 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1048 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1050 RegisterClass KRC, RegisterClass GRC> {
1051 let hasSideEffects = 0 in {
1052 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1053 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1054 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1055 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1059 let Predicates = [HasDQI] in
1060 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1062 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1065 let Predicates = [HasAVX512] in
1066 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1068 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1071 let Predicates = [HasBWI] in {
1072 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1073 i32mem>, VEX, PD, VEX_W;
1074 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1078 let Predicates = [HasBWI] in {
1079 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1080 i64mem>, VEX, PS, VEX_W;
1081 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1085 // GR from/to mask register
1086 let Predicates = [HasDQI] in {
1087 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1088 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1089 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1090 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1092 let Predicates = [HasAVX512] in {
1093 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1094 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1095 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1096 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1098 let Predicates = [HasBWI] in {
1099 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1100 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1102 let Predicates = [HasBWI] in {
1103 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1104 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1108 let Predicates = [HasDQI] in {
1109 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1110 (KMOVBmk addr:$dst, VK8:$src)>;
1112 let Predicates = [HasAVX512] in {
1113 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1114 (KMOVWmk addr:$dst, VK16:$src)>;
1115 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1116 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1117 def : Pat<(i1 (load addr:$src)),
1118 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1119 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1120 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1122 let Predicates = [HasBWI] in {
1123 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1124 (KMOVDmk addr:$dst, VK32:$src)>;
1126 let Predicates = [HasBWI] in {
1127 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1128 (KMOVQmk addr:$dst, VK64:$src)>;
1131 let Predicates = [HasAVX512] in {
1132 def : Pat<(i1 (trunc (i32 GR32:$src))),
1133 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1135 def : Pat<(i1 (trunc (i8 GR8:$src))),
1137 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1139 def : Pat<(i1 (trunc (i16 GR16:$src))),
1141 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1144 def : Pat<(i32 (zext VK1:$src)),
1145 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1146 def : Pat<(i8 (zext VK1:$src)),
1149 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1150 def : Pat<(i64 (zext VK1:$src)),
1151 (AND64ri8 (SUBREG_TO_REG (i64 0),
1152 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1153 def : Pat<(i16 (zext VK1:$src)),
1155 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1157 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1158 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1159 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1160 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1162 let Predicates = [HasBWI] in {
1163 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1164 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1165 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1166 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1170 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1171 let Predicates = [HasAVX512] in {
1172 // GR from/to 8-bit mask without native support
1173 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1175 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1177 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1179 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1182 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1183 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1184 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1185 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1187 let Predicates = [HasBWI] in {
1188 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1189 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1190 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1191 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1194 // Mask unary operation
1196 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1197 RegisterClass KRC, SDPatternOperator OpNode,
1199 let Predicates = [prd] in
1200 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1201 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1202 [(set KRC:$dst, (OpNode KRC:$src))]>;
1205 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1206 SDPatternOperator OpNode> {
1207 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1209 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1210 HasAVX512>, VEX, PS;
1211 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1212 HasBWI>, VEX, PD, VEX_W;
1213 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1214 HasBWI>, VEX, PS, VEX_W;
1217 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1219 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1220 let Predicates = [HasAVX512] in
1221 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1223 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1224 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1226 defm : avx512_mask_unop_int<"knot", "KNOT">;
1228 let Predicates = [HasDQI] in
1229 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1230 let Predicates = [HasAVX512] in
1231 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1232 let Predicates = [HasBWI] in
1233 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1234 let Predicates = [HasBWI] in
1235 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1237 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1238 let Predicates = [HasAVX512] in {
1239 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1240 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1242 def : Pat<(not VK8:$src),
1244 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1247 // Mask binary operation
1248 // - KAND, KANDN, KOR, KXNOR, KXOR
1249 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1250 RegisterClass KRC, SDPatternOperator OpNode> {
1251 let Predicates = [HasAVX512] in
1252 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1253 !strconcat(OpcodeStr,
1254 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1255 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1258 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1259 SDPatternOperator OpNode> {
1260 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1264 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1265 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1267 let isCommutable = 1 in {
1268 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1269 let isCommutable = 0 in
1270 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1271 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1272 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1273 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1276 def : Pat<(xor VK1:$src1, VK1:$src2),
1277 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1278 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1280 def : Pat<(or VK1:$src1, VK1:$src2),
1281 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1282 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1284 def : Pat<(and VK1:$src1, VK1:$src2),
1285 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1286 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1288 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1289 let Predicates = [HasAVX512] in
1290 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1291 (i16 GR16:$src1), (i16 GR16:$src2)),
1292 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1293 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1294 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1297 defm : avx512_mask_binop_int<"kand", "KAND">;
1298 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1299 defm : avx512_mask_binop_int<"kor", "KOR">;
1300 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1301 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1303 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1304 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1305 let Predicates = [HasAVX512] in
1306 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1308 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1309 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1312 defm : avx512_binop_pat<and, KANDWrr>;
1313 defm : avx512_binop_pat<andn, KANDNWrr>;
1314 defm : avx512_binop_pat<or, KORWrr>;
1315 defm : avx512_binop_pat<xnor, KXNORWrr>;
1316 defm : avx512_binop_pat<xor, KXORWrr>;
1319 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1320 RegisterClass KRC> {
1321 let Predicates = [HasAVX512] in
1322 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1323 !strconcat(OpcodeStr,
1324 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1327 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1328 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1332 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1333 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1334 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1335 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1338 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1339 let Predicates = [HasAVX512] in
1340 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1341 (i16 GR16:$src1), (i16 GR16:$src2)),
1342 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1343 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1344 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1346 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1349 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1351 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1352 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1353 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1354 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1357 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1358 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1362 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1364 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1365 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1366 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1369 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1371 let Predicates = [HasAVX512] in
1372 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1373 !strconcat(OpcodeStr,
1374 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1375 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1378 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1380 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1384 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1385 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1387 // Mask setting all 0s or 1s
1388 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1389 let Predicates = [HasAVX512] in
1390 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1391 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1392 [(set KRC:$dst, (VT Val))]>;
1395 multiclass avx512_mask_setop_w<PatFrag Val> {
1396 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1397 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1400 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1401 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1403 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1404 let Predicates = [HasAVX512] in {
1405 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1406 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1407 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1408 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1409 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1411 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1412 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1414 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1415 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1417 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1418 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1420 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1421 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1423 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1424 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1425 //===----------------------------------------------------------------------===//
1426 // AVX-512 - Aligned and unaligned load and store
1429 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1430 X86MemOperand x86memop, PatFrag ld_frag,
1431 string asm, Domain d,
1432 ValueType vt, bit IsReMaterializable = 1> {
1433 let hasSideEffects = 0 in {
1434 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1435 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1437 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1439 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1440 [], d>, EVEX, EVEX_KZ;
1442 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1443 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1444 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1445 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1446 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1447 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1448 (ins RC:$src1, KRC:$mask, RC:$src2),
1450 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1453 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1454 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1456 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1457 [], d>, EVEX, EVEX_K;
1460 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1461 (ins KRC:$mask, x86memop:$src2),
1463 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1464 [], d>, EVEX, EVEX_KZ;
1467 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1468 X86MemOperand x86memop, PatFrag store_frag,
1469 string asm, Domain d, ValueType vt> {
1470 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1471 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1472 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1474 let Constraints = "$src1 = $dst" in
1475 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1476 (ins RC:$src1, KRC:$mask, RC:$src2),
1478 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1480 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1481 (ins KRC:$mask, RC:$src),
1483 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1484 [], d>, EVEX, EVEX_KZ;
1486 let mayStore = 1 in {
1487 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1488 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1489 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1490 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1491 (ins x86memop:$dst, KRC:$mask, RC:$src),
1493 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1494 [], d>, EVEX, EVEX_K;
1495 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1496 (ins x86memop:$dst, KRC:$mask, RC:$src),
1498 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1499 [], d>, EVEX, EVEX_KZ;
1503 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1504 "vmovaps", SSEPackedSingle, v16f32>,
1505 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1506 "vmovaps", SSEPackedSingle, v16f32>,
1507 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1508 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1509 "vmovapd", SSEPackedDouble, v8f64>,
1510 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1511 "vmovapd", SSEPackedDouble, v8f64>,
1512 PD, EVEX_V512, VEX_W,
1513 EVEX_CD8<64, CD8VF>;
1514 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1515 "vmovups", SSEPackedSingle, v16f32>,
1516 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1517 "vmovups", SSEPackedSingle, v16f32>,
1518 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1519 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1520 "vmovupd", SSEPackedDouble, v8f64, 0>,
1521 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1522 "vmovupd", SSEPackedDouble, v8f64>,
1523 PD, EVEX_V512, VEX_W,
1524 EVEX_CD8<64, CD8VF>;
1525 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1526 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1527 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1529 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1530 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1531 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1533 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1535 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1537 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1539 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1542 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1543 "vmovdqa32", SSEPackedInt, v16i32>,
1544 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1545 "vmovdqa32", SSEPackedInt, v16i32>,
1546 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1547 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1548 "vmovdqa64", SSEPackedInt, v8i64>,
1549 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1550 "vmovdqa64", SSEPackedInt, v8i64>,
1551 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1552 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1553 "vmovdqu32", SSEPackedInt, v16i32>,
1554 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1555 "vmovdqu32", SSEPackedInt, v16i32>,
1556 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1557 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1558 "vmovdqu64", SSEPackedInt, v8i64>,
1559 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1560 "vmovdqu64", SSEPackedInt, v8i64>,
1561 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1563 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1564 (v16i32 immAllZerosV), GR16:$mask)),
1565 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1567 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1568 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1569 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1571 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1573 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1575 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1577 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1580 let AddedComplexity = 20 in {
1581 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1582 (bc_v8i64 (v16i32 immAllZerosV)))),
1583 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1585 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1586 (v8i64 VR512:$src))),
1587 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1590 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1591 (v16i32 immAllZerosV))),
1592 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1594 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1595 (v16i32 VR512:$src))),
1596 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1598 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1599 (v16f32 VR512:$src2))),
1600 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1601 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1602 (v8f64 VR512:$src2))),
1603 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1604 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1605 (v16i32 VR512:$src2))),
1606 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1607 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1608 (v8i64 VR512:$src2))),
1609 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1611 // Move Int Doubleword to Packed Double Int
1613 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1614 "vmovd\t{$src, $dst|$dst, $src}",
1616 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1618 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1619 "vmovd\t{$src, $dst|$dst, $src}",
1621 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1622 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1623 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1624 "vmovq\t{$src, $dst|$dst, $src}",
1626 (v2i64 (scalar_to_vector GR64:$src)))],
1627 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1628 let isCodeGenOnly = 1 in {
1629 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1630 "vmovq\t{$src, $dst|$dst, $src}",
1631 [(set FR64:$dst, (bitconvert GR64:$src))],
1632 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1633 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1634 "vmovq\t{$src, $dst|$dst, $src}",
1635 [(set GR64:$dst, (bitconvert FR64:$src))],
1636 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1638 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1639 "vmovq\t{$src, $dst|$dst, $src}",
1640 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1641 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1642 EVEX_CD8<64, CD8VT1>;
1644 // Move Int Doubleword to Single Scalar
1646 let isCodeGenOnly = 1 in {
1647 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1648 "vmovd\t{$src, $dst|$dst, $src}",
1649 [(set FR32X:$dst, (bitconvert GR32:$src))],
1650 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1652 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1653 "vmovd\t{$src, $dst|$dst, $src}",
1654 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1655 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1658 // Move doubleword from xmm register to r/m32
1660 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1661 "vmovd\t{$src, $dst|$dst, $src}",
1662 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1663 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1665 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1666 (ins i32mem:$dst, VR128X:$src),
1667 "vmovd\t{$src, $dst|$dst, $src}",
1668 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1669 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1670 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1672 // Move quadword from xmm1 register to r/m64
1674 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1675 "vmovq\t{$src, $dst|$dst, $src}",
1676 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1678 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1679 Requires<[HasAVX512, In64BitMode]>;
1681 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1682 (ins i64mem:$dst, VR128X:$src),
1683 "vmovq\t{$src, $dst|$dst, $src}",
1684 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1685 addr:$dst)], IIC_SSE_MOVDQ>,
1686 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1687 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1689 // Move Scalar Single to Double Int
1691 let isCodeGenOnly = 1 in {
1692 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1694 "vmovd\t{$src, $dst|$dst, $src}",
1695 [(set GR32:$dst, (bitconvert FR32X:$src))],
1696 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1697 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1698 (ins i32mem:$dst, FR32X:$src),
1699 "vmovd\t{$src, $dst|$dst, $src}",
1700 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1701 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1704 // Move Quadword Int to Packed Quadword Int
1706 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1708 "vmovq\t{$src, $dst|$dst, $src}",
1710 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1711 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1713 //===----------------------------------------------------------------------===//
1714 // AVX-512 MOVSS, MOVSD
1715 //===----------------------------------------------------------------------===//
1717 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1718 SDNode OpNode, ValueType vt,
1719 X86MemOperand x86memop, PatFrag mem_pat> {
1720 let hasSideEffects = 0 in {
1721 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1722 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1723 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1724 (scalar_to_vector RC:$src2))))],
1725 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1726 let Constraints = "$src1 = $dst" in
1727 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1728 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1730 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1731 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1732 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1733 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1734 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1736 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1737 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1738 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1740 } //hasSideEffects = 0
1743 let ExeDomain = SSEPackedSingle in
1744 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1745 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1747 let ExeDomain = SSEPackedDouble in
1748 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1749 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1751 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1752 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1753 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1755 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1756 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1757 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1759 // For the disassembler
1760 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1761 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1762 (ins VR128X:$src1, FR32X:$src2),
1763 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1765 XS, EVEX_4V, VEX_LIG;
1766 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1767 (ins VR128X:$src1, FR64X:$src2),
1768 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1770 XD, EVEX_4V, VEX_LIG, VEX_W;
1773 let Predicates = [HasAVX512] in {
1774 let AddedComplexity = 15 in {
1775 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1776 // MOVS{S,D} to the lower bits.
1777 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1778 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1779 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1780 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1781 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1782 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1783 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1784 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1786 // Move low f32 and clear high bits.
1787 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1788 (SUBREG_TO_REG (i32 0),
1789 (VMOVSSZrr (v4f32 (V_SET0)),
1790 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1791 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1792 (SUBREG_TO_REG (i32 0),
1793 (VMOVSSZrr (v4i32 (V_SET0)),
1794 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1797 let AddedComplexity = 20 in {
1798 // MOVSSrm zeros the high parts of the register; represent this
1799 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1800 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1801 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1802 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1803 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1804 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1805 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1807 // MOVSDrm zeros the high parts of the register; represent this
1808 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1809 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1810 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1811 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1812 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1813 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1814 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1815 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1816 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1817 def : Pat<(v2f64 (X86vzload addr:$src)),
1818 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1820 // Represent the same patterns above but in the form they appear for
1822 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1823 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1824 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1825 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1826 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1827 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1828 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1829 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1830 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1832 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1833 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1834 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1835 FR32X:$src)), sub_xmm)>;
1836 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1837 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1838 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1839 FR64X:$src)), sub_xmm)>;
1840 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1841 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1842 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1844 // Move low f64 and clear high bits.
1845 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1846 (SUBREG_TO_REG (i32 0),
1847 (VMOVSDZrr (v2f64 (V_SET0)),
1848 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1850 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1851 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1852 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1854 // Extract and store.
1855 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1857 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1858 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1860 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1862 // Shuffle with VMOVSS
1863 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1864 (VMOVSSZrr (v4i32 VR128X:$src1),
1865 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1866 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1867 (VMOVSSZrr (v4f32 VR128X:$src1),
1868 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1871 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1872 (SUBREG_TO_REG (i32 0),
1873 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1874 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1876 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1877 (SUBREG_TO_REG (i32 0),
1878 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1879 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1882 // Shuffle with VMOVSD
1883 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1884 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1885 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1886 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1887 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1888 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1889 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1890 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1893 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1894 (SUBREG_TO_REG (i32 0),
1895 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1896 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1898 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1899 (SUBREG_TO_REG (i32 0),
1900 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1901 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1904 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1905 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1906 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1907 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1908 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1909 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1910 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1911 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1914 let AddedComplexity = 15 in
1915 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1917 "vmovq\t{$src, $dst|$dst, $src}",
1918 [(set VR128X:$dst, (v2i64 (X86vzmovl
1919 (v2i64 VR128X:$src))))],
1920 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1922 let AddedComplexity = 20 in
1923 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1925 "vmovq\t{$src, $dst|$dst, $src}",
1926 [(set VR128X:$dst, (v2i64 (X86vzmovl
1927 (loadv2i64 addr:$src))))],
1928 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1929 EVEX_CD8<8, CD8VT8>;
1931 let Predicates = [HasAVX512] in {
1932 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1933 let AddedComplexity = 20 in {
1934 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1935 (VMOVDI2PDIZrm addr:$src)>;
1936 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1937 (VMOV64toPQIZrr GR64:$src)>;
1938 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1939 (VMOVDI2PDIZrr GR32:$src)>;
1941 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1942 (VMOVDI2PDIZrm addr:$src)>;
1943 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1944 (VMOVDI2PDIZrm addr:$src)>;
1945 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1946 (VMOVZPQILo2PQIZrm addr:$src)>;
1947 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1948 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1949 def : Pat<(v2i64 (X86vzload addr:$src)),
1950 (VMOVZPQILo2PQIZrm addr:$src)>;
1953 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1954 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1955 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1956 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1957 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1958 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1959 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1962 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1963 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1965 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1966 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1968 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1969 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1971 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1972 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1974 //===----------------------------------------------------------------------===//
1975 // AVX-512 - Non-temporals
1976 //===----------------------------------------------------------------------===//
1978 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1980 "vmovntdqa\t{$src, $dst|$dst, $src}",
1982 (int_x86_avx512_movntdqa addr:$src))]>,
1983 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1985 // Prefer non-temporal over temporal versions
1986 let AddedComplexity = 400, SchedRW = [WriteStore] in {
1988 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
1989 (ins f512mem:$dst, VR512:$src),
1990 "vmovntps\t{$src, $dst|$dst, $src}",
1991 [(alignednontemporalstore (v16f32 VR512:$src),
1994 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1996 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
1997 (ins f512mem:$dst, VR512:$src),
1998 "vmovntpd\t{$src, $dst|$dst, $src}",
1999 [(alignednontemporalstore (v8f64 VR512:$src),
2002 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2005 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
2006 (ins i512mem:$dst, VR512:$src),
2007 "vmovntdq\t{$src, $dst|$dst, $src}",
2008 [(alignednontemporalstore (v8i64 VR512:$src),
2011 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2014 //===----------------------------------------------------------------------===//
2015 // AVX-512 - Integer arithmetic
2017 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2018 ValueType OpVT, RegisterClass KRC,
2019 RegisterClass RC, PatFrag memop_frag,
2020 X86MemOperand x86memop, PatFrag scalar_mfrag,
2021 X86MemOperand x86scalar_mop, string BrdcstStr,
2022 OpndItins itins, bit IsCommutable = 0> {
2023 let isCommutable = IsCommutable in
2024 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2025 (ins RC:$src1, RC:$src2),
2026 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2027 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2029 let AddedComplexity = 30 in {
2030 let Constraints = "$src0 = $dst" in
2031 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2032 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2033 !strconcat(OpcodeStr,
2034 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2035 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2036 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2038 itins.rr>, EVEX_4V, EVEX_K;
2039 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2040 (ins KRC:$mask, RC:$src1, RC:$src2),
2041 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2042 "|$dst {${mask}} {z}, $src1, $src2}"),
2043 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2044 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2045 (OpVT immAllZerosV))))],
2046 itins.rr>, EVEX_4V, EVEX_KZ;
2049 let mayLoad = 1 in {
2050 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2051 (ins RC:$src1, x86memop:$src2),
2052 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2053 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2055 let AddedComplexity = 30 in {
2056 let Constraints = "$src0 = $dst" in
2057 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2058 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2059 !strconcat(OpcodeStr,
2060 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2061 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2062 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2064 itins.rm>, EVEX_4V, EVEX_K;
2065 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2066 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2067 !strconcat(OpcodeStr,
2068 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2069 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2070 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2071 (OpVT immAllZerosV))))],
2072 itins.rm>, EVEX_4V, EVEX_KZ;
2074 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2075 (ins RC:$src1, x86scalar_mop:$src2),
2076 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2077 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2078 [(set RC:$dst, (OpNode RC:$src1,
2079 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2080 itins.rm>, EVEX_4V, EVEX_B;
2081 let AddedComplexity = 30 in {
2082 let Constraints = "$src0 = $dst" in
2083 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2084 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2085 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2086 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2088 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2089 (OpNode (OpVT RC:$src1),
2090 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2092 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2093 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2094 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2095 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2096 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2098 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2099 (OpNode (OpVT RC:$src1),
2100 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2101 (OpVT immAllZerosV))))],
2102 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2107 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2108 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2109 PatFrag memop_frag, X86MemOperand x86memop,
2110 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2111 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2112 let isCommutable = IsCommutable in
2114 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2115 (ins RC:$src1, RC:$src2),
2116 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2118 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2119 (ins KRC:$mask, RC:$src1, RC:$src2),
2120 !strconcat(OpcodeStr,
2121 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2122 [], itins.rr>, EVEX_4V, EVEX_K;
2123 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2124 (ins KRC:$mask, RC:$src1, RC:$src2),
2125 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2126 "|$dst {${mask}} {z}, $src1, $src2}"),
2127 [], itins.rr>, EVEX_4V, EVEX_KZ;
2129 let mayLoad = 1 in {
2130 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2131 (ins RC:$src1, x86memop:$src2),
2132 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2134 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2135 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2136 !strconcat(OpcodeStr,
2137 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2138 [], itins.rm>, EVEX_4V, EVEX_K;
2139 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2140 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2141 !strconcat(OpcodeStr,
2142 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2143 [], itins.rm>, EVEX_4V, EVEX_KZ;
2144 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2145 (ins RC:$src1, x86scalar_mop:$src2),
2146 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2147 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2148 [], itins.rm>, EVEX_4V, EVEX_B;
2149 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2150 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2151 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2152 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2154 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2155 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2156 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2157 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2158 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2160 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2164 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2165 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2166 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2168 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2169 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2170 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2172 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2173 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2174 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2176 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2177 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2178 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2180 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2181 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2182 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2184 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2185 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2186 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2187 EVEX_CD8<64, CD8VF>, VEX_W;
2189 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2190 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2191 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2193 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2194 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2196 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2197 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2198 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2199 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2200 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2201 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2203 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2204 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2205 SSE_INTALU_ITINS_P, 1>,
2206 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2207 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2208 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2209 SSE_INTALU_ITINS_P, 0>,
2210 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2212 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2213 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2214 SSE_INTALU_ITINS_P, 1>,
2215 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2216 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2217 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2218 SSE_INTALU_ITINS_P, 0>,
2219 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2221 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2222 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2223 SSE_INTALU_ITINS_P, 1>,
2224 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2225 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2226 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2227 SSE_INTALU_ITINS_P, 0>,
2228 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2230 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2231 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2232 SSE_INTALU_ITINS_P, 1>,
2233 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2234 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2235 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2236 SSE_INTALU_ITINS_P, 0>,
2237 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2239 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2240 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2241 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2242 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2243 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2244 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2245 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2246 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2247 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2248 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2249 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2250 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2251 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2252 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2253 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2254 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2255 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2256 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2257 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2258 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2259 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2260 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2261 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2262 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2263 //===----------------------------------------------------------------------===//
2264 // AVX-512 - Unpack Instructions
2265 //===----------------------------------------------------------------------===//
2267 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2268 PatFrag mem_frag, RegisterClass RC,
2269 X86MemOperand x86memop, string asm,
2271 def rr : AVX512PI<opc, MRMSrcReg,
2272 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2274 (vt (OpNode RC:$src1, RC:$src2)))],
2276 def rm : AVX512PI<opc, MRMSrcMem,
2277 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2279 (vt (OpNode RC:$src1,
2280 (bitconvert (mem_frag addr:$src2)))))],
2284 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2285 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2286 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2287 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2288 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2289 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2290 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2291 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2292 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2293 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2294 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2295 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2297 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2298 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2299 X86MemOperand x86memop> {
2300 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2301 (ins RC:$src1, RC:$src2),
2302 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2303 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2304 IIC_SSE_UNPCK>, EVEX_4V;
2305 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2306 (ins RC:$src1, x86memop:$src2),
2307 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2308 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2309 (bitconvert (memop_frag addr:$src2)))))],
2310 IIC_SSE_UNPCK>, EVEX_4V;
2312 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2313 VR512, memopv16i32, i512mem>, EVEX_V512,
2314 EVEX_CD8<32, CD8VF>;
2315 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2316 VR512, memopv8i64, i512mem>, EVEX_V512,
2317 VEX_W, EVEX_CD8<64, CD8VF>;
2318 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2319 VR512, memopv16i32, i512mem>, EVEX_V512,
2320 EVEX_CD8<32, CD8VF>;
2321 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2322 VR512, memopv8i64, i512mem>, EVEX_V512,
2323 VEX_W, EVEX_CD8<64, CD8VF>;
2324 //===----------------------------------------------------------------------===//
2328 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2329 SDNode OpNode, PatFrag mem_frag,
2330 X86MemOperand x86memop, ValueType OpVT> {
2331 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2332 (ins RC:$src1, i8imm:$src2),
2333 !strconcat(OpcodeStr,
2334 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2336 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2338 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2339 (ins x86memop:$src1, i8imm:$src2),
2340 !strconcat(OpcodeStr,
2341 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2343 (OpVT (OpNode (mem_frag addr:$src1),
2344 (i8 imm:$src2))))]>, EVEX;
2347 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2348 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2350 let ExeDomain = SSEPackedSingle in
2351 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2352 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2353 EVEX_CD8<32, CD8VF>;
2354 let ExeDomain = SSEPackedDouble in
2355 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2356 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2357 VEX_W, EVEX_CD8<32, CD8VF>;
2359 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2360 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2361 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2362 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2364 //===----------------------------------------------------------------------===//
2365 // AVX-512 Logical Instructions
2366 //===----------------------------------------------------------------------===//
2368 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2369 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2370 EVEX_V512, EVEX_CD8<32, CD8VF>;
2371 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2372 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2373 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2374 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2375 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2376 EVEX_V512, EVEX_CD8<32, CD8VF>;
2377 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2378 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2379 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2380 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2381 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2382 EVEX_V512, EVEX_CD8<32, CD8VF>;
2383 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2384 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2385 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2386 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2387 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2388 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2389 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2390 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2391 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2393 //===----------------------------------------------------------------------===//
2394 // AVX-512 FP arithmetic
2395 //===----------------------------------------------------------------------===//
2397 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2399 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2400 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2401 EVEX_CD8<32, CD8VT1>;
2402 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2403 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2404 EVEX_CD8<64, CD8VT1>;
2407 let isCommutable = 1 in {
2408 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2409 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2410 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2411 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2413 let isCommutable = 0 in {
2414 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2415 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2418 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2420 RegisterClass RC, ValueType vt,
2421 X86MemOperand x86memop, PatFrag mem_frag,
2422 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2424 Domain d, OpndItins itins, bit commutable> {
2425 let isCommutable = commutable in {
2426 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2427 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2428 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2431 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2432 !strconcat(OpcodeStr,
2433 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2434 [], itins.rr, d>, EVEX_4V, EVEX_K;
2436 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2437 !strconcat(OpcodeStr,
2438 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2439 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2442 let mayLoad = 1 in {
2443 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2444 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2445 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2446 itins.rm, d>, EVEX_4V;
2448 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2449 (ins RC:$src1, x86scalar_mop:$src2),
2450 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2451 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2452 [(set RC:$dst, (OpNode RC:$src1,
2453 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2454 itins.rm, d>, EVEX_4V, EVEX_B;
2456 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2457 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2458 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2459 [], itins.rm, d>, EVEX_4V, EVEX_K;
2461 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2462 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2463 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2464 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2466 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2467 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2468 " \t{${src2}", BrdcstStr,
2469 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2470 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2472 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2473 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2474 " \t{${src2}", BrdcstStr,
2475 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2477 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2481 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2482 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2483 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2485 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2486 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2487 SSE_ALU_ITINS_P.d, 1>,
2488 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2490 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2491 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2492 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2493 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2494 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2495 SSE_ALU_ITINS_P.d, 1>,
2496 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2498 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2499 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2500 SSE_ALU_ITINS_P.s, 1>,
2501 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2502 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2503 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2504 SSE_ALU_ITINS_P.s, 1>,
2505 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2507 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2508 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2509 SSE_ALU_ITINS_P.d, 1>,
2510 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2511 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2512 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2513 SSE_ALU_ITINS_P.d, 1>,
2514 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2516 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2517 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2518 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2519 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2520 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2521 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2523 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2524 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2525 SSE_ALU_ITINS_P.d, 0>,
2526 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2527 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2528 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2529 SSE_ALU_ITINS_P.d, 0>,
2530 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2532 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2533 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2534 (i16 -1), FROUND_CURRENT)),
2535 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2537 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2538 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2539 (i8 -1), FROUND_CURRENT)),
2540 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2542 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2543 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2544 (i16 -1), FROUND_CURRENT)),
2545 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2547 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2548 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2549 (i8 -1), FROUND_CURRENT)),
2550 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2551 //===----------------------------------------------------------------------===//
2552 // AVX-512 VPTESTM instructions
2553 //===----------------------------------------------------------------------===//
2555 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2556 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2557 SDNode OpNode, ValueType vt> {
2558 def rr : AVX512PI<opc, MRMSrcReg,
2559 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2560 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2561 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2562 SSEPackedInt>, EVEX_4V;
2563 def rm : AVX512PI<opc, MRMSrcMem,
2564 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2565 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2566 [(set KRC:$dst, (OpNode (vt RC:$src1),
2567 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2570 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2571 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2572 EVEX_CD8<32, CD8VF>;
2573 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2574 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2575 EVEX_CD8<64, CD8VF>;
2577 let Predicates = [HasCDI] in {
2578 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2579 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2580 EVEX_CD8<32, CD8VF>;
2581 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2582 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2583 EVEX_CD8<64, CD8VF>;
2586 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2587 (v16i32 VR512:$src2), (i16 -1))),
2588 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2590 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2591 (v8i64 VR512:$src2), (i8 -1))),
2592 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2593 //===----------------------------------------------------------------------===//
2594 // AVX-512 Shift instructions
2595 //===----------------------------------------------------------------------===//
2596 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2597 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2598 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2599 RegisterClass KRC> {
2600 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2601 (ins RC:$src1, i8imm:$src2),
2602 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2603 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2604 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2605 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2606 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2607 !strconcat(OpcodeStr,
2608 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2609 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2610 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2611 (ins x86memop:$src1, i8imm:$src2),
2612 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2613 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2614 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2615 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2616 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2617 !strconcat(OpcodeStr,
2618 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2619 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2622 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2623 RegisterClass RC, ValueType vt, ValueType SrcVT,
2624 PatFrag bc_frag, RegisterClass KRC> {
2625 // src2 is always 128-bit
2626 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2627 (ins RC:$src1, VR128X:$src2),
2628 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2629 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2630 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2631 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2632 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2633 !strconcat(OpcodeStr,
2634 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2635 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2636 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2637 (ins RC:$src1, i128mem:$src2),
2638 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2639 [(set RC:$dst, (vt (OpNode RC:$src1,
2640 (bc_frag (memopv2i64 addr:$src2)))))],
2641 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2642 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2643 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2644 !strconcat(OpcodeStr,
2645 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2646 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2649 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2650 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2651 EVEX_V512, EVEX_CD8<32, CD8VF>;
2652 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2653 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2654 EVEX_CD8<32, CD8VQ>;
2656 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2657 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2658 EVEX_CD8<64, CD8VF>, VEX_W;
2659 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2660 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2661 EVEX_CD8<64, CD8VQ>, VEX_W;
2663 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2664 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2665 EVEX_CD8<32, CD8VF>;
2666 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2667 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2668 EVEX_CD8<32, CD8VQ>;
2670 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2671 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2672 EVEX_CD8<64, CD8VF>, VEX_W;
2673 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2674 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2675 EVEX_CD8<64, CD8VQ>, VEX_W;
2677 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2678 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2679 EVEX_V512, EVEX_CD8<32, CD8VF>;
2680 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2681 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2682 EVEX_CD8<32, CD8VQ>;
2684 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2685 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2686 EVEX_CD8<64, CD8VF>, VEX_W;
2687 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2688 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2689 EVEX_CD8<64, CD8VQ>, VEX_W;
2691 //===-------------------------------------------------------------------===//
2692 // Variable Bit Shifts
2693 //===-------------------------------------------------------------------===//
2694 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2695 RegisterClass RC, ValueType vt,
2696 X86MemOperand x86memop, PatFrag mem_frag> {
2697 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2698 (ins RC:$src1, RC:$src2),
2699 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2701 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2703 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2704 (ins RC:$src1, x86memop:$src2),
2705 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2707 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2711 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2712 i512mem, memopv16i32>, EVEX_V512,
2713 EVEX_CD8<32, CD8VF>;
2714 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2715 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2716 EVEX_CD8<64, CD8VF>;
2717 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2718 i512mem, memopv16i32>, EVEX_V512,
2719 EVEX_CD8<32, CD8VF>;
2720 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2721 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2722 EVEX_CD8<64, CD8VF>;
2723 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2724 i512mem, memopv16i32>, EVEX_V512,
2725 EVEX_CD8<32, CD8VF>;
2726 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2727 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2728 EVEX_CD8<64, CD8VF>;
2730 //===----------------------------------------------------------------------===//
2731 // AVX-512 - MOVDDUP
2732 //===----------------------------------------------------------------------===//
2734 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2735 X86MemOperand x86memop, PatFrag memop_frag> {
2736 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2737 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2738 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2739 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2740 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2742 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2745 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2746 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2747 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2748 (VMOVDDUPZrm addr:$src)>;
2750 //===---------------------------------------------------------------------===//
2751 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2752 //===---------------------------------------------------------------------===//
2753 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2754 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2755 X86MemOperand x86memop> {
2756 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2757 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2758 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2760 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2761 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2762 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2765 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2766 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2767 EVEX_CD8<32, CD8VF>;
2768 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2769 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2770 EVEX_CD8<32, CD8VF>;
2772 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2773 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2774 (VMOVSHDUPZrm addr:$src)>;
2775 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2776 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2777 (VMOVSLDUPZrm addr:$src)>;
2779 //===----------------------------------------------------------------------===//
2780 // Move Low to High and High to Low packed FP Instructions
2781 //===----------------------------------------------------------------------===//
2782 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2783 (ins VR128X:$src1, VR128X:$src2),
2784 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2785 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2786 IIC_SSE_MOV_LH>, EVEX_4V;
2787 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2788 (ins VR128X:$src1, VR128X:$src2),
2789 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2790 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2791 IIC_SSE_MOV_LH>, EVEX_4V;
2793 let Predicates = [HasAVX512] in {
2795 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2796 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2797 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2798 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2801 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2802 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2805 //===----------------------------------------------------------------------===//
2806 // FMA - Fused Multiply Operations
2808 let Constraints = "$src1 = $dst" in {
2809 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2810 RegisterClass RC, X86MemOperand x86memop,
2811 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2812 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2813 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2814 (ins RC:$src1, RC:$src2, RC:$src3),
2815 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2816 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2819 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2820 (ins RC:$src1, RC:$src2, x86memop:$src3),
2821 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2822 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2823 (mem_frag addr:$src3))))]>;
2824 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2825 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2826 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2827 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2828 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2829 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2831 } // Constraints = "$src1 = $dst"
2833 let ExeDomain = SSEPackedSingle in {
2834 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2835 memopv16f32, f32mem, loadf32, "{1to16}",
2836 X86Fmadd, v16f32>, EVEX_V512,
2837 EVEX_CD8<32, CD8VF>;
2838 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2839 memopv16f32, f32mem, loadf32, "{1to16}",
2840 X86Fmsub, v16f32>, EVEX_V512,
2841 EVEX_CD8<32, CD8VF>;
2842 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2843 memopv16f32, f32mem, loadf32, "{1to16}",
2844 X86Fmaddsub, v16f32>,
2845 EVEX_V512, EVEX_CD8<32, CD8VF>;
2846 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2847 memopv16f32, f32mem, loadf32, "{1to16}",
2848 X86Fmsubadd, v16f32>,
2849 EVEX_V512, EVEX_CD8<32, CD8VF>;
2850 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2851 memopv16f32, f32mem, loadf32, "{1to16}",
2852 X86Fnmadd, v16f32>, EVEX_V512,
2853 EVEX_CD8<32, CD8VF>;
2854 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2855 memopv16f32, f32mem, loadf32, "{1to16}",
2856 X86Fnmsub, v16f32>, EVEX_V512,
2857 EVEX_CD8<32, CD8VF>;
2859 let ExeDomain = SSEPackedDouble in {
2860 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2861 memopv8f64, f64mem, loadf64, "{1to8}",
2862 X86Fmadd, v8f64>, EVEX_V512,
2863 VEX_W, EVEX_CD8<64, CD8VF>;
2864 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2865 memopv8f64, f64mem, loadf64, "{1to8}",
2866 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2867 EVEX_CD8<64, CD8VF>;
2868 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2869 memopv8f64, f64mem, loadf64, "{1to8}",
2870 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2871 EVEX_CD8<64, CD8VF>;
2872 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2873 memopv8f64, f64mem, loadf64, "{1to8}",
2874 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2875 EVEX_CD8<64, CD8VF>;
2876 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2877 memopv8f64, f64mem, loadf64, "{1to8}",
2878 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2879 EVEX_CD8<64, CD8VF>;
2880 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2881 memopv8f64, f64mem, loadf64, "{1to8}",
2882 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2883 EVEX_CD8<64, CD8VF>;
2886 let Constraints = "$src1 = $dst" in {
2887 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2888 RegisterClass RC, X86MemOperand x86memop,
2889 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2890 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2892 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2893 (ins RC:$src1, RC:$src3, x86memop:$src2),
2894 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2895 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2896 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2897 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2898 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2899 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2900 [(set RC:$dst, (OpNode RC:$src1,
2901 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2903 } // Constraints = "$src1 = $dst"
2906 let ExeDomain = SSEPackedSingle in {
2907 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2908 memopv16f32, f32mem, loadf32, "{1to16}",
2909 X86Fmadd, v16f32>, EVEX_V512,
2910 EVEX_CD8<32, CD8VF>;
2911 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2912 memopv16f32, f32mem, loadf32, "{1to16}",
2913 X86Fmsub, v16f32>, EVEX_V512,
2914 EVEX_CD8<32, CD8VF>;
2915 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2916 memopv16f32, f32mem, loadf32, "{1to16}",
2917 X86Fmaddsub, v16f32>,
2918 EVEX_V512, EVEX_CD8<32, CD8VF>;
2919 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2920 memopv16f32, f32mem, loadf32, "{1to16}",
2921 X86Fmsubadd, v16f32>,
2922 EVEX_V512, EVEX_CD8<32, CD8VF>;
2923 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2924 memopv16f32, f32mem, loadf32, "{1to16}",
2925 X86Fnmadd, v16f32>, EVEX_V512,
2926 EVEX_CD8<32, CD8VF>;
2927 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2928 memopv16f32, f32mem, loadf32, "{1to16}",
2929 X86Fnmsub, v16f32>, EVEX_V512,
2930 EVEX_CD8<32, CD8VF>;
2932 let ExeDomain = SSEPackedDouble in {
2933 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2934 memopv8f64, f64mem, loadf64, "{1to8}",
2935 X86Fmadd, v8f64>, EVEX_V512,
2936 VEX_W, EVEX_CD8<64, CD8VF>;
2937 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2938 memopv8f64, f64mem, loadf64, "{1to8}",
2939 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2940 EVEX_CD8<64, CD8VF>;
2941 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2942 memopv8f64, f64mem, loadf64, "{1to8}",
2943 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2944 EVEX_CD8<64, CD8VF>;
2945 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2946 memopv8f64, f64mem, loadf64, "{1to8}",
2947 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2948 EVEX_CD8<64, CD8VF>;
2949 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2950 memopv8f64, f64mem, loadf64, "{1to8}",
2951 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2952 EVEX_CD8<64, CD8VF>;
2953 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2954 memopv8f64, f64mem, loadf64, "{1to8}",
2955 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2956 EVEX_CD8<64, CD8VF>;
2960 let Constraints = "$src1 = $dst" in {
2961 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2962 RegisterClass RC, ValueType OpVT,
2963 X86MemOperand x86memop, Operand memop,
2965 let isCommutable = 1 in
2966 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2967 (ins RC:$src1, RC:$src2, RC:$src3),
2968 !strconcat(OpcodeStr,
2969 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2971 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2973 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2974 (ins RC:$src1, RC:$src2, f128mem:$src3),
2975 !strconcat(OpcodeStr,
2976 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2978 (OpVT (OpNode RC:$src2, RC:$src1,
2979 (mem_frag addr:$src3))))]>;
2982 } // Constraints = "$src1 = $dst"
2984 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2985 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2986 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2987 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2988 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2989 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2990 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2991 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2992 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2993 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2994 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2995 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2996 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2997 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2998 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2999 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3001 //===----------------------------------------------------------------------===//
3002 // AVX-512 Scalar convert from sign integer to float/double
3003 //===----------------------------------------------------------------------===//
3005 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3006 X86MemOperand x86memop, string asm> {
3007 let hasSideEffects = 0 in {
3008 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3009 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3012 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3013 (ins DstRC:$src1, x86memop:$src),
3014 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3016 } // hasSideEffects = 0
3018 let Predicates = [HasAVX512] in {
3019 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3020 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3021 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3022 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3023 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3024 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3025 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3026 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3028 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3029 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3030 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3031 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3032 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3033 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3034 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3035 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3037 def : Pat<(f32 (sint_to_fp GR32:$src)),
3038 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3039 def : Pat<(f32 (sint_to_fp GR64:$src)),
3040 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3041 def : Pat<(f64 (sint_to_fp GR32:$src)),
3042 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3043 def : Pat<(f64 (sint_to_fp GR64:$src)),
3044 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3046 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3047 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3048 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3049 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3050 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3051 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3052 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3053 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3055 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3056 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3057 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3058 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3059 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3060 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3061 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3062 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3064 def : Pat<(f32 (uint_to_fp GR32:$src)),
3065 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3066 def : Pat<(f32 (uint_to_fp GR64:$src)),
3067 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3068 def : Pat<(f64 (uint_to_fp GR32:$src)),
3069 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3070 def : Pat<(f64 (uint_to_fp GR64:$src)),
3071 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3074 //===----------------------------------------------------------------------===//
3075 // AVX-512 Scalar convert from float/double to integer
3076 //===----------------------------------------------------------------------===//
3077 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3078 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3080 let hasSideEffects = 0 in {
3081 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3082 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3083 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3084 Requires<[HasAVX512]>;
3086 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3087 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3088 Requires<[HasAVX512]>;
3089 } // hasSideEffects = 0
3091 let Predicates = [HasAVX512] in {
3092 // Convert float/double to signed/unsigned int 32/64
3093 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3094 ssmem, sse_load_f32, "cvtss2si">,
3095 XS, EVEX_CD8<32, CD8VT1>;
3096 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3097 ssmem, sse_load_f32, "cvtss2si">,
3098 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3099 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3100 ssmem, sse_load_f32, "cvtss2usi">,
3101 XS, EVEX_CD8<32, CD8VT1>;
3102 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3103 int_x86_avx512_cvtss2usi64, ssmem,
3104 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3105 EVEX_CD8<32, CD8VT1>;
3106 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3107 sdmem, sse_load_f64, "cvtsd2si">,
3108 XD, EVEX_CD8<64, CD8VT1>;
3109 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3110 sdmem, sse_load_f64, "cvtsd2si">,
3111 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3112 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3113 sdmem, sse_load_f64, "cvtsd2usi">,
3114 XD, EVEX_CD8<64, CD8VT1>;
3115 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3116 int_x86_avx512_cvtsd2usi64, sdmem,
3117 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3118 EVEX_CD8<64, CD8VT1>;
3120 let isCodeGenOnly = 1 in {
3121 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3122 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3123 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3124 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3125 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3126 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3127 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3128 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3129 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3130 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3131 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3132 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3134 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3135 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3136 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3137 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3138 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3139 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3140 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3141 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3142 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3143 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3144 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3145 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3146 } // isCodeGenOnly = 1
3148 // Convert float/double to signed/unsigned int 32/64 with truncation
3149 let isCodeGenOnly = 1 in {
3150 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3151 ssmem, sse_load_f32, "cvttss2si">,
3152 XS, EVEX_CD8<32, CD8VT1>;
3153 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3154 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3155 "cvttss2si">, XS, VEX_W,
3156 EVEX_CD8<32, CD8VT1>;
3157 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3158 sdmem, sse_load_f64, "cvttsd2si">, XD,
3159 EVEX_CD8<64, CD8VT1>;
3160 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3161 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3162 "cvttsd2si">, XD, VEX_W,
3163 EVEX_CD8<64, CD8VT1>;
3164 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3165 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3166 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3167 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3168 int_x86_avx512_cvttss2usi64, ssmem,
3169 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3170 EVEX_CD8<32, CD8VT1>;
3171 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3172 int_x86_avx512_cvttsd2usi,
3173 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3174 EVEX_CD8<64, CD8VT1>;
3175 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3176 int_x86_avx512_cvttsd2usi64, sdmem,
3177 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3178 EVEX_CD8<64, CD8VT1>;
3179 } // isCodeGenOnly = 1
3181 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3182 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3184 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3185 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3186 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3187 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3188 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3189 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3192 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3193 loadf32, "cvttss2si">, XS,
3194 EVEX_CD8<32, CD8VT1>;
3195 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3196 loadf32, "cvttss2usi">, XS,
3197 EVEX_CD8<32, CD8VT1>;
3198 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3199 loadf32, "cvttss2si">, XS, VEX_W,
3200 EVEX_CD8<32, CD8VT1>;
3201 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3202 loadf32, "cvttss2usi">, XS, VEX_W,
3203 EVEX_CD8<32, CD8VT1>;
3204 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3205 loadf64, "cvttsd2si">, XD,
3206 EVEX_CD8<64, CD8VT1>;
3207 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3208 loadf64, "cvttsd2usi">, XD,
3209 EVEX_CD8<64, CD8VT1>;
3210 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3211 loadf64, "cvttsd2si">, XD, VEX_W,
3212 EVEX_CD8<64, CD8VT1>;
3213 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3214 loadf64, "cvttsd2usi">, XD, VEX_W,
3215 EVEX_CD8<64, CD8VT1>;
3217 //===----------------------------------------------------------------------===//
3218 // AVX-512 Convert form float to double and back
3219 //===----------------------------------------------------------------------===//
3220 let hasSideEffects = 0 in {
3221 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3222 (ins FR32X:$src1, FR32X:$src2),
3223 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3224 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3226 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3227 (ins FR32X:$src1, f32mem:$src2),
3228 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3229 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3230 EVEX_CD8<32, CD8VT1>;
3232 // Convert scalar double to scalar single
3233 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3234 (ins FR64X:$src1, FR64X:$src2),
3235 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3236 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3238 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3239 (ins FR64X:$src1, f64mem:$src2),
3240 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3241 []>, EVEX_4V, VEX_LIG, VEX_W,
3242 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3245 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3246 Requires<[HasAVX512]>;
3247 def : Pat<(fextend (loadf32 addr:$src)),
3248 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3250 def : Pat<(extloadf32 addr:$src),
3251 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3252 Requires<[HasAVX512, OptForSize]>;
3254 def : Pat<(extloadf32 addr:$src),
3255 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3256 Requires<[HasAVX512, OptForSpeed]>;
3258 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3259 Requires<[HasAVX512]>;
3261 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3262 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3263 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3265 let hasSideEffects = 0 in {
3266 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3267 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3269 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3270 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3271 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3272 [], d>, EVEX, EVEX_B, EVEX_RC;
3274 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3275 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3277 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3278 } // hasSideEffects = 0
3281 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3282 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3283 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3285 let hasSideEffects = 0 in {
3286 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3287 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3289 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3291 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3292 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3294 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3295 } // hasSideEffects = 0
3298 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3299 memopv8f64, f512mem, v8f32, v8f64,
3300 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3301 EVEX_CD8<64, CD8VF>;
3303 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3304 memopv4f64, f256mem, v8f64, v8f32,
3305 SSEPackedDouble>, EVEX_V512, PS,
3306 EVEX_CD8<32, CD8VH>;
3307 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3308 (VCVTPS2PDZrm addr:$src)>;
3310 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3311 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3312 (VCVTPD2PSZrr VR512:$src)>;
3314 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3315 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3316 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3318 //===----------------------------------------------------------------------===//
3319 // AVX-512 Vector convert from sign integer to float/double
3320 //===----------------------------------------------------------------------===//
3322 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3323 memopv8i64, i512mem, v16f32, v16i32,
3324 SSEPackedSingle>, EVEX_V512, PS,
3325 EVEX_CD8<32, CD8VF>;
3327 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3328 memopv4i64, i256mem, v8f64, v8i32,
3329 SSEPackedDouble>, EVEX_V512, XS,
3330 EVEX_CD8<32, CD8VH>;
3332 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3333 memopv16f32, f512mem, v16i32, v16f32,
3334 SSEPackedSingle>, EVEX_V512, XS,
3335 EVEX_CD8<32, CD8VF>;
3337 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3338 memopv8f64, f512mem, v8i32, v8f64,
3339 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3340 EVEX_CD8<64, CD8VF>;
3342 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3343 memopv16f32, f512mem, v16i32, v16f32,
3344 SSEPackedSingle>, EVEX_V512, PS,
3345 EVEX_CD8<32, CD8VF>;
3347 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3348 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3349 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3350 (VCVTTPS2UDQZrr VR512:$src)>;
3352 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3353 memopv8f64, f512mem, v8i32, v8f64,
3354 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3355 EVEX_CD8<64, CD8VF>;
3357 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3358 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3359 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3360 (VCVTTPD2UDQZrr VR512:$src)>;
3362 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3363 memopv4i64, f256mem, v8f64, v8i32,
3364 SSEPackedDouble>, EVEX_V512, XS,
3365 EVEX_CD8<32, CD8VH>;
3367 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3368 memopv16i32, f512mem, v16f32, v16i32,
3369 SSEPackedSingle>, EVEX_V512, XD,
3370 EVEX_CD8<32, CD8VF>;
3372 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3373 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3374 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3376 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3377 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3378 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3380 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3381 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3382 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3384 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3385 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3386 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3388 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3389 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3390 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3392 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3393 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3394 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3395 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3396 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3397 (VCVTDQ2PDZrr VR256X:$src)>;
3398 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3399 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3400 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3401 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3402 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3403 (VCVTUDQ2PDZrr VR256X:$src)>;
3405 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3406 RegisterClass DstRC, PatFrag mem_frag,
3407 X86MemOperand x86memop, Domain d> {
3408 let hasSideEffects = 0 in {
3409 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3410 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3412 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3413 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3414 [], d>, EVEX, EVEX_B, EVEX_RC;
3416 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3417 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3419 } // hasSideEffects = 0
3422 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3423 memopv16f32, f512mem, SSEPackedSingle>, PD,
3424 EVEX_V512, EVEX_CD8<32, CD8VF>;
3425 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3426 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3427 EVEX_V512, EVEX_CD8<64, CD8VF>;
3429 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3430 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3431 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3433 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3434 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3435 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3437 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3438 memopv16f32, f512mem, SSEPackedSingle>,
3439 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3440 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3441 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3442 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3444 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3445 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3446 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3448 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3449 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3450 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3452 let Predicates = [HasAVX512] in {
3453 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3454 (VCVTPD2PSZrm addr:$src)>;
3455 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3456 (VCVTPS2PDZrm addr:$src)>;
3459 //===----------------------------------------------------------------------===//
3460 // Half precision conversion instructions
3461 //===----------------------------------------------------------------------===//
3462 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3463 X86MemOperand x86memop> {
3464 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3465 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3467 let hasSideEffects = 0, mayLoad = 1 in
3468 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3469 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3472 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3473 X86MemOperand x86memop> {
3474 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3475 (ins srcRC:$src1, i32i8imm:$src2),
3476 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3478 let hasSideEffects = 0, mayStore = 1 in
3479 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3480 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3481 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3484 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3485 EVEX_CD8<32, CD8VH>;
3486 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3487 EVEX_CD8<32, CD8VH>;
3489 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3490 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3491 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3493 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3494 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3495 (VCVTPH2PSZrr VR256X:$src)>;
3497 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3498 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3499 "ucomiss">, PS, EVEX, VEX_LIG,
3500 EVEX_CD8<32, CD8VT1>;
3501 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3502 "ucomisd">, PD, EVEX,
3503 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3504 let Pattern = []<dag> in {
3505 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3506 "comiss">, PS, EVEX, VEX_LIG,
3507 EVEX_CD8<32, CD8VT1>;
3508 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3509 "comisd">, PD, EVEX,
3510 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3512 let isCodeGenOnly = 1 in {
3513 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3514 load, "ucomiss">, PS, EVEX, VEX_LIG,
3515 EVEX_CD8<32, CD8VT1>;
3516 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3517 load, "ucomisd">, PD, EVEX,
3518 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3520 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3521 load, "comiss">, PS, EVEX, VEX_LIG,
3522 EVEX_CD8<32, CD8VT1>;
3523 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3524 load, "comisd">, PD, EVEX,
3525 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3529 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3530 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3531 X86MemOperand x86memop> {
3532 let hasSideEffects = 0 in {
3533 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3534 (ins RC:$src1, RC:$src2),
3535 !strconcat(OpcodeStr,
3536 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3537 let mayLoad = 1 in {
3538 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3539 (ins RC:$src1, x86memop:$src2),
3540 !strconcat(OpcodeStr,
3541 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3546 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3547 EVEX_CD8<32, CD8VT1>;
3548 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3549 VEX_W, EVEX_CD8<64, CD8VT1>;
3550 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3551 EVEX_CD8<32, CD8VT1>;
3552 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3553 VEX_W, EVEX_CD8<64, CD8VT1>;
3555 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3556 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3557 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3558 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3560 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3561 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3562 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3563 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3565 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3566 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3567 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3568 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3570 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3571 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3572 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3573 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3575 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3576 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3577 RegisterClass RC, X86MemOperand x86memop,
3578 PatFrag mem_frag, ValueType OpVt> {
3579 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3580 !strconcat(OpcodeStr,
3581 " \t{$src, $dst|$dst, $src}"),
3582 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3584 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3585 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3586 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3589 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3590 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3591 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3592 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3593 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3594 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3595 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3596 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3598 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3599 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3600 (VRSQRT14PSZr VR512:$src)>;
3601 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3602 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3603 (VRSQRT14PDZr VR512:$src)>;
3605 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3606 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3607 (VRCP14PSZr VR512:$src)>;
3608 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3609 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3610 (VRCP14PDZr VR512:$src)>;
3612 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3613 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3614 X86MemOperand x86memop> {
3615 let hasSideEffects = 0, Predicates = [HasERI] in {
3616 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3617 (ins RC:$src1, RC:$src2),
3618 !strconcat(OpcodeStr,
3619 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3620 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3621 (ins RC:$src1, RC:$src2),
3622 !strconcat(OpcodeStr,
3623 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3624 []>, EVEX_4V, EVEX_B;
3625 let mayLoad = 1 in {
3626 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3627 (ins RC:$src1, x86memop:$src2),
3628 !strconcat(OpcodeStr,
3629 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3634 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3635 EVEX_CD8<32, CD8VT1>;
3636 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3637 VEX_W, EVEX_CD8<64, CD8VT1>;
3638 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3639 EVEX_CD8<32, CD8VT1>;
3640 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3641 VEX_W, EVEX_CD8<64, CD8VT1>;
3643 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3644 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3646 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3647 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3649 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3650 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3652 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3653 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3655 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3656 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3658 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3659 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3661 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3662 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3664 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3665 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3667 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3668 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3669 RegisterClass RC, X86MemOperand x86memop> {
3670 let hasSideEffects = 0, Predicates = [HasERI] in {
3671 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3672 !strconcat(OpcodeStr,
3673 " \t{$src, $dst|$dst, $src}"),
3675 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3676 !strconcat(OpcodeStr,
3677 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3679 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3680 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3684 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3685 EVEX_V512, EVEX_CD8<32, CD8VF>;
3686 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3687 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3688 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3689 EVEX_V512, EVEX_CD8<32, CD8VF>;
3690 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3691 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3693 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3694 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3695 (VRSQRT28PSZrb VR512:$src)>;
3696 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3697 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3698 (VRSQRT28PDZrb VR512:$src)>;
3700 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3701 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3702 (VRCP28PSZrb VR512:$src)>;
3703 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3704 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3705 (VRCP28PDZrb VR512:$src)>;
3707 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3708 OpndItins itins_s, OpndItins itins_d> {
3709 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3710 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3711 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3715 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3716 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3718 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3719 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3721 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3722 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3723 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3727 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3728 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3729 [(set VR512:$dst, (OpNode
3730 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3731 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3735 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3736 Intrinsic F32Int, Intrinsic F64Int,
3737 OpndItins itins_s, OpndItins itins_d> {
3738 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3739 (ins FR32X:$src1, FR32X:$src2),
3740 !strconcat(OpcodeStr,
3741 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3742 [], itins_s.rr>, XS, EVEX_4V;
3743 let isCodeGenOnly = 1 in
3744 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3745 (ins VR128X:$src1, VR128X:$src2),
3746 !strconcat(OpcodeStr,
3747 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3749 (F32Int VR128X:$src1, VR128X:$src2))],
3750 itins_s.rr>, XS, EVEX_4V;
3751 let mayLoad = 1 in {
3752 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3753 (ins FR32X:$src1, f32mem:$src2),
3754 !strconcat(OpcodeStr,
3755 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3756 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3757 let isCodeGenOnly = 1 in
3758 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3759 (ins VR128X:$src1, ssmem:$src2),
3760 !strconcat(OpcodeStr,
3761 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3763 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3764 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3766 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3767 (ins FR64X:$src1, FR64X:$src2),
3768 !strconcat(OpcodeStr,
3769 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3771 let isCodeGenOnly = 1 in
3772 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3773 (ins VR128X:$src1, VR128X:$src2),
3774 !strconcat(OpcodeStr,
3775 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3777 (F64Int VR128X:$src1, VR128X:$src2))],
3778 itins_s.rr>, XD, EVEX_4V, VEX_W;
3779 let mayLoad = 1 in {
3780 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3781 (ins FR64X:$src1, f64mem:$src2),
3782 !strconcat(OpcodeStr,
3783 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3784 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3785 let isCodeGenOnly = 1 in
3786 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3787 (ins VR128X:$src1, sdmem:$src2),
3788 !strconcat(OpcodeStr,
3789 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3791 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3792 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3797 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3798 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3799 SSE_SQRTSS, SSE_SQRTSD>,
3800 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3801 SSE_SQRTPS, SSE_SQRTPD>;
3803 let Predicates = [HasAVX512] in {
3804 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
3805 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
3806 (VSQRTPSZrr VR512:$src1)>;
3807 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
3808 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
3809 (VSQRTPDZrr VR512:$src1)>;
3811 def : Pat<(f32 (fsqrt FR32X:$src)),
3812 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3813 def : Pat<(f32 (fsqrt (load addr:$src))),
3814 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3815 Requires<[OptForSize]>;
3816 def : Pat<(f64 (fsqrt FR64X:$src)),
3817 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3818 def : Pat<(f64 (fsqrt (load addr:$src))),
3819 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3820 Requires<[OptForSize]>;
3822 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3823 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3824 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3825 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3826 Requires<[OptForSize]>;
3828 def : Pat<(f32 (X86frcp FR32X:$src)),
3829 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3830 def : Pat<(f32 (X86frcp (load addr:$src))),
3831 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3832 Requires<[OptForSize]>;
3834 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3835 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3836 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3838 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3839 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3841 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3842 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3843 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3845 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3846 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3850 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3851 X86MemOperand x86memop, RegisterClass RC,
3852 PatFrag mem_frag32, PatFrag mem_frag64,
3853 Intrinsic V4F32Int, Intrinsic V2F64Int,
3855 let ExeDomain = SSEPackedSingle in {
3856 // Intrinsic operation, reg.
3857 // Vector intrinsic operation, reg
3858 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3859 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3860 !strconcat(OpcodeStr,
3861 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3862 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3864 // Vector intrinsic operation, mem
3865 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3866 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3867 !strconcat(OpcodeStr,
3868 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3870 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3871 EVEX_CD8<32, VForm>;
3872 } // ExeDomain = SSEPackedSingle
3874 let ExeDomain = SSEPackedDouble in {
3875 // Vector intrinsic operation, reg
3876 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3877 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3878 !strconcat(OpcodeStr,
3879 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3880 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3882 // Vector intrinsic operation, mem
3883 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3884 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3885 !strconcat(OpcodeStr,
3886 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3888 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3889 EVEX_CD8<64, VForm>;
3890 } // ExeDomain = SSEPackedDouble
3893 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3897 let ExeDomain = GenericDomain in {
3899 let hasSideEffects = 0 in
3900 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3901 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3902 !strconcat(OpcodeStr,
3903 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3906 // Intrinsic operation, reg.
3907 let isCodeGenOnly = 1 in
3908 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3909 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3910 !strconcat(OpcodeStr,
3911 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3912 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3914 // Intrinsic operation, mem.
3915 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3916 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3917 !strconcat(OpcodeStr,
3918 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3919 [(set VR128X:$dst, (F32Int VR128X:$src1,
3920 sse_load_f32:$src2, imm:$src3))]>,
3921 EVEX_CD8<32, CD8VT1>;
3924 let hasSideEffects = 0 in
3925 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3926 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3927 !strconcat(OpcodeStr,
3928 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3931 // Intrinsic operation, reg.
3932 let isCodeGenOnly = 1 in
3933 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3934 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3935 !strconcat(OpcodeStr,
3936 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3937 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3940 // Intrinsic operation, mem.
3941 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3942 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3943 !strconcat(OpcodeStr,
3944 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3946 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3947 VEX_W, EVEX_CD8<64, CD8VT1>;
3948 } // ExeDomain = GenericDomain
3951 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3952 X86MemOperand x86memop, RegisterClass RC,
3953 PatFrag mem_frag, Domain d> {
3954 let ExeDomain = d in {
3955 // Intrinsic operation, reg.
3956 // Vector intrinsic operation, reg
3957 def r : AVX512AIi8<opc, MRMSrcReg,
3958 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3959 !strconcat(OpcodeStr,
3960 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3963 // Vector intrinsic operation, mem
3964 def m : AVX512AIi8<opc, MRMSrcMem,
3965 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3966 !strconcat(OpcodeStr,
3967 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3973 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3974 memopv16f32, SSEPackedSingle>, EVEX_V512,
3975 EVEX_CD8<32, CD8VF>;
3977 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3978 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3980 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3983 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3984 memopv8f64, SSEPackedDouble>, EVEX_V512,
3985 VEX_W, EVEX_CD8<64, CD8VF>;
3987 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3988 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3990 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3992 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3993 Operand x86memop, RegisterClass RC, Domain d> {
3994 let ExeDomain = d in {
3995 def r : AVX512AIi8<opc, MRMSrcReg,
3996 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3997 !strconcat(OpcodeStr,
3998 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4001 def m : AVX512AIi8<opc, MRMSrcMem,
4002 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4003 !strconcat(OpcodeStr,
4004 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4009 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4010 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4012 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4013 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4015 def : Pat<(ffloor FR32X:$src),
4016 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4017 def : Pat<(f64 (ffloor FR64X:$src)),
4018 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4019 def : Pat<(f32 (fnearbyint FR32X:$src)),
4020 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4021 def : Pat<(f64 (fnearbyint FR64X:$src)),
4022 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4023 def : Pat<(f32 (fceil FR32X:$src)),
4024 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4025 def : Pat<(f64 (fceil FR64X:$src)),
4026 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4027 def : Pat<(f32 (frint FR32X:$src)),
4028 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4029 def : Pat<(f64 (frint FR64X:$src)),
4030 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4031 def : Pat<(f32 (ftrunc FR32X:$src)),
4032 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4033 def : Pat<(f64 (ftrunc FR64X:$src)),
4034 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4036 def : Pat<(v16f32 (ffloor VR512:$src)),
4037 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4038 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4039 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4040 def : Pat<(v16f32 (fceil VR512:$src)),
4041 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4042 def : Pat<(v16f32 (frint VR512:$src)),
4043 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4044 def : Pat<(v16f32 (ftrunc VR512:$src)),
4045 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4047 def : Pat<(v8f64 (ffloor VR512:$src)),
4048 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4049 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4050 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4051 def : Pat<(v8f64 (fceil VR512:$src)),
4052 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4053 def : Pat<(v8f64 (frint VR512:$src)),
4054 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4055 def : Pat<(v8f64 (ftrunc VR512:$src)),
4056 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4058 //-------------------------------------------------
4059 // Integer truncate and extend operations
4060 //-------------------------------------------------
4062 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4063 RegisterClass dstRC, RegisterClass srcRC,
4064 RegisterClass KRC, X86MemOperand x86memop> {
4065 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4067 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4070 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4071 (ins KRC:$mask, srcRC:$src),
4072 !strconcat(OpcodeStr,
4073 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4076 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4077 (ins KRC:$mask, srcRC:$src),
4078 !strconcat(OpcodeStr,
4079 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4082 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4083 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4086 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4087 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4088 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4092 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4093 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4094 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4095 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4096 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4097 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4098 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4099 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4100 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4101 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4102 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4103 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4104 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4105 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4106 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4107 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4108 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4109 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4110 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4111 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4112 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4113 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4114 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4115 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4116 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4117 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4118 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4119 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4120 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4121 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4123 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4124 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4125 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4126 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4127 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4129 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4130 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4131 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4132 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4133 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4134 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4135 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4136 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4139 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4140 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4141 PatFrag mem_frag, X86MemOperand x86memop,
4142 ValueType OpVT, ValueType InVT> {
4144 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4146 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4147 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4149 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4150 (ins KRC:$mask, SrcRC:$src),
4151 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4154 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4155 (ins KRC:$mask, SrcRC:$src),
4156 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4159 let mayLoad = 1 in {
4160 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4161 (ins x86memop:$src),
4162 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4164 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4167 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4168 (ins KRC:$mask, x86memop:$src),
4169 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4173 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4174 (ins KRC:$mask, x86memop:$src),
4175 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4181 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4182 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4184 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4185 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4187 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4188 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4189 EVEX_CD8<16, CD8VH>;
4190 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4191 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4192 EVEX_CD8<16, CD8VQ>;
4193 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4194 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4195 EVEX_CD8<32, CD8VH>;
4197 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4198 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4200 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4201 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4203 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4204 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4205 EVEX_CD8<16, CD8VH>;
4206 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4207 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4208 EVEX_CD8<16, CD8VQ>;
4209 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4210 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4211 EVEX_CD8<32, CD8VH>;
4213 //===----------------------------------------------------------------------===//
4214 // GATHER - SCATTER Operations
4216 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4217 RegisterClass RC, X86MemOperand memop> {
4219 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4220 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4221 (ins RC:$src1, KRC:$mask, memop:$src2),
4222 !strconcat(OpcodeStr,
4223 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4227 let ExeDomain = SSEPackedDouble in {
4228 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4229 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4230 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4231 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4234 let ExeDomain = SSEPackedSingle in {
4235 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4236 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4237 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4238 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4241 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4242 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4243 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4244 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4246 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4247 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4248 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4249 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4251 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4252 RegisterClass RC, X86MemOperand memop> {
4253 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4254 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4255 (ins memop:$dst, KRC:$mask, RC:$src2),
4256 !strconcat(OpcodeStr,
4257 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4261 let ExeDomain = SSEPackedDouble in {
4262 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4263 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4264 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4265 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4268 let ExeDomain = SSEPackedSingle in {
4269 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4270 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4271 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4272 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4275 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4276 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4277 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4278 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4280 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4281 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4282 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4283 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4286 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4287 RegisterClass KRC, X86MemOperand memop> {
4288 let Predicates = [HasPFI], hasSideEffects = 1 in
4289 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4290 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4294 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4295 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4297 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4298 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4300 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4301 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4303 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4304 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4306 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4307 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4309 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4310 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4312 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4313 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4315 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4316 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4318 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4319 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4321 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4322 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4324 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4325 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4327 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4328 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4330 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4331 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4333 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4334 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4336 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4337 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4339 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4340 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4341 //===----------------------------------------------------------------------===//
4342 // VSHUFPS - VSHUFPD Operations
4344 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4345 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4347 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4348 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4349 !strconcat(OpcodeStr,
4350 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4351 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4352 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4353 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4354 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4355 (ins RC:$src1, RC:$src2, i8imm:$src3),
4356 !strconcat(OpcodeStr,
4357 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4358 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4359 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4360 EVEX_4V, Sched<[WriteShuffle]>;
4363 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4364 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4365 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4366 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4368 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4369 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4370 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4371 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4372 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4374 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4375 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4376 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4377 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4378 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4380 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4381 X86MemOperand x86memop> {
4382 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4383 (ins RC:$src1, RC:$src2, i8imm:$src3),
4384 !strconcat(OpcodeStr,
4385 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4388 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4389 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4390 !strconcat(OpcodeStr,
4391 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4394 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4395 EVEX_V512, EVEX_CD8<32, CD8VF>;
4396 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4397 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4399 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4400 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4401 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4402 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4403 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4404 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4405 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4406 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4408 // Helper fragments to match sext vXi1 to vXiY.
4409 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4410 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4412 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4413 RegisterClass KRC, RegisterClass RC,
4414 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4416 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4417 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4419 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4420 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4422 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4423 !strconcat(OpcodeStr,
4424 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4426 let mayLoad = 1 in {
4427 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4428 (ins x86memop:$src),
4429 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4431 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4432 (ins KRC:$mask, x86memop:$src),
4433 !strconcat(OpcodeStr,
4434 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4436 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4437 (ins KRC:$mask, x86memop:$src),
4438 !strconcat(OpcodeStr,
4439 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4441 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4442 (ins x86scalar_mop:$src),
4443 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4444 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4446 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4447 (ins KRC:$mask, x86scalar_mop:$src),
4448 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4449 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4450 []>, EVEX, EVEX_B, EVEX_K;
4451 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4452 (ins KRC:$mask, x86scalar_mop:$src),
4453 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4454 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4456 []>, EVEX, EVEX_B, EVEX_KZ;
4460 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4461 i512mem, i32mem, "{1to16}">, EVEX_V512,
4462 EVEX_CD8<32, CD8VF>;
4463 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4464 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4465 EVEX_CD8<64, CD8VF>;
4468 (bc_v16i32 (v16i1sextv16i32)),
4469 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4470 (VPABSDZrr VR512:$src)>;
4472 (bc_v8i64 (v8i1sextv8i64)),
4473 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4474 (VPABSQZrr VR512:$src)>;
4476 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4477 (v16i32 immAllZerosV), (i16 -1))),
4478 (VPABSDZrr VR512:$src)>;
4479 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4480 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4481 (VPABSQZrr VR512:$src)>;
4483 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4484 RegisterClass RC, RegisterClass KRC,
4485 X86MemOperand x86memop,
4486 X86MemOperand x86scalar_mop, string BrdcstStr> {
4487 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4489 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4491 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4492 (ins x86memop:$src),
4493 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4495 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4496 (ins x86scalar_mop:$src),
4497 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4498 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4500 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4501 (ins KRC:$mask, RC:$src),
4502 !strconcat(OpcodeStr,
4503 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4505 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4506 (ins KRC:$mask, x86memop:$src),
4507 !strconcat(OpcodeStr,
4508 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4510 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4511 (ins KRC:$mask, x86scalar_mop:$src),
4512 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4513 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4515 []>, EVEX, EVEX_KZ, EVEX_B;
4517 let Constraints = "$src1 = $dst" in {
4518 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4519 (ins RC:$src1, KRC:$mask, RC:$src2),
4520 !strconcat(OpcodeStr,
4521 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4523 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4524 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4525 !strconcat(OpcodeStr,
4526 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4528 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4529 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4530 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4531 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4532 []>, EVEX, EVEX_K, EVEX_B;
4536 let Predicates = [HasCDI] in {
4537 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4538 i512mem, i32mem, "{1to16}">,
4539 EVEX_V512, EVEX_CD8<32, CD8VF>;
4542 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4543 i512mem, i64mem, "{1to8}">,
4544 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4548 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4550 (VPCONFLICTDrrk VR512:$src1,
4551 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4553 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4555 (VPCONFLICTQrrk VR512:$src1,
4556 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4558 let Predicates = [HasCDI] in {
4559 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4560 i512mem, i32mem, "{1to16}">,
4561 EVEX_V512, EVEX_CD8<32, CD8VF>;
4564 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4565 i512mem, i64mem, "{1to8}">,
4566 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4570 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4572 (VPLZCNTDrrk VR512:$src1,
4573 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4575 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4577 (VPLZCNTQrrk VR512:$src1,
4578 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4580 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4581 (VPLZCNTDrm addr:$src)>;
4582 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4583 (VPLZCNTDrr VR512:$src)>;
4584 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4585 (VPLZCNTQrm addr:$src)>;
4586 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4587 (VPLZCNTQrr VR512:$src)>;
4589 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4590 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4591 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4593 def : Pat<(store VK1:$src, addr:$dst),
4594 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4596 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4597 (truncstore node:$val, node:$ptr), [{
4598 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4601 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4602 (MOV8mr addr:$dst, GR8:$src)>;