1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
25 string VTName = "v" # NumElts # EltVT;
28 ValueType VT = !cast<ValueType>(VTName);
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
35 // "i" for integer types and "f" for floating-point types
36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
38 // Size of RC in bits, e.g. 512 for VR512.
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
63 // The corresponding float type, e.g. v16f32 for v16i32
64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
83 // A vector type of the same width with element type i32. This is used to
84 // create the canonical constant zero node ImmAllZerosV.
85 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
86 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
89 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
90 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
91 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
92 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
93 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
94 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
96 // "x" in v32i8x_info means RC = VR256X
97 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
98 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
99 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
100 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
102 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
103 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
104 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
105 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
107 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
108 X86VectorVTInfo i128> {
109 X86VectorVTInfo info512 = i512;
110 X86VectorVTInfo info256 = i256;
111 X86VectorVTInfo info128 = i128;
114 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
116 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
118 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
120 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
123 // This multiclass generates the masking variants from the non-masking
124 // variant. It only provides the assembly pieces for the masking variants.
125 // It assumes custom ISel patterns for masking which can be provided as
126 // template arguments.
127 multiclass AVX512_masking_custom<bits<8> O, Format F,
129 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
131 string AttSrcAsm, string IntelSrcAsm,
133 list<dag> MaskingPattern,
134 list<dag> ZeroMaskingPattern,
135 string MaskingConstraint = "",
136 InstrItinClass itin = NoItinerary,
137 bit IsCommutable = 0> {
138 let isCommutable = IsCommutable in
139 def NAME: AVX512<O, F, Outs, Ins,
140 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
141 "$dst, "#IntelSrcAsm#"}",
144 // Prefer over VMOV*rrk Pat<>
145 let AddedComplexity = 20 in
146 def NAME#k: AVX512<O, F, Outs, MaskingIns,
147 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
148 "$dst {${mask}}, "#IntelSrcAsm#"}",
149 MaskingPattern, itin>,
151 // In case of the 3src subclass this is overridden with a let.
152 string Constraints = MaskingConstraint;
154 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
155 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
156 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
157 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
164 // Common base class of AVX512_masking and AVX512_masking_3src.
165 multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
167 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
169 string AttSrcAsm, string IntelSrcAsm,
170 dag RHS, dag MaskingRHS,
171 string MaskingConstraint = "",
172 InstrItinClass itin = NoItinerary,
173 bit IsCommutable = 0> :
174 AVX512_masking_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
175 AttSrcAsm, IntelSrcAsm,
176 [(set _.RC:$dst, RHS)],
177 [(set _.RC:$dst, MaskingRHS)],
179 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
180 MaskingConstraint, NoItinerary, IsCommutable>;
182 // This multiclass generates the unconditional/non-masking, the masking and
183 // the zero-masking variant of the instruction. In the masking case, the
184 // perserved vector elements come from a new dummy input operand tied to $dst.
185 multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
186 dag Outs, dag Ins, string OpcodeStr,
187 string AttSrcAsm, string IntelSrcAsm,
188 dag RHS, InstrItinClass itin = NoItinerary,
189 bit IsCommutable = 0> :
190 AVX512_masking_common<O, F, _, Outs, Ins,
191 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
192 !con((ins _.KRCWM:$mask), Ins),
193 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
194 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
195 "$src0 = $dst", itin, IsCommutable>;
197 // Similar to AVX512_masking but in this case one of the source operands
198 // ($src1) is already tied to $dst so we just use that for the preserved
199 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
201 multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Outs, dag NonTiedIns, string OpcodeStr,
203 string AttSrcAsm, string IntelSrcAsm,
205 AVX512_masking_common<O, F, _, Outs,
206 !con((ins _.RC:$src1), NonTiedIns),
207 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
208 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
209 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
210 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
212 // Bitcasts between 512-bit vector types. Return the original type since
213 // no instruction is needed for the conversion
214 let Predicates = [HasAVX512] in {
215 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
216 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
217 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
218 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
219 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
220 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
221 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
222 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
223 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
224 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
225 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
226 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
227 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
228 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
229 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
230 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
231 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
232 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
233 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
234 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
235 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
236 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
237 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
238 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
239 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
240 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
241 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
242 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
243 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
244 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
245 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
247 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
248 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
249 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
250 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
251 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
252 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
253 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
254 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
255 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
256 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
257 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
258 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
259 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
260 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
261 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
262 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
263 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
264 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
265 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
266 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
267 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
268 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
269 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
270 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
271 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
272 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
273 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
274 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
275 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
276 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
278 // Bitcasts between 256-bit vector types. Return the original type since
279 // no instruction is needed for the conversion
280 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
281 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
282 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
283 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
284 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
285 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
286 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
287 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
288 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
289 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
290 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
291 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
292 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
293 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
294 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
295 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
296 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
297 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
298 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
299 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
300 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
301 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
302 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
303 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
304 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
305 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
306 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
307 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
308 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
309 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
313 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
316 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
317 isPseudo = 1, Predicates = [HasAVX512] in {
318 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
319 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
322 let Predicates = [HasAVX512] in {
323 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
324 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
325 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
328 //===----------------------------------------------------------------------===//
329 // AVX-512 - VECTOR INSERT
332 multiclass vinsert_for_size<int Opcode,
333 X86VectorVTInfo From, X86VectorVTInfo To,
334 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
335 PatFrag vinsert_insert,
336 SDNodeXForm INSERT_get_vinsert_imm> {
337 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
338 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
339 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
340 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
341 "$dst, $src1, $src2, $src3}",
342 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
343 (From.VT From.RC:$src2),
348 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
349 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
350 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
351 "$dst, $src1, $src2, $src3}",
352 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
355 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
357 def : Pat<(vinsert_insert:$ins
358 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
359 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
360 VR512:$src1, From.RC:$src2,
361 (INSERT_get_vinsert_imm VR512:$ins)))>;
364 multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
365 ValueType EltVT64, int Opcode64> {
366 defm NAME # "32x4" : vinsert_for_size<Opcode32,
367 X86VectorVTInfo< 4, EltVT32, VR128X>,
368 X86VectorVTInfo<16, EltVT32, VR512>,
369 X86VectorVTInfo< 2, EltVT64, VR128X>,
370 X86VectorVTInfo< 8, EltVT64, VR512>,
372 INSERT_get_vinsert128_imm>;
373 defm NAME # "64x4" : vinsert_for_size<Opcode64,
374 X86VectorVTInfo< 4, EltVT64, VR256X>,
375 X86VectorVTInfo< 8, EltVT64, VR512>,
376 X86VectorVTInfo< 8, EltVT32, VR256>,
377 X86VectorVTInfo<16, EltVT32, VR512>,
379 INSERT_get_vinsert256_imm>, VEX_W;
382 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
383 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
385 // vinsertps - insert f32 to XMM
386 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
387 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
388 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
389 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
391 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
392 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
393 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
394 [(set VR128X:$dst, (X86insertps VR128X:$src1,
395 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
396 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
398 //===----------------------------------------------------------------------===//
399 // AVX-512 VECTOR EXTRACT
402 multiclass vextract_for_size<int Opcode,
403 X86VectorVTInfo From, X86VectorVTInfo To,
404 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
405 PatFrag vextract_extract,
406 SDNodeXForm EXTRACT_get_vextract_imm> {
407 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
408 def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
409 (ins VR512:$src1, i8imm:$idx),
410 "vextract" # To.EltTypeName # "x4\t{$idx, $src1, $dst|"
411 "$dst, $src1, $idx}",
412 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
416 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
417 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
418 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
419 "$dst, $src1, $src2}",
420 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
423 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
425 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
426 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
428 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
430 // A 128/256-bit subvector extract from the first 512-bit vector position is
431 // a subregister copy that needs no instruction.
432 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
434 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
436 // And for the alternative types.
437 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
439 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
442 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
443 ValueType EltVT64, int Opcode64> {
444 defm NAME # "32x4" : vextract_for_size<Opcode32,
445 X86VectorVTInfo<16, EltVT32, VR512>,
446 X86VectorVTInfo< 4, EltVT32, VR128X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
448 X86VectorVTInfo< 2, EltVT64, VR128X>,
450 EXTRACT_get_vextract128_imm>;
451 defm NAME # "64x4" : vextract_for_size<Opcode64,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
453 X86VectorVTInfo< 4, EltVT64, VR256X>,
454 X86VectorVTInfo<16, EltVT32, VR512>,
455 X86VectorVTInfo< 8, EltVT32, VR256>,
457 EXTRACT_get_vextract256_imm>, VEX_W;
460 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
461 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
463 // A 128-bit subvector insert to the first 512-bit vector position
464 // is a subregister copy that needs no instruction.
465 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
466 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
467 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
469 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
470 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
471 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
473 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
474 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
475 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
477 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
478 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
479 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
482 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
483 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
484 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
485 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
486 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
487 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
488 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
489 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
491 // vextractps - extract 32 bits from XMM
492 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
493 (ins VR128X:$src1, i32i8imm:$src2),
494 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
495 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
498 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
499 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
500 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
501 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
502 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
504 //===---------------------------------------------------------------------===//
507 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
508 RegisterClass DestRC,
509 RegisterClass SrcRC, X86MemOperand x86memop> {
510 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
511 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
513 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
514 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
516 let ExeDomain = SSEPackedSingle in {
517 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
519 EVEX_V512, EVEX_CD8<32, CD8VT1>;
522 let ExeDomain = SSEPackedDouble in {
523 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
525 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
528 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
529 (VBROADCASTSSZrm addr:$src)>;
530 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
531 (VBROADCASTSDZrm addr:$src)>;
533 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
534 (VBROADCASTSSZrm addr:$src)>;
535 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
536 (VBROADCASTSDZrm addr:$src)>;
538 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
539 RegisterClass SrcRC, RegisterClass KRC> {
540 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
541 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
542 []>, EVEX, EVEX_V512;
543 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
544 (ins KRC:$mask, SrcRC:$src),
545 !strconcat(OpcodeStr,
546 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
547 []>, EVEX, EVEX_V512, EVEX_KZ;
550 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
551 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
554 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
555 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
557 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
558 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
560 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
561 (VPBROADCASTDrZrr GR32:$src)>;
562 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
563 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
564 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
565 (VPBROADCASTQrZrr GR64:$src)>;
566 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
567 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
569 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
570 (VPBROADCASTDrZrr GR32:$src)>;
571 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
572 (VPBROADCASTQrZrr GR64:$src)>;
574 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
575 (v16i32 immAllZerosV), (i16 GR16:$mask))),
576 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
577 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
578 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
579 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
581 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
582 X86MemOperand x86memop, PatFrag ld_frag,
583 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
585 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
586 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
588 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
589 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
591 !strconcat(OpcodeStr,
592 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
594 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
597 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
600 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
601 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
603 !strconcat(OpcodeStr,
604 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
605 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
606 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
610 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
611 loadi32, VR512, v16i32, v4i32, VK16WM>,
612 EVEX_V512, EVEX_CD8<32, CD8VT1>;
613 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
614 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
615 EVEX_CD8<64, CD8VT1>;
617 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
618 X86MemOperand x86memop, PatFrag ld_frag,
621 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
622 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
624 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
626 !strconcat(OpcodeStr,
627 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
632 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
633 i128mem, loadv2i64, VK16WM>,
634 EVEX_V512, EVEX_CD8<32, CD8VT4>;
635 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
636 i256mem, loadv4i64, VK16WM>, VEX_W,
637 EVEX_V512, EVEX_CD8<64, CD8VT4>;
639 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
640 (VPBROADCASTDZrr VR128X:$src)>;
641 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
642 (VPBROADCASTQZrr VR128X:$src)>;
644 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
645 (VBROADCASTSSZrr VR128X:$src)>;
646 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
647 (VBROADCASTSDZrr VR128X:$src)>;
649 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
650 (VBROADCASTSSZrr VR128X:$src)>;
651 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
652 (VBROADCASTSDZrr VR128X:$src)>;
654 // Provide fallback in case the load node that is used in the patterns above
655 // is used by additional users, which prevents the pattern selection.
656 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
657 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
658 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
659 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
662 let Predicates = [HasAVX512] in {
663 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
665 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
666 addr:$src)), sub_ymm)>;
668 //===----------------------------------------------------------------------===//
669 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
672 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
673 RegisterClass DstRC, RegisterClass KRC,
674 ValueType OpVT, ValueType SrcVT> {
675 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
676 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
680 let Predicates = [HasCDI] in {
681 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
682 VK16, v16i32, v16i1>, EVEX_V512;
683 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
684 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
687 //===----------------------------------------------------------------------===//
690 // -- immediate form --
691 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
692 SDNode OpNode, PatFrag mem_frag,
693 X86MemOperand x86memop, ValueType OpVT> {
694 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
695 (ins RC:$src1, i8imm:$src2),
696 !strconcat(OpcodeStr,
697 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
699 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
701 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
702 (ins x86memop:$src1, i8imm:$src2),
703 !strconcat(OpcodeStr,
704 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
706 (OpVT (OpNode (mem_frag addr:$src1),
707 (i8 imm:$src2))))]>, EVEX;
710 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
711 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
712 let ExeDomain = SSEPackedDouble in
713 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
714 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
716 // -- VPERM - register form --
717 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
718 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
720 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
721 (ins RC:$src1, RC:$src2),
722 !strconcat(OpcodeStr,
723 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
725 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
727 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
728 (ins RC:$src1, x86memop:$src2),
729 !strconcat(OpcodeStr,
730 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
732 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
736 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
737 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
738 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
739 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
740 let ExeDomain = SSEPackedSingle in
741 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
742 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
743 let ExeDomain = SSEPackedDouble in
744 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
745 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
747 // -- VPERM2I - 3 source operands form --
748 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
749 PatFrag mem_frag, X86MemOperand x86memop,
750 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
751 let Constraints = "$src1 = $dst" in {
752 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
753 (ins RC:$src1, RC:$src2, RC:$src3),
754 !strconcat(OpcodeStr,
755 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
757 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
760 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
761 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
762 !strconcat(OpcodeStr,
763 " \t{$src3, $src2, $dst {${mask}}|"
764 "$dst {${mask}}, $src2, $src3}"),
765 [(set RC:$dst, (OpVT (vselect KRC:$mask,
766 (OpNode RC:$src1, RC:$src2,
771 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
772 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
773 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
774 !strconcat(OpcodeStr,
775 " \t{$src3, $src2, $dst {${mask}} {z} |",
776 "$dst {${mask}} {z}, $src2, $src3}"),
777 [(set RC:$dst, (OpVT (vselect KRC:$mask,
778 (OpNode RC:$src1, RC:$src2,
781 (v16i32 immAllZerosV))))))]>,
784 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
785 (ins RC:$src1, RC:$src2, x86memop:$src3),
786 !strconcat(OpcodeStr,
787 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
789 (OpVT (OpNode RC:$src1, RC:$src2,
790 (mem_frag addr:$src3))))]>, EVEX_4V;
792 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
793 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
794 !strconcat(OpcodeStr,
795 " \t{$src3, $src2, $dst {${mask}}|"
796 "$dst {${mask}}, $src2, $src3}"),
798 (OpVT (vselect KRC:$mask,
799 (OpNode RC:$src1, RC:$src2,
800 (mem_frag addr:$src3)),
804 let AddedComplexity = 10 in // Prefer over the rrkz variant
805 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
806 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
807 !strconcat(OpcodeStr,
808 " \t{$src3, $src2, $dst {${mask}} {z}|"
809 "$dst {${mask}} {z}, $src2, $src3}"),
811 (OpVT (vselect KRC:$mask,
812 (OpNode RC:$src1, RC:$src2,
813 (mem_frag addr:$src3)),
815 (v16i32 immAllZerosV))))))]>,
819 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
820 i512mem, X86VPermiv3, v16i32, VK16WM>,
821 EVEX_V512, EVEX_CD8<32, CD8VF>;
822 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
823 i512mem, X86VPermiv3, v8i64, VK8WM>,
824 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
825 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
826 i512mem, X86VPermiv3, v16f32, VK16WM>,
827 EVEX_V512, EVEX_CD8<32, CD8VF>;
828 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
829 i512mem, X86VPermiv3, v8f64, VK8WM>,
830 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
832 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
833 PatFrag mem_frag, X86MemOperand x86memop,
834 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
835 ValueType MaskVT, RegisterClass MRC> :
836 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
838 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
839 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
840 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
842 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
843 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
844 (!cast<Instruction>(NAME#rrk) VR512:$src1,
845 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
848 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
849 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
850 EVEX_V512, EVEX_CD8<32, CD8VF>;
851 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
852 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
853 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
854 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
855 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
856 EVEX_V512, EVEX_CD8<32, CD8VF>;
857 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
858 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
859 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
861 //===----------------------------------------------------------------------===//
862 // AVX-512 - BLEND using mask
864 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
865 RegisterClass KRC, RegisterClass RC,
866 X86MemOperand x86memop, PatFrag mem_frag,
867 SDNode OpNode, ValueType vt> {
868 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
869 (ins KRC:$mask, RC:$src1, RC:$src2),
870 !strconcat(OpcodeStr,
871 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
872 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
873 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
875 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
876 (ins KRC:$mask, RC:$src1, x86memop:$src2),
877 !strconcat(OpcodeStr,
878 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
879 []>, EVEX_4V, EVEX_K;
882 let ExeDomain = SSEPackedSingle in
883 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
884 VK16WM, VR512, f512mem,
885 memopv16f32, vselect, v16f32>,
886 EVEX_CD8<32, CD8VF>, EVEX_V512;
887 let ExeDomain = SSEPackedDouble in
888 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
889 VK8WM, VR512, f512mem,
890 memopv8f64, vselect, v8f64>,
891 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
893 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
894 (v16f32 VR512:$src2), (i16 GR16:$mask))),
895 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
896 VR512:$src1, VR512:$src2)>;
898 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
899 (v8f64 VR512:$src2), (i8 GR8:$mask))),
900 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
901 VR512:$src1, VR512:$src2)>;
903 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
904 VK16WM, VR512, f512mem,
905 memopv16i32, vselect, v16i32>,
906 EVEX_CD8<32, CD8VF>, EVEX_V512;
908 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
909 VK8WM, VR512, f512mem,
910 memopv8i64, vselect, v8i64>,
911 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
913 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
914 (v16i32 VR512:$src2), (i16 GR16:$mask))),
915 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
916 VR512:$src1, VR512:$src2)>;
918 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
919 (v8i64 VR512:$src2), (i8 GR8:$mask))),
920 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
921 VR512:$src1, VR512:$src2)>;
923 let Predicates = [HasAVX512] in {
924 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
925 (v8f32 VR256X:$src2))),
927 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
928 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
929 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
931 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
932 (v8i32 VR256X:$src2))),
934 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
935 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
936 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
938 //===----------------------------------------------------------------------===//
939 // Compare Instructions
940 //===----------------------------------------------------------------------===//
942 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
943 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
944 Operand CC, SDNode OpNode, ValueType VT,
945 PatFrag ld_frag, string asm, string asm_alt> {
946 def rr : AVX512Ii8<0xC2, MRMSrcReg,
947 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
948 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
949 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
950 def rm : AVX512Ii8<0xC2, MRMSrcMem,
951 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
952 [(set VK1:$dst, (OpNode (VT RC:$src1),
953 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
954 let isAsmParserOnly = 1, hasSideEffects = 0 in {
955 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
956 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
957 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
958 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
959 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
960 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
964 let Predicates = [HasAVX512] in {
965 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
966 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
967 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
969 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
970 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
971 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
975 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
977 def rr : AVX512BI<opc, MRMSrcReg,
978 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
979 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
980 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
981 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
983 def rm : AVX512BI<opc, MRMSrcMem,
984 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
985 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
986 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
987 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
988 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
989 def rrk : AVX512BI<opc, MRMSrcReg,
990 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
991 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
992 "$dst {${mask}}, $src1, $src2}"),
993 [(set _.KRC:$dst, (and _.KRCWM:$mask,
994 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
995 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
997 def rmk : AVX512BI<opc, MRMSrcMem,
998 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
999 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1000 "$dst {${mask}}, $src1, $src2}"),
1001 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1002 (OpNode (_.VT _.RC:$src1),
1004 (_.LdFrag addr:$src2))))))],
1005 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1008 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1009 X86VectorVTInfo _> :
1010 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1011 let mayLoad = 1 in {
1012 def rmb : AVX512BI<opc, MRMSrcMem,
1013 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1014 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1015 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1016 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1017 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1018 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1019 def rmbk : AVX512BI<opc, MRMSrcMem,
1020 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1021 _.ScalarMemOp:$src2),
1022 !strconcat(OpcodeStr,
1023 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1024 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1025 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1026 (OpNode (_.VT _.RC:$src1),
1028 (_.ScalarLdFrag addr:$src2)))))],
1029 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1033 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1034 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1035 let Predicates = [prd] in
1036 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1039 let Predicates = [prd, HasVLX] in {
1040 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1042 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1047 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1048 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1050 let Predicates = [prd] in
1051 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1054 let Predicates = [prd, HasVLX] in {
1055 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1057 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1062 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1063 avx512vl_i8_info, HasBWI>,
1066 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1067 avx512vl_i16_info, HasBWI>,
1068 EVEX_CD8<16, CD8VF>;
1070 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1071 avx512vl_i32_info, HasAVX512>,
1072 EVEX_CD8<32, CD8VF>;
1074 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1075 avx512vl_i64_info, HasAVX512>,
1076 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1078 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1079 avx512vl_i8_info, HasBWI>,
1082 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1083 avx512vl_i16_info, HasBWI>,
1084 EVEX_CD8<16, CD8VF>;
1086 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1087 avx512vl_i32_info, HasAVX512>,
1088 EVEX_CD8<32, CD8VF>;
1090 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1091 avx512vl_i64_info, HasAVX512>,
1092 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1094 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1095 (COPY_TO_REGCLASS (VPCMPGTDZrr
1096 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1097 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1099 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1100 (COPY_TO_REGCLASS (VPCMPEQDZrr
1101 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1102 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1104 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1105 X86VectorVTInfo _> {
1106 def rri : AVX512AIi8<opc, MRMSrcReg,
1107 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1108 !strconcat("vpcmp${cc}", Suffix,
1109 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1110 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1112 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1114 def rmi : AVX512AIi8<opc, MRMSrcMem,
1115 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1116 !strconcat("vpcmp${cc}", Suffix,
1117 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1118 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1119 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1121 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1122 def rrik : AVX512AIi8<opc, MRMSrcReg,
1123 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1125 !strconcat("vpcmp${cc}", Suffix,
1126 "\t{$src2, $src1, $dst {${mask}}|",
1127 "$dst {${mask}}, $src1, $src2}"),
1128 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1129 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1131 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1133 def rmik : AVX512AIi8<opc, MRMSrcMem,
1134 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1136 !strconcat("vpcmp${cc}", Suffix,
1137 "\t{$src2, $src1, $dst {${mask}}|",
1138 "$dst {${mask}}, $src1, $src2}"),
1139 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1140 (OpNode (_.VT _.RC:$src1),
1141 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1143 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1145 // Accept explicit immediate argument form instead of comparison code.
1146 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1147 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1148 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1149 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1150 "$dst, $src1, $src2, $cc}"),
1151 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1152 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1153 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1154 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1155 "$dst, $src1, $src2, $cc}"),
1156 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1157 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1158 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1160 !strconcat("vpcmp", Suffix,
1161 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1162 "$dst {${mask}}, $src1, $src2, $cc}"),
1163 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1164 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1165 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1167 !strconcat("vpcmp", Suffix,
1168 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1169 "$dst {${mask}}, $src1, $src2, $cc}"),
1170 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1174 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1175 X86VectorVTInfo _> :
1176 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1177 let mayLoad = 1 in {
1178 def rmib : AVX512AIi8<opc, MRMSrcMem,
1179 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1181 !strconcat("vpcmp${cc}", Suffix,
1182 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1183 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1184 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1185 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1187 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1188 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1189 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1190 _.ScalarMemOp:$src2, AVXCC:$cc),
1191 !strconcat("vpcmp${cc}", Suffix,
1192 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1193 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1194 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1195 (OpNode (_.VT _.RC:$src1),
1196 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1198 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1201 // Accept explicit immediate argument form instead of comparison code.
1202 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1203 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1204 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1206 !strconcat("vpcmp", Suffix,
1207 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1208 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1209 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1210 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1211 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1212 _.ScalarMemOp:$src2, i8imm:$cc),
1213 !strconcat("vpcmp", Suffix,
1214 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1215 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1216 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1220 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1221 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1222 let Predicates = [prd] in
1223 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1225 let Predicates = [prd, HasVLX] in {
1226 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1227 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1231 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1232 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1233 let Predicates = [prd] in
1234 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1237 let Predicates = [prd, HasVLX] in {
1238 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1240 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1245 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1246 HasBWI>, EVEX_CD8<8, CD8VF>;
1247 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1248 HasBWI>, EVEX_CD8<8, CD8VF>;
1250 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1251 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1252 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1253 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1255 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1256 HasAVX512>, EVEX_CD8<32, CD8VF>;
1257 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1258 HasAVX512>, EVEX_CD8<32, CD8VF>;
1260 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1261 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1262 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1263 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1265 // avx512_cmp_packed - compare packed instructions
1266 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1267 X86MemOperand x86memop, ValueType vt,
1268 string suffix, Domain d> {
1269 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1270 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1271 !strconcat("vcmp${cc}", suffix,
1272 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1273 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1274 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1275 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1276 !strconcat("vcmp${cc}", suffix,
1277 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1279 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1280 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1281 !strconcat("vcmp${cc}", suffix,
1282 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1284 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1286 // Accept explicit immediate argument form instead of comparison code.
1287 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1288 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1289 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1290 !strconcat("vcmp", suffix,
1291 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1292 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1293 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1294 !strconcat("vcmp", suffix,
1295 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1299 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1300 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1301 EVEX_CD8<32, CD8VF>;
1302 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1303 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1304 EVEX_CD8<64, CD8VF>;
1306 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1307 (COPY_TO_REGCLASS (VCMPPSZrri
1308 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1309 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1311 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1312 (COPY_TO_REGCLASS (VPCMPDZrri
1313 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1314 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1316 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1317 (COPY_TO_REGCLASS (VPCMPUDZrri
1318 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1319 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1322 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1323 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1325 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1326 (I8Imm imm:$cc)), GR16)>;
1328 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1329 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1331 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1332 (I8Imm imm:$cc)), GR8)>;
1334 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1335 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1337 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1338 (I8Imm imm:$cc)), GR16)>;
1340 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1341 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1343 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1344 (I8Imm imm:$cc)), GR8)>;
1346 // Mask register copy, including
1347 // - copy between mask registers
1348 // - load/store mask registers
1349 // - copy from GPR to mask register and vice versa
1351 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1352 string OpcodeStr, RegisterClass KRC,
1353 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1354 let hasSideEffects = 0 in {
1355 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1356 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1358 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1359 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1360 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1362 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1363 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1367 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1369 RegisterClass KRC, RegisterClass GRC> {
1370 let hasSideEffects = 0 in {
1371 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1372 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1373 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1374 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1378 let Predicates = [HasDQI] in
1379 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1381 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1384 let Predicates = [HasAVX512] in
1385 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1387 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1390 let Predicates = [HasBWI] in {
1391 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1392 i32mem>, VEX, PD, VEX_W;
1393 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1397 let Predicates = [HasBWI] in {
1398 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1399 i64mem>, VEX, PS, VEX_W;
1400 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1404 // GR from/to mask register
1405 let Predicates = [HasDQI] in {
1406 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1407 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1408 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1409 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1411 let Predicates = [HasAVX512] in {
1412 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1413 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1414 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1415 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1417 let Predicates = [HasBWI] in {
1418 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1419 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1421 let Predicates = [HasBWI] in {
1422 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1423 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1427 let Predicates = [HasDQI] in {
1428 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1429 (KMOVBmk addr:$dst, VK8:$src)>;
1431 let Predicates = [HasAVX512] in {
1432 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1433 (KMOVWmk addr:$dst, VK16:$src)>;
1434 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1435 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1436 def : Pat<(i1 (load addr:$src)),
1437 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1438 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1439 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1441 let Predicates = [HasBWI] in {
1442 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1443 (KMOVDmk addr:$dst, VK32:$src)>;
1445 let Predicates = [HasBWI] in {
1446 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1447 (KMOVQmk addr:$dst, VK64:$src)>;
1450 let Predicates = [HasAVX512] in {
1451 def : Pat<(i1 (trunc (i64 GR64:$src))),
1452 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1455 def : Pat<(i1 (trunc (i32 GR32:$src))),
1456 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1458 def : Pat<(i1 (trunc (i8 GR8:$src))),
1460 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1462 def : Pat<(i1 (trunc (i16 GR16:$src))),
1464 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1467 def : Pat<(i32 (zext VK1:$src)),
1468 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1469 def : Pat<(i8 (zext VK1:$src)),
1472 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1473 def : Pat<(i64 (zext VK1:$src)),
1474 (AND64ri8 (SUBREG_TO_REG (i64 0),
1475 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1476 def : Pat<(i16 (zext VK1:$src)),
1478 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1480 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1481 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1482 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1483 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1485 let Predicates = [HasBWI] in {
1486 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1487 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1488 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1489 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1493 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1494 let Predicates = [HasAVX512] in {
1495 // GR from/to 8-bit mask without native support
1496 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1498 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1500 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1502 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1505 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1506 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1507 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1508 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1510 let Predicates = [HasBWI] in {
1511 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1512 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1513 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1514 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1517 // Mask unary operation
1519 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1520 RegisterClass KRC, SDPatternOperator OpNode,
1522 let Predicates = [prd] in
1523 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1524 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1525 [(set KRC:$dst, (OpNode KRC:$src))]>;
1528 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1529 SDPatternOperator OpNode> {
1530 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1532 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1533 HasAVX512>, VEX, PS;
1534 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1535 HasBWI>, VEX, PD, VEX_W;
1536 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1537 HasBWI>, VEX, PS, VEX_W;
1540 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1542 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1543 let Predicates = [HasAVX512] in
1544 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1546 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1547 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1549 defm : avx512_mask_unop_int<"knot", "KNOT">;
1551 let Predicates = [HasDQI] in
1552 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1553 let Predicates = [HasAVX512] in
1554 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1555 let Predicates = [HasBWI] in
1556 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1557 let Predicates = [HasBWI] in
1558 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1560 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1561 let Predicates = [HasAVX512] in {
1562 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1563 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1565 def : Pat<(not VK8:$src),
1567 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1570 // Mask binary operation
1571 // - KAND, KANDN, KOR, KXNOR, KXOR
1572 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1573 RegisterClass KRC, SDPatternOperator OpNode,
1575 let Predicates = [prd] in
1576 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1577 !strconcat(OpcodeStr,
1578 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1579 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1582 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1583 SDPatternOperator OpNode> {
1584 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1585 HasDQI>, VEX_4V, VEX_L, PD;
1586 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1587 HasAVX512>, VEX_4V, VEX_L, PS;
1588 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1589 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1590 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1591 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1594 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1595 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1597 let isCommutable = 1 in {
1598 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1599 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1600 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1601 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1603 let isCommutable = 0 in
1604 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1606 def : Pat<(xor VK1:$src1, VK1:$src2),
1607 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1608 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1610 def : Pat<(or VK1:$src1, VK1:$src2),
1611 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1612 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1614 def : Pat<(and VK1:$src1, VK1:$src2),
1615 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1616 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1618 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1619 let Predicates = [HasAVX512] in
1620 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1621 (i16 GR16:$src1), (i16 GR16:$src2)),
1622 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1623 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1624 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1627 defm : avx512_mask_binop_int<"kand", "KAND">;
1628 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1629 defm : avx512_mask_binop_int<"kor", "KOR">;
1630 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1631 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1633 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1634 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1635 let Predicates = [HasAVX512] in
1636 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1638 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1639 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1642 defm : avx512_binop_pat<and, KANDWrr>;
1643 defm : avx512_binop_pat<andn, KANDNWrr>;
1644 defm : avx512_binop_pat<or, KORWrr>;
1645 defm : avx512_binop_pat<xnor, KXNORWrr>;
1646 defm : avx512_binop_pat<xor, KXORWrr>;
1649 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1650 RegisterClass KRC> {
1651 let Predicates = [HasAVX512] in
1652 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1653 !strconcat(OpcodeStr,
1654 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1657 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1658 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1662 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1663 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1664 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1665 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1668 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1669 let Predicates = [HasAVX512] in
1670 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1671 (i16 GR16:$src1), (i16 GR16:$src2)),
1672 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1673 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1674 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1676 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1679 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1681 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1682 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1683 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1684 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1687 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1688 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1692 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1694 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1695 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1696 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1699 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1701 let Predicates = [HasAVX512] in
1702 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1703 !strconcat(OpcodeStr,
1704 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1705 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1708 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1710 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1714 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1715 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1717 // Mask setting all 0s or 1s
1718 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1719 let Predicates = [HasAVX512] in
1720 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1721 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1722 [(set KRC:$dst, (VT Val))]>;
1725 multiclass avx512_mask_setop_w<PatFrag Val> {
1726 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1727 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1730 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1731 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1733 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1734 let Predicates = [HasAVX512] in {
1735 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1736 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1737 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1738 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1739 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1741 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1742 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1744 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1745 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1747 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1748 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1750 let Predicates = [HasVLX] in {
1751 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1752 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1753 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1754 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1755 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1756 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1757 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1758 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1761 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1762 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1764 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1765 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1766 //===----------------------------------------------------------------------===//
1767 // AVX-512 - Aligned and unaligned load and store
1770 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1771 RegisterClass KRC, RegisterClass RC,
1772 ValueType vt, ValueType zvt, X86MemOperand memop,
1773 Domain d, bit IsReMaterializable = 1> {
1774 let hasSideEffects = 0 in {
1775 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1776 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1778 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1779 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1780 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1782 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1783 SchedRW = [WriteLoad] in
1784 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1786 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1789 let AddedComplexity = 20 in {
1790 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1791 let hasSideEffects = 0 in
1792 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1793 (ins RC:$src0, KRC:$mask, RC:$src1),
1794 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1795 "${dst} {${mask}}, $src1}"),
1796 [(set RC:$dst, (vt (vselect KRC:$mask,
1800 let mayLoad = 1, SchedRW = [WriteLoad] in
1801 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1802 (ins RC:$src0, KRC:$mask, memop:$src1),
1803 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1804 "${dst} {${mask}}, $src1}"),
1807 (vt (bitconvert (ld_frag addr:$src1))),
1811 let mayLoad = 1, SchedRW = [WriteLoad] in
1812 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1813 (ins KRC:$mask, memop:$src),
1814 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1815 "${dst} {${mask}} {z}, $src}"),
1818 (vt (bitconvert (ld_frag addr:$src))),
1819 (vt (bitconvert (zvt immAllZerosV))))))],
1824 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1825 string elty, string elsz, string vsz512,
1826 string vsz256, string vsz128, Domain d,
1827 Predicate prd, bit IsReMaterializable = 1> {
1828 let Predicates = [prd] in
1829 defm Z : avx512_load<opc, OpcodeStr,
1830 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1831 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1832 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1833 !cast<X86MemOperand>(elty##"512mem"), d,
1834 IsReMaterializable>, EVEX_V512;
1836 let Predicates = [prd, HasVLX] in {
1837 defm Z256 : avx512_load<opc, OpcodeStr,
1838 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1839 "v"##vsz256##elty##elsz, "v4i64")),
1840 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1841 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1842 !cast<X86MemOperand>(elty##"256mem"), d,
1843 IsReMaterializable>, EVEX_V256;
1845 defm Z128 : avx512_load<opc, OpcodeStr,
1846 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1847 "v"##vsz128##elty##elsz, "v2i64")),
1848 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1849 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1850 !cast<X86MemOperand>(elty##"128mem"), d,
1851 IsReMaterializable>, EVEX_V128;
1856 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1857 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1858 X86MemOperand memop, Domain d> {
1859 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1860 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1861 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1863 let Constraints = "$src1 = $dst" in
1864 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1865 (ins RC:$src1, KRC:$mask, RC:$src2),
1866 !strconcat(OpcodeStr,
1867 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1869 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1870 (ins KRC:$mask, RC:$src),
1871 !strconcat(OpcodeStr,
1872 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1873 [], d>, EVEX, EVEX_KZ;
1875 let mayStore = 1 in {
1876 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1877 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1878 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1879 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1880 (ins memop:$dst, KRC:$mask, RC:$src),
1881 !strconcat(OpcodeStr,
1882 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1883 [], d>, EVEX, EVEX_K;
1888 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1889 string st_suff_512, string st_suff_256,
1890 string st_suff_128, string elty, string elsz,
1891 string vsz512, string vsz256, string vsz128,
1892 Domain d, Predicate prd> {
1893 let Predicates = [prd] in
1894 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1895 !cast<ValueType>("v"##vsz512##elty##elsz),
1896 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1897 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1899 let Predicates = [prd, HasVLX] in {
1900 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1901 !cast<ValueType>("v"##vsz256##elty##elsz),
1902 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1903 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1905 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1906 !cast<ValueType>("v"##vsz128##elty##elsz),
1907 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1908 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1912 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1913 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1914 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1915 "512", "256", "", "f", "32", "16", "8", "4",
1916 SSEPackedSingle, HasAVX512>,
1917 PS, EVEX_CD8<32, CD8VF>;
1919 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1920 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1921 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1922 "512", "256", "", "f", "64", "8", "4", "2",
1923 SSEPackedDouble, HasAVX512>,
1924 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1926 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1927 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1928 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1929 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1930 PS, EVEX_CD8<32, CD8VF>;
1932 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1933 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1934 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1935 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1936 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1938 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1939 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1940 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1942 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1943 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1944 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1946 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1948 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1950 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1952 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1955 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1956 "16", "8", "4", SSEPackedInt, HasAVX512>,
1957 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1958 "512", "256", "", "i", "32", "16", "8", "4",
1959 SSEPackedInt, HasAVX512>,
1960 PD, EVEX_CD8<32, CD8VF>;
1962 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1963 "8", "4", "2", SSEPackedInt, HasAVX512>,
1964 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1965 "512", "256", "", "i", "64", "8", "4", "2",
1966 SSEPackedInt, HasAVX512>,
1967 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1969 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1970 "64", "32", "16", SSEPackedInt, HasBWI>,
1971 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1972 "i", "8", "64", "32", "16", SSEPackedInt,
1973 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1975 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1976 "32", "16", "8", SSEPackedInt, HasBWI>,
1977 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1978 "i", "16", "32", "16", "8", SSEPackedInt,
1979 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1981 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1982 "16", "8", "4", SSEPackedInt, HasAVX512>,
1983 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1984 "i", "32", "16", "8", "4", SSEPackedInt,
1985 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1987 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1988 "8", "4", "2", SSEPackedInt, HasAVX512>,
1989 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1990 "i", "64", "8", "4", "2", SSEPackedInt,
1991 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
1993 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1994 (v16i32 immAllZerosV), GR16:$mask)),
1995 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1997 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1998 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1999 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2001 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2003 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2005 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2007 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2010 let AddedComplexity = 20 in {
2011 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2012 (bc_v8i64 (v16i32 immAllZerosV)))),
2013 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2015 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2016 (v8i64 VR512:$src))),
2017 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2020 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2021 (v16i32 immAllZerosV))),
2022 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2024 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2025 (v16i32 VR512:$src))),
2026 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2029 // Move Int Doubleword to Packed Double Int
2031 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2032 "vmovd\t{$src, $dst|$dst, $src}",
2034 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2036 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2037 "vmovd\t{$src, $dst|$dst, $src}",
2039 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2040 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2041 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2042 "vmovq\t{$src, $dst|$dst, $src}",
2044 (v2i64 (scalar_to_vector GR64:$src)))],
2045 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2046 let isCodeGenOnly = 1 in {
2047 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2048 "vmovq\t{$src, $dst|$dst, $src}",
2049 [(set FR64:$dst, (bitconvert GR64:$src))],
2050 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2051 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2052 "vmovq\t{$src, $dst|$dst, $src}",
2053 [(set GR64:$dst, (bitconvert FR64:$src))],
2054 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2056 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2057 "vmovq\t{$src, $dst|$dst, $src}",
2058 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2059 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2060 EVEX_CD8<64, CD8VT1>;
2062 // Move Int Doubleword to Single Scalar
2064 let isCodeGenOnly = 1 in {
2065 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2066 "vmovd\t{$src, $dst|$dst, $src}",
2067 [(set FR32X:$dst, (bitconvert GR32:$src))],
2068 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2070 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2071 "vmovd\t{$src, $dst|$dst, $src}",
2072 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2073 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2076 // Move doubleword from xmm register to r/m32
2078 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2079 "vmovd\t{$src, $dst|$dst, $src}",
2080 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2081 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2083 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2084 (ins i32mem:$dst, VR128X:$src),
2085 "vmovd\t{$src, $dst|$dst, $src}",
2086 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2087 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2088 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2090 // Move quadword from xmm1 register to r/m64
2092 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2093 "vmovq\t{$src, $dst|$dst, $src}",
2094 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2096 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2097 Requires<[HasAVX512, In64BitMode]>;
2099 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2100 (ins i64mem:$dst, VR128X:$src),
2101 "vmovq\t{$src, $dst|$dst, $src}",
2102 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2103 addr:$dst)], IIC_SSE_MOVDQ>,
2104 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2105 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2107 // Move Scalar Single to Double Int
2109 let isCodeGenOnly = 1 in {
2110 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2112 "vmovd\t{$src, $dst|$dst, $src}",
2113 [(set GR32:$dst, (bitconvert FR32X:$src))],
2114 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2115 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2116 (ins i32mem:$dst, FR32X:$src),
2117 "vmovd\t{$src, $dst|$dst, $src}",
2118 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2119 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2122 // Move Quadword Int to Packed Quadword Int
2124 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2126 "vmovq\t{$src, $dst|$dst, $src}",
2128 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2129 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2131 //===----------------------------------------------------------------------===//
2132 // AVX-512 MOVSS, MOVSD
2133 //===----------------------------------------------------------------------===//
2135 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2136 SDNode OpNode, ValueType vt,
2137 X86MemOperand x86memop, PatFrag mem_pat> {
2138 let hasSideEffects = 0 in {
2139 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2140 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2141 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2142 (scalar_to_vector RC:$src2))))],
2143 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2144 let Constraints = "$src1 = $dst" in
2145 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2146 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2148 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2149 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2150 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2151 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2152 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2154 let mayStore = 1 in {
2155 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2156 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2157 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2159 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2160 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2161 [], IIC_SSE_MOV_S_MR>,
2162 EVEX, VEX_LIG, EVEX_K;
2164 } //hasSideEffects = 0
2167 let ExeDomain = SSEPackedSingle in
2168 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2169 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2171 let ExeDomain = SSEPackedDouble in
2172 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2173 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2175 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2176 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2177 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2179 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2180 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2181 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2183 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2184 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2185 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2187 // For the disassembler
2188 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2189 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2190 (ins VR128X:$src1, FR32X:$src2),
2191 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2193 XS, EVEX_4V, VEX_LIG;
2194 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2195 (ins VR128X:$src1, FR64X:$src2),
2196 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2198 XD, EVEX_4V, VEX_LIG, VEX_W;
2201 let Predicates = [HasAVX512] in {
2202 let AddedComplexity = 15 in {
2203 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2204 // MOVS{S,D} to the lower bits.
2205 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2206 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2207 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2208 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2209 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2210 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2211 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2212 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2214 // Move low f32 and clear high bits.
2215 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2216 (SUBREG_TO_REG (i32 0),
2217 (VMOVSSZrr (v4f32 (V_SET0)),
2218 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2219 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2220 (SUBREG_TO_REG (i32 0),
2221 (VMOVSSZrr (v4i32 (V_SET0)),
2222 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2225 let AddedComplexity = 20 in {
2226 // MOVSSrm zeros the high parts of the register; represent this
2227 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2228 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2229 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2230 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2231 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2232 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2233 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2235 // MOVSDrm zeros the high parts of the register; represent this
2236 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2237 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2238 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2239 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2240 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2241 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2242 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2243 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2244 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2245 def : Pat<(v2f64 (X86vzload addr:$src)),
2246 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2248 // Represent the same patterns above but in the form they appear for
2250 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2251 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2252 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2253 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2254 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2255 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2256 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2257 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2258 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2260 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2261 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2262 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2263 FR32X:$src)), sub_xmm)>;
2264 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2265 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2266 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2267 FR64X:$src)), sub_xmm)>;
2268 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2269 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2270 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2272 // Move low f64 and clear high bits.
2273 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2274 (SUBREG_TO_REG (i32 0),
2275 (VMOVSDZrr (v2f64 (V_SET0)),
2276 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2278 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2279 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2280 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2282 // Extract and store.
2283 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2285 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2286 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2288 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2290 // Shuffle with VMOVSS
2291 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2292 (VMOVSSZrr (v4i32 VR128X:$src1),
2293 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2294 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2295 (VMOVSSZrr (v4f32 VR128X:$src1),
2296 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2299 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2300 (SUBREG_TO_REG (i32 0),
2301 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2302 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2304 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2305 (SUBREG_TO_REG (i32 0),
2306 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2307 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2310 // Shuffle with VMOVSD
2311 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2312 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2313 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2314 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2315 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2316 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2317 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2318 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2321 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2322 (SUBREG_TO_REG (i32 0),
2323 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2324 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2326 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2327 (SUBREG_TO_REG (i32 0),
2328 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2329 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2332 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2333 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2334 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2335 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2336 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2337 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2338 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2339 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2342 let AddedComplexity = 15 in
2343 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2345 "vmovq\t{$src, $dst|$dst, $src}",
2346 [(set VR128X:$dst, (v2i64 (X86vzmovl
2347 (v2i64 VR128X:$src))))],
2348 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2350 let AddedComplexity = 20 in
2351 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2353 "vmovq\t{$src, $dst|$dst, $src}",
2354 [(set VR128X:$dst, (v2i64 (X86vzmovl
2355 (loadv2i64 addr:$src))))],
2356 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2357 EVEX_CD8<8, CD8VT8>;
2359 let Predicates = [HasAVX512] in {
2360 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2361 let AddedComplexity = 20 in {
2362 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2363 (VMOVDI2PDIZrm addr:$src)>;
2364 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2365 (VMOV64toPQIZrr GR64:$src)>;
2366 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2367 (VMOVDI2PDIZrr GR32:$src)>;
2369 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2370 (VMOVDI2PDIZrm addr:$src)>;
2371 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2372 (VMOVDI2PDIZrm addr:$src)>;
2373 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2374 (VMOVZPQILo2PQIZrm addr:$src)>;
2375 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2376 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2377 def : Pat<(v2i64 (X86vzload addr:$src)),
2378 (VMOVZPQILo2PQIZrm addr:$src)>;
2381 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2382 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2383 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2384 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2385 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2386 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2387 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2390 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2391 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2393 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2394 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2396 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2397 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2399 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2400 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2402 //===----------------------------------------------------------------------===//
2403 // AVX-512 - Non-temporals
2404 //===----------------------------------------------------------------------===//
2405 let SchedRW = [WriteLoad] in {
2406 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2407 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2408 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2409 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2410 EVEX_CD8<64, CD8VF>;
2412 let Predicates = [HasAVX512, HasVLX] in {
2413 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2415 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2416 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2417 EVEX_CD8<64, CD8VF>;
2419 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2421 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2422 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2423 EVEX_CD8<64, CD8VF>;
2427 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2428 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2429 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2430 let SchedRW = [WriteStore], mayStore = 1,
2431 AddedComplexity = 400 in
2432 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2434 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2437 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2438 string elty, string elsz, string vsz512,
2439 string vsz256, string vsz128, Domain d,
2440 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2441 let Predicates = [prd] in
2442 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2443 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2444 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2447 let Predicates = [prd, HasVLX] in {
2448 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2449 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2450 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2453 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2454 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2455 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2460 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2461 "i", "64", "8", "4", "2", SSEPackedInt,
2462 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2464 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2465 "f", "64", "8", "4", "2", SSEPackedDouble,
2466 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2468 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2469 "f", "32", "16", "8", "4", SSEPackedSingle,
2470 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2472 //===----------------------------------------------------------------------===//
2473 // AVX-512 - Integer arithmetic
2475 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2476 X86VectorVTInfo _, OpndItins itins,
2477 bit IsCommutable = 0> {
2478 defm rr : AVX512_masking<opc, MRMSrcReg, _, (outs _.RC:$dst),
2479 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2480 "$src2, $src1", "$src1, $src2",
2481 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2482 itins.rr, IsCommutable>,
2483 AVX512BIBase, EVEX_4V;
2485 let mayLoad = 1 in {
2486 defm rm : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2487 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2488 "$src2, $src1", "$src1, $src2",
2489 (_.VT (OpNode _.RC:$src1,
2490 (bitconvert (_.LdFrag addr:$src2)))),
2492 AVX512BIBase, EVEX_4V;
2493 defm rmb : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2494 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2495 "${src2}"##_.BroadcastStr##", $src1",
2496 "$src1, ${src2}"##_.BroadcastStr,
2497 (_.VT (OpNode _.RC:$src1,
2499 (_.ScalarLdFrag addr:$src2)))),
2501 AVX512BIBase, EVEX_4V, EVEX_B;
2505 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2506 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2507 PatFrag memop_frag, X86MemOperand x86memop,
2508 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2509 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2510 let isCommutable = IsCommutable in
2512 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2513 (ins RC:$src1, RC:$src2),
2514 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2516 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2517 (ins KRC:$mask, RC:$src1, RC:$src2),
2518 !strconcat(OpcodeStr,
2519 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2520 [], itins.rr>, EVEX_4V, EVEX_K;
2521 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2522 (ins KRC:$mask, RC:$src1, RC:$src2),
2523 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2524 "|$dst {${mask}} {z}, $src1, $src2}"),
2525 [], itins.rr>, EVEX_4V, EVEX_KZ;
2527 let mayLoad = 1 in {
2528 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2529 (ins RC:$src1, x86memop:$src2),
2530 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2532 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2533 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2534 !strconcat(OpcodeStr,
2535 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2536 [], itins.rm>, EVEX_4V, EVEX_K;
2537 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2538 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2539 !strconcat(OpcodeStr,
2540 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2541 [], itins.rm>, EVEX_4V, EVEX_KZ;
2542 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2543 (ins RC:$src1, x86scalar_mop:$src2),
2544 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2545 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2546 [], itins.rm>, EVEX_4V, EVEX_B;
2547 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2548 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2549 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2550 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2552 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2553 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2554 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2555 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2556 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2558 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2562 defm VPADDDZ : avx512_binop_rm<0xFE, "vpadd", add, v16i32_info,
2563 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2565 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsub", sub, v16i32_info,
2566 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2568 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmull", mul, v16i32_info,
2569 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2571 defm VPADDQZ : avx512_binop_rm<0xD4, "vpadd", add, v8i64_info,
2572 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2574 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsub", sub, v8i64_info,
2575 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2577 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2578 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2579 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2580 EVEX_CD8<64, CD8VF>, VEX_W;
2582 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2583 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2584 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2586 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2587 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2589 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2590 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2591 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2592 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2593 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2594 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2596 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v16i32_info,
2597 SSE_INTALU_ITINS_P, 1>,
2598 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2599 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v8i64_info,
2600 SSE_INTALU_ITINS_P, 0>,
2601 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2603 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v16i32_info,
2604 SSE_INTALU_ITINS_P, 1>,
2605 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2606 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v8i64_info,
2607 SSE_INTALU_ITINS_P, 0>,
2608 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2610 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v16i32_info,
2611 SSE_INTALU_ITINS_P, 1>,
2612 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2613 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v8i64_info,
2614 SSE_INTALU_ITINS_P, 0>,
2615 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2617 defm VPMINSDZ : avx512_binop_rm<0x39, "vpmins", X86smin, v16i32_info,
2618 SSE_INTALU_ITINS_P, 1>,
2619 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2620 defm VPMINSQZ : avx512_binop_rm<0x39, "vpmins", X86smin, v8i64_info,
2621 SSE_INTALU_ITINS_P, 0>,
2622 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2624 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2625 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2626 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2627 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2628 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2629 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2630 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2631 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2632 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2633 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2634 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2635 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2636 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2637 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2638 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2639 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2640 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2641 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2642 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2643 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2644 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2645 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2646 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2647 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2648 //===----------------------------------------------------------------------===//
2649 // AVX-512 - Unpack Instructions
2650 //===----------------------------------------------------------------------===//
2652 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2653 PatFrag mem_frag, RegisterClass RC,
2654 X86MemOperand x86memop, string asm,
2656 def rr : AVX512PI<opc, MRMSrcReg,
2657 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2659 (vt (OpNode RC:$src1, RC:$src2)))],
2661 def rm : AVX512PI<opc, MRMSrcMem,
2662 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2664 (vt (OpNode RC:$src1,
2665 (bitconvert (mem_frag addr:$src2)))))],
2669 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2670 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2671 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2672 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2673 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2674 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2675 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2676 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2677 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2678 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2679 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2680 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2682 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2683 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2684 X86MemOperand x86memop> {
2685 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2686 (ins RC:$src1, RC:$src2),
2687 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2688 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2689 IIC_SSE_UNPCK>, EVEX_4V;
2690 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2691 (ins RC:$src1, x86memop:$src2),
2692 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2693 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2694 (bitconvert (memop_frag addr:$src2)))))],
2695 IIC_SSE_UNPCK>, EVEX_4V;
2697 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2698 VR512, memopv16i32, i512mem>, EVEX_V512,
2699 EVEX_CD8<32, CD8VF>;
2700 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2701 VR512, memopv8i64, i512mem>, EVEX_V512,
2702 VEX_W, EVEX_CD8<64, CD8VF>;
2703 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2704 VR512, memopv16i32, i512mem>, EVEX_V512,
2705 EVEX_CD8<32, CD8VF>;
2706 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2707 VR512, memopv8i64, i512mem>, EVEX_V512,
2708 VEX_W, EVEX_CD8<64, CD8VF>;
2709 //===----------------------------------------------------------------------===//
2713 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2714 SDNode OpNode, PatFrag mem_frag,
2715 X86MemOperand x86memop, ValueType OpVT> {
2716 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2717 (ins RC:$src1, i8imm:$src2),
2718 !strconcat(OpcodeStr,
2719 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2721 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2723 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2724 (ins x86memop:$src1, i8imm:$src2),
2725 !strconcat(OpcodeStr,
2726 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2728 (OpVT (OpNode (mem_frag addr:$src1),
2729 (i8 imm:$src2))))]>, EVEX;
2732 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2733 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2735 let ExeDomain = SSEPackedSingle in
2736 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
2737 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2738 EVEX_CD8<32, CD8VF>;
2739 let ExeDomain = SSEPackedDouble in
2740 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
2741 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2742 VEX_W, EVEX_CD8<32, CD8VF>;
2744 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2745 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2746 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2747 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2749 //===----------------------------------------------------------------------===//
2750 // AVX-512 Logical Instructions
2751 //===----------------------------------------------------------------------===//
2753 defm VPANDDZ : avx512_binop_rm<0xDB, "vpand", and, v16i32_info, SSE_BIT_ITINS_P, 1>,
2754 EVEX_V512, EVEX_CD8<32, CD8VF>;
2755 defm VPANDQZ : avx512_binop_rm<0xDB, "vpand", and, v8i64_info, SSE_BIT_ITINS_P, 1>,
2756 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2757 defm VPORDZ : avx512_binop_rm<0xEB, "vpor", or, v16i32_info, SSE_BIT_ITINS_P, 1>,
2758 EVEX_V512, EVEX_CD8<32, CD8VF>;
2759 defm VPORQZ : avx512_binop_rm<0xEB, "vpor", or, v8i64_info, SSE_BIT_ITINS_P, 1>,
2760 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2761 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxor", xor, v16i32_info, SSE_BIT_ITINS_P, 1>,
2762 EVEX_V512, EVEX_CD8<32, CD8VF>;
2763 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxor", xor, v8i64_info, SSE_BIT_ITINS_P, 1>,
2764 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2765 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v16i32_info,
2766 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2767 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v8i64_info,
2768 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2770 //===----------------------------------------------------------------------===//
2771 // AVX-512 FP arithmetic
2772 //===----------------------------------------------------------------------===//
2774 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2776 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2777 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2778 EVEX_CD8<32, CD8VT1>;
2779 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2780 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2781 EVEX_CD8<64, CD8VT1>;
2784 let isCommutable = 1 in {
2785 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2786 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2787 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2788 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2790 let isCommutable = 0 in {
2791 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2792 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2795 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2797 RegisterClass RC, ValueType vt,
2798 X86MemOperand x86memop, PatFrag mem_frag,
2799 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2801 Domain d, OpndItins itins, bit commutable> {
2802 let isCommutable = commutable in {
2803 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2804 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2805 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2808 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2809 !strconcat(OpcodeStr,
2810 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2811 [], itins.rr, d>, EVEX_4V, EVEX_K;
2813 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2814 !strconcat(OpcodeStr,
2815 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2816 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2819 let mayLoad = 1 in {
2820 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2821 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2822 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2823 itins.rm, d>, EVEX_4V;
2825 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2826 (ins RC:$src1, x86scalar_mop:$src2),
2827 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2828 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2829 [(set RC:$dst, (OpNode RC:$src1,
2830 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2831 itins.rm, d>, EVEX_4V, EVEX_B;
2833 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2834 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2835 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2836 [], itins.rm, d>, EVEX_4V, EVEX_K;
2838 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2839 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2840 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2841 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2843 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2844 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2845 " \t{${src2}", BrdcstStr,
2846 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2847 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2849 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2850 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2851 " \t{${src2}", BrdcstStr,
2852 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2854 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2858 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2859 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2860 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2862 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2863 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2864 SSE_ALU_ITINS_P.d, 1>,
2865 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2867 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2868 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2869 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2870 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2871 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2872 SSE_ALU_ITINS_P.d, 1>,
2873 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2875 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2876 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2877 SSE_ALU_ITINS_P.s, 1>,
2878 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2879 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2880 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2881 SSE_ALU_ITINS_P.s, 1>,
2882 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2884 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2885 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2886 SSE_ALU_ITINS_P.d, 1>,
2887 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2888 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2889 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2890 SSE_ALU_ITINS_P.d, 1>,
2891 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2893 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2894 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2895 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2896 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2897 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2898 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2900 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2901 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2902 SSE_ALU_ITINS_P.d, 0>,
2903 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2904 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2905 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2906 SSE_ALU_ITINS_P.d, 0>,
2907 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2909 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2910 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2911 (i16 -1), FROUND_CURRENT)),
2912 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2914 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2915 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2916 (i8 -1), FROUND_CURRENT)),
2917 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2919 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2920 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2921 (i16 -1), FROUND_CURRENT)),
2922 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2924 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2925 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2926 (i8 -1), FROUND_CURRENT)),
2927 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2928 //===----------------------------------------------------------------------===//
2929 // AVX-512 VPTESTM instructions
2930 //===----------------------------------------------------------------------===//
2932 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2933 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2934 SDNode OpNode, ValueType vt> {
2935 def rr : AVX512PI<opc, MRMSrcReg,
2936 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2937 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2938 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2939 SSEPackedInt>, EVEX_4V;
2940 def rm : AVX512PI<opc, MRMSrcMem,
2941 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2942 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2943 [(set KRC:$dst, (OpNode (vt RC:$src1),
2944 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2947 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2948 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2949 EVEX_CD8<32, CD8VF>;
2950 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2951 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2952 EVEX_CD8<64, CD8VF>;
2954 let Predicates = [HasCDI] in {
2955 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2956 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2957 EVEX_CD8<32, CD8VF>;
2958 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2959 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2960 EVEX_CD8<64, CD8VF>;
2963 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2964 (v16i32 VR512:$src2), (i16 -1))),
2965 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2967 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2968 (v8i64 VR512:$src2), (i8 -1))),
2969 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2970 //===----------------------------------------------------------------------===//
2971 // AVX-512 Shift instructions
2972 //===----------------------------------------------------------------------===//
2973 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2974 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2975 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2976 RegisterClass KRC> {
2977 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2978 (ins RC:$src1, i8imm:$src2),
2979 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2980 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2981 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2982 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2983 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2984 !strconcat(OpcodeStr,
2985 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2986 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2987 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2988 (ins x86memop:$src1, i8imm:$src2),
2989 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2990 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2991 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2992 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2993 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2994 !strconcat(OpcodeStr,
2995 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2996 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2999 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3000 RegisterClass RC, ValueType vt, ValueType SrcVT,
3001 PatFrag bc_frag, RegisterClass KRC> {
3002 // src2 is always 128-bit
3003 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3004 (ins RC:$src1, VR128X:$src2),
3005 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3006 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3007 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3008 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3009 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3010 !strconcat(OpcodeStr,
3011 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3012 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3013 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3014 (ins RC:$src1, i128mem:$src2),
3015 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3016 [(set RC:$dst, (vt (OpNode RC:$src1,
3017 (bc_frag (memopv2i64 addr:$src2)))))],
3018 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3019 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3020 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3021 !strconcat(OpcodeStr,
3022 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3023 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3026 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3027 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3028 EVEX_V512, EVEX_CD8<32, CD8VF>;
3029 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3030 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3031 EVEX_CD8<32, CD8VQ>;
3033 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3034 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3035 EVEX_CD8<64, CD8VF>, VEX_W;
3036 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3037 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3038 EVEX_CD8<64, CD8VQ>, VEX_W;
3040 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3041 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3042 EVEX_CD8<32, CD8VF>;
3043 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3044 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3045 EVEX_CD8<32, CD8VQ>;
3047 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3048 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3049 EVEX_CD8<64, CD8VF>, VEX_W;
3050 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3051 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3052 EVEX_CD8<64, CD8VQ>, VEX_W;
3054 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3055 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3056 EVEX_V512, EVEX_CD8<32, CD8VF>;
3057 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3058 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3059 EVEX_CD8<32, CD8VQ>;
3061 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3062 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3063 EVEX_CD8<64, CD8VF>, VEX_W;
3064 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3065 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3066 EVEX_CD8<64, CD8VQ>, VEX_W;
3068 //===-------------------------------------------------------------------===//
3069 // Variable Bit Shifts
3070 //===-------------------------------------------------------------------===//
3071 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3072 RegisterClass RC, ValueType vt,
3073 X86MemOperand x86memop, PatFrag mem_frag> {
3074 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3075 (ins RC:$src1, RC:$src2),
3076 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3078 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3080 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3081 (ins RC:$src1, x86memop:$src2),
3082 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3084 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3088 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3089 i512mem, memopv16i32>, EVEX_V512,
3090 EVEX_CD8<32, CD8VF>;
3091 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3092 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3093 EVEX_CD8<64, CD8VF>;
3094 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3095 i512mem, memopv16i32>, EVEX_V512,
3096 EVEX_CD8<32, CD8VF>;
3097 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3098 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3099 EVEX_CD8<64, CD8VF>;
3100 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3101 i512mem, memopv16i32>, EVEX_V512,
3102 EVEX_CD8<32, CD8VF>;
3103 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3104 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3105 EVEX_CD8<64, CD8VF>;
3107 //===----------------------------------------------------------------------===//
3108 // AVX-512 - MOVDDUP
3109 //===----------------------------------------------------------------------===//
3111 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3112 X86MemOperand x86memop, PatFrag memop_frag> {
3113 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3114 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3115 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3116 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3117 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3119 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3122 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3123 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3124 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3125 (VMOVDDUPZrm addr:$src)>;
3127 //===---------------------------------------------------------------------===//
3128 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3129 //===---------------------------------------------------------------------===//
3130 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3131 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3132 X86MemOperand x86memop> {
3133 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3134 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3135 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3137 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3138 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3139 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3142 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3143 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3144 EVEX_CD8<32, CD8VF>;
3145 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3146 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3147 EVEX_CD8<32, CD8VF>;
3149 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3150 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3151 (VMOVSHDUPZrm addr:$src)>;
3152 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3153 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3154 (VMOVSLDUPZrm addr:$src)>;
3156 //===----------------------------------------------------------------------===//
3157 // Move Low to High and High to Low packed FP Instructions
3158 //===----------------------------------------------------------------------===//
3159 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3160 (ins VR128X:$src1, VR128X:$src2),
3161 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3162 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3163 IIC_SSE_MOV_LH>, EVEX_4V;
3164 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3165 (ins VR128X:$src1, VR128X:$src2),
3166 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3167 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3168 IIC_SSE_MOV_LH>, EVEX_4V;
3170 let Predicates = [HasAVX512] in {
3172 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3173 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3174 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3175 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3178 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3179 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3182 //===----------------------------------------------------------------------===//
3183 // FMA - Fused Multiply Operations
3185 let Constraints = "$src1 = $dst" in {
3186 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3187 X86VectorVTInfo _> {
3188 defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3189 (ins _.RC:$src2, _.RC:$src3),
3190 OpcodeStr, "$src3, $src2", "$src2, $src3",
3191 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3195 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3196 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3197 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3198 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3199 (_.MemOpFrag addr:$src3))))]>;
3200 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3201 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3202 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3203 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3204 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3205 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3207 } // Constraints = "$src1 = $dst"
3209 let ExeDomain = SSEPackedSingle in {
3210 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3212 EVEX_V512, EVEX_CD8<32, CD8VF>;
3213 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3215 EVEX_V512, EVEX_CD8<32, CD8VF>;
3216 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3218 EVEX_V512, EVEX_CD8<32, CD8VF>;
3219 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3221 EVEX_V512, EVEX_CD8<32, CD8VF>;
3222 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3224 EVEX_V512, EVEX_CD8<32, CD8VF>;
3225 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3227 EVEX_V512, EVEX_CD8<32, CD8VF>;
3229 let ExeDomain = SSEPackedDouble in {
3230 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3232 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3233 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3235 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3236 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3238 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3239 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3241 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3242 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3244 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3245 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3247 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3250 let Constraints = "$src1 = $dst" in {
3251 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3252 X86VectorVTInfo _> {
3254 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3255 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3256 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3257 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3259 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3260 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3261 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3262 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3264 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3265 (_.ScalarLdFrag addr:$src2))),
3266 _.RC:$src3))]>, EVEX_B;
3268 } // Constraints = "$src1 = $dst"
3271 let ExeDomain = SSEPackedSingle in {
3272 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3274 EVEX_V512, EVEX_CD8<32, CD8VF>;
3275 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3277 EVEX_V512, EVEX_CD8<32, CD8VF>;
3278 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3280 EVEX_V512, EVEX_CD8<32, CD8VF>;
3281 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3283 EVEX_V512, EVEX_CD8<32, CD8VF>;
3284 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3286 EVEX_V512, EVEX_CD8<32, CD8VF>;
3287 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3289 EVEX_V512, EVEX_CD8<32, CD8VF>;
3291 let ExeDomain = SSEPackedDouble in {
3292 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3294 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3295 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3297 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3298 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3300 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3301 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3303 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3304 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3306 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3307 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3309 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3313 let Constraints = "$src1 = $dst" in {
3314 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3315 RegisterClass RC, ValueType OpVT,
3316 X86MemOperand x86memop, Operand memop,
3318 let isCommutable = 1 in
3319 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3320 (ins RC:$src1, RC:$src2, RC:$src3),
3321 !strconcat(OpcodeStr,
3322 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3324 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3326 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3327 (ins RC:$src1, RC:$src2, f128mem:$src3),
3328 !strconcat(OpcodeStr,
3329 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3331 (OpVT (OpNode RC:$src2, RC:$src1,
3332 (mem_frag addr:$src3))))]>;
3335 } // Constraints = "$src1 = $dst"
3337 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3338 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3339 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3340 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3341 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3342 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3343 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3344 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3345 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3346 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3347 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3348 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3349 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3350 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3351 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3352 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3354 //===----------------------------------------------------------------------===//
3355 // AVX-512 Scalar convert from sign integer to float/double
3356 //===----------------------------------------------------------------------===//
3358 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3359 X86MemOperand x86memop, string asm> {
3360 let hasSideEffects = 0 in {
3361 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3362 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3365 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3366 (ins DstRC:$src1, x86memop:$src),
3367 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3369 } // hasSideEffects = 0
3371 let Predicates = [HasAVX512] in {
3372 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3373 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3374 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3375 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3376 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3377 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3378 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3379 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3381 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3382 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3383 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3384 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3385 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3386 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3387 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3388 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3390 def : Pat<(f32 (sint_to_fp GR32:$src)),
3391 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3392 def : Pat<(f32 (sint_to_fp GR64:$src)),
3393 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3394 def : Pat<(f64 (sint_to_fp GR32:$src)),
3395 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3396 def : Pat<(f64 (sint_to_fp GR64:$src)),
3397 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3399 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3400 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3401 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3402 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3403 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3404 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3405 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3406 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3408 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3409 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3410 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3411 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3412 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3413 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3414 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3415 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3417 def : Pat<(f32 (uint_to_fp GR32:$src)),
3418 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3419 def : Pat<(f32 (uint_to_fp GR64:$src)),
3420 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3421 def : Pat<(f64 (uint_to_fp GR32:$src)),
3422 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3423 def : Pat<(f64 (uint_to_fp GR64:$src)),
3424 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3427 //===----------------------------------------------------------------------===//
3428 // AVX-512 Scalar convert from float/double to integer
3429 //===----------------------------------------------------------------------===//
3430 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3431 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3433 let hasSideEffects = 0 in {
3434 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3435 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3436 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3437 Requires<[HasAVX512]>;
3439 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3440 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3441 Requires<[HasAVX512]>;
3442 } // hasSideEffects = 0
3444 let Predicates = [HasAVX512] in {
3445 // Convert float/double to signed/unsigned int 32/64
3446 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3447 ssmem, sse_load_f32, "cvtss2si">,
3448 XS, EVEX_CD8<32, CD8VT1>;
3449 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3450 ssmem, sse_load_f32, "cvtss2si">,
3451 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3452 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3453 ssmem, sse_load_f32, "cvtss2usi">,
3454 XS, EVEX_CD8<32, CD8VT1>;
3455 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3456 int_x86_avx512_cvtss2usi64, ssmem,
3457 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3458 EVEX_CD8<32, CD8VT1>;
3459 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3460 sdmem, sse_load_f64, "cvtsd2si">,
3461 XD, EVEX_CD8<64, CD8VT1>;
3462 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3463 sdmem, sse_load_f64, "cvtsd2si">,
3464 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3465 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3466 sdmem, sse_load_f64, "cvtsd2usi">,
3467 XD, EVEX_CD8<64, CD8VT1>;
3468 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3469 int_x86_avx512_cvtsd2usi64, sdmem,
3470 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3471 EVEX_CD8<64, CD8VT1>;
3473 let isCodeGenOnly = 1 in {
3474 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3475 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3476 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3477 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3478 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3479 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3480 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3481 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3482 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3483 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3484 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3485 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3487 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3488 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3489 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3490 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3491 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3492 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3493 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3494 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3495 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3496 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3497 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3498 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3499 } // isCodeGenOnly = 1
3501 // Convert float/double to signed/unsigned int 32/64 with truncation
3502 let isCodeGenOnly = 1 in {
3503 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3504 ssmem, sse_load_f32, "cvttss2si">,
3505 XS, EVEX_CD8<32, CD8VT1>;
3506 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3507 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3508 "cvttss2si">, XS, VEX_W,
3509 EVEX_CD8<32, CD8VT1>;
3510 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3511 sdmem, sse_load_f64, "cvttsd2si">, XD,
3512 EVEX_CD8<64, CD8VT1>;
3513 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3514 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3515 "cvttsd2si">, XD, VEX_W,
3516 EVEX_CD8<64, CD8VT1>;
3517 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3518 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3519 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3520 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3521 int_x86_avx512_cvttss2usi64, ssmem,
3522 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3523 EVEX_CD8<32, CD8VT1>;
3524 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3525 int_x86_avx512_cvttsd2usi,
3526 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3527 EVEX_CD8<64, CD8VT1>;
3528 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3529 int_x86_avx512_cvttsd2usi64, sdmem,
3530 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3531 EVEX_CD8<64, CD8VT1>;
3532 } // isCodeGenOnly = 1
3534 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3535 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3537 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3538 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3539 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3540 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3541 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3542 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3545 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3546 loadf32, "cvttss2si">, XS,
3547 EVEX_CD8<32, CD8VT1>;
3548 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3549 loadf32, "cvttss2usi">, XS,
3550 EVEX_CD8<32, CD8VT1>;
3551 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3552 loadf32, "cvttss2si">, XS, VEX_W,
3553 EVEX_CD8<32, CD8VT1>;
3554 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3555 loadf32, "cvttss2usi">, XS, VEX_W,
3556 EVEX_CD8<32, CD8VT1>;
3557 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3558 loadf64, "cvttsd2si">, XD,
3559 EVEX_CD8<64, CD8VT1>;
3560 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3561 loadf64, "cvttsd2usi">, XD,
3562 EVEX_CD8<64, CD8VT1>;
3563 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3564 loadf64, "cvttsd2si">, XD, VEX_W,
3565 EVEX_CD8<64, CD8VT1>;
3566 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3567 loadf64, "cvttsd2usi">, XD, VEX_W,
3568 EVEX_CD8<64, CD8VT1>;
3570 //===----------------------------------------------------------------------===//
3571 // AVX-512 Convert form float to double and back
3572 //===----------------------------------------------------------------------===//
3573 let hasSideEffects = 0 in {
3574 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3575 (ins FR32X:$src1, FR32X:$src2),
3576 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3577 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3579 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3580 (ins FR32X:$src1, f32mem:$src2),
3581 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3582 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3583 EVEX_CD8<32, CD8VT1>;
3585 // Convert scalar double to scalar single
3586 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3587 (ins FR64X:$src1, FR64X:$src2),
3588 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3589 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3591 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3592 (ins FR64X:$src1, f64mem:$src2),
3593 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3594 []>, EVEX_4V, VEX_LIG, VEX_W,
3595 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3598 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3599 Requires<[HasAVX512]>;
3600 def : Pat<(fextend (loadf32 addr:$src)),
3601 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3603 def : Pat<(extloadf32 addr:$src),
3604 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3605 Requires<[HasAVX512, OptForSize]>;
3607 def : Pat<(extloadf32 addr:$src),
3608 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3609 Requires<[HasAVX512, OptForSpeed]>;
3611 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3612 Requires<[HasAVX512]>;
3614 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3615 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3616 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3618 let hasSideEffects = 0 in {
3619 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3620 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3622 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3623 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3624 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3625 [], d>, EVEX, EVEX_B, EVEX_RC;
3627 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3628 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3630 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3631 } // hasSideEffects = 0
3634 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3635 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3636 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3638 let hasSideEffects = 0 in {
3639 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3640 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3642 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3644 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3645 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3647 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3648 } // hasSideEffects = 0
3651 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3652 memopv8f64, f512mem, v8f32, v8f64,
3653 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3654 EVEX_CD8<64, CD8VF>;
3656 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3657 memopv4f64, f256mem, v8f64, v8f32,
3658 SSEPackedDouble>, EVEX_V512, PS,
3659 EVEX_CD8<32, CD8VH>;
3660 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3661 (VCVTPS2PDZrm addr:$src)>;
3663 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3664 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3665 (VCVTPD2PSZrr VR512:$src)>;
3667 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3668 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3669 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3671 //===----------------------------------------------------------------------===//
3672 // AVX-512 Vector convert from sign integer to float/double
3673 //===----------------------------------------------------------------------===//
3675 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3676 memopv8i64, i512mem, v16f32, v16i32,
3677 SSEPackedSingle>, EVEX_V512, PS,
3678 EVEX_CD8<32, CD8VF>;
3680 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3681 memopv4i64, i256mem, v8f64, v8i32,
3682 SSEPackedDouble>, EVEX_V512, XS,
3683 EVEX_CD8<32, CD8VH>;
3685 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3686 memopv16f32, f512mem, v16i32, v16f32,
3687 SSEPackedSingle>, EVEX_V512, XS,
3688 EVEX_CD8<32, CD8VF>;
3690 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3691 memopv8f64, f512mem, v8i32, v8f64,
3692 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3693 EVEX_CD8<64, CD8VF>;
3695 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3696 memopv16f32, f512mem, v16i32, v16f32,
3697 SSEPackedSingle>, EVEX_V512, PS,
3698 EVEX_CD8<32, CD8VF>;
3700 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3701 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3702 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3703 (VCVTTPS2UDQZrr VR512:$src)>;
3705 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3706 memopv8f64, f512mem, v8i32, v8f64,
3707 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3708 EVEX_CD8<64, CD8VF>;
3710 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3711 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3712 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3713 (VCVTTPD2UDQZrr VR512:$src)>;
3715 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3716 memopv4i64, f256mem, v8f64, v8i32,
3717 SSEPackedDouble>, EVEX_V512, XS,
3718 EVEX_CD8<32, CD8VH>;
3720 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3721 memopv16i32, f512mem, v16f32, v16i32,
3722 SSEPackedSingle>, EVEX_V512, XD,
3723 EVEX_CD8<32, CD8VF>;
3725 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3726 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3727 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3729 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3730 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3731 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3733 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3734 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3735 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3737 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3738 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3739 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3741 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3742 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3743 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3745 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3746 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3747 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3748 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3749 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3750 (VCVTDQ2PDZrr VR256X:$src)>;
3751 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3752 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3753 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3754 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3755 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3756 (VCVTUDQ2PDZrr VR256X:$src)>;
3758 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3759 RegisterClass DstRC, PatFrag mem_frag,
3760 X86MemOperand x86memop, Domain d> {
3761 let hasSideEffects = 0 in {
3762 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3763 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3765 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3766 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3767 [], d>, EVEX, EVEX_B, EVEX_RC;
3769 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3770 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3772 } // hasSideEffects = 0
3775 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3776 memopv16f32, f512mem, SSEPackedSingle>, PD,
3777 EVEX_V512, EVEX_CD8<32, CD8VF>;
3778 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3779 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3780 EVEX_V512, EVEX_CD8<64, CD8VF>;
3782 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3783 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3784 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3786 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3787 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3788 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3790 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3791 memopv16f32, f512mem, SSEPackedSingle>,
3792 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3793 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3794 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3795 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3797 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3798 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3799 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3801 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3802 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3803 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3805 let Predicates = [HasAVX512] in {
3806 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3807 (VCVTPD2PSZrm addr:$src)>;
3808 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3809 (VCVTPS2PDZrm addr:$src)>;
3812 //===----------------------------------------------------------------------===//
3813 // Half precision conversion instructions
3814 //===----------------------------------------------------------------------===//
3815 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3816 X86MemOperand x86memop> {
3817 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3818 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3820 let hasSideEffects = 0, mayLoad = 1 in
3821 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3822 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3825 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3826 X86MemOperand x86memop> {
3827 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3828 (ins srcRC:$src1, i32i8imm:$src2),
3829 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3831 let hasSideEffects = 0, mayStore = 1 in
3832 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3833 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3834 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3837 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3838 EVEX_CD8<32, CD8VH>;
3839 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3840 EVEX_CD8<32, CD8VH>;
3842 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3843 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3844 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3846 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3847 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3848 (VCVTPH2PSZrr VR256X:$src)>;
3850 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3851 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3852 "ucomiss">, PS, EVEX, VEX_LIG,
3853 EVEX_CD8<32, CD8VT1>;
3854 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3855 "ucomisd">, PD, EVEX,
3856 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3857 let Pattern = []<dag> in {
3858 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3859 "comiss">, PS, EVEX, VEX_LIG,
3860 EVEX_CD8<32, CD8VT1>;
3861 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3862 "comisd">, PD, EVEX,
3863 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3865 let isCodeGenOnly = 1 in {
3866 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3867 load, "ucomiss">, PS, EVEX, VEX_LIG,
3868 EVEX_CD8<32, CD8VT1>;
3869 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3870 load, "ucomisd">, PD, EVEX,
3871 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3873 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3874 load, "comiss">, PS, EVEX, VEX_LIG,
3875 EVEX_CD8<32, CD8VT1>;
3876 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3877 load, "comisd">, PD, EVEX,
3878 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3882 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3883 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3884 X86MemOperand x86memop> {
3885 let hasSideEffects = 0 in {
3886 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3887 (ins RC:$src1, RC:$src2),
3888 !strconcat(OpcodeStr,
3889 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3890 let mayLoad = 1 in {
3891 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3892 (ins RC:$src1, x86memop:$src2),
3893 !strconcat(OpcodeStr,
3894 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3899 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3900 EVEX_CD8<32, CD8VT1>;
3901 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3902 VEX_W, EVEX_CD8<64, CD8VT1>;
3903 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3904 EVEX_CD8<32, CD8VT1>;
3905 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3906 VEX_W, EVEX_CD8<64, CD8VT1>;
3908 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3909 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3910 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3911 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3913 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3914 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3915 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3916 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3918 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3919 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3920 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3921 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3923 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3924 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3925 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3926 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3928 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3929 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3930 RegisterClass RC, X86MemOperand x86memop,
3931 PatFrag mem_frag, ValueType OpVt> {
3932 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3933 !strconcat(OpcodeStr,
3934 " \t{$src, $dst|$dst, $src}"),
3935 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3937 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3938 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3939 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3942 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3943 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3944 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3945 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3946 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3947 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3948 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3949 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3951 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3952 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3953 (VRSQRT14PSZr VR512:$src)>;
3954 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3955 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3956 (VRSQRT14PDZr VR512:$src)>;
3958 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3959 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3960 (VRCP14PSZr VR512:$src)>;
3961 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3962 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3963 (VRCP14PDZr VR512:$src)>;
3965 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3966 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3967 X86MemOperand x86memop> {
3968 let hasSideEffects = 0, Predicates = [HasERI] in {
3969 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3970 (ins RC:$src1, RC:$src2),
3971 !strconcat(OpcodeStr,
3972 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3973 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3974 (ins RC:$src1, RC:$src2),
3975 !strconcat(OpcodeStr,
3976 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3977 []>, EVEX_4V, EVEX_B;
3978 let mayLoad = 1 in {
3979 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3980 (ins RC:$src1, x86memop:$src2),
3981 !strconcat(OpcodeStr,
3982 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3987 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3988 EVEX_CD8<32, CD8VT1>;
3989 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3990 VEX_W, EVEX_CD8<64, CD8VT1>;
3991 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3992 EVEX_CD8<32, CD8VT1>;
3993 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3994 VEX_W, EVEX_CD8<64, CD8VT1>;
3996 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3997 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3999 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4000 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4002 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4003 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4005 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4006 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4008 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4009 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4011 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4012 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4014 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4015 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4017 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4018 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4020 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4021 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4022 RegisterClass RC, X86MemOperand x86memop> {
4023 let hasSideEffects = 0, Predicates = [HasERI] in {
4024 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4025 !strconcat(OpcodeStr,
4026 " \t{$src, $dst|$dst, $src}"),
4028 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4029 !strconcat(OpcodeStr,
4030 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4032 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4033 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4037 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4038 EVEX_V512, EVEX_CD8<32, CD8VF>;
4039 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4040 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4041 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4042 EVEX_V512, EVEX_CD8<32, CD8VF>;
4043 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4044 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4046 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4047 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4048 (VRSQRT28PSZrb VR512:$src)>;
4049 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4050 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4051 (VRSQRT28PDZrb VR512:$src)>;
4053 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4054 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4055 (VRCP28PSZrb VR512:$src)>;
4056 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4057 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4058 (VRCP28PDZrb VR512:$src)>;
4060 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4061 OpndItins itins_s, OpndItins itins_d> {
4062 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4063 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4064 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4068 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4069 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4071 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4072 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4074 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4075 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4076 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4080 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4081 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4082 [(set VR512:$dst, (OpNode
4083 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4084 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4088 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4089 Intrinsic F32Int, Intrinsic F64Int,
4090 OpndItins itins_s, OpndItins itins_d> {
4091 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4092 (ins FR32X:$src1, FR32X:$src2),
4093 !strconcat(OpcodeStr,
4094 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4095 [], itins_s.rr>, XS, EVEX_4V;
4096 let isCodeGenOnly = 1 in
4097 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4098 (ins VR128X:$src1, VR128X:$src2),
4099 !strconcat(OpcodeStr,
4100 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4102 (F32Int VR128X:$src1, VR128X:$src2))],
4103 itins_s.rr>, XS, EVEX_4V;
4104 let mayLoad = 1 in {
4105 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4106 (ins FR32X:$src1, f32mem:$src2),
4107 !strconcat(OpcodeStr,
4108 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4109 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4110 let isCodeGenOnly = 1 in
4111 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4112 (ins VR128X:$src1, ssmem:$src2),
4113 !strconcat(OpcodeStr,
4114 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4116 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4117 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4119 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4120 (ins FR64X:$src1, FR64X:$src2),
4121 !strconcat(OpcodeStr,
4122 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4124 let isCodeGenOnly = 1 in
4125 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4126 (ins VR128X:$src1, VR128X:$src2),
4127 !strconcat(OpcodeStr,
4128 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4130 (F64Int VR128X:$src1, VR128X:$src2))],
4131 itins_s.rr>, XD, EVEX_4V, VEX_W;
4132 let mayLoad = 1 in {
4133 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4134 (ins FR64X:$src1, f64mem:$src2),
4135 !strconcat(OpcodeStr,
4136 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4137 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4138 let isCodeGenOnly = 1 in
4139 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4140 (ins VR128X:$src1, sdmem:$src2),
4141 !strconcat(OpcodeStr,
4142 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4144 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4145 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4150 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4151 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4152 SSE_SQRTSS, SSE_SQRTSD>,
4153 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
4154 SSE_SQRTPS, SSE_SQRTPD>;
4156 let Predicates = [HasAVX512] in {
4157 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4158 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4159 (VSQRTPSZrr VR512:$src1)>;
4160 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4161 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4162 (VSQRTPDZrr VR512:$src1)>;
4164 def : Pat<(f32 (fsqrt FR32X:$src)),
4165 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4166 def : Pat<(f32 (fsqrt (load addr:$src))),
4167 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4168 Requires<[OptForSize]>;
4169 def : Pat<(f64 (fsqrt FR64X:$src)),
4170 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4171 def : Pat<(f64 (fsqrt (load addr:$src))),
4172 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4173 Requires<[OptForSize]>;
4175 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4176 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4177 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4178 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4179 Requires<[OptForSize]>;
4181 def : Pat<(f32 (X86frcp FR32X:$src)),
4182 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4183 def : Pat<(f32 (X86frcp (load addr:$src))),
4184 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4185 Requires<[OptForSize]>;
4187 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4188 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4189 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4191 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4192 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4194 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4195 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4196 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4198 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4199 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4203 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4204 X86MemOperand x86memop, RegisterClass RC,
4205 PatFrag mem_frag32, PatFrag mem_frag64,
4206 Intrinsic V4F32Int, Intrinsic V2F64Int,
4208 let ExeDomain = SSEPackedSingle in {
4209 // Intrinsic operation, reg.
4210 // Vector intrinsic operation, reg
4211 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4212 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4213 !strconcat(OpcodeStr,
4214 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4215 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4217 // Vector intrinsic operation, mem
4218 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4219 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4220 !strconcat(OpcodeStr,
4221 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4223 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4224 EVEX_CD8<32, VForm>;
4225 } // ExeDomain = SSEPackedSingle
4227 let ExeDomain = SSEPackedDouble in {
4228 // Vector intrinsic operation, reg
4229 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4230 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4231 !strconcat(OpcodeStr,
4232 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4233 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4235 // Vector intrinsic operation, mem
4236 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4237 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4238 !strconcat(OpcodeStr,
4239 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4241 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4242 EVEX_CD8<64, VForm>;
4243 } // ExeDomain = SSEPackedDouble
4246 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4250 let ExeDomain = GenericDomain in {
4252 let hasSideEffects = 0 in
4253 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4254 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4255 !strconcat(OpcodeStr,
4256 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4259 // Intrinsic operation, reg.
4260 let isCodeGenOnly = 1 in
4261 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4262 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4263 !strconcat(OpcodeStr,
4264 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4265 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4267 // Intrinsic operation, mem.
4268 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4269 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4270 !strconcat(OpcodeStr,
4271 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4272 [(set VR128X:$dst, (F32Int VR128X:$src1,
4273 sse_load_f32:$src2, imm:$src3))]>,
4274 EVEX_CD8<32, CD8VT1>;
4277 let hasSideEffects = 0 in
4278 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4279 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4280 !strconcat(OpcodeStr,
4281 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4284 // Intrinsic operation, reg.
4285 let isCodeGenOnly = 1 in
4286 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4287 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4288 !strconcat(OpcodeStr,
4289 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4290 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4293 // Intrinsic operation, mem.
4294 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4295 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4296 !strconcat(OpcodeStr,
4297 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4299 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4300 VEX_W, EVEX_CD8<64, CD8VT1>;
4301 } // ExeDomain = GenericDomain
4304 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4305 X86MemOperand x86memop, RegisterClass RC,
4306 PatFrag mem_frag, Domain d> {
4307 let ExeDomain = d in {
4308 // Intrinsic operation, reg.
4309 // Vector intrinsic operation, reg
4310 def r : AVX512AIi8<opc, MRMSrcReg,
4311 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4312 !strconcat(OpcodeStr,
4313 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4316 // Vector intrinsic operation, mem
4317 def m : AVX512AIi8<opc, MRMSrcMem,
4318 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4319 !strconcat(OpcodeStr,
4320 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4326 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4327 memopv16f32, SSEPackedSingle>, EVEX_V512,
4328 EVEX_CD8<32, CD8VF>;
4330 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4331 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4333 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4336 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4337 memopv8f64, SSEPackedDouble>, EVEX_V512,
4338 VEX_W, EVEX_CD8<64, CD8VF>;
4340 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4341 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4343 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4345 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4346 Operand x86memop, RegisterClass RC, Domain d> {
4347 let ExeDomain = d in {
4348 def r : AVX512AIi8<opc, MRMSrcReg,
4349 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4350 !strconcat(OpcodeStr,
4351 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4354 def m : AVX512AIi8<opc, MRMSrcMem,
4355 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4356 !strconcat(OpcodeStr,
4357 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4362 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4363 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4365 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4366 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4368 def : Pat<(ffloor FR32X:$src),
4369 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4370 def : Pat<(f64 (ffloor FR64X:$src)),
4371 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4372 def : Pat<(f32 (fnearbyint FR32X:$src)),
4373 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4374 def : Pat<(f64 (fnearbyint FR64X:$src)),
4375 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4376 def : Pat<(f32 (fceil FR32X:$src)),
4377 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4378 def : Pat<(f64 (fceil FR64X:$src)),
4379 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4380 def : Pat<(f32 (frint FR32X:$src)),
4381 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4382 def : Pat<(f64 (frint FR64X:$src)),
4383 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4384 def : Pat<(f32 (ftrunc FR32X:$src)),
4385 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4386 def : Pat<(f64 (ftrunc FR64X:$src)),
4387 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4389 def : Pat<(v16f32 (ffloor VR512:$src)),
4390 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4391 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4392 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4393 def : Pat<(v16f32 (fceil VR512:$src)),
4394 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4395 def : Pat<(v16f32 (frint VR512:$src)),
4396 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4397 def : Pat<(v16f32 (ftrunc VR512:$src)),
4398 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4400 def : Pat<(v8f64 (ffloor VR512:$src)),
4401 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4402 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4403 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4404 def : Pat<(v8f64 (fceil VR512:$src)),
4405 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4406 def : Pat<(v8f64 (frint VR512:$src)),
4407 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4408 def : Pat<(v8f64 (ftrunc VR512:$src)),
4409 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4411 //-------------------------------------------------
4412 // Integer truncate and extend operations
4413 //-------------------------------------------------
4415 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4416 RegisterClass dstRC, RegisterClass srcRC,
4417 RegisterClass KRC, X86MemOperand x86memop> {
4418 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4420 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4423 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4424 (ins KRC:$mask, srcRC:$src),
4425 !strconcat(OpcodeStr,
4426 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4429 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4430 (ins KRC:$mask, srcRC:$src),
4431 !strconcat(OpcodeStr,
4432 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4435 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4436 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4439 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4440 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4441 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4445 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4446 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4447 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4448 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4449 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4450 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4451 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4452 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4453 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4454 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4455 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4456 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4457 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4458 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4459 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4460 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4461 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4462 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4463 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4464 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4465 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4466 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4467 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4468 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4469 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4470 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4471 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4472 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4473 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4474 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4476 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4477 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4478 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4479 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4480 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4482 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4483 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4484 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4485 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4486 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4487 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4488 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4489 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4492 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4493 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4494 PatFrag mem_frag, X86MemOperand x86memop,
4495 ValueType OpVT, ValueType InVT> {
4497 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4499 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4500 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4502 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4503 (ins KRC:$mask, SrcRC:$src),
4504 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4507 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4508 (ins KRC:$mask, SrcRC:$src),
4509 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4512 let mayLoad = 1 in {
4513 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4514 (ins x86memop:$src),
4515 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4517 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4520 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4521 (ins KRC:$mask, x86memop:$src),
4522 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4526 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4527 (ins KRC:$mask, x86memop:$src),
4528 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4534 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4535 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4537 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4538 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4540 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4541 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4542 EVEX_CD8<16, CD8VH>;
4543 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4544 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4545 EVEX_CD8<16, CD8VQ>;
4546 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4547 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4548 EVEX_CD8<32, CD8VH>;
4550 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4551 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4553 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4554 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4556 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4557 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4558 EVEX_CD8<16, CD8VH>;
4559 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4560 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4561 EVEX_CD8<16, CD8VQ>;
4562 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4563 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4564 EVEX_CD8<32, CD8VH>;
4566 //===----------------------------------------------------------------------===//
4567 // GATHER - SCATTER Operations
4569 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4570 RegisterClass RC, X86MemOperand memop> {
4572 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4573 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4574 (ins RC:$src1, KRC:$mask, memop:$src2),
4575 !strconcat(OpcodeStr,
4576 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4580 let ExeDomain = SSEPackedDouble in {
4581 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4582 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4583 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4584 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4587 let ExeDomain = SSEPackedSingle in {
4588 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4589 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4590 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4591 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4594 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4595 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4596 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4597 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4599 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4600 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4601 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4602 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4604 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4605 RegisterClass RC, X86MemOperand memop> {
4606 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4607 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4608 (ins memop:$dst, KRC:$mask, RC:$src2),
4609 !strconcat(OpcodeStr,
4610 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4614 let ExeDomain = SSEPackedDouble in {
4615 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4616 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4617 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4618 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4621 let ExeDomain = SSEPackedSingle in {
4622 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4623 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4624 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4625 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4628 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4629 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4630 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4631 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4633 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4634 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4635 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4636 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4639 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4640 RegisterClass KRC, X86MemOperand memop> {
4641 let Predicates = [HasPFI], hasSideEffects = 1 in
4642 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4643 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4647 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4648 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4650 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4651 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4653 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4654 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4656 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4657 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4659 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4660 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4662 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4663 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4665 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4666 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4668 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4669 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4671 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4672 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4674 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4675 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4677 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4678 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4680 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4681 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4683 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4684 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4686 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4687 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4689 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4690 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4692 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4693 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4694 //===----------------------------------------------------------------------===//
4695 // VSHUFPS - VSHUFPD Operations
4697 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4698 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4700 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4701 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4702 !strconcat(OpcodeStr,
4703 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4704 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4705 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4706 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4707 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4708 (ins RC:$src1, RC:$src2, i8imm:$src3),
4709 !strconcat(OpcodeStr,
4710 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4711 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4712 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4713 EVEX_4V, Sched<[WriteShuffle]>;
4716 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4717 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4718 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4719 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4721 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4722 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4723 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4724 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4725 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4727 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4728 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4729 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4730 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4731 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4733 multiclass avx512_valign<X86VectorVTInfo _> {
4734 defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4735 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4737 "$src3, $src2, $src1", "$src1, $src2, $src3",
4738 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4740 AVX512AIi8Base, EVEX_4V;
4742 // Also match valign of packed floats.
4743 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4744 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4747 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4748 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4749 !strconcat("valign"##_.Suffix,
4750 " \t{$src3, $src2, $src1, $dst|"
4751 "$dst, $src1, $src2, $src3}"),
4754 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4755 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4757 // Helper fragments to match sext vXi1 to vXiY.
4758 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4759 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4761 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4762 RegisterClass KRC, RegisterClass RC,
4763 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4765 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4766 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4768 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4769 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4771 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4772 !strconcat(OpcodeStr,
4773 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4775 let mayLoad = 1 in {
4776 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4777 (ins x86memop:$src),
4778 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4780 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4781 (ins KRC:$mask, x86memop:$src),
4782 !strconcat(OpcodeStr,
4783 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4785 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4786 (ins KRC:$mask, x86memop:$src),
4787 !strconcat(OpcodeStr,
4788 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4790 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4791 (ins x86scalar_mop:$src),
4792 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4793 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4795 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4796 (ins KRC:$mask, x86scalar_mop:$src),
4797 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4798 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4799 []>, EVEX, EVEX_B, EVEX_K;
4800 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4801 (ins KRC:$mask, x86scalar_mop:$src),
4802 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4803 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4805 []>, EVEX, EVEX_B, EVEX_KZ;
4809 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4810 i512mem, i32mem, "{1to16}">, EVEX_V512,
4811 EVEX_CD8<32, CD8VF>;
4812 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4813 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4814 EVEX_CD8<64, CD8VF>;
4817 (bc_v16i32 (v16i1sextv16i32)),
4818 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4819 (VPABSDZrr VR512:$src)>;
4821 (bc_v8i64 (v8i1sextv8i64)),
4822 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4823 (VPABSQZrr VR512:$src)>;
4825 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4826 (v16i32 immAllZerosV), (i16 -1))),
4827 (VPABSDZrr VR512:$src)>;
4828 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4829 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4830 (VPABSQZrr VR512:$src)>;
4832 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4833 RegisterClass RC, RegisterClass KRC,
4834 X86MemOperand x86memop,
4835 X86MemOperand x86scalar_mop, string BrdcstStr> {
4836 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4838 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4840 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4841 (ins x86memop:$src),
4842 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4844 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4845 (ins x86scalar_mop:$src),
4846 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4847 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4849 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4850 (ins KRC:$mask, RC:$src),
4851 !strconcat(OpcodeStr,
4852 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4854 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4855 (ins KRC:$mask, x86memop:$src),
4856 !strconcat(OpcodeStr,
4857 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4859 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4860 (ins KRC:$mask, x86scalar_mop:$src),
4861 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4862 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4864 []>, EVEX, EVEX_KZ, EVEX_B;
4866 let Constraints = "$src1 = $dst" in {
4867 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4868 (ins RC:$src1, KRC:$mask, RC:$src2),
4869 !strconcat(OpcodeStr,
4870 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4872 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4873 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4874 !strconcat(OpcodeStr,
4875 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4877 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4878 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4879 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4880 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4881 []>, EVEX, EVEX_K, EVEX_B;
4885 let Predicates = [HasCDI] in {
4886 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4887 i512mem, i32mem, "{1to16}">,
4888 EVEX_V512, EVEX_CD8<32, CD8VF>;
4891 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4892 i512mem, i64mem, "{1to8}">,
4893 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4897 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4899 (VPCONFLICTDrrk VR512:$src1,
4900 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4902 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4904 (VPCONFLICTQrrk VR512:$src1,
4905 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4907 let Predicates = [HasCDI] in {
4908 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4909 i512mem, i32mem, "{1to16}">,
4910 EVEX_V512, EVEX_CD8<32, CD8VF>;
4913 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4914 i512mem, i64mem, "{1to8}">,
4915 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4919 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4921 (VPLZCNTDrrk VR512:$src1,
4922 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4924 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4926 (VPLZCNTQrrk VR512:$src1,
4927 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4929 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4930 (VPLZCNTDrm addr:$src)>;
4931 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4932 (VPLZCNTDrr VR512:$src)>;
4933 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4934 (VPLZCNTQrm addr:$src)>;
4935 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4936 (VPLZCNTQrr VR512:$src)>;
4938 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4939 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4940 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4942 def : Pat<(store VK1:$src, addr:$dst),
4943 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4945 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4946 (truncstore node:$val, node:$ptr), [{
4947 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4950 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4951 (MOV8mr addr:$dst, GR8:$src)>;
4953 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
4954 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
4955 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
4956 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
4959 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
4960 string OpcodeStr, Predicate prd> {
4961 let Predicates = [prd] in
4962 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
4964 let Predicates = [prd, HasVLX] in {
4965 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
4966 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
4970 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
4971 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
4973 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
4975 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
4977 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
4981 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;