1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
26 int NumEltsInVT = !if (!eq (NumElts, 1),
27 !if (!eq (EltVT.Size, 32), 4,
28 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts);
30 string VTName = "v" # NumEltsInVT # EltVT;
33 ValueType VT = !cast<ValueType>(VTName);
35 string EltTypeName = !cast<string>(EltVT);
36 // Size of the element type in bits, e.g. 32 for v16i32.
37 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
38 int EltSize = EltVT.Size;
40 // "i" for integer types and "f" for floating-point types
41 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
43 // Size of RC in bits, e.g. 512 for VR512.
46 // The corresponding memory operand, e.g. i512mem for VR512.
47 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
48 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
51 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
52 // due to load promotion during legalization
53 PatFrag LdFrag = !cast<PatFrag>("load" #
54 !if (!eq (TypeVariantName, "i"),
55 !if (!eq (Size, 128), "v2i64",
56 !if (!eq (Size, 256), "v4i64",
58 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
60 // Load patterns used for memory operands. We only have this defined in
61 // case of i64 element types for sub-512 integer vectors. For now, keep
62 // MemOpFrag undefined in these cases.
64 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
65 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
66 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
67 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
68 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
70 // The corresponding float type, e.g. v16f32 for v16i32
71 // Note: For EltSize < 32, FloatVT is illegal and TableGen
72 // fails to compile, so we choose FloatVT = VT
73 ValueType FloatVT = !cast<ValueType>(
74 !if (!eq (!srl(EltSize,5),0),
76 !if (!eq(TypeVariantName, "i"),
77 "v" # NumElts # "f" # EltSize,
80 // The string to specify embedded broadcast in assembly.
81 string BroadcastStr = "{1to" # NumElts # "}";
83 // 8-bit compressed displacement tuple/subvector format. This is only
84 // defined for NumElts <= 8.
85 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
86 !cast<CD8VForm>("CD8VT" # NumElts), ?);
88 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
89 !if (!eq (Size, 256), sub_ymm, ?));
91 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
92 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
95 // A vector type of the same width with element type i32. This is used to
96 // create the canonical constant zero node ImmAllZerosV.
97 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
98 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
101 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
102 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
103 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
104 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
105 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
106 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
108 // "x" in v32i8x_info means RC = VR256X
109 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
110 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
111 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
112 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
113 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
114 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
116 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
117 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
118 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
119 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
120 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
121 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
124 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
125 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
127 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
128 X86VectorVTInfo i128> {
129 X86VectorVTInfo info512 = i512;
130 X86VectorVTInfo info256 = i256;
131 X86VectorVTInfo info128 = i128;
134 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
136 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
138 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
140 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
142 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
144 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
147 // This multiclass generates the masking variants from the non-masking
148 // variant. It only provides the assembly pieces for the masking variants.
149 // It assumes custom ISel patterns for masking which can be provided as
150 // template arguments.
151 multiclass AVX512_maskable_custom<bits<8> O, Format F,
153 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
155 string AttSrcAsm, string IntelSrcAsm,
157 list<dag> MaskingPattern,
158 list<dag> ZeroMaskingPattern,
160 string MaskingConstraint = "",
161 InstrItinClass itin = NoItinerary,
162 bit IsCommutable = 0> {
163 let isCommutable = IsCommutable in
164 def NAME: AVX512<O, F, Outs, Ins,
165 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
166 "$dst "#Round#", "#IntelSrcAsm#"}",
169 // Prefer over VMOV*rrk Pat<>
170 let AddedComplexity = 20 in
171 def NAME#k: AVX512<O, F, Outs, MaskingIns,
172 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
173 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
174 MaskingPattern, itin>,
176 // In case of the 3src subclass this is overridden with a let.
177 string Constraints = MaskingConstraint;
179 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
180 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
181 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
182 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
189 // Common base class of AVX512_maskable and AVX512_maskable_3src.
190 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
192 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
194 string AttSrcAsm, string IntelSrcAsm,
195 dag RHS, dag MaskingRHS,
196 SDNode Select = vselect, string Round = "",
197 string MaskingConstraint = "",
198 InstrItinClass itin = NoItinerary,
199 bit IsCommutable = 0> :
200 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
201 AttSrcAsm, IntelSrcAsm,
202 [(set _.RC:$dst, RHS)],
203 [(set _.RC:$dst, MaskingRHS)],
205 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
206 Round, MaskingConstraint, NoItinerary, IsCommutable>;
208 // This multiclass generates the unconditional/non-masking, the masking and
209 // the zero-masking variant of the vector instruction. In the masking case, the
210 // perserved vector elements come from a new dummy input operand tied to $dst.
211 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
212 dag Outs, dag Ins, string OpcodeStr,
213 string AttSrcAsm, string IntelSrcAsm,
214 dag RHS, string Round = "",
215 InstrItinClass itin = NoItinerary,
216 bit IsCommutable = 0> :
217 AVX512_maskable_common<O, F, _, Outs, Ins,
218 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
219 !con((ins _.KRCWM:$mask), Ins),
220 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
221 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
222 Round, "$src0 = $dst", itin, IsCommutable>;
224 // This multiclass generates the unconditional/non-masking, the masking and
225 // the zero-masking variant of the scalar instruction.
226 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
227 dag Outs, dag Ins, string OpcodeStr,
228 string AttSrcAsm, string IntelSrcAsm,
229 dag RHS, string Round = "",
230 InstrItinClass itin = NoItinerary,
231 bit IsCommutable = 0> :
232 AVX512_maskable_common<O, F, _, Outs, Ins,
233 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
234 !con((ins _.KRCWM:$mask), Ins),
235 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
236 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
237 Round, "$src0 = $dst", itin, IsCommutable>;
239 // Similar to AVX512_maskable but in this case one of the source operands
240 // ($src1) is already tied to $dst so we just use that for the preserved
241 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
243 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
244 dag Outs, dag NonTiedIns, string OpcodeStr,
245 string AttSrcAsm, string IntelSrcAsm,
247 AVX512_maskable_common<O, F, _, Outs,
248 !con((ins _.RC:$src1), NonTiedIns),
249 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
250 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
251 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
252 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
255 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
258 string AttSrcAsm, string IntelSrcAsm,
260 AVX512_maskable_custom<O, F, Outs, Ins,
261 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
262 !con((ins _.KRCWM:$mask), Ins),
263 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
266 // Bitcasts between 512-bit vector types. Return the original type since
267 // no instruction is needed for the conversion
268 let Predicates = [HasAVX512] in {
269 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
270 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
271 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
272 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
273 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
274 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
275 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
276 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
277 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
278 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
279 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
280 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
281 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
282 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
283 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
284 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
285 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
286 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
287 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
288 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
289 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
290 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
291 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
292 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
293 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
296 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
297 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
298 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
299 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
302 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
303 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
304 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
305 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
307 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
308 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
309 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
310 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
313 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
314 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
315 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
318 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
319 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
320 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
321 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
322 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
323 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
324 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
325 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
326 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
328 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
329 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
330 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
332 // Bitcasts between 256-bit vector types. Return the original type since
333 // no instruction is needed for the conversion
334 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
335 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
336 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
337 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
338 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
339 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
341 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
342 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
343 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
345 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
346 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
347 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
348 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
350 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
352 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
353 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
354 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
355 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
356 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
358 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
360 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
362 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
363 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
367 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
370 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
371 isPseudo = 1, Predicates = [HasAVX512] in {
372 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
373 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
376 let Predicates = [HasAVX512] in {
377 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
378 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
379 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
382 //===----------------------------------------------------------------------===//
383 // AVX-512 - VECTOR INSERT
386 multiclass vinsert_for_size_no_alt<int Opcode,
387 X86VectorVTInfo From, X86VectorVTInfo To,
388 PatFrag vinsert_insert,
389 SDNodeXForm INSERT_get_vinsert_imm> {
390 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
391 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
392 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
393 "vinsert" # From.EltTypeName # "x" # From.NumElts #
394 "\t{$src3, $src2, $src1, $dst|"
395 "$dst, $src1, $src2, $src3}",
396 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
397 (From.VT From.RC:$src2),
402 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
403 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
404 "vinsert" # From.EltTypeName # "x" # From.NumElts #
405 "\t{$src3, $src2, $src1, $dst|"
406 "$dst, $src1, $src2, $src3}",
408 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
412 multiclass vinsert_for_size<int Opcode,
413 X86VectorVTInfo From, X86VectorVTInfo To,
414 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
415 PatFrag vinsert_insert,
416 SDNodeXForm INSERT_get_vinsert_imm> :
417 vinsert_for_size_no_alt<Opcode, From, To,
418 vinsert_insert, INSERT_get_vinsert_imm> {
419 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
420 // vinserti32x4. Only add this if 64x2 and friends are not supported
421 // natively via AVX512DQ.
422 let Predicates = [NoDQI] in
423 def : Pat<(vinsert_insert:$ins
424 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
425 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
426 VR512:$src1, From.RC:$src2,
427 (INSERT_get_vinsert_imm VR512:$ins)))>;
430 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
431 ValueType EltVT64, int Opcode256> {
432 defm NAME # "32x4" : vinsert_for_size<Opcode128,
433 X86VectorVTInfo< 4, EltVT32, VR128X>,
434 X86VectorVTInfo<16, EltVT32, VR512>,
435 X86VectorVTInfo< 2, EltVT64, VR128X>,
436 X86VectorVTInfo< 8, EltVT64, VR512>,
438 INSERT_get_vinsert128_imm>;
439 let Predicates = [HasDQI] in
440 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
441 X86VectorVTInfo< 2, EltVT64, VR128X>,
442 X86VectorVTInfo< 8, EltVT64, VR512>,
444 INSERT_get_vinsert128_imm>, VEX_W;
445 defm NAME # "64x4" : vinsert_for_size<Opcode256,
446 X86VectorVTInfo< 4, EltVT64, VR256X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
448 X86VectorVTInfo< 8, EltVT32, VR256>,
449 X86VectorVTInfo<16, EltVT32, VR512>,
451 INSERT_get_vinsert256_imm>, VEX_W;
452 let Predicates = [HasDQI] in
453 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
454 X86VectorVTInfo< 8, EltVT32, VR256X>,
455 X86VectorVTInfo<16, EltVT32, VR512>,
457 INSERT_get_vinsert256_imm>;
460 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
461 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
463 // vinsertps - insert f32 to XMM
464 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
465 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
466 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
467 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
469 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
470 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
472 [(set VR128X:$dst, (X86insertps VR128X:$src1,
473 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
474 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
476 //===----------------------------------------------------------------------===//
477 // AVX-512 VECTOR EXTRACT
480 multiclass vextract_for_size<int Opcode,
481 X86VectorVTInfo From, X86VectorVTInfo To,
482 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
483 PatFrag vextract_extract,
484 SDNodeXForm EXTRACT_get_vextract_imm> {
485 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
486 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
487 (ins VR512:$src1, i8imm:$idx),
488 "vextract" # To.EltTypeName # "x4",
489 "$idx, $src1", "$src1, $idx",
490 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
492 AVX512AIi8Base, EVEX, EVEX_V512;
494 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
495 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
496 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
497 "$dst, $src1, $src2}",
498 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
501 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
503 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
504 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
506 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
508 // A 128/256-bit subvector extract from the first 512-bit vector position is
509 // a subregister copy that needs no instruction.
510 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
512 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
514 // And for the alternative types.
515 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
517 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
519 // Intrinsic call with masking.
520 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
522 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
523 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
524 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
525 VR512:$src1, imm:$idx)>;
527 // Intrinsic call with zero-masking.
528 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
530 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
531 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
532 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
533 VR512:$src1, imm:$idx)>;
535 // Intrinsic call without masking.
536 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
538 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
539 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
540 VR512:$src1, imm:$idx)>;
543 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
544 ValueType EltVT64, int Opcode64> {
545 defm NAME # "32x4" : vextract_for_size<Opcode32,
546 X86VectorVTInfo<16, EltVT32, VR512>,
547 X86VectorVTInfo< 4, EltVT32, VR128X>,
548 X86VectorVTInfo< 8, EltVT64, VR512>,
549 X86VectorVTInfo< 2, EltVT64, VR128X>,
551 EXTRACT_get_vextract128_imm>;
552 defm NAME # "64x4" : vextract_for_size<Opcode64,
553 X86VectorVTInfo< 8, EltVT64, VR512>,
554 X86VectorVTInfo< 4, EltVT64, VR256X>,
555 X86VectorVTInfo<16, EltVT32, VR512>,
556 X86VectorVTInfo< 8, EltVT32, VR256>,
558 EXTRACT_get_vextract256_imm>, VEX_W;
561 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
562 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
564 // A 128-bit subvector insert to the first 512-bit vector position
565 // is a subregister copy that needs no instruction.
566 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
567 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
568 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
570 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
571 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
572 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
574 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
575 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
576 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
578 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
579 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
580 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
583 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
584 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
585 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
586 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
587 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
588 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
589 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
590 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
592 // vextractps - extract 32 bits from XMM
593 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
594 (ins VR128X:$src1, i32i8imm:$src2),
595 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
596 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
599 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
600 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
601 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
602 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
603 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
605 //===---------------------------------------------------------------------===//
608 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
609 ValueType svt, X86VectorVTInfo _> {
610 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
611 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
612 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
616 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
617 (ins _.ScalarMemOp:$src),
618 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
619 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
624 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
625 AVX512VLVectorVTInfo _> {
626 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
629 let Predicates = [HasVLX] in {
630 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
635 let ExeDomain = SSEPackedSingle in {
636 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
637 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
638 let Predicates = [HasVLX] in {
639 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
640 v4f32, v4f32x_info>, EVEX_V128,
641 EVEX_CD8<32, CD8VT1>;
645 let ExeDomain = SSEPackedDouble in {
646 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
647 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
650 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
651 (VBROADCASTSSZm addr:$src)>;
652 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
653 (VBROADCASTSDZm addr:$src)>;
655 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
656 (VBROADCASTSSZm addr:$src)>;
657 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
658 (VBROADCASTSDZm addr:$src)>;
660 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
661 RegisterClass SrcRC, RegisterClass KRC> {
662 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
663 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
664 []>, EVEX, EVEX_V512;
665 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
666 (ins KRC:$mask, SrcRC:$src),
667 !strconcat(OpcodeStr,
668 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
669 []>, EVEX, EVEX_V512, EVEX_KZ;
672 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
673 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
676 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
677 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
679 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
680 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
682 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
683 (VPBROADCASTDrZrr GR32:$src)>;
684 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
685 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
686 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
687 (VPBROADCASTQrZrr GR64:$src)>;
688 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
689 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
691 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
692 (VPBROADCASTDrZrr GR32:$src)>;
693 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
694 (VPBROADCASTQrZrr GR64:$src)>;
696 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
697 (v16i32 immAllZerosV), (i16 GR16:$mask))),
698 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
699 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
700 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
701 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
703 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
704 X86MemOperand x86memop, PatFrag ld_frag,
705 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
707 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
710 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
711 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
713 !strconcat(OpcodeStr,
714 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
716 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
719 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
720 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
722 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
723 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
725 !strconcat(OpcodeStr,
726 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
727 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
728 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
732 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
733 loadi32, VR512, v16i32, v4i32, VK16WM>,
734 EVEX_V512, EVEX_CD8<32, CD8VT1>;
735 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
736 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
737 EVEX_CD8<64, CD8VT1>;
739 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
740 X86MemOperand x86memop, PatFrag ld_frag,
743 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
744 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
746 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
748 !strconcat(OpcodeStr,
749 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
754 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
755 i128mem, loadv2i64, VK16WM>,
756 EVEX_V512, EVEX_CD8<32, CD8VT4>;
757 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
758 i256mem, loadv4i64, VK16WM>, VEX_W,
759 EVEX_V512, EVEX_CD8<64, CD8VT4>;
761 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
762 (VPBROADCASTDZrr VR128X:$src)>;
763 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
764 (VPBROADCASTQZrr VR128X:$src)>;
766 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
767 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
768 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
769 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
771 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
772 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
773 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
774 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
776 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
777 (VBROADCASTSSZr VR128X:$src)>;
778 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
779 (VBROADCASTSDZr VR128X:$src)>;
781 // Provide fallback in case the load node that is used in the patterns above
782 // is used by additional users, which prevents the pattern selection.
783 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
784 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
785 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
786 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
789 let Predicates = [HasAVX512] in {
790 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
792 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
793 addr:$src)), sub_ymm)>;
795 //===----------------------------------------------------------------------===//
796 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
799 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
801 let Predicates = [HasCDI] in
802 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
803 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
804 []>, EVEX, EVEX_V512;
806 let Predicates = [HasCDI, HasVLX] in {
807 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
808 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
809 []>, EVEX, EVEX_V128;
810 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
811 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
812 []>, EVEX, EVEX_V256;
816 let Predicates = [HasCDI] in {
817 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
819 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
823 //===----------------------------------------------------------------------===//
826 // -- immediate form --
827 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
829 let ExeDomain = _.ExeDomain in {
830 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
831 (ins _.RC:$src1, i8imm:$src2),
832 !strconcat(OpcodeStr,
833 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
835 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
837 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
838 (ins _.MemOp:$src1, i8imm:$src2),
839 !strconcat(OpcodeStr,
840 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
842 (_.VT (OpNode (_.MemOpFrag addr:$src1),
844 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
848 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
849 X86VectorVTInfo Ctrl> :
850 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
851 let ExeDomain = _.ExeDomain in {
852 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
853 (ins _.RC:$src1, _.RC:$src2),
854 !strconcat("vpermil" # _.Suffix,
855 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
857 (_.VT (X86VPermilpv _.RC:$src1,
858 (Ctrl.VT Ctrl.RC:$src2))))]>,
860 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
861 (ins _.RC:$src1, Ctrl.MemOp:$src2),
862 !strconcat("vpermil" # _.Suffix,
863 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
865 (_.VT (X86VPermilpv _.RC:$src1,
866 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
871 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
873 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
876 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
878 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
881 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
882 (VPERMILPSZri VR512:$src1, imm:$imm)>;
883 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
884 (VPERMILPDZri VR512:$src1, imm:$imm)>;
886 // -- VPERM - register form --
887 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
888 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
890 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
891 (ins RC:$src1, RC:$src2),
892 !strconcat(OpcodeStr,
893 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
895 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
897 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
898 (ins RC:$src1, x86memop:$src2),
899 !strconcat(OpcodeStr,
900 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
902 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
906 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
907 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
908 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
909 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
910 let ExeDomain = SSEPackedSingle in
911 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
912 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
913 let ExeDomain = SSEPackedDouble in
914 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
915 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
917 // -- VPERM2I - 3 source operands form --
918 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
919 PatFrag mem_frag, X86MemOperand x86memop,
920 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
921 let Constraints = "$src1 = $dst" in {
922 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
923 (ins RC:$src1, RC:$src2, RC:$src3),
924 !strconcat(OpcodeStr,
925 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
927 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
930 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
931 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
932 !strconcat(OpcodeStr,
933 "\t{$src3, $src2, $dst {${mask}}|"
934 "$dst {${mask}}, $src2, $src3}"),
935 [(set RC:$dst, (OpVT (vselect KRC:$mask,
936 (OpNode RC:$src1, RC:$src2,
941 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
942 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
943 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
944 !strconcat(OpcodeStr,
945 "\t{$src3, $src2, $dst {${mask}} {z} |",
946 "$dst {${mask}} {z}, $src2, $src3}"),
947 [(set RC:$dst, (OpVT (vselect KRC:$mask,
948 (OpNode RC:$src1, RC:$src2,
951 (v16i32 immAllZerosV))))))]>,
954 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
955 (ins RC:$src1, RC:$src2, x86memop:$src3),
956 !strconcat(OpcodeStr,
957 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
959 (OpVT (OpNode RC:$src1, RC:$src2,
960 (mem_frag addr:$src3))))]>, EVEX_4V;
962 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
963 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
964 !strconcat(OpcodeStr,
965 "\t{$src3, $src2, $dst {${mask}}|"
966 "$dst {${mask}}, $src2, $src3}"),
968 (OpVT (vselect KRC:$mask,
969 (OpNode RC:$src1, RC:$src2,
970 (mem_frag addr:$src3)),
974 let AddedComplexity = 10 in // Prefer over the rrkz variant
975 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
976 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
977 !strconcat(OpcodeStr,
978 "\t{$src3, $src2, $dst {${mask}} {z}|"
979 "$dst {${mask}} {z}, $src2, $src3}"),
981 (OpVT (vselect KRC:$mask,
982 (OpNode RC:$src1, RC:$src2,
983 (mem_frag addr:$src3)),
985 (v16i32 immAllZerosV))))))]>,
989 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
990 i512mem, X86VPermiv3, v16i32, VK16WM>,
991 EVEX_V512, EVEX_CD8<32, CD8VF>;
992 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
993 i512mem, X86VPermiv3, v8i64, VK8WM>,
994 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
995 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
996 i512mem, X86VPermiv3, v16f32, VK16WM>,
997 EVEX_V512, EVEX_CD8<32, CD8VF>;
998 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
999 i512mem, X86VPermiv3, v8f64, VK8WM>,
1000 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1002 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1003 PatFrag mem_frag, X86MemOperand x86memop,
1004 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1005 ValueType MaskVT, RegisterClass MRC> :
1006 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1008 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1009 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1010 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1012 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1013 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1014 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1015 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1018 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1019 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1020 EVEX_V512, EVEX_CD8<32, CD8VF>;
1021 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1022 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1023 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1024 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1025 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1026 EVEX_V512, EVEX_CD8<32, CD8VF>;
1027 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1028 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1029 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1031 //===----------------------------------------------------------------------===//
1032 // AVX-512 - BLEND using mask
1034 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1035 RegisterClass KRC, RegisterClass RC,
1036 X86MemOperand x86memop, PatFrag mem_frag,
1037 SDNode OpNode, ValueType vt> {
1038 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1039 (ins KRC:$mask, RC:$src1, RC:$src2),
1040 !strconcat(OpcodeStr,
1041 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1042 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1043 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1045 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1046 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1047 !strconcat(OpcodeStr,
1048 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1049 []>, EVEX_4V, EVEX_K;
1052 let ExeDomain = SSEPackedSingle in
1053 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1054 VK16WM, VR512, f512mem,
1055 memopv16f32, vselect, v16f32>,
1056 EVEX_CD8<32, CD8VF>, EVEX_V512;
1057 let ExeDomain = SSEPackedDouble in
1058 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1059 VK8WM, VR512, f512mem,
1060 memopv8f64, vselect, v8f64>,
1061 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1063 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1064 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1065 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1066 VR512:$src1, VR512:$src2)>;
1068 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1069 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1070 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1071 VR512:$src1, VR512:$src2)>;
1073 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1074 VK16WM, VR512, f512mem,
1075 memopv16i32, vselect, v16i32>,
1076 EVEX_CD8<32, CD8VF>, EVEX_V512;
1078 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1079 VK8WM, VR512, f512mem,
1080 memopv8i64, vselect, v8i64>,
1081 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1083 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1084 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1085 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1086 VR512:$src1, VR512:$src2)>;
1088 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1089 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1090 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1091 VR512:$src1, VR512:$src2)>;
1093 let Predicates = [HasAVX512] in {
1094 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1095 (v8f32 VR256X:$src2))),
1097 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1098 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1099 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1101 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1102 (v8i32 VR256X:$src2))),
1104 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1105 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1106 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1108 //===----------------------------------------------------------------------===//
1109 // Compare Instructions
1110 //===----------------------------------------------------------------------===//
1112 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1113 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1114 Operand CC, SDNode OpNode, ValueType VT,
1115 PatFrag ld_frag, string asm, string asm_alt> {
1116 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1117 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1118 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1119 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1120 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1121 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1122 [(set VK1:$dst, (OpNode (VT RC:$src1),
1123 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1124 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1125 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1126 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1127 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1128 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1129 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1130 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1134 let Predicates = [HasAVX512] in {
1135 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1136 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1137 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1139 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1140 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1141 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1145 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1146 X86VectorVTInfo _> {
1147 def rr : AVX512BI<opc, MRMSrcReg,
1148 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1149 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1150 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1151 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1153 def rm : AVX512BI<opc, MRMSrcMem,
1154 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1155 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1156 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1157 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1158 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1159 def rrk : AVX512BI<opc, MRMSrcReg,
1160 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1161 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1162 "$dst {${mask}}, $src1, $src2}"),
1163 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1164 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1165 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1167 def rmk : AVX512BI<opc, MRMSrcMem,
1168 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1169 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1170 "$dst {${mask}}, $src1, $src2}"),
1171 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1172 (OpNode (_.VT _.RC:$src1),
1174 (_.LdFrag addr:$src2))))))],
1175 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1178 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1179 X86VectorVTInfo _> :
1180 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1181 let mayLoad = 1 in {
1182 def rmb : AVX512BI<opc, MRMSrcMem,
1183 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1184 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1185 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1186 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1187 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1188 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1189 def rmbk : AVX512BI<opc, MRMSrcMem,
1190 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1191 _.ScalarMemOp:$src2),
1192 !strconcat(OpcodeStr,
1193 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1194 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1195 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1196 (OpNode (_.VT _.RC:$src1),
1198 (_.ScalarLdFrag addr:$src2)))))],
1199 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1203 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1204 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1205 let Predicates = [prd] in
1206 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1209 let Predicates = [prd, HasVLX] in {
1210 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1212 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1217 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1218 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1220 let Predicates = [prd] in
1221 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1224 let Predicates = [prd, HasVLX] in {
1225 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1227 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1232 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1233 avx512vl_i8_info, HasBWI>,
1236 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1237 avx512vl_i16_info, HasBWI>,
1238 EVEX_CD8<16, CD8VF>;
1240 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1241 avx512vl_i32_info, HasAVX512>,
1242 EVEX_CD8<32, CD8VF>;
1244 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1245 avx512vl_i64_info, HasAVX512>,
1246 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1248 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1249 avx512vl_i8_info, HasBWI>,
1252 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1253 avx512vl_i16_info, HasBWI>,
1254 EVEX_CD8<16, CD8VF>;
1256 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1257 avx512vl_i32_info, HasAVX512>,
1258 EVEX_CD8<32, CD8VF>;
1260 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1261 avx512vl_i64_info, HasAVX512>,
1262 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1264 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1265 (COPY_TO_REGCLASS (VPCMPGTDZrr
1266 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1267 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1269 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1270 (COPY_TO_REGCLASS (VPCMPEQDZrr
1271 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1272 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1274 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1275 X86VectorVTInfo _> {
1276 def rri : AVX512AIi8<opc, MRMSrcReg,
1277 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1278 !strconcat("vpcmp${cc}", Suffix,
1279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1280 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1282 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1284 def rmi : AVX512AIi8<opc, MRMSrcMem,
1285 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1286 !strconcat("vpcmp${cc}", Suffix,
1287 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1288 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1289 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1291 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1292 def rrik : AVX512AIi8<opc, MRMSrcReg,
1293 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1295 !strconcat("vpcmp${cc}", Suffix,
1296 "\t{$src2, $src1, $dst {${mask}}|",
1297 "$dst {${mask}}, $src1, $src2}"),
1298 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1299 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1301 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1303 def rmik : AVX512AIi8<opc, MRMSrcMem,
1304 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1306 !strconcat("vpcmp${cc}", Suffix,
1307 "\t{$src2, $src1, $dst {${mask}}|",
1308 "$dst {${mask}}, $src1, $src2}"),
1309 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1310 (OpNode (_.VT _.RC:$src1),
1311 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1313 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1315 // Accept explicit immediate argument form instead of comparison code.
1316 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1317 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1318 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1319 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1320 "$dst, $src1, $src2, $cc}"),
1321 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1322 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1323 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1324 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1325 "$dst, $src1, $src2, $cc}"),
1326 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1327 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1328 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1330 !strconcat("vpcmp", Suffix,
1331 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1332 "$dst {${mask}}, $src1, $src2, $cc}"),
1333 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1334 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1335 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1337 !strconcat("vpcmp", Suffix,
1338 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1339 "$dst {${mask}}, $src1, $src2, $cc}"),
1340 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1344 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1345 X86VectorVTInfo _> :
1346 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1347 let mayLoad = 1 in {
1348 def rmib : AVX512AIi8<opc, MRMSrcMem,
1349 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1351 !strconcat("vpcmp${cc}", Suffix,
1352 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1353 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1354 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1355 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1357 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1358 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1359 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1360 _.ScalarMemOp:$src2, AVXCC:$cc),
1361 !strconcat("vpcmp${cc}", Suffix,
1362 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1363 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1364 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1365 (OpNode (_.VT _.RC:$src1),
1366 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1368 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1371 // Accept explicit immediate argument form instead of comparison code.
1372 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1373 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1374 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1376 !strconcat("vpcmp", Suffix,
1377 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1378 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1379 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1380 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1381 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1382 _.ScalarMemOp:$src2, i8imm:$cc),
1383 !strconcat("vpcmp", Suffix,
1384 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1385 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1386 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1390 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1391 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1392 let Predicates = [prd] in
1393 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1395 let Predicates = [prd, HasVLX] in {
1396 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1397 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1401 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1402 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1403 let Predicates = [prd] in
1404 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1407 let Predicates = [prd, HasVLX] in {
1408 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1410 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1415 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1416 HasBWI>, EVEX_CD8<8, CD8VF>;
1417 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1418 HasBWI>, EVEX_CD8<8, CD8VF>;
1420 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1421 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1422 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1423 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1425 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1426 HasAVX512>, EVEX_CD8<32, CD8VF>;
1427 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1428 HasAVX512>, EVEX_CD8<32, CD8VF>;
1430 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1431 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1432 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1433 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1435 // avx512_cmp_packed - compare packed instructions
1436 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1437 X86MemOperand x86memop, ValueType vt,
1438 string suffix, Domain d> {
1439 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1440 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1441 !strconcat("vcmp${cc}", suffix,
1442 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1443 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1444 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1445 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1446 !strconcat("vcmp${cc}", suffix,
1447 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1449 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1450 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1451 !strconcat("vcmp${cc}", suffix,
1452 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1454 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1456 // Accept explicit immediate argument form instead of comparison code.
1457 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1458 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1459 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1460 !strconcat("vcmp", suffix,
1461 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1462 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1463 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1464 !strconcat("vcmp", suffix,
1465 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1469 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1470 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1471 EVEX_CD8<32, CD8VF>;
1472 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1473 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1474 EVEX_CD8<64, CD8VF>;
1476 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1477 (COPY_TO_REGCLASS (VCMPPSZrri
1478 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1479 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1481 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1482 (COPY_TO_REGCLASS (VPCMPDZrri
1483 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1484 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1486 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1487 (COPY_TO_REGCLASS (VPCMPUDZrri
1488 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1489 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1492 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1493 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1495 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1496 (I8Imm imm:$cc)), GR16)>;
1498 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1499 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1501 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1502 (I8Imm imm:$cc)), GR8)>;
1504 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1505 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1507 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1508 (I8Imm imm:$cc)), GR16)>;
1510 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1511 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1513 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1514 (I8Imm imm:$cc)), GR8)>;
1516 // Mask register copy, including
1517 // - copy between mask registers
1518 // - load/store mask registers
1519 // - copy from GPR to mask register and vice versa
1521 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1522 string OpcodeStr, RegisterClass KRC,
1523 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1524 let hasSideEffects = 0 in {
1525 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1526 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1528 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1529 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1530 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1532 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1533 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1537 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1539 RegisterClass KRC, RegisterClass GRC> {
1540 let hasSideEffects = 0 in {
1541 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1543 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1544 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1548 let Predicates = [HasDQI] in
1549 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1551 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1554 let Predicates = [HasAVX512] in
1555 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1557 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1560 let Predicates = [HasBWI] in {
1561 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1562 i32mem>, VEX, PD, VEX_W;
1563 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1567 let Predicates = [HasBWI] in {
1568 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1569 i64mem>, VEX, PS, VEX_W;
1570 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1574 // GR from/to mask register
1575 let Predicates = [HasDQI] in {
1576 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1577 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1578 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1579 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1581 let Predicates = [HasAVX512] in {
1582 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1583 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1584 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1585 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1587 let Predicates = [HasBWI] in {
1588 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1589 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1591 let Predicates = [HasBWI] in {
1592 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1593 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1597 let Predicates = [HasDQI] in {
1598 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1599 (KMOVBmk addr:$dst, VK8:$src)>;
1601 let Predicates = [HasAVX512] in {
1602 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1603 (KMOVWmk addr:$dst, VK16:$src)>;
1604 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1605 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1606 def : Pat<(i1 (load addr:$src)),
1607 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1608 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1609 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1611 let Predicates = [HasBWI] in {
1612 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1613 (KMOVDmk addr:$dst, VK32:$src)>;
1615 let Predicates = [HasBWI] in {
1616 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1617 (KMOVQmk addr:$dst, VK64:$src)>;
1620 let Predicates = [HasAVX512] in {
1621 def : Pat<(i1 (trunc (i64 GR64:$src))),
1622 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1625 def : Pat<(i1 (trunc (i32 GR32:$src))),
1626 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1628 def : Pat<(i1 (trunc (i8 GR8:$src))),
1630 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1632 def : Pat<(i1 (trunc (i16 GR16:$src))),
1634 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1637 def : Pat<(i32 (zext VK1:$src)),
1638 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1639 def : Pat<(i8 (zext VK1:$src)),
1642 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1643 def : Pat<(i64 (zext VK1:$src)),
1644 (AND64ri8 (SUBREG_TO_REG (i64 0),
1645 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1646 def : Pat<(i16 (zext VK1:$src)),
1648 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1650 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1651 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1652 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1653 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1655 let Predicates = [HasBWI] in {
1656 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1657 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1658 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1659 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1663 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1664 let Predicates = [HasAVX512] in {
1665 // GR from/to 8-bit mask without native support
1666 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1668 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1670 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1672 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1675 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1676 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1677 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1678 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1680 let Predicates = [HasBWI] in {
1681 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1682 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1683 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1684 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1687 // Mask unary operation
1689 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1690 RegisterClass KRC, SDPatternOperator OpNode,
1692 let Predicates = [prd] in
1693 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1694 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1695 [(set KRC:$dst, (OpNode KRC:$src))]>;
1698 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1699 SDPatternOperator OpNode> {
1700 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1702 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1703 HasAVX512>, VEX, PS;
1704 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1705 HasBWI>, VEX, PD, VEX_W;
1706 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1707 HasBWI>, VEX, PS, VEX_W;
1710 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1712 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1713 let Predicates = [HasAVX512] in
1714 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1716 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1717 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1719 defm : avx512_mask_unop_int<"knot", "KNOT">;
1721 let Predicates = [HasDQI] in
1722 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1723 let Predicates = [HasAVX512] in
1724 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1725 let Predicates = [HasBWI] in
1726 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1727 let Predicates = [HasBWI] in
1728 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1730 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1731 let Predicates = [HasAVX512] in {
1732 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1733 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1735 def : Pat<(not VK8:$src),
1737 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1740 // Mask binary operation
1741 // - KAND, KANDN, KOR, KXNOR, KXOR
1742 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1743 RegisterClass KRC, SDPatternOperator OpNode,
1745 let Predicates = [prd] in
1746 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1747 !strconcat(OpcodeStr,
1748 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1749 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1752 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1753 SDPatternOperator OpNode> {
1754 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1755 HasDQI>, VEX_4V, VEX_L, PD;
1756 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1757 HasAVX512>, VEX_4V, VEX_L, PS;
1758 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1759 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1760 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1761 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1764 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1765 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1767 let isCommutable = 1 in {
1768 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1769 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1770 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1771 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1773 let isCommutable = 0 in
1774 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1776 def : Pat<(xor VK1:$src1, VK1:$src2),
1777 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1778 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1780 def : Pat<(or VK1:$src1, VK1:$src2),
1781 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1782 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1784 def : Pat<(and VK1:$src1, VK1:$src2),
1785 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1786 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1788 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1789 let Predicates = [HasAVX512] in
1790 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1791 (i16 GR16:$src1), (i16 GR16:$src2)),
1792 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1793 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1794 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1797 defm : avx512_mask_binop_int<"kand", "KAND">;
1798 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1799 defm : avx512_mask_binop_int<"kor", "KOR">;
1800 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1801 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1803 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1804 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1805 let Predicates = [HasAVX512] in
1806 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1808 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1809 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1812 defm : avx512_binop_pat<and, KANDWrr>;
1813 defm : avx512_binop_pat<andn, KANDNWrr>;
1814 defm : avx512_binop_pat<or, KORWrr>;
1815 defm : avx512_binop_pat<xnor, KXNORWrr>;
1816 defm : avx512_binop_pat<xor, KXORWrr>;
1819 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1820 RegisterClass KRC> {
1821 let Predicates = [HasAVX512] in
1822 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1823 !strconcat(OpcodeStr,
1824 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1827 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1828 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1832 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1833 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1834 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1835 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1838 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1839 let Predicates = [HasAVX512] in
1840 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1841 (i16 GR16:$src1), (i16 GR16:$src2)),
1842 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1843 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1844 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1846 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1849 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1851 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1852 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1853 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1854 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1857 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1858 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1862 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1864 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1865 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1866 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1869 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1871 let Predicates = [HasAVX512] in
1872 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1873 !strconcat(OpcodeStr,
1874 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1875 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1878 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1880 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1884 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1885 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1887 // Mask setting all 0s or 1s
1888 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1889 let Predicates = [HasAVX512] in
1890 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1891 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1892 [(set KRC:$dst, (VT Val))]>;
1895 multiclass avx512_mask_setop_w<PatFrag Val> {
1896 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1897 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1900 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1901 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1903 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1904 let Predicates = [HasAVX512] in {
1905 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1906 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1907 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1908 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1909 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1911 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1912 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1914 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1915 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1917 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1918 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1920 let Predicates = [HasVLX] in {
1921 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1922 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1923 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1924 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1925 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1926 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1927 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1928 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1931 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1932 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1934 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1935 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1936 //===----------------------------------------------------------------------===//
1937 // AVX-512 - Aligned and unaligned load and store
1940 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1941 RegisterClass KRC, RegisterClass RC,
1942 ValueType vt, ValueType zvt, X86MemOperand memop,
1943 Domain d, bit IsReMaterializable = 1> {
1944 let hasSideEffects = 0 in {
1945 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1946 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1948 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1949 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1950 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1952 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1953 SchedRW = [WriteLoad] in
1954 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1956 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1959 let AddedComplexity = 20 in {
1960 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1961 let hasSideEffects = 0 in
1962 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1963 (ins RC:$src0, KRC:$mask, RC:$src1),
1964 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1965 "${dst} {${mask}}, $src1}"),
1966 [(set RC:$dst, (vt (vselect KRC:$mask,
1970 let mayLoad = 1, SchedRW = [WriteLoad] in
1971 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1972 (ins RC:$src0, KRC:$mask, memop:$src1),
1973 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1974 "${dst} {${mask}}, $src1}"),
1977 (vt (bitconvert (ld_frag addr:$src1))),
1981 let mayLoad = 1, SchedRW = [WriteLoad] in
1982 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1983 (ins KRC:$mask, memop:$src),
1984 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1985 "${dst} {${mask}} {z}, $src}"),
1988 (vt (bitconvert (ld_frag addr:$src))),
1989 (vt (bitconvert (zvt immAllZerosV))))))],
1994 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1995 string elty, string elsz, string vsz512,
1996 string vsz256, string vsz128, Domain d,
1997 Predicate prd, bit IsReMaterializable = 1> {
1998 let Predicates = [prd] in
1999 defm Z : avx512_load<opc, OpcodeStr,
2000 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2001 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2002 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2003 !cast<X86MemOperand>(elty##"512mem"), d,
2004 IsReMaterializable>, EVEX_V512;
2006 let Predicates = [prd, HasVLX] in {
2007 defm Z256 : avx512_load<opc, OpcodeStr,
2008 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2009 "v"##vsz256##elty##elsz, "v4i64")),
2010 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2011 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2012 !cast<X86MemOperand>(elty##"256mem"), d,
2013 IsReMaterializable>, EVEX_V256;
2015 defm Z128 : avx512_load<opc, OpcodeStr,
2016 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2017 "v"##vsz128##elty##elsz, "v2i64")),
2018 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2019 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2020 !cast<X86MemOperand>(elty##"128mem"), d,
2021 IsReMaterializable>, EVEX_V128;
2026 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2027 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2028 X86MemOperand memop, Domain d> {
2029 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2030 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2031 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2033 let Constraints = "$src1 = $dst" in
2034 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2035 (ins RC:$src1, KRC:$mask, RC:$src2),
2036 !strconcat(OpcodeStr,
2037 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2039 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2040 (ins KRC:$mask, RC:$src),
2041 !strconcat(OpcodeStr,
2042 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2043 [], d>, EVEX, EVEX_KZ;
2045 let mayStore = 1 in {
2046 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2047 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2048 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2049 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2050 (ins memop:$dst, KRC:$mask, RC:$src),
2051 !strconcat(OpcodeStr,
2052 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2053 [], d>, EVEX, EVEX_K;
2058 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2059 string st_suff_512, string st_suff_256,
2060 string st_suff_128, string elty, string elsz,
2061 string vsz512, string vsz256, string vsz128,
2062 Domain d, Predicate prd> {
2063 let Predicates = [prd] in
2064 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2065 !cast<ValueType>("v"##vsz512##elty##elsz),
2066 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2067 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2069 let Predicates = [prd, HasVLX] in {
2070 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2071 !cast<ValueType>("v"##vsz256##elty##elsz),
2072 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2073 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2075 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2076 !cast<ValueType>("v"##vsz128##elty##elsz),
2077 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2078 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2082 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2083 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2084 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2085 "512", "256", "", "f", "32", "16", "8", "4",
2086 SSEPackedSingle, HasAVX512>,
2087 PS, EVEX_CD8<32, CD8VF>;
2089 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2090 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2091 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2092 "512", "256", "", "f", "64", "8", "4", "2",
2093 SSEPackedDouble, HasAVX512>,
2094 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2096 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2097 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2098 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2099 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2100 PS, EVEX_CD8<32, CD8VF>;
2102 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2103 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2104 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2105 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2106 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2108 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2109 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2110 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2112 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2113 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2114 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2116 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2118 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2120 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2122 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2125 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2126 "16", "8", "4", SSEPackedInt, HasAVX512>,
2127 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2128 "512", "256", "", "i", "32", "16", "8", "4",
2129 SSEPackedInt, HasAVX512>,
2130 PD, EVEX_CD8<32, CD8VF>;
2132 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2133 "8", "4", "2", SSEPackedInt, HasAVX512>,
2134 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2135 "512", "256", "", "i", "64", "8", "4", "2",
2136 SSEPackedInt, HasAVX512>,
2137 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2139 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2140 "64", "32", "16", SSEPackedInt, HasBWI>,
2141 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2142 "i", "8", "64", "32", "16", SSEPackedInt,
2143 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2145 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2146 "32", "16", "8", SSEPackedInt, HasBWI>,
2147 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2148 "i", "16", "32", "16", "8", SSEPackedInt,
2149 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2151 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2152 "16", "8", "4", SSEPackedInt, HasAVX512>,
2153 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2154 "i", "32", "16", "8", "4", SSEPackedInt,
2155 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2157 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2158 "8", "4", "2", SSEPackedInt, HasAVX512>,
2159 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2160 "i", "64", "8", "4", "2", SSEPackedInt,
2161 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2163 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2164 (v16i32 immAllZerosV), GR16:$mask)),
2165 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2167 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2168 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2169 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2171 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2173 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2175 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2177 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2180 let AddedComplexity = 20 in {
2181 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2182 (bc_v8i64 (v16i32 immAllZerosV)))),
2183 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2185 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2186 (v8i64 VR512:$src))),
2187 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2190 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2191 (v16i32 immAllZerosV))),
2192 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2194 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2195 (v16i32 VR512:$src))),
2196 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2199 // Move Int Doubleword to Packed Double Int
2201 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2202 "vmovd\t{$src, $dst|$dst, $src}",
2204 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2206 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2207 "vmovd\t{$src, $dst|$dst, $src}",
2209 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2210 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2211 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2212 "vmovq\t{$src, $dst|$dst, $src}",
2214 (v2i64 (scalar_to_vector GR64:$src)))],
2215 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2216 let isCodeGenOnly = 1 in {
2217 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2218 "vmovq\t{$src, $dst|$dst, $src}",
2219 [(set FR64:$dst, (bitconvert GR64:$src))],
2220 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2221 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2222 "vmovq\t{$src, $dst|$dst, $src}",
2223 [(set GR64:$dst, (bitconvert FR64:$src))],
2224 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2226 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2227 "vmovq\t{$src, $dst|$dst, $src}",
2228 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2229 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2230 EVEX_CD8<64, CD8VT1>;
2232 // Move Int Doubleword to Single Scalar
2234 let isCodeGenOnly = 1 in {
2235 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2236 "vmovd\t{$src, $dst|$dst, $src}",
2237 [(set FR32X:$dst, (bitconvert GR32:$src))],
2238 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2240 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2241 "vmovd\t{$src, $dst|$dst, $src}",
2242 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2243 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2246 // Move doubleword from xmm register to r/m32
2248 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2249 "vmovd\t{$src, $dst|$dst, $src}",
2250 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2251 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2253 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2254 (ins i32mem:$dst, VR128X:$src),
2255 "vmovd\t{$src, $dst|$dst, $src}",
2256 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2257 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2258 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2260 // Move quadword from xmm1 register to r/m64
2262 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2263 "vmovq\t{$src, $dst|$dst, $src}",
2264 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2266 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2267 Requires<[HasAVX512, In64BitMode]>;
2269 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2270 (ins i64mem:$dst, VR128X:$src),
2271 "vmovq\t{$src, $dst|$dst, $src}",
2272 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2273 addr:$dst)], IIC_SSE_MOVDQ>,
2274 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2275 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2277 // Move Scalar Single to Double Int
2279 let isCodeGenOnly = 1 in {
2280 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2282 "vmovd\t{$src, $dst|$dst, $src}",
2283 [(set GR32:$dst, (bitconvert FR32X:$src))],
2284 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2285 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2286 (ins i32mem:$dst, FR32X:$src),
2287 "vmovd\t{$src, $dst|$dst, $src}",
2288 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2289 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2292 // Move Quadword Int to Packed Quadword Int
2294 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2296 "vmovq\t{$src, $dst|$dst, $src}",
2298 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2299 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2301 //===----------------------------------------------------------------------===//
2302 // AVX-512 MOVSS, MOVSD
2303 //===----------------------------------------------------------------------===//
2305 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2306 SDNode OpNode, ValueType vt,
2307 X86MemOperand x86memop, PatFrag mem_pat> {
2308 let hasSideEffects = 0 in {
2309 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2310 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2311 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2312 (scalar_to_vector RC:$src2))))],
2313 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2314 let Constraints = "$src1 = $dst" in
2315 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2316 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2318 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2319 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2320 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2321 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2322 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2324 let mayStore = 1 in {
2325 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2326 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2327 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2329 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2330 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2331 [], IIC_SSE_MOV_S_MR>,
2332 EVEX, VEX_LIG, EVEX_K;
2334 } //hasSideEffects = 0
2337 let ExeDomain = SSEPackedSingle in
2338 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2339 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2341 let ExeDomain = SSEPackedDouble in
2342 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2343 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2345 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2346 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2347 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2349 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2350 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2351 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2353 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2354 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2355 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2357 // For the disassembler
2358 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2359 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2360 (ins VR128X:$src1, FR32X:$src2),
2361 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2363 XS, EVEX_4V, VEX_LIG;
2364 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2365 (ins VR128X:$src1, FR64X:$src2),
2366 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2368 XD, EVEX_4V, VEX_LIG, VEX_W;
2371 let Predicates = [HasAVX512] in {
2372 let AddedComplexity = 15 in {
2373 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2374 // MOVS{S,D} to the lower bits.
2375 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2376 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2377 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2378 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2379 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2380 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2381 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2382 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2384 // Move low f32 and clear high bits.
2385 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2386 (SUBREG_TO_REG (i32 0),
2387 (VMOVSSZrr (v4f32 (V_SET0)),
2388 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2389 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2390 (SUBREG_TO_REG (i32 0),
2391 (VMOVSSZrr (v4i32 (V_SET0)),
2392 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2395 let AddedComplexity = 20 in {
2396 // MOVSSrm zeros the high parts of the register; represent this
2397 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2398 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2399 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2400 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2401 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2402 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2403 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2405 // MOVSDrm zeros the high parts of the register; represent this
2406 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2407 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2408 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2409 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2410 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2411 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2412 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2413 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2414 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2415 def : Pat<(v2f64 (X86vzload addr:$src)),
2416 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2418 // Represent the same patterns above but in the form they appear for
2420 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2421 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2422 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2423 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2424 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2425 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2426 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2427 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2428 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2430 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2431 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2432 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2433 FR32X:$src)), sub_xmm)>;
2434 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2435 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2436 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2437 FR64X:$src)), sub_xmm)>;
2438 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2439 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2440 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2442 // Move low f64 and clear high bits.
2443 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2444 (SUBREG_TO_REG (i32 0),
2445 (VMOVSDZrr (v2f64 (V_SET0)),
2446 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2448 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2449 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2450 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2452 // Extract and store.
2453 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2455 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2456 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2458 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2460 // Shuffle with VMOVSS
2461 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2462 (VMOVSSZrr (v4i32 VR128X:$src1),
2463 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2464 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2465 (VMOVSSZrr (v4f32 VR128X:$src1),
2466 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2469 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2470 (SUBREG_TO_REG (i32 0),
2471 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2472 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2474 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2475 (SUBREG_TO_REG (i32 0),
2476 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2477 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2480 // Shuffle with VMOVSD
2481 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2482 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2483 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2484 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2485 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2486 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2487 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2488 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2491 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2492 (SUBREG_TO_REG (i32 0),
2493 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2494 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2496 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2497 (SUBREG_TO_REG (i32 0),
2498 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2499 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2502 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2503 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2504 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2505 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2506 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2507 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2508 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2509 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2512 let AddedComplexity = 15 in
2513 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2515 "vmovq\t{$src, $dst|$dst, $src}",
2516 [(set VR128X:$dst, (v2i64 (X86vzmovl
2517 (v2i64 VR128X:$src))))],
2518 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2520 let AddedComplexity = 20 in
2521 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2523 "vmovq\t{$src, $dst|$dst, $src}",
2524 [(set VR128X:$dst, (v2i64 (X86vzmovl
2525 (loadv2i64 addr:$src))))],
2526 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2527 EVEX_CD8<8, CD8VT8>;
2529 let Predicates = [HasAVX512] in {
2530 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2531 let AddedComplexity = 20 in {
2532 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2533 (VMOVDI2PDIZrm addr:$src)>;
2534 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2535 (VMOV64toPQIZrr GR64:$src)>;
2536 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2537 (VMOVDI2PDIZrr GR32:$src)>;
2539 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2540 (VMOVDI2PDIZrm addr:$src)>;
2541 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2542 (VMOVDI2PDIZrm addr:$src)>;
2543 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2544 (VMOVZPQILo2PQIZrm addr:$src)>;
2545 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2546 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2547 def : Pat<(v2i64 (X86vzload addr:$src)),
2548 (VMOVZPQILo2PQIZrm addr:$src)>;
2551 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2552 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2553 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2554 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2555 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2556 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2557 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2560 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2561 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2563 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2564 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2566 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2567 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2569 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2570 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2572 //===----------------------------------------------------------------------===//
2573 // AVX-512 - Non-temporals
2574 //===----------------------------------------------------------------------===//
2575 let SchedRW = [WriteLoad] in {
2576 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2577 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2578 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2579 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2580 EVEX_CD8<64, CD8VF>;
2582 let Predicates = [HasAVX512, HasVLX] in {
2583 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2585 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2586 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2587 EVEX_CD8<64, CD8VF>;
2589 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2591 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2592 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2593 EVEX_CD8<64, CD8VF>;
2597 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2598 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2599 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2600 let SchedRW = [WriteStore], mayStore = 1,
2601 AddedComplexity = 400 in
2602 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2603 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2604 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2607 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2608 string elty, string elsz, string vsz512,
2609 string vsz256, string vsz128, Domain d,
2610 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2611 let Predicates = [prd] in
2612 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2613 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2614 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2617 let Predicates = [prd, HasVLX] in {
2618 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2619 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2620 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2623 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2624 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2625 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2630 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2631 "i", "64", "8", "4", "2", SSEPackedInt,
2632 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2634 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2635 "f", "64", "8", "4", "2", SSEPackedDouble,
2636 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2638 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2639 "f", "32", "16", "8", "4", SSEPackedSingle,
2640 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2642 //===----------------------------------------------------------------------===//
2643 // AVX-512 - Integer arithmetic
2645 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2646 X86VectorVTInfo _, OpndItins itins,
2647 bit IsCommutable = 0> {
2648 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2649 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2650 "$src2, $src1", "$src1, $src2",
2651 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2652 "", itins.rr, IsCommutable>,
2653 AVX512BIBase, EVEX_4V;
2656 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2657 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2658 "$src2, $src1", "$src1, $src2",
2659 (_.VT (OpNode _.RC:$src1,
2660 (bitconvert (_.LdFrag addr:$src2)))),
2662 AVX512BIBase, EVEX_4V;
2665 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2666 X86VectorVTInfo _, OpndItins itins,
2667 bit IsCommutable = 0> :
2668 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2670 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2671 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2672 "${src2}"##_.BroadcastStr##", $src1",
2673 "$src1, ${src2}"##_.BroadcastStr,
2674 (_.VT (OpNode _.RC:$src1,
2676 (_.ScalarLdFrag addr:$src2)))),
2678 AVX512BIBase, EVEX_4V, EVEX_B;
2681 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2682 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2683 Predicate prd, bit IsCommutable = 0> {
2684 let Predicates = [prd] in
2685 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2686 IsCommutable>, EVEX_V512;
2688 let Predicates = [prd, HasVLX] in {
2689 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2690 IsCommutable>, EVEX_V256;
2691 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2692 IsCommutable>, EVEX_V128;
2696 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2697 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2698 Predicate prd, bit IsCommutable = 0> {
2699 let Predicates = [prd] in
2700 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2701 IsCommutable>, EVEX_V512;
2703 let Predicates = [prd, HasVLX] in {
2704 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2705 IsCommutable>, EVEX_V256;
2706 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2707 IsCommutable>, EVEX_V128;
2711 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2712 OpndItins itins, Predicate prd,
2713 bit IsCommutable = 0> {
2714 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2715 itins, prd, IsCommutable>,
2716 VEX_W, EVEX_CD8<64, CD8VF>;
2719 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2720 OpndItins itins, Predicate prd,
2721 bit IsCommutable = 0> {
2722 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2723 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2726 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2727 OpndItins itins, Predicate prd,
2728 bit IsCommutable = 0> {
2729 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2730 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2733 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2734 OpndItins itins, Predicate prd,
2735 bit IsCommutable = 0> {
2736 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2737 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2740 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2741 SDNode OpNode, OpndItins itins, Predicate prd,
2742 bit IsCommutable = 0> {
2743 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2746 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2750 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2751 SDNode OpNode, OpndItins itins, Predicate prd,
2752 bit IsCommutable = 0> {
2753 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2756 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2760 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2761 bits<8> opc_d, bits<8> opc_q,
2762 string OpcodeStr, SDNode OpNode,
2763 OpndItins itins, bit IsCommutable = 0> {
2764 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2765 itins, HasAVX512, IsCommutable>,
2766 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2767 itins, HasBWI, IsCommutable>;
2770 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2771 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2772 PatFrag memop_frag, X86MemOperand x86memop,
2773 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2774 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2775 let isCommutable = IsCommutable in
2777 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2778 (ins RC:$src1, RC:$src2),
2779 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2781 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2782 (ins KRC:$mask, RC:$src1, RC:$src2),
2783 !strconcat(OpcodeStr,
2784 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2785 [], itins.rr>, EVEX_4V, EVEX_K;
2786 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2787 (ins KRC:$mask, RC:$src1, RC:$src2),
2788 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2789 "|$dst {${mask}} {z}, $src1, $src2}"),
2790 [], itins.rr>, EVEX_4V, EVEX_KZ;
2792 let mayLoad = 1 in {
2793 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2794 (ins RC:$src1, x86memop:$src2),
2795 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2797 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2798 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2799 !strconcat(OpcodeStr,
2800 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2801 [], itins.rm>, EVEX_4V, EVEX_K;
2802 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2803 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2804 !strconcat(OpcodeStr,
2805 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2806 [], itins.rm>, EVEX_4V, EVEX_KZ;
2807 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2808 (ins RC:$src1, x86scalar_mop:$src2),
2809 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2810 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2811 [], itins.rm>, EVEX_4V, EVEX_B;
2812 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2813 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2814 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2815 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2817 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2818 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2819 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2820 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2821 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2823 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2827 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2828 SSE_INTALU_ITINS_P, 1>;
2829 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2830 SSE_INTALU_ITINS_P, 0>;
2831 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2832 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2833 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2834 SSE_INTALU_ITINS_P, HasBWI, 1>;
2835 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2836 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2838 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2839 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2840 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2841 EVEX_CD8<64, CD8VF>, VEX_W;
2843 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2844 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2845 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2847 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2848 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2850 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2851 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2852 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2853 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2854 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2855 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2857 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2858 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2859 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2860 SSE_INTALU_ITINS_P, HasBWI, 1>;
2861 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2862 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2864 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2865 SSE_INTALU_ITINS_P, HasBWI, 1>;
2866 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2867 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2868 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2869 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2871 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2872 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2873 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2874 SSE_INTALU_ITINS_P, HasBWI, 1>;
2875 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2876 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2878 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2879 SSE_INTALU_ITINS_P, HasBWI, 1>;
2880 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2881 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2882 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2883 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2885 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2886 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2887 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2888 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2889 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2890 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2891 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2892 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2893 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2894 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2895 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2896 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2897 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2898 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2899 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2900 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2901 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2902 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2903 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2904 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2905 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2906 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2907 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2908 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2909 //===----------------------------------------------------------------------===//
2910 // AVX-512 - Unpack Instructions
2911 //===----------------------------------------------------------------------===//
2913 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2914 PatFrag mem_frag, RegisterClass RC,
2915 X86MemOperand x86memop, string asm,
2917 def rr : AVX512PI<opc, MRMSrcReg,
2918 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2920 (vt (OpNode RC:$src1, RC:$src2)))],
2922 def rm : AVX512PI<opc, MRMSrcMem,
2923 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2925 (vt (OpNode RC:$src1,
2926 (bitconvert (mem_frag addr:$src2)))))],
2930 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2931 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2932 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2933 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2934 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2935 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2936 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2937 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2938 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2939 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2940 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2941 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2943 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2944 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2945 X86MemOperand x86memop> {
2946 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2947 (ins RC:$src1, RC:$src2),
2948 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2949 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2950 IIC_SSE_UNPCK>, EVEX_4V;
2951 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2952 (ins RC:$src1, x86memop:$src2),
2953 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2954 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2955 (bitconvert (memop_frag addr:$src2)))))],
2956 IIC_SSE_UNPCK>, EVEX_4V;
2958 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2959 VR512, memopv16i32, i512mem>, EVEX_V512,
2960 EVEX_CD8<32, CD8VF>;
2961 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2962 VR512, memopv8i64, i512mem>, EVEX_V512,
2963 VEX_W, EVEX_CD8<64, CD8VF>;
2964 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2965 VR512, memopv16i32, i512mem>, EVEX_V512,
2966 EVEX_CD8<32, CD8VF>;
2967 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2968 VR512, memopv8i64, i512mem>, EVEX_V512,
2969 VEX_W, EVEX_CD8<64, CD8VF>;
2970 //===----------------------------------------------------------------------===//
2974 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2975 SDNode OpNode, PatFrag mem_frag,
2976 X86MemOperand x86memop, ValueType OpVT> {
2977 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2978 (ins RC:$src1, i8imm:$src2),
2979 !strconcat(OpcodeStr,
2980 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2982 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2984 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2985 (ins x86memop:$src1, i8imm:$src2),
2986 !strconcat(OpcodeStr,
2987 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2989 (OpVT (OpNode (mem_frag addr:$src1),
2990 (i8 imm:$src2))))]>, EVEX;
2993 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2994 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2996 //===----------------------------------------------------------------------===//
2997 // AVX-512 Logical Instructions
2998 //===----------------------------------------------------------------------===//
3000 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3001 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3002 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3003 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3004 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3005 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3006 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3007 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3009 //===----------------------------------------------------------------------===//
3010 // AVX-512 FP arithmetic
3011 //===----------------------------------------------------------------------===//
3013 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3015 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3016 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3017 EVEX_CD8<32, CD8VT1>;
3018 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3019 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3020 EVEX_CD8<64, CD8VT1>;
3023 let isCommutable = 1 in {
3024 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3025 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3026 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3027 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3029 let isCommutable = 0 in {
3030 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3031 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3034 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3035 X86VectorVTInfo _, bit IsCommutable> {
3036 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3037 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3038 "$src2, $src1", "$src1, $src2",
3039 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3040 let mayLoad = 1 in {
3041 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3042 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3043 "$src2, $src1", "$src1, $src2",
3044 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3045 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3046 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3047 "${src2}"##_.BroadcastStr##", $src1",
3048 "$src1, ${src2}"##_.BroadcastStr,
3049 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3050 (_.ScalarLdFrag addr:$src2))))>,
3055 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3056 bit IsCommutable = 0> {
3057 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3058 IsCommutable>, EVEX_V512, PS,
3059 EVEX_CD8<32, CD8VF>;
3060 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3061 IsCommutable>, EVEX_V512, PD, VEX_W,
3062 EVEX_CD8<64, CD8VF>;
3064 // Define only if AVX512VL feature is present.
3065 let Predicates = [HasVLX] in {
3066 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3067 IsCommutable>, EVEX_V128, PS,
3068 EVEX_CD8<32, CD8VF>;
3069 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3070 IsCommutable>, EVEX_V256, PS,
3071 EVEX_CD8<32, CD8VF>;
3072 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3073 IsCommutable>, EVEX_V128, PD, VEX_W,
3074 EVEX_CD8<64, CD8VF>;
3075 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3076 IsCommutable>, EVEX_V256, PD, VEX_W,
3077 EVEX_CD8<64, CD8VF>;
3081 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3082 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3083 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3084 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3085 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3086 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3088 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3089 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3090 (i16 -1), FROUND_CURRENT)),
3091 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3093 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3094 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3095 (i8 -1), FROUND_CURRENT)),
3096 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3098 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3099 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3100 (i16 -1), FROUND_CURRENT)),
3101 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3103 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3104 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3105 (i8 -1), FROUND_CURRENT)),
3106 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3107 //===----------------------------------------------------------------------===//
3108 // AVX-512 VPTESTM instructions
3109 //===----------------------------------------------------------------------===//
3111 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3112 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3113 SDNode OpNode, ValueType vt> {
3114 def rr : AVX512PI<opc, MRMSrcReg,
3115 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3116 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3117 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3118 SSEPackedInt>, EVEX_4V;
3119 def rm : AVX512PI<opc, MRMSrcMem,
3120 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3121 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3122 [(set KRC:$dst, (OpNode (vt RC:$src1),
3123 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3126 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3127 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3128 EVEX_CD8<32, CD8VF>;
3129 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3130 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3131 EVEX_CD8<64, CD8VF>;
3133 let Predicates = [HasCDI] in {
3134 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3135 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3136 EVEX_CD8<32, CD8VF>;
3137 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3138 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3139 EVEX_CD8<64, CD8VF>;
3142 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3143 (v16i32 VR512:$src2), (i16 -1))),
3144 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3146 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3147 (v8i64 VR512:$src2), (i8 -1))),
3148 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3150 //===----------------------------------------------------------------------===//
3151 // AVX-512 Shift instructions
3152 //===----------------------------------------------------------------------===//
3153 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3154 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3155 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3156 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3157 "$src2, $src1", "$src1, $src2",
3158 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3159 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3160 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3161 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3162 "$src2, $src1", "$src1, $src2",
3163 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3164 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3167 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3168 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3169 // src2 is always 128-bit
3170 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3171 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3172 "$src2, $src1", "$src1, $src2",
3173 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3174 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3175 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3176 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3177 "$src2, $src1", "$src1, $src2",
3178 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3179 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3182 multiclass avx512_varshift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3183 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3184 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3187 multiclass avx512_varshift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3189 defm D : avx512_varshift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3190 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3191 defm Q : avx512_varshift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3192 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3195 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3197 EVEX_V512, EVEX_CD8<32, CD8VF>;
3198 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3199 v8i64_info>, EVEX_V512,
3200 EVEX_CD8<64, CD8VF>, VEX_W;
3202 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3203 v16i32_info>, EVEX_V512,
3204 EVEX_CD8<32, CD8VF>;
3205 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3206 v8i64_info>, EVEX_V512,
3207 EVEX_CD8<64, CD8VF>, VEX_W;
3209 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3211 EVEX_V512, EVEX_CD8<32, CD8VF>;
3212 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3213 v8i64_info>, EVEX_V512,
3214 EVEX_CD8<64, CD8VF>, VEX_W;
3216 defm VPSRL : avx512_varshift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3217 defm VPSLL : avx512_varshift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3218 defm VPSRA : avx512_varshift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3220 //===-------------------------------------------------------------------===//
3221 // Variable Bit Shifts
3222 //===-------------------------------------------------------------------===//
3223 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3224 RegisterClass RC, ValueType vt,
3225 X86MemOperand x86memop, PatFrag mem_frag> {
3226 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3227 (ins RC:$src1, RC:$src2),
3228 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3230 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3232 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3233 (ins RC:$src1, x86memop:$src2),
3234 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3236 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3240 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3241 i512mem, memopv16i32>, EVEX_V512,
3242 EVEX_CD8<32, CD8VF>;
3243 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3244 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3245 EVEX_CD8<64, CD8VF>;
3246 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3247 i512mem, memopv16i32>, EVEX_V512,
3248 EVEX_CD8<32, CD8VF>;
3249 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3250 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3251 EVEX_CD8<64, CD8VF>;
3252 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3253 i512mem, memopv16i32>, EVEX_V512,
3254 EVEX_CD8<32, CD8VF>;
3255 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3256 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3257 EVEX_CD8<64, CD8VF>;
3259 //===----------------------------------------------------------------------===//
3260 // AVX-512 - MOVDDUP
3261 //===----------------------------------------------------------------------===//
3263 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3264 X86MemOperand x86memop, PatFrag memop_frag> {
3265 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3266 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3267 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3268 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3269 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3271 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3274 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3275 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3276 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3277 (VMOVDDUPZrm addr:$src)>;
3279 //===---------------------------------------------------------------------===//
3280 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3281 //===---------------------------------------------------------------------===//
3282 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3283 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3284 X86MemOperand x86memop> {
3285 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3286 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3287 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3289 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3290 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3291 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3294 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3295 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3296 EVEX_CD8<32, CD8VF>;
3297 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3298 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3299 EVEX_CD8<32, CD8VF>;
3301 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3302 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3303 (VMOVSHDUPZrm addr:$src)>;
3304 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3305 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3306 (VMOVSLDUPZrm addr:$src)>;
3308 //===----------------------------------------------------------------------===//
3309 // Move Low to High and High to Low packed FP Instructions
3310 //===----------------------------------------------------------------------===//
3311 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3312 (ins VR128X:$src1, VR128X:$src2),
3313 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3314 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3315 IIC_SSE_MOV_LH>, EVEX_4V;
3316 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3317 (ins VR128X:$src1, VR128X:$src2),
3318 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3319 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3320 IIC_SSE_MOV_LH>, EVEX_4V;
3322 let Predicates = [HasAVX512] in {
3324 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3325 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3326 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3327 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3330 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3331 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3334 //===----------------------------------------------------------------------===//
3335 // FMA - Fused Multiply Operations
3338 let Constraints = "$src1 = $dst" in {
3339 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3340 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3341 SDPatternOperator OpNode = null_frag> {
3342 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3343 (ins _.RC:$src2, _.RC:$src3),
3344 OpcodeStr, "$src3, $src2", "$src2, $src3",
3345 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3349 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3350 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3351 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3352 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3353 (_.MemOpFrag addr:$src3))))]>;
3354 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3355 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3356 !strconcat(OpcodeStr, "\t{${src3}", _.BroadcastStr,
3357 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3358 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3359 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3361 } // Constraints = "$src1 = $dst"
3363 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3364 string OpcodeStr, X86VectorVTInfo VTI,
3365 SDPatternOperator OpNode> {
3366 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3368 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3370 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3372 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3375 let ExeDomain = SSEPackedSingle in {
3376 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3377 v16f32_info, X86Fmadd>;
3378 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3379 v16f32_info, X86Fmsub>;
3380 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3381 v16f32_info, X86Fmaddsub>;
3382 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3383 v16f32_info, X86Fmsubadd>;
3384 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3385 v16f32_info, X86Fnmadd>;
3386 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3387 v16f32_info, X86Fnmsub>;
3389 let ExeDomain = SSEPackedDouble in {
3390 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3391 v8f64_info, X86Fmadd>, VEX_W;
3392 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3393 v8f64_info, X86Fmsub>, VEX_W;
3394 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3395 v8f64_info, X86Fmaddsub>, VEX_W;
3396 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3397 v8f64_info, X86Fmsubadd>, VEX_W;
3398 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3399 v8f64_info, X86Fnmadd>, VEX_W;
3400 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3401 v8f64_info, X86Fnmsub>, VEX_W;
3404 let Constraints = "$src1 = $dst" in {
3405 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3406 X86VectorVTInfo _> {
3408 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3409 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3410 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3411 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3413 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3414 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3415 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3416 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3418 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3419 (_.ScalarLdFrag addr:$src2))),
3420 _.RC:$src3))]>, EVEX_B;
3422 } // Constraints = "$src1 = $dst"
3425 let ExeDomain = SSEPackedSingle in {
3426 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3428 EVEX_V512, EVEX_CD8<32, CD8VF>;
3429 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3431 EVEX_V512, EVEX_CD8<32, CD8VF>;
3432 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3434 EVEX_V512, EVEX_CD8<32, CD8VF>;
3435 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3437 EVEX_V512, EVEX_CD8<32, CD8VF>;
3438 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3440 EVEX_V512, EVEX_CD8<32, CD8VF>;
3441 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3443 EVEX_V512, EVEX_CD8<32, CD8VF>;
3445 let ExeDomain = SSEPackedDouble in {
3446 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3448 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3449 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3451 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3452 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3454 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3455 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3457 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3458 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3460 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3461 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3463 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3467 let Constraints = "$src1 = $dst" in {
3468 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3469 RegisterClass RC, ValueType OpVT,
3470 X86MemOperand x86memop, Operand memop,
3472 let isCommutable = 1 in
3473 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3474 (ins RC:$src1, RC:$src2, RC:$src3),
3475 !strconcat(OpcodeStr,
3476 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3478 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3480 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3481 (ins RC:$src1, RC:$src2, f128mem:$src3),
3482 !strconcat(OpcodeStr,
3483 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3485 (OpVT (OpNode RC:$src2, RC:$src1,
3486 (mem_frag addr:$src3))))]>;
3489 } // Constraints = "$src1 = $dst"
3491 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3492 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3493 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3494 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3495 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3496 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3497 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3498 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3499 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3500 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3501 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3502 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3503 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3504 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3505 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3506 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3508 //===----------------------------------------------------------------------===//
3509 // AVX-512 Scalar convert from sign integer to float/double
3510 //===----------------------------------------------------------------------===//
3512 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3513 X86MemOperand x86memop, string asm> {
3514 let hasSideEffects = 0 in {
3515 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3516 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3519 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3520 (ins DstRC:$src1, x86memop:$src),
3521 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3523 } // hasSideEffects = 0
3525 let Predicates = [HasAVX512] in {
3526 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3527 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3528 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3529 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3530 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3531 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3532 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3533 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3535 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3536 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3537 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3538 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3539 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3540 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3541 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3542 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3544 def : Pat<(f32 (sint_to_fp GR32:$src)),
3545 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3546 def : Pat<(f32 (sint_to_fp GR64:$src)),
3547 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3548 def : Pat<(f64 (sint_to_fp GR32:$src)),
3549 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3550 def : Pat<(f64 (sint_to_fp GR64:$src)),
3551 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3553 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3554 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3555 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3556 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3557 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3558 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3559 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3560 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3562 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3563 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3564 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3565 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3566 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3567 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3568 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3569 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3571 def : Pat<(f32 (uint_to_fp GR32:$src)),
3572 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3573 def : Pat<(f32 (uint_to_fp GR64:$src)),
3574 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3575 def : Pat<(f64 (uint_to_fp GR32:$src)),
3576 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3577 def : Pat<(f64 (uint_to_fp GR64:$src)),
3578 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3581 //===----------------------------------------------------------------------===//
3582 // AVX-512 Scalar convert from float/double to integer
3583 //===----------------------------------------------------------------------===//
3584 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3585 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3587 let hasSideEffects = 0 in {
3588 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3589 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3590 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3591 Requires<[HasAVX512]>;
3593 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3594 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3595 Requires<[HasAVX512]>;
3596 } // hasSideEffects = 0
3598 let Predicates = [HasAVX512] in {
3599 // Convert float/double to signed/unsigned int 32/64
3600 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3601 ssmem, sse_load_f32, "cvtss2si">,
3602 XS, EVEX_CD8<32, CD8VT1>;
3603 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3604 ssmem, sse_load_f32, "cvtss2si">,
3605 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3606 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3607 ssmem, sse_load_f32, "cvtss2usi">,
3608 XS, EVEX_CD8<32, CD8VT1>;
3609 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3610 int_x86_avx512_cvtss2usi64, ssmem,
3611 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3612 EVEX_CD8<32, CD8VT1>;
3613 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3614 sdmem, sse_load_f64, "cvtsd2si">,
3615 XD, EVEX_CD8<64, CD8VT1>;
3616 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3617 sdmem, sse_load_f64, "cvtsd2si">,
3618 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3619 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3620 sdmem, sse_load_f64, "cvtsd2usi">,
3621 XD, EVEX_CD8<64, CD8VT1>;
3622 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3623 int_x86_avx512_cvtsd2usi64, sdmem,
3624 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3625 EVEX_CD8<64, CD8VT1>;
3627 let isCodeGenOnly = 1 in {
3628 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3629 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3630 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3631 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3632 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3633 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3634 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3635 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3636 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3637 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3638 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3639 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3641 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3642 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3643 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3644 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3645 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3646 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3647 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3648 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3649 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3650 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3651 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3652 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3653 } // isCodeGenOnly = 1
3655 // Convert float/double to signed/unsigned int 32/64 with truncation
3656 let isCodeGenOnly = 1 in {
3657 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3658 ssmem, sse_load_f32, "cvttss2si">,
3659 XS, EVEX_CD8<32, CD8VT1>;
3660 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3661 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3662 "cvttss2si">, XS, VEX_W,
3663 EVEX_CD8<32, CD8VT1>;
3664 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3665 sdmem, sse_load_f64, "cvttsd2si">, XD,
3666 EVEX_CD8<64, CD8VT1>;
3667 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3668 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3669 "cvttsd2si">, XD, VEX_W,
3670 EVEX_CD8<64, CD8VT1>;
3671 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3672 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3673 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3674 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3675 int_x86_avx512_cvttss2usi64, ssmem,
3676 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3677 EVEX_CD8<32, CD8VT1>;
3678 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3679 int_x86_avx512_cvttsd2usi,
3680 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3681 EVEX_CD8<64, CD8VT1>;
3682 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3683 int_x86_avx512_cvttsd2usi64, sdmem,
3684 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3685 EVEX_CD8<64, CD8VT1>;
3686 } // isCodeGenOnly = 1
3688 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3689 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3691 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3692 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3693 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3694 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3695 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3696 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3699 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3700 loadf32, "cvttss2si">, XS,
3701 EVEX_CD8<32, CD8VT1>;
3702 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3703 loadf32, "cvttss2usi">, XS,
3704 EVEX_CD8<32, CD8VT1>;
3705 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3706 loadf32, "cvttss2si">, XS, VEX_W,
3707 EVEX_CD8<32, CD8VT1>;
3708 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3709 loadf32, "cvttss2usi">, XS, VEX_W,
3710 EVEX_CD8<32, CD8VT1>;
3711 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3712 loadf64, "cvttsd2si">, XD,
3713 EVEX_CD8<64, CD8VT1>;
3714 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3715 loadf64, "cvttsd2usi">, XD,
3716 EVEX_CD8<64, CD8VT1>;
3717 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3718 loadf64, "cvttsd2si">, XD, VEX_W,
3719 EVEX_CD8<64, CD8VT1>;
3720 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3721 loadf64, "cvttsd2usi">, XD, VEX_W,
3722 EVEX_CD8<64, CD8VT1>;
3724 //===----------------------------------------------------------------------===//
3725 // AVX-512 Convert form float to double and back
3726 //===----------------------------------------------------------------------===//
3727 let hasSideEffects = 0 in {
3728 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3729 (ins FR32X:$src1, FR32X:$src2),
3730 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3731 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3733 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3734 (ins FR32X:$src1, f32mem:$src2),
3735 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3736 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3737 EVEX_CD8<32, CD8VT1>;
3739 // Convert scalar double to scalar single
3740 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3741 (ins FR64X:$src1, FR64X:$src2),
3742 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3743 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3745 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3746 (ins FR64X:$src1, f64mem:$src2),
3747 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3748 []>, EVEX_4V, VEX_LIG, VEX_W,
3749 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3752 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3753 Requires<[HasAVX512]>;
3754 def : Pat<(fextend (loadf32 addr:$src)),
3755 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3757 def : Pat<(extloadf32 addr:$src),
3758 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3759 Requires<[HasAVX512, OptForSize]>;
3761 def : Pat<(extloadf32 addr:$src),
3762 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3763 Requires<[HasAVX512, OptForSpeed]>;
3765 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3766 Requires<[HasAVX512]>;
3768 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3769 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3770 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3772 let hasSideEffects = 0 in {
3773 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3774 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3776 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3777 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3778 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3779 [], d>, EVEX, EVEX_B, EVEX_RC;
3781 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3782 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3784 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3785 } // hasSideEffects = 0
3788 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3789 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3790 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3792 let hasSideEffects = 0 in {
3793 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3794 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3796 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3798 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3799 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3801 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3802 } // hasSideEffects = 0
3805 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3806 memopv8f64, f512mem, v8f32, v8f64,
3807 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3808 EVEX_CD8<64, CD8VF>;
3810 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3811 memopv4f64, f256mem, v8f64, v8f32,
3812 SSEPackedDouble>, EVEX_V512, PS,
3813 EVEX_CD8<32, CD8VH>;
3814 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3815 (VCVTPS2PDZrm addr:$src)>;
3817 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3818 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3819 (VCVTPD2PSZrr VR512:$src)>;
3821 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3822 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3823 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3825 //===----------------------------------------------------------------------===//
3826 // AVX-512 Vector convert from sign integer to float/double
3827 //===----------------------------------------------------------------------===//
3829 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3830 memopv8i64, i512mem, v16f32, v16i32,
3831 SSEPackedSingle>, EVEX_V512, PS,
3832 EVEX_CD8<32, CD8VF>;
3834 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3835 memopv4i64, i256mem, v8f64, v8i32,
3836 SSEPackedDouble>, EVEX_V512, XS,
3837 EVEX_CD8<32, CD8VH>;
3839 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3840 memopv16f32, f512mem, v16i32, v16f32,
3841 SSEPackedSingle>, EVEX_V512, XS,
3842 EVEX_CD8<32, CD8VF>;
3844 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3845 memopv8f64, f512mem, v8i32, v8f64,
3846 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3847 EVEX_CD8<64, CD8VF>;
3849 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3850 memopv16f32, f512mem, v16i32, v16f32,
3851 SSEPackedSingle>, EVEX_V512, PS,
3852 EVEX_CD8<32, CD8VF>;
3854 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3855 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3856 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3857 (VCVTTPS2UDQZrr VR512:$src)>;
3859 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3860 memopv8f64, f512mem, v8i32, v8f64,
3861 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3862 EVEX_CD8<64, CD8VF>;
3864 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3865 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3866 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3867 (VCVTTPD2UDQZrr VR512:$src)>;
3869 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3870 memopv4i64, f256mem, v8f64, v8i32,
3871 SSEPackedDouble>, EVEX_V512, XS,
3872 EVEX_CD8<32, CD8VH>;
3874 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3875 memopv16i32, f512mem, v16f32, v16i32,
3876 SSEPackedSingle>, EVEX_V512, XD,
3877 EVEX_CD8<32, CD8VF>;
3879 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3880 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3881 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3883 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3884 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3885 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3887 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3888 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3889 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3891 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3892 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3893 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3895 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3896 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3897 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3899 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3900 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3901 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3902 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3903 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3904 (VCVTDQ2PDZrr VR256X:$src)>;
3905 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3906 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3907 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3908 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3909 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3910 (VCVTUDQ2PDZrr VR256X:$src)>;
3912 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3913 RegisterClass DstRC, PatFrag mem_frag,
3914 X86MemOperand x86memop, Domain d> {
3915 let hasSideEffects = 0 in {
3916 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3917 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3919 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3920 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3921 [], d>, EVEX, EVEX_B, EVEX_RC;
3923 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3924 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3926 } // hasSideEffects = 0
3929 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3930 memopv16f32, f512mem, SSEPackedSingle>, PD,
3931 EVEX_V512, EVEX_CD8<32, CD8VF>;
3932 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3933 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3934 EVEX_V512, EVEX_CD8<64, CD8VF>;
3936 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3937 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3938 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3940 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3941 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3942 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3944 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3945 memopv16f32, f512mem, SSEPackedSingle>,
3946 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3947 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3948 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3949 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3951 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3952 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3953 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3955 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3956 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3957 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3959 let Predicates = [HasAVX512] in {
3960 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3961 (VCVTPD2PSZrm addr:$src)>;
3962 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3963 (VCVTPS2PDZrm addr:$src)>;
3966 //===----------------------------------------------------------------------===//
3967 // Half precision conversion instructions
3968 //===----------------------------------------------------------------------===//
3969 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3970 X86MemOperand x86memop> {
3971 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3972 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3974 let hasSideEffects = 0, mayLoad = 1 in
3975 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3976 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3979 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3980 X86MemOperand x86memop> {
3981 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3982 (ins srcRC:$src1, i32i8imm:$src2),
3983 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3985 let hasSideEffects = 0, mayStore = 1 in
3986 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3987 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3988 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3991 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3992 EVEX_CD8<32, CD8VH>;
3993 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3994 EVEX_CD8<32, CD8VH>;
3996 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3997 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3998 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4000 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4001 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4002 (VCVTPH2PSZrr VR256X:$src)>;
4004 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4005 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4006 "ucomiss">, PS, EVEX, VEX_LIG,
4007 EVEX_CD8<32, CD8VT1>;
4008 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4009 "ucomisd">, PD, EVEX,
4010 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4011 let Pattern = []<dag> in {
4012 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4013 "comiss">, PS, EVEX, VEX_LIG,
4014 EVEX_CD8<32, CD8VT1>;
4015 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4016 "comisd">, PD, EVEX,
4017 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4019 let isCodeGenOnly = 1 in {
4020 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4021 load, "ucomiss">, PS, EVEX, VEX_LIG,
4022 EVEX_CD8<32, CD8VT1>;
4023 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4024 load, "ucomisd">, PD, EVEX,
4025 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4027 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4028 load, "comiss">, PS, EVEX, VEX_LIG,
4029 EVEX_CD8<32, CD8VT1>;
4030 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4031 load, "comisd">, PD, EVEX,
4032 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4036 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4037 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4038 X86MemOperand x86memop> {
4039 let hasSideEffects = 0 in {
4040 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4041 (ins RC:$src1, RC:$src2),
4042 !strconcat(OpcodeStr,
4043 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4044 let mayLoad = 1 in {
4045 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4046 (ins RC:$src1, x86memop:$src2),
4047 !strconcat(OpcodeStr,
4048 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4053 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4054 EVEX_CD8<32, CD8VT1>;
4055 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4056 VEX_W, EVEX_CD8<64, CD8VT1>;
4057 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4058 EVEX_CD8<32, CD8VT1>;
4059 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4060 VEX_W, EVEX_CD8<64, CD8VT1>;
4062 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4063 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4064 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4065 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4067 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4068 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4069 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4070 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4072 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4073 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4074 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4075 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4077 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4078 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4079 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4080 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4082 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4083 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4084 X86VectorVTInfo _> {
4085 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4086 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4087 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4088 let mayLoad = 1 in {
4089 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4090 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4092 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4093 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4094 (ins _.ScalarMemOp:$src), OpcodeStr,
4095 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4097 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4102 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4103 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4104 EVEX_V512, EVEX_CD8<32, CD8VF>;
4105 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4106 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4108 // Define only if AVX512VL feature is present.
4109 let Predicates = [HasVLX] in {
4110 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4111 OpNode, v4f32x_info>,
4112 EVEX_V128, EVEX_CD8<32, CD8VF>;
4113 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4114 OpNode, v8f32x_info>,
4115 EVEX_V256, EVEX_CD8<32, CD8VF>;
4116 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4117 OpNode, v2f64x_info>,
4118 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4119 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4120 OpNode, v4f64x_info>,
4121 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4125 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4126 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4128 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4129 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4130 (VRSQRT14PSZr VR512:$src)>;
4131 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4132 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4133 (VRSQRT14PDZr VR512:$src)>;
4135 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4136 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4137 (VRCP14PSZr VR512:$src)>;
4138 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4139 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4140 (VRCP14PDZr VR512:$src)>;
4142 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4143 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4146 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4147 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4148 "$src2, $src1", "$src1, $src2",
4149 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4150 (i32 FROUND_CURRENT))>;
4152 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4153 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4154 "$src2, $src1", "$src1, $src2",
4155 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4156 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4158 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4159 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4160 "$src2, $src1", "$src1, $src2",
4161 (OpNode (_.VT _.RC:$src1),
4162 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4163 (i32 FROUND_CURRENT))>;
4166 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4167 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4168 EVEX_CD8<32, CD8VT1>;
4169 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4170 EVEX_CD8<64, CD8VT1>, VEX_W;
4173 let hasSideEffects = 0, Predicates = [HasERI] in {
4174 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4175 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4177 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4179 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4182 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4183 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4184 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4186 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4187 (ins _.RC:$src), OpcodeStr,
4189 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4192 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4193 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4195 (bitconvert (_.LdFrag addr:$src))),
4196 (i32 FROUND_CURRENT))>;
4198 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4199 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4201 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4202 (i32 FROUND_CURRENT))>, EVEX_B;
4205 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4206 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4207 EVEX_CD8<32, CD8VF>;
4208 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4209 VEX_W, EVEX_CD8<32, CD8VF>;
4212 let Predicates = [HasERI], hasSideEffects = 0 in {
4214 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4215 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4216 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4219 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4220 SDNode OpNode, X86VectorVTInfo _>{
4221 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4222 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4223 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4224 let mayLoad = 1 in {
4225 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4226 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4228 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4230 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4231 (ins _.ScalarMemOp:$src), OpcodeStr,
4232 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4234 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4239 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4240 Intrinsic F32Int, Intrinsic F64Int,
4241 OpndItins itins_s, OpndItins itins_d> {
4242 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4243 (ins FR32X:$src1, FR32X:$src2),
4244 !strconcat(OpcodeStr,
4245 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4246 [], itins_s.rr>, XS, EVEX_4V;
4247 let isCodeGenOnly = 1 in
4248 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4249 (ins VR128X:$src1, VR128X:$src2),
4250 !strconcat(OpcodeStr,
4251 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4253 (F32Int VR128X:$src1, VR128X:$src2))],
4254 itins_s.rr>, XS, EVEX_4V;
4255 let mayLoad = 1 in {
4256 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4257 (ins FR32X:$src1, f32mem:$src2),
4258 !strconcat(OpcodeStr,
4259 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4260 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4261 let isCodeGenOnly = 1 in
4262 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4263 (ins VR128X:$src1, ssmem:$src2),
4264 !strconcat(OpcodeStr,
4265 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4267 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4268 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4270 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4271 (ins FR64X:$src1, FR64X:$src2),
4272 !strconcat(OpcodeStr,
4273 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4275 let isCodeGenOnly = 1 in
4276 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4277 (ins VR128X:$src1, VR128X:$src2),
4278 !strconcat(OpcodeStr,
4279 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4281 (F64Int VR128X:$src1, VR128X:$src2))],
4282 itins_s.rr>, XD, EVEX_4V, VEX_W;
4283 let mayLoad = 1 in {
4284 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4285 (ins FR64X:$src1, f64mem:$src2),
4286 !strconcat(OpcodeStr,
4287 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4288 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4289 let isCodeGenOnly = 1 in
4290 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4291 (ins VR128X:$src1, sdmem:$src2),
4292 !strconcat(OpcodeStr,
4293 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4295 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4296 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4300 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4302 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4304 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4305 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4307 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4308 // Define only if AVX512VL feature is present.
4309 let Predicates = [HasVLX] in {
4310 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4311 OpNode, v4f32x_info>,
4312 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4313 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4314 OpNode, v8f32x_info>,
4315 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4316 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4317 OpNode, v2f64x_info>,
4318 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4319 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4320 OpNode, v4f64x_info>,
4321 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4325 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4327 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4328 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4329 SSE_SQRTSS, SSE_SQRTSD>;
4331 let Predicates = [HasAVX512] in {
4332 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4333 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4334 (VSQRTPSZr VR512:$src1)>;
4335 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4336 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4337 (VSQRTPDZr VR512:$src1)>;
4339 def : Pat<(f32 (fsqrt FR32X:$src)),
4340 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4341 def : Pat<(f32 (fsqrt (load addr:$src))),
4342 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4343 Requires<[OptForSize]>;
4344 def : Pat<(f64 (fsqrt FR64X:$src)),
4345 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4346 def : Pat<(f64 (fsqrt (load addr:$src))),
4347 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4348 Requires<[OptForSize]>;
4350 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4351 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4352 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4353 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4354 Requires<[OptForSize]>;
4356 def : Pat<(f32 (X86frcp FR32X:$src)),
4357 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4358 def : Pat<(f32 (X86frcp (load addr:$src))),
4359 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4360 Requires<[OptForSize]>;
4362 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4363 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4364 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4366 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4367 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4369 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4370 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4371 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4373 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4374 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4378 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4379 X86MemOperand x86memop, RegisterClass RC,
4380 PatFrag mem_frag32, PatFrag mem_frag64,
4381 Intrinsic V4F32Int, Intrinsic V2F64Int,
4383 let ExeDomain = SSEPackedSingle in {
4384 // Intrinsic operation, reg.
4385 // Vector intrinsic operation, reg
4386 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4387 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4388 !strconcat(OpcodeStr,
4389 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4390 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4392 // Vector intrinsic operation, mem
4393 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4394 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4395 !strconcat(OpcodeStr,
4396 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4398 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4399 EVEX_CD8<32, VForm>;
4400 } // ExeDomain = SSEPackedSingle
4402 let ExeDomain = SSEPackedDouble in {
4403 // Vector intrinsic operation, reg
4404 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4405 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4406 !strconcat(OpcodeStr,
4407 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4408 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4410 // Vector intrinsic operation, mem
4411 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4412 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4413 !strconcat(OpcodeStr,
4414 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4416 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4417 EVEX_CD8<64, VForm>;
4418 } // ExeDomain = SSEPackedDouble
4421 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4425 let ExeDomain = GenericDomain in {
4427 let hasSideEffects = 0 in
4428 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4429 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4430 !strconcat(OpcodeStr,
4431 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4434 // Intrinsic operation, reg.
4435 let isCodeGenOnly = 1 in
4436 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4437 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4438 !strconcat(OpcodeStr,
4439 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4440 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4442 // Intrinsic operation, mem.
4443 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4444 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4445 !strconcat(OpcodeStr,
4446 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4447 [(set VR128X:$dst, (F32Int VR128X:$src1,
4448 sse_load_f32:$src2, imm:$src3))]>,
4449 EVEX_CD8<32, CD8VT1>;
4452 let hasSideEffects = 0 in
4453 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4454 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4455 !strconcat(OpcodeStr,
4456 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4459 // Intrinsic operation, reg.
4460 let isCodeGenOnly = 1 in
4461 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4462 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4463 !strconcat(OpcodeStr,
4464 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4465 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4468 // Intrinsic operation, mem.
4469 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4470 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4471 !strconcat(OpcodeStr,
4472 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4474 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4475 VEX_W, EVEX_CD8<64, CD8VT1>;
4476 } // ExeDomain = GenericDomain
4479 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4480 X86MemOperand x86memop, RegisterClass RC,
4481 PatFrag mem_frag, Domain d> {
4482 let ExeDomain = d in {
4483 // Intrinsic operation, reg.
4484 // Vector intrinsic operation, reg
4485 def r : AVX512AIi8<opc, MRMSrcReg,
4486 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4487 !strconcat(OpcodeStr,
4488 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4491 // Vector intrinsic operation, mem
4492 def m : AVX512AIi8<opc, MRMSrcMem,
4493 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4494 !strconcat(OpcodeStr,
4495 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4501 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4502 memopv16f32, SSEPackedSingle>, EVEX_V512,
4503 EVEX_CD8<32, CD8VF>;
4505 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4506 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4508 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4511 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4512 memopv8f64, SSEPackedDouble>, EVEX_V512,
4513 VEX_W, EVEX_CD8<64, CD8VF>;
4515 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4516 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4518 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4520 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4521 Operand x86memop, RegisterClass RC, Domain d> {
4522 let ExeDomain = d in {
4523 def r : AVX512AIi8<opc, MRMSrcReg,
4524 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4525 !strconcat(OpcodeStr,
4526 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4529 def m : AVX512AIi8<opc, MRMSrcMem,
4530 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4531 !strconcat(OpcodeStr,
4532 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4537 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4538 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4540 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4541 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4543 def : Pat<(ffloor FR32X:$src),
4544 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4545 def : Pat<(f64 (ffloor FR64X:$src)),
4546 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4547 def : Pat<(f32 (fnearbyint FR32X:$src)),
4548 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4549 def : Pat<(f64 (fnearbyint FR64X:$src)),
4550 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4551 def : Pat<(f32 (fceil FR32X:$src)),
4552 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4553 def : Pat<(f64 (fceil FR64X:$src)),
4554 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4555 def : Pat<(f32 (frint FR32X:$src)),
4556 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4557 def : Pat<(f64 (frint FR64X:$src)),
4558 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4559 def : Pat<(f32 (ftrunc FR32X:$src)),
4560 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4561 def : Pat<(f64 (ftrunc FR64X:$src)),
4562 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4564 def : Pat<(v16f32 (ffloor VR512:$src)),
4565 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4566 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4567 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4568 def : Pat<(v16f32 (fceil VR512:$src)),
4569 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4570 def : Pat<(v16f32 (frint VR512:$src)),
4571 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4572 def : Pat<(v16f32 (ftrunc VR512:$src)),
4573 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4575 def : Pat<(v8f64 (ffloor VR512:$src)),
4576 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4577 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4578 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4579 def : Pat<(v8f64 (fceil VR512:$src)),
4580 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4581 def : Pat<(v8f64 (frint VR512:$src)),
4582 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4583 def : Pat<(v8f64 (ftrunc VR512:$src)),
4584 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4586 //-------------------------------------------------
4587 // Integer truncate and extend operations
4588 //-------------------------------------------------
4590 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4591 RegisterClass dstRC, RegisterClass srcRC,
4592 RegisterClass KRC, X86MemOperand x86memop> {
4593 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4595 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4598 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4599 (ins KRC:$mask, srcRC:$src),
4600 !strconcat(OpcodeStr,
4601 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4604 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4605 (ins KRC:$mask, srcRC:$src),
4606 !strconcat(OpcodeStr,
4607 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4610 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4611 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4614 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4615 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4616 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4620 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4621 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4622 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4623 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4624 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4625 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4626 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4627 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4628 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4629 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4630 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4631 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4632 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4633 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4634 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4635 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4636 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4637 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4638 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4639 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4640 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4641 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4642 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4643 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4644 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4645 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4646 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4647 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4648 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4649 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4651 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4652 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4653 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4654 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4655 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4657 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4658 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4659 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4660 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4661 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4662 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4663 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4664 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4667 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4668 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4669 PatFrag mem_frag, X86MemOperand x86memop,
4670 ValueType OpVT, ValueType InVT> {
4672 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4674 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4675 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4677 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4678 (ins KRC:$mask, SrcRC:$src),
4679 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4682 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4683 (ins KRC:$mask, SrcRC:$src),
4684 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4687 let mayLoad = 1 in {
4688 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4689 (ins x86memop:$src),
4690 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4692 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4695 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4696 (ins KRC:$mask, x86memop:$src),
4697 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4701 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4702 (ins KRC:$mask, x86memop:$src),
4703 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4709 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4710 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4712 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4713 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4715 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4716 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4717 EVEX_CD8<16, CD8VH>;
4718 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4719 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4720 EVEX_CD8<16, CD8VQ>;
4721 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4722 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4723 EVEX_CD8<32, CD8VH>;
4725 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4726 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4728 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4729 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4731 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4732 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4733 EVEX_CD8<16, CD8VH>;
4734 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4735 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4736 EVEX_CD8<16, CD8VQ>;
4737 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4738 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4739 EVEX_CD8<32, CD8VH>;
4741 //===----------------------------------------------------------------------===//
4742 // GATHER - SCATTER Operations
4744 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4745 RegisterClass RC, X86MemOperand memop> {
4747 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4748 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4749 (ins RC:$src1, KRC:$mask, memop:$src2),
4750 !strconcat(OpcodeStr,
4751 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4755 let ExeDomain = SSEPackedDouble in {
4756 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4757 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4758 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4759 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4762 let ExeDomain = SSEPackedSingle in {
4763 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4764 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4765 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4766 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4769 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4770 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4771 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4772 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4774 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4775 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4776 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4777 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4779 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4780 RegisterClass RC, X86MemOperand memop> {
4781 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4782 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4783 (ins memop:$dst, KRC:$mask, RC:$src2),
4784 !strconcat(OpcodeStr,
4785 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4789 let ExeDomain = SSEPackedDouble in {
4790 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4791 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4792 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4793 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4796 let ExeDomain = SSEPackedSingle in {
4797 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4798 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4799 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4800 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4803 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4804 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4805 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4806 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4808 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4809 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4810 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4811 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4814 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4815 RegisterClass KRC, X86MemOperand memop> {
4816 let Predicates = [HasPFI], hasSideEffects = 1 in
4817 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4818 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4822 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4823 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4825 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4826 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4828 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4829 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4831 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4832 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4834 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4835 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4837 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4838 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4840 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4841 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4843 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4844 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4846 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4847 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4849 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4850 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4852 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4853 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4855 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4856 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4858 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4859 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4861 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4862 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4864 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4865 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4867 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4868 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4869 //===----------------------------------------------------------------------===//
4870 // VSHUFPS - VSHUFPD Operations
4872 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4873 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4875 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4876 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4877 !strconcat(OpcodeStr,
4878 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4879 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4880 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4881 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4882 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4883 (ins RC:$src1, RC:$src2, i8imm:$src3),
4884 !strconcat(OpcodeStr,
4885 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4886 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4887 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4888 EVEX_4V, Sched<[WriteShuffle]>;
4891 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4892 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4893 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4894 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4896 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4897 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4898 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4899 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4900 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4902 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4903 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4904 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4905 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4906 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4908 multiclass avx512_valign<X86VectorVTInfo _> {
4909 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4910 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4912 "$src3, $src2, $src1", "$src1, $src2, $src3",
4913 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4915 AVX512AIi8Base, EVEX_4V;
4917 // Also match valign of packed floats.
4918 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4919 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4922 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4923 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4924 !strconcat("valign"##_.Suffix,
4925 "\t{$src3, $src2, $src1, $dst|"
4926 "$dst, $src1, $src2, $src3}"),
4929 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4930 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4932 // Helper fragments to match sext vXi1 to vXiY.
4933 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4934 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4936 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4937 RegisterClass KRC, RegisterClass RC,
4938 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4940 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4941 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4943 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4944 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4946 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4947 !strconcat(OpcodeStr,
4948 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4950 let mayLoad = 1 in {
4951 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4952 (ins x86memop:$src),
4953 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4955 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4956 (ins KRC:$mask, x86memop:$src),
4957 !strconcat(OpcodeStr,
4958 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4960 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4961 (ins KRC:$mask, x86memop:$src),
4962 !strconcat(OpcodeStr,
4963 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4965 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4966 (ins x86scalar_mop:$src),
4967 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
4968 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4970 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4971 (ins KRC:$mask, x86scalar_mop:$src),
4972 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
4973 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4974 []>, EVEX, EVEX_B, EVEX_K;
4975 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4976 (ins KRC:$mask, x86scalar_mop:$src),
4977 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
4978 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4980 []>, EVEX, EVEX_B, EVEX_KZ;
4984 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4985 i512mem, i32mem, "{1to16}">, EVEX_V512,
4986 EVEX_CD8<32, CD8VF>;
4987 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4988 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4989 EVEX_CD8<64, CD8VF>;
4992 (bc_v16i32 (v16i1sextv16i32)),
4993 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4994 (VPABSDZrr VR512:$src)>;
4996 (bc_v8i64 (v8i1sextv8i64)),
4997 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4998 (VPABSQZrr VR512:$src)>;
5000 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5001 (v16i32 immAllZerosV), (i16 -1))),
5002 (VPABSDZrr VR512:$src)>;
5003 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5004 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5005 (VPABSQZrr VR512:$src)>;
5007 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5008 RegisterClass RC, RegisterClass KRC,
5009 X86MemOperand x86memop,
5010 X86MemOperand x86scalar_mop, string BrdcstStr> {
5011 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5013 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5015 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5016 (ins x86memop:$src),
5017 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5019 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5020 (ins x86scalar_mop:$src),
5021 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5022 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5024 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5025 (ins KRC:$mask, RC:$src),
5026 !strconcat(OpcodeStr,
5027 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5029 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5030 (ins KRC:$mask, x86memop:$src),
5031 !strconcat(OpcodeStr,
5032 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5034 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5035 (ins KRC:$mask, x86scalar_mop:$src),
5036 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5037 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5039 []>, EVEX, EVEX_KZ, EVEX_B;
5041 let Constraints = "$src1 = $dst" in {
5042 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5043 (ins RC:$src1, KRC:$mask, RC:$src2),
5044 !strconcat(OpcodeStr,
5045 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5047 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5048 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5049 !strconcat(OpcodeStr,
5050 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5052 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5053 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5054 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5055 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5056 []>, EVEX, EVEX_K, EVEX_B;
5060 let Predicates = [HasCDI] in {
5061 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5062 i512mem, i32mem, "{1to16}">,
5063 EVEX_V512, EVEX_CD8<32, CD8VF>;
5066 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5067 i512mem, i64mem, "{1to8}">,
5068 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5072 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5074 (VPCONFLICTDrrk VR512:$src1,
5075 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5077 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5079 (VPCONFLICTQrrk VR512:$src1,
5080 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5082 let Predicates = [HasCDI] in {
5083 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5084 i512mem, i32mem, "{1to16}">,
5085 EVEX_V512, EVEX_CD8<32, CD8VF>;
5088 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5089 i512mem, i64mem, "{1to8}">,
5090 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5094 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5096 (VPLZCNTDrrk VR512:$src1,
5097 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5099 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5101 (VPLZCNTQrrk VR512:$src1,
5102 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5104 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5105 (VPLZCNTDrm addr:$src)>;
5106 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5107 (VPLZCNTDrr VR512:$src)>;
5108 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5109 (VPLZCNTQrm addr:$src)>;
5110 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5111 (VPLZCNTQrr VR512:$src)>;
5113 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5114 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5115 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5117 def : Pat<(store VK1:$src, addr:$dst),
5118 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5120 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5121 (truncstore node:$val, node:$ptr), [{
5122 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5125 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5126 (MOV8mr addr:$dst, GR8:$src)>;
5128 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5129 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5130 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5131 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5134 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5135 string OpcodeStr, Predicate prd> {
5136 let Predicates = [prd] in
5137 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5139 let Predicates = [prd, HasVLX] in {
5140 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5141 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5145 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5146 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5148 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5150 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5152 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5156 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;