1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
143 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
144 "lcall{q}\t{*}$dst", []>;
147 // FIXME: We need to teach codegen about single list of call-clobbered registers.
149 // All calls clobber the non-callee saved registers. RSP is marked as
150 // a use to prevent stack-pointer assignments that appear immediately
151 // before calls from potentially appearing dead. Uses for argument
152 // registers are added manually.
153 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
154 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
155 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
158 def WINCALL64pcrel32 : I<0xE8, RawFrm,
159 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
162 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
164 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
165 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
167 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
174 "#TC_RETURN $dst $offset",
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
180 "#TC_RETURN $dst $offset",
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
185 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
186 "jmp{q}\t{*}$dst # TAILCALL",
190 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
191 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
192 [(brind GR64:$dst)]>;
193 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
194 [(brind (loadi64 addr:$dst))]>;
195 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
196 "ljmp{q}\t{*}$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // EH Pseudo Instructions
202 let isTerminator = 1, isReturn = 1, isBarrier = 1,
204 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
205 "ret\t#eh_return, addr: $addr",
206 [(X86ehret GR64:$addr)]>;
210 //===----------------------------------------------------------------------===//
211 // Miscellaneous Instructions...
213 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
214 def LEAVE64 : I<0xC9, RawFrm,
215 (outs), (ins), "leave", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
218 def POP64r : I<0x58, AddRegFrm,
219 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
220 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
221 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
223 let mayStore = 1 in {
224 def PUSH64r : I<0x50, AddRegFrm,
225 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
226 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
227 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
231 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
232 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
233 "push{q}\t$imm", []>;
234 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
235 "push{q}\t$imm", []>;
236 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
237 "push{q}\t$imm", []>;
240 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
241 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
242 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
243 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
245 def LEA64_32r : I<0x8D, MRMSrcMem,
246 (outs GR32:$dst), (ins lea64_32mem:$src),
247 "lea{l}\t{$src|$dst}, {$dst|$src}",
248 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
250 let isReMaterializable = 1 in
251 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
252 "lea{q}\t{$src|$dst}, {$dst|$src}",
253 [(set GR64:$dst, lea64addr:$src)]>;
255 let isTwoAddress = 1 in
256 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
258 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
260 // Bit scan instructions.
261 let Defs = [EFLAGS] in {
262 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
263 "bsf{q}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
265 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
266 "bsf{q}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
268 (implicit EFLAGS)]>, TB;
270 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
271 "bsr{q}\t{$src, $dst|$dst, $src}",
272 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
273 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
274 "bsr{q}\t{$src, $dst|$dst, $src}",
275 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
276 (implicit EFLAGS)]>, TB;
280 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
281 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
282 [(X86rep_movs i64)]>, REP;
283 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
284 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
285 [(X86rep_stos i64)]>, REP;
287 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
289 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
291 // Fast system-call instructions
292 def SYSEXIT64 : RI<0x35, RawFrm,
293 (outs), (ins), "sysexit", []>, TB;
295 //===----------------------------------------------------------------------===//
296 // Move Instructions...
299 let neverHasSideEffects = 1 in
300 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
301 "mov{q}\t{$src, $dst|$dst, $src}", []>;
303 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
304 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
305 "movabs{q}\t{$src, $dst|$dst, $src}",
306 [(set GR64:$dst, imm:$src)]>;
307 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
308 "mov{q}\t{$src, $dst|$dst, $src}",
309 [(set GR64:$dst, i64immSExt32:$src)]>;
312 let canFoldAsLoad = 1 in
313 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
314 "mov{q}\t{$src, $dst|$dst, $src}",
315 [(set GR64:$dst, (load addr:$src))]>;
317 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
318 "mov{q}\t{$src, $dst|$dst, $src}",
319 [(store GR64:$src, addr:$dst)]>;
320 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
321 "mov{q}\t{$src, $dst|$dst, $src}",
322 [(store i64immSExt32:$src, addr:$dst)]>;
324 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
325 "mov{q}\t{$src, %rax|%rax, $src}", []>;
326 def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
327 "mov{q}\t{$src, %rax|%rax, $src}", []>;
328 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
329 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
330 def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
331 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
333 // Moves to and from segment registers
334 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
335 "mov{w}\t{$src, $dst|$dst, $src}", []>;
336 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
337 "mov{w}\t{$src, $dst|$dst, $src}", []>;
338 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
339 "mov{w}\t{$src, $dst|$dst, $src}", []>;
340 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
341 "mov{w}\t{$src, $dst|$dst, $src}", []>;
343 // Sign/Zero extenders
345 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
346 // operand, which makes it a rare instruction with an 8-bit register
347 // operand that can never access an h register. If support for h registers
348 // were generalized, this would require a special register class.
349 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
350 "movs{bq|x}\t{$src, $dst|$dst, $src}",
351 [(set GR64:$dst, (sext GR8:$src))]>, TB;
352 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
353 "movs{bq|x}\t{$src, $dst|$dst, $src}",
354 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
355 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
356 "movs{wq|x}\t{$src, $dst|$dst, $src}",
357 [(set GR64:$dst, (sext GR16:$src))]>, TB;
358 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
359 "movs{wq|x}\t{$src, $dst|$dst, $src}",
360 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
361 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
362 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
363 [(set GR64:$dst, (sext GR32:$src))]>;
364 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
365 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
366 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
368 // Use movzbl instead of movzbq when the destination is a register; it's
369 // equivalent due to implicit zero-extending, and it has a smaller encoding.
370 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
371 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
372 [(set GR64:$dst, (zext GR8:$src))]>, TB;
373 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
374 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
375 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
376 // Use movzwl instead of movzwq when the destination is a register; it's
377 // equivalent due to implicit zero-extending, and it has a smaller encoding.
378 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
379 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
380 [(set GR64:$dst, (zext GR16:$src))]>, TB;
381 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
382 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
383 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
385 // There's no movzlq instruction, but movl can be used for this purpose, using
386 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
387 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
388 // zero-extension, however this isn't possible when the 32-bit value is
389 // defined by a truncate or is copied from something where the high bits aren't
390 // necessarily all zero. In such cases, we fall back to these explicit zext
392 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
393 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
394 [(set GR64:$dst, (zext GR32:$src))]>;
395 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
396 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
397 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
399 // Any instruction that defines a 32-bit result leaves the high half of the
400 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
401 // be copying from a truncate. And x86's cmov doesn't do anything if the
402 // condition is false. But any other 32-bit operation will zero-extend
404 def def32 : PatLeaf<(i32 GR32:$src), [{
405 return N->getOpcode() != ISD::TRUNCATE &&
406 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
407 N->getOpcode() != ISD::CopyFromReg &&
408 N->getOpcode() != X86ISD::CMOV;
411 // In the case of a 32-bit def that is known to implicitly zero-extend,
412 // we can use a SUBREG_TO_REG.
413 def : Pat<(i64 (zext def32:$src)),
414 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
416 let neverHasSideEffects = 1 in {
417 let Defs = [RAX], Uses = [EAX] in
418 def CDQE : RI<0x98, RawFrm, (outs), (ins),
419 "{cltq|cdqe}", []>; // RAX = signext(EAX)
421 let Defs = [RAX,RDX], Uses = [RAX] in
422 def CQO : RI<0x99, RawFrm, (outs), (ins),
423 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
426 //===----------------------------------------------------------------------===//
427 // Arithmetic Instructions...
430 let Defs = [EFLAGS] in {
432 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
433 "add{q}\t{$src, %rax|%rax, $src}", []>;
435 let isTwoAddress = 1 in {
436 let isConvertibleToThreeAddress = 1 in {
437 let isCommutable = 1 in
438 // Register-Register Addition
439 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
440 "add{q}\t{$src2, $dst|$dst, $src2}",
441 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
444 // Register-Integer Addition
445 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
446 "add{q}\t{$src2, $dst|$dst, $src2}",
447 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
449 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
450 "add{q}\t{$src2, $dst|$dst, $src2}",
451 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
453 } // isConvertibleToThreeAddress
455 // Register-Memory Addition
456 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
457 "add{q}\t{$src2, $dst|$dst, $src2}",
458 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
461 // Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
462 // differently encoded.
463 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
464 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
468 // Memory-Register Addition
469 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
470 "add{q}\t{$src2, $dst|$dst, $src2}",
471 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
473 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
474 "add{q}\t{$src2, $dst|$dst, $src2}",
475 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
477 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
478 "add{q}\t{$src2, $dst|$dst, $src2}",
479 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
482 let Uses = [EFLAGS] in {
484 def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
485 "adc{q}\t{$src, %rax|%rax, $src}", []>;
487 let isTwoAddress = 1 in {
488 let isCommutable = 1 in
489 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
490 "adc{q}\t{$src2, $dst|$dst, $src2}",
491 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
493 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
494 "adc{q}\t{$src2, $dst|$dst, $src2}",
495 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
497 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
498 "adc{q}\t{$src2, $dst|$dst, $src2}",
499 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
500 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
501 "adc{q}\t{$src2, $dst|$dst, $src2}",
502 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
505 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
506 "adc{q}\t{$src2, $dst|$dst, $src2}",
507 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
508 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
509 "adc{q}\t{$src2, $dst|$dst, $src2}",
510 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
511 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
512 "adc{q}\t{$src2, $dst|$dst, $src2}",
513 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
516 let isTwoAddress = 1 in {
517 // Register-Register Subtraction
518 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
519 "sub{q}\t{$src2, $dst|$dst, $src2}",
520 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
523 // Register-Memory Subtraction
524 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
525 "sub{q}\t{$src2, $dst|$dst, $src2}",
526 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
529 // Register-Integer Subtraction
530 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
531 (ins GR64:$src1, i64i8imm:$src2),
532 "sub{q}\t{$src2, $dst|$dst, $src2}",
533 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
535 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
536 (ins GR64:$src1, i64i32imm:$src2),
537 "sub{q}\t{$src2, $dst|$dst, $src2}",
538 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
542 def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
543 "sub{q}\t{$src, %rax|%rax, $src}", []>;
545 // Memory-Register Subtraction
546 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
547 "sub{q}\t{$src2, $dst|$dst, $src2}",
548 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
551 // Memory-Integer Subtraction
552 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
553 "sub{q}\t{$src2, $dst|$dst, $src2}",
554 [(store (sub (load addr:$dst), i64immSExt8:$src2),
557 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
558 "sub{q}\t{$src2, $dst|$dst, $src2}",
559 [(store (sub (load addr:$dst), i64immSExt32:$src2),
563 let Uses = [EFLAGS] in {
564 let isTwoAddress = 1 in {
565 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
566 "sbb{q}\t{$src2, $dst|$dst, $src2}",
567 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
569 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
570 "sbb{q}\t{$src2, $dst|$dst, $src2}",
571 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
573 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
574 "sbb{q}\t{$src2, $dst|$dst, $src2}",
575 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
576 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
577 "sbb{q}\t{$src2, $dst|$dst, $src2}",
578 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
581 def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
582 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
584 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
585 "sbb{q}\t{$src2, $dst|$dst, $src2}",
586 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
587 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
588 "sbb{q}\t{$src2, $dst|$dst, $src2}",
589 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
590 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
591 "sbb{q}\t{$src2, $dst|$dst, $src2}",
592 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
596 // Unsigned multiplication
597 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
598 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
599 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
601 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
602 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
604 // Signed multiplication
605 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
606 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
608 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
609 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
612 let Defs = [EFLAGS] in {
613 let isTwoAddress = 1 in {
614 let isCommutable = 1 in
615 // Register-Register Signed Integer Multiplication
616 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
617 (ins GR64:$src1, GR64:$src2),
618 "imul{q}\t{$src2, $dst|$dst, $src2}",
619 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
620 (implicit EFLAGS)]>, TB;
622 // Register-Memory Signed Integer Multiplication
623 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
624 (ins GR64:$src1, i64mem:$src2),
625 "imul{q}\t{$src2, $dst|$dst, $src2}",
626 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
627 (implicit EFLAGS)]>, TB;
630 // Suprisingly enough, these are not two address instructions!
632 // Register-Integer Signed Integer Multiplication
633 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
634 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
635 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
636 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
638 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
639 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
640 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
641 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
644 // Memory-Integer Signed Integer Multiplication
645 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
646 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
647 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
648 [(set GR64:$dst, (mul (load addr:$src1),
651 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
652 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
653 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
654 [(set GR64:$dst, (mul (load addr:$src1),
655 i64immSExt32:$src2)),
659 // Unsigned division / remainder
660 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
661 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
663 // Signed division / remainder
664 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
665 "idiv{q}\t$src", []>;
667 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
669 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
670 "idiv{q}\t$src", []>;
674 // Unary instructions
675 let Defs = [EFLAGS], CodeSize = 2 in {
676 let isTwoAddress = 1 in
677 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
678 [(set GR64:$dst, (ineg GR64:$src)),
680 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
681 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
684 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
685 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
686 [(set GR64:$dst, (add GR64:$src, 1)),
688 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
689 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
692 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
693 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
694 [(set GR64:$dst, (add GR64:$src, -1)),
696 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
697 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
700 // In 64-bit mode, single byte INC and DEC cannot be encoded.
701 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
702 // Can transform into LEA.
703 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
704 [(set GR16:$dst, (add GR16:$src, 1)),
706 OpSize, Requires<[In64BitMode]>;
707 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
708 [(set GR32:$dst, (add GR32:$src, 1)),
710 Requires<[In64BitMode]>;
711 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
712 [(set GR16:$dst, (add GR16:$src, -1)),
714 OpSize, Requires<[In64BitMode]>;
715 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
716 [(set GR32:$dst, (add GR32:$src, -1)),
718 Requires<[In64BitMode]>;
719 } // isConvertibleToThreeAddress
721 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
722 // how to unfold them.
723 let isTwoAddress = 0, CodeSize = 2 in {
724 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
725 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
727 OpSize, Requires<[In64BitMode]>;
728 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
729 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
731 Requires<[In64BitMode]>;
732 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
733 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
735 OpSize, Requires<[In64BitMode]>;
736 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
737 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
739 Requires<[In64BitMode]>;
741 } // Defs = [EFLAGS], CodeSize
744 let Defs = [EFLAGS] in {
745 // Shift instructions
746 let isTwoAddress = 1 in {
748 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
749 "shl{q}\t{%cl, $dst|$dst, %CL}",
750 [(set GR64:$dst, (shl GR64:$src, CL))]>;
751 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
752 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
753 "shl{q}\t{$src2, $dst|$dst, $src2}",
754 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
755 // NOTE: We don't include patterns for shifts of a register by one, because
756 // 'add reg,reg' is cheaper.
757 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
762 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
763 "shl{q}\t{%cl, $dst|$dst, %CL}",
764 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
765 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
766 "shl{q}\t{$src, $dst|$dst, $src}",
767 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
768 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
770 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
772 let isTwoAddress = 1 in {
774 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
775 "shr{q}\t{%cl, $dst|$dst, %CL}",
776 [(set GR64:$dst, (srl GR64:$src, CL))]>;
777 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
778 "shr{q}\t{$src2, $dst|$dst, $src2}",
779 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
780 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
782 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
786 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
787 "shr{q}\t{%cl, $dst|$dst, %CL}",
788 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
789 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
790 "shr{q}\t{$src, $dst|$dst, $src}",
791 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
792 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
794 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
796 let isTwoAddress = 1 in {
798 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
799 "sar{q}\t{%cl, $dst|$dst, %CL}",
800 [(set GR64:$dst, (sra GR64:$src, CL))]>;
801 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
802 "sar{q}\t{$src2, $dst|$dst, $src2}",
803 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
804 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
806 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
810 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
811 "sar{q}\t{%cl, $dst|$dst, %CL}",
812 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
813 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
814 "sar{q}\t{$src, $dst|$dst, $src}",
815 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
816 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
818 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
820 // Rotate instructions
822 let isTwoAddress = 1 in {
823 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
824 "rcl{q}\t{1, $dst|$dst, 1}", []>;
825 def RCL64m1 : RI<0xD1, MRM2m, (outs i64mem:$dst), (ins i64mem:$src),
826 "rcl{q}\t{1, $dst|$dst, 1}", []>;
828 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
829 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
830 def RCL64mCL : RI<0xD3, MRM2m, (outs i64mem:$dst), (ins i64mem:$src),
831 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
833 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
834 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
835 def RCL64mi : RIi8<0xC1, MRM2m, (outs i64mem:$dst), (ins i64mem:$src, i8imm:$cnt),
836 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
838 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
839 "rcr{q}\t{1, $dst|$dst, 1}", []>;
840 def RCR64m1 : RI<0xD1, MRM3m, (outs i64mem:$dst), (ins i64mem:$src),
841 "rcr{q}\t{1, $dst|$dst, 1}", []>;
843 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
844 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
845 def RCR64mCL : RI<0xD3, MRM3m, (outs i64mem:$dst), (ins i64mem:$src),
846 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
848 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
849 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
850 def RCR64mi : RIi8<0xC1, MRM3m, (outs i64mem:$dst), (ins i64mem:$src, i8imm:$cnt),
851 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
854 let isTwoAddress = 1 in {
856 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
857 "rol{q}\t{%cl, $dst|$dst, %CL}",
858 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
859 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
860 "rol{q}\t{$src2, $dst|$dst, $src2}",
861 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
862 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
864 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
868 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
869 "rol{q}\t{%cl, $dst|$dst, %CL}",
870 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
871 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
872 "rol{q}\t{$src, $dst|$dst, $src}",
873 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
874 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
876 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
878 let isTwoAddress = 1 in {
880 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
881 "ror{q}\t{%cl, $dst|$dst, %CL}",
882 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
883 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
884 "ror{q}\t{$src2, $dst|$dst, $src2}",
885 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
886 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
888 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
892 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
893 "ror{q}\t{%cl, $dst|$dst, %CL}",
894 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
895 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
896 "ror{q}\t{$src, $dst|$dst, $src}",
897 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
898 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
900 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
902 // Double shift instructions (generalizations of rotate)
903 let isTwoAddress = 1 in {
905 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
906 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
907 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
908 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
909 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
910 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
913 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
914 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
915 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
916 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
917 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
920 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
921 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
922 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
923 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
930 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
931 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
932 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
934 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
935 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
936 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
939 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
940 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
941 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
942 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
943 (i8 imm:$src3)), addr:$dst)]>,
945 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
946 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
947 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
948 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
949 (i8 imm:$src3)), addr:$dst)]>,
953 //===----------------------------------------------------------------------===//
954 // Logical Instructions...
957 let isTwoAddress = 1 , AddedComplexity = 15 in
958 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
959 [(set GR64:$dst, (not GR64:$src))]>;
960 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
961 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
963 let Defs = [EFLAGS] in {
964 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
965 "and{q}\t{$src, %rax|%rax, $src}", []>;
967 let isTwoAddress = 1 in {
968 let isCommutable = 1 in
969 def AND64rr : RI<0x21, MRMDestReg,
970 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
971 "and{q}\t{$src2, $dst|$dst, $src2}",
972 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
974 def AND64rm : RI<0x23, MRMSrcMem,
975 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
976 "and{q}\t{$src2, $dst|$dst, $src2}",
977 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
979 def AND64ri8 : RIi8<0x83, MRM4r,
980 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
981 "and{q}\t{$src2, $dst|$dst, $src2}",
982 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
984 def AND64ri32 : RIi32<0x81, MRM4r,
985 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
986 "and{q}\t{$src2, $dst|$dst, $src2}",
987 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
991 def AND64mr : RI<0x21, MRMDestMem,
992 (outs), (ins i64mem:$dst, GR64:$src),
993 "and{q}\t{$src, $dst|$dst, $src}",
994 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
996 def AND64mi8 : RIi8<0x83, MRM4m,
997 (outs), (ins i64mem:$dst, i64i8imm :$src),
998 "and{q}\t{$src, $dst|$dst, $src}",
999 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1000 (implicit EFLAGS)]>;
1001 def AND64mi32 : RIi32<0x81, MRM4m,
1002 (outs), (ins i64mem:$dst, i64i32imm:$src),
1003 "and{q}\t{$src, $dst|$dst, $src}",
1004 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1005 (implicit EFLAGS)]>;
1007 let isTwoAddress = 1 in {
1008 let isCommutable = 1 in
1009 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1010 "or{q}\t{$src2, $dst|$dst, $src2}",
1011 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
1012 (implicit EFLAGS)]>;
1013 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1014 "or{q}\t{$src2, $dst|$dst, $src2}",
1015 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
1016 (implicit EFLAGS)]>;
1017 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1018 "or{q}\t{$src2, $dst|$dst, $src2}",
1019 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
1020 (implicit EFLAGS)]>;
1021 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1022 "or{q}\t{$src2, $dst|$dst, $src2}",
1023 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
1024 (implicit EFLAGS)]>;
1027 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1028 "or{q}\t{$src, $dst|$dst, $src}",
1029 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1030 (implicit EFLAGS)]>;
1031 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1032 "or{q}\t{$src, $dst|$dst, $src}",
1033 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1034 (implicit EFLAGS)]>;
1035 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1036 "or{q}\t{$src, $dst|$dst, $src}",
1037 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1038 (implicit EFLAGS)]>;
1040 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1041 "or{q}\t{$src, %rax|%rax, $src}", []>;
1043 let isTwoAddress = 1 in {
1044 let isCommutable = 1 in
1045 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1046 "xor{q}\t{$src2, $dst|$dst, $src2}",
1047 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1048 (implicit EFLAGS)]>;
1049 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1050 "xor{q}\t{$src2, $dst|$dst, $src2}",
1051 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1052 (implicit EFLAGS)]>;
1053 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1054 "xor{q}\t{$src2, $dst|$dst, $src2}",
1055 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1056 (implicit EFLAGS)]>;
1057 def XOR64ri32 : RIi32<0x81, MRM6r,
1058 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1059 "xor{q}\t{$src2, $dst|$dst, $src2}",
1060 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1061 (implicit EFLAGS)]>;
1064 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1065 "xor{q}\t{$src, $dst|$dst, $src}",
1066 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1067 (implicit EFLAGS)]>;
1068 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1069 "xor{q}\t{$src, $dst|$dst, $src}",
1070 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1071 (implicit EFLAGS)]>;
1072 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1073 "xor{q}\t{$src, $dst|$dst, $src}",
1074 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1075 (implicit EFLAGS)]>;
1077 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1078 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1080 } // Defs = [EFLAGS]
1082 //===----------------------------------------------------------------------===//
1083 // Comparison Instructions...
1086 // Integer comparison
1087 let Defs = [EFLAGS] in {
1088 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1089 "test{q}\t{$src, %rax|%rax, $src}", []>;
1090 let isCommutable = 1 in
1091 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1092 "test{q}\t{$src2, $src1|$src1, $src2}",
1093 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1094 (implicit EFLAGS)]>;
1095 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1096 "test{q}\t{$src2, $src1|$src1, $src2}",
1097 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1098 (implicit EFLAGS)]>;
1099 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1100 (ins GR64:$src1, i64i32imm:$src2),
1101 "test{q}\t{$src2, $src1|$src1, $src2}",
1102 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1103 (implicit EFLAGS)]>;
1104 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1105 (ins i64mem:$src1, i64i32imm:$src2),
1106 "test{q}\t{$src2, $src1|$src1, $src2}",
1107 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1108 (implicit EFLAGS)]>;
1111 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1112 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1113 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1114 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1115 [(X86cmp GR64:$src1, GR64:$src2),
1116 (implicit EFLAGS)]>;
1117 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1118 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1119 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1120 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1121 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1122 (implicit EFLAGS)]>;
1123 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1124 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1125 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1126 (implicit EFLAGS)]>;
1127 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1128 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1129 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1130 (implicit EFLAGS)]>;
1131 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1132 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1133 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1134 (implicit EFLAGS)]>;
1135 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1136 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1137 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1138 (implicit EFLAGS)]>;
1139 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1140 (ins i64mem:$src1, i64i32imm:$src2),
1141 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1142 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1143 (implicit EFLAGS)]>;
1144 } // Defs = [EFLAGS]
1147 // TODO: BTC, BTR, and BTS
1148 let Defs = [EFLAGS] in {
1149 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1150 "bt{q}\t{$src2, $src1|$src1, $src2}",
1151 [(X86bt GR64:$src1, GR64:$src2),
1152 (implicit EFLAGS)]>, TB;
1154 // Unlike with the register+register form, the memory+register form of the
1155 // bt instruction does not ignore the high bits of the index. From ISel's
1156 // perspective, this is pretty bizarre. Disable these instructions for now.
1157 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1158 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1159 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1160 // (implicit EFLAGS)]>, TB;
1162 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1163 "bt{q}\t{$src2, $src1|$src1, $src2}",
1164 [(X86bt GR64:$src1, i64immSExt8:$src2),
1165 (implicit EFLAGS)]>, TB;
1166 // Note that these instructions don't need FastBTMem because that
1167 // only applies when the other operand is in a register. When it's
1168 // an immediate, bt is still fast.
1169 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1170 "bt{q}\t{$src2, $src1|$src1, $src2}",
1171 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1172 (implicit EFLAGS)]>, TB;
1173 } // Defs = [EFLAGS]
1175 // Conditional moves
1176 let Uses = [EFLAGS], isTwoAddress = 1 in {
1177 let isCommutable = 1 in {
1178 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1179 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1180 "cmovb\t{$src2, $dst|$dst, $src2}",
1181 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1182 X86_COND_B, EFLAGS))]>, TB;
1183 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1184 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1185 "cmovae\t{$src2, $dst|$dst, $src2}",
1186 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1187 X86_COND_AE, EFLAGS))]>, TB;
1188 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1189 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1190 "cmove\t{$src2, $dst|$dst, $src2}",
1191 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1192 X86_COND_E, EFLAGS))]>, TB;
1193 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1194 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1195 "cmovne\t{$src2, $dst|$dst, $src2}",
1196 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1197 X86_COND_NE, EFLAGS))]>, TB;
1198 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1199 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1200 "cmovbe\t{$src2, $dst|$dst, $src2}",
1201 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1202 X86_COND_BE, EFLAGS))]>, TB;
1203 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1204 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1205 "cmova\t{$src2, $dst|$dst, $src2}",
1206 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1207 X86_COND_A, EFLAGS))]>, TB;
1208 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1209 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1210 "cmovl\t{$src2, $dst|$dst, $src2}",
1211 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1212 X86_COND_L, EFLAGS))]>, TB;
1213 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1214 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1215 "cmovge\t{$src2, $dst|$dst, $src2}",
1216 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1217 X86_COND_GE, EFLAGS))]>, TB;
1218 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1219 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1220 "cmovle\t{$src2, $dst|$dst, $src2}",
1221 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1222 X86_COND_LE, EFLAGS))]>, TB;
1223 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1224 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1225 "cmovg\t{$src2, $dst|$dst, $src2}",
1226 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1227 X86_COND_G, EFLAGS))]>, TB;
1228 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1229 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1230 "cmovs\t{$src2, $dst|$dst, $src2}",
1231 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1232 X86_COND_S, EFLAGS))]>, TB;
1233 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1234 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1235 "cmovns\t{$src2, $dst|$dst, $src2}",
1236 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1237 X86_COND_NS, EFLAGS))]>, TB;
1238 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1239 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1240 "cmovp\t{$src2, $dst|$dst, $src2}",
1241 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1242 X86_COND_P, EFLAGS))]>, TB;
1243 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1244 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1245 "cmovnp\t{$src2, $dst|$dst, $src2}",
1246 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1247 X86_COND_NP, EFLAGS))]>, TB;
1248 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1249 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1250 "cmovo\t{$src2, $dst|$dst, $src2}",
1251 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1252 X86_COND_O, EFLAGS))]>, TB;
1253 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1254 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1255 "cmovno\t{$src2, $dst|$dst, $src2}",
1256 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1257 X86_COND_NO, EFLAGS))]>, TB;
1258 } // isCommutable = 1
1260 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1261 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1262 "cmovb\t{$src2, $dst|$dst, $src2}",
1263 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1264 X86_COND_B, EFLAGS))]>, TB;
1265 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1266 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1267 "cmovae\t{$src2, $dst|$dst, $src2}",
1268 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1269 X86_COND_AE, EFLAGS))]>, TB;
1270 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1271 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1272 "cmove\t{$src2, $dst|$dst, $src2}",
1273 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1274 X86_COND_E, EFLAGS))]>, TB;
1275 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1276 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1277 "cmovne\t{$src2, $dst|$dst, $src2}",
1278 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1279 X86_COND_NE, EFLAGS))]>, TB;
1280 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1281 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1282 "cmovbe\t{$src2, $dst|$dst, $src2}",
1283 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1284 X86_COND_BE, EFLAGS))]>, TB;
1285 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1286 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1287 "cmova\t{$src2, $dst|$dst, $src2}",
1288 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1289 X86_COND_A, EFLAGS))]>, TB;
1290 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1291 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1292 "cmovl\t{$src2, $dst|$dst, $src2}",
1293 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1294 X86_COND_L, EFLAGS))]>, TB;
1295 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1296 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1297 "cmovge\t{$src2, $dst|$dst, $src2}",
1298 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1299 X86_COND_GE, EFLAGS))]>, TB;
1300 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1301 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1302 "cmovle\t{$src2, $dst|$dst, $src2}",
1303 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1304 X86_COND_LE, EFLAGS))]>, TB;
1305 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1306 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1307 "cmovg\t{$src2, $dst|$dst, $src2}",
1308 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1309 X86_COND_G, EFLAGS))]>, TB;
1310 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1311 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1312 "cmovs\t{$src2, $dst|$dst, $src2}",
1313 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1314 X86_COND_S, EFLAGS))]>, TB;
1315 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1316 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1317 "cmovns\t{$src2, $dst|$dst, $src2}",
1318 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1319 X86_COND_NS, EFLAGS))]>, TB;
1320 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1321 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1322 "cmovp\t{$src2, $dst|$dst, $src2}",
1323 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1324 X86_COND_P, EFLAGS))]>, TB;
1325 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1326 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1327 "cmovnp\t{$src2, $dst|$dst, $src2}",
1328 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1329 X86_COND_NP, EFLAGS))]>, TB;
1330 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1331 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1332 "cmovo\t{$src2, $dst|$dst, $src2}",
1333 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1334 X86_COND_O, EFLAGS))]>, TB;
1335 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1336 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1337 "cmovno\t{$src2, $dst|$dst, $src2}",
1338 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1339 X86_COND_NO, EFLAGS))]>, TB;
1342 //===----------------------------------------------------------------------===//
1343 // Conversion Instructions...
1346 // f64 -> signed i64
1347 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1348 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1350 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1351 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1352 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1353 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1354 (load addr:$src)))]>;
1355 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1356 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1357 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1358 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1359 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1360 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1361 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1362 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1364 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1365 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1366 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1368 (int_x86_sse2_cvttsd2si64
1369 (load addr:$src)))]>;
1371 // Signed i64 -> f64
1372 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1373 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1374 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1375 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1376 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1377 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1379 let isTwoAddress = 1 in {
1380 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1381 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1382 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1384 (int_x86_sse2_cvtsi642sd VR128:$src1,
1386 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1387 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1388 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1390 (int_x86_sse2_cvtsi642sd VR128:$src1,
1391 (loadi64 addr:$src2)))]>;
1394 // Signed i64 -> f32
1395 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1396 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1397 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1398 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1399 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1400 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1402 let isTwoAddress = 1 in {
1403 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1404 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1405 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1407 (int_x86_sse_cvtsi642ss VR128:$src1,
1409 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1410 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1411 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1413 (int_x86_sse_cvtsi642ss VR128:$src1,
1414 (loadi64 addr:$src2)))]>;
1417 // f32 -> signed i64
1418 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1419 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1421 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1422 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1423 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1424 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1425 (load addr:$src)))]>;
1426 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1427 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1428 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1429 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1430 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1431 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1432 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1433 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1435 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1436 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1437 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1439 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1441 //===----------------------------------------------------------------------===//
1442 // Alias Instructions
1443 //===----------------------------------------------------------------------===//
1445 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1446 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1448 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1449 // when we have a better way to specify isel priority.
1450 let AddedComplexity = 1 in
1452 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1455 // Materialize i64 constant where top 32-bits are zero.
1456 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1457 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1458 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1459 [(set GR64:$dst, i64immZExt32:$src)]>;
1461 //===----------------------------------------------------------------------===//
1462 // Thread Local Storage Instructions
1463 //===----------------------------------------------------------------------===//
1465 // All calls clobber the non-callee saved registers. RSP is marked as
1466 // a use to prevent stack-pointer assignments that appear immediately
1467 // before calls from potentially appearing dead.
1468 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1469 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1470 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1471 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1472 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1474 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1476 "leaq\t$sym(%rip), %rdi; "
1479 "call\t__tls_get_addr@PLT",
1480 [(X86tlsaddr tls64addr:$sym)]>,
1481 Requires<[In64BitMode]>;
1483 let AddedComplexity = 5, isCodeGenOnly = 1 in
1484 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1485 "movq\t%gs:$src, $dst",
1486 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1488 let AddedComplexity = 5, isCodeGenOnly = 1 in
1489 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1490 "movq\t%fs:$src, $dst",
1491 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1493 //===----------------------------------------------------------------------===//
1494 // Atomic Instructions
1495 //===----------------------------------------------------------------------===//
1497 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1498 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1500 "cmpxchgq\t$swap,$ptr",
1501 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1504 let Constraints = "$val = $dst" in {
1505 let Defs = [EFLAGS] in
1506 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1509 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1512 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1514 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1517 // Optimized codegen when the non-memory output is not used.
1518 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1519 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1521 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1522 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1523 (ins i64mem:$dst, i64i8imm :$src2),
1525 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1526 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1527 (ins i64mem:$dst, i64i32imm :$src2),
1529 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1530 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1532 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1533 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1534 (ins i64mem:$dst, i64i8imm :$src2),
1536 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1537 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1538 (ins i64mem:$dst, i64i32imm:$src2),
1540 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1541 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1543 "inc{q}\t$dst", []>, LOCK;
1544 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1546 "dec{q}\t$dst", []>, LOCK;
1548 // Atomic exchange, and, or, xor
1549 let Constraints = "$val = $dst", Defs = [EFLAGS],
1550 usesCustomDAGSchedInserter = 1 in {
1551 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1552 "#ATOMAND64 PSEUDO!",
1553 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1554 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1555 "#ATOMOR64 PSEUDO!",
1556 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1557 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1558 "#ATOMXOR64 PSEUDO!",
1559 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1560 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1561 "#ATOMNAND64 PSEUDO!",
1562 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1563 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1564 "#ATOMMIN64 PSEUDO!",
1565 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1566 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1567 "#ATOMMAX64 PSEUDO!",
1568 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1569 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1570 "#ATOMUMIN64 PSEUDO!",
1571 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1572 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1573 "#ATOMUMAX64 PSEUDO!",
1574 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1577 // Segmentation support instructions
1579 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1580 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1581 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1582 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1583 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1585 // String manipulation instructions
1587 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1589 //===----------------------------------------------------------------------===//
1590 // Non-Instruction Patterns
1591 //===----------------------------------------------------------------------===//
1593 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1594 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1595 // 'movabs' predicate should handle this sort of thing.
1596 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1597 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1598 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1599 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1600 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1601 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1602 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1603 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1605 // In static codegen with small code model, we can get the address of a label
1606 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1607 // the MOV64ri64i32 should accept these.
1608 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1609 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1610 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1611 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1612 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1613 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1614 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1615 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1617 // In kernel code model, we can get the address of a label
1618 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1619 // the MOV64ri32 should accept these.
1620 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1621 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1622 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1623 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1624 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1625 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1626 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1627 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1629 // If we have small model and -static mode, it is safe to store global addresses
1630 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1631 // for MOV64mi32 should handle this sort of thing.
1632 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1633 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1634 Requires<[NearData, IsStatic]>;
1635 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1636 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1637 Requires<[NearData, IsStatic]>;
1638 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1639 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1640 Requires<[NearData, IsStatic]>;
1641 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1642 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1643 Requires<[NearData, IsStatic]>;
1646 // Direct PC relative function call for small code model. 32-bit displacement
1647 // sign extended to 64-bit.
1648 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1649 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1650 def : Pat<(X86call (i64 texternalsym:$dst)),
1651 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1653 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1654 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1655 def : Pat<(X86call (i64 texternalsym:$dst)),
1656 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1659 def : Pat<(X86tcret GR64:$dst, imm:$off),
1660 (TCRETURNri64 GR64:$dst, imm:$off)>;
1662 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1663 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1665 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1666 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1670 // TEST R,R is smaller than CMP R,0
1671 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1672 (TEST64rr GR64:$src1, GR64:$src1)>;
1674 // Conditional moves with folded loads with operands swapped and conditions
1676 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1677 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1678 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1679 (CMOVB64rm GR64:$src2, addr:$src1)>;
1680 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1681 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1682 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1683 (CMOVE64rm GR64:$src2, addr:$src1)>;
1684 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1685 (CMOVA64rm GR64:$src2, addr:$src1)>;
1686 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1687 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1688 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1689 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1690 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1691 (CMOVL64rm GR64:$src2, addr:$src1)>;
1692 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1693 (CMOVG64rm GR64:$src2, addr:$src1)>;
1694 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1695 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1696 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1697 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1698 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1699 (CMOVP64rm GR64:$src2, addr:$src1)>;
1700 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1701 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1702 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1703 (CMOVS64rm GR64:$src2, addr:$src1)>;
1704 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1705 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1706 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1707 (CMOVO64rm GR64:$src2, addr:$src1)>;
1709 // zextload bool -> zextload byte
1710 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1713 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1714 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1715 // partial-register updates.
1716 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1717 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1718 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1719 // For other extloads, use subregs, since the high contents of the register are
1720 // defined after an extload.
1721 def : Pat<(extloadi64i32 addr:$src),
1722 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1725 // anyext. Define these to do an explicit zero-extend to
1726 // avoid partial-register updates.
1727 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1728 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1729 def : Pat<(i64 (anyext GR32:$src)),
1730 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1732 //===----------------------------------------------------------------------===//
1734 //===----------------------------------------------------------------------===//
1736 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1737 // +128 doesn't, so in this special case use a sub instead of an add.
1738 def : Pat<(add GR64:$src1, 128),
1739 (SUB64ri8 GR64:$src1, -128)>;
1740 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1741 (SUB64mi8 addr:$dst, -128)>;
1743 // The same trick applies for 32-bit immediate fields in 64-bit
1745 def : Pat<(add GR64:$src1, 0x0000000080000000),
1746 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1747 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1748 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1750 // r & (2^32-1) ==> movz
1751 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1752 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1753 // r & (2^16-1) ==> movz
1754 def : Pat<(and GR64:$src, 0xffff),
1755 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1756 // r & (2^8-1) ==> movz
1757 def : Pat<(and GR64:$src, 0xff),
1758 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1759 // r & (2^8-1) ==> movz
1760 def : Pat<(and GR32:$src1, 0xff),
1761 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1762 Requires<[In64BitMode]>;
1763 // r & (2^8-1) ==> movz
1764 def : Pat<(and GR16:$src1, 0xff),
1765 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1766 Requires<[In64BitMode]>;
1768 // sext_inreg patterns
1769 def : Pat<(sext_inreg GR64:$src, i32),
1770 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1771 def : Pat<(sext_inreg GR64:$src, i16),
1772 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1773 def : Pat<(sext_inreg GR64:$src, i8),
1774 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1775 def : Pat<(sext_inreg GR32:$src, i8),
1776 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1777 Requires<[In64BitMode]>;
1778 def : Pat<(sext_inreg GR16:$src, i8),
1779 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1780 Requires<[In64BitMode]>;
1783 def : Pat<(i32 (trunc GR64:$src)),
1784 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1785 def : Pat<(i16 (trunc GR64:$src)),
1786 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1787 def : Pat<(i8 (trunc GR64:$src)),
1788 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1789 def : Pat<(i8 (trunc GR32:$src)),
1790 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1791 Requires<[In64BitMode]>;
1792 def : Pat<(i8 (trunc GR16:$src)),
1793 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1794 Requires<[In64BitMode]>;
1796 // h-register tricks.
1797 // For now, be conservative on x86-64 and use an h-register extract only if the
1798 // value is immediately zero-extended or stored, which are somewhat common
1799 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1800 // from being allocated in the same instruction as the h register, as there's
1801 // currently no way to describe this requirement to the register allocator.
1803 // h-register extract and zero-extend.
1804 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1808 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1809 x86_subreg_8bit_hi)),
1811 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1813 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1814 x86_subreg_8bit_hi))>,
1815 Requires<[In64BitMode]>;
1816 def : Pat<(srl_su GR16:$src, (i8 8)),
1819 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1820 x86_subreg_8bit_hi)),
1822 Requires<[In64BitMode]>;
1823 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1825 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1826 x86_subreg_8bit_hi))>,
1827 Requires<[In64BitMode]>;
1828 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1830 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1831 x86_subreg_8bit_hi))>,
1832 Requires<[In64BitMode]>;
1833 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1837 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1838 x86_subreg_8bit_hi)),
1840 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1844 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1845 x86_subreg_8bit_hi)),
1848 // h-register extract and store.
1849 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1852 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1853 x86_subreg_8bit_hi))>;
1854 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1857 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1858 x86_subreg_8bit_hi))>,
1859 Requires<[In64BitMode]>;
1860 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1863 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1864 x86_subreg_8bit_hi))>,
1865 Requires<[In64BitMode]>;
1867 // (shl x, 1) ==> (add x, x)
1868 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1870 // (shl x (and y, 63)) ==> (shl x, y)
1871 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1872 (SHL64rCL GR64:$src1)>;
1873 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1874 (SHL64mCL addr:$dst)>;
1876 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1877 (SHR64rCL GR64:$src1)>;
1878 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1879 (SHR64mCL addr:$dst)>;
1881 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1882 (SAR64rCL GR64:$src1)>;
1883 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1884 (SAR64mCL addr:$dst)>;
1886 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1887 def : Pat<(or (srl GR64:$src1, CL:$amt),
1888 (shl GR64:$src2, (sub 64, CL:$amt))),
1889 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1891 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1892 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1893 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1895 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1896 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1897 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1899 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1900 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1902 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1904 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1905 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1907 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1908 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1909 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1911 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1912 def : Pat<(or (shl GR64:$src1, CL:$amt),
1913 (srl GR64:$src2, (sub 64, CL:$amt))),
1914 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1916 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1917 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1918 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1920 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1921 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1922 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1924 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1925 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1927 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1929 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1930 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1932 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1933 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1934 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1936 // X86 specific add which produces a flag.
1937 def : Pat<(addc GR64:$src1, GR64:$src2),
1938 (ADD64rr GR64:$src1, GR64:$src2)>;
1939 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1940 (ADD64rm GR64:$src1, addr:$src2)>;
1941 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1942 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1943 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1944 (ADD64ri32 GR64:$src1, imm:$src2)>;
1946 def : Pat<(subc GR64:$src1, GR64:$src2),
1947 (SUB64rr GR64:$src1, GR64:$src2)>;
1948 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1949 (SUB64rm GR64:$src1, addr:$src2)>;
1950 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1951 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1952 def : Pat<(subc GR64:$src1, imm:$src2),
1953 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1955 //===----------------------------------------------------------------------===//
1956 // EFLAGS-defining Patterns
1957 //===----------------------------------------------------------------------===//
1959 // Register-Register Addition with EFLAGS result
1960 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1962 (ADD64rr GR64:$src1, GR64:$src2)>;
1964 // Register-Integer Addition with EFLAGS result
1965 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1967 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1968 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1970 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1972 // Register-Memory Addition with EFLAGS result
1973 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1975 (ADD64rm GR64:$src1, addr:$src2)>;
1977 // Memory-Register Addition with EFLAGS result
1978 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1981 (ADD64mr addr:$dst, GR64:$src2)>;
1982 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1985 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1986 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1989 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1991 // Register-Register Subtraction with EFLAGS result
1992 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1994 (SUB64rr GR64:$src1, GR64:$src2)>;
1996 // Register-Memory Subtraction with EFLAGS result
1997 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1999 (SUB64rm GR64:$src1, addr:$src2)>;
2001 // Register-Integer Subtraction with EFLAGS result
2002 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
2004 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2005 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
2007 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2009 // Memory-Register Subtraction with EFLAGS result
2010 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
2013 (SUB64mr addr:$dst, GR64:$src2)>;
2015 // Memory-Integer Subtraction with EFLAGS result
2016 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2019 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
2020 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2023 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
2025 // Register-Register Signed Integer Multiplication with EFLAGS result
2026 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
2028 (IMUL64rr GR64:$src1, GR64:$src2)>;
2030 // Register-Memory Signed Integer Multiplication with EFLAGS result
2031 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
2033 (IMUL64rm GR64:$src1, addr:$src2)>;
2035 // Register-Integer Signed Integer Multiplication with EFLAGS result
2036 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
2038 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2039 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
2041 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2043 // Memory-Integer Signed Integer Multiplication with EFLAGS result
2044 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
2046 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2047 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
2049 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2051 // INC and DEC with EFLAGS result. Note that these do not set CF.
2052 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
2053 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2054 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2056 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2057 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2058 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2059 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2061 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2063 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2064 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2065 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2067 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2068 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2069 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2070 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2072 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2074 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2075 (INC64r GR64:$src)>;
2076 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2078 (INC64m addr:$dst)>;
2079 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2080 (DEC64r GR64:$src)>;
2081 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2083 (DEC64m addr:$dst)>;
2085 // Register-Register Logical Or with EFLAGS result
2086 def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
2088 (OR64rr GR64:$src1, GR64:$src2)>;
2090 // Register-Integer Logical Or with EFLAGS result
2091 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
2093 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2094 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
2096 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2098 // Register-Memory Logical Or with EFLAGS result
2099 def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
2101 (OR64rm GR64:$src1, addr:$src2)>;
2103 // Memory-Register Logical Or with EFLAGS result
2104 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
2107 (OR64mr addr:$dst, GR64:$src2)>;
2108 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2111 (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
2112 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2115 (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
2117 // Register-Register Logical XOr with EFLAGS result
2118 def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
2120 (XOR64rr GR64:$src1, GR64:$src2)>;
2122 // Register-Integer Logical XOr with EFLAGS result
2123 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
2125 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2126 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
2128 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2130 // Register-Memory Logical XOr with EFLAGS result
2131 def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
2133 (XOR64rm GR64:$src1, addr:$src2)>;
2135 // Memory-Register Logical XOr with EFLAGS result
2136 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
2139 (XOR64mr addr:$dst, GR64:$src2)>;
2140 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2143 (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2144 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2147 (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
2149 // Register-Register Logical And with EFLAGS result
2150 def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
2152 (AND64rr GR64:$src1, GR64:$src2)>;
2154 // Register-Integer Logical And with EFLAGS result
2155 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
2157 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2158 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
2160 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2162 // Register-Memory Logical And with EFLAGS result
2163 def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
2165 (AND64rm GR64:$src1, addr:$src2)>;
2167 // Memory-Register Logical And with EFLAGS result
2168 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
2171 (AND64mr addr:$dst, GR64:$src2)>;
2172 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2175 (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2176 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2179 (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
2181 //===----------------------------------------------------------------------===//
2182 // X86-64 SSE Instructions
2183 //===----------------------------------------------------------------------===//
2185 // Move instructions...
2187 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2188 "mov{d|q}\t{$src, $dst|$dst, $src}",
2190 (v2i64 (scalar_to_vector GR64:$src)))]>;
2191 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2192 "mov{d|q}\t{$src, $dst|$dst, $src}",
2193 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2196 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2197 "mov{d|q}\t{$src, $dst|$dst, $src}",
2198 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2199 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2200 "movq\t{$src, $dst|$dst, $src}",
2201 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2203 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2204 "mov{d|q}\t{$src, $dst|$dst, $src}",
2205 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2206 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2207 "movq\t{$src, $dst|$dst, $src}",
2208 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2210 //===----------------------------------------------------------------------===//
2211 // X86-64 SSE4.1 Instructions
2212 //===----------------------------------------------------------------------===//
2214 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2215 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2216 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2217 (ins VR128:$src1, i32i8imm:$src2),
2218 !strconcat(OpcodeStr,
2219 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2221 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2222 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2223 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2224 !strconcat(OpcodeStr,
2225 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2226 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2227 addr:$dst)]>, OpSize, REX_W;
2230 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2232 let isTwoAddress = 1 in {
2233 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2234 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2235 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2236 !strconcat(OpcodeStr,
2237 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2239 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2241 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2242 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2243 !strconcat(OpcodeStr,
2244 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2246 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2247 imm:$src3)))]>, OpSize, REX_W;
2251 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2253 // -disable-16bit support.
2254 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2255 (MOV16mi addr:$dst, imm:$src)>;
2256 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2257 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2258 def : Pat<(i64 (sextloadi16 addr:$dst)),
2259 (MOVSX64rm16 addr:$dst)>;
2260 def : Pat<(i64 (zextloadi16 addr:$dst)),
2261 (MOVZX64rm16 addr:$dst)>;
2262 def : Pat<(i64 (extloadi16 addr:$dst)),
2263 (MOVZX64rm16 addr:$dst)>;