1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!Subtarget->useSoftFloat()) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!Subtarget->useSoftFloat()) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!Subtarget->useSoftFloat()) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
835 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
836 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
837 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
845 // Only provide customized ctpop vector bit twiddling for vector types we
846 // know to perform better than using the popcnt instructions on each vector
847 // element. If popcnt isn't supported, always provide the custom version.
848 if (!Subtarget->hasPOPCNT()) {
849 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
853 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
854 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
855 MVT VT = (MVT::SimpleValueType)i;
856 // Do not attempt to custom lower non-power-of-2 vectors
857 if (!isPowerOf2_32(VT.getVectorNumElements()))
859 // Do not attempt to custom lower non-128-bit vectors
860 if (!VT.is128BitVector())
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::VSELECT, VT, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
868 // We support custom legalizing of sext and anyext loads for specific
869 // memory vector types which we can load as a scalar (or sequence of
870 // scalars) and extend in-register to a legal 128-bit vector type. For sext
871 // loads these must work with a single scalar load.
872 for (MVT VT : MVT::integer_vector_valuetypes()) {
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
889 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to promote non-128-bit vectors
903 if (!VT.is128BitVector())
906 setOperationAction(ISD::AND, VT, Promote);
907 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
908 setOperationAction(ISD::OR, VT, Promote);
909 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
910 setOperationAction(ISD::XOR, VT, Promote);
911 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
912 setOperationAction(ISD::LOAD, VT, Promote);
913 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
914 setOperationAction(ISD::SELECT, VT, Promote);
915 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
918 // Custom lower v2i64 and v2f64 selects.
919 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
920 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
921 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
922 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
924 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 // FIXME: Do we need to handle scalar-to-vector here?
955 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
957 // We directly match byte blends in the backend as they match the VSELECT
959 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
961 // SSE41 brings specific instructions for doing vector sign extend even in
962 // cases where we don't have SRA.
963 for (MVT VT : MVT::integer_vector_valuetypes()) {
964 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
965 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
966 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
969 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
970 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
971 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
972 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
973 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
974 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
977 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
978 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
979 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
980 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
981 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
984 // i8 and i16 vectors are custom because the source register and source
985 // source memory operand types are not the same width. f32 vectors are
986 // custom since the immediate controlling the insert encodes additional
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
994 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
998 // FIXME: these should be Legal, but that's only for the case where
999 // the index is constant. For now custom expand to deal with that.
1000 if (Subtarget->is64Bit()) {
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1006 if (Subtarget->hasSSE2()) {
1007 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1008 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1009 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1011 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1012 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1014 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1015 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1017 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1018 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1020 // In the customized shift lowering, the legal cases in AVX2 will be
1022 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1023 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1025 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1026 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1028 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1031 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1032 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1033 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1034 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1035 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1036 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1037 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1039 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1040 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1041 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1043 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1045 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1047 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1048 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1049 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1050 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1051 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1052 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1053 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1054 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1056 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1058 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1060 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1061 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1062 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1063 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1064 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1066 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1067 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1069 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1070 // even though v8i16 is a legal type.
1071 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1072 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1073 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1075 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1076 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1077 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1079 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1080 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1082 for (MVT VT : MVT::fp_vector_valuetypes())
1083 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1085 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1086 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1088 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1089 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1091 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1092 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1094 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1095 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1096 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1097 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1099 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1100 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1103 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1104 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1105 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1106 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1107 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1108 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1109 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1110 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1111 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1112 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1113 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1114 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1116 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1117 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1119 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1120 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1121 setOperationAction(ISD::FMA, MVT::f32, Legal);
1122 setOperationAction(ISD::FMA, MVT::f64, Legal);
1125 if (Subtarget->hasInt256()) {
1126 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1128 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1129 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1131 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1132 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1133 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1134 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1136 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1137 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1138 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1139 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1141 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1142 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1143 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1144 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1146 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1147 // when we have a 256bit-wide blend with immediate.
1148 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1150 // Only provide customized ctpop vector bit twiddling for vector types we
1151 // know to perform better than using the popcnt instructions on each
1152 // vector element. If popcnt isn't supported, always provide the custom
1154 if (!Subtarget->hasPOPCNT())
1155 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1157 // Custom CTPOP always performs better on natively supported v8i32
1158 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1160 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1161 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1162 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1163 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1164 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1165 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1166 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1168 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1169 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1170 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1171 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1172 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1173 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1175 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1176 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1177 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1178 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1180 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1181 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1182 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1183 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1185 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1186 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1187 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1188 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1191 // In the customized shift lowering, the legal cases in AVX2 will be
1193 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1194 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1196 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1197 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1199 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1201 // Custom lower several nodes for 256-bit types.
1202 for (MVT VT : MVT::vector_valuetypes()) {
1203 if (VT.getScalarSizeInBits() >= 32) {
1204 setOperationAction(ISD::MLOAD, VT, Legal);
1205 setOperationAction(ISD::MSTORE, VT, Legal);
1207 // Extract subvector is special because the value type
1208 // (result) is 128-bit but the source is 256-bit wide.
1209 if (VT.is128BitVector()) {
1210 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1212 // Do not attempt to custom lower other non-256-bit vectors
1213 if (!VT.is256BitVector())
1216 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1217 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1218 setOperationAction(ISD::VSELECT, VT, Custom);
1219 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1220 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1221 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1222 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1223 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1226 if (Subtarget->hasInt256())
1227 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1230 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1231 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1232 MVT VT = (MVT::SimpleValueType)i;
1234 // Do not attempt to promote non-256-bit vectors
1235 if (!VT.is256BitVector())
1238 setOperationAction(ISD::AND, VT, Promote);
1239 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1240 setOperationAction(ISD::OR, VT, Promote);
1241 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1242 setOperationAction(ISD::XOR, VT, Promote);
1243 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1244 setOperationAction(ISD::LOAD, VT, Promote);
1245 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1246 setOperationAction(ISD::SELECT, VT, Promote);
1247 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1251 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1252 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1253 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1254 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1255 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1257 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1258 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1259 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1261 for (MVT VT : MVT::fp_vector_valuetypes())
1262 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1264 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1265 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1266 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1267 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1268 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1269 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1270 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1271 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1272 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1273 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1274 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1275 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1277 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1278 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1279 setOperationAction(ISD::XOR, MVT::i1, Legal);
1280 setOperationAction(ISD::OR, MVT::i1, Legal);
1281 setOperationAction(ISD::AND, MVT::i1, Legal);
1282 setOperationAction(ISD::SUB, MVT::i1, Custom);
1283 setOperationAction(ISD::ADD, MVT::i1, Custom);
1284 setOperationAction(ISD::MUL, MVT::i1, Custom);
1285 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1286 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1287 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1288 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1289 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1291 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1292 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1293 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1294 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1295 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1296 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1298 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1299 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1300 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1301 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1302 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1303 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1304 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1305 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1307 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1308 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1309 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1310 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1311 if (Subtarget->is64Bit()) {
1312 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1313 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1314 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1315 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1317 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1318 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1319 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1320 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1321 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1322 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1323 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1324 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1325 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1326 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1327 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1328 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1329 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1330 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1331 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1332 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1334 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1335 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1336 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1337 if (Subtarget->hasDQI()) {
1338 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1339 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1341 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1342 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1343 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1344 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1345 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1346 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1347 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1348 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1349 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1353 if (Subtarget->hasDQI()) {
1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1355 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1357 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1358 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1360 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1362 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1363 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1364 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1365 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1366 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1370 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1371 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1374 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1377 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1379 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1380 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1381 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1382 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1383 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1384 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1385 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1386 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1387 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1388 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1389 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1391 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1392 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1394 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1395 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1397 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1399 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1400 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1402 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1403 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1405 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1406 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1408 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1409 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1410 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1411 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1412 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1413 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1415 if (Subtarget->hasCDI()) {
1416 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1417 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1419 if (Subtarget->hasDQI()) {
1420 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1421 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1422 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1424 // Custom lower several nodes.
1425 for (MVT VT : MVT::vector_valuetypes()) {
1426 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1428 setOperationAction(ISD::AND, VT, Legal);
1429 setOperationAction(ISD::OR, VT, Legal);
1430 setOperationAction(ISD::XOR, VT, Legal);
1432 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1433 setOperationAction(ISD::MGATHER, VT, Custom);
1434 setOperationAction(ISD::MSCATTER, VT, Custom);
1436 // Extract subvector is special because the value type
1437 // (result) is 256/128-bit but the source is 512-bit wide.
1438 if (VT.is128BitVector() || VT.is256BitVector()) {
1439 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1441 if (VT.getVectorElementType() == MVT::i1)
1442 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1444 // Do not attempt to custom lower other non-512-bit vectors
1445 if (!VT.is512BitVector())
1448 if (EltSize >= 32) {
1449 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1450 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1451 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1452 setOperationAction(ISD::VSELECT, VT, Legal);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1454 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1455 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1456 setOperationAction(ISD::MLOAD, VT, Legal);
1457 setOperationAction(ISD::MSTORE, VT, Legal);
1460 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1461 MVT VT = (MVT::SimpleValueType)i;
1463 // Do not attempt to promote non-512-bit vectors.
1464 if (!VT.is512BitVector())
1467 setOperationAction(ISD::SELECT, VT, Promote);
1468 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1472 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1473 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1474 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1476 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1477 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1479 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1480 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1481 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1482 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1483 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1484 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1485 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1486 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1487 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1488 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1489 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1490 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1491 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1492 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1493 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1494 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1495 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1496 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1497 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1498 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1499 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1500 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1501 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1502 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1503 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1504 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1505 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1507 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1508 const MVT VT = (MVT::SimpleValueType)i;
1510 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1512 // Do not attempt to promote non-512-bit vectors.
1513 if (!VT.is512BitVector())
1517 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1518 setOperationAction(ISD::VSELECT, VT, Legal);
1523 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1524 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1525 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1527 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1528 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1529 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1530 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1531 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1532 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1533 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1534 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1536 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1538 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1539 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1540 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1541 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1542 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1543 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1544 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1545 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1548 // We want to custom lower some of our intrinsics.
1549 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1550 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1551 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1552 if (!Subtarget->is64Bit())
1553 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1555 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1556 // handle type legalization for these operations here.
1558 // FIXME: We really should do custom legalization for addition and
1559 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1560 // than generic legalization for 64-bit multiplication-with-overflow, though.
1561 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1562 // Add/Sub/Mul with overflow operations are custom lowered.
1564 setOperationAction(ISD::SADDO, VT, Custom);
1565 setOperationAction(ISD::UADDO, VT, Custom);
1566 setOperationAction(ISD::SSUBO, VT, Custom);
1567 setOperationAction(ISD::USUBO, VT, Custom);
1568 setOperationAction(ISD::SMULO, VT, Custom);
1569 setOperationAction(ISD::UMULO, VT, Custom);
1573 if (!Subtarget->is64Bit()) {
1574 // These libcalls are not available in 32-bit.
1575 setLibcallName(RTLIB::SHL_I128, nullptr);
1576 setLibcallName(RTLIB::SRL_I128, nullptr);
1577 setLibcallName(RTLIB::SRA_I128, nullptr);
1580 // Combine sin / cos into one node or libcall if possible.
1581 if (Subtarget->hasSinCos()) {
1582 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1583 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1584 if (Subtarget->isTargetDarwin()) {
1585 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1586 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1587 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1588 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1592 if (Subtarget->isTargetWin64()) {
1593 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1594 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1595 setOperationAction(ISD::SREM, MVT::i128, Custom);
1596 setOperationAction(ISD::UREM, MVT::i128, Custom);
1597 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1598 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1601 // We have target-specific dag combine patterns for the following nodes:
1602 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1603 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1604 setTargetDAGCombine(ISD::BITCAST);
1605 setTargetDAGCombine(ISD::VSELECT);
1606 setTargetDAGCombine(ISD::SELECT);
1607 setTargetDAGCombine(ISD::SHL);
1608 setTargetDAGCombine(ISD::SRA);
1609 setTargetDAGCombine(ISD::SRL);
1610 setTargetDAGCombine(ISD::OR);
1611 setTargetDAGCombine(ISD::AND);
1612 setTargetDAGCombine(ISD::ADD);
1613 setTargetDAGCombine(ISD::FADD);
1614 setTargetDAGCombine(ISD::FSUB);
1615 setTargetDAGCombine(ISD::FMA);
1616 setTargetDAGCombine(ISD::SUB);
1617 setTargetDAGCombine(ISD::LOAD);
1618 setTargetDAGCombine(ISD::MLOAD);
1619 setTargetDAGCombine(ISD::STORE);
1620 setTargetDAGCombine(ISD::MSTORE);
1621 setTargetDAGCombine(ISD::ZERO_EXTEND);
1622 setTargetDAGCombine(ISD::ANY_EXTEND);
1623 setTargetDAGCombine(ISD::SIGN_EXTEND);
1624 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1625 setTargetDAGCombine(ISD::SINT_TO_FP);
1626 setTargetDAGCombine(ISD::SETCC);
1627 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1628 setTargetDAGCombine(ISD::BUILD_VECTOR);
1629 setTargetDAGCombine(ISD::MUL);
1630 setTargetDAGCombine(ISD::XOR);
1632 computeRegisterProperties(Subtarget->getRegisterInfo());
1634 // On Darwin, -Os means optimize for size without hurting performance,
1635 // do not reduce the limit.
1636 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1637 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1638 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1639 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1640 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1641 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1642 setPrefLoopAlignment(4); // 2^4 bytes.
1644 // Predictable cmov don't hurt on atom because it's in-order.
1645 PredictableSelectIsExpensive = !Subtarget->isAtom();
1646 EnableExtLdPromotion = true;
1647 setPrefFunctionAlignment(4); // 2^4 bytes.
1649 verifyIntrinsicTables();
1652 // This has so far only been implemented for 64-bit MachO.
1653 bool X86TargetLowering::useLoadStackGuardNode() const {
1654 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1657 TargetLoweringBase::LegalizeTypeAction
1658 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1659 if (ExperimentalVectorWideningLegalization &&
1660 VT.getVectorNumElements() != 1 &&
1661 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1662 return TypeWidenVector;
1664 return TargetLoweringBase::getPreferredVectorAction(VT);
1667 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1669 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1671 const unsigned NumElts = VT.getVectorNumElements();
1672 const EVT EltVT = VT.getVectorElementType();
1673 if (VT.is512BitVector()) {
1674 if (Subtarget->hasAVX512())
1675 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1676 EltVT == MVT::f32 || EltVT == MVT::f64)
1678 case 8: return MVT::v8i1;
1679 case 16: return MVT::v16i1;
1681 if (Subtarget->hasBWI())
1682 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1684 case 32: return MVT::v32i1;
1685 case 64: return MVT::v64i1;
1689 if (VT.is256BitVector() || VT.is128BitVector()) {
1690 if (Subtarget->hasVLX())
1691 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1692 EltVT == MVT::f32 || EltVT == MVT::f64)
1694 case 2: return MVT::v2i1;
1695 case 4: return MVT::v4i1;
1696 case 8: return MVT::v8i1;
1698 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1699 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1701 case 8: return MVT::v8i1;
1702 case 16: return MVT::v16i1;
1703 case 32: return MVT::v32i1;
1707 return VT.changeVectorElementTypeToInteger();
1710 /// Helper for getByValTypeAlignment to determine
1711 /// the desired ByVal argument alignment.
1712 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1715 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1716 if (VTy->getBitWidth() == 128)
1718 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1719 unsigned EltAlign = 0;
1720 getMaxByValAlign(ATy->getElementType(), EltAlign);
1721 if (EltAlign > MaxAlign)
1722 MaxAlign = EltAlign;
1723 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1724 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1725 unsigned EltAlign = 0;
1726 getMaxByValAlign(STy->getElementType(i), EltAlign);
1727 if (EltAlign > MaxAlign)
1728 MaxAlign = EltAlign;
1735 /// Return the desired alignment for ByVal aggregate
1736 /// function arguments in the caller parameter area. For X86, aggregates
1737 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1738 /// are at 4-byte boundaries.
1739 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1740 if (Subtarget->is64Bit()) {
1741 // Max of 8 and alignment of type.
1742 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1749 if (Subtarget->hasSSE1())
1750 getMaxByValAlign(Ty, Align);
1754 /// Returns the target specific optimal type for load
1755 /// and store operations as a result of memset, memcpy, and memmove
1756 /// lowering. If DstAlign is zero that means it's safe to destination
1757 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1758 /// means there isn't a need to check it against alignment requirement,
1759 /// probably because the source does not need to be loaded. If 'IsMemset' is
1760 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1761 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1762 /// source is constant so it does not need to be loaded.
1763 /// It returns EVT::Other if the type should be determined using generic
1764 /// target-independent logic.
1766 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1767 unsigned DstAlign, unsigned SrcAlign,
1768 bool IsMemset, bool ZeroMemset,
1770 MachineFunction &MF) const {
1771 const Function *F = MF.getFunction();
1772 if ((!IsMemset || ZeroMemset) &&
1773 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1775 (Subtarget->isUnalignedMemAccessFast() ||
1776 ((DstAlign == 0 || DstAlign >= 16) &&
1777 (SrcAlign == 0 || SrcAlign >= 16)))) {
1779 if (Subtarget->hasInt256())
1781 if (Subtarget->hasFp256())
1784 if (Subtarget->hasSSE2())
1786 if (Subtarget->hasSSE1())
1788 } else if (!MemcpyStrSrc && Size >= 8 &&
1789 !Subtarget->is64Bit() &&
1790 Subtarget->hasSSE2()) {
1791 // Do not use f64 to lower memcpy if source is string constant. It's
1792 // better to use i32 to avoid the loads.
1796 if (Subtarget->is64Bit() && Size >= 8)
1801 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1803 return X86ScalarSSEf32;
1804 else if (VT == MVT::f64)
1805 return X86ScalarSSEf64;
1810 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1815 *Fast = Subtarget->isUnalignedMemAccessFast();
1819 /// Return the entry encoding for a jump table in the
1820 /// current function. The returned value is a member of the
1821 /// MachineJumpTableInfo::JTEntryKind enum.
1822 unsigned X86TargetLowering::getJumpTableEncoding() const {
1823 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1825 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1826 Subtarget->isPICStyleGOT())
1827 return MachineJumpTableInfo::EK_Custom32;
1829 // Otherwise, use the normal jump table encoding heuristics.
1830 return TargetLowering::getJumpTableEncoding();
1833 bool X86TargetLowering::useSoftFloat() const {
1834 return Subtarget->useSoftFloat();
1838 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1839 const MachineBasicBlock *MBB,
1840 unsigned uid,MCContext &Ctx) const{
1841 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1842 Subtarget->isPICStyleGOT());
1843 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1845 return MCSymbolRefExpr::create(MBB->getSymbol(),
1846 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1849 /// Returns relocation base for the given PIC jumptable.
1850 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1851 SelectionDAG &DAG) const {
1852 if (!Subtarget->is64Bit())
1853 // This doesn't have SDLoc associated with it, but is not really the
1854 // same as a Register.
1855 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1859 /// This returns the relocation base for the given PIC jumptable,
1860 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1861 const MCExpr *X86TargetLowering::
1862 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1863 MCContext &Ctx) const {
1864 // X86-64 uses RIP relative addressing based on the jump table label.
1865 if (Subtarget->isPICStyleRIPRel())
1866 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1868 // Otherwise, the reference is relative to the PIC base.
1869 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1872 std::pair<const TargetRegisterClass *, uint8_t>
1873 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1875 const TargetRegisterClass *RRC = nullptr;
1877 switch (VT.SimpleTy) {
1879 return TargetLowering::findRepresentativeClass(TRI, VT);
1880 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1881 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1884 RRC = &X86::VR64RegClass;
1886 case MVT::f32: case MVT::f64:
1887 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1888 case MVT::v4f32: case MVT::v2f64:
1889 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1891 RRC = &X86::VR128RegClass;
1894 return std::make_pair(RRC, Cost);
1897 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1898 unsigned &Offset) const {
1899 if (!Subtarget->isTargetLinux())
1902 if (Subtarget->is64Bit()) {
1903 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1905 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1917 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1918 unsigned DestAS) const {
1919 assert(SrcAS != DestAS && "Expected different address spaces!");
1921 return SrcAS < 256 && DestAS < 256;
1924 //===----------------------------------------------------------------------===//
1925 // Return Value Calling Convention Implementation
1926 //===----------------------------------------------------------------------===//
1928 #include "X86GenCallingConv.inc"
1931 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1932 MachineFunction &MF, bool isVarArg,
1933 const SmallVectorImpl<ISD::OutputArg> &Outs,
1934 LLVMContext &Context) const {
1935 SmallVector<CCValAssign, 16> RVLocs;
1936 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1937 return CCInfo.CheckReturn(Outs, RetCC_X86);
1940 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1941 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1946 X86TargetLowering::LowerReturn(SDValue Chain,
1947 CallingConv::ID CallConv, bool isVarArg,
1948 const SmallVectorImpl<ISD::OutputArg> &Outs,
1949 const SmallVectorImpl<SDValue> &OutVals,
1950 SDLoc dl, SelectionDAG &DAG) const {
1951 MachineFunction &MF = DAG.getMachineFunction();
1952 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1954 SmallVector<CCValAssign, 16> RVLocs;
1955 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1956 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1959 SmallVector<SDValue, 6> RetOps;
1960 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1961 // Operand #1 = Bytes To Pop
1962 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1965 // Copy the result values into the output registers.
1966 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1967 CCValAssign &VA = RVLocs[i];
1968 assert(VA.isRegLoc() && "Can only return in registers!");
1969 SDValue ValToCopy = OutVals[i];
1970 EVT ValVT = ValToCopy.getValueType();
1972 // Promote values to the appropriate types.
1973 if (VA.getLocInfo() == CCValAssign::SExt)
1974 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1975 else if (VA.getLocInfo() == CCValAssign::ZExt)
1976 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1977 else if (VA.getLocInfo() == CCValAssign::AExt) {
1978 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1979 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1981 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1983 else if (VA.getLocInfo() == CCValAssign::BCvt)
1984 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1986 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1987 "Unexpected FP-extend for return value.");
1989 // If this is x86-64, and we disabled SSE, we can't return FP values,
1990 // or SSE or MMX vectors.
1991 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1992 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1993 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1994 report_fatal_error("SSE register return with SSE disabled");
1996 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1997 // llvm-gcc has never done it right and no one has noticed, so this
1998 // should be OK for now.
1999 if (ValVT == MVT::f64 &&
2000 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2001 report_fatal_error("SSE2 register return with SSE2 disabled");
2003 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2004 // the RET instruction and handled by the FP Stackifier.
2005 if (VA.getLocReg() == X86::FP0 ||
2006 VA.getLocReg() == X86::FP1) {
2007 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2008 // change the value to the FP stack register class.
2009 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2010 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2011 RetOps.push_back(ValToCopy);
2012 // Don't emit a copytoreg.
2016 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2017 // which is returned in RAX / RDX.
2018 if (Subtarget->is64Bit()) {
2019 if (ValVT == MVT::x86mmx) {
2020 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2021 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2022 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2024 // If we don't have SSE2 available, convert to v4f32 so the generated
2025 // register is legal.
2026 if (!Subtarget->hasSSE2())
2027 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2032 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2033 Flag = Chain.getValue(1);
2034 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2037 // All x86 ABIs require that for returning structs by value we copy
2038 // the sret argument into %rax/%eax (depending on ABI) for the return.
2039 // We saved the argument into a virtual register in the entry block,
2040 // so now we copy the value out and into %rax/%eax.
2042 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2043 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2044 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2045 // either case FuncInfo->setSRetReturnReg() will have been called.
2046 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2047 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2050 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2051 X86::RAX : X86::EAX;
2052 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2053 Flag = Chain.getValue(1);
2055 // RAX/EAX now acts like a return value.
2056 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2059 RetOps[0] = Chain; // Update chain.
2061 // Add the flag if we have it.
2063 RetOps.push_back(Flag);
2065 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2068 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2069 if (N->getNumValues() != 1)
2071 if (!N->hasNUsesOfValue(1, 0))
2074 SDValue TCChain = Chain;
2075 SDNode *Copy = *N->use_begin();
2076 if (Copy->getOpcode() == ISD::CopyToReg) {
2077 // If the copy has a glue operand, we conservatively assume it isn't safe to
2078 // perform a tail call.
2079 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2081 TCChain = Copy->getOperand(0);
2082 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2085 bool HasRet = false;
2086 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2088 if (UI->getOpcode() != X86ISD::RET_FLAG)
2090 // If we are returning more than one value, we can definitely
2091 // not make a tail call see PR19530
2092 if (UI->getNumOperands() > 4)
2094 if (UI->getNumOperands() == 4 &&
2095 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2108 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2109 ISD::NodeType ExtendKind) const {
2111 // TODO: Is this also valid on 32-bit?
2112 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2113 ReturnMVT = MVT::i8;
2115 ReturnMVT = MVT::i32;
2117 EVT MinVT = getRegisterType(Context, ReturnMVT);
2118 return VT.bitsLT(MinVT) ? MinVT : VT;
2121 /// Lower the result values of a call into the
2122 /// appropriate copies out of appropriate physical registers.
2125 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2126 CallingConv::ID CallConv, bool isVarArg,
2127 const SmallVectorImpl<ISD::InputArg> &Ins,
2128 SDLoc dl, SelectionDAG &DAG,
2129 SmallVectorImpl<SDValue> &InVals) const {
2131 // Assign locations to each value returned by this call.
2132 SmallVector<CCValAssign, 16> RVLocs;
2133 bool Is64Bit = Subtarget->is64Bit();
2134 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2136 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2138 // Copy all of the result registers out of their specified physreg.
2139 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2140 CCValAssign &VA = RVLocs[i];
2141 EVT CopyVT = VA.getLocVT();
2143 // If this is x86-64, and we disabled SSE, we can't return FP values
2144 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2145 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2146 report_fatal_error("SSE register return with SSE disabled");
2149 // If we prefer to use the value in xmm registers, copy it out as f80 and
2150 // use a truncate to move it from fp stack reg to xmm reg.
2151 bool RoundAfterCopy = false;
2152 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2153 isScalarFPTypeInSSEReg(VA.getValVT())) {
2155 RoundAfterCopy = (CopyVT != VA.getLocVT());
2158 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2159 CopyVT, InFlag).getValue(1);
2160 SDValue Val = Chain.getValue(0);
2163 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2164 // This truncation won't change the value.
2165 DAG.getIntPtrConstant(1, dl));
2167 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2168 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2170 InFlag = Chain.getValue(2);
2171 InVals.push_back(Val);
2177 //===----------------------------------------------------------------------===//
2178 // C & StdCall & Fast Calling Convention implementation
2179 //===----------------------------------------------------------------------===//
2180 // StdCall calling convention seems to be standard for many Windows' API
2181 // routines and around. It differs from C calling convention just a little:
2182 // callee should clean up the stack, not caller. Symbols should be also
2183 // decorated in some fancy way :) It doesn't support any vector arguments.
2184 // For info on fast calling convention see Fast Calling Convention (tail call)
2185 // implementation LowerX86_32FastCCCallTo.
2187 /// CallIsStructReturn - Determines whether a call uses struct return
2189 enum StructReturnType {
2194 static StructReturnType
2195 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2197 return NotStructReturn;
2199 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2200 if (!Flags.isSRet())
2201 return NotStructReturn;
2202 if (Flags.isInReg())
2203 return RegStructReturn;
2204 return StackStructReturn;
2207 /// Determines whether a function uses struct return semantics.
2208 static StructReturnType
2209 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2211 return NotStructReturn;
2213 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2214 if (!Flags.isSRet())
2215 return NotStructReturn;
2216 if (Flags.isInReg())
2217 return RegStructReturn;
2218 return StackStructReturn;
2221 /// Make a copy of an aggregate at address specified by "Src" to address
2222 /// "Dst" with size and alignment information specified by the specific
2223 /// parameter attribute. The copy will be passed as a byval function parameter.
2225 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2226 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2228 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2230 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2231 /*isVolatile*/false, /*AlwaysInline=*/true,
2232 /*isTailCall*/false,
2233 MachinePointerInfo(), MachinePointerInfo());
2236 /// Return true if the calling convention is one that
2237 /// supports tail call optimization.
2238 static bool IsTailCallConvention(CallingConv::ID CC) {
2239 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2240 CC == CallingConv::HiPE);
2243 /// \brief Return true if the calling convention is a C calling convention.
2244 static bool IsCCallConvention(CallingConv::ID CC) {
2245 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2246 CC == CallingConv::X86_64_SysV);
2249 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2250 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2254 CallingConv::ID CalleeCC = CS.getCallingConv();
2255 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2261 /// Return true if the function is being made into
2262 /// a tailcall target by changing its ABI.
2263 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2264 bool GuaranteedTailCallOpt) {
2265 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2269 X86TargetLowering::LowerMemArgument(SDValue Chain,
2270 CallingConv::ID CallConv,
2271 const SmallVectorImpl<ISD::InputArg> &Ins,
2272 SDLoc dl, SelectionDAG &DAG,
2273 const CCValAssign &VA,
2274 MachineFrameInfo *MFI,
2276 // Create the nodes corresponding to a load from this parameter slot.
2277 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2278 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2279 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2280 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2283 // If value is passed by pointer we have address passed instead of the value
2285 bool ExtendedInMem = VA.isExtInLoc() &&
2286 VA.getValVT().getScalarType() == MVT::i1;
2288 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2289 ValVT = VA.getLocVT();
2291 ValVT = VA.getValVT();
2293 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2294 // changed with more analysis.
2295 // In case of tail call optimization mark all arguments mutable. Since they
2296 // could be overwritten by lowering of arguments in case of a tail call.
2297 if (Flags.isByVal()) {
2298 unsigned Bytes = Flags.getByValSize();
2299 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2300 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2301 return DAG.getFrameIndex(FI, getPointerTy());
2303 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2304 VA.getLocMemOffset(), isImmutable);
2305 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2306 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2307 MachinePointerInfo::getFixedStack(FI),
2308 false, false, false, 0);
2309 return ExtendedInMem ?
2310 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2314 // FIXME: Get this from tablegen.
2315 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2316 const X86Subtarget *Subtarget) {
2317 assert(Subtarget->is64Bit());
2319 if (Subtarget->isCallingConvWin64(CallConv)) {
2320 static const MCPhysReg GPR64ArgRegsWin64[] = {
2321 X86::RCX, X86::RDX, X86::R8, X86::R9
2323 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2326 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2327 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2329 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2332 // FIXME: Get this from tablegen.
2333 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2334 CallingConv::ID CallConv,
2335 const X86Subtarget *Subtarget) {
2336 assert(Subtarget->is64Bit());
2337 if (Subtarget->isCallingConvWin64(CallConv)) {
2338 // The XMM registers which might contain var arg parameters are shadowed
2339 // in their paired GPR. So we only need to save the GPR to their home
2341 // TODO: __vectorcall will change this.
2345 const Function *Fn = MF.getFunction();
2346 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2347 bool isSoftFloat = Subtarget->useSoftFloat();
2348 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2349 "SSE register cannot be used when SSE is disabled!");
2350 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2351 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2355 static const MCPhysReg XMMArgRegs64Bit[] = {
2356 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2357 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2359 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2363 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2364 CallingConv::ID CallConv,
2366 const SmallVectorImpl<ISD::InputArg> &Ins,
2369 SmallVectorImpl<SDValue> &InVals)
2371 MachineFunction &MF = DAG.getMachineFunction();
2372 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2373 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2375 const Function* Fn = MF.getFunction();
2376 if (Fn->hasExternalLinkage() &&
2377 Subtarget->isTargetCygMing() &&
2378 Fn->getName() == "main")
2379 FuncInfo->setForceFramePointer(true);
2381 MachineFrameInfo *MFI = MF.getFrameInfo();
2382 bool Is64Bit = Subtarget->is64Bit();
2383 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2385 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2386 "Var args not supported with calling convention fastcc, ghc or hipe");
2388 // Assign locations to all of the incoming arguments.
2389 SmallVector<CCValAssign, 16> ArgLocs;
2390 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2392 // Allocate shadow area for Win64
2394 CCInfo.AllocateStack(32, 8);
2396 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2398 unsigned LastVal = ~0U;
2400 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2401 CCValAssign &VA = ArgLocs[i];
2402 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2404 assert(VA.getValNo() != LastVal &&
2405 "Don't support value assigned to multiple locs yet");
2407 LastVal = VA.getValNo();
2409 if (VA.isRegLoc()) {
2410 EVT RegVT = VA.getLocVT();
2411 const TargetRegisterClass *RC;
2412 if (RegVT == MVT::i32)
2413 RC = &X86::GR32RegClass;
2414 else if (Is64Bit && RegVT == MVT::i64)
2415 RC = &X86::GR64RegClass;
2416 else if (RegVT == MVT::f32)
2417 RC = &X86::FR32RegClass;
2418 else if (RegVT == MVT::f64)
2419 RC = &X86::FR64RegClass;
2420 else if (RegVT.is512BitVector())
2421 RC = &X86::VR512RegClass;
2422 else if (RegVT.is256BitVector())
2423 RC = &X86::VR256RegClass;
2424 else if (RegVT.is128BitVector())
2425 RC = &X86::VR128RegClass;
2426 else if (RegVT == MVT::x86mmx)
2427 RC = &X86::VR64RegClass;
2428 else if (RegVT == MVT::i1)
2429 RC = &X86::VK1RegClass;
2430 else if (RegVT == MVT::v8i1)
2431 RC = &X86::VK8RegClass;
2432 else if (RegVT == MVT::v16i1)
2433 RC = &X86::VK16RegClass;
2434 else if (RegVT == MVT::v32i1)
2435 RC = &X86::VK32RegClass;
2436 else if (RegVT == MVT::v64i1)
2437 RC = &X86::VK64RegClass;
2439 llvm_unreachable("Unknown argument type!");
2441 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2442 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2444 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2445 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2447 if (VA.getLocInfo() == CCValAssign::SExt)
2448 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2449 DAG.getValueType(VA.getValVT()));
2450 else if (VA.getLocInfo() == CCValAssign::ZExt)
2451 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2452 DAG.getValueType(VA.getValVT()));
2453 else if (VA.getLocInfo() == CCValAssign::BCvt)
2454 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2456 if (VA.isExtInLoc()) {
2457 // Handle MMX values passed in XMM regs.
2458 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2459 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2461 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2464 assert(VA.isMemLoc());
2465 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2468 // If value is passed via pointer - do a load.
2469 if (VA.getLocInfo() == CCValAssign::Indirect)
2470 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2471 MachinePointerInfo(), false, false, false, 0);
2473 InVals.push_back(ArgValue);
2476 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2477 // All x86 ABIs require that for returning structs by value we copy the
2478 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2479 // the argument into a virtual register so that we can access it from the
2481 if (Ins[i].Flags.isSRet()) {
2482 unsigned Reg = FuncInfo->getSRetReturnReg();
2484 MVT PtrTy = getPointerTy();
2485 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2486 FuncInfo->setSRetReturnReg(Reg);
2488 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2489 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2494 unsigned StackSize = CCInfo.getNextStackOffset();
2495 // Align stack specially for tail calls.
2496 if (FuncIsMadeTailCallSafe(CallConv,
2497 MF.getTarget().Options.GuaranteedTailCallOpt))
2498 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2500 // If the function takes variable number of arguments, make a frame index for
2501 // the start of the first vararg value... for expansion of llvm.va_start. We
2502 // can skip this if there are no va_start calls.
2503 if (MFI->hasVAStart() &&
2504 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2505 CallConv != CallingConv::X86_ThisCall))) {
2506 FuncInfo->setVarArgsFrameIndex(
2507 MFI->CreateFixedObject(1, StackSize, true));
2510 MachineModuleInfo &MMI = MF.getMMI();
2511 const Function *WinEHParent = nullptr;
2512 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2513 WinEHParent = MMI.getWinEHParent(Fn);
2514 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2515 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2517 // Figure out if XMM registers are in use.
2518 assert(!(Subtarget->useSoftFloat() &&
2519 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2520 "SSE register cannot be used when SSE is disabled!");
2522 // 64-bit calling conventions support varargs and register parameters, so we
2523 // have to do extra work to spill them in the prologue.
2524 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2525 // Find the first unallocated argument registers.
2526 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2527 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2528 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2529 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2530 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2531 "SSE register cannot be used when SSE is disabled!");
2533 // Gather all the live in physical registers.
2534 SmallVector<SDValue, 6> LiveGPRs;
2535 SmallVector<SDValue, 8> LiveXMMRegs;
2537 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2538 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2540 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2542 if (!ArgXMMs.empty()) {
2543 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2544 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2545 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2546 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2547 LiveXMMRegs.push_back(
2548 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2553 // Get to the caller-allocated home save location. Add 8 to account
2554 // for the return address.
2555 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2556 FuncInfo->setRegSaveFrameIndex(
2557 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2558 // Fixup to set vararg frame on shadow area (4 x i64).
2560 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2562 // For X86-64, if there are vararg parameters that are passed via
2563 // registers, then we must store them to their spots on the stack so
2564 // they may be loaded by deferencing the result of va_next.
2565 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2566 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2567 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2568 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2571 // Store the integer parameter registers.
2572 SmallVector<SDValue, 8> MemOps;
2573 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2575 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2576 for (SDValue Val : LiveGPRs) {
2577 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2578 DAG.getIntPtrConstant(Offset, dl));
2580 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2581 MachinePointerInfo::getFixedStack(
2582 FuncInfo->getRegSaveFrameIndex(), Offset),
2584 MemOps.push_back(Store);
2588 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2589 // Now store the XMM (fp + vector) parameter registers.
2590 SmallVector<SDValue, 12> SaveXMMOps;
2591 SaveXMMOps.push_back(Chain);
2592 SaveXMMOps.push_back(ALVal);
2593 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2594 FuncInfo->getRegSaveFrameIndex(), dl));
2595 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2596 FuncInfo->getVarArgsFPOffset(), dl));
2597 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2599 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2600 MVT::Other, SaveXMMOps));
2603 if (!MemOps.empty())
2604 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2605 } else if (IsWinEHOutlined) {
2606 // Get to the caller-allocated home save location. Add 8 to account
2607 // for the return address.
2608 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2609 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2610 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2612 MMI.getWinEHFuncInfo(Fn)
2613 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2614 FuncInfo->getRegSaveFrameIndex();
2616 // Store the second integer parameter (rdx) into rsp+16 relative to the
2617 // stack pointer at the entry of the function.
2619 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2620 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2621 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2622 Chain = DAG.getStore(
2623 Val.getValue(1), dl, Val, RSFIN,
2624 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2625 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2628 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2629 // Find the largest legal vector type.
2630 MVT VecVT = MVT::Other;
2631 // FIXME: Only some x86_32 calling conventions support AVX512.
2632 if (Subtarget->hasAVX512() &&
2633 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2634 CallConv == CallingConv::Intel_OCL_BI)))
2635 VecVT = MVT::v16f32;
2636 else if (Subtarget->hasAVX())
2638 else if (Subtarget->hasSSE2())
2641 // We forward some GPRs and some vector types.
2642 SmallVector<MVT, 2> RegParmTypes;
2643 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2644 RegParmTypes.push_back(IntVT);
2645 if (VecVT != MVT::Other)
2646 RegParmTypes.push_back(VecVT);
2648 // Compute the set of forwarded registers. The rest are scratch.
2649 SmallVectorImpl<ForwardedRegister> &Forwards =
2650 FuncInfo->getForwardedMustTailRegParms();
2651 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2653 // Conservatively forward AL on x86_64, since it might be used for varargs.
2654 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2655 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2656 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2659 // Copy all forwards from physical to virtual registers.
2660 for (ForwardedRegister &F : Forwards) {
2661 // FIXME: Can we use a less constrained schedule?
2662 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2663 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2664 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2668 // Some CCs need callee pop.
2669 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2670 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2671 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2673 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2674 // If this is an sret function, the return should pop the hidden pointer.
2675 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2676 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2677 argsAreStructReturn(Ins) == StackStructReturn)
2678 FuncInfo->setBytesToPopOnReturn(4);
2682 // RegSaveFrameIndex is X86-64 only.
2683 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2684 if (CallConv == CallingConv::X86_FastCall ||
2685 CallConv == CallingConv::X86_ThisCall)
2686 // fastcc functions can't have varargs.
2687 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2690 FuncInfo->setArgumentStackSize(StackSize);
2692 if (IsWinEHParent) {
2693 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2694 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2695 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2696 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2697 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2698 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2699 /*isVolatile=*/true,
2700 /*isNonTemporal=*/false, /*Alignment=*/0);
2707 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2708 SDValue StackPtr, SDValue Arg,
2709 SDLoc dl, SelectionDAG &DAG,
2710 const CCValAssign &VA,
2711 ISD::ArgFlagsTy Flags) const {
2712 unsigned LocMemOffset = VA.getLocMemOffset();
2713 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2714 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2715 if (Flags.isByVal())
2716 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2718 return DAG.getStore(Chain, dl, Arg, PtrOff,
2719 MachinePointerInfo::getStack(LocMemOffset),
2723 /// Emit a load of return address if tail call
2724 /// optimization is performed and it is required.
2726 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2727 SDValue &OutRetAddr, SDValue Chain,
2728 bool IsTailCall, bool Is64Bit,
2729 int FPDiff, SDLoc dl) const {
2730 // Adjust the Return address stack slot.
2731 EVT VT = getPointerTy();
2732 OutRetAddr = getReturnAddressFrameIndex(DAG);
2734 // Load the "old" Return address.
2735 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2736 false, false, false, 0);
2737 return SDValue(OutRetAddr.getNode(), 1);
2740 /// Emit a store of the return address if tail call
2741 /// optimization is performed and it is required (FPDiff!=0).
2742 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2743 SDValue Chain, SDValue RetAddrFrIdx,
2744 EVT PtrVT, unsigned SlotSize,
2745 int FPDiff, SDLoc dl) {
2746 // Store the return address to the appropriate stack slot.
2747 if (!FPDiff) return Chain;
2748 // Calculate the new stack slot for the return address.
2749 int NewReturnAddrFI =
2750 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2752 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2753 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2754 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2760 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2761 SmallVectorImpl<SDValue> &InVals) const {
2762 SelectionDAG &DAG = CLI.DAG;
2764 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2765 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2766 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2767 SDValue Chain = CLI.Chain;
2768 SDValue Callee = CLI.Callee;
2769 CallingConv::ID CallConv = CLI.CallConv;
2770 bool &isTailCall = CLI.IsTailCall;
2771 bool isVarArg = CLI.IsVarArg;
2773 MachineFunction &MF = DAG.getMachineFunction();
2774 bool Is64Bit = Subtarget->is64Bit();
2775 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2776 StructReturnType SR = callIsStructReturn(Outs);
2777 bool IsSibcall = false;
2778 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2780 if (MF.getTarget().Options.DisableTailCalls)
2783 if (Subtarget->isPICStyleGOT() &&
2784 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2785 // If we are using a GOT, disable tail calls to external symbols with
2786 // default visibility. Tail calling such a symbol requires using a GOT
2787 // relocation, which forces early binding of the symbol. This breaks code
2788 // that require lazy function symbol resolution. Using musttail or
2789 // GuaranteedTailCallOpt will override this.
2790 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2791 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2792 G->getGlobal()->hasDefaultVisibility()))
2796 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2798 // Force this to be a tail call. The verifier rules are enough to ensure
2799 // that we can lower this successfully without moving the return address
2802 } else if (isTailCall) {
2803 // Check if it's really possible to do a tail call.
2804 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2805 isVarArg, SR != NotStructReturn,
2806 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2807 Outs, OutVals, Ins, DAG);
2809 // Sibcalls are automatically detected tailcalls which do not require
2811 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2818 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2819 "Var args not supported with calling convention fastcc, ghc or hipe");
2821 // Analyze operands of the call, assigning locations to each operand.
2822 SmallVector<CCValAssign, 16> ArgLocs;
2823 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2825 // Allocate shadow area for Win64
2827 CCInfo.AllocateStack(32, 8);
2829 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2831 // Get a count of how many bytes are to be pushed on the stack.
2832 unsigned NumBytes = CCInfo.getNextStackOffset();
2834 // This is a sibcall. The memory operands are available in caller's
2835 // own caller's stack.
2837 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2838 IsTailCallConvention(CallConv))
2839 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2842 if (isTailCall && !IsSibcall && !IsMustTail) {
2843 // Lower arguments at fp - stackoffset + fpdiff.
2844 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2846 FPDiff = NumBytesCallerPushed - NumBytes;
2848 // Set the delta of movement of the returnaddr stackslot.
2849 // But only set if delta is greater than previous delta.
2850 if (FPDiff < X86Info->getTCReturnAddrDelta())
2851 X86Info->setTCReturnAddrDelta(FPDiff);
2854 unsigned NumBytesToPush = NumBytes;
2855 unsigned NumBytesToPop = NumBytes;
2857 // If we have an inalloca argument, all stack space has already been allocated
2858 // for us and be right at the top of the stack. We don't support multiple
2859 // arguments passed in memory when using inalloca.
2860 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2862 if (!ArgLocs.back().isMemLoc())
2863 report_fatal_error("cannot use inalloca attribute on a register "
2865 if (ArgLocs.back().getLocMemOffset() != 0)
2866 report_fatal_error("any parameter with the inalloca attribute must be "
2867 "the only memory argument");
2871 Chain = DAG.getCALLSEQ_START(
2872 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2874 SDValue RetAddrFrIdx;
2875 // Load return address for tail calls.
2876 if (isTailCall && FPDiff)
2877 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2878 Is64Bit, FPDiff, dl);
2880 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2881 SmallVector<SDValue, 8> MemOpChains;
2884 // Walk the register/memloc assignments, inserting copies/loads. In the case
2885 // of tail call optimization arguments are handle later.
2886 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2887 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2888 // Skip inalloca arguments, they have already been written.
2889 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2890 if (Flags.isInAlloca())
2893 CCValAssign &VA = ArgLocs[i];
2894 EVT RegVT = VA.getLocVT();
2895 SDValue Arg = OutVals[i];
2896 bool isByVal = Flags.isByVal();
2898 // Promote the value if needed.
2899 switch (VA.getLocInfo()) {
2900 default: llvm_unreachable("Unknown loc info!");
2901 case CCValAssign::Full: break;
2902 case CCValAssign::SExt:
2903 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2905 case CCValAssign::ZExt:
2906 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2908 case CCValAssign::AExt:
2909 if (Arg.getValueType().isVector() &&
2910 Arg.getValueType().getScalarType() == MVT::i1)
2911 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2912 else if (RegVT.is128BitVector()) {
2913 // Special case: passing MMX values in XMM registers.
2914 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2915 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2916 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2918 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2920 case CCValAssign::BCvt:
2921 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2923 case CCValAssign::Indirect: {
2924 // Store the argument.
2925 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2926 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2927 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2928 MachinePointerInfo::getFixedStack(FI),
2935 if (VA.isRegLoc()) {
2936 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2937 if (isVarArg && IsWin64) {
2938 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2939 // shadow reg if callee is a varargs function.
2940 unsigned ShadowReg = 0;
2941 switch (VA.getLocReg()) {
2942 case X86::XMM0: ShadowReg = X86::RCX; break;
2943 case X86::XMM1: ShadowReg = X86::RDX; break;
2944 case X86::XMM2: ShadowReg = X86::R8; break;
2945 case X86::XMM3: ShadowReg = X86::R9; break;
2948 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2950 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2951 assert(VA.isMemLoc());
2952 if (!StackPtr.getNode())
2953 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2955 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2956 dl, DAG, VA, Flags));
2960 if (!MemOpChains.empty())
2961 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2963 if (Subtarget->isPICStyleGOT()) {
2964 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2967 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2968 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2970 // If we are tail calling and generating PIC/GOT style code load the
2971 // address of the callee into ECX. The value in ecx is used as target of
2972 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2973 // for tail calls on PIC/GOT architectures. Normally we would just put the
2974 // address of GOT into ebx and then call target@PLT. But for tail calls
2975 // ebx would be restored (since ebx is callee saved) before jumping to the
2978 // Note: The actual moving to ECX is done further down.
2979 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2980 if (G && !G->getGlobal()->hasLocalLinkage() &&
2981 G->getGlobal()->hasDefaultVisibility())
2982 Callee = LowerGlobalAddress(Callee, DAG);
2983 else if (isa<ExternalSymbolSDNode>(Callee))
2984 Callee = LowerExternalSymbol(Callee, DAG);
2988 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2989 // From AMD64 ABI document:
2990 // For calls that may call functions that use varargs or stdargs
2991 // (prototype-less calls or calls to functions containing ellipsis (...) in
2992 // the declaration) %al is used as hidden argument to specify the number
2993 // of SSE registers used. The contents of %al do not need to match exactly
2994 // the number of registers, but must be an ubound on the number of SSE
2995 // registers used and is in the range 0 - 8 inclusive.
2997 // Count the number of XMM registers allocated.
2998 static const MCPhysReg XMMArgRegs[] = {
2999 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3000 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3002 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3003 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3004 && "SSE registers cannot be used when SSE is disabled");
3006 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3007 DAG.getConstant(NumXMMRegs, dl,
3011 if (isVarArg && IsMustTail) {
3012 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3013 for (const auto &F : Forwards) {
3014 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3015 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3019 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3020 // don't need this because the eligibility check rejects calls that require
3021 // shuffling arguments passed in memory.
3022 if (!IsSibcall && isTailCall) {
3023 // Force all the incoming stack arguments to be loaded from the stack
3024 // before any new outgoing arguments are stored to the stack, because the
3025 // outgoing stack slots may alias the incoming argument stack slots, and
3026 // the alias isn't otherwise explicit. This is slightly more conservative
3027 // than necessary, because it means that each store effectively depends
3028 // on every argument instead of just those arguments it would clobber.
3029 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3031 SmallVector<SDValue, 8> MemOpChains2;
3034 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3035 CCValAssign &VA = ArgLocs[i];
3038 assert(VA.isMemLoc());
3039 SDValue Arg = OutVals[i];
3040 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3041 // Skip inalloca arguments. They don't require any work.
3042 if (Flags.isInAlloca())
3044 // Create frame index.
3045 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3046 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3047 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3048 FIN = DAG.getFrameIndex(FI, getPointerTy());
3050 if (Flags.isByVal()) {
3051 // Copy relative to framepointer.
3052 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3053 if (!StackPtr.getNode())
3054 StackPtr = DAG.getCopyFromReg(Chain, dl,
3055 RegInfo->getStackRegister(),
3057 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3059 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3063 // Store relative to framepointer.
3064 MemOpChains2.push_back(
3065 DAG.getStore(ArgChain, dl, Arg, FIN,
3066 MachinePointerInfo::getFixedStack(FI),
3071 if (!MemOpChains2.empty())
3072 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3074 // Store the return address to the appropriate stack slot.
3075 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3076 getPointerTy(), RegInfo->getSlotSize(),
3080 // Build a sequence of copy-to-reg nodes chained together with token chain
3081 // and flag operands which copy the outgoing args into registers.
3083 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3084 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3085 RegsToPass[i].second, InFlag);
3086 InFlag = Chain.getValue(1);
3089 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3090 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3091 // In the 64-bit large code model, we have to make all calls
3092 // through a register, since the call instruction's 32-bit
3093 // pc-relative offset may not be large enough to hold the whole
3095 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3096 // If the callee is a GlobalAddress node (quite common, every direct call
3097 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3099 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3101 // We should use extra load for direct calls to dllimported functions in
3103 const GlobalValue *GV = G->getGlobal();
3104 if (!GV->hasDLLImportStorageClass()) {
3105 unsigned char OpFlags = 0;
3106 bool ExtraLoad = false;
3107 unsigned WrapperKind = ISD::DELETED_NODE;
3109 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3110 // external symbols most go through the PLT in PIC mode. If the symbol
3111 // has hidden or protected visibility, or if it is static or local, then
3112 // we don't need to use the PLT - we can directly call it.
3113 if (Subtarget->isTargetELF() &&
3114 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3115 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3116 OpFlags = X86II::MO_PLT;
3117 } else if (Subtarget->isPICStyleStubAny() &&
3118 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3119 (!Subtarget->getTargetTriple().isMacOSX() ||
3120 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3121 // PC-relative references to external symbols should go through $stub,
3122 // unless we're building with the leopard linker or later, which
3123 // automatically synthesizes these stubs.
3124 OpFlags = X86II::MO_DARWIN_STUB;
3125 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3126 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3127 // If the function is marked as non-lazy, generate an indirect call
3128 // which loads from the GOT directly. This avoids runtime overhead
3129 // at the cost of eager binding (and one extra byte of encoding).
3130 OpFlags = X86II::MO_GOTPCREL;
3131 WrapperKind = X86ISD::WrapperRIP;
3135 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3136 G->getOffset(), OpFlags);
3138 // Add a wrapper if needed.
3139 if (WrapperKind != ISD::DELETED_NODE)
3140 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3141 // Add extra indirection if needed.
3143 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3144 MachinePointerInfo::getGOT(),
3145 false, false, false, 0);
3147 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3148 unsigned char OpFlags = 0;
3150 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3151 // external symbols should go through the PLT.
3152 if (Subtarget->isTargetELF() &&
3153 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3154 OpFlags = X86II::MO_PLT;
3155 } else if (Subtarget->isPICStyleStubAny() &&
3156 (!Subtarget->getTargetTriple().isMacOSX() ||
3157 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3158 // PC-relative references to external symbols should go through $stub,
3159 // unless we're building with the leopard linker or later, which
3160 // automatically synthesizes these stubs.
3161 OpFlags = X86II::MO_DARWIN_STUB;
3164 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3166 } else if (Subtarget->isTarget64BitILP32() &&
3167 Callee->getValueType(0) == MVT::i32) {
3168 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3169 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3172 // Returns a chain & a flag for retval copy to use.
3173 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3174 SmallVector<SDValue, 8> Ops;
3176 if (!IsSibcall && isTailCall) {
3177 Chain = DAG.getCALLSEQ_END(Chain,
3178 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3179 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3180 InFlag = Chain.getValue(1);
3183 Ops.push_back(Chain);
3184 Ops.push_back(Callee);
3187 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3189 // Add argument registers to the end of the list so that they are known live
3191 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3192 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3193 RegsToPass[i].second.getValueType()));
3195 // Add a register mask operand representing the call-preserved registers.
3196 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3197 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3198 assert(Mask && "Missing call preserved mask for calling convention");
3199 Ops.push_back(DAG.getRegisterMask(Mask));
3201 if (InFlag.getNode())
3202 Ops.push_back(InFlag);
3206 //// If this is the first return lowered for this function, add the regs
3207 //// to the liveout set for the function.
3208 // This isn't right, although it's probably harmless on x86; liveouts
3209 // should be computed from returns not tail calls. Consider a void
3210 // function making a tail call to a function returning int.
3211 MF.getFrameInfo()->setHasTailCall();
3212 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3215 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3216 InFlag = Chain.getValue(1);
3218 // Create the CALLSEQ_END node.
3219 unsigned NumBytesForCalleeToPop;
3220 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3221 DAG.getTarget().Options.GuaranteedTailCallOpt))
3222 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3223 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3224 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3225 SR == StackStructReturn)
3226 // If this is a call to a struct-return function, the callee
3227 // pops the hidden struct pointer, so we have to push it back.
3228 // This is common for Darwin/X86, Linux & Mingw32 targets.
3229 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3230 NumBytesForCalleeToPop = 4;
3232 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3234 // Returns a flag for retval copy to use.
3236 Chain = DAG.getCALLSEQ_END(Chain,
3237 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3238 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3241 InFlag = Chain.getValue(1);
3244 // Handle result values, copying them out of physregs into vregs that we
3246 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3247 Ins, dl, DAG, InVals);
3250 //===----------------------------------------------------------------------===//
3251 // Fast Calling Convention (tail call) implementation
3252 //===----------------------------------------------------------------------===//
3254 // Like std call, callee cleans arguments, convention except that ECX is
3255 // reserved for storing the tail called function address. Only 2 registers are
3256 // free for argument passing (inreg). Tail call optimization is performed
3258 // * tailcallopt is enabled
3259 // * caller/callee are fastcc
3260 // On X86_64 architecture with GOT-style position independent code only local
3261 // (within module) calls are supported at the moment.
3262 // To keep the stack aligned according to platform abi the function
3263 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3264 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3265 // If a tail called function callee has more arguments than the caller the
3266 // caller needs to make sure that there is room to move the RETADDR to. This is
3267 // achieved by reserving an area the size of the argument delta right after the
3268 // original RETADDR, but before the saved framepointer or the spilled registers
3269 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3281 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3282 /// for a 16 byte align requirement.
3284 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3285 SelectionDAG& DAG) const {
3286 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3287 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3288 unsigned StackAlignment = TFI.getStackAlignment();
3289 uint64_t AlignMask = StackAlignment - 1;
3290 int64_t Offset = StackSize;
3291 unsigned SlotSize = RegInfo->getSlotSize();
3292 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3293 // Number smaller than 12 so just add the difference.
3294 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3296 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3297 Offset = ((~AlignMask) & Offset) + StackAlignment +
3298 (StackAlignment-SlotSize);
3303 /// MatchingStackOffset - Return true if the given stack call argument is
3304 /// already available in the same position (relatively) of the caller's
3305 /// incoming argument stack.
3307 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3308 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3309 const X86InstrInfo *TII) {
3310 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3312 if (Arg.getOpcode() == ISD::CopyFromReg) {
3313 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3314 if (!TargetRegisterInfo::isVirtualRegister(VR))
3316 MachineInstr *Def = MRI->getVRegDef(VR);
3319 if (!Flags.isByVal()) {
3320 if (!TII->isLoadFromStackSlot(Def, FI))
3323 unsigned Opcode = Def->getOpcode();
3324 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3325 Opcode == X86::LEA64_32r) &&
3326 Def->getOperand(1).isFI()) {
3327 FI = Def->getOperand(1).getIndex();
3328 Bytes = Flags.getByValSize();
3332 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3333 if (Flags.isByVal())
3334 // ByVal argument is passed in as a pointer but it's now being
3335 // dereferenced. e.g.
3336 // define @foo(%struct.X* %A) {
3337 // tail call @bar(%struct.X* byval %A)
3340 SDValue Ptr = Ld->getBasePtr();
3341 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3344 FI = FINode->getIndex();
3345 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3346 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3347 FI = FINode->getIndex();
3348 Bytes = Flags.getByValSize();
3352 assert(FI != INT_MAX);
3353 if (!MFI->isFixedObjectIndex(FI))
3355 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3358 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3359 /// for tail call optimization. Targets which want to do tail call
3360 /// optimization should implement this function.
3362 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3363 CallingConv::ID CalleeCC,
3365 bool isCalleeStructRet,
3366 bool isCallerStructRet,
3368 const SmallVectorImpl<ISD::OutputArg> &Outs,
3369 const SmallVectorImpl<SDValue> &OutVals,
3370 const SmallVectorImpl<ISD::InputArg> &Ins,
3371 SelectionDAG &DAG) const {
3372 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3375 // If -tailcallopt is specified, make fastcc functions tail-callable.
3376 const MachineFunction &MF = DAG.getMachineFunction();
3377 const Function *CallerF = MF.getFunction();
3379 // If the function return type is x86_fp80 and the callee return type is not,
3380 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3381 // perform a tailcall optimization here.
3382 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3385 CallingConv::ID CallerCC = CallerF->getCallingConv();
3386 bool CCMatch = CallerCC == CalleeCC;
3387 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3388 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3390 // Win64 functions have extra shadow space for argument homing. Don't do the
3391 // sibcall if the caller and callee have mismatched expectations for this
3393 if (IsCalleeWin64 != IsCallerWin64)
3396 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3397 if (IsTailCallConvention(CalleeCC) && CCMatch)
3402 // Look for obvious safe cases to perform tail call optimization that do not
3403 // require ABI changes. This is what gcc calls sibcall.
3405 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3406 // emit a special epilogue.
3407 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3408 if (RegInfo->needsStackRealignment(MF))
3411 // Also avoid sibcall optimization if either caller or callee uses struct
3412 // return semantics.
3413 if (isCalleeStructRet || isCallerStructRet)
3416 // An stdcall/thiscall caller is expected to clean up its arguments; the
3417 // callee isn't going to do that.
3418 // FIXME: this is more restrictive than needed. We could produce a tailcall
3419 // when the stack adjustment matches. For example, with a thiscall that takes
3420 // only one argument.
3421 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3422 CallerCC == CallingConv::X86_ThisCall))
3425 // Do not sibcall optimize vararg calls unless all arguments are passed via
3427 if (isVarArg && !Outs.empty()) {
3429 // Optimizing for varargs on Win64 is unlikely to be safe without
3430 // additional testing.
3431 if (IsCalleeWin64 || IsCallerWin64)
3434 SmallVector<CCValAssign, 16> ArgLocs;
3435 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3438 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3440 if (!ArgLocs[i].isRegLoc())
3444 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3445 // stack. Therefore, if it's not used by the call it is not safe to optimize
3446 // this into a sibcall.
3447 bool Unused = false;
3448 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3455 SmallVector<CCValAssign, 16> RVLocs;
3456 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3458 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3459 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3460 CCValAssign &VA = RVLocs[i];
3461 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3466 // If the calling conventions do not match, then we'd better make sure the
3467 // results are returned in the same way as what the caller expects.
3469 SmallVector<CCValAssign, 16> RVLocs1;
3470 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3472 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3474 SmallVector<CCValAssign, 16> RVLocs2;
3475 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3477 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3479 if (RVLocs1.size() != RVLocs2.size())
3481 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3482 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3484 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3486 if (RVLocs1[i].isRegLoc()) {
3487 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3490 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3496 // If the callee takes no arguments then go on to check the results of the
3498 if (!Outs.empty()) {
3499 // Check if stack adjustment is needed. For now, do not do this if any
3500 // argument is passed on the stack.
3501 SmallVector<CCValAssign, 16> ArgLocs;
3502 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3505 // Allocate shadow area for Win64
3507 CCInfo.AllocateStack(32, 8);
3509 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3510 if (CCInfo.getNextStackOffset()) {
3511 MachineFunction &MF = DAG.getMachineFunction();
3512 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3515 // Check if the arguments are already laid out in the right way as
3516 // the caller's fixed stack objects.
3517 MachineFrameInfo *MFI = MF.getFrameInfo();
3518 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3519 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3520 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3521 CCValAssign &VA = ArgLocs[i];
3522 SDValue Arg = OutVals[i];
3523 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3524 if (VA.getLocInfo() == CCValAssign::Indirect)
3526 if (!VA.isRegLoc()) {
3527 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3534 // If the tailcall address may be in a register, then make sure it's
3535 // possible to register allocate for it. In 32-bit, the call address can
3536 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3537 // callee-saved registers are restored. These happen to be the same
3538 // registers used to pass 'inreg' arguments so watch out for those.
3539 if (!Subtarget->is64Bit() &&
3540 ((!isa<GlobalAddressSDNode>(Callee) &&
3541 !isa<ExternalSymbolSDNode>(Callee)) ||
3542 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3543 unsigned NumInRegs = 0;
3544 // In PIC we need an extra register to formulate the address computation
3546 unsigned MaxInRegs =
3547 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3549 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3550 CCValAssign &VA = ArgLocs[i];
3553 unsigned Reg = VA.getLocReg();
3556 case X86::EAX: case X86::EDX: case X86::ECX:
3557 if (++NumInRegs == MaxInRegs)
3569 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3570 const TargetLibraryInfo *libInfo) const {
3571 return X86::createFastISel(funcInfo, libInfo);
3574 //===----------------------------------------------------------------------===//
3575 // Other Lowering Hooks
3576 //===----------------------------------------------------------------------===//
3578 static bool MayFoldLoad(SDValue Op) {
3579 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3582 static bool MayFoldIntoStore(SDValue Op) {
3583 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3586 static bool isTargetShuffle(unsigned Opcode) {
3588 default: return false;
3589 case X86ISD::BLENDI:
3590 case X86ISD::PSHUFB:
3591 case X86ISD::PSHUFD:
3592 case X86ISD::PSHUFHW:
3593 case X86ISD::PSHUFLW:
3595 case X86ISD::PALIGNR:
3596 case X86ISD::MOVLHPS:
3597 case X86ISD::MOVLHPD:
3598 case X86ISD::MOVHLPS:
3599 case X86ISD::MOVLPS:
3600 case X86ISD::MOVLPD:
3601 case X86ISD::MOVSHDUP:
3602 case X86ISD::MOVSLDUP:
3603 case X86ISD::MOVDDUP:
3606 case X86ISD::UNPCKL:
3607 case X86ISD::UNPCKH:
3608 case X86ISD::VPERMILPI:
3609 case X86ISD::VPERM2X128:
3610 case X86ISD::VPERMI:
3615 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3616 SDValue V1, unsigned TargetMask,
3617 SelectionDAG &DAG) {
3619 default: llvm_unreachable("Unknown x86 shuffle node");
3620 case X86ISD::PSHUFD:
3621 case X86ISD::PSHUFHW:
3622 case X86ISD::PSHUFLW:
3623 case X86ISD::VPERMILPI:
3624 case X86ISD::VPERMI:
3625 return DAG.getNode(Opc, dl, VT, V1,
3626 DAG.getConstant(TargetMask, dl, MVT::i8));
3630 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3631 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3633 default: llvm_unreachable("Unknown x86 shuffle node");
3634 case X86ISD::MOVLHPS:
3635 case X86ISD::MOVLHPD:
3636 case X86ISD::MOVHLPS:
3637 case X86ISD::MOVLPS:
3638 case X86ISD::MOVLPD:
3641 case X86ISD::UNPCKL:
3642 case X86ISD::UNPCKH:
3643 return DAG.getNode(Opc, dl, VT, V1, V2);
3647 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3648 MachineFunction &MF = DAG.getMachineFunction();
3649 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3650 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3651 int ReturnAddrIndex = FuncInfo->getRAIndex();
3653 if (ReturnAddrIndex == 0) {
3654 // Set up a frame object for the return address.
3655 unsigned SlotSize = RegInfo->getSlotSize();
3656 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3659 FuncInfo->setRAIndex(ReturnAddrIndex);
3662 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3665 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3666 bool hasSymbolicDisplacement) {
3667 // Offset should fit into 32 bit immediate field.
3668 if (!isInt<32>(Offset))
3671 // If we don't have a symbolic displacement - we don't have any extra
3673 if (!hasSymbolicDisplacement)
3676 // FIXME: Some tweaks might be needed for medium code model.
3677 if (M != CodeModel::Small && M != CodeModel::Kernel)
3680 // For small code model we assume that latest object is 16MB before end of 31
3681 // bits boundary. We may also accept pretty large negative constants knowing
3682 // that all objects are in the positive half of address space.
3683 if (M == CodeModel::Small && Offset < 16*1024*1024)
3686 // For kernel code model we know that all object resist in the negative half
3687 // of 32bits address space. We may not accept negative offsets, since they may
3688 // be just off and we may accept pretty large positive ones.
3689 if (M == CodeModel::Kernel && Offset >= 0)
3695 /// isCalleePop - Determines whether the callee is required to pop its
3696 /// own arguments. Callee pop is necessary to support tail calls.
3697 bool X86::isCalleePop(CallingConv::ID CallingConv,
3698 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3699 switch (CallingConv) {
3702 case CallingConv::X86_StdCall:
3703 case CallingConv::X86_FastCall:
3704 case CallingConv::X86_ThisCall:
3706 case CallingConv::Fast:
3707 case CallingConv::GHC:
3708 case CallingConv::HiPE:
3715 /// \brief Return true if the condition is an unsigned comparison operation.
3716 static bool isX86CCUnsigned(unsigned X86CC) {
3718 default: llvm_unreachable("Invalid integer condition!");
3719 case X86::COND_E: return true;
3720 case X86::COND_G: return false;
3721 case X86::COND_GE: return false;
3722 case X86::COND_L: return false;
3723 case X86::COND_LE: return false;
3724 case X86::COND_NE: return true;
3725 case X86::COND_B: return true;
3726 case X86::COND_A: return true;
3727 case X86::COND_BE: return true;
3728 case X86::COND_AE: return true;
3730 llvm_unreachable("covered switch fell through?!");
3733 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3734 /// specific condition code, returning the condition code and the LHS/RHS of the
3735 /// comparison to make.
3736 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3737 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3739 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3740 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3741 // X > -1 -> X == 0, jump !sign.
3742 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3743 return X86::COND_NS;
3745 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3746 // X < 0 -> X == 0, jump on sign.
3749 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3751 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3752 return X86::COND_LE;
3756 switch (SetCCOpcode) {
3757 default: llvm_unreachable("Invalid integer condition!");
3758 case ISD::SETEQ: return X86::COND_E;
3759 case ISD::SETGT: return X86::COND_G;
3760 case ISD::SETGE: return X86::COND_GE;
3761 case ISD::SETLT: return X86::COND_L;
3762 case ISD::SETLE: return X86::COND_LE;
3763 case ISD::SETNE: return X86::COND_NE;
3764 case ISD::SETULT: return X86::COND_B;
3765 case ISD::SETUGT: return X86::COND_A;
3766 case ISD::SETULE: return X86::COND_BE;
3767 case ISD::SETUGE: return X86::COND_AE;
3771 // First determine if it is required or is profitable to flip the operands.
3773 // If LHS is a foldable load, but RHS is not, flip the condition.
3774 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3775 !ISD::isNON_EXTLoad(RHS.getNode())) {
3776 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3777 std::swap(LHS, RHS);
3780 switch (SetCCOpcode) {
3786 std::swap(LHS, RHS);
3790 // On a floating point condition, the flags are set as follows:
3792 // 0 | 0 | 0 | X > Y
3793 // 0 | 0 | 1 | X < Y
3794 // 1 | 0 | 0 | X == Y
3795 // 1 | 1 | 1 | unordered
3796 switch (SetCCOpcode) {
3797 default: llvm_unreachable("Condcode should be pre-legalized away");
3799 case ISD::SETEQ: return X86::COND_E;
3800 case ISD::SETOLT: // flipped
3802 case ISD::SETGT: return X86::COND_A;
3803 case ISD::SETOLE: // flipped
3805 case ISD::SETGE: return X86::COND_AE;
3806 case ISD::SETUGT: // flipped
3808 case ISD::SETLT: return X86::COND_B;
3809 case ISD::SETUGE: // flipped
3811 case ISD::SETLE: return X86::COND_BE;
3813 case ISD::SETNE: return X86::COND_NE;
3814 case ISD::SETUO: return X86::COND_P;
3815 case ISD::SETO: return X86::COND_NP;
3817 case ISD::SETUNE: return X86::COND_INVALID;
3821 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3822 /// code. Current x86 isa includes the following FP cmov instructions:
3823 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3824 static bool hasFPCMov(unsigned X86CC) {
3840 /// isFPImmLegal - Returns true if the target can instruction select the
3841 /// specified FP immediate natively. If false, the legalizer will
3842 /// materialize the FP immediate as a load from a constant pool.
3843 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3844 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3845 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3851 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3852 ISD::LoadExtType ExtTy,
3854 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3855 // relocation target a movq or addq instruction: don't let the load shrink.
3856 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3857 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3858 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3859 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3863 /// \brief Returns true if it is beneficial to convert a load of a constant
3864 /// to just the constant itself.
3865 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3867 assert(Ty->isIntegerTy());
3869 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3870 if (BitSize == 0 || BitSize > 64)
3875 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3876 unsigned Index) const {
3877 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3880 return (Index == 0 || Index == ResVT.getVectorNumElements());
3883 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3884 // Speculate cttz only if we can directly use TZCNT.
3885 return Subtarget->hasBMI();
3888 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3889 // Speculate ctlz only if we can directly use LZCNT.
3890 return Subtarget->hasLZCNT();
3893 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3894 /// the specified range (L, H].
3895 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3896 return (Val < 0) || (Val >= Low && Val < Hi);
3899 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3900 /// specified value.
3901 static bool isUndefOrEqual(int Val, int CmpVal) {
3902 return (Val < 0 || Val == CmpVal);
3905 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3906 /// from position Pos and ending in Pos+Size, falls within the specified
3907 /// sequential range (Low, Low+Size]. or is undef.
3908 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3909 unsigned Pos, unsigned Size, int Low) {
3910 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3911 if (!isUndefOrEqual(Mask[i], Low))
3916 /// isVEXTRACTIndex - Return true if the specified
3917 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3918 /// suitable for instruction that extract 128 or 256 bit vectors
3919 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3920 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3921 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3924 // The index should be aligned on a vecWidth-bit boundary.
3926 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3928 MVT VT = N->getSimpleValueType(0);
3929 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3930 bool Result = (Index * ElSize) % vecWidth == 0;
3935 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3936 /// operand specifies a subvector insert that is suitable for input to
3937 /// insertion of 128 or 256-bit subvectors
3938 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3939 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3940 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3942 // The index should be aligned on a vecWidth-bit boundary.
3944 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3946 MVT VT = N->getSimpleValueType(0);
3947 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3948 bool Result = (Index * ElSize) % vecWidth == 0;
3953 bool X86::isVINSERT128Index(SDNode *N) {
3954 return isVINSERTIndex(N, 128);
3957 bool X86::isVINSERT256Index(SDNode *N) {
3958 return isVINSERTIndex(N, 256);
3961 bool X86::isVEXTRACT128Index(SDNode *N) {
3962 return isVEXTRACTIndex(N, 128);
3965 bool X86::isVEXTRACT256Index(SDNode *N) {
3966 return isVEXTRACTIndex(N, 256);
3969 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3970 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3971 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3972 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3975 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3977 MVT VecVT = N->getOperand(0).getSimpleValueType();
3978 MVT ElVT = VecVT.getVectorElementType();
3980 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3981 return Index / NumElemsPerChunk;
3984 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3985 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3986 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3987 llvm_unreachable("Illegal insert subvector for VINSERT");
3990 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3992 MVT VecVT = N->getSimpleValueType(0);
3993 MVT ElVT = VecVT.getVectorElementType();
3995 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3996 return Index / NumElemsPerChunk;
3999 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4000 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4001 /// and VINSERTI128 instructions.
4002 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4003 return getExtractVEXTRACTImmediate(N, 128);
4006 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4007 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4008 /// and VINSERTI64x4 instructions.
4009 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4010 return getExtractVEXTRACTImmediate(N, 256);
4013 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4014 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4015 /// and VINSERTI128 instructions.
4016 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4017 return getInsertVINSERTImmediate(N, 128);
4020 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4021 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4022 /// and VINSERTI64x4 instructions.
4023 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4024 return getInsertVINSERTImmediate(N, 256);
4027 /// isZero - Returns true if Elt is a constant integer zero
4028 static bool isZero(SDValue V) {
4029 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4030 return C && C->isNullValue();
4033 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4035 bool X86::isZeroNode(SDValue Elt) {
4038 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4039 return CFP->getValueAPF().isPosZero();
4043 /// getZeroVector - Returns a vector of specified type with all zero elements.
4045 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4046 SelectionDAG &DAG, SDLoc dl) {
4047 assert(VT.isVector() && "Expected a vector type");
4049 // Always build SSE zero vectors as <4 x i32> bitcasted
4050 // to their dest type. This ensures they get CSE'd.
4052 if (VT.is128BitVector()) { // SSE
4053 if (Subtarget->hasSSE2()) { // SSE2
4054 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4055 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4057 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4058 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4060 } else if (VT.is256BitVector()) { // AVX
4061 if (Subtarget->hasInt256()) { // AVX2
4062 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4063 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4064 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4066 // 256-bit logic and arithmetic instructions in AVX are all
4067 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4068 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4069 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4072 } else if (VT.is512BitVector()) { // AVX-512
4073 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4074 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4075 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4077 } else if (VT.getScalarType() == MVT::i1) {
4079 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4080 && "Unexpected vector type");
4081 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4082 && "Unexpected vector type");
4083 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4084 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4085 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4087 llvm_unreachable("Unexpected vector type");
4089 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4092 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4093 SelectionDAG &DAG, SDLoc dl,
4094 unsigned vectorWidth) {
4095 assert((vectorWidth == 128 || vectorWidth == 256) &&
4096 "Unsupported vector width");
4097 EVT VT = Vec.getValueType();
4098 EVT ElVT = VT.getVectorElementType();
4099 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4100 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4101 VT.getVectorNumElements()/Factor);
4103 // Extract from UNDEF is UNDEF.
4104 if (Vec.getOpcode() == ISD::UNDEF)
4105 return DAG.getUNDEF(ResultVT);
4107 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4108 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4110 // This is the index of the first element of the vectorWidth-bit chunk
4112 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4115 // If the input is a buildvector just emit a smaller one.
4116 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4117 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4118 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4122 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4125 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4126 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4127 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4128 /// instructions or a simple subregister reference. Idx is an index in the
4129 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4130 /// lowering EXTRACT_VECTOR_ELT operations easier.
4131 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4132 SelectionDAG &DAG, SDLoc dl) {
4133 assert((Vec.getValueType().is256BitVector() ||
4134 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4135 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4138 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4139 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4140 SelectionDAG &DAG, SDLoc dl) {
4141 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4142 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4145 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4146 unsigned IdxVal, SelectionDAG &DAG,
4147 SDLoc dl, unsigned vectorWidth) {
4148 assert((vectorWidth == 128 || vectorWidth == 256) &&
4149 "Unsupported vector width");
4150 // Inserting UNDEF is Result
4151 if (Vec.getOpcode() == ISD::UNDEF)
4153 EVT VT = Vec.getValueType();
4154 EVT ElVT = VT.getVectorElementType();
4155 EVT ResultVT = Result.getValueType();
4157 // Insert the relevant vectorWidth bits.
4158 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4160 // This is the index of the first element of the vectorWidth-bit chunk
4162 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4165 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4166 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4169 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4170 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4171 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4172 /// simple superregister reference. Idx is an index in the 128 bits
4173 /// we want. It need not be aligned to a 128-bit boundary. That makes
4174 /// lowering INSERT_VECTOR_ELT operations easier.
4175 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4176 SelectionDAG &DAG, SDLoc dl) {
4177 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4179 // For insertion into the zero index (low half) of a 256-bit vector, it is
4180 // more efficient to generate a blend with immediate instead of an insert*128.
4181 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4182 // extend the subvector to the size of the result vector. Make sure that
4183 // we are not recursing on that node by checking for undef here.
4184 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4185 Result.getOpcode() != ISD::UNDEF) {
4186 EVT ResultVT = Result.getValueType();
4187 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4188 SDValue Undef = DAG.getUNDEF(ResultVT);
4189 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4192 // The blend instruction, and therefore its mask, depend on the data type.
4193 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4194 if (ScalarType.isFloatingPoint()) {
4195 // Choose either vblendps (float) or vblendpd (double).
4196 unsigned ScalarSize = ScalarType.getSizeInBits();
4197 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4198 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4199 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4200 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4203 const X86Subtarget &Subtarget =
4204 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4206 // AVX2 is needed for 256-bit integer blend support.
4207 // Integers must be cast to 32-bit because there is only vpblendd;
4208 // vpblendw can't be used for this because it has a handicapped mask.
4210 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4211 // is still more efficient than using the wrong domain vinsertf128 that
4212 // will be created by InsertSubVector().
4213 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4215 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4216 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4217 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4218 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4221 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4224 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4225 SelectionDAG &DAG, SDLoc dl) {
4226 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4227 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4230 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4231 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4232 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4233 /// large BUILD_VECTORS.
4234 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4235 unsigned NumElems, SelectionDAG &DAG,
4237 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4238 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4241 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4242 unsigned NumElems, SelectionDAG &DAG,
4244 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4245 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4248 /// getOnesVector - Returns a vector of specified type with all bits set.
4249 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4250 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4251 /// Then bitcast to their original type, ensuring they get CSE'd.
4252 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4254 assert(VT.isVector() && "Expected a vector type");
4256 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4258 if (VT.is256BitVector()) {
4259 if (HasInt256) { // AVX2
4260 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4263 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4264 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4266 } else if (VT.is128BitVector()) {
4267 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4269 llvm_unreachable("Unexpected vector type");
4271 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4274 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4275 /// operation of specified width.
4276 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4278 unsigned NumElems = VT.getVectorNumElements();
4279 SmallVector<int, 8> Mask;
4280 Mask.push_back(NumElems);
4281 for (unsigned i = 1; i != NumElems; ++i)
4283 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4286 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4287 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4289 unsigned NumElems = VT.getVectorNumElements();
4290 SmallVector<int, 8> Mask;
4291 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4293 Mask.push_back(i + NumElems);
4295 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4298 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4299 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4301 unsigned NumElems = VT.getVectorNumElements();
4302 SmallVector<int, 8> Mask;
4303 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4304 Mask.push_back(i + Half);
4305 Mask.push_back(i + NumElems + Half);
4307 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4310 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4311 /// vector of zero or undef vector. This produces a shuffle where the low
4312 /// element of V2 is swizzled into the zero/undef vector, landing at element
4313 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4314 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4316 const X86Subtarget *Subtarget,
4317 SelectionDAG &DAG) {
4318 MVT VT = V2.getSimpleValueType();
4320 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4321 unsigned NumElems = VT.getVectorNumElements();
4322 SmallVector<int, 16> MaskVec;
4323 for (unsigned i = 0; i != NumElems; ++i)
4324 // If this is the insertion idx, put the low elt of V2 here.
4325 MaskVec.push_back(i == Idx ? NumElems : i);
4326 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4329 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4330 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4331 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4332 /// shuffles which use a single input multiple times, and in those cases it will
4333 /// adjust the mask to only have indices within that single input.
4334 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4335 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4336 unsigned NumElems = VT.getVectorNumElements();
4340 bool IsFakeUnary = false;
4341 switch(N->getOpcode()) {
4342 case X86ISD::BLENDI:
4343 ImmN = N->getOperand(N->getNumOperands()-1);
4344 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4347 ImmN = N->getOperand(N->getNumOperands()-1);
4348 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4349 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4351 case X86ISD::UNPCKH:
4352 DecodeUNPCKHMask(VT, Mask);
4353 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4355 case X86ISD::UNPCKL:
4356 DecodeUNPCKLMask(VT, Mask);
4357 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4359 case X86ISD::MOVHLPS:
4360 DecodeMOVHLPSMask(NumElems, Mask);
4361 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4363 case X86ISD::MOVLHPS:
4364 DecodeMOVLHPSMask(NumElems, Mask);
4365 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4367 case X86ISD::PALIGNR:
4368 ImmN = N->getOperand(N->getNumOperands()-1);
4369 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4371 case X86ISD::PSHUFD:
4372 case X86ISD::VPERMILPI:
4373 ImmN = N->getOperand(N->getNumOperands()-1);
4374 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4377 case X86ISD::PSHUFHW:
4378 ImmN = N->getOperand(N->getNumOperands()-1);
4379 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4382 case X86ISD::PSHUFLW:
4383 ImmN = N->getOperand(N->getNumOperands()-1);
4384 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4387 case X86ISD::PSHUFB: {
4389 SDValue MaskNode = N->getOperand(1);
4390 while (MaskNode->getOpcode() == ISD::BITCAST)
4391 MaskNode = MaskNode->getOperand(0);
4393 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4394 // If we have a build-vector, then things are easy.
4395 EVT VT = MaskNode.getValueType();
4396 assert(VT.isVector() &&
4397 "Can't produce a non-vector with a build_vector!");
4398 if (!VT.isInteger())
4401 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4403 SmallVector<uint64_t, 32> RawMask;
4404 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4405 SDValue Op = MaskNode->getOperand(i);
4406 if (Op->getOpcode() == ISD::UNDEF) {
4407 RawMask.push_back((uint64_t)SM_SentinelUndef);
4410 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4413 APInt MaskElement = CN->getAPIntValue();
4415 // We now have to decode the element which could be any integer size and
4416 // extract each byte of it.
4417 for (int j = 0; j < NumBytesPerElement; ++j) {
4418 // Note that this is x86 and so always little endian: the low byte is
4419 // the first byte of the mask.
4420 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4421 MaskElement = MaskElement.lshr(8);
4424 DecodePSHUFBMask(RawMask, Mask);
4428 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4432 SDValue Ptr = MaskLoad->getBasePtr();
4433 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4434 Ptr->getOpcode() == X86ISD::WrapperRIP)
4435 Ptr = Ptr->getOperand(0);
4437 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4438 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4441 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4442 DecodePSHUFBMask(C, Mask);
4450 case X86ISD::VPERMI:
4451 ImmN = N->getOperand(N->getNumOperands()-1);
4452 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4457 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4459 case X86ISD::VPERM2X128:
4460 ImmN = N->getOperand(N->getNumOperands()-1);
4461 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4462 if (Mask.empty()) return false;
4464 case X86ISD::MOVSLDUP:
4465 DecodeMOVSLDUPMask(VT, Mask);
4468 case X86ISD::MOVSHDUP:
4469 DecodeMOVSHDUPMask(VT, Mask);
4472 case X86ISD::MOVDDUP:
4473 DecodeMOVDDUPMask(VT, Mask);
4476 case X86ISD::MOVLHPD:
4477 case X86ISD::MOVLPD:
4478 case X86ISD::MOVLPS:
4479 // Not yet implemented
4481 default: llvm_unreachable("unknown target shuffle node");
4484 // If we have a fake unary shuffle, the shuffle mask is spread across two
4485 // inputs that are actually the same node. Re-map the mask to always point
4486 // into the first input.
4489 if (M >= (int)Mask.size())
4495 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4496 /// element of the result of the vector shuffle.
4497 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4500 return SDValue(); // Limit search depth.
4502 SDValue V = SDValue(N, 0);
4503 EVT VT = V.getValueType();
4504 unsigned Opcode = V.getOpcode();
4506 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4507 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4508 int Elt = SV->getMaskElt(Index);
4511 return DAG.getUNDEF(VT.getVectorElementType());
4513 unsigned NumElems = VT.getVectorNumElements();
4514 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4515 : SV->getOperand(1);
4516 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4519 // Recurse into target specific vector shuffles to find scalars.
4520 if (isTargetShuffle(Opcode)) {
4521 MVT ShufVT = V.getSimpleValueType();
4522 unsigned NumElems = ShufVT.getVectorNumElements();
4523 SmallVector<int, 16> ShuffleMask;
4526 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4529 int Elt = ShuffleMask[Index];
4531 return DAG.getUNDEF(ShufVT.getVectorElementType());
4533 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4535 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4539 // Actual nodes that may contain scalar elements
4540 if (Opcode == ISD::BITCAST) {
4541 V = V.getOperand(0);
4542 EVT SrcVT = V.getValueType();
4543 unsigned NumElems = VT.getVectorNumElements();
4545 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4549 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4550 return (Index == 0) ? V.getOperand(0)
4551 : DAG.getUNDEF(VT.getVectorElementType());
4553 if (V.getOpcode() == ISD::BUILD_VECTOR)
4554 return V.getOperand(Index);
4559 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4561 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4562 unsigned NumNonZero, unsigned NumZero,
4564 const X86Subtarget* Subtarget,
4565 const TargetLowering &TLI) {
4573 // SSE4.1 - use PINSRB to insert each byte directly.
4574 if (Subtarget->hasSSE41()) {
4575 for (unsigned i = 0; i < 16; ++i) {
4576 bool isNonZero = (NonZeros & (1 << i)) != 0;
4580 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4582 V = DAG.getUNDEF(MVT::v16i8);
4585 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4586 MVT::v16i8, V, Op.getOperand(i),
4587 DAG.getIntPtrConstant(i, dl));
4594 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4595 for (unsigned i = 0; i < 16; ++i) {
4596 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4597 if (ThisIsNonZero && First) {
4599 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4601 V = DAG.getUNDEF(MVT::v8i16);
4606 SDValue ThisElt, LastElt;
4607 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4608 if (LastIsNonZero) {
4609 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4610 MVT::i16, Op.getOperand(i-1));
4612 if (ThisIsNonZero) {
4613 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4614 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4615 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4617 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4621 if (ThisElt.getNode())
4622 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4623 DAG.getIntPtrConstant(i/2, dl));
4627 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4630 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4632 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4633 unsigned NumNonZero, unsigned NumZero,
4635 const X86Subtarget* Subtarget,
4636 const TargetLowering &TLI) {
4643 for (unsigned i = 0; i < 8; ++i) {
4644 bool isNonZero = (NonZeros & (1 << i)) != 0;
4648 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4650 V = DAG.getUNDEF(MVT::v8i16);
4653 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4654 MVT::v8i16, V, Op.getOperand(i),
4655 DAG.getIntPtrConstant(i, dl));
4662 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4663 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4664 const X86Subtarget *Subtarget,
4665 const TargetLowering &TLI) {
4666 // Find all zeroable elements.
4667 std::bitset<4> Zeroable;
4668 for (int i=0; i < 4; ++i) {
4669 SDValue Elt = Op->getOperand(i);
4670 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4672 assert(Zeroable.size() - Zeroable.count() > 1 &&
4673 "We expect at least two non-zero elements!");
4675 // We only know how to deal with build_vector nodes where elements are either
4676 // zeroable or extract_vector_elt with constant index.
4677 SDValue FirstNonZero;
4678 unsigned FirstNonZeroIdx;
4679 for (unsigned i=0; i < 4; ++i) {
4682 SDValue Elt = Op->getOperand(i);
4683 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4684 !isa<ConstantSDNode>(Elt.getOperand(1)))
4686 // Make sure that this node is extracting from a 128-bit vector.
4687 MVT VT = Elt.getOperand(0).getSimpleValueType();
4688 if (!VT.is128BitVector())
4690 if (!FirstNonZero.getNode()) {
4692 FirstNonZeroIdx = i;
4696 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4697 SDValue V1 = FirstNonZero.getOperand(0);
4698 MVT VT = V1.getSimpleValueType();
4700 // See if this build_vector can be lowered as a blend with zero.
4702 unsigned EltMaskIdx, EltIdx;
4704 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4705 if (Zeroable[EltIdx]) {
4706 // The zero vector will be on the right hand side.
4707 Mask[EltIdx] = EltIdx+4;
4711 Elt = Op->getOperand(EltIdx);
4712 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4713 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4714 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4716 Mask[EltIdx] = EltIdx;
4720 // Let the shuffle legalizer deal with blend operations.
4721 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4722 if (V1.getSimpleValueType() != VT)
4723 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4724 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4727 // See if we can lower this build_vector to a INSERTPS.
4728 if (!Subtarget->hasSSE41())
4731 SDValue V2 = Elt.getOperand(0);
4732 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4735 bool CanFold = true;
4736 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4740 SDValue Current = Op->getOperand(i);
4741 SDValue SrcVector = Current->getOperand(0);
4744 CanFold = SrcVector == V1 &&
4745 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4751 assert(V1.getNode() && "Expected at least two non-zero elements!");
4752 if (V1.getSimpleValueType() != MVT::v4f32)
4753 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4754 if (V2.getSimpleValueType() != MVT::v4f32)
4755 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4757 // Ok, we can emit an INSERTPS instruction.
4758 unsigned ZMask = Zeroable.to_ulong();
4760 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4761 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4763 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4764 DAG.getIntPtrConstant(InsertPSMask, DL));
4765 return DAG.getNode(ISD::BITCAST, DL, VT, Result);
4768 /// Return a vector logical shift node.
4769 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4770 unsigned NumBits, SelectionDAG &DAG,
4771 const TargetLowering &TLI, SDLoc dl) {
4772 assert(VT.is128BitVector() && "Unknown type for VShift");
4773 MVT ShVT = MVT::v2i64;
4774 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4775 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4776 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4777 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4778 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4779 return DAG.getNode(ISD::BITCAST, dl, VT,
4780 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4784 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4786 // Check if the scalar load can be widened into a vector load. And if
4787 // the address is "base + cst" see if the cst can be "absorbed" into
4788 // the shuffle mask.
4789 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4790 SDValue Ptr = LD->getBasePtr();
4791 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4793 EVT PVT = LD->getValueType(0);
4794 if (PVT != MVT::i32 && PVT != MVT::f32)
4799 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4800 FI = FINode->getIndex();
4802 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4803 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4804 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4805 Offset = Ptr.getConstantOperandVal(1);
4806 Ptr = Ptr.getOperand(0);
4811 // FIXME: 256-bit vector instructions don't require a strict alignment,
4812 // improve this code to support it better.
4813 unsigned RequiredAlign = VT.getSizeInBits()/8;
4814 SDValue Chain = LD->getChain();
4815 // Make sure the stack object alignment is at least 16 or 32.
4816 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4817 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4818 if (MFI->isFixedObjectIndex(FI)) {
4819 // Can't change the alignment. FIXME: It's possible to compute
4820 // the exact stack offset and reference FI + adjust offset instead.
4821 // If someone *really* cares about this. That's the way to implement it.
4824 MFI->setObjectAlignment(FI, RequiredAlign);
4828 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4829 // Ptr + (Offset & ~15).
4832 if ((Offset % RequiredAlign) & 3)
4834 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4837 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4838 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4841 int EltNo = (Offset - StartOffset) >> 2;
4842 unsigned NumElems = VT.getVectorNumElements();
4844 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4845 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4846 LD->getPointerInfo().getWithOffset(StartOffset),
4847 false, false, false, 0);
4849 SmallVector<int, 8> Mask(NumElems, EltNo);
4851 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4857 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4858 /// elements can be replaced by a single large load which has the same value as
4859 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4861 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4863 /// FIXME: we'd also like to handle the case where the last elements are zero
4864 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4865 /// There's even a handy isZeroNode for that purpose.
4866 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4867 SDLoc &DL, SelectionDAG &DAG,
4868 bool isAfterLegalize) {
4869 unsigned NumElems = Elts.size();
4871 LoadSDNode *LDBase = nullptr;
4872 unsigned LastLoadedElt = -1U;
4874 // For each element in the initializer, see if we've found a load or an undef.
4875 // If we don't find an initial load element, or later load elements are
4876 // non-consecutive, bail out.
4877 for (unsigned i = 0; i < NumElems; ++i) {
4878 SDValue Elt = Elts[i];
4879 // Look through a bitcast.
4880 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4881 Elt = Elt.getOperand(0);
4882 if (!Elt.getNode() ||
4883 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4886 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4888 LDBase = cast<LoadSDNode>(Elt.getNode());
4892 if (Elt.getOpcode() == ISD::UNDEF)
4895 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4896 EVT LdVT = Elt.getValueType();
4897 // Each loaded element must be the correct fractional portion of the
4898 // requested vector load.
4899 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4901 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4906 // If we have found an entire vector of loads and undefs, then return a large
4907 // load of the entire vector width starting at the base pointer. If we found
4908 // consecutive loads for the low half, generate a vzext_load node.
4909 if (LastLoadedElt == NumElems - 1) {
4910 assert(LDBase && "Did not find base load for merging consecutive loads");
4911 EVT EltVT = LDBase->getValueType(0);
4912 // Ensure that the input vector size for the merged loads matches the
4913 // cumulative size of the input elements.
4914 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4917 if (isAfterLegalize &&
4918 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4921 SDValue NewLd = SDValue();
4923 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4924 LDBase->getPointerInfo(), LDBase->isVolatile(),
4925 LDBase->isNonTemporal(), LDBase->isInvariant(),
4926 LDBase->getAlignment());
4928 if (LDBase->hasAnyUseOfValue(1)) {
4929 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4931 SDValue(NewLd.getNode(), 1));
4932 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4933 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4934 SDValue(NewLd.getNode(), 1));
4940 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4941 //of a v4i32 / v4f32. It's probably worth generalizing.
4942 EVT EltVT = VT.getVectorElementType();
4943 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4944 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4945 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4946 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4948 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4949 LDBase->getPointerInfo(),
4950 LDBase->getAlignment(),
4951 false/*isVolatile*/, true/*ReadMem*/,
4954 // Make sure the newly-created LOAD is in the same position as LDBase in
4955 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4956 // update uses of LDBase's output chain to use the TokenFactor.
4957 if (LDBase->hasAnyUseOfValue(1)) {
4958 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4959 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4960 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4961 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4962 SDValue(ResNode.getNode(), 1));
4965 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4970 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4971 /// to generate a splat value for the following cases:
4972 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4973 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4974 /// a scalar load, or a constant.
4975 /// The VBROADCAST node is returned when a pattern is found,
4976 /// or SDValue() otherwise.
4977 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4978 SelectionDAG &DAG) {
4979 // VBROADCAST requires AVX.
4980 // TODO: Splats could be generated for non-AVX CPUs using SSE
4981 // instructions, but there's less potential gain for only 128-bit vectors.
4982 if (!Subtarget->hasAVX())
4985 MVT VT = Op.getSimpleValueType();
4988 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4989 "Unsupported vector type for broadcast.");
4994 switch (Op.getOpcode()) {
4996 // Unknown pattern found.
4999 case ISD::BUILD_VECTOR: {
5000 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5001 BitVector UndefElements;
5002 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5004 // We need a splat of a single value to use broadcast, and it doesn't
5005 // make any sense if the value is only in one element of the vector.
5006 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5010 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5011 Ld.getOpcode() == ISD::ConstantFP);
5013 // Make sure that all of the users of a non-constant load are from the
5014 // BUILD_VECTOR node.
5015 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5020 case ISD::VECTOR_SHUFFLE: {
5021 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5023 // Shuffles must have a splat mask where the first element is
5025 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5028 SDValue Sc = Op.getOperand(0);
5029 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5030 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5032 if (!Subtarget->hasInt256())
5035 // Use the register form of the broadcast instruction available on AVX2.
5036 if (VT.getSizeInBits() >= 256)
5037 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5038 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5041 Ld = Sc.getOperand(0);
5042 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5043 Ld.getOpcode() == ISD::ConstantFP);
5045 // The scalar_to_vector node and the suspected
5046 // load node must have exactly one user.
5047 // Constants may have multiple users.
5049 // AVX-512 has register version of the broadcast
5050 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5051 Ld.getValueType().getSizeInBits() >= 32;
5052 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5059 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5060 bool IsGE256 = (VT.getSizeInBits() >= 256);
5062 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5063 // instruction to save 8 or more bytes of constant pool data.
5064 // TODO: If multiple splats are generated to load the same constant,
5065 // it may be detrimental to overall size. There needs to be a way to detect
5066 // that condition to know if this is truly a size win.
5067 const Function *F = DAG.getMachineFunction().getFunction();
5068 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5070 // Handle broadcasting a single constant scalar from the constant pool
5072 // On Sandybridge (no AVX2), it is still better to load a constant vector
5073 // from the constant pool and not to broadcast it from a scalar.
5074 // But override that restriction when optimizing for size.
5075 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5076 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5077 EVT CVT = Ld.getValueType();
5078 assert(!CVT.isVector() && "Must not broadcast a vector type");
5080 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5081 // For size optimization, also splat v2f64 and v2i64, and for size opt
5082 // with AVX2, also splat i8 and i16.
5083 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5084 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5085 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5086 const Constant *C = nullptr;
5087 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5088 C = CI->getConstantIntValue();
5089 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5090 C = CF->getConstantFPValue();
5092 assert(C && "Invalid constant type");
5094 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5095 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5096 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5097 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5098 MachinePointerInfo::getConstantPool(),
5099 false, false, false, Alignment);
5101 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5105 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5107 // Handle AVX2 in-register broadcasts.
5108 if (!IsLoad && Subtarget->hasInt256() &&
5109 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5110 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5112 // The scalar source must be a normal load.
5116 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5117 (Subtarget->hasVLX() && ScalarSize == 64))
5118 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5120 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5121 // double since there is no vbroadcastsd xmm
5122 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5123 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5124 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5127 // Unsupported broadcast.
5131 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5132 /// underlying vector and index.
5134 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5136 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5138 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5139 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5142 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5144 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5146 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5147 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5150 // In this case the vector is the extract_subvector expression and the index
5151 // is 2, as specified by the shuffle.
5152 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5153 SDValue ShuffleVec = SVOp->getOperand(0);
5154 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5155 assert(ShuffleVecVT.getVectorElementType() ==
5156 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5158 int ShuffleIdx = SVOp->getMaskElt(Idx);
5159 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5160 ExtractedFromVec = ShuffleVec;
5166 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5167 MVT VT = Op.getSimpleValueType();
5169 // Skip if insert_vec_elt is not supported.
5170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5171 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5175 unsigned NumElems = Op.getNumOperands();
5179 SmallVector<unsigned, 4> InsertIndices;
5180 SmallVector<int, 8> Mask(NumElems, -1);
5182 for (unsigned i = 0; i != NumElems; ++i) {
5183 unsigned Opc = Op.getOperand(i).getOpcode();
5185 if (Opc == ISD::UNDEF)
5188 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5189 // Quit if more than 1 elements need inserting.
5190 if (InsertIndices.size() > 1)
5193 InsertIndices.push_back(i);
5197 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5198 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5199 // Quit if non-constant index.
5200 if (!isa<ConstantSDNode>(ExtIdx))
5202 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5204 // Quit if extracted from vector of different type.
5205 if (ExtractedFromVec.getValueType() != VT)
5208 if (!VecIn1.getNode())
5209 VecIn1 = ExtractedFromVec;
5210 else if (VecIn1 != ExtractedFromVec) {
5211 if (!VecIn2.getNode())
5212 VecIn2 = ExtractedFromVec;
5213 else if (VecIn2 != ExtractedFromVec)
5214 // Quit if more than 2 vectors to shuffle
5218 if (ExtractedFromVec == VecIn1)
5220 else if (ExtractedFromVec == VecIn2)
5221 Mask[i] = Idx + NumElems;
5224 if (!VecIn1.getNode())
5227 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5228 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5229 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5230 unsigned Idx = InsertIndices[i];
5231 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5232 DAG.getIntPtrConstant(Idx, DL));
5238 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5239 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5240 Op.getScalarValueSizeInBits() == 1 &&
5241 "Can not convert non-constant vector");
5242 uint64_t Immediate = 0;
5243 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5244 SDValue In = Op.getOperand(idx);
5245 if (In.getOpcode() != ISD::UNDEF)
5246 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5250 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5251 return DAG.getConstant(Immediate, dl, VT);
5253 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5255 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5257 MVT VT = Op.getSimpleValueType();
5258 assert((VT.getVectorElementType() == MVT::i1) &&
5259 "Unexpected type in LowerBUILD_VECTORvXi1!");
5262 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5263 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5264 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5265 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5268 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5269 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5270 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5271 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5274 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5275 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5276 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5277 return DAG.getNode(ISD::BITCAST, dl, VT, Imm);
5278 SDValue ExtVec = DAG.getNode(ISD::BITCAST, dl, MVT::v8i1, Imm);
5279 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5280 DAG.getIntPtrConstant(0, dl));
5283 // Vector has one or more non-const elements
5284 uint64_t Immediate = 0;
5285 SmallVector<unsigned, 16> NonConstIdx;
5286 bool IsSplat = true;
5287 bool HasConstElts = false;
5289 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5290 SDValue In = Op.getOperand(idx);
5291 if (In.getOpcode() == ISD::UNDEF)
5293 if (!isa<ConstantSDNode>(In))
5294 NonConstIdx.push_back(idx);
5296 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5297 HasConstElts = true;
5301 else if (In != Op.getOperand(SplatIdx))
5305 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5307 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5308 DAG.getConstant(1, dl, VT),
5309 DAG.getConstant(0, dl, VT));
5311 // insert elements one by one
5315 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5316 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5318 else if (HasConstElts)
5319 Imm = DAG.getConstant(0, dl, VT);
5321 Imm = DAG.getUNDEF(VT);
5322 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5323 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, Imm);
5325 SDValue ExtVec = DAG.getNode(ISD::BITCAST, dl, MVT::v8i1, Imm);
5326 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5327 DAG.getIntPtrConstant(0, dl));
5330 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5331 unsigned InsertIdx = NonConstIdx[i];
5332 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5333 Op.getOperand(InsertIdx),
5334 DAG.getIntPtrConstant(InsertIdx, dl));
5339 /// \brief Return true if \p N implements a horizontal binop and return the
5340 /// operands for the horizontal binop into V0 and V1.
5342 /// This is a helper function of LowerToHorizontalOp().
5343 /// This function checks that the build_vector \p N in input implements a
5344 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5345 /// operation to match.
5346 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5347 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5348 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5351 /// This function only analyzes elements of \p N whose indices are
5352 /// in range [BaseIdx, LastIdx).
5353 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5355 unsigned BaseIdx, unsigned LastIdx,
5356 SDValue &V0, SDValue &V1) {
5357 EVT VT = N->getValueType(0);
5359 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5360 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5361 "Invalid Vector in input!");
5363 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5364 bool CanFold = true;
5365 unsigned ExpectedVExtractIdx = BaseIdx;
5366 unsigned NumElts = LastIdx - BaseIdx;
5367 V0 = DAG.getUNDEF(VT);
5368 V1 = DAG.getUNDEF(VT);
5370 // Check if N implements a horizontal binop.
5371 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5372 SDValue Op = N->getOperand(i + BaseIdx);
5375 if (Op->getOpcode() == ISD::UNDEF) {
5376 // Update the expected vector extract index.
5377 if (i * 2 == NumElts)
5378 ExpectedVExtractIdx = BaseIdx;
5379 ExpectedVExtractIdx += 2;
5383 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5388 SDValue Op0 = Op.getOperand(0);
5389 SDValue Op1 = Op.getOperand(1);
5391 // Try to match the following pattern:
5392 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5393 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5394 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5395 Op0.getOperand(0) == Op1.getOperand(0) &&
5396 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5397 isa<ConstantSDNode>(Op1.getOperand(1)));
5401 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5402 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5404 if (i * 2 < NumElts) {
5405 if (V0.getOpcode() == ISD::UNDEF) {
5406 V0 = Op0.getOperand(0);
5407 if (V0.getValueType() != VT)
5411 if (V1.getOpcode() == ISD::UNDEF) {
5412 V1 = Op0.getOperand(0);
5413 if (V1.getValueType() != VT)
5416 if (i * 2 == NumElts)
5417 ExpectedVExtractIdx = BaseIdx;
5420 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5421 if (I0 == ExpectedVExtractIdx)
5422 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5423 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5424 // Try to match the following dag sequence:
5425 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5426 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5430 ExpectedVExtractIdx += 2;
5436 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5437 /// a concat_vector.
5439 /// This is a helper function of LowerToHorizontalOp().
5440 /// This function expects two 256-bit vectors called V0 and V1.
5441 /// At first, each vector is split into two separate 128-bit vectors.
5442 /// Then, the resulting 128-bit vectors are used to implement two
5443 /// horizontal binary operations.
5445 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5447 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5448 /// the two new horizontal binop.
5449 /// When Mode is set, the first horizontal binop dag node would take as input
5450 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5451 /// horizontal binop dag node would take as input the lower 128-bit of V1
5452 /// and the upper 128-bit of V1.
5454 /// HADD V0_LO, V0_HI
5455 /// HADD V1_LO, V1_HI
5457 /// Otherwise, the first horizontal binop dag node takes as input the lower
5458 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5459 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5461 /// HADD V0_LO, V1_LO
5462 /// HADD V0_HI, V1_HI
5464 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5465 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5466 /// the upper 128-bits of the result.
5467 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5468 SDLoc DL, SelectionDAG &DAG,
5469 unsigned X86Opcode, bool Mode,
5470 bool isUndefLO, bool isUndefHI) {
5471 EVT VT = V0.getValueType();
5472 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5473 "Invalid nodes in input!");
5475 unsigned NumElts = VT.getVectorNumElements();
5476 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5477 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5478 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5479 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5480 EVT NewVT = V0_LO.getValueType();
5482 SDValue LO = DAG.getUNDEF(NewVT);
5483 SDValue HI = DAG.getUNDEF(NewVT);
5486 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5487 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5488 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5489 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5490 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5492 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5493 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5494 V1_LO->getOpcode() != ISD::UNDEF))
5495 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5497 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5498 V1_HI->getOpcode() != ISD::UNDEF))
5499 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5502 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5505 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5507 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5508 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5509 EVT VT = BV->getValueType(0);
5510 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5511 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5515 unsigned NumElts = VT.getVectorNumElements();
5516 SDValue InVec0 = DAG.getUNDEF(VT);
5517 SDValue InVec1 = DAG.getUNDEF(VT);
5519 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5520 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5522 // Odd-numbered elements in the input build vector are obtained from
5523 // adding two integer/float elements.
5524 // Even-numbered elements in the input build vector are obtained from
5525 // subtracting two integer/float elements.
5526 unsigned ExpectedOpcode = ISD::FSUB;
5527 unsigned NextExpectedOpcode = ISD::FADD;
5528 bool AddFound = false;
5529 bool SubFound = false;
5531 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5532 SDValue Op = BV->getOperand(i);
5534 // Skip 'undef' values.
5535 unsigned Opcode = Op.getOpcode();
5536 if (Opcode == ISD::UNDEF) {
5537 std::swap(ExpectedOpcode, NextExpectedOpcode);
5541 // Early exit if we found an unexpected opcode.
5542 if (Opcode != ExpectedOpcode)
5545 SDValue Op0 = Op.getOperand(0);
5546 SDValue Op1 = Op.getOperand(1);
5548 // Try to match the following pattern:
5549 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5550 // Early exit if we cannot match that sequence.
5551 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5552 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5553 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5554 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5555 Op0.getOperand(1) != Op1.getOperand(1))
5558 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5562 // We found a valid add/sub node. Update the information accordingly.
5568 // Update InVec0 and InVec1.
5569 if (InVec0.getOpcode() == ISD::UNDEF) {
5570 InVec0 = Op0.getOperand(0);
5571 if (InVec0.getValueType() != VT)
5574 if (InVec1.getOpcode() == ISD::UNDEF) {
5575 InVec1 = Op1.getOperand(0);
5576 if (InVec1.getValueType() != VT)
5580 // Make sure that operands in input to each add/sub node always
5581 // come from a same pair of vectors.
5582 if (InVec0 != Op0.getOperand(0)) {
5583 if (ExpectedOpcode == ISD::FSUB)
5586 // FADD is commutable. Try to commute the operands
5587 // and then test again.
5588 std::swap(Op0, Op1);
5589 if (InVec0 != Op0.getOperand(0))
5593 if (InVec1 != Op1.getOperand(0))
5596 // Update the pair of expected opcodes.
5597 std::swap(ExpectedOpcode, NextExpectedOpcode);
5600 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5601 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5602 InVec1.getOpcode() != ISD::UNDEF)
5603 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5608 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5609 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5610 const X86Subtarget *Subtarget,
5611 SelectionDAG &DAG) {
5612 EVT VT = BV->getValueType(0);
5613 unsigned NumElts = VT.getVectorNumElements();
5614 unsigned NumUndefsLO = 0;
5615 unsigned NumUndefsHI = 0;
5616 unsigned Half = NumElts/2;
5618 // Count the number of UNDEF operands in the build_vector in input.
5619 for (unsigned i = 0, e = Half; i != e; ++i)
5620 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5623 for (unsigned i = Half, e = NumElts; i != e; ++i)
5624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5627 // Early exit if this is either a build_vector of all UNDEFs or all the
5628 // operands but one are UNDEF.
5629 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5633 SDValue InVec0, InVec1;
5634 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5635 // Try to match an SSE3 float HADD/HSUB.
5636 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5637 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5639 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5640 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5641 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5642 // Try to match an SSSE3 integer HADD/HSUB.
5643 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5644 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5646 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5647 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5650 if (!Subtarget->hasAVX())
5653 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5654 // Try to match an AVX horizontal add/sub of packed single/double
5655 // precision floating point values from 256-bit vectors.
5656 SDValue InVec2, InVec3;
5657 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5658 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5659 ((InVec0.getOpcode() == ISD::UNDEF ||
5660 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5661 ((InVec1.getOpcode() == ISD::UNDEF ||
5662 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5663 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5665 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5666 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5667 ((InVec0.getOpcode() == ISD::UNDEF ||
5668 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5669 ((InVec1.getOpcode() == ISD::UNDEF ||
5670 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5671 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5672 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5673 // Try to match an AVX2 horizontal add/sub of signed integers.
5674 SDValue InVec2, InVec3;
5676 bool CanFold = true;
5678 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5679 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5680 ((InVec0.getOpcode() == ISD::UNDEF ||
5681 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5682 ((InVec1.getOpcode() == ISD::UNDEF ||
5683 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5684 X86Opcode = X86ISD::HADD;
5685 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5686 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5687 ((InVec0.getOpcode() == ISD::UNDEF ||
5688 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5689 ((InVec1.getOpcode() == ISD::UNDEF ||
5690 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5691 X86Opcode = X86ISD::HSUB;
5696 // Fold this build_vector into a single horizontal add/sub.
5697 // Do this only if the target has AVX2.
5698 if (Subtarget->hasAVX2())
5699 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5701 // Do not try to expand this build_vector into a pair of horizontal
5702 // add/sub if we can emit a pair of scalar add/sub.
5703 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5706 // Convert this build_vector into a pair of horizontal binop followed by
5708 bool isUndefLO = NumUndefsLO == Half;
5709 bool isUndefHI = NumUndefsHI == Half;
5710 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5711 isUndefLO, isUndefHI);
5715 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5716 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5718 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5719 X86Opcode = X86ISD::HADD;
5720 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5721 X86Opcode = X86ISD::HSUB;
5722 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5723 X86Opcode = X86ISD::FHADD;
5724 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5725 X86Opcode = X86ISD::FHSUB;
5729 // Don't try to expand this build_vector into a pair of horizontal add/sub
5730 // if we can simply emit a pair of scalar add/sub.
5731 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5734 // Convert this build_vector into two horizontal add/sub followed by
5736 bool isUndefLO = NumUndefsLO == Half;
5737 bool isUndefHI = NumUndefsHI == Half;
5738 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5739 isUndefLO, isUndefHI);
5746 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5749 MVT VT = Op.getSimpleValueType();
5750 MVT ExtVT = VT.getVectorElementType();
5751 unsigned NumElems = Op.getNumOperands();
5753 // Generate vectors for predicate vectors.
5754 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5755 return LowerBUILD_VECTORvXi1(Op, DAG);
5757 // Vectors containing all zeros can be matched by pxor and xorps later
5758 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5759 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5760 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5761 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5764 return getZeroVector(VT, Subtarget, DAG, dl);
5767 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5768 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5769 // vpcmpeqd on 256-bit vectors.
5770 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5771 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5774 if (!VT.is512BitVector())
5775 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5778 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5779 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5781 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5782 return HorizontalOp;
5783 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5786 unsigned EVTBits = ExtVT.getSizeInBits();
5788 unsigned NumZero = 0;
5789 unsigned NumNonZero = 0;
5790 unsigned NonZeros = 0;
5791 bool IsAllConstants = true;
5792 SmallSet<SDValue, 8> Values;
5793 for (unsigned i = 0; i < NumElems; ++i) {
5794 SDValue Elt = Op.getOperand(i);
5795 if (Elt.getOpcode() == ISD::UNDEF)
5798 if (Elt.getOpcode() != ISD::Constant &&
5799 Elt.getOpcode() != ISD::ConstantFP)
5800 IsAllConstants = false;
5801 if (X86::isZeroNode(Elt))
5804 NonZeros |= (1 << i);
5809 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5810 if (NumNonZero == 0)
5811 return DAG.getUNDEF(VT);
5813 // Special case for single non-zero, non-undef, element.
5814 if (NumNonZero == 1) {
5815 unsigned Idx = countTrailingZeros(NonZeros);
5816 SDValue Item = Op.getOperand(Idx);
5818 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5819 // the value are obviously zero, truncate the value to i32 and do the
5820 // insertion that way. Only do this if the value is non-constant or if the
5821 // value is a constant being inserted into element 0. It is cheaper to do
5822 // a constant pool load than it is to do a movd + shuffle.
5823 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5824 (!IsAllConstants || Idx == 0)) {
5825 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5827 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5828 EVT VecVT = MVT::v4i32;
5830 // Truncate the value (which may itself be a constant) to i32, and
5831 // convert it to a vector with movd (S2V+shuffle to zero extend).
5832 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5833 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5835 ISD::BITCAST, dl, VT,
5836 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5840 // If we have a constant or non-constant insertion into the low element of
5841 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5842 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5843 // depending on what the source datatype is.
5846 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5848 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5849 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5850 if (VT.is512BitVector()) {
5851 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5852 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5853 Item, DAG.getIntPtrConstant(0, dl));
5855 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5856 "Expected an SSE value type!");
5857 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5858 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5859 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5862 // We can't directly insert an i8 or i16 into a vector, so zero extend
5864 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5865 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5866 if (VT.is256BitVector()) {
5867 if (Subtarget->hasAVX()) {
5868 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5869 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5871 // Without AVX, we need to extend to a 128-bit vector and then
5872 // insert into the 256-bit vector.
5873 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5874 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5875 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5878 assert(VT.is128BitVector() && "Expected an SSE value type!");
5879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5880 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5882 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5886 // Is it a vector logical left shift?
5887 if (NumElems == 2 && Idx == 1 &&
5888 X86::isZeroNode(Op.getOperand(0)) &&
5889 !X86::isZeroNode(Op.getOperand(1))) {
5890 unsigned NumBits = VT.getSizeInBits();
5891 return getVShift(true, VT,
5892 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5893 VT, Op.getOperand(1)),
5894 NumBits/2, DAG, *this, dl);
5897 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5900 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5901 // is a non-constant being inserted into an element other than the low one,
5902 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5903 // movd/movss) to move this into the low element, then shuffle it into
5905 if (EVTBits == 32) {
5906 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5907 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5911 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5912 if (Values.size() == 1) {
5913 if (EVTBits == 32) {
5914 // Instead of a shuffle like this:
5915 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5916 // Check if it's possible to issue this instead.
5917 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5918 unsigned Idx = countTrailingZeros(NonZeros);
5919 SDValue Item = Op.getOperand(Idx);
5920 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5921 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5926 // A vector full of immediates; various special cases are already
5927 // handled, so this is best done with a single constant-pool load.
5931 // For AVX-length vectors, see if we can use a vector load to get all of the
5932 // elements, otherwise build the individual 128-bit pieces and use
5933 // shuffles to put them in place.
5934 if (VT.is256BitVector() || VT.is512BitVector()) {
5935 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5937 // Check for a build vector of consecutive loads.
5938 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5941 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5943 // Build both the lower and upper subvector.
5944 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5945 makeArrayRef(&V[0], NumElems/2));
5946 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5947 makeArrayRef(&V[NumElems / 2], NumElems/2));
5949 // Recreate the wider vector with the lower and upper part.
5950 if (VT.is256BitVector())
5951 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5952 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5955 // Let legalizer expand 2-wide build_vectors.
5956 if (EVTBits == 64) {
5957 if (NumNonZero == 1) {
5958 // One half is zero or undef.
5959 unsigned Idx = countTrailingZeros(NonZeros);
5960 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5961 Op.getOperand(Idx));
5962 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5967 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5968 if (EVTBits == 8 && NumElems == 16)
5969 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5973 if (EVTBits == 16 && NumElems == 8)
5974 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5978 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5979 if (EVTBits == 32 && NumElems == 4)
5980 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5983 // If element VT is == 32 bits, turn it into a number of shuffles.
5984 SmallVector<SDValue, 8> V(NumElems);
5985 if (NumElems == 4 && NumZero > 0) {
5986 for (unsigned i = 0; i < 4; ++i) {
5987 bool isZero = !(NonZeros & (1 << i));
5989 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5991 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5994 for (unsigned i = 0; i < 2; ++i) {
5995 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5998 V[i] = V[i*2]; // Must be a zero vector.
6001 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6004 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6007 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6012 bool Reverse1 = (NonZeros & 0x3) == 2;
6013 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6017 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6018 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6020 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6023 if (Values.size() > 1 && VT.is128BitVector()) {
6024 // Check for a build vector of consecutive loads.
6025 for (unsigned i = 0; i < NumElems; ++i)
6026 V[i] = Op.getOperand(i);
6028 // Check for elements which are consecutive loads.
6029 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6032 // Check for a build vector from mostly shuffle plus few inserting.
6033 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6036 // For SSE 4.1, use insertps to put the high elements into the low element.
6037 if (Subtarget->hasSSE41()) {
6039 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6040 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6042 Result = DAG.getUNDEF(VT);
6044 for (unsigned i = 1; i < NumElems; ++i) {
6045 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6046 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6047 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6052 // Otherwise, expand into a number of unpckl*, start by extending each of
6053 // our (non-undef) elements to the full vector width with the element in the
6054 // bottom slot of the vector (which generates no code for SSE).
6055 for (unsigned i = 0; i < NumElems; ++i) {
6056 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6057 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6059 V[i] = DAG.getUNDEF(VT);
6062 // Next, we iteratively mix elements, e.g. for v4f32:
6063 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6064 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6065 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6066 unsigned EltStride = NumElems >> 1;
6067 while (EltStride != 0) {
6068 for (unsigned i = 0; i < EltStride; ++i) {
6069 // If V[i+EltStride] is undef and this is the first round of mixing,
6070 // then it is safe to just drop this shuffle: V[i] is already in the
6071 // right place, the one element (since it's the first round) being
6072 // inserted as undef can be dropped. This isn't safe for successive
6073 // rounds because they will permute elements within both vectors.
6074 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6075 EltStride == NumElems/2)
6078 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6087 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6088 // to create 256-bit vectors from two other 128-bit ones.
6089 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6091 MVT ResVT = Op.getSimpleValueType();
6093 assert((ResVT.is256BitVector() ||
6094 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6096 SDValue V1 = Op.getOperand(0);
6097 SDValue V2 = Op.getOperand(1);
6098 unsigned NumElems = ResVT.getVectorNumElements();
6099 if (ResVT.is256BitVector())
6100 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6102 if (Op.getNumOperands() == 4) {
6103 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6104 ResVT.getVectorNumElements()/2);
6105 SDValue V3 = Op.getOperand(2);
6106 SDValue V4 = Op.getOperand(3);
6107 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6108 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6110 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6113 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6114 const X86Subtarget *Subtarget,
6115 SelectionDAG & DAG) {
6117 MVT ResVT = Op.getSimpleValueType();
6118 unsigned NumOfOperands = Op.getNumOperands();
6120 assert(isPowerOf2_32(NumOfOperands) &&
6121 "Unexpected number of operands in CONCAT_VECTORS");
6123 if (NumOfOperands > 2) {
6124 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6125 ResVT.getVectorNumElements()/2);
6126 SmallVector<SDValue, 2> Ops;
6127 for (unsigned i = 0; i < NumOfOperands/2; i++)
6128 Ops.push_back(Op.getOperand(i));
6129 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6131 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6132 Ops.push_back(Op.getOperand(i));
6133 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6134 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6137 SDValue V1 = Op.getOperand(0);
6138 SDValue V2 = Op.getOperand(1);
6139 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6140 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6142 if (IsZeroV1 && IsZeroV2)
6143 return getZeroVector(ResVT, Subtarget, DAG, dl);
6145 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6146 SDValue Undef = DAG.getUNDEF(ResVT);
6147 unsigned NumElems = ResVT.getVectorNumElements();
6148 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6150 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6151 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6155 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6156 // Zero the upper bits of V1
6157 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6158 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6161 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6164 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6165 const X86Subtarget *Subtarget,
6166 SelectionDAG &DAG) {
6167 MVT VT = Op.getSimpleValueType();
6168 if (VT.getVectorElementType() == MVT::i1)
6169 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6171 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6172 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6173 Op.getNumOperands() == 4)));
6175 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6176 // from two other 128-bit ones.
6178 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6179 return LowerAVXCONCAT_VECTORS(Op, DAG);
6183 //===----------------------------------------------------------------------===//
6184 // Vector shuffle lowering
6186 // This is an experimental code path for lowering vector shuffles on x86. It is
6187 // designed to handle arbitrary vector shuffles and blends, gracefully
6188 // degrading performance as necessary. It works hard to recognize idiomatic
6189 // shuffles and lower them to optimal instruction patterns without leaving
6190 // a framework that allows reasonably efficient handling of all vector shuffle
6192 //===----------------------------------------------------------------------===//
6194 /// \brief Tiny helper function to identify a no-op mask.
6196 /// This is a somewhat boring predicate function. It checks whether the mask
6197 /// array input, which is assumed to be a single-input shuffle mask of the kind
6198 /// used by the X86 shuffle instructions (not a fully general
6199 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6200 /// in-place shuffle are 'no-op's.
6201 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6202 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6203 if (Mask[i] != -1 && Mask[i] != i)
6208 /// \brief Helper function to classify a mask as a single-input mask.
6210 /// This isn't a generic single-input test because in the vector shuffle
6211 /// lowering we canonicalize single inputs to be the first input operand. This
6212 /// means we can more quickly test for a single input by only checking whether
6213 /// an input from the second operand exists. We also assume that the size of
6214 /// mask corresponds to the size of the input vectors which isn't true in the
6215 /// fully general case.
6216 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6218 if (M >= (int)Mask.size())
6223 /// \brief Test whether there are elements crossing 128-bit lanes in this
6226 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6227 /// and we routinely test for these.
6228 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6229 int LaneSize = 128 / VT.getScalarSizeInBits();
6230 int Size = Mask.size();
6231 for (int i = 0; i < Size; ++i)
6232 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6237 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6239 /// This checks a shuffle mask to see if it is performing the same
6240 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6241 /// that it is also not lane-crossing. It may however involve a blend from the
6242 /// same lane of a second vector.
6244 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6245 /// non-trivial to compute in the face of undef lanes. The representation is
6246 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6247 /// entries from both V1 and V2 inputs to the wider mask.
6249 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6250 SmallVectorImpl<int> &RepeatedMask) {
6251 int LaneSize = 128 / VT.getScalarSizeInBits();
6252 RepeatedMask.resize(LaneSize, -1);
6253 int Size = Mask.size();
6254 for (int i = 0; i < Size; ++i) {
6257 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6258 // This entry crosses lanes, so there is no way to model this shuffle.
6261 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6262 if (RepeatedMask[i % LaneSize] == -1)
6263 // This is the first non-undef entry in this slot of a 128-bit lane.
6264 RepeatedMask[i % LaneSize] =
6265 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6266 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6267 // Found a mismatch with the repeated mask.
6273 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6276 /// This is a fast way to test a shuffle mask against a fixed pattern:
6278 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6280 /// It returns true if the mask is exactly as wide as the argument list, and
6281 /// each element of the mask is either -1 (signifying undef) or the value given
6282 /// in the argument.
6283 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6284 ArrayRef<int> ExpectedMask) {
6285 if (Mask.size() != ExpectedMask.size())
6288 int Size = Mask.size();
6290 // If the values are build vectors, we can look through them to find
6291 // equivalent inputs that make the shuffles equivalent.
6292 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6293 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6295 for (int i = 0; i < Size; ++i)
6296 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6297 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6298 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6299 if (!MaskBV || !ExpectedBV ||
6300 MaskBV->getOperand(Mask[i] % Size) !=
6301 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6308 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6310 /// This helper function produces an 8-bit shuffle immediate corresponding to
6311 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6312 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6315 /// NB: We rely heavily on "undef" masks preserving the input lane.
6316 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6317 SelectionDAG &DAG) {
6318 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6319 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6320 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6321 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6322 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6325 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6326 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6327 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6328 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6329 return DAG.getConstant(Imm, DL, MVT::i8);
6332 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6334 /// This is used as a fallback approach when first class blend instructions are
6335 /// unavailable. Currently it is only suitable for integer vectors, but could
6336 /// be generalized for floating point vectors if desirable.
6337 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6338 SDValue V2, ArrayRef<int> Mask,
6339 SelectionDAG &DAG) {
6340 assert(VT.isInteger() && "Only supports integer vector types!");
6341 MVT EltVT = VT.getScalarType();
6342 int NumEltBits = EltVT.getSizeInBits();
6343 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6344 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6346 SmallVector<SDValue, 16> MaskOps;
6347 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6348 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6349 return SDValue(); // Shuffled input!
6350 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6353 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6354 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6355 // We have to cast V2 around.
6356 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6357 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6358 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6359 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6360 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6361 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6364 /// \brief Try to emit a blend instruction for a shuffle.
6366 /// This doesn't do any checks for the availability of instructions for blending
6367 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6368 /// be matched in the backend with the type given. What it does check for is
6369 /// that the shuffle mask is in fact a blend.
6370 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6371 SDValue V2, ArrayRef<int> Mask,
6372 const X86Subtarget *Subtarget,
6373 SelectionDAG &DAG) {
6374 unsigned BlendMask = 0;
6375 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6376 if (Mask[i] >= Size) {
6377 if (Mask[i] != i + Size)
6378 return SDValue(); // Shuffled V2 input!
6379 BlendMask |= 1u << i;
6382 if (Mask[i] >= 0 && Mask[i] != i)
6383 return SDValue(); // Shuffled V1 input!
6385 switch (VT.SimpleTy) {
6390 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6391 DAG.getConstant(BlendMask, DL, MVT::i8));
6395 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6399 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6400 // that instruction.
6401 if (Subtarget->hasAVX2()) {
6402 // Scale the blend by the number of 32-bit dwords per element.
6403 int Scale = VT.getScalarSizeInBits() / 32;
6405 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6406 if (Mask[i] >= Size)
6407 for (int j = 0; j < Scale; ++j)
6408 BlendMask |= 1u << (i * Scale + j);
6410 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6411 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6412 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6413 return DAG.getNode(ISD::BITCAST, DL, VT,
6414 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6415 DAG.getConstant(BlendMask, DL, MVT::i8)));
6419 // For integer shuffles we need to expand the mask and cast the inputs to
6420 // v8i16s prior to blending.
6421 int Scale = 8 / VT.getVectorNumElements();
6423 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6424 if (Mask[i] >= Size)
6425 for (int j = 0; j < Scale; ++j)
6426 BlendMask |= 1u << (i * Scale + j);
6428 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6429 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6430 return DAG.getNode(ISD::BITCAST, DL, VT,
6431 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6432 DAG.getConstant(BlendMask, DL, MVT::i8)));
6436 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6437 SmallVector<int, 8> RepeatedMask;
6438 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6439 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6440 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6442 for (int i = 0; i < 8; ++i)
6443 if (RepeatedMask[i] >= 16)
6444 BlendMask |= 1u << i;
6445 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6446 DAG.getConstant(BlendMask, DL, MVT::i8));
6452 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6453 "256-bit byte-blends require AVX2 support!");
6455 // Scale the blend by the number of bytes per element.
6456 int Scale = VT.getScalarSizeInBits() / 8;
6458 // This form of blend is always done on bytes. Compute the byte vector
6460 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6462 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6463 // mix of LLVM's code generator and the x86 backend. We tell the code
6464 // generator that boolean values in the elements of an x86 vector register
6465 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6466 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6467 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6468 // of the element (the remaining are ignored) and 0 in that high bit would
6469 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6470 // the LLVM model for boolean values in vector elements gets the relevant
6471 // bit set, it is set backwards and over constrained relative to x86's
6473 SmallVector<SDValue, 32> VSELECTMask;
6474 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6475 for (int j = 0; j < Scale; ++j)
6476 VSELECTMask.push_back(
6477 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6478 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6481 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6482 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6484 ISD::BITCAST, DL, VT,
6485 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6486 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6491 llvm_unreachable("Not a supported integer vector type!");
6495 /// \brief Try to lower as a blend of elements from two inputs followed by
6496 /// a single-input permutation.
6498 /// This matches the pattern where we can blend elements from two inputs and
6499 /// then reduce the shuffle to a single-input permutation.
6500 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6503 SelectionDAG &DAG) {
6504 // We build up the blend mask while checking whether a blend is a viable way
6505 // to reduce the shuffle.
6506 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6507 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6509 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6513 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6515 if (BlendMask[Mask[i] % Size] == -1)
6516 BlendMask[Mask[i] % Size] = Mask[i];
6517 else if (BlendMask[Mask[i] % Size] != Mask[i])
6518 return SDValue(); // Can't blend in the needed input!
6520 PermuteMask[i] = Mask[i] % Size;
6523 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6524 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6527 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6528 /// blends and permutes.
6530 /// This matches the extremely common pattern for handling combined
6531 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6532 /// operations. It will try to pick the best arrangement of shuffles and
6534 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6538 SelectionDAG &DAG) {
6539 // Shuffle the input elements into the desired positions in V1 and V2 and
6540 // blend them together.
6541 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6542 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6543 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6544 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6545 if (Mask[i] >= 0 && Mask[i] < Size) {
6546 V1Mask[i] = Mask[i];
6548 } else if (Mask[i] >= Size) {
6549 V2Mask[i] = Mask[i] - Size;
6550 BlendMask[i] = i + Size;
6553 // Try to lower with the simpler initial blend strategy unless one of the
6554 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6555 // shuffle may be able to fold with a load or other benefit. However, when
6556 // we'll have to do 2x as many shuffles in order to achieve this, blending
6557 // first is a better strategy.
6558 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6559 if (SDValue BlendPerm =
6560 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6563 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6564 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6565 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6568 /// \brief Try to lower a vector shuffle as a byte rotation.
6570 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6571 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6572 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6573 /// try to generically lower a vector shuffle through such an pattern. It
6574 /// does not check for the profitability of lowering either as PALIGNR or
6575 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6576 /// This matches shuffle vectors that look like:
6578 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6580 /// Essentially it concatenates V1 and V2, shifts right by some number of
6581 /// elements, and takes the low elements as the result. Note that while this is
6582 /// specified as a *right shift* because x86 is little-endian, it is a *left
6583 /// rotate* of the vector lanes.
6584 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6587 const X86Subtarget *Subtarget,
6588 SelectionDAG &DAG) {
6589 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6591 int NumElts = Mask.size();
6592 int NumLanes = VT.getSizeInBits() / 128;
6593 int NumLaneElts = NumElts / NumLanes;
6595 // We need to detect various ways of spelling a rotation:
6596 // [11, 12, 13, 14, 15, 0, 1, 2]
6597 // [-1, 12, 13, 14, -1, -1, 1, -1]
6598 // [-1, -1, -1, -1, -1, -1, 1, 2]
6599 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6600 // [-1, 4, 5, 6, -1, -1, 9, -1]
6601 // [-1, 4, 5, 6, -1, -1, -1, -1]
6604 for (int l = 0; l < NumElts; l += NumLaneElts) {
6605 for (int i = 0; i < NumLaneElts; ++i) {
6606 if (Mask[l + i] == -1)
6608 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6610 // Get the mod-Size index and lane correct it.
6611 int LaneIdx = (Mask[l + i] % NumElts) - l;
6612 // Make sure it was in this lane.
6613 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6616 // Determine where a rotated vector would have started.
6617 int StartIdx = i - LaneIdx;
6619 // The identity rotation isn't interesting, stop.
6622 // If we found the tail of a vector the rotation must be the missing
6623 // front. If we found the head of a vector, it must be how much of the
6625 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6628 Rotation = CandidateRotation;
6629 else if (Rotation != CandidateRotation)
6630 // The rotations don't match, so we can't match this mask.
6633 // Compute which value this mask is pointing at.
6634 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6636 // Compute which of the two target values this index should be assigned
6637 // to. This reflects whether the high elements are remaining or the low
6638 // elements are remaining.
6639 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6641 // Either set up this value if we've not encountered it before, or check
6642 // that it remains consistent.
6645 else if (TargetV != MaskV)
6646 // This may be a rotation, but it pulls from the inputs in some
6647 // unsupported interleaving.
6652 // Check that we successfully analyzed the mask, and normalize the results.
6653 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6654 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6660 // The actual rotate instruction rotates bytes, so we need to scale the
6661 // rotation based on how many bytes are in the vector lane.
6662 int Scale = 16 / NumLaneElts;
6664 // SSSE3 targets can use the palignr instruction.
6665 if (Subtarget->hasSSSE3()) {
6666 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6667 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6668 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6669 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6671 return DAG.getNode(ISD::BITCAST, DL, VT,
6672 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6673 DAG.getConstant(Rotation * Scale, DL,
6677 assert(VT.getSizeInBits() == 128 &&
6678 "Rotate-based lowering only supports 128-bit lowering!");
6679 assert(Mask.size() <= 16 &&
6680 "Can shuffle at most 16 bytes in a 128-bit vector!");
6682 // Default SSE2 implementation
6683 int LoByteShift = 16 - Rotation * Scale;
6684 int HiByteShift = Rotation * Scale;
6686 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6687 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6688 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6690 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6691 DAG.getConstant(LoByteShift, DL, MVT::i8));
6692 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6693 DAG.getConstant(HiByteShift, DL, MVT::i8));
6694 return DAG.getNode(ISD::BITCAST, DL, VT,
6695 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6698 /// \brief Compute whether each element of a shuffle is zeroable.
6700 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6701 /// Either it is an undef element in the shuffle mask, the element of the input
6702 /// referenced is undef, or the element of the input referenced is known to be
6703 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6704 /// as many lanes with this technique as possible to simplify the remaining
6706 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6707 SDValue V1, SDValue V2) {
6708 SmallBitVector Zeroable(Mask.size(), false);
6710 while (V1.getOpcode() == ISD::BITCAST)
6711 V1 = V1->getOperand(0);
6712 while (V2.getOpcode() == ISD::BITCAST)
6713 V2 = V2->getOperand(0);
6715 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6716 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6718 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6720 // Handle the easy cases.
6721 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6726 // If this is an index into a build_vector node (which has the same number
6727 // of elements), dig out the input value and use it.
6728 SDValue V = M < Size ? V1 : V2;
6729 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6732 SDValue Input = V.getOperand(M % Size);
6733 // The UNDEF opcode check really should be dead code here, but not quite
6734 // worth asserting on (it isn't invalid, just unexpected).
6735 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6742 /// \brief Try to emit a bitmask instruction for a shuffle.
6744 /// This handles cases where we can model a blend exactly as a bitmask due to
6745 /// one of the inputs being zeroable.
6746 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6747 SDValue V2, ArrayRef<int> Mask,
6748 SelectionDAG &DAG) {
6749 MVT EltVT = VT.getScalarType();
6750 int NumEltBits = EltVT.getSizeInBits();
6751 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6752 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6753 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6755 if (EltVT.isFloatingPoint()) {
6756 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6757 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6759 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6760 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6762 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6765 if (Mask[i] % Size != i)
6766 return SDValue(); // Not a blend.
6768 V = Mask[i] < Size ? V1 : V2;
6769 else if (V != (Mask[i] < Size ? V1 : V2))
6770 return SDValue(); // Can only let one input through the mask.
6772 VMaskOps[i] = AllOnes;
6775 return SDValue(); // No non-zeroable elements!
6777 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6778 V = DAG.getNode(VT.isFloatingPoint()
6779 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6784 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6786 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6787 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6788 /// matches elements from one of the input vectors shuffled to the left or
6789 /// right with zeroable elements 'shifted in'. It handles both the strictly
6790 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6793 /// PSHL : (little-endian) left bit shift.
6794 /// [ zz, 0, zz, 2 ]
6795 /// [ -1, 4, zz, -1 ]
6796 /// PSRL : (little-endian) right bit shift.
6798 /// [ -1, -1, 7, zz]
6799 /// PSLLDQ : (little-endian) left byte shift
6800 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6801 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6802 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6803 /// PSRLDQ : (little-endian) right byte shift
6804 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6805 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6806 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6807 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6808 SDValue V2, ArrayRef<int> Mask,
6809 SelectionDAG &DAG) {
6810 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6812 int Size = Mask.size();
6813 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6815 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6816 for (int i = 0; i < Size; i += Scale)
6817 for (int j = 0; j < Shift; ++j)
6818 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6824 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6825 for (int i = 0; i != Size; i += Scale) {
6826 unsigned Pos = Left ? i + Shift : i;
6827 unsigned Low = Left ? i : i + Shift;
6828 unsigned Len = Scale - Shift;
6829 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6830 Low + (V == V1 ? 0 : Size)))
6834 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6835 bool ByteShift = ShiftEltBits > 64;
6836 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6837 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6838 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6840 // Normalize the scale for byte shifts to still produce an i64 element
6842 Scale = ByteShift ? Scale / 2 : Scale;
6844 // We need to round trip through the appropriate type for the shift.
6845 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6846 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6847 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6848 "Illegal integer vector type");
6849 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6851 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6852 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6853 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6856 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6857 // keep doubling the size of the integer elements up to that. We can
6858 // then shift the elements of the integer vector by whole multiples of
6859 // their width within the elements of the larger integer vector. Test each
6860 // multiple to see if we can find a match with the moved element indices
6861 // and that the shifted in elements are all zeroable.
6862 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6863 for (int Shift = 1; Shift != Scale; ++Shift)
6864 for (bool Left : {true, false})
6865 if (CheckZeros(Shift, Scale, Left))
6866 for (SDValue V : {V1, V2})
6867 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6874 /// \brief Lower a vector shuffle as a zero or any extension.
6876 /// Given a specific number of elements, element bit width, and extension
6877 /// stride, produce either a zero or any extension based on the available
6878 /// features of the subtarget.
6879 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6880 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6881 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6882 assert(Scale > 1 && "Need a scale to extend.");
6883 int NumElements = VT.getVectorNumElements();
6884 int EltBits = VT.getScalarSizeInBits();
6885 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6886 "Only 8, 16, and 32 bit elements can be extended.");
6887 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6889 // Found a valid zext mask! Try various lowering strategies based on the
6890 // input type and available ISA extensions.
6891 if (Subtarget->hasSSE41()) {
6892 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6893 NumElements / Scale);
6894 return DAG.getNode(ISD::BITCAST, DL, VT,
6895 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6898 // For any extends we can cheat for larger element sizes and use shuffle
6899 // instructions that can fold with a load and/or copy.
6900 if (AnyExt && EltBits == 32) {
6901 int PSHUFDMask[4] = {0, -1, 1, -1};
6903 ISD::BITCAST, DL, VT,
6904 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6905 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6906 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6908 if (AnyExt && EltBits == 16 && Scale > 2) {
6909 int PSHUFDMask[4] = {0, -1, 0, -1};
6910 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6911 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6912 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6913 int PSHUFHWMask[4] = {1, -1, -1, -1};
6915 ISD::BITCAST, DL, VT,
6916 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6917 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6918 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6921 // If this would require more than 2 unpack instructions to expand, use
6922 // pshufb when available. We can only use more than 2 unpack instructions
6923 // when zero extending i8 elements which also makes it easier to use pshufb.
6924 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6925 assert(NumElements == 16 && "Unexpected byte vector width!");
6926 SDValue PSHUFBMask[16];
6927 for (int i = 0; i < 16; ++i)
6929 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6930 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6931 return DAG.getNode(ISD::BITCAST, DL, VT,
6932 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6933 DAG.getNode(ISD::BUILD_VECTOR, DL,
6934 MVT::v16i8, PSHUFBMask)));
6937 // Otherwise emit a sequence of unpacks.
6939 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6940 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6941 : getZeroVector(InputVT, Subtarget, DAG, DL);
6942 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6943 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6947 } while (Scale > 1);
6948 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6951 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6953 /// This routine will try to do everything in its power to cleverly lower
6954 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6955 /// check for the profitability of this lowering, it tries to aggressively
6956 /// match this pattern. It will use all of the micro-architectural details it
6957 /// can to emit an efficient lowering. It handles both blends with all-zero
6958 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6959 /// masking out later).
6961 /// The reason we have dedicated lowering for zext-style shuffles is that they
6962 /// are both incredibly common and often quite performance sensitive.
6963 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6964 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6965 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6966 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6968 int Bits = VT.getSizeInBits();
6969 int NumElements = VT.getVectorNumElements();
6970 assert(VT.getScalarSizeInBits() <= 32 &&
6971 "Exceeds 32-bit integer zero extension limit");
6972 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6974 // Define a helper function to check a particular ext-scale and lower to it if
6976 auto Lower = [&](int Scale) -> SDValue {
6979 for (int i = 0; i < NumElements; ++i) {
6981 continue; // Valid anywhere but doesn't tell us anything.
6982 if (i % Scale != 0) {
6983 // Each of the extended elements need to be zeroable.
6987 // We no longer are in the anyext case.
6992 // Each of the base elements needs to be consecutive indices into the
6993 // same input vector.
6994 SDValue V = Mask[i] < NumElements ? V1 : V2;
6997 else if (InputV != V)
6998 return SDValue(); // Flip-flopping inputs.
7000 if (Mask[i] % NumElements != i / Scale)
7001 return SDValue(); // Non-consecutive strided elements.
7004 // If we fail to find an input, we have a zero-shuffle which should always
7005 // have already been handled.
7006 // FIXME: Maybe handle this here in case during blending we end up with one?
7010 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7011 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
7014 // The widest scale possible for extending is to a 64-bit integer.
7015 assert(Bits % 64 == 0 &&
7016 "The number of bits in a vector must be divisible by 64 on x86!");
7017 int NumExtElements = Bits / 64;
7019 // Each iteration, try extending the elements half as much, but into twice as
7021 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7022 assert(NumElements % NumExtElements == 0 &&
7023 "The input vector size must be divisible by the extended size.");
7024 if (SDValue V = Lower(NumElements / NumExtElements))
7028 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7032 // Returns one of the source operands if the shuffle can be reduced to a
7033 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7034 auto CanZExtLowHalf = [&]() {
7035 for (int i = NumElements / 2; i != NumElements; ++i)
7038 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7040 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7045 if (SDValue V = CanZExtLowHalf()) {
7046 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
7047 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7048 return DAG.getNode(ISD::BITCAST, DL, VT, V);
7051 // No viable ext lowering found.
7055 /// \brief Try to get a scalar value for a specific element of a vector.
7057 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7058 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7059 SelectionDAG &DAG) {
7060 MVT VT = V.getSimpleValueType();
7061 MVT EltVT = VT.getVectorElementType();
7062 while (V.getOpcode() == ISD::BITCAST)
7063 V = V.getOperand(0);
7064 // If the bitcasts shift the element size, we can't extract an equivalent
7066 MVT NewVT = V.getSimpleValueType();
7067 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7070 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7071 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7072 // Ensure the scalar operand is the same size as the destination.
7073 // FIXME: Add support for scalar truncation where possible.
7074 SDValue S = V.getOperand(Idx);
7075 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7076 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7082 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7084 /// This is particularly important because the set of instructions varies
7085 /// significantly based on whether the operand is a load or not.
7086 static bool isShuffleFoldableLoad(SDValue V) {
7087 while (V.getOpcode() == ISD::BITCAST)
7088 V = V.getOperand(0);
7090 return ISD::isNON_EXTLoad(V.getNode());
7093 /// \brief Try to lower insertion of a single element into a zero vector.
7095 /// This is a common pattern that we have especially efficient patterns to lower
7096 /// across all subtarget feature sets.
7097 static SDValue lowerVectorShuffleAsElementInsertion(
7098 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7099 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7100 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7102 MVT EltVT = VT.getVectorElementType();
7104 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7105 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7107 bool IsV1Zeroable = true;
7108 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7109 if (i != V2Index && !Zeroable[i]) {
7110 IsV1Zeroable = false;
7114 // Check for a single input from a SCALAR_TO_VECTOR node.
7115 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7116 // all the smarts here sunk into that routine. However, the current
7117 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7118 // vector shuffle lowering is dead.
7119 if (SDValue V2S = getScalarValueForVectorElement(
7120 V2, Mask[V2Index] - Mask.size(), DAG)) {
7121 // We need to zext the scalar if it is smaller than an i32.
7122 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7123 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7124 // Using zext to expand a narrow element won't work for non-zero
7129 // Zero-extend directly to i32.
7131 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7133 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7134 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7135 EltVT == MVT::i16) {
7136 // Either not inserting from the low element of the input or the input
7137 // element size is too small to use VZEXT_MOVL to clear the high bits.
7141 if (!IsV1Zeroable) {
7142 // If V1 can't be treated as a zero vector we have fewer options to lower
7143 // this. We can't support integer vectors or non-zero targets cheaply, and
7144 // the V1 elements can't be permuted in any way.
7145 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7146 if (!VT.isFloatingPoint() || V2Index != 0)
7148 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7149 V1Mask[V2Index] = -1;
7150 if (!isNoopShuffleMask(V1Mask))
7152 // This is essentially a special case blend operation, but if we have
7153 // general purpose blend operations, they are always faster. Bail and let
7154 // the rest of the lowering handle these as blends.
7155 if (Subtarget->hasSSE41())
7158 // Otherwise, use MOVSD or MOVSS.
7159 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7160 "Only two types of floating point element types to handle!");
7161 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7165 // This lowering only works for the low element with floating point vectors.
7166 if (VT.isFloatingPoint() && V2Index != 0)
7169 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7171 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7174 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7175 // the desired position. Otherwise it is more efficient to do a vector
7176 // shift left. We know that we can do a vector shift left because all
7177 // the inputs are zero.
7178 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7179 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7180 V2Shuffle[V2Index] = 0;
7181 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7183 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7185 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7187 V2Index * EltVT.getSizeInBits()/8, DL,
7188 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7189 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7195 /// \brief Try to lower broadcast of a single element.
7197 /// For convenience, this code also bundles all of the subtarget feature set
7198 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7199 /// a convenient way to factor it out.
7200 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7202 const X86Subtarget *Subtarget,
7203 SelectionDAG &DAG) {
7204 if (!Subtarget->hasAVX())
7206 if (VT.isInteger() && !Subtarget->hasAVX2())
7209 // Check that the mask is a broadcast.
7210 int BroadcastIdx = -1;
7212 if (M >= 0 && BroadcastIdx == -1)
7214 else if (M >= 0 && M != BroadcastIdx)
7217 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7218 "a sorted mask where the broadcast "
7221 // Go up the chain of (vector) values to find a scalar load that we can
7222 // combine with the broadcast.
7224 switch (V.getOpcode()) {
7225 case ISD::CONCAT_VECTORS: {
7226 int OperandSize = Mask.size() / V.getNumOperands();
7227 V = V.getOperand(BroadcastIdx / OperandSize);
7228 BroadcastIdx %= OperandSize;
7232 case ISD::INSERT_SUBVECTOR: {
7233 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7234 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7238 int BeginIdx = (int)ConstantIdx->getZExtValue();
7240 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7241 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7242 BroadcastIdx -= BeginIdx;
7253 // Check if this is a broadcast of a scalar. We special case lowering
7254 // for scalars so that we can more effectively fold with loads.
7255 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7256 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7257 V = V.getOperand(BroadcastIdx);
7259 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7260 // Only AVX2 has register broadcasts.
7261 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7263 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7264 // We can't broadcast from a vector register without AVX2, and we can only
7265 // broadcast from the zero-element of a vector register.
7269 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7272 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7273 // INSERTPS when the V1 elements are already in the correct locations
7274 // because otherwise we can just always use two SHUFPS instructions which
7275 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7276 // perform INSERTPS if a single V1 element is out of place and all V2
7277 // elements are zeroable.
7278 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7280 SelectionDAG &DAG) {
7281 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7282 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7283 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7284 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7286 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7289 int V1DstIndex = -1;
7290 int V2DstIndex = -1;
7291 bool V1UsedInPlace = false;
7293 for (int i = 0; i < 4; ++i) {
7294 // Synthesize a zero mask from the zeroable elements (includes undefs).
7300 // Flag if we use any V1 inputs in place.
7302 V1UsedInPlace = true;
7306 // We can only insert a single non-zeroable element.
7307 if (V1DstIndex != -1 || V2DstIndex != -1)
7311 // V1 input out of place for insertion.
7314 // V2 input for insertion.
7319 // Don't bother if we have no (non-zeroable) element for insertion.
7320 if (V1DstIndex == -1 && V2DstIndex == -1)
7323 // Determine element insertion src/dst indices. The src index is from the
7324 // start of the inserted vector, not the start of the concatenated vector.
7325 unsigned V2SrcIndex = 0;
7326 if (V1DstIndex != -1) {
7327 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7328 // and don't use the original V2 at all.
7329 V2SrcIndex = Mask[V1DstIndex];
7330 V2DstIndex = V1DstIndex;
7333 V2SrcIndex = Mask[V2DstIndex] - 4;
7336 // If no V1 inputs are used in place, then the result is created only from
7337 // the zero mask and the V2 insertion - so remove V1 dependency.
7339 V1 = DAG.getUNDEF(MVT::v4f32);
7341 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7342 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7344 // Insert the V2 element into the desired position.
7346 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7347 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7350 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7351 /// UNPCK instruction.
7353 /// This specifically targets cases where we end up with alternating between
7354 /// the two inputs, and so can permute them into something that feeds a single
7355 /// UNPCK instruction. Note that this routine only targets integer vectors
7356 /// because for floating point vectors we have a generalized SHUFPS lowering
7357 /// strategy that handles everything that doesn't *exactly* match an unpack,
7358 /// making this clever lowering unnecessary.
7359 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7360 SDValue V2, ArrayRef<int> Mask,
7361 SelectionDAG &DAG) {
7362 assert(!VT.isFloatingPoint() &&
7363 "This routine only supports integer vectors.");
7364 assert(!isSingleInputShuffleMask(Mask) &&
7365 "This routine should only be used when blending two inputs.");
7366 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7368 int Size = Mask.size();
7370 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7371 return M >= 0 && M % Size < Size / 2;
7373 int NumHiInputs = std::count_if(
7374 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7376 bool UnpackLo = NumLoInputs >= NumHiInputs;
7378 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7379 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7380 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7382 for (int i = 0; i < Size; ++i) {
7386 // Each element of the unpack contains Scale elements from this mask.
7387 int UnpackIdx = i / Scale;
7389 // We only handle the case where V1 feeds the first slots of the unpack.
7390 // We rely on canonicalization to ensure this is the case.
7391 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7394 // Setup the mask for this input. The indexing is tricky as we have to
7395 // handle the unpack stride.
7396 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7397 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7401 // If we will have to shuffle both inputs to use the unpack, check whether
7402 // we can just unpack first and shuffle the result. If so, skip this unpack.
7403 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7404 !isNoopShuffleMask(V2Mask))
7407 // Shuffle the inputs into place.
7408 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7409 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7411 // Cast the inputs to the type we will use to unpack them.
7412 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7413 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7415 // Unpack the inputs and cast the result back to the desired type.
7416 return DAG.getNode(ISD::BITCAST, DL, VT,
7417 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7418 DL, UnpackVT, V1, V2));
7421 // We try each unpack from the largest to the smallest to try and find one
7422 // that fits this mask.
7423 int OrigNumElements = VT.getVectorNumElements();
7424 int OrigScalarSize = VT.getScalarSizeInBits();
7425 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7426 int Scale = ScalarSize / OrigScalarSize;
7427 int NumElements = OrigNumElements / Scale;
7428 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7429 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7433 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7435 if (NumLoInputs == 0 || NumHiInputs == 0) {
7436 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7437 "We have to have *some* inputs!");
7438 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7440 // FIXME: We could consider the total complexity of the permute of each
7441 // possible unpacking. Or at the least we should consider how many
7442 // half-crossings are created.
7443 // FIXME: We could consider commuting the unpacks.
7445 SmallVector<int, 32> PermMask;
7446 PermMask.assign(Size, -1);
7447 for (int i = 0; i < Size; ++i) {
7451 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7454 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7456 return DAG.getVectorShuffle(
7457 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7459 DAG.getUNDEF(VT), PermMask);
7465 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7467 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7468 /// support for floating point shuffles but not integer shuffles. These
7469 /// instructions will incur a domain crossing penalty on some chips though so
7470 /// it is better to avoid lowering through this for integer vectors where
7472 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7473 const X86Subtarget *Subtarget,
7474 SelectionDAG &DAG) {
7476 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7477 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7478 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7479 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7480 ArrayRef<int> Mask = SVOp->getMask();
7481 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7483 if (isSingleInputShuffleMask(Mask)) {
7484 // Use low duplicate instructions for masks that match their pattern.
7485 if (Subtarget->hasSSE3())
7486 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7487 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7489 // Straight shuffle of a single input vector. Simulate this by using the
7490 // single input as both of the "inputs" to this instruction..
7491 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7493 if (Subtarget->hasAVX()) {
7494 // If we have AVX, we can use VPERMILPS which will allow folding a load
7495 // into the shuffle.
7496 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7497 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7500 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7501 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7503 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7504 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7506 // If we have a single input, insert that into V1 if we can do so cheaply.
7507 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7508 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7509 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7511 // Try inverting the insertion since for v2 masks it is easy to do and we
7512 // can't reliably sort the mask one way or the other.
7513 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7514 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7515 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7516 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7520 // Try to use one of the special instruction patterns to handle two common
7521 // blend patterns if a zero-blend above didn't work.
7522 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7523 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7524 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7525 // We can either use a special instruction to load over the low double or
7526 // to move just the low double.
7528 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7530 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7532 if (Subtarget->hasSSE41())
7533 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7537 // Use dedicated unpack instructions for masks that match their pattern.
7538 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7539 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7540 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7541 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7543 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7544 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7545 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7548 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7550 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7551 /// the integer unit to minimize domain crossing penalties. However, for blends
7552 /// it falls back to the floating point shuffle operation with appropriate bit
7554 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7555 const X86Subtarget *Subtarget,
7556 SelectionDAG &DAG) {
7558 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7559 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7560 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7561 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7562 ArrayRef<int> Mask = SVOp->getMask();
7563 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7565 if (isSingleInputShuffleMask(Mask)) {
7566 // Check for being able to broadcast a single element.
7567 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7568 Mask, Subtarget, DAG))
7571 // Straight shuffle of a single input vector. For everything from SSE2
7572 // onward this has a single fast instruction with no scary immediates.
7573 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7574 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7575 int WidenedMask[4] = {
7576 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7577 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7579 ISD::BITCAST, DL, MVT::v2i64,
7580 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7581 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7583 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7584 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7585 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7586 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7588 // If we have a blend of two PACKUS operations an the blend aligns with the
7589 // low and half halves, we can just merge the PACKUS operations. This is
7590 // particularly important as it lets us merge shuffles that this routine itself
7592 auto GetPackNode = [](SDValue V) {
7593 while (V.getOpcode() == ISD::BITCAST)
7594 V = V.getOperand(0);
7596 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7598 if (SDValue V1Pack = GetPackNode(V1))
7599 if (SDValue V2Pack = GetPackNode(V2))
7600 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7601 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7602 Mask[0] == 0 ? V1Pack.getOperand(0)
7603 : V1Pack.getOperand(1),
7604 Mask[1] == 2 ? V2Pack.getOperand(0)
7605 : V2Pack.getOperand(1)));
7607 // Try to use shift instructions.
7609 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7612 // When loading a scalar and then shuffling it into a vector we can often do
7613 // the insertion cheaply.
7614 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7615 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7617 // Try inverting the insertion since for v2 masks it is easy to do and we
7618 // can't reliably sort the mask one way or the other.
7619 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7620 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7621 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7624 // We have different paths for blend lowering, but they all must use the
7625 // *exact* same predicate.
7626 bool IsBlendSupported = Subtarget->hasSSE41();
7627 if (IsBlendSupported)
7628 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7632 // Use dedicated unpack instructions for masks that match their pattern.
7633 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7634 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7635 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7636 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7638 // Try to use byte rotation instructions.
7639 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7640 if (Subtarget->hasSSSE3())
7641 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7642 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7645 // If we have direct support for blends, we should lower by decomposing into
7646 // a permute. That will be faster than the domain cross.
7647 if (IsBlendSupported)
7648 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7651 // We implement this with SHUFPD which is pretty lame because it will likely
7652 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7653 // However, all the alternatives are still more cycles and newer chips don't
7654 // have this problem. It would be really nice if x86 had better shuffles here.
7655 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7656 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7657 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7658 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7661 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7663 /// This is used to disable more specialized lowerings when the shufps lowering
7664 /// will happen to be efficient.
7665 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7666 // This routine only handles 128-bit shufps.
7667 assert(Mask.size() == 4 && "Unsupported mask size!");
7669 // To lower with a single SHUFPS we need to have the low half and high half
7670 // each requiring a single input.
7671 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7673 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7679 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7681 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7682 /// It makes no assumptions about whether this is the *best* lowering, it simply
7684 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7685 ArrayRef<int> Mask, SDValue V1,
7686 SDValue V2, SelectionDAG &DAG) {
7687 SDValue LowV = V1, HighV = V2;
7688 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7691 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7693 if (NumV2Elements == 1) {
7695 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7698 // Compute the index adjacent to V2Index and in the same half by toggling
7700 int V2AdjIndex = V2Index ^ 1;
7702 if (Mask[V2AdjIndex] == -1) {
7703 // Handles all the cases where we have a single V2 element and an undef.
7704 // This will only ever happen in the high lanes because we commute the
7705 // vector otherwise.
7707 std::swap(LowV, HighV);
7708 NewMask[V2Index] -= 4;
7710 // Handle the case where the V2 element ends up adjacent to a V1 element.
7711 // To make this work, blend them together as the first step.
7712 int V1Index = V2AdjIndex;
7713 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7714 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7715 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7717 // Now proceed to reconstruct the final blend as we have the necessary
7718 // high or low half formed.
7725 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7726 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7728 } else if (NumV2Elements == 2) {
7729 if (Mask[0] < 4 && Mask[1] < 4) {
7730 // Handle the easy case where we have V1 in the low lanes and V2 in the
7734 } else if (Mask[2] < 4 && Mask[3] < 4) {
7735 // We also handle the reversed case because this utility may get called
7736 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7737 // arrange things in the right direction.
7743 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7744 // trying to place elements directly, just blend them and set up the final
7745 // shuffle to place them.
7747 // The first two blend mask elements are for V1, the second two are for
7749 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7750 Mask[2] < 4 ? Mask[2] : Mask[3],
7751 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7752 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7753 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7754 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7756 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7759 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7760 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7761 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7762 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7765 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7766 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7769 /// \brief Lower 4-lane 32-bit floating point shuffles.
7771 /// Uses instructions exclusively from the floating point unit to minimize
7772 /// domain crossing penalties, as these are sufficient to implement all v4f32
7774 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7775 const X86Subtarget *Subtarget,
7776 SelectionDAG &DAG) {
7778 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7779 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7780 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7781 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7782 ArrayRef<int> Mask = SVOp->getMask();
7783 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7786 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7788 if (NumV2Elements == 0) {
7789 // Check for being able to broadcast a single element.
7790 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7791 Mask, Subtarget, DAG))
7794 // Use even/odd duplicate instructions for masks that match their pattern.
7795 if (Subtarget->hasSSE3()) {
7796 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7797 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7798 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7799 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7802 if (Subtarget->hasAVX()) {
7803 // If we have AVX, we can use VPERMILPS which will allow folding a load
7804 // into the shuffle.
7805 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7806 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7809 // Otherwise, use a straight shuffle of a single input vector. We pass the
7810 // input vector to both operands to simulate this with a SHUFPS.
7811 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7812 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7815 // There are special ways we can lower some single-element blends. However, we
7816 // have custom ways we can lower more complex single-element blends below that
7817 // we defer to if both this and BLENDPS fail to match, so restrict this to
7818 // when the V2 input is targeting element 0 of the mask -- that is the fast
7820 if (NumV2Elements == 1 && Mask[0] >= 4)
7821 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7822 Mask, Subtarget, DAG))
7825 if (Subtarget->hasSSE41()) {
7826 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7830 // Use INSERTPS if we can complete the shuffle efficiently.
7831 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7834 if (!isSingleSHUFPSMask(Mask))
7835 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7836 DL, MVT::v4f32, V1, V2, Mask, DAG))
7840 // Use dedicated unpack instructions for masks that match their pattern.
7841 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7842 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7843 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7844 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7845 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7846 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7847 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7848 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7850 // Otherwise fall back to a SHUFPS lowering strategy.
7851 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7854 /// \brief Lower 4-lane i32 vector shuffles.
7856 /// We try to handle these with integer-domain shuffles where we can, but for
7857 /// blends we use the floating point domain blend instructions.
7858 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7859 const X86Subtarget *Subtarget,
7860 SelectionDAG &DAG) {
7862 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7863 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7864 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7865 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7866 ArrayRef<int> Mask = SVOp->getMask();
7867 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7869 // Whenever we can lower this as a zext, that instruction is strictly faster
7870 // than any alternative. It also allows us to fold memory operands into the
7871 // shuffle in many cases.
7872 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7873 Mask, Subtarget, DAG))
7877 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7879 if (NumV2Elements == 0) {
7880 // Check for being able to broadcast a single element.
7881 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7882 Mask, Subtarget, DAG))
7885 // Straight shuffle of a single input vector. For everything from SSE2
7886 // onward this has a single fast instruction with no scary immediates.
7887 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7888 // but we aren't actually going to use the UNPCK instruction because doing
7889 // so prevents folding a load into this instruction or making a copy.
7890 const int UnpackLoMask[] = {0, 0, 1, 1};
7891 const int UnpackHiMask[] = {2, 2, 3, 3};
7892 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7893 Mask = UnpackLoMask;
7894 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7895 Mask = UnpackHiMask;
7897 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7898 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7901 // Try to use shift instructions.
7903 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7906 // There are special ways we can lower some single-element blends.
7907 if (NumV2Elements == 1)
7908 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7909 Mask, Subtarget, DAG))
7912 // We have different paths for blend lowering, but they all must use the
7913 // *exact* same predicate.
7914 bool IsBlendSupported = Subtarget->hasSSE41();
7915 if (IsBlendSupported)
7916 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7920 if (SDValue Masked =
7921 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7924 // Use dedicated unpack instructions for masks that match their pattern.
7925 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7926 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7927 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7928 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7929 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7930 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7931 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7932 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7934 // Try to use byte rotation instructions.
7935 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7936 if (Subtarget->hasSSSE3())
7937 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7938 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7941 // If we have direct support for blends, we should lower by decomposing into
7942 // a permute. That will be faster than the domain cross.
7943 if (IsBlendSupported)
7944 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7947 // Try to lower by permuting the inputs into an unpack instruction.
7948 if (SDValue Unpack =
7949 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7952 // We implement this with SHUFPS because it can blend from two vectors.
7953 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7954 // up the inputs, bypassing domain shift penalties that we would encur if we
7955 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7957 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7958 DAG.getVectorShuffle(
7960 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7961 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7964 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7965 /// shuffle lowering, and the most complex part.
7967 /// The lowering strategy is to try to form pairs of input lanes which are
7968 /// targeted at the same half of the final vector, and then use a dword shuffle
7969 /// to place them onto the right half, and finally unpack the paired lanes into
7970 /// their final position.
7972 /// The exact breakdown of how to form these dword pairs and align them on the
7973 /// correct sides is really tricky. See the comments within the function for
7974 /// more of the details.
7976 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7977 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7978 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7979 /// vector, form the analogous 128-bit 8-element Mask.
7980 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7981 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7982 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7983 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7984 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7986 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7987 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7988 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7990 SmallVector<int, 4> LoInputs;
7991 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7992 [](int M) { return M >= 0; });
7993 std::sort(LoInputs.begin(), LoInputs.end());
7994 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7995 SmallVector<int, 4> HiInputs;
7996 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7997 [](int M) { return M >= 0; });
7998 std::sort(HiInputs.begin(), HiInputs.end());
7999 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8001 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8002 int NumHToL = LoInputs.size() - NumLToL;
8004 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8005 int NumHToH = HiInputs.size() - NumLToH;
8006 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8007 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8008 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8009 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8011 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8012 // such inputs we can swap two of the dwords across the half mark and end up
8013 // with <=2 inputs to each half in each half. Once there, we can fall through
8014 // to the generic code below. For example:
8016 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8017 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8019 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8020 // and an existing 2-into-2 on the other half. In this case we may have to
8021 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8022 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8023 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8024 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8025 // half than the one we target for fixing) will be fixed when we re-enter this
8026 // path. We will also combine away any sequence of PSHUFD instructions that
8027 // result into a single instruction. Here is an example of the tricky case:
8029 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8030 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8032 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8034 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8035 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8037 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8038 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8040 // The result is fine to be handled by the generic logic.
8041 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8042 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8043 int AOffset, int BOffset) {
8044 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8045 "Must call this with A having 3 or 1 inputs from the A half.");
8046 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8047 "Must call this with B having 1 or 3 inputs from the B half.");
8048 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8049 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8051 // Compute the index of dword with only one word among the three inputs in
8052 // a half by taking the sum of the half with three inputs and subtracting
8053 // the sum of the actual three inputs. The difference is the remaining
8056 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8057 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8058 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8059 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8060 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8061 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8062 int TripleNonInputIdx =
8063 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8064 TripleDWord = TripleNonInputIdx / 2;
8066 // We use xor with one to compute the adjacent DWord to whichever one the
8068 OneInputDWord = (OneInput / 2) ^ 1;
8070 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8071 // and BToA inputs. If there is also such a problem with the BToB and AToB
8072 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8073 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8074 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8075 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8076 // Compute how many inputs will be flipped by swapping these DWords. We
8078 // to balance this to ensure we don't form a 3-1 shuffle in the other
8080 int NumFlippedAToBInputs =
8081 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8082 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8083 int NumFlippedBToBInputs =
8084 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8085 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8086 if ((NumFlippedAToBInputs == 1 &&
8087 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8088 (NumFlippedBToBInputs == 1 &&
8089 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8090 // We choose whether to fix the A half or B half based on whether that
8091 // half has zero flipped inputs. At zero, we may not be able to fix it
8092 // with that half. We also bias towards fixing the B half because that
8093 // will more commonly be the high half, and we have to bias one way.
8094 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8095 ArrayRef<int> Inputs) {
8096 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8097 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8098 PinnedIdx ^ 1) != Inputs.end();
8099 // Determine whether the free index is in the flipped dword or the
8100 // unflipped dword based on where the pinned index is. We use this bit
8101 // in an xor to conditionally select the adjacent dword.
8102 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8103 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8104 FixFreeIdx) != Inputs.end();
8105 if (IsFixIdxInput == IsFixFreeIdxInput)
8107 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8108 FixFreeIdx) != Inputs.end();
8109 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8110 "We need to be changing the number of flipped inputs!");
8111 int PSHUFHalfMask[] = {0, 1, 2, 3};
8112 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8113 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8115 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8118 if (M != -1 && M == FixIdx)
8120 else if (M != -1 && M == FixFreeIdx)
8123 if (NumFlippedBToBInputs != 0) {
8125 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8126 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8128 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8130 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8131 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8136 int PSHUFDMask[] = {0, 1, 2, 3};
8137 PSHUFDMask[ADWord] = BDWord;
8138 PSHUFDMask[BDWord] = ADWord;
8139 V = DAG.getNode(ISD::BITCAST, DL, VT,
8140 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8141 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8142 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8145 // Adjust the mask to match the new locations of A and B.
8147 if (M != -1 && M/2 == ADWord)
8148 M = 2 * BDWord + M % 2;
8149 else if (M != -1 && M/2 == BDWord)
8150 M = 2 * ADWord + M % 2;
8152 // Recurse back into this routine to re-compute state now that this isn't
8153 // a 3 and 1 problem.
8154 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8157 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8158 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8159 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8160 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8162 // At this point there are at most two inputs to the low and high halves from
8163 // each half. That means the inputs can always be grouped into dwords and
8164 // those dwords can then be moved to the correct half with a dword shuffle.
8165 // We use at most one low and one high word shuffle to collect these paired
8166 // inputs into dwords, and finally a dword shuffle to place them.
8167 int PSHUFLMask[4] = {-1, -1, -1, -1};
8168 int PSHUFHMask[4] = {-1, -1, -1, -1};
8169 int PSHUFDMask[4] = {-1, -1, -1, -1};
8171 // First fix the masks for all the inputs that are staying in their
8172 // original halves. This will then dictate the targets of the cross-half
8174 auto fixInPlaceInputs =
8175 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8176 MutableArrayRef<int> SourceHalfMask,
8177 MutableArrayRef<int> HalfMask, int HalfOffset) {
8178 if (InPlaceInputs.empty())
8180 if (InPlaceInputs.size() == 1) {
8181 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8182 InPlaceInputs[0] - HalfOffset;
8183 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8186 if (IncomingInputs.empty()) {
8187 // Just fix all of the in place inputs.
8188 for (int Input : InPlaceInputs) {
8189 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8190 PSHUFDMask[Input / 2] = Input / 2;
8195 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8196 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8197 InPlaceInputs[0] - HalfOffset;
8198 // Put the second input next to the first so that they are packed into
8199 // a dword. We find the adjacent index by toggling the low bit.
8200 int AdjIndex = InPlaceInputs[0] ^ 1;
8201 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8202 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8203 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8205 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8206 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8208 // Now gather the cross-half inputs and place them into a free dword of
8209 // their target half.
8210 // FIXME: This operation could almost certainly be simplified dramatically to
8211 // look more like the 3-1 fixing operation.
8212 auto moveInputsToRightHalf = [&PSHUFDMask](
8213 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8214 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8215 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8217 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8218 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8220 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8222 int LowWord = Word & ~1;
8223 int HighWord = Word | 1;
8224 return isWordClobbered(SourceHalfMask, LowWord) ||
8225 isWordClobbered(SourceHalfMask, HighWord);
8228 if (IncomingInputs.empty())
8231 if (ExistingInputs.empty()) {
8232 // Map any dwords with inputs from them into the right half.
8233 for (int Input : IncomingInputs) {
8234 // If the source half mask maps over the inputs, turn those into
8235 // swaps and use the swapped lane.
8236 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8237 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8238 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8239 Input - SourceOffset;
8240 // We have to swap the uses in our half mask in one sweep.
8241 for (int &M : HalfMask)
8242 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8244 else if (M == Input)
8245 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8247 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8248 Input - SourceOffset &&
8249 "Previous placement doesn't match!");
8251 // Note that this correctly re-maps both when we do a swap and when
8252 // we observe the other side of the swap above. We rely on that to
8253 // avoid swapping the members of the input list directly.
8254 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8257 // Map the input's dword into the correct half.
8258 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8259 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8261 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8263 "Previous placement doesn't match!");
8266 // And just directly shift any other-half mask elements to be same-half
8267 // as we will have mirrored the dword containing the element into the
8268 // same position within that half.
8269 for (int &M : HalfMask)
8270 if (M >= SourceOffset && M < SourceOffset + 4) {
8271 M = M - SourceOffset + DestOffset;
8272 assert(M >= 0 && "This should never wrap below zero!");
8277 // Ensure we have the input in a viable dword of its current half. This
8278 // is particularly tricky because the original position may be clobbered
8279 // by inputs being moved and *staying* in that half.
8280 if (IncomingInputs.size() == 1) {
8281 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8282 int InputFixed = std::find(std::begin(SourceHalfMask),
8283 std::end(SourceHalfMask), -1) -
8284 std::begin(SourceHalfMask) + SourceOffset;
8285 SourceHalfMask[InputFixed - SourceOffset] =
8286 IncomingInputs[0] - SourceOffset;
8287 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8289 IncomingInputs[0] = InputFixed;
8291 } else if (IncomingInputs.size() == 2) {
8292 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8293 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8294 // We have two non-adjacent or clobbered inputs we need to extract from
8295 // the source half. To do this, we need to map them into some adjacent
8296 // dword slot in the source mask.
8297 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8298 IncomingInputs[1] - SourceOffset};
8300 // If there is a free slot in the source half mask adjacent to one of
8301 // the inputs, place the other input in it. We use (Index XOR 1) to
8302 // compute an adjacent index.
8303 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8304 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8305 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8306 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8307 InputsFixed[1] = InputsFixed[0] ^ 1;
8308 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8309 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8310 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8311 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8312 InputsFixed[0] = InputsFixed[1] ^ 1;
8313 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8314 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8315 // The two inputs are in the same DWord but it is clobbered and the
8316 // adjacent DWord isn't used at all. Move both inputs to the free
8318 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8319 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8320 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8321 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8323 // The only way we hit this point is if there is no clobbering
8324 // (because there are no off-half inputs to this half) and there is no
8325 // free slot adjacent to one of the inputs. In this case, we have to
8326 // swap an input with a non-input.
8327 for (int i = 0; i < 4; ++i)
8328 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8329 "We can't handle any clobbers here!");
8330 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8331 "Cannot have adjacent inputs here!");
8333 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8334 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8336 // We also have to update the final source mask in this case because
8337 // it may need to undo the above swap.
8338 for (int &M : FinalSourceHalfMask)
8339 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8340 M = InputsFixed[1] + SourceOffset;
8341 else if (M == InputsFixed[1] + SourceOffset)
8342 M = (InputsFixed[0] ^ 1) + SourceOffset;
8344 InputsFixed[1] = InputsFixed[0] ^ 1;
8347 // Point everything at the fixed inputs.
8348 for (int &M : HalfMask)
8349 if (M == IncomingInputs[0])
8350 M = InputsFixed[0] + SourceOffset;
8351 else if (M == IncomingInputs[1])
8352 M = InputsFixed[1] + SourceOffset;
8354 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8355 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8358 llvm_unreachable("Unhandled input size!");
8361 // Now hoist the DWord down to the right half.
8362 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8363 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8364 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8365 for (int &M : HalfMask)
8366 for (int Input : IncomingInputs)
8368 M = FreeDWord * 2 + Input % 2;
8370 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8371 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8372 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8373 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8375 // Now enact all the shuffles we've computed to move the inputs into their
8377 if (!isNoopShuffleMask(PSHUFLMask))
8378 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8379 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8380 if (!isNoopShuffleMask(PSHUFHMask))
8381 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8382 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8383 if (!isNoopShuffleMask(PSHUFDMask))
8384 V = DAG.getNode(ISD::BITCAST, DL, VT,
8385 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8386 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8387 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8390 // At this point, each half should contain all its inputs, and we can then
8391 // just shuffle them into their final position.
8392 assert(std::count_if(LoMask.begin(), LoMask.end(),
8393 [](int M) { return M >= 4; }) == 0 &&
8394 "Failed to lift all the high half inputs to the low mask!");
8395 assert(std::count_if(HiMask.begin(), HiMask.end(),
8396 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8397 "Failed to lift all the low half inputs to the high mask!");
8399 // Do a half shuffle for the low mask.
8400 if (!isNoopShuffleMask(LoMask))
8401 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8402 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8404 // Do a half shuffle with the high mask after shifting its values down.
8405 for (int &M : HiMask)
8408 if (!isNoopShuffleMask(HiMask))
8409 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8410 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8415 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8416 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8417 SDValue V2, ArrayRef<int> Mask,
8418 SelectionDAG &DAG, bool &V1InUse,
8420 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8426 int Size = Mask.size();
8427 int Scale = 16 / Size;
8428 for (int i = 0; i < 16; ++i) {
8429 if (Mask[i / Scale] == -1) {
8430 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8432 const int ZeroMask = 0x80;
8433 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8435 int V2Idx = Mask[i / Scale] < Size
8437 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8438 if (Zeroable[i / Scale])
8439 V1Idx = V2Idx = ZeroMask;
8440 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8441 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8442 V1InUse |= (ZeroMask != V1Idx);
8443 V2InUse |= (ZeroMask != V2Idx);
8448 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8449 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8450 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8452 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8453 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8454 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8456 // If we need shuffled inputs from both, blend the two.
8458 if (V1InUse && V2InUse)
8459 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8461 V = V1InUse ? V1 : V2;
8463 // Cast the result back to the correct type.
8464 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8467 /// \brief Generic lowering of 8-lane i16 shuffles.
8469 /// This handles both single-input shuffles and combined shuffle/blends with
8470 /// two inputs. The single input shuffles are immediately delegated to
8471 /// a dedicated lowering routine.
8473 /// The blends are lowered in one of three fundamental ways. If there are few
8474 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8475 /// of the input is significantly cheaper when lowered as an interleaving of
8476 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8477 /// halves of the inputs separately (making them have relatively few inputs)
8478 /// and then concatenate them.
8479 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8480 const X86Subtarget *Subtarget,
8481 SelectionDAG &DAG) {
8483 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8484 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8485 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8486 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8487 ArrayRef<int> OrigMask = SVOp->getMask();
8488 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8489 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8490 MutableArrayRef<int> Mask(MaskStorage);
8492 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8494 // Whenever we can lower this as a zext, that instruction is strictly faster
8495 // than any alternative.
8496 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8497 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8500 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8502 auto isV2 = [](int M) { return M >= 8; };
8504 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8506 if (NumV2Inputs == 0) {
8507 // Check for being able to broadcast a single element.
8508 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8509 Mask, Subtarget, DAG))
8512 // Try to use shift instructions.
8514 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8517 // Use dedicated unpack instructions for masks that match their pattern.
8518 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8519 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8520 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8521 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8523 // Try to use byte rotation instructions.
8524 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8525 Mask, Subtarget, DAG))
8528 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8532 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8533 "All single-input shuffles should be canonicalized to be V1-input "
8536 // Try to use shift instructions.
8538 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8541 // There are special ways we can lower some single-element blends.
8542 if (NumV2Inputs == 1)
8543 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8544 Mask, Subtarget, DAG))
8547 // We have different paths for blend lowering, but they all must use the
8548 // *exact* same predicate.
8549 bool IsBlendSupported = Subtarget->hasSSE41();
8550 if (IsBlendSupported)
8551 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8555 if (SDValue Masked =
8556 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8559 // Use dedicated unpack instructions for masks that match their pattern.
8560 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8561 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8562 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8563 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8565 // Try to use byte rotation instructions.
8566 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8567 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8570 if (SDValue BitBlend =
8571 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8574 if (SDValue Unpack =
8575 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8578 // If we can't directly blend but can use PSHUFB, that will be better as it
8579 // can both shuffle and set up the inefficient blend.
8580 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8581 bool V1InUse, V2InUse;
8582 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8586 // We can always bit-blend if we have to so the fallback strategy is to
8587 // decompose into single-input permutes and blends.
8588 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8592 /// \brief Check whether a compaction lowering can be done by dropping even
8593 /// elements and compute how many times even elements must be dropped.
8595 /// This handles shuffles which take every Nth element where N is a power of
8596 /// two. Example shuffle masks:
8598 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8599 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8600 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8601 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8602 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8603 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8605 /// Any of these lanes can of course be undef.
8607 /// This routine only supports N <= 3.
8608 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8611 /// \returns N above, or the number of times even elements must be dropped if
8612 /// there is such a number. Otherwise returns zero.
8613 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8614 // Figure out whether we're looping over two inputs or just one.
8615 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8617 // The modulus for the shuffle vector entries is based on whether this is
8618 // a single input or not.
8619 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8620 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8621 "We should only be called with masks with a power-of-2 size!");
8623 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8625 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8626 // and 2^3 simultaneously. This is because we may have ambiguity with
8627 // partially undef inputs.
8628 bool ViableForN[3] = {true, true, true};
8630 for (int i = 0, e = Mask.size(); i < e; ++i) {
8631 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8636 bool IsAnyViable = false;
8637 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8638 if (ViableForN[j]) {
8641 // The shuffle mask must be equal to (i * 2^N) % M.
8642 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8645 ViableForN[j] = false;
8647 // Early exit if we exhaust the possible powers of two.
8652 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8656 // Return 0 as there is no viable power of two.
8660 /// \brief Generic lowering of v16i8 shuffles.
8662 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8663 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8664 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8665 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8667 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8668 const X86Subtarget *Subtarget,
8669 SelectionDAG &DAG) {
8671 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8672 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8673 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8674 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8675 ArrayRef<int> Mask = SVOp->getMask();
8676 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8678 // Try to use shift instructions.
8680 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8683 // Try to use byte rotation instructions.
8684 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8685 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8688 // Try to use a zext lowering.
8689 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8690 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8694 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8696 // For single-input shuffles, there are some nicer lowering tricks we can use.
8697 if (NumV2Elements == 0) {
8698 // Check for being able to broadcast a single element.
8699 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8700 Mask, Subtarget, DAG))
8703 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8704 // Notably, this handles splat and partial-splat shuffles more efficiently.
8705 // However, it only makes sense if the pre-duplication shuffle simplifies
8706 // things significantly. Currently, this means we need to be able to
8707 // express the pre-duplication shuffle as an i16 shuffle.
8709 // FIXME: We should check for other patterns which can be widened into an
8710 // i16 shuffle as well.
8711 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8712 for (int i = 0; i < 16; i += 2)
8713 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8718 auto tryToWidenViaDuplication = [&]() -> SDValue {
8719 if (!canWidenViaDuplication(Mask))
8721 SmallVector<int, 4> LoInputs;
8722 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8723 [](int M) { return M >= 0 && M < 8; });
8724 std::sort(LoInputs.begin(), LoInputs.end());
8725 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8727 SmallVector<int, 4> HiInputs;
8728 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8729 [](int M) { return M >= 8; });
8730 std::sort(HiInputs.begin(), HiInputs.end());
8731 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8734 bool TargetLo = LoInputs.size() >= HiInputs.size();
8735 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8736 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8738 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8739 SmallDenseMap<int, int, 8> LaneMap;
8740 for (int I : InPlaceInputs) {
8741 PreDupI16Shuffle[I/2] = I/2;
8744 int j = TargetLo ? 0 : 4, je = j + 4;
8745 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8746 // Check if j is already a shuffle of this input. This happens when
8747 // there are two adjacent bytes after we move the low one.
8748 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8749 // If we haven't yet mapped the input, search for a slot into which
8751 while (j < je && PreDupI16Shuffle[j] != -1)
8755 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8758 // Map this input with the i16 shuffle.
8759 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8762 // Update the lane map based on the mapping we ended up with.
8763 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8766 ISD::BITCAST, DL, MVT::v16i8,
8767 DAG.getVectorShuffle(MVT::v8i16, DL,
8768 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8769 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8771 // Unpack the bytes to form the i16s that will be shuffled into place.
8772 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8773 MVT::v16i8, V1, V1);
8775 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8776 for (int i = 0; i < 16; ++i)
8777 if (Mask[i] != -1) {
8778 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8779 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8780 if (PostDupI16Shuffle[i / 2] == -1)
8781 PostDupI16Shuffle[i / 2] = MappedMask;
8783 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8784 "Conflicting entrties in the original shuffle!");
8787 ISD::BITCAST, DL, MVT::v16i8,
8788 DAG.getVectorShuffle(MVT::v8i16, DL,
8789 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8790 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8792 if (SDValue V = tryToWidenViaDuplication())
8796 // Use dedicated unpack instructions for masks that match their pattern.
8797 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8798 0, 16, 1, 17, 2, 18, 3, 19,
8800 4, 20, 5, 21, 6, 22, 7, 23}))
8801 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8802 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8803 8, 24, 9, 25, 10, 26, 11, 27,
8805 12, 28, 13, 29, 14, 30, 15, 31}))
8806 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8808 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8809 // with PSHUFB. It is important to do this before we attempt to generate any
8810 // blends but after all of the single-input lowerings. If the single input
8811 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8812 // want to preserve that and we can DAG combine any longer sequences into
8813 // a PSHUFB in the end. But once we start blending from multiple inputs,
8814 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8815 // and there are *very* few patterns that would actually be faster than the
8816 // PSHUFB approach because of its ability to zero lanes.
8818 // FIXME: The only exceptions to the above are blends which are exact
8819 // interleavings with direct instructions supporting them. We currently don't
8820 // handle those well here.
8821 if (Subtarget->hasSSSE3()) {
8822 bool V1InUse = false;
8823 bool V2InUse = false;
8825 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8826 DAG, V1InUse, V2InUse);
8828 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8829 // do so. This avoids using them to handle blends-with-zero which is
8830 // important as a single pshufb is significantly faster for that.
8831 if (V1InUse && V2InUse) {
8832 if (Subtarget->hasSSE41())
8833 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8834 Mask, Subtarget, DAG))
8837 // We can use an unpack to do the blending rather than an or in some
8838 // cases. Even though the or may be (very minorly) more efficient, we
8839 // preference this lowering because there are common cases where part of
8840 // the complexity of the shuffles goes away when we do the final blend as
8842 // FIXME: It might be worth trying to detect if the unpack-feeding
8843 // shuffles will both be pshufb, in which case we shouldn't bother with
8845 if (SDValue Unpack =
8846 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8853 // There are special ways we can lower some single-element blends.
8854 if (NumV2Elements == 1)
8855 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8856 Mask, Subtarget, DAG))
8859 if (SDValue BitBlend =
8860 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8863 // Check whether a compaction lowering can be done. This handles shuffles
8864 // which take every Nth element for some even N. See the helper function for
8867 // We special case these as they can be particularly efficiently handled with
8868 // the PACKUSB instruction on x86 and they show up in common patterns of
8869 // rearranging bytes to truncate wide elements.
8870 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8871 // NumEvenDrops is the power of two stride of the elements. Another way of
8872 // thinking about it is that we need to drop the even elements this many
8873 // times to get the original input.
8874 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8876 // First we need to zero all the dropped bytes.
8877 assert(NumEvenDrops <= 3 &&
8878 "No support for dropping even elements more than 3 times.");
8879 // We use the mask type to pick which bytes are preserved based on how many
8880 // elements are dropped.
8881 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8882 SDValue ByteClearMask =
8883 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8884 DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8885 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8887 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8889 // Now pack things back together.
8890 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8891 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8892 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8893 for (int i = 1; i < NumEvenDrops; ++i) {
8894 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8895 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8901 // Handle multi-input cases by blending single-input shuffles.
8902 if (NumV2Elements > 0)
8903 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8906 // The fallback path for single-input shuffles widens this into two v8i16
8907 // vectors with unpacks, shuffles those, and then pulls them back together
8911 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8912 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8913 for (int i = 0; i < 16; ++i)
8915 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8917 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8919 SDValue VLoHalf, VHiHalf;
8920 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8921 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8923 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8924 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8925 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8926 [](int M) { return M >= 0 && M % 2 == 1; })) {
8927 // Use a mask to drop the high bytes.
8928 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8929 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8930 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8932 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8933 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8935 // Squash the masks to point directly into VLoHalf.
8936 for (int &M : LoBlendMask)
8939 for (int &M : HiBlendMask)
8943 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8944 // VHiHalf so that we can blend them as i16s.
8945 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8946 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8947 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8948 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8951 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8952 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8954 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8957 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8959 /// This routine breaks down the specific type of 128-bit shuffle and
8960 /// dispatches to the lowering routines accordingly.
8961 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8962 MVT VT, const X86Subtarget *Subtarget,
8963 SelectionDAG &DAG) {
8964 switch (VT.SimpleTy) {
8966 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8968 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8970 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8972 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8974 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8976 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8979 llvm_unreachable("Unimplemented!");
8983 /// \brief Helper function to test whether a shuffle mask could be
8984 /// simplified by widening the elements being shuffled.
8986 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8987 /// leaves it in an unspecified state.
8989 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8990 /// shuffle masks. The latter have the special property of a '-2' representing
8991 /// a zero-ed lane of a vector.
8992 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8993 SmallVectorImpl<int> &WidenedMask) {
8994 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8995 // If both elements are undef, its trivial.
8996 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8997 WidenedMask.push_back(SM_SentinelUndef);
9001 // Check for an undef mask and a mask value properly aligned to fit with
9002 // a pair of values. If we find such a case, use the non-undef mask's value.
9003 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9004 WidenedMask.push_back(Mask[i + 1] / 2);
9007 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9008 WidenedMask.push_back(Mask[i] / 2);
9012 // When zeroing, we need to spread the zeroing across both lanes to widen.
9013 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9014 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9015 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9016 WidenedMask.push_back(SM_SentinelZero);
9022 // Finally check if the two mask values are adjacent and aligned with
9024 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9025 WidenedMask.push_back(Mask[i] / 2);
9029 // Otherwise we can't safely widen the elements used in this shuffle.
9032 assert(WidenedMask.size() == Mask.size() / 2 &&
9033 "Incorrect size of mask after widening the elements!");
9038 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9040 /// This routine just extracts two subvectors, shuffles them independently, and
9041 /// then concatenates them back together. This should work effectively with all
9042 /// AVX vector shuffle types.
9043 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9044 SDValue V2, ArrayRef<int> Mask,
9045 SelectionDAG &DAG) {
9046 assert(VT.getSizeInBits() >= 256 &&
9047 "Only for 256-bit or wider vector shuffles!");
9048 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9049 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9051 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9052 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9054 int NumElements = VT.getVectorNumElements();
9055 int SplitNumElements = NumElements / 2;
9056 MVT ScalarVT = VT.getScalarType();
9057 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9059 // Rather than splitting build-vectors, just build two narrower build
9060 // vectors. This helps shuffling with splats and zeros.
9061 auto SplitVector = [&](SDValue V) {
9062 while (V.getOpcode() == ISD::BITCAST)
9063 V = V->getOperand(0);
9065 MVT OrigVT = V.getSimpleValueType();
9066 int OrigNumElements = OrigVT.getVectorNumElements();
9067 int OrigSplitNumElements = OrigNumElements / 2;
9068 MVT OrigScalarVT = OrigVT.getScalarType();
9069 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9073 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9075 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9076 DAG.getIntPtrConstant(0, DL));
9077 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9078 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9081 SmallVector<SDValue, 16> LoOps, HiOps;
9082 for (int i = 0; i < OrigSplitNumElements; ++i) {
9083 LoOps.push_back(BV->getOperand(i));
9084 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9086 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9087 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9089 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
9090 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
9093 SDValue LoV1, HiV1, LoV2, HiV2;
9094 std::tie(LoV1, HiV1) = SplitVector(V1);
9095 std::tie(LoV2, HiV2) = SplitVector(V2);
9097 // Now create two 4-way blends of these half-width vectors.
9098 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9099 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9100 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9101 for (int i = 0; i < SplitNumElements; ++i) {
9102 int M = HalfMask[i];
9103 if (M >= NumElements) {
9104 if (M >= NumElements + SplitNumElements)
9108 V2BlendMask.push_back(M - NumElements);
9109 V1BlendMask.push_back(-1);
9110 BlendMask.push_back(SplitNumElements + i);
9111 } else if (M >= 0) {
9112 if (M >= SplitNumElements)
9116 V2BlendMask.push_back(-1);
9117 V1BlendMask.push_back(M);
9118 BlendMask.push_back(i);
9120 V2BlendMask.push_back(-1);
9121 V1BlendMask.push_back(-1);
9122 BlendMask.push_back(-1);
9126 // Because the lowering happens after all combining takes place, we need to
9127 // manually combine these blend masks as much as possible so that we create
9128 // a minimal number of high-level vector shuffle nodes.
9130 // First try just blending the halves of V1 or V2.
9131 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9132 return DAG.getUNDEF(SplitVT);
9133 if (!UseLoV2 && !UseHiV2)
9134 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9135 if (!UseLoV1 && !UseHiV1)
9136 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9138 SDValue V1Blend, V2Blend;
9139 if (UseLoV1 && UseHiV1) {
9141 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9143 // We only use half of V1 so map the usage down into the final blend mask.
9144 V1Blend = UseLoV1 ? LoV1 : HiV1;
9145 for (int i = 0; i < SplitNumElements; ++i)
9146 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9147 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9149 if (UseLoV2 && UseHiV2) {
9151 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9153 // We only use half of V2 so map the usage down into the final blend mask.
9154 V2Blend = UseLoV2 ? LoV2 : HiV2;
9155 for (int i = 0; i < SplitNumElements; ++i)
9156 if (BlendMask[i] >= SplitNumElements)
9157 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9159 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9161 SDValue Lo = HalfBlend(LoMask);
9162 SDValue Hi = HalfBlend(HiMask);
9163 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9166 /// \brief Either split a vector in halves or decompose the shuffles and the
9169 /// This is provided as a good fallback for many lowerings of non-single-input
9170 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9171 /// between splitting the shuffle into 128-bit components and stitching those
9172 /// back together vs. extracting the single-input shuffles and blending those
9174 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9175 SDValue V2, ArrayRef<int> Mask,
9176 SelectionDAG &DAG) {
9177 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9178 "lower single-input shuffles as it "
9179 "could then recurse on itself.");
9180 int Size = Mask.size();
9182 // If this can be modeled as a broadcast of two elements followed by a blend,
9183 // prefer that lowering. This is especially important because broadcasts can
9184 // often fold with memory operands.
9185 auto DoBothBroadcast = [&] {
9186 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9189 if (V2BroadcastIdx == -1)
9190 V2BroadcastIdx = M - Size;
9191 else if (M - Size != V2BroadcastIdx)
9193 } else if (M >= 0) {
9194 if (V1BroadcastIdx == -1)
9196 else if (M != V1BroadcastIdx)
9201 if (DoBothBroadcast())
9202 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9205 // If the inputs all stem from a single 128-bit lane of each input, then we
9206 // split them rather than blending because the split will decompose to
9207 // unusually few instructions.
9208 int LaneCount = VT.getSizeInBits() / 128;
9209 int LaneSize = Size / LaneCount;
9210 SmallBitVector LaneInputs[2];
9211 LaneInputs[0].resize(LaneCount, false);
9212 LaneInputs[1].resize(LaneCount, false);
9213 for (int i = 0; i < Size; ++i)
9215 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9216 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9217 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9219 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9220 // that the decomposed single-input shuffles don't end up here.
9221 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9224 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9225 /// a permutation and blend of those lanes.
9227 /// This essentially blends the out-of-lane inputs to each lane into the lane
9228 /// from a permuted copy of the vector. This lowering strategy results in four
9229 /// instructions in the worst case for a single-input cross lane shuffle which
9230 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9231 /// of. Special cases for each particular shuffle pattern should be handled
9232 /// prior to trying this lowering.
9233 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9234 SDValue V1, SDValue V2,
9236 SelectionDAG &DAG) {
9237 // FIXME: This should probably be generalized for 512-bit vectors as well.
9238 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9239 int LaneSize = Mask.size() / 2;
9241 // If there are only inputs from one 128-bit lane, splitting will in fact be
9242 // less expensive. The flags track whether the given lane contains an element
9243 // that crosses to another lane.
9244 bool LaneCrossing[2] = {false, false};
9245 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9246 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9247 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9248 if (!LaneCrossing[0] || !LaneCrossing[1])
9249 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9251 if (isSingleInputShuffleMask(Mask)) {
9252 SmallVector<int, 32> FlippedBlendMask;
9253 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9254 FlippedBlendMask.push_back(
9255 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9257 : Mask[i] % LaneSize +
9258 (i / LaneSize) * LaneSize + Size));
9260 // Flip the vector, and blend the results which should now be in-lane. The
9261 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9262 // 5 for the high source. The value 3 selects the high half of source 2 and
9263 // the value 2 selects the low half of source 2. We only use source 2 to
9264 // allow folding it into a memory operand.
9265 unsigned PERMMask = 3 | 2 << 4;
9266 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9267 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9268 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9271 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9272 // will be handled by the above logic and a blend of the results, much like
9273 // other patterns in AVX.
9274 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9277 /// \brief Handle lowering 2-lane 128-bit shuffles.
9278 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9279 SDValue V2, ArrayRef<int> Mask,
9280 const X86Subtarget *Subtarget,
9281 SelectionDAG &DAG) {
9282 // TODO: If minimizing size and one of the inputs is a zero vector and the
9283 // the zero vector has only one use, we could use a VPERM2X128 to save the
9284 // instruction bytes needed to explicitly generate the zero vector.
9286 // Blends are faster and handle all the non-lane-crossing cases.
9287 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9291 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9292 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9294 // If either input operand is a zero vector, use VPERM2X128 because its mask
9295 // allows us to replace the zero input with an implicit zero.
9296 if (!IsV1Zero && !IsV2Zero) {
9297 // Check for patterns which can be matched with a single insert of a 128-bit
9299 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9300 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9301 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9302 VT.getVectorNumElements() / 2);
9303 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9304 DAG.getIntPtrConstant(0, DL));
9305 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9306 OnlyUsesV1 ? V1 : V2,
9307 DAG.getIntPtrConstant(0, DL));
9308 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9312 // Otherwise form a 128-bit permutation. After accounting for undefs,
9313 // convert the 64-bit shuffle mask selection values into 128-bit
9314 // selection bits by dividing the indexes by 2 and shifting into positions
9315 // defined by a vperm2*128 instruction's immediate control byte.
9317 // The immediate permute control byte looks like this:
9318 // [1:0] - select 128 bits from sources for low half of destination
9320 // [3] - zero low half of destination
9321 // [5:4] - select 128 bits from sources for high half of destination
9323 // [7] - zero high half of destination
9325 int MaskLO = Mask[0];
9326 if (MaskLO == SM_SentinelUndef)
9327 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9329 int MaskHI = Mask[2];
9330 if (MaskHI == SM_SentinelUndef)
9331 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9333 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9335 // If either input is a zero vector, replace it with an undef input.
9336 // Shuffle mask values < 4 are selecting elements of V1.
9337 // Shuffle mask values >= 4 are selecting elements of V2.
9338 // Adjust each half of the permute mask by clearing the half that was
9339 // selecting the zero vector and setting the zero mask bit.
9341 V1 = DAG.getUNDEF(VT);
9343 PermMask = (PermMask & 0xf0) | 0x08;
9345 PermMask = (PermMask & 0x0f) | 0x80;
9348 V2 = DAG.getUNDEF(VT);
9350 PermMask = (PermMask & 0xf0) | 0x08;
9352 PermMask = (PermMask & 0x0f) | 0x80;
9355 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9356 DAG.getConstant(PermMask, DL, MVT::i8));
9359 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9360 /// shuffling each lane.
9362 /// This will only succeed when the result of fixing the 128-bit lanes results
9363 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9364 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9365 /// the lane crosses early and then use simpler shuffles within each lane.
9367 /// FIXME: It might be worthwhile at some point to support this without
9368 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9369 /// in x86 only floating point has interesting non-repeating shuffles, and even
9370 /// those are still *marginally* more expensive.
9371 static SDValue lowerVectorShuffleByMerging128BitLanes(
9372 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9373 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9374 assert(!isSingleInputShuffleMask(Mask) &&
9375 "This is only useful with multiple inputs.");
9377 int Size = Mask.size();
9378 int LaneSize = 128 / VT.getScalarSizeInBits();
9379 int NumLanes = Size / LaneSize;
9380 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9382 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9383 // check whether the in-128-bit lane shuffles share a repeating pattern.
9384 SmallVector<int, 4> Lanes;
9385 Lanes.resize(NumLanes, -1);
9386 SmallVector<int, 4> InLaneMask;
9387 InLaneMask.resize(LaneSize, -1);
9388 for (int i = 0; i < Size; ++i) {
9392 int j = i / LaneSize;
9395 // First entry we've seen for this lane.
9396 Lanes[j] = Mask[i] / LaneSize;
9397 } else if (Lanes[j] != Mask[i] / LaneSize) {
9398 // This doesn't match the lane selected previously!
9402 // Check that within each lane we have a consistent shuffle mask.
9403 int k = i % LaneSize;
9404 if (InLaneMask[k] < 0) {
9405 InLaneMask[k] = Mask[i] % LaneSize;
9406 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9407 // This doesn't fit a repeating in-lane mask.
9412 // First shuffle the lanes into place.
9413 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9414 VT.getSizeInBits() / 64);
9415 SmallVector<int, 8> LaneMask;
9416 LaneMask.resize(NumLanes * 2, -1);
9417 for (int i = 0; i < NumLanes; ++i)
9418 if (Lanes[i] >= 0) {
9419 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9420 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9423 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9424 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9425 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9427 // Cast it back to the type we actually want.
9428 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9430 // Now do a simple shuffle that isn't lane crossing.
9431 SmallVector<int, 8> NewMask;
9432 NewMask.resize(Size, -1);
9433 for (int i = 0; i < Size; ++i)
9435 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9436 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9437 "Must not introduce lane crosses at this point!");
9439 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9442 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9445 /// This returns true if the elements from a particular input are already in the
9446 /// slot required by the given mask and require no permutation.
9447 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9448 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9449 int Size = Mask.size();
9450 for (int i = 0; i < Size; ++i)
9451 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9457 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9459 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9460 /// isn't available.
9461 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9462 const X86Subtarget *Subtarget,
9463 SelectionDAG &DAG) {
9465 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9466 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9467 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9468 ArrayRef<int> Mask = SVOp->getMask();
9469 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9471 SmallVector<int, 4> WidenedMask;
9472 if (canWidenShuffleElements(Mask, WidenedMask))
9473 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9476 if (isSingleInputShuffleMask(Mask)) {
9477 // Check for being able to broadcast a single element.
9478 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9479 Mask, Subtarget, DAG))
9482 // Use low duplicate instructions for masks that match their pattern.
9483 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9484 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9486 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9487 // Non-half-crossing single input shuffles can be lowerid with an
9488 // interleaved permutation.
9489 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9490 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9491 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9492 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9495 // With AVX2 we have direct support for this permutation.
9496 if (Subtarget->hasAVX2())
9497 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9498 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9500 // Otherwise, fall back.
9501 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9505 // X86 has dedicated unpack instructions that can handle specific blend
9506 // operations: UNPCKH and UNPCKL.
9507 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9508 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9509 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9510 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9511 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9512 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9513 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9514 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9516 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9520 // Check if the blend happens to exactly fit that of SHUFPD.
9521 if ((Mask[0] == -1 || Mask[0] < 2) &&
9522 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9523 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9524 (Mask[3] == -1 || Mask[3] >= 6)) {
9525 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9526 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9527 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9528 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9530 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9531 (Mask[1] == -1 || Mask[1] < 2) &&
9532 (Mask[2] == -1 || Mask[2] >= 6) &&
9533 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9534 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9535 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9536 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9537 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9540 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9541 // shuffle. However, if we have AVX2 and either inputs are already in place,
9542 // we will be able to shuffle even across lanes the other input in a single
9543 // instruction so skip this pattern.
9544 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9545 isShuffleMaskInputInPlace(1, Mask))))
9546 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9547 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9550 // If we have AVX2 then we always want to lower with a blend because an v4 we
9551 // can fully permute the elements.
9552 if (Subtarget->hasAVX2())
9553 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9556 // Otherwise fall back on generic lowering.
9557 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9560 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9562 /// This routine is only called when we have AVX2 and thus a reasonable
9563 /// instruction set for v4i64 shuffling..
9564 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9565 const X86Subtarget *Subtarget,
9566 SelectionDAG &DAG) {
9568 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9569 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9570 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9571 ArrayRef<int> Mask = SVOp->getMask();
9572 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9573 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9575 SmallVector<int, 4> WidenedMask;
9576 if (canWidenShuffleElements(Mask, WidenedMask))
9577 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9580 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9584 // Check for being able to broadcast a single element.
9585 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9586 Mask, Subtarget, DAG))
9589 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9590 // use lower latency instructions that will operate on both 128-bit lanes.
9591 SmallVector<int, 2> RepeatedMask;
9592 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9593 if (isSingleInputShuffleMask(Mask)) {
9594 int PSHUFDMask[] = {-1, -1, -1, -1};
9595 for (int i = 0; i < 2; ++i)
9596 if (RepeatedMask[i] >= 0) {
9597 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9598 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9601 ISD::BITCAST, DL, MVT::v4i64,
9602 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9603 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9604 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9608 // AVX2 provides a direct instruction for permuting a single input across
9610 if (isSingleInputShuffleMask(Mask))
9611 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9612 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9614 // Try to use shift instructions.
9616 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9619 // Use dedicated unpack instructions for masks that match their pattern.
9620 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9621 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9622 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9623 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9624 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9625 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9626 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9627 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9629 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9630 // shuffle. However, if we have AVX2 and either inputs are already in place,
9631 // we will be able to shuffle even across lanes the other input in a single
9632 // instruction so skip this pattern.
9633 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9634 isShuffleMaskInputInPlace(1, Mask))))
9635 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9636 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9639 // Otherwise fall back on generic blend lowering.
9640 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9644 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9646 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9647 /// isn't available.
9648 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9649 const X86Subtarget *Subtarget,
9650 SelectionDAG &DAG) {
9652 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9653 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9654 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9655 ArrayRef<int> Mask = SVOp->getMask();
9656 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9658 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9662 // Check for being able to broadcast a single element.
9663 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9664 Mask, Subtarget, DAG))
9667 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9668 // options to efficiently lower the shuffle.
9669 SmallVector<int, 4> RepeatedMask;
9670 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9671 assert(RepeatedMask.size() == 4 &&
9672 "Repeated masks must be half the mask width!");
9674 // Use even/odd duplicate instructions for masks that match their pattern.
9675 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9676 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9677 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9678 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9680 if (isSingleInputShuffleMask(Mask))
9681 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9682 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9684 // Use dedicated unpack instructions for masks that match their pattern.
9685 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9686 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9687 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9688 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9689 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9690 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9691 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9692 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9694 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9695 // have already handled any direct blends. We also need to squash the
9696 // repeated mask into a simulated v4f32 mask.
9697 for (int i = 0; i < 4; ++i)
9698 if (RepeatedMask[i] >= 8)
9699 RepeatedMask[i] -= 4;
9700 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9703 // If we have a single input shuffle with different shuffle patterns in the
9704 // two 128-bit lanes use the variable mask to VPERMILPS.
9705 if (isSingleInputShuffleMask(Mask)) {
9706 SDValue VPermMask[8];
9707 for (int i = 0; i < 8; ++i)
9708 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9709 : DAG.getConstant(Mask[i], DL, MVT::i32);
9710 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9712 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9713 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9715 if (Subtarget->hasAVX2())
9716 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9717 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9718 DAG.getNode(ISD::BUILD_VECTOR, DL,
9719 MVT::v8i32, VPermMask)),
9722 // Otherwise, fall back.
9723 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9727 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9729 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9730 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9733 // If we have AVX2 then we always want to lower with a blend because at v8 we
9734 // can fully permute the elements.
9735 if (Subtarget->hasAVX2())
9736 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9739 // Otherwise fall back on generic lowering.
9740 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9743 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9745 /// This routine is only called when we have AVX2 and thus a reasonable
9746 /// instruction set for v8i32 shuffling..
9747 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9748 const X86Subtarget *Subtarget,
9749 SelectionDAG &DAG) {
9751 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9752 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9753 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9754 ArrayRef<int> Mask = SVOp->getMask();
9755 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9756 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9758 // Whenever we can lower this as a zext, that instruction is strictly faster
9759 // than any alternative. It also allows us to fold memory operands into the
9760 // shuffle in many cases.
9761 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9762 Mask, Subtarget, DAG))
9765 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9769 // Check for being able to broadcast a single element.
9770 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9771 Mask, Subtarget, DAG))
9774 // If the shuffle mask is repeated in each 128-bit lane we can use more
9775 // efficient instructions that mirror the shuffles across the two 128-bit
9777 SmallVector<int, 4> RepeatedMask;
9778 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9779 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9780 if (isSingleInputShuffleMask(Mask))
9781 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9782 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9784 // Use dedicated unpack instructions for masks that match their pattern.
9785 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9786 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9787 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9788 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9789 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9790 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9791 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9792 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9795 // Try to use shift instructions.
9797 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9800 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9801 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9804 // If the shuffle patterns aren't repeated but it is a single input, directly
9805 // generate a cross-lane VPERMD instruction.
9806 if (isSingleInputShuffleMask(Mask)) {
9807 SDValue VPermMask[8];
9808 for (int i = 0; i < 8; ++i)
9809 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9810 : DAG.getConstant(Mask[i], DL, MVT::i32);
9812 X86ISD::VPERMV, DL, MVT::v8i32,
9813 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9816 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9818 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9819 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9822 // Otherwise fall back on generic blend lowering.
9823 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9827 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9829 /// This routine is only called when we have AVX2 and thus a reasonable
9830 /// instruction set for v16i16 shuffling..
9831 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9832 const X86Subtarget *Subtarget,
9833 SelectionDAG &DAG) {
9835 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9836 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9837 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9838 ArrayRef<int> Mask = SVOp->getMask();
9839 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9840 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9842 // Whenever we can lower this as a zext, that instruction is strictly faster
9843 // than any alternative. It also allows us to fold memory operands into the
9844 // shuffle in many cases.
9845 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9846 Mask, Subtarget, DAG))
9849 // Check for being able to broadcast a single element.
9850 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9851 Mask, Subtarget, DAG))
9854 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9858 // Use dedicated unpack instructions for masks that match their pattern.
9859 if (isShuffleEquivalent(V1, V2, Mask,
9860 {// First 128-bit lane:
9861 0, 16, 1, 17, 2, 18, 3, 19,
9862 // Second 128-bit lane:
9863 8, 24, 9, 25, 10, 26, 11, 27}))
9864 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9865 if (isShuffleEquivalent(V1, V2, Mask,
9866 {// First 128-bit lane:
9867 4, 20, 5, 21, 6, 22, 7, 23,
9868 // Second 128-bit lane:
9869 12, 28, 13, 29, 14, 30, 15, 31}))
9870 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9872 // Try to use shift instructions.
9874 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9877 // Try to use byte rotation instructions.
9878 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9879 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9882 if (isSingleInputShuffleMask(Mask)) {
9883 // There are no generalized cross-lane shuffle operations available on i16
9885 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9886 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9889 SmallVector<int, 8> RepeatedMask;
9890 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9891 // As this is a single-input shuffle, the repeated mask should be
9892 // a strictly valid v8i16 mask that we can pass through to the v8i16
9893 // lowering to handle even the v16 case.
9894 return lowerV8I16GeneralSingleInputVectorShuffle(
9895 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9898 SDValue PSHUFBMask[32];
9899 for (int i = 0; i < 16; ++i) {
9900 if (Mask[i] == -1) {
9901 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9905 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9906 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9907 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9908 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9911 ISD::BITCAST, DL, MVT::v16i16,
9913 X86ISD::PSHUFB, DL, MVT::v32i8,
9914 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9915 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9918 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9920 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9921 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9924 // Otherwise fall back on generic lowering.
9925 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9928 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9930 /// This routine is only called when we have AVX2 and thus a reasonable
9931 /// instruction set for v32i8 shuffling..
9932 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9933 const X86Subtarget *Subtarget,
9934 SelectionDAG &DAG) {
9936 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9937 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9938 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9939 ArrayRef<int> Mask = SVOp->getMask();
9940 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9941 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9943 // Whenever we can lower this as a zext, that instruction is strictly faster
9944 // than any alternative. It also allows us to fold memory operands into the
9945 // shuffle in many cases.
9946 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9947 Mask, Subtarget, DAG))
9950 // Check for being able to broadcast a single element.
9951 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9952 Mask, Subtarget, DAG))
9955 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9959 // Use dedicated unpack instructions for masks that match their pattern.
9960 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9962 if (isShuffleEquivalent(
9964 {// First 128-bit lane:
9965 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9966 // Second 128-bit lane:
9967 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9968 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9969 if (isShuffleEquivalent(
9971 {// First 128-bit lane:
9972 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9973 // Second 128-bit lane:
9974 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9975 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9977 // Try to use shift instructions.
9979 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9982 // Try to use byte rotation instructions.
9983 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9984 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9987 if (isSingleInputShuffleMask(Mask)) {
9988 // There are no generalized cross-lane shuffle operations available on i8
9990 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9991 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9994 SDValue PSHUFBMask[32];
9995 for (int i = 0; i < 32; ++i)
9998 ? DAG.getUNDEF(MVT::i8)
9999 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10002 return DAG.getNode(
10003 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10004 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10007 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10009 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10010 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10013 // Otherwise fall back on generic lowering.
10014 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10017 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10019 /// This routine either breaks down the specific type of a 256-bit x86 vector
10020 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10021 /// together based on the available instructions.
10022 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10023 MVT VT, const X86Subtarget *Subtarget,
10024 SelectionDAG &DAG) {
10026 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10027 ArrayRef<int> Mask = SVOp->getMask();
10029 // If we have a single input to the zero element, insert that into V1 if we
10030 // can do so cheaply.
10031 int NumElts = VT.getVectorNumElements();
10032 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10033 return M >= NumElts;
10036 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10037 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10038 DL, VT, V1, V2, Mask, Subtarget, DAG))
10041 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10042 // check for those subtargets here and avoid much of the subtarget querying in
10043 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10044 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10045 // floating point types there eventually, just immediately cast everything to
10046 // a float and operate entirely in that domain.
10047 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10048 int ElementBits = VT.getScalarSizeInBits();
10049 if (ElementBits < 32)
10050 // No floating point type available, decompose into 128-bit vectors.
10051 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10053 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10054 VT.getVectorNumElements());
10055 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10056 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10057 return DAG.getNode(ISD::BITCAST, DL, VT,
10058 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10061 switch (VT.SimpleTy) {
10063 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10065 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10067 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10069 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10071 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10073 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10076 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10080 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10081 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10082 const X86Subtarget *Subtarget,
10083 SelectionDAG &DAG) {
10085 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10086 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10087 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10088 ArrayRef<int> Mask = SVOp->getMask();
10089 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10091 // X86 has dedicated unpack instructions that can handle specific blend
10092 // operations: UNPCKH and UNPCKL.
10093 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10094 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10095 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10096 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10098 // FIXME: Implement direct support for this type!
10099 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10102 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10103 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10104 const X86Subtarget *Subtarget,
10105 SelectionDAG &DAG) {
10107 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10108 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10109 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10110 ArrayRef<int> Mask = SVOp->getMask();
10111 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10113 // Use dedicated unpack instructions for masks that match their pattern.
10114 if (isShuffleEquivalent(V1, V2, Mask,
10115 {// First 128-bit lane.
10116 0, 16, 1, 17, 4, 20, 5, 21,
10117 // Second 128-bit lane.
10118 8, 24, 9, 25, 12, 28, 13, 29}))
10119 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10120 if (isShuffleEquivalent(V1, V2, Mask,
10121 {// First 128-bit lane.
10122 2, 18, 3, 19, 6, 22, 7, 23,
10123 // Second 128-bit lane.
10124 10, 26, 11, 27, 14, 30, 15, 31}))
10125 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10127 // FIXME: Implement direct support for this type!
10128 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10131 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10132 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10133 const X86Subtarget *Subtarget,
10134 SelectionDAG &DAG) {
10136 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10137 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10138 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10139 ArrayRef<int> Mask = SVOp->getMask();
10140 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10142 // X86 has dedicated unpack instructions that can handle specific blend
10143 // operations: UNPCKH and UNPCKL.
10144 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10145 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10146 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10147 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10149 // FIXME: Implement direct support for this type!
10150 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10153 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10154 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10155 const X86Subtarget *Subtarget,
10156 SelectionDAG &DAG) {
10158 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10159 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10161 ArrayRef<int> Mask = SVOp->getMask();
10162 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10164 // Use dedicated unpack instructions for masks that match their pattern.
10165 if (isShuffleEquivalent(V1, V2, Mask,
10166 {// First 128-bit lane.
10167 0, 16, 1, 17, 4, 20, 5, 21,
10168 // Second 128-bit lane.
10169 8, 24, 9, 25, 12, 28, 13, 29}))
10170 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10171 if (isShuffleEquivalent(V1, V2, Mask,
10172 {// First 128-bit lane.
10173 2, 18, 3, 19, 6, 22, 7, 23,
10174 // Second 128-bit lane.
10175 10, 26, 11, 27, 14, 30, 15, 31}))
10176 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10178 // FIXME: Implement direct support for this type!
10179 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10182 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10183 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10184 const X86Subtarget *Subtarget,
10185 SelectionDAG &DAG) {
10187 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10188 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10189 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10190 ArrayRef<int> Mask = SVOp->getMask();
10191 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10192 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10194 // FIXME: Implement direct support for this type!
10195 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10198 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10199 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10200 const X86Subtarget *Subtarget,
10201 SelectionDAG &DAG) {
10203 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10204 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10206 ArrayRef<int> Mask = SVOp->getMask();
10207 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10208 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10210 // FIXME: Implement direct support for this type!
10211 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10214 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10216 /// This routine either breaks down the specific type of a 512-bit x86 vector
10217 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10218 /// together based on the available instructions.
10219 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10220 MVT VT, const X86Subtarget *Subtarget,
10221 SelectionDAG &DAG) {
10223 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10224 ArrayRef<int> Mask = SVOp->getMask();
10225 assert(Subtarget->hasAVX512() &&
10226 "Cannot lower 512-bit vectors w/ basic ISA!");
10228 // Check for being able to broadcast a single element.
10229 if (SDValue Broadcast =
10230 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10233 // Dispatch to each element type for lowering. If we don't have supprot for
10234 // specific element type shuffles at 512 bits, immediately split them and
10235 // lower them. Each lowering routine of a given type is allowed to assume that
10236 // the requisite ISA extensions for that element type are available.
10237 switch (VT.SimpleTy) {
10239 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10241 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10243 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10245 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10247 if (Subtarget->hasBWI())
10248 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10251 if (Subtarget->hasBWI())
10252 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10256 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10259 // Otherwise fall back on splitting.
10260 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10263 /// \brief Top-level lowering for x86 vector shuffles.
10265 /// This handles decomposition, canonicalization, and lowering of all x86
10266 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10267 /// above in helper routines. The canonicalization attempts to widen shuffles
10268 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10269 /// s.t. only one of the two inputs needs to be tested, etc.
10270 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10271 SelectionDAG &DAG) {
10272 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10273 ArrayRef<int> Mask = SVOp->getMask();
10274 SDValue V1 = Op.getOperand(0);
10275 SDValue V2 = Op.getOperand(1);
10276 MVT VT = Op.getSimpleValueType();
10277 int NumElements = VT.getVectorNumElements();
10280 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10282 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10283 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10284 if (V1IsUndef && V2IsUndef)
10285 return DAG.getUNDEF(VT);
10287 // When we create a shuffle node we put the UNDEF node to second operand,
10288 // but in some cases the first operand may be transformed to UNDEF.
10289 // In this case we should just commute the node.
10291 return DAG.getCommutedVectorShuffle(*SVOp);
10293 // Check for non-undef masks pointing at an undef vector and make the masks
10294 // undef as well. This makes it easier to match the shuffle based solely on
10298 if (M >= NumElements) {
10299 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10300 for (int &M : NewMask)
10301 if (M >= NumElements)
10303 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10306 // We actually see shuffles that are entirely re-arrangements of a set of
10307 // zero inputs. This mostly happens while decomposing complex shuffles into
10308 // simple ones. Directly lower these as a buildvector of zeros.
10309 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10310 if (Zeroable.all())
10311 return getZeroVector(VT, Subtarget, DAG, dl);
10313 // Try to collapse shuffles into using a vector type with fewer elements but
10314 // wider element types. We cap this to not form integers or floating point
10315 // elements wider than 64 bits, but it might be interesting to form i128
10316 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10317 SmallVector<int, 16> WidenedMask;
10318 if (VT.getScalarSizeInBits() < 64 &&
10319 canWidenShuffleElements(Mask, WidenedMask)) {
10320 MVT NewEltVT = VT.isFloatingPoint()
10321 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10322 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10323 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10324 // Make sure that the new vector type is legal. For example, v2f64 isn't
10326 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10327 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10328 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10329 return DAG.getNode(ISD::BITCAST, dl, VT,
10330 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10334 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10335 for (int M : SVOp->getMask())
10337 ++NumUndefElements;
10338 else if (M < NumElements)
10343 // Commute the shuffle as needed such that more elements come from V1 than
10344 // V2. This allows us to match the shuffle pattern strictly on how many
10345 // elements come from V1 without handling the symmetric cases.
10346 if (NumV2Elements > NumV1Elements)
10347 return DAG.getCommutedVectorShuffle(*SVOp);
10349 // When the number of V1 and V2 elements are the same, try to minimize the
10350 // number of uses of V2 in the low half of the vector. When that is tied,
10351 // ensure that the sum of indices for V1 is equal to or lower than the sum
10352 // indices for V2. When those are equal, try to ensure that the number of odd
10353 // indices for V1 is lower than the number of odd indices for V2.
10354 if (NumV1Elements == NumV2Elements) {
10355 int LowV1Elements = 0, LowV2Elements = 0;
10356 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10357 if (M >= NumElements)
10361 if (LowV2Elements > LowV1Elements) {
10362 return DAG.getCommutedVectorShuffle(*SVOp);
10363 } else if (LowV2Elements == LowV1Elements) {
10364 int SumV1Indices = 0, SumV2Indices = 0;
10365 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10366 if (SVOp->getMask()[i] >= NumElements)
10368 else if (SVOp->getMask()[i] >= 0)
10370 if (SumV2Indices < SumV1Indices) {
10371 return DAG.getCommutedVectorShuffle(*SVOp);
10372 } else if (SumV2Indices == SumV1Indices) {
10373 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10374 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10375 if (SVOp->getMask()[i] >= NumElements)
10376 NumV2OddIndices += i % 2;
10377 else if (SVOp->getMask()[i] >= 0)
10378 NumV1OddIndices += i % 2;
10379 if (NumV2OddIndices < NumV1OddIndices)
10380 return DAG.getCommutedVectorShuffle(*SVOp);
10385 // For each vector width, delegate to a specialized lowering routine.
10386 if (VT.getSizeInBits() == 128)
10387 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10389 if (VT.getSizeInBits() == 256)
10390 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10392 // Force AVX-512 vectors to be scalarized for now.
10393 // FIXME: Implement AVX-512 support!
10394 if (VT.getSizeInBits() == 512)
10395 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10397 llvm_unreachable("Unimplemented!");
10400 // This function assumes its argument is a BUILD_VECTOR of constants or
10401 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10403 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10404 unsigned &MaskValue) {
10406 unsigned NumElems = BuildVector->getNumOperands();
10407 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10408 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10409 unsigned NumElemsInLane = NumElems / NumLanes;
10411 // Blend for v16i16 should be symetric for the both lanes.
10412 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10413 SDValue EltCond = BuildVector->getOperand(i);
10414 SDValue SndLaneEltCond =
10415 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10417 int Lane1Cond = -1, Lane2Cond = -1;
10418 if (isa<ConstantSDNode>(EltCond))
10419 Lane1Cond = !isZero(EltCond);
10420 if (isa<ConstantSDNode>(SndLaneEltCond))
10421 Lane2Cond = !isZero(SndLaneEltCond);
10423 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10424 // Lane1Cond != 0, means we want the first argument.
10425 // Lane1Cond == 0, means we want the second argument.
10426 // The encoding of this argument is 0 for the first argument, 1
10427 // for the second. Therefore, invert the condition.
10428 MaskValue |= !Lane1Cond << i;
10429 else if (Lane1Cond < 0)
10430 MaskValue |= !Lane2Cond << i;
10437 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10438 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10439 const X86Subtarget *Subtarget,
10440 SelectionDAG &DAG) {
10441 SDValue Cond = Op.getOperand(0);
10442 SDValue LHS = Op.getOperand(1);
10443 SDValue RHS = Op.getOperand(2);
10445 MVT VT = Op.getSimpleValueType();
10447 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10449 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10451 // Only non-legal VSELECTs reach this lowering, convert those into generic
10452 // shuffles and re-use the shuffle lowering path for blends.
10453 SmallVector<int, 32> Mask;
10454 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10455 SDValue CondElt = CondBV->getOperand(i);
10457 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10459 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10462 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10463 // A vselect where all conditions and data are constants can be optimized into
10464 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10465 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10466 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10467 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10470 // Try to lower this to a blend-style vector shuffle. This can handle all
10471 // constant condition cases.
10472 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10475 // Variable blends are only legal from SSE4.1 onward.
10476 if (!Subtarget->hasSSE41())
10479 // Only some types will be legal on some subtargets. If we can emit a legal
10480 // VSELECT-matching blend, return Op, and but if we need to expand, return
10482 switch (Op.getSimpleValueType().SimpleTy) {
10484 // Most of the vector types have blends past SSE4.1.
10488 // The byte blends for AVX vectors were introduced only in AVX2.
10489 if (Subtarget->hasAVX2())
10496 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10497 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10500 // FIXME: We should custom lower this by fixing the condition and using i8
10506 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10507 MVT VT = Op.getSimpleValueType();
10510 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10513 if (VT.getSizeInBits() == 8) {
10514 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10515 Op.getOperand(0), Op.getOperand(1));
10516 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10517 DAG.getValueType(VT));
10518 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10521 if (VT.getSizeInBits() == 16) {
10522 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10523 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10525 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10526 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10527 DAG.getNode(ISD::BITCAST, dl,
10530 Op.getOperand(1)));
10531 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10532 Op.getOperand(0), Op.getOperand(1));
10533 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10534 DAG.getValueType(VT));
10535 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10538 if (VT == MVT::f32) {
10539 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10540 // the result back to FR32 register. It's only worth matching if the
10541 // result has a single use which is a store or a bitcast to i32. And in
10542 // the case of a store, it's not worth it if the index is a constant 0,
10543 // because a MOVSSmr can be used instead, which is smaller and faster.
10544 if (!Op.hasOneUse())
10546 SDNode *User = *Op.getNode()->use_begin();
10547 if ((User->getOpcode() != ISD::STORE ||
10548 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10549 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10550 (User->getOpcode() != ISD::BITCAST ||
10551 User->getValueType(0) != MVT::i32))
10553 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10554 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10557 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10560 if (VT == MVT::i32 || VT == MVT::i64) {
10561 // ExtractPS/pextrq works with constant index.
10562 if (isa<ConstantSDNode>(Op.getOperand(1)))
10568 /// Extract one bit from mask vector, like v16i1 or v8i1.
10569 /// AVX-512 feature.
10571 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10572 SDValue Vec = Op.getOperand(0);
10574 MVT VecVT = Vec.getSimpleValueType();
10575 SDValue Idx = Op.getOperand(1);
10576 MVT EltVT = Op.getSimpleValueType();
10578 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10579 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10580 "Unexpected vector type in ExtractBitFromMaskVector");
10582 // variable index can't be handled in mask registers,
10583 // extend vector to VR512
10584 if (!isa<ConstantSDNode>(Idx)) {
10585 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10586 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10587 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10588 ExtVT.getVectorElementType(), Ext, Idx);
10589 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10592 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10593 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10594 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10595 rc = getRegClassFor(MVT::v16i1);
10596 unsigned MaxSift = rc->getSize()*8 - 1;
10597 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10598 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10599 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10600 DAG.getConstant(MaxSift, dl, MVT::i8));
10601 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10602 DAG.getIntPtrConstant(0, dl));
10606 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10607 SelectionDAG &DAG) const {
10609 SDValue Vec = Op.getOperand(0);
10610 MVT VecVT = Vec.getSimpleValueType();
10611 SDValue Idx = Op.getOperand(1);
10613 if (Op.getSimpleValueType() == MVT::i1)
10614 return ExtractBitFromMaskVector(Op, DAG);
10616 if (!isa<ConstantSDNode>(Idx)) {
10617 if (VecVT.is512BitVector() ||
10618 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10619 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10622 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10623 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10624 MaskEltVT.getSizeInBits());
10626 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10627 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10628 getZeroVector(MaskVT, Subtarget, DAG, dl),
10629 Idx, DAG.getConstant(0, dl, getPointerTy()));
10630 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10631 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10632 Perm, DAG.getConstant(0, dl, getPointerTy()));
10637 // If this is a 256-bit vector result, first extract the 128-bit vector and
10638 // then extract the element from the 128-bit vector.
10639 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10641 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10642 // Get the 128-bit vector.
10643 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10644 MVT EltVT = VecVT.getVectorElementType();
10646 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10648 //if (IdxVal >= NumElems/2)
10649 // IdxVal -= NumElems/2;
10650 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10651 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10652 DAG.getConstant(IdxVal, dl, MVT::i32));
10655 assert(VecVT.is128BitVector() && "Unexpected vector length");
10657 if (Subtarget->hasSSE41()) {
10658 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10663 MVT VT = Op.getSimpleValueType();
10664 // TODO: handle v16i8.
10665 if (VT.getSizeInBits() == 16) {
10666 SDValue Vec = Op.getOperand(0);
10667 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10669 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10670 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10671 DAG.getNode(ISD::BITCAST, dl,
10673 Op.getOperand(1)));
10674 // Transform it so it match pextrw which produces a 32-bit result.
10675 MVT EltVT = MVT::i32;
10676 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10677 Op.getOperand(0), Op.getOperand(1));
10678 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10679 DAG.getValueType(VT));
10680 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10683 if (VT.getSizeInBits() == 32) {
10684 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10688 // SHUFPS the element to the lowest double word, then movss.
10689 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10690 MVT VVT = Op.getOperand(0).getSimpleValueType();
10691 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10692 DAG.getUNDEF(VVT), Mask);
10693 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10694 DAG.getIntPtrConstant(0, dl));
10697 if (VT.getSizeInBits() == 64) {
10698 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10699 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10700 // to match extract_elt for f64.
10701 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10705 // UNPCKHPD the element to the lowest double word, then movsd.
10706 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10707 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10708 int Mask[2] = { 1, -1 };
10709 MVT VVT = Op.getOperand(0).getSimpleValueType();
10710 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10711 DAG.getUNDEF(VVT), Mask);
10712 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10713 DAG.getIntPtrConstant(0, dl));
10719 /// Insert one bit to mask vector, like v16i1 or v8i1.
10720 /// AVX-512 feature.
10722 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10724 SDValue Vec = Op.getOperand(0);
10725 SDValue Elt = Op.getOperand(1);
10726 SDValue Idx = Op.getOperand(2);
10727 MVT VecVT = Vec.getSimpleValueType();
10729 if (!isa<ConstantSDNode>(Idx)) {
10730 // Non constant index. Extend source and destination,
10731 // insert element and then truncate the result.
10732 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10733 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10734 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10735 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10736 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10737 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10740 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10741 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10743 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10744 DAG.getConstant(IdxVal, dl, MVT::i8));
10745 if (Vec.getOpcode() == ISD::UNDEF)
10747 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10750 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10751 SelectionDAG &DAG) const {
10752 MVT VT = Op.getSimpleValueType();
10753 MVT EltVT = VT.getVectorElementType();
10755 if (EltVT == MVT::i1)
10756 return InsertBitToMaskVector(Op, DAG);
10759 SDValue N0 = Op.getOperand(0);
10760 SDValue N1 = Op.getOperand(1);
10761 SDValue N2 = Op.getOperand(2);
10762 if (!isa<ConstantSDNode>(N2))
10764 auto *N2C = cast<ConstantSDNode>(N2);
10765 unsigned IdxVal = N2C->getZExtValue();
10767 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10768 // into that, and then insert the subvector back into the result.
10769 if (VT.is256BitVector() || VT.is512BitVector()) {
10770 // With a 256-bit vector, we can insert into the zero element efficiently
10771 // using a blend if we have AVX or AVX2 and the right data type.
10772 if (VT.is256BitVector() && IdxVal == 0) {
10773 // TODO: It is worthwhile to cast integer to floating point and back
10774 // and incur a domain crossing penalty if that's what we'll end up
10775 // doing anyway after extracting to a 128-bit vector.
10776 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10777 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10778 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10779 N2 = DAG.getIntPtrConstant(1, dl);
10780 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10784 // Get the desired 128-bit vector chunk.
10785 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10787 // Insert the element into the desired chunk.
10788 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10789 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10791 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10792 DAG.getConstant(IdxIn128, dl, MVT::i32));
10794 // Insert the changed part back into the bigger vector
10795 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10797 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10799 if (Subtarget->hasSSE41()) {
10800 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10802 if (VT == MVT::v8i16) {
10803 Opc = X86ISD::PINSRW;
10805 assert(VT == MVT::v16i8);
10806 Opc = X86ISD::PINSRB;
10809 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10811 if (N1.getValueType() != MVT::i32)
10812 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10813 if (N2.getValueType() != MVT::i32)
10814 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10815 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10818 if (EltVT == MVT::f32) {
10819 // Bits [7:6] of the constant are the source select. This will always be
10820 // zero here. The DAG Combiner may combine an extract_elt index into
10821 // these bits. For example (insert (extract, 3), 2) could be matched by
10822 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10823 // Bits [5:4] of the constant are the destination select. This is the
10824 // value of the incoming immediate.
10825 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10826 // combine either bitwise AND or insert of float 0.0 to set these bits.
10828 const Function *F = DAG.getMachineFunction().getFunction();
10829 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10830 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10831 // If this is an insertion of 32-bits into the low 32-bits of
10832 // a vector, we prefer to generate a blend with immediate rather
10833 // than an insertps. Blends are simpler operations in hardware and so
10834 // will always have equal or better performance than insertps.
10835 // But if optimizing for size and there's a load folding opportunity,
10836 // generate insertps because blendps does not have a 32-bit memory
10838 N2 = DAG.getIntPtrConstant(1, dl);
10839 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10840 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10842 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10843 // Create this as a scalar to vector..
10844 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10845 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10848 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10849 // PINSR* works with constant index.
10854 if (EltVT == MVT::i8)
10857 if (EltVT.getSizeInBits() == 16) {
10858 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10859 // as its second argument.
10860 if (N1.getValueType() != MVT::i32)
10861 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10862 if (N2.getValueType() != MVT::i32)
10863 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10864 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10869 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10871 MVT OpVT = Op.getSimpleValueType();
10873 // If this is a 256-bit vector result, first insert into a 128-bit
10874 // vector and then insert into the 256-bit vector.
10875 if (!OpVT.is128BitVector()) {
10876 // Insert into a 128-bit vector.
10877 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10878 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10879 OpVT.getVectorNumElements() / SizeFactor);
10881 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10883 // Insert the 128-bit vector.
10884 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10887 if (OpVT == MVT::v1i64 &&
10888 Op.getOperand(0).getValueType() == MVT::i64)
10889 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10891 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10892 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10893 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10894 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10897 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10898 // a simple subregister reference or explicit instructions to grab
10899 // upper bits of a vector.
10900 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10901 SelectionDAG &DAG) {
10903 SDValue In = Op.getOperand(0);
10904 SDValue Idx = Op.getOperand(1);
10905 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10906 MVT ResVT = Op.getSimpleValueType();
10907 MVT InVT = In.getSimpleValueType();
10909 if (Subtarget->hasFp256()) {
10910 if (ResVT.is128BitVector() &&
10911 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10912 isa<ConstantSDNode>(Idx)) {
10913 return Extract128BitVector(In, IdxVal, DAG, dl);
10915 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10916 isa<ConstantSDNode>(Idx)) {
10917 return Extract256BitVector(In, IdxVal, DAG, dl);
10923 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10924 // simple superregister reference or explicit instructions to insert
10925 // the upper bits of a vector.
10926 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10927 SelectionDAG &DAG) {
10928 if (!Subtarget->hasAVX())
10932 SDValue Vec = Op.getOperand(0);
10933 SDValue SubVec = Op.getOperand(1);
10934 SDValue Idx = Op.getOperand(2);
10936 if (!isa<ConstantSDNode>(Idx))
10939 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10940 MVT OpVT = Op.getSimpleValueType();
10941 MVT SubVecVT = SubVec.getSimpleValueType();
10943 // Fold two 16-byte subvector loads into one 32-byte load:
10944 // (insert_subvector (insert_subvector undef, (load addr), 0),
10945 // (load addr + 16), Elts/2)
10947 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10948 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10949 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10950 !Subtarget->isUnalignedMem32Slow()) {
10951 SDValue SubVec2 = Vec.getOperand(1);
10952 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10953 if (Idx2->getZExtValue() == 0) {
10954 SDValue Ops[] = { SubVec2, SubVec };
10955 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10962 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10963 SubVecVT.is128BitVector())
10964 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10966 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10967 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10969 if (OpVT.getVectorElementType() == MVT::i1) {
10970 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10972 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10973 SDValue Undef = DAG.getUNDEF(OpVT);
10974 unsigned NumElems = OpVT.getVectorNumElements();
10975 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10977 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10978 // Zero upper bits of the Vec
10979 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10980 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10982 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10984 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10985 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10988 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10990 // Zero upper bits of the Vec2
10991 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10992 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10993 // Zero lower bits of the Vec
10994 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10995 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10996 // Merge them together
10997 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11003 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11004 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11005 // one of the above mentioned nodes. It has to be wrapped because otherwise
11006 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11007 // be used to form addressing mode. These wrapped nodes will be selected
11010 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11011 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11013 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11014 // global base reg.
11015 unsigned char OpFlag = 0;
11016 unsigned WrapperKind = X86ISD::Wrapper;
11017 CodeModel::Model M = DAG.getTarget().getCodeModel();
11019 if (Subtarget->isPICStyleRIPRel() &&
11020 (M == CodeModel::Small || M == CodeModel::Kernel))
11021 WrapperKind = X86ISD::WrapperRIP;
11022 else if (Subtarget->isPICStyleGOT())
11023 OpFlag = X86II::MO_GOTOFF;
11024 else if (Subtarget->isPICStyleStubPIC())
11025 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11027 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11028 CP->getAlignment(),
11029 CP->getOffset(), OpFlag);
11031 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11032 // With PIC, the address is actually $g + Offset.
11034 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11035 DAG.getNode(X86ISD::GlobalBaseReg,
11036 SDLoc(), getPointerTy()),
11043 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11044 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11046 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11047 // global base reg.
11048 unsigned char OpFlag = 0;
11049 unsigned WrapperKind = X86ISD::Wrapper;
11050 CodeModel::Model M = DAG.getTarget().getCodeModel();
11052 if (Subtarget->isPICStyleRIPRel() &&
11053 (M == CodeModel::Small || M == CodeModel::Kernel))
11054 WrapperKind = X86ISD::WrapperRIP;
11055 else if (Subtarget->isPICStyleGOT())
11056 OpFlag = X86II::MO_GOTOFF;
11057 else if (Subtarget->isPICStyleStubPIC())
11058 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11060 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11063 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11065 // With PIC, the address is actually $g + Offset.
11067 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11068 DAG.getNode(X86ISD::GlobalBaseReg,
11069 SDLoc(), getPointerTy()),
11076 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11077 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11079 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11080 // global base reg.
11081 unsigned char OpFlag = 0;
11082 unsigned WrapperKind = X86ISD::Wrapper;
11083 CodeModel::Model M = DAG.getTarget().getCodeModel();
11085 if (Subtarget->isPICStyleRIPRel() &&
11086 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11087 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11088 OpFlag = X86II::MO_GOTPCREL;
11089 WrapperKind = X86ISD::WrapperRIP;
11090 } else if (Subtarget->isPICStyleGOT()) {
11091 OpFlag = X86II::MO_GOT;
11092 } else if (Subtarget->isPICStyleStubPIC()) {
11093 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11094 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11095 OpFlag = X86II::MO_DARWIN_NONLAZY;
11098 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11101 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11103 // With PIC, the address is actually $g + Offset.
11104 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11105 !Subtarget->is64Bit()) {
11106 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11107 DAG.getNode(X86ISD::GlobalBaseReg,
11108 SDLoc(), getPointerTy()),
11112 // For symbols that require a load from a stub to get the address, emit the
11114 if (isGlobalStubReference(OpFlag))
11115 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11116 MachinePointerInfo::getGOT(), false, false, false, 0);
11122 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11123 // Create the TargetBlockAddressAddress node.
11124 unsigned char OpFlags =
11125 Subtarget->ClassifyBlockAddressReference();
11126 CodeModel::Model M = DAG.getTarget().getCodeModel();
11127 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11128 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11130 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11133 if (Subtarget->isPICStyleRIPRel() &&
11134 (M == CodeModel::Small || M == CodeModel::Kernel))
11135 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11137 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11139 // With PIC, the address is actually $g + Offset.
11140 if (isGlobalRelativeToPICBase(OpFlags)) {
11141 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11142 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11150 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11151 int64_t Offset, SelectionDAG &DAG) const {
11152 // Create the TargetGlobalAddress node, folding in the constant
11153 // offset if it is legal.
11154 unsigned char OpFlags =
11155 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11156 CodeModel::Model M = DAG.getTarget().getCodeModel();
11158 if (OpFlags == X86II::MO_NO_FLAG &&
11159 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11160 // A direct static reference to a global.
11161 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11164 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11167 if (Subtarget->isPICStyleRIPRel() &&
11168 (M == CodeModel::Small || M == CodeModel::Kernel))
11169 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11171 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11173 // With PIC, the address is actually $g + Offset.
11174 if (isGlobalRelativeToPICBase(OpFlags)) {
11175 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11176 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11180 // For globals that require a load from a stub to get the address, emit the
11182 if (isGlobalStubReference(OpFlags))
11183 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11184 MachinePointerInfo::getGOT(), false, false, false, 0);
11186 // If there was a non-zero offset that we didn't fold, create an explicit
11187 // addition for it.
11189 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11190 DAG.getConstant(Offset, dl, getPointerTy()));
11196 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11197 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11198 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11199 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11203 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11204 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11205 unsigned char OperandFlags, bool LocalDynamic = false) {
11206 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11207 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11209 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11210 GA->getValueType(0),
11214 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11218 SDValue Ops[] = { Chain, TGA, *InFlag };
11219 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11221 SDValue Ops[] = { Chain, TGA };
11222 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11225 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11226 MFI->setAdjustsStack(true);
11227 MFI->setHasCalls(true);
11229 SDValue Flag = Chain.getValue(1);
11230 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11233 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11235 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11238 SDLoc dl(GA); // ? function entry point might be better
11239 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11240 DAG.getNode(X86ISD::GlobalBaseReg,
11241 SDLoc(), PtrVT), InFlag);
11242 InFlag = Chain.getValue(1);
11244 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11247 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11249 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11251 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11252 X86::RAX, X86II::MO_TLSGD);
11255 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11261 // Get the start address of the TLS block for this module.
11262 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11263 .getInfo<X86MachineFunctionInfo>();
11264 MFI->incNumLocalDynamicTLSAccesses();
11268 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11269 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11272 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11273 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11274 InFlag = Chain.getValue(1);
11275 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11276 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11279 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11283 unsigned char OperandFlags = X86II::MO_DTPOFF;
11284 unsigned WrapperKind = X86ISD::Wrapper;
11285 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11286 GA->getValueType(0),
11287 GA->getOffset(), OperandFlags);
11288 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11290 // Add x@dtpoff with the base.
11291 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11294 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11295 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11296 const EVT PtrVT, TLSModel::Model model,
11297 bool is64Bit, bool isPIC) {
11300 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11301 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11302 is64Bit ? 257 : 256));
11304 SDValue ThreadPointer =
11305 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11306 MachinePointerInfo(Ptr), false, false, false, 0);
11308 unsigned char OperandFlags = 0;
11309 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11311 unsigned WrapperKind = X86ISD::Wrapper;
11312 if (model == TLSModel::LocalExec) {
11313 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11314 } else if (model == TLSModel::InitialExec) {
11316 OperandFlags = X86II::MO_GOTTPOFF;
11317 WrapperKind = X86ISD::WrapperRIP;
11319 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11322 llvm_unreachable("Unexpected model");
11325 // emit "addl x@ntpoff,%eax" (local exec)
11326 // or "addl x@indntpoff,%eax" (initial exec)
11327 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11329 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11330 GA->getOffset(), OperandFlags);
11331 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11333 if (model == TLSModel::InitialExec) {
11334 if (isPIC && !is64Bit) {
11335 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11336 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11340 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11341 MachinePointerInfo::getGOT(), false, false, false, 0);
11344 // The address of the thread local variable is the add of the thread
11345 // pointer with the offset of the variable.
11346 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11350 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11352 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11353 const GlobalValue *GV = GA->getGlobal();
11355 if (Subtarget->isTargetELF()) {
11356 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11358 case TLSModel::GeneralDynamic:
11359 if (Subtarget->is64Bit())
11360 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11361 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11362 case TLSModel::LocalDynamic:
11363 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11364 Subtarget->is64Bit());
11365 case TLSModel::InitialExec:
11366 case TLSModel::LocalExec:
11367 return LowerToTLSExecModel(
11368 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11369 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11371 llvm_unreachable("Unknown TLS model.");
11374 if (Subtarget->isTargetDarwin()) {
11375 // Darwin only has one model of TLS. Lower to that.
11376 unsigned char OpFlag = 0;
11377 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11378 X86ISD::WrapperRIP : X86ISD::Wrapper;
11380 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11381 // global base reg.
11382 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11383 !Subtarget->is64Bit();
11385 OpFlag = X86II::MO_TLVP_PIC_BASE;
11387 OpFlag = X86II::MO_TLVP;
11389 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11390 GA->getValueType(0),
11391 GA->getOffset(), OpFlag);
11392 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11394 // With PIC32, the address is actually $g + Offset.
11396 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11397 DAG.getNode(X86ISD::GlobalBaseReg,
11398 SDLoc(), getPointerTy()),
11401 // Lowering the machine isd will make sure everything is in the right
11403 SDValue Chain = DAG.getEntryNode();
11404 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11405 SDValue Args[] = { Chain, Offset };
11406 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11408 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11409 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11410 MFI->setAdjustsStack(true);
11412 // And our return value (tls address) is in the standard call return value
11414 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11415 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11416 Chain.getValue(1));
11419 if (Subtarget->isTargetKnownWindowsMSVC() ||
11420 Subtarget->isTargetWindowsGNU()) {
11421 // Just use the implicit TLS architecture
11422 // Need to generate someting similar to:
11423 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11425 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11426 // mov rcx, qword [rdx+rcx*8]
11427 // mov eax, .tls$:tlsvar
11428 // [rax+rcx] contains the address
11429 // Windows 64bit: gs:0x58
11430 // Windows 32bit: fs:__tls_array
11433 SDValue Chain = DAG.getEntryNode();
11435 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11436 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11437 // use its literal value of 0x2C.
11438 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11439 ? Type::getInt8PtrTy(*DAG.getContext(),
11441 : Type::getInt32PtrTy(*DAG.getContext(),
11445 Subtarget->is64Bit()
11446 ? DAG.getIntPtrConstant(0x58, dl)
11447 : (Subtarget->isTargetWindowsGNU()
11448 ? DAG.getIntPtrConstant(0x2C, dl)
11449 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11451 SDValue ThreadPointer =
11452 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11453 MachinePointerInfo(Ptr), false, false, false, 0);
11456 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11457 res = ThreadPointer;
11459 // Load the _tls_index variable
11460 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11461 if (Subtarget->is64Bit())
11462 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11463 MachinePointerInfo(), MVT::i32, false, false,
11466 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11467 false, false, false, 0);
11469 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11471 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11473 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11476 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11477 false, false, false, 0);
11479 // Get the offset of start of .tls section
11480 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11481 GA->getValueType(0),
11482 GA->getOffset(), X86II::MO_SECREL);
11483 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11485 // The address of the thread local variable is the add of the thread
11486 // pointer with the offset of the variable.
11487 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11490 llvm_unreachable("TLS not implemented for this target.");
11493 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11494 /// and take a 2 x i32 value to shift plus a shift amount.
11495 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11496 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11497 MVT VT = Op.getSimpleValueType();
11498 unsigned VTBits = VT.getSizeInBits();
11500 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11501 SDValue ShOpLo = Op.getOperand(0);
11502 SDValue ShOpHi = Op.getOperand(1);
11503 SDValue ShAmt = Op.getOperand(2);
11504 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11505 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11507 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11508 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11509 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11510 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11511 : DAG.getConstant(0, dl, VT);
11513 SDValue Tmp2, Tmp3;
11514 if (Op.getOpcode() == ISD::SHL_PARTS) {
11515 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11516 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11518 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11519 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11522 // If the shift amount is larger or equal than the width of a part we can't
11523 // rely on the results of shld/shrd. Insert a test and select the appropriate
11524 // values for large shift amounts.
11525 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11526 DAG.getConstant(VTBits, dl, MVT::i8));
11527 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11528 AndNode, DAG.getConstant(0, dl, MVT::i8));
11531 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11532 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11533 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11535 if (Op.getOpcode() == ISD::SHL_PARTS) {
11536 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11537 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11539 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11540 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11543 SDValue Ops[2] = { Lo, Hi };
11544 return DAG.getMergeValues(Ops, dl);
11547 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11548 SelectionDAG &DAG) const {
11549 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11552 if (SrcVT.isVector()) {
11553 if (SrcVT.getVectorElementType() == MVT::i1) {
11554 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11555 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11556 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11557 Op.getOperand(0)));
11562 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11563 "Unknown SINT_TO_FP to lower!");
11565 // These are really Legal; return the operand so the caller accepts it as
11567 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11569 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11570 Subtarget->is64Bit()) {
11574 unsigned Size = SrcVT.getSizeInBits()/8;
11575 MachineFunction &MF = DAG.getMachineFunction();
11576 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11577 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11578 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11580 MachinePointerInfo::getFixedStack(SSFI),
11582 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11585 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11587 SelectionDAG &DAG) const {
11591 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11593 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11595 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11597 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11599 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11600 MachineMemOperand *MMO;
11602 int SSFI = FI->getIndex();
11604 DAG.getMachineFunction()
11605 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11606 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11608 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11609 StackSlot = StackSlot.getOperand(1);
11611 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11612 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11614 Tys, Ops, SrcVT, MMO);
11617 Chain = Result.getValue(1);
11618 SDValue InFlag = Result.getValue(2);
11620 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11621 // shouldn't be necessary except that RFP cannot be live across
11622 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11623 MachineFunction &MF = DAG.getMachineFunction();
11624 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11625 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11626 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11627 Tys = DAG.getVTList(MVT::Other);
11629 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11631 MachineMemOperand *MMO =
11632 DAG.getMachineFunction()
11633 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11634 MachineMemOperand::MOStore, SSFISize, SSFISize);
11636 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11637 Ops, Op.getValueType(), MMO);
11638 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11639 MachinePointerInfo::getFixedStack(SSFI),
11640 false, false, false, 0);
11646 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11647 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11648 SelectionDAG &DAG) const {
11649 // This algorithm is not obvious. Here it is what we're trying to output:
11652 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11653 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11655 haddpd %xmm0, %xmm0
11657 pshufd $0x4e, %xmm0, %xmm1
11663 LLVMContext *Context = DAG.getContext();
11665 // Build some magic constants.
11666 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11667 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11668 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11670 SmallVector<Constant*,2> CV1;
11672 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11673 APInt(64, 0x4330000000000000ULL))));
11675 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11676 APInt(64, 0x4530000000000000ULL))));
11677 Constant *C1 = ConstantVector::get(CV1);
11678 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11680 // Load the 64-bit value into an XMM register.
11681 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11683 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11684 MachinePointerInfo::getConstantPool(),
11685 false, false, false, 16);
11686 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11687 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11690 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11691 MachinePointerInfo::getConstantPool(),
11692 false, false, false, 16);
11693 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11694 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11697 if (Subtarget->hasSSE3()) {
11698 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11699 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11701 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11702 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11704 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11705 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11709 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11710 DAG.getIntPtrConstant(0, dl));
11713 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11714 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11715 SelectionDAG &DAG) const {
11717 // FP constant to bias correct the final result.
11718 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11721 // Load the 32-bit value into an XMM register.
11722 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11725 // Zero out the upper parts of the register.
11726 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11728 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11729 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11730 DAG.getIntPtrConstant(0, dl));
11732 // Or the load with the bias.
11733 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11734 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11735 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11736 MVT::v2f64, Load)),
11737 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11738 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11739 MVT::v2f64, Bias)));
11740 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11741 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11742 DAG.getIntPtrConstant(0, dl));
11744 // Subtract the bias.
11745 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11747 // Handle final rounding.
11748 EVT DestVT = Op.getValueType();
11750 if (DestVT.bitsLT(MVT::f64))
11751 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11752 DAG.getIntPtrConstant(0, dl));
11753 if (DestVT.bitsGT(MVT::f64))
11754 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11756 // Handle final rounding.
11760 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11761 const X86Subtarget &Subtarget) {
11762 // The algorithm is the following:
11763 // #ifdef __SSE4_1__
11764 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11765 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11766 // (uint4) 0x53000000, 0xaa);
11768 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11769 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11771 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11772 // return (float4) lo + fhi;
11775 SDValue V = Op->getOperand(0);
11776 EVT VecIntVT = V.getValueType();
11777 bool Is128 = VecIntVT == MVT::v4i32;
11778 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11779 // If we convert to something else than the supported type, e.g., to v4f64,
11781 if (VecFloatVT != Op->getValueType(0))
11784 unsigned NumElts = VecIntVT.getVectorNumElements();
11785 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11786 "Unsupported custom type");
11787 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11789 // In the #idef/#else code, we have in common:
11790 // - The vector of constants:
11796 // Create the splat vector for 0x4b000000.
11797 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11798 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11799 CstLow, CstLow, CstLow, CstLow};
11800 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11801 makeArrayRef(&CstLowArray[0], NumElts));
11802 // Create the splat vector for 0x53000000.
11803 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11804 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11805 CstHigh, CstHigh, CstHigh, CstHigh};
11806 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11807 makeArrayRef(&CstHighArray[0], NumElts));
11809 // Create the right shift.
11810 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11811 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11812 CstShift, CstShift, CstShift, CstShift};
11813 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11814 makeArrayRef(&CstShiftArray[0], NumElts));
11815 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11818 if (Subtarget.hasSSE41()) {
11819 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11820 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11821 SDValue VecCstLowBitcast =
11822 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11823 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11824 // Low will be bitcasted right away, so do not bother bitcasting back to its
11826 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11827 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11828 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11829 // (uint4) 0x53000000, 0xaa);
11830 SDValue VecCstHighBitcast =
11831 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11832 SDValue VecShiftBitcast =
11833 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11834 // High will be bitcasted right away, so do not bother bitcasting back to
11835 // its original type.
11836 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11837 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11839 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11840 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11841 CstMask, CstMask, CstMask);
11842 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11843 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11844 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11846 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11847 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11850 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11851 SDValue CstFAdd = DAG.getConstantFP(
11852 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11853 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11854 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11855 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11856 makeArrayRef(&CstFAddArray[0], NumElts));
11858 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11859 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11861 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11862 // return (float4) lo + fhi;
11863 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11864 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11867 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11868 SelectionDAG &DAG) const {
11869 SDValue N0 = Op.getOperand(0);
11870 MVT SVT = N0.getSimpleValueType();
11873 switch (SVT.SimpleTy) {
11875 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11880 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11881 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11882 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11886 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11889 if (Subtarget->hasAVX512())
11890 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11891 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11893 llvm_unreachable(nullptr);
11896 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11897 SelectionDAG &DAG) const {
11898 SDValue N0 = Op.getOperand(0);
11901 if (Op.getValueType().isVector())
11902 return lowerUINT_TO_FP_vec(Op, DAG);
11904 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11905 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11906 // the optimization here.
11907 if (DAG.SignBitIsZero(N0))
11908 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11910 MVT SrcVT = N0.getSimpleValueType();
11911 MVT DstVT = Op.getSimpleValueType();
11912 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11913 return LowerUINT_TO_FP_i64(Op, DAG);
11914 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11915 return LowerUINT_TO_FP_i32(Op, DAG);
11916 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11919 // Make a 64-bit buffer, and use it to build an FILD.
11920 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11921 if (SrcVT == MVT::i32) {
11922 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11923 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11924 getPointerTy(), StackSlot, WordOff);
11925 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11926 StackSlot, MachinePointerInfo(),
11928 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11929 OffsetSlot, MachinePointerInfo(),
11931 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11935 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11936 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11937 StackSlot, MachinePointerInfo(),
11939 // For i64 source, we need to add the appropriate power of 2 if the input
11940 // was negative. This is the same as the optimization in
11941 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11942 // we must be careful to do the computation in x87 extended precision, not
11943 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11944 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11945 MachineMemOperand *MMO =
11946 DAG.getMachineFunction()
11947 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11948 MachineMemOperand::MOLoad, 8, 8);
11950 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11951 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11952 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11955 APInt FF(32, 0x5F800000ULL);
11957 // Check whether the sign bit is set.
11958 SDValue SignSet = DAG.getSetCC(dl,
11959 getSetCCResultType(*DAG.getContext(), MVT::i64),
11961 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11963 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11964 SDValue FudgePtr = DAG.getConstantPool(
11965 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11968 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11969 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11970 SDValue Four = DAG.getIntPtrConstant(4, dl);
11971 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11973 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11975 // Load the value out, extending it from f32 to f80.
11976 // FIXME: Avoid the extend by constructing the right constant pool?
11977 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11978 FudgePtr, MachinePointerInfo::getConstantPool(),
11979 MVT::f32, false, false, false, 4);
11980 // Extend everything to 80 bits to force it to be done on x87.
11981 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11982 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11983 DAG.getIntPtrConstant(0, dl));
11986 std::pair<SDValue,SDValue>
11987 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11988 bool IsSigned, bool IsReplace) const {
11991 EVT DstTy = Op.getValueType();
11993 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11994 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11998 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11999 DstTy.getSimpleVT() >= MVT::i16 &&
12000 "Unknown FP_TO_INT to lower!");
12002 // These are really Legal.
12003 if (DstTy == MVT::i32 &&
12004 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12005 return std::make_pair(SDValue(), SDValue());
12006 if (Subtarget->is64Bit() &&
12007 DstTy == MVT::i64 &&
12008 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12009 return std::make_pair(SDValue(), SDValue());
12011 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12012 // stack slot, or into the FTOL runtime function.
12013 MachineFunction &MF = DAG.getMachineFunction();
12014 unsigned MemSize = DstTy.getSizeInBits()/8;
12015 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12016 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12019 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12020 Opc = X86ISD::WIN_FTOL;
12022 switch (DstTy.getSimpleVT().SimpleTy) {
12023 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12024 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12025 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12026 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12029 SDValue Chain = DAG.getEntryNode();
12030 SDValue Value = Op.getOperand(0);
12031 EVT TheVT = Op.getOperand(0).getValueType();
12032 // FIXME This causes a redundant load/store if the SSE-class value is already
12033 // in memory, such as if it is on the callstack.
12034 if (isScalarFPTypeInSSEReg(TheVT)) {
12035 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12036 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12037 MachinePointerInfo::getFixedStack(SSFI),
12039 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12041 Chain, StackSlot, DAG.getValueType(TheVT)
12044 MachineMemOperand *MMO =
12045 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12046 MachineMemOperand::MOLoad, MemSize, MemSize);
12047 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12048 Chain = Value.getValue(1);
12049 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12050 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12053 MachineMemOperand *MMO =
12054 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12055 MachineMemOperand::MOStore, MemSize, MemSize);
12057 if (Opc != X86ISD::WIN_FTOL) {
12058 // Build the FP_TO_INT*_IN_MEM
12059 SDValue Ops[] = { Chain, Value, StackSlot };
12060 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12062 return std::make_pair(FIST, StackSlot);
12064 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12065 DAG.getVTList(MVT::Other, MVT::Glue),
12067 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12068 MVT::i32, ftol.getValue(1));
12069 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12070 MVT::i32, eax.getValue(2));
12071 SDValue Ops[] = { eax, edx };
12072 SDValue pair = IsReplace
12073 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12074 : DAG.getMergeValues(Ops, DL);
12075 return std::make_pair(pair, SDValue());
12079 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12080 const X86Subtarget *Subtarget) {
12081 MVT VT = Op->getSimpleValueType(0);
12082 SDValue In = Op->getOperand(0);
12083 MVT InVT = In.getSimpleValueType();
12086 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12087 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12089 // Optimize vectors in AVX mode:
12092 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12093 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12094 // Concat upper and lower parts.
12097 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12098 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12099 // Concat upper and lower parts.
12102 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12103 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12104 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12107 if (Subtarget->hasInt256())
12108 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12110 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12111 SDValue Undef = DAG.getUNDEF(InVT);
12112 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12113 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12114 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12116 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12117 VT.getVectorNumElements()/2);
12119 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12120 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12122 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12125 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12126 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12127 MVT VT = Op->getSimpleValueType(0);
12128 SDValue In = Op->getOperand(0);
12129 MVT InVT = In.getSimpleValueType();
12131 unsigned int NumElts = VT.getVectorNumElements();
12132 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12135 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12136 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12138 assert(InVT.getVectorElementType() == MVT::i1);
12139 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12141 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12143 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12145 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12146 if (VT.is512BitVector())
12148 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12151 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12152 SelectionDAG &DAG) {
12153 if (Subtarget->hasFp256()) {
12154 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12162 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12163 SelectionDAG &DAG) {
12165 MVT VT = Op.getSimpleValueType();
12166 SDValue In = Op.getOperand(0);
12167 MVT SVT = In.getSimpleValueType();
12169 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12170 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12172 if (Subtarget->hasFp256()) {
12173 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12178 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12179 VT.getVectorNumElements() != SVT.getVectorNumElements());
12183 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12185 MVT VT = Op.getSimpleValueType();
12186 SDValue In = Op.getOperand(0);
12187 MVT InVT = In.getSimpleValueType();
12189 if (VT == MVT::i1) {
12190 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12191 "Invalid scalar TRUNCATE operation");
12192 if (InVT.getSizeInBits() >= 32)
12194 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12195 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12197 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12198 "Invalid TRUNCATE operation");
12200 // move vector to mask - truncate solution for SKX
12201 if (VT.getVectorElementType() == MVT::i1) {
12202 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12203 Subtarget->hasBWI())
12204 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12205 if ((InVT.is256BitVector() || InVT.is128BitVector())
12206 && InVT.getScalarSizeInBits() <= 16 &&
12207 Subtarget->hasBWI() && Subtarget->hasVLX())
12208 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12209 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12210 Subtarget->hasDQI())
12211 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12212 if ((InVT.is256BitVector() || InVT.is128BitVector())
12213 && InVT.getScalarSizeInBits() >= 32 &&
12214 Subtarget->hasDQI() && Subtarget->hasVLX())
12215 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12217 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12218 if (VT.getVectorElementType().getSizeInBits() >=8)
12219 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12221 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12222 unsigned NumElts = InVT.getVectorNumElements();
12223 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12224 if (InVT.getSizeInBits() < 512) {
12225 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12226 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12231 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12232 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12233 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12236 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12237 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12238 if (Subtarget->hasInt256()) {
12239 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12240 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12241 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12243 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12244 DAG.getIntPtrConstant(0, DL));
12247 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12248 DAG.getIntPtrConstant(0, DL));
12249 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12250 DAG.getIntPtrConstant(2, DL));
12251 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12252 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12253 static const int ShufMask[] = {0, 2, 4, 6};
12254 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12257 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12258 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12259 if (Subtarget->hasInt256()) {
12260 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12262 SmallVector<SDValue,32> pshufbMask;
12263 for (unsigned i = 0; i < 2; ++i) {
12264 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12265 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12266 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12267 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12268 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12269 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12270 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12271 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12272 for (unsigned j = 0; j < 8; ++j)
12273 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12275 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12276 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12277 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12279 static const int ShufMask[] = {0, 2, -1, -1};
12280 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12282 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12283 DAG.getIntPtrConstant(0, DL));
12284 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12287 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12288 DAG.getIntPtrConstant(0, DL));
12290 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12291 DAG.getIntPtrConstant(4, DL));
12293 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12294 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12296 // The PSHUFB mask:
12297 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12298 -1, -1, -1, -1, -1, -1, -1, -1};
12300 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12301 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12302 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12304 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12305 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12307 // The MOVLHPS Mask:
12308 static const int ShufMask2[] = {0, 1, 4, 5};
12309 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12310 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12313 // Handle truncation of V256 to V128 using shuffles.
12314 if (!VT.is128BitVector() || !InVT.is256BitVector())
12317 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12319 unsigned NumElems = VT.getVectorNumElements();
12320 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12322 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12323 // Prepare truncation shuffle mask
12324 for (unsigned i = 0; i != NumElems; ++i)
12325 MaskVec[i] = i * 2;
12326 SDValue V = DAG.getVectorShuffle(NVT, DL,
12327 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12328 DAG.getUNDEF(NVT), &MaskVec[0]);
12329 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12330 DAG.getIntPtrConstant(0, DL));
12333 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12334 SelectionDAG &DAG) const {
12335 assert(!Op.getSimpleValueType().isVector());
12337 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12338 /*IsSigned=*/ true, /*IsReplace=*/ false);
12339 SDValue FIST = Vals.first, StackSlot = Vals.second;
12340 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12341 if (!FIST.getNode()) return Op;
12343 if (StackSlot.getNode())
12344 // Load the result.
12345 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12346 FIST, StackSlot, MachinePointerInfo(),
12347 false, false, false, 0);
12349 // The node is the result.
12353 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12354 SelectionDAG &DAG) const {
12355 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12356 /*IsSigned=*/ false, /*IsReplace=*/ false);
12357 SDValue FIST = Vals.first, StackSlot = Vals.second;
12358 assert(FIST.getNode() && "Unexpected failure");
12360 if (StackSlot.getNode())
12361 // Load the result.
12362 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12363 FIST, StackSlot, MachinePointerInfo(),
12364 false, false, false, 0);
12366 // The node is the result.
12370 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12372 MVT VT = Op.getSimpleValueType();
12373 SDValue In = Op.getOperand(0);
12374 MVT SVT = In.getSimpleValueType();
12376 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12378 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12379 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12380 In, DAG.getUNDEF(SVT)));
12383 /// The only differences between FABS and FNEG are the mask and the logic op.
12384 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12385 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12386 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12387 "Wrong opcode for lowering FABS or FNEG.");
12389 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12391 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12392 // into an FNABS. We'll lower the FABS after that if it is still in use.
12394 for (SDNode *User : Op->uses())
12395 if (User->getOpcode() == ISD::FNEG)
12398 SDValue Op0 = Op.getOperand(0);
12399 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12402 MVT VT = Op.getSimpleValueType();
12403 // Assume scalar op for initialization; update for vector if needed.
12404 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12405 // generate a 16-byte vector constant and logic op even for the scalar case.
12406 // Using a 16-byte mask allows folding the load of the mask with
12407 // the logic op, so it can save (~4 bytes) on code size.
12409 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12410 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12411 // decide if we should generate a 16-byte constant mask when we only need 4 or
12412 // 8 bytes for the scalar case.
12413 if (VT.isVector()) {
12414 EltVT = VT.getVectorElementType();
12415 NumElts = VT.getVectorNumElements();
12418 unsigned EltBits = EltVT.getSizeInBits();
12419 LLVMContext *Context = DAG.getContext();
12420 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12422 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12423 Constant *C = ConstantInt::get(*Context, MaskElt);
12424 C = ConstantVector::getSplat(NumElts, C);
12425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12426 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12427 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12428 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12429 MachinePointerInfo::getConstantPool(),
12430 false, false, false, Alignment);
12432 if (VT.isVector()) {
12433 // For a vector, cast operands to a vector type, perform the logic op,
12434 // and cast the result back to the original value type.
12435 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12436 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12437 SDValue Operand = IsFNABS ?
12438 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12439 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12440 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12441 return DAG.getNode(ISD::BITCAST, dl, VT,
12442 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12445 // If not vector, then scalar.
12446 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12447 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12448 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12451 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12452 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12453 LLVMContext *Context = DAG.getContext();
12454 SDValue Op0 = Op.getOperand(0);
12455 SDValue Op1 = Op.getOperand(1);
12457 MVT VT = Op.getSimpleValueType();
12458 MVT SrcVT = Op1.getSimpleValueType();
12460 // If second operand is smaller, extend it first.
12461 if (SrcVT.bitsLT(VT)) {
12462 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12465 // And if it is bigger, shrink it first.
12466 if (SrcVT.bitsGT(VT)) {
12467 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12471 // At this point the operands and the result should have the same
12472 // type, and that won't be f80 since that is not custom lowered.
12474 const fltSemantics &Sem =
12475 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12476 const unsigned SizeInBits = VT.getSizeInBits();
12478 SmallVector<Constant *, 4> CV(
12479 VT == MVT::f64 ? 2 : 4,
12480 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12482 // First, clear all bits but the sign bit from the second operand (sign).
12483 CV[0] = ConstantFP::get(*Context,
12484 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12485 Constant *C = ConstantVector::get(CV);
12486 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12487 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12488 MachinePointerInfo::getConstantPool(),
12489 false, false, false, 16);
12490 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12492 // Next, clear the sign bit from the first operand (magnitude).
12493 // If it's a constant, we can clear it here.
12494 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12495 APFloat APF = Op0CN->getValueAPF();
12496 // If the magnitude is a positive zero, the sign bit alone is enough.
12497 if (APF.isPosZero())
12500 CV[0] = ConstantFP::get(*Context, APF);
12502 CV[0] = ConstantFP::get(
12504 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12506 C = ConstantVector::get(CV);
12507 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12508 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12509 MachinePointerInfo::getConstantPool(),
12510 false, false, false, 16);
12511 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12512 if (!isa<ConstantFPSDNode>(Op0))
12513 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12515 // OR the magnitude value with the sign bit.
12516 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12519 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12520 SDValue N0 = Op.getOperand(0);
12522 MVT VT = Op.getSimpleValueType();
12524 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12525 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12526 DAG.getConstant(1, dl, VT));
12527 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12530 // Check whether an OR'd tree is PTEST-able.
12531 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12532 SelectionDAG &DAG) {
12533 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12535 if (!Subtarget->hasSSE41())
12538 if (!Op->hasOneUse())
12541 SDNode *N = Op.getNode();
12544 SmallVector<SDValue, 8> Opnds;
12545 DenseMap<SDValue, unsigned> VecInMap;
12546 SmallVector<SDValue, 8> VecIns;
12547 EVT VT = MVT::Other;
12549 // Recognize a special case where a vector is casted into wide integer to
12551 Opnds.push_back(N->getOperand(0));
12552 Opnds.push_back(N->getOperand(1));
12554 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12555 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12556 // BFS traverse all OR'd operands.
12557 if (I->getOpcode() == ISD::OR) {
12558 Opnds.push_back(I->getOperand(0));
12559 Opnds.push_back(I->getOperand(1));
12560 // Re-evaluate the number of nodes to be traversed.
12561 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12565 // Quit if a non-EXTRACT_VECTOR_ELT
12566 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12569 // Quit if without a constant index.
12570 SDValue Idx = I->getOperand(1);
12571 if (!isa<ConstantSDNode>(Idx))
12574 SDValue ExtractedFromVec = I->getOperand(0);
12575 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12576 if (M == VecInMap.end()) {
12577 VT = ExtractedFromVec.getValueType();
12578 // Quit if not 128/256-bit vector.
12579 if (!VT.is128BitVector() && !VT.is256BitVector())
12581 // Quit if not the same type.
12582 if (VecInMap.begin() != VecInMap.end() &&
12583 VT != VecInMap.begin()->first.getValueType())
12585 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12586 VecIns.push_back(ExtractedFromVec);
12588 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12591 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12592 "Not extracted from 128-/256-bit vector.");
12594 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12596 for (DenseMap<SDValue, unsigned>::const_iterator
12597 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12598 // Quit if not all elements are used.
12599 if (I->second != FullMask)
12603 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12605 // Cast all vectors into TestVT for PTEST.
12606 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12607 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12609 // If more than one full vectors are evaluated, OR them first before PTEST.
12610 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12611 // Each iteration will OR 2 nodes and append the result until there is only
12612 // 1 node left, i.e. the final OR'd value of all vectors.
12613 SDValue LHS = VecIns[Slot];
12614 SDValue RHS = VecIns[Slot + 1];
12615 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12618 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12619 VecIns.back(), VecIns.back());
12622 /// \brief return true if \c Op has a use that doesn't just read flags.
12623 static bool hasNonFlagsUse(SDValue Op) {
12624 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12626 SDNode *User = *UI;
12627 unsigned UOpNo = UI.getOperandNo();
12628 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12629 // Look pass truncate.
12630 UOpNo = User->use_begin().getOperandNo();
12631 User = *User->use_begin();
12634 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12635 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12641 /// Emit nodes that will be selected as "test Op0,Op0", or something
12643 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12644 SelectionDAG &DAG) const {
12645 if (Op.getValueType() == MVT::i1) {
12646 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12647 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12648 DAG.getConstant(0, dl, MVT::i8));
12650 // CF and OF aren't always set the way we want. Determine which
12651 // of these we need.
12652 bool NeedCF = false;
12653 bool NeedOF = false;
12656 case X86::COND_A: case X86::COND_AE:
12657 case X86::COND_B: case X86::COND_BE:
12660 case X86::COND_G: case X86::COND_GE:
12661 case X86::COND_L: case X86::COND_LE:
12662 case X86::COND_O: case X86::COND_NO: {
12663 // Check if we really need to set the
12664 // Overflow flag. If NoSignedWrap is present
12665 // that is not actually needed.
12666 switch (Op->getOpcode()) {
12671 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12672 if (BinNode->Flags.hasNoSignedWrap())
12682 // See if we can use the EFLAGS value from the operand instead of
12683 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12684 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12685 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12686 // Emit a CMP with 0, which is the TEST pattern.
12687 //if (Op.getValueType() == MVT::i1)
12688 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12689 // DAG.getConstant(0, MVT::i1));
12690 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12691 DAG.getConstant(0, dl, Op.getValueType()));
12693 unsigned Opcode = 0;
12694 unsigned NumOperands = 0;
12696 // Truncate operations may prevent the merge of the SETCC instruction
12697 // and the arithmetic instruction before it. Attempt to truncate the operands
12698 // of the arithmetic instruction and use a reduced bit-width instruction.
12699 bool NeedTruncation = false;
12700 SDValue ArithOp = Op;
12701 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12702 SDValue Arith = Op->getOperand(0);
12703 // Both the trunc and the arithmetic op need to have one user each.
12704 if (Arith->hasOneUse())
12705 switch (Arith.getOpcode()) {
12712 NeedTruncation = true;
12718 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12719 // which may be the result of a CAST. We use the variable 'Op', which is the
12720 // non-casted variable when we check for possible users.
12721 switch (ArithOp.getOpcode()) {
12723 // Due to an isel shortcoming, be conservative if this add is likely to be
12724 // selected as part of a load-modify-store instruction. When the root node
12725 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12726 // uses of other nodes in the match, such as the ADD in this case. This
12727 // leads to the ADD being left around and reselected, with the result being
12728 // two adds in the output. Alas, even if none our users are stores, that
12729 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12730 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12731 // climbing the DAG back to the root, and it doesn't seem to be worth the
12733 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12734 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12735 if (UI->getOpcode() != ISD::CopyToReg &&
12736 UI->getOpcode() != ISD::SETCC &&
12737 UI->getOpcode() != ISD::STORE)
12740 if (ConstantSDNode *C =
12741 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12742 // An add of one will be selected as an INC.
12743 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12744 Opcode = X86ISD::INC;
12749 // An add of negative one (subtract of one) will be selected as a DEC.
12750 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12751 Opcode = X86ISD::DEC;
12757 // Otherwise use a regular EFLAGS-setting add.
12758 Opcode = X86ISD::ADD;
12763 // If we have a constant logical shift that's only used in a comparison
12764 // against zero turn it into an equivalent AND. This allows turning it into
12765 // a TEST instruction later.
12766 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12767 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12768 EVT VT = Op.getValueType();
12769 unsigned BitWidth = VT.getSizeInBits();
12770 unsigned ShAmt = Op->getConstantOperandVal(1);
12771 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12773 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12774 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12775 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12776 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12778 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12779 DAG.getConstant(Mask, dl, VT));
12780 DAG.ReplaceAllUsesWith(Op, New);
12786 // If the primary and result isn't used, don't bother using X86ISD::AND,
12787 // because a TEST instruction will be better.
12788 if (!hasNonFlagsUse(Op))
12794 // Due to the ISEL shortcoming noted above, be conservative if this op is
12795 // likely to be selected as part of a load-modify-store instruction.
12796 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12797 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12798 if (UI->getOpcode() == ISD::STORE)
12801 // Otherwise use a regular EFLAGS-setting instruction.
12802 switch (ArithOp.getOpcode()) {
12803 default: llvm_unreachable("unexpected operator!");
12804 case ISD::SUB: Opcode = X86ISD::SUB; break;
12805 case ISD::XOR: Opcode = X86ISD::XOR; break;
12806 case ISD::AND: Opcode = X86ISD::AND; break;
12808 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12809 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12810 if (EFLAGS.getNode())
12813 Opcode = X86ISD::OR;
12827 return SDValue(Op.getNode(), 1);
12833 // If we found that truncation is beneficial, perform the truncation and
12835 if (NeedTruncation) {
12836 EVT VT = Op.getValueType();
12837 SDValue WideVal = Op->getOperand(0);
12838 EVT WideVT = WideVal.getValueType();
12839 unsigned ConvertedOp = 0;
12840 // Use a target machine opcode to prevent further DAGCombine
12841 // optimizations that may separate the arithmetic operations
12842 // from the setcc node.
12843 switch (WideVal.getOpcode()) {
12845 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12846 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12847 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12848 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12849 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12854 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12855 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12856 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12857 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12863 // Emit a CMP with 0, which is the TEST pattern.
12864 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12865 DAG.getConstant(0, dl, Op.getValueType()));
12867 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12868 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12870 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12871 DAG.ReplaceAllUsesWith(Op, New);
12872 return SDValue(New.getNode(), 1);
12875 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12877 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12878 SDLoc dl, SelectionDAG &DAG) const {
12879 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12880 if (C->getAPIntValue() == 0)
12881 return EmitTest(Op0, X86CC, dl, DAG);
12883 if (Op0.getValueType() == MVT::i1)
12884 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12887 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12888 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12889 // Do the comparison at i32 if it's smaller, besides the Atom case.
12890 // This avoids subregister aliasing issues. Keep the smaller reference
12891 // if we're optimizing for size, however, as that'll allow better folding
12892 // of memory operations.
12893 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12894 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12895 Attribute::MinSize) &&
12896 !Subtarget->isAtom()) {
12897 unsigned ExtendOp =
12898 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12899 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12900 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12902 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12903 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12904 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12906 return SDValue(Sub.getNode(), 1);
12908 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12911 /// Convert a comparison if required by the subtarget.
12912 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12913 SelectionDAG &DAG) const {
12914 // If the subtarget does not support the FUCOMI instruction, floating-point
12915 // comparisons have to be converted.
12916 if (Subtarget->hasCMov() ||
12917 Cmp.getOpcode() != X86ISD::CMP ||
12918 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12919 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12922 // The instruction selector will select an FUCOM instruction instead of
12923 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12924 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12925 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12927 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12928 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12929 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12930 DAG.getConstant(8, dl, MVT::i8));
12931 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12932 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12935 /// The minimum architected relative accuracy is 2^-12. We need one
12936 /// Newton-Raphson step to have a good float result (24 bits of precision).
12937 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12938 DAGCombinerInfo &DCI,
12939 unsigned &RefinementSteps,
12940 bool &UseOneConstNR) const {
12941 // FIXME: We should use instruction latency models to calculate the cost of
12942 // each potential sequence, but this is very hard to do reliably because
12943 // at least Intel's Core* chips have variable timing based on the number of
12944 // significant digits in the divisor and/or sqrt operand.
12945 if (!Subtarget->useSqrtEst())
12948 EVT VT = Op.getValueType();
12950 // SSE1 has rsqrtss and rsqrtps.
12951 // TODO: Add support for AVX512 (v16f32).
12952 // It is likely not profitable to do this for f64 because a double-precision
12953 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12954 // instructions: convert to single, rsqrtss, convert back to double, refine
12955 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12956 // along with FMA, this could be a throughput win.
12957 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12958 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12959 RefinementSteps = 1;
12960 UseOneConstNR = false;
12961 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12966 /// The minimum architected relative accuracy is 2^-12. We need one
12967 /// Newton-Raphson step to have a good float result (24 bits of precision).
12968 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12969 DAGCombinerInfo &DCI,
12970 unsigned &RefinementSteps) const {
12971 // FIXME: We should use instruction latency models to calculate the cost of
12972 // each potential sequence, but this is very hard to do reliably because
12973 // at least Intel's Core* chips have variable timing based on the number of
12974 // significant digits in the divisor.
12975 if (!Subtarget->useReciprocalEst())
12978 EVT VT = Op.getValueType();
12980 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12981 // TODO: Add support for AVX512 (v16f32).
12982 // It is likely not profitable to do this for f64 because a double-precision
12983 // reciprocal estimate with refinement on x86 prior to FMA requires
12984 // 15 instructions: convert to single, rcpss, convert back to double, refine
12985 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12986 // along with FMA, this could be a throughput win.
12987 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12988 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12989 RefinementSteps = ReciprocalEstimateRefinementSteps;
12990 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12995 /// If we have at least two divisions that use the same divisor, convert to
12996 /// multplication by a reciprocal. This may need to be adjusted for a given
12997 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12998 /// This is because we still need one division to calculate the reciprocal and
12999 /// then we need two multiplies by that reciprocal as replacements for the
13000 /// original divisions.
13001 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13002 return NumUsers > 1;
13005 static bool isAllOnes(SDValue V) {
13006 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13007 return C && C->isAllOnesValue();
13010 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13011 /// if it's possible.
13012 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13013 SDLoc dl, SelectionDAG &DAG) const {
13014 SDValue Op0 = And.getOperand(0);
13015 SDValue Op1 = And.getOperand(1);
13016 if (Op0.getOpcode() == ISD::TRUNCATE)
13017 Op0 = Op0.getOperand(0);
13018 if (Op1.getOpcode() == ISD::TRUNCATE)
13019 Op1 = Op1.getOperand(0);
13022 if (Op1.getOpcode() == ISD::SHL)
13023 std::swap(Op0, Op1);
13024 if (Op0.getOpcode() == ISD::SHL) {
13025 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13026 if (And00C->getZExtValue() == 1) {
13027 // If we looked past a truncate, check that it's only truncating away
13029 unsigned BitWidth = Op0.getValueSizeInBits();
13030 unsigned AndBitWidth = And.getValueSizeInBits();
13031 if (BitWidth > AndBitWidth) {
13033 DAG.computeKnownBits(Op0, Zeros, Ones);
13034 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13038 RHS = Op0.getOperand(1);
13040 } else if (Op1.getOpcode() == ISD::Constant) {
13041 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13042 uint64_t AndRHSVal = AndRHS->getZExtValue();
13043 SDValue AndLHS = Op0;
13045 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13046 LHS = AndLHS.getOperand(0);
13047 RHS = AndLHS.getOperand(1);
13050 // Use BT if the immediate can't be encoded in a TEST instruction.
13051 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13053 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13057 if (LHS.getNode()) {
13058 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13059 // instruction. Since the shift amount is in-range-or-undefined, we know
13060 // that doing a bittest on the i32 value is ok. We extend to i32 because
13061 // the encoding for the i16 version is larger than the i32 version.
13062 // Also promote i16 to i32 for performance / code size reason.
13063 if (LHS.getValueType() == MVT::i8 ||
13064 LHS.getValueType() == MVT::i16)
13065 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13067 // If the operand types disagree, extend the shift amount to match. Since
13068 // BT ignores high bits (like shifts) we can use anyextend.
13069 if (LHS.getValueType() != RHS.getValueType())
13070 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13072 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13073 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13074 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13075 DAG.getConstant(Cond, dl, MVT::i8), BT);
13081 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13083 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13088 // SSE Condition code mapping:
13097 switch (SetCCOpcode) {
13098 default: llvm_unreachable("Unexpected SETCC condition");
13100 case ISD::SETEQ: SSECC = 0; break;
13102 case ISD::SETGT: Swap = true; // Fallthrough
13104 case ISD::SETOLT: SSECC = 1; break;
13106 case ISD::SETGE: Swap = true; // Fallthrough
13108 case ISD::SETOLE: SSECC = 2; break;
13109 case ISD::SETUO: SSECC = 3; break;
13111 case ISD::SETNE: SSECC = 4; break;
13112 case ISD::SETULE: Swap = true; // Fallthrough
13113 case ISD::SETUGE: SSECC = 5; break;
13114 case ISD::SETULT: Swap = true; // Fallthrough
13115 case ISD::SETUGT: SSECC = 6; break;
13116 case ISD::SETO: SSECC = 7; break;
13118 case ISD::SETONE: SSECC = 8; break;
13121 std::swap(Op0, Op1);
13126 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13127 // ones, and then concatenate the result back.
13128 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13129 MVT VT = Op.getSimpleValueType();
13131 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13132 "Unsupported value type for operation");
13134 unsigned NumElems = VT.getVectorNumElements();
13136 SDValue CC = Op.getOperand(2);
13138 // Extract the LHS vectors
13139 SDValue LHS = Op.getOperand(0);
13140 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13141 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13143 // Extract the RHS vectors
13144 SDValue RHS = Op.getOperand(1);
13145 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13146 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13148 // Issue the operation on the smaller types and concatenate the result back
13149 MVT EltVT = VT.getVectorElementType();
13150 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13151 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13152 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13153 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13156 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13157 SDValue Op0 = Op.getOperand(0);
13158 SDValue Op1 = Op.getOperand(1);
13159 SDValue CC = Op.getOperand(2);
13160 MVT VT = Op.getSimpleValueType();
13163 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13164 "Unexpected type for boolean compare operation");
13165 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13166 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13167 DAG.getConstant(-1, dl, VT));
13168 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13169 DAG.getConstant(-1, dl, VT));
13170 switch (SetCCOpcode) {
13171 default: llvm_unreachable("Unexpected SETCC condition");
13173 // (x != y) -> ~(x ^ y)
13174 return DAG.getNode(ISD::XOR, dl, VT,
13175 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13176 DAG.getConstant(-1, dl, VT));
13178 // (x == y) -> (x ^ y)
13179 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13182 // (x > y) -> (x & ~y)
13183 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13186 // (x < y) -> (~x & y)
13187 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13190 // (x <= y) -> (~x | y)
13191 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13194 // (x >=y) -> (x | ~y)
13195 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13199 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13200 const X86Subtarget *Subtarget) {
13201 SDValue Op0 = Op.getOperand(0);
13202 SDValue Op1 = Op.getOperand(1);
13203 SDValue CC = Op.getOperand(2);
13204 MVT VT = Op.getSimpleValueType();
13207 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13208 Op.getValueType().getScalarType() == MVT::i1 &&
13209 "Cannot set masked compare for this operation");
13211 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13213 bool Unsigned = false;
13216 switch (SetCCOpcode) {
13217 default: llvm_unreachable("Unexpected SETCC condition");
13218 case ISD::SETNE: SSECC = 4; break;
13219 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13220 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13221 case ISD::SETLT: Swap = true; //fall-through
13222 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13223 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13224 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13225 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13226 case ISD::SETULE: Unsigned = true; //fall-through
13227 case ISD::SETLE: SSECC = 2; break;
13231 std::swap(Op0, Op1);
13233 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13234 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13235 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13236 DAG.getConstant(SSECC, dl, MVT::i8));
13239 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13240 /// operand \p Op1. If non-trivial (for example because it's not constant)
13241 /// return an empty value.
13242 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13244 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13248 MVT VT = Op1.getSimpleValueType();
13249 MVT EVT = VT.getVectorElementType();
13250 unsigned n = VT.getVectorNumElements();
13251 SmallVector<SDValue, 8> ULTOp1;
13253 for (unsigned i = 0; i < n; ++i) {
13254 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13255 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13258 // Avoid underflow.
13259 APInt Val = Elt->getAPIntValue();
13263 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13266 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13269 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13270 SelectionDAG &DAG) {
13271 SDValue Op0 = Op.getOperand(0);
13272 SDValue Op1 = Op.getOperand(1);
13273 SDValue CC = Op.getOperand(2);
13274 MVT VT = Op.getSimpleValueType();
13275 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13276 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13281 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13282 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13285 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13286 unsigned Opc = X86ISD::CMPP;
13287 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13288 assert(VT.getVectorNumElements() <= 16);
13289 Opc = X86ISD::CMPM;
13291 // In the two special cases we can't handle, emit two comparisons.
13294 unsigned CombineOpc;
13295 if (SetCCOpcode == ISD::SETUEQ) {
13296 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13298 assert(SetCCOpcode == ISD::SETONE);
13299 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13302 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13303 DAG.getConstant(CC0, dl, MVT::i8));
13304 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13305 DAG.getConstant(CC1, dl, MVT::i8));
13306 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13308 // Handle all other FP comparisons here.
13309 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13310 DAG.getConstant(SSECC, dl, MVT::i8));
13313 // Break 256-bit integer vector compare into smaller ones.
13314 if (VT.is256BitVector() && !Subtarget->hasInt256())
13315 return Lower256IntVSETCC(Op, DAG);
13317 EVT OpVT = Op1.getValueType();
13318 if (OpVT.getVectorElementType() == MVT::i1)
13319 return LowerBoolVSETCC_AVX512(Op, DAG);
13321 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13322 if (Subtarget->hasAVX512()) {
13323 if (Op1.getValueType().is512BitVector() ||
13324 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13325 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13326 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13328 // In AVX-512 architecture setcc returns mask with i1 elements,
13329 // But there is no compare instruction for i8 and i16 elements in KNL.
13330 // We are not talking about 512-bit operands in this case, these
13331 // types are illegal.
13333 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13334 OpVT.getVectorElementType().getSizeInBits() >= 8))
13335 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13336 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13339 // We are handling one of the integer comparisons here. Since SSE only has
13340 // GT and EQ comparisons for integer, swapping operands and multiple
13341 // operations may be required for some comparisons.
13343 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13344 bool Subus = false;
13346 switch (SetCCOpcode) {
13347 default: llvm_unreachable("Unexpected SETCC condition");
13348 case ISD::SETNE: Invert = true;
13349 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13350 case ISD::SETLT: Swap = true;
13351 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13352 case ISD::SETGE: Swap = true;
13353 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13354 Invert = true; break;
13355 case ISD::SETULT: Swap = true;
13356 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13357 FlipSigns = true; break;
13358 case ISD::SETUGE: Swap = true;
13359 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13360 FlipSigns = true; Invert = true; break;
13363 // Special case: Use min/max operations for SETULE/SETUGE
13364 MVT VET = VT.getVectorElementType();
13366 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13367 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13370 switch (SetCCOpcode) {
13372 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13373 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13376 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13379 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13380 if (!MinMax && hasSubus) {
13381 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13383 // t = psubus Op0, Op1
13384 // pcmpeq t, <0..0>
13385 switch (SetCCOpcode) {
13387 case ISD::SETULT: {
13388 // If the comparison is against a constant we can turn this into a
13389 // setule. With psubus, setule does not require a swap. This is
13390 // beneficial because the constant in the register is no longer
13391 // destructed as the destination so it can be hoisted out of a loop.
13392 // Only do this pre-AVX since vpcmp* is no longer destructive.
13393 if (Subtarget->hasAVX())
13395 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13396 if (ULEOp1.getNode()) {
13398 Subus = true; Invert = false; Swap = false;
13402 // Psubus is better than flip-sign because it requires no inversion.
13403 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13404 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13408 Opc = X86ISD::SUBUS;
13414 std::swap(Op0, Op1);
13416 // Check that the operation in question is available (most are plain SSE2,
13417 // but PCMPGTQ and PCMPEQQ have different requirements).
13418 if (VT == MVT::v2i64) {
13419 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13420 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13422 // First cast everything to the right type.
13423 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13424 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13426 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13427 // bits of the inputs before performing those operations. The lower
13428 // compare is always unsigned.
13431 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13433 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13434 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13435 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13436 Sign, Zero, Sign, Zero);
13438 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13439 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13441 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13442 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13443 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13445 // Create masks for only the low parts/high parts of the 64 bit integers.
13446 static const int MaskHi[] = { 1, 1, 3, 3 };
13447 static const int MaskLo[] = { 0, 0, 2, 2 };
13448 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13449 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13450 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13452 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13453 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13456 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13458 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13461 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13462 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13463 // pcmpeqd + pshufd + pand.
13464 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13466 // First cast everything to the right type.
13467 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13468 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13471 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13473 // Make sure the lower and upper halves are both all-ones.
13474 static const int Mask[] = { 1, 0, 3, 2 };
13475 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13476 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13479 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13481 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13485 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13486 // bits of the inputs before performing those operations.
13488 EVT EltVT = VT.getVectorElementType();
13489 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13491 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13492 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13495 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13497 // If the logical-not of the result is required, perform that now.
13499 Result = DAG.getNOT(dl, Result, VT);
13502 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13505 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13506 getZeroVector(VT, Subtarget, DAG, dl));
13511 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13513 MVT VT = Op.getSimpleValueType();
13515 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13517 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13518 && "SetCC type must be 8-bit or 1-bit integer");
13519 SDValue Op0 = Op.getOperand(0);
13520 SDValue Op1 = Op.getOperand(1);
13522 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13524 // Optimize to BT if possible.
13525 // Lower (X & (1 << N)) == 0 to BT(X, N).
13526 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13527 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13528 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13529 Op1.getOpcode() == ISD::Constant &&
13530 cast<ConstantSDNode>(Op1)->isNullValue() &&
13531 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13532 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13533 if (NewSetCC.getNode()) {
13535 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13540 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13542 if (Op1.getOpcode() == ISD::Constant &&
13543 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13544 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13545 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13547 // If the input is a setcc, then reuse the input setcc or use a new one with
13548 // the inverted condition.
13549 if (Op0.getOpcode() == X86ISD::SETCC) {
13550 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13551 bool Invert = (CC == ISD::SETNE) ^
13552 cast<ConstantSDNode>(Op1)->isNullValue();
13556 CCode = X86::GetOppositeBranchCondition(CCode);
13557 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13558 DAG.getConstant(CCode, dl, MVT::i8),
13559 Op0.getOperand(1));
13561 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13565 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13566 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13567 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13569 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13570 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13573 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13574 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13575 if (X86CC == X86::COND_INVALID)
13578 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13579 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13580 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13581 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13583 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13587 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13588 static bool isX86LogicalCmp(SDValue Op) {
13589 unsigned Opc = Op.getNode()->getOpcode();
13590 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13591 Opc == X86ISD::SAHF)
13593 if (Op.getResNo() == 1 &&
13594 (Opc == X86ISD::ADD ||
13595 Opc == X86ISD::SUB ||
13596 Opc == X86ISD::ADC ||
13597 Opc == X86ISD::SBB ||
13598 Opc == X86ISD::SMUL ||
13599 Opc == X86ISD::UMUL ||
13600 Opc == X86ISD::INC ||
13601 Opc == X86ISD::DEC ||
13602 Opc == X86ISD::OR ||
13603 Opc == X86ISD::XOR ||
13604 Opc == X86ISD::AND))
13607 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13613 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13614 if (V.getOpcode() != ISD::TRUNCATE)
13617 SDValue VOp0 = V.getOperand(0);
13618 unsigned InBits = VOp0.getValueSizeInBits();
13619 unsigned Bits = V.getValueSizeInBits();
13620 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13623 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13624 bool addTest = true;
13625 SDValue Cond = Op.getOperand(0);
13626 SDValue Op1 = Op.getOperand(1);
13627 SDValue Op2 = Op.getOperand(2);
13629 EVT VT = Op1.getValueType();
13632 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13633 // are available or VBLENDV if AVX is available.
13634 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13635 if (Cond.getOpcode() == ISD::SETCC &&
13636 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13637 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13638 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13639 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13640 int SSECC = translateX86FSETCC(
13641 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13644 if (Subtarget->hasAVX512()) {
13645 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13646 DAG.getConstant(SSECC, DL, MVT::i8));
13647 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13650 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13651 DAG.getConstant(SSECC, DL, MVT::i8));
13653 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13654 // of 3 logic instructions for size savings and potentially speed.
13655 // Unfortunately, there is no scalar form of VBLENDV.
13657 // If either operand is a constant, don't try this. We can expect to
13658 // optimize away at least one of the logic instructions later in that
13659 // case, so that sequence would be faster than a variable blend.
13661 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13662 // uses XMM0 as the selection register. That may need just as many
13663 // instructions as the AND/ANDN/OR sequence due to register moves, so
13666 if (Subtarget->hasAVX() &&
13667 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13669 // Convert to vectors, do a VSELECT, and convert back to scalar.
13670 // All of the conversions should be optimized away.
13672 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13673 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13674 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13675 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13677 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13678 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13680 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13682 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13683 VSel, DAG.getIntPtrConstant(0, DL));
13685 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13686 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13687 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13691 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13693 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13694 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13695 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13696 Op1Scalar = Op1.getOperand(0);
13698 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13699 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13700 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13701 Op2Scalar = Op2.getOperand(0);
13702 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13703 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13704 Op1Scalar.getValueType(),
13705 Cond, Op1Scalar, Op2Scalar);
13706 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13707 return DAG.getNode(ISD::BITCAST, DL, VT, newSelect);
13708 SDValue ExtVec = DAG.getNode(ISD::BITCAST, DL, MVT::v8i1, newSelect);
13709 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13710 DAG.getIntPtrConstant(0, DL));
13714 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13715 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13716 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13717 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13718 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13719 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13720 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13722 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13725 if (Cond.getOpcode() == ISD::SETCC) {
13726 SDValue NewCond = LowerSETCC(Cond, DAG);
13727 if (NewCond.getNode())
13731 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13732 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13733 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13734 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13735 if (Cond.getOpcode() == X86ISD::SETCC &&
13736 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13737 isZero(Cond.getOperand(1).getOperand(1))) {
13738 SDValue Cmp = Cond.getOperand(1);
13740 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13742 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13743 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13744 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13746 SDValue CmpOp0 = Cmp.getOperand(0);
13747 // Apply further optimizations for special cases
13748 // (select (x != 0), -1, 0) -> neg & sbb
13749 // (select (x == 0), 0, -1) -> neg & sbb
13750 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13751 if (YC->isNullValue() &&
13752 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13753 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13754 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13755 DAG.getConstant(0, DL,
13756 CmpOp0.getValueType()),
13758 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13759 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13760 SDValue(Neg.getNode(), 1));
13764 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13765 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13766 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13768 SDValue Res = // Res = 0 or -1.
13769 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13770 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13772 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13773 Res = DAG.getNOT(DL, Res, Res.getValueType());
13775 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13776 if (!N2C || !N2C->isNullValue())
13777 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13782 // Look past (and (setcc_carry (cmp ...)), 1).
13783 if (Cond.getOpcode() == ISD::AND &&
13784 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13785 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13786 if (C && C->getAPIntValue() == 1)
13787 Cond = Cond.getOperand(0);
13790 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13791 // setting operand in place of the X86ISD::SETCC.
13792 unsigned CondOpcode = Cond.getOpcode();
13793 if (CondOpcode == X86ISD::SETCC ||
13794 CondOpcode == X86ISD::SETCC_CARRY) {
13795 CC = Cond.getOperand(0);
13797 SDValue Cmp = Cond.getOperand(1);
13798 unsigned Opc = Cmp.getOpcode();
13799 MVT VT = Op.getSimpleValueType();
13801 bool IllegalFPCMov = false;
13802 if (VT.isFloatingPoint() && !VT.isVector() &&
13803 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13804 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13806 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13807 Opc == X86ISD::BT) { // FIXME
13811 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13812 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13813 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13814 Cond.getOperand(0).getValueType() != MVT::i8)) {
13815 SDValue LHS = Cond.getOperand(0);
13816 SDValue RHS = Cond.getOperand(1);
13817 unsigned X86Opcode;
13820 switch (CondOpcode) {
13821 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13822 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13823 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13824 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13825 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13826 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13827 default: llvm_unreachable("unexpected overflowing operator");
13829 if (CondOpcode == ISD::UMULO)
13830 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13833 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13835 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13837 if (CondOpcode == ISD::UMULO)
13838 Cond = X86Op.getValue(2);
13840 Cond = X86Op.getValue(1);
13842 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13847 // Look pass the truncate if the high bits are known zero.
13848 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13849 Cond = Cond.getOperand(0);
13851 // We know the result of AND is compared against zero. Try to match
13853 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13854 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13855 if (NewSetCC.getNode()) {
13856 CC = NewSetCC.getOperand(0);
13857 Cond = NewSetCC.getOperand(1);
13864 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13865 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13868 // a < b ? -1 : 0 -> RES = ~setcc_carry
13869 // a < b ? 0 : -1 -> RES = setcc_carry
13870 // a >= b ? -1 : 0 -> RES = setcc_carry
13871 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13872 if (Cond.getOpcode() == X86ISD::SUB) {
13873 Cond = ConvertCmpIfNecessary(Cond, DAG);
13874 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13876 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13877 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13878 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13879 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13881 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13882 return DAG.getNOT(DL, Res, Res.getValueType());
13887 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13888 // widen the cmov and push the truncate through. This avoids introducing a new
13889 // branch during isel and doesn't add any extensions.
13890 if (Op.getValueType() == MVT::i8 &&
13891 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13892 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13893 if (T1.getValueType() == T2.getValueType() &&
13894 // Blacklist CopyFromReg to avoid partial register stalls.
13895 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13896 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13897 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13898 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13902 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13903 // condition is true.
13904 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13905 SDValue Ops[] = { Op2, Op1, CC, Cond };
13906 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13909 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
13910 const X86Subtarget *Subtarget,
13911 SelectionDAG &DAG) {
13912 MVT VT = Op->getSimpleValueType(0);
13913 SDValue In = Op->getOperand(0);
13914 MVT InVT = In.getSimpleValueType();
13915 MVT VTElt = VT.getVectorElementType();
13916 MVT InVTElt = InVT.getVectorElementType();
13920 if ((InVTElt == MVT::i1) &&
13921 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13922 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13924 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13925 VTElt.getSizeInBits() <= 16)) ||
13927 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13928 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13930 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13931 VTElt.getSizeInBits() >= 32))))
13932 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13934 unsigned int NumElts = VT.getVectorNumElements();
13936 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13939 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13940 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13941 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13942 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13945 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13946 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13948 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
13951 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
13953 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
13954 if (VT.is512BitVector())
13956 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
13959 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
13960 const X86Subtarget *Subtarget,
13961 SelectionDAG &DAG) {
13962 SDValue In = Op->getOperand(0);
13963 MVT VT = Op->getSimpleValueType(0);
13964 MVT InVT = In.getSimpleValueType();
13965 assert(VT.getSizeInBits() == InVT.getSizeInBits());
13967 MVT InSVT = InVT.getScalarType();
13968 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
13970 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13972 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
13977 // SSE41 targets can use the pmovsx* instructions directly.
13978 if (Subtarget->hasSSE41())
13979 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13981 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
13985 // As SRAI is only available on i16/i32 types, we expand only up to i32
13986 // and handle i64 separately.
13987 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
13988 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
13989 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
13990 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
13991 Curr = DAG.getNode(ISD::BITCAST, dl, CurrVT, Curr);
13994 SDValue SignExt = Curr;
13995 if (CurrVT != InVT) {
13996 unsigned SignExtShift =
13997 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
13998 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
13999 DAG.getConstant(SignExtShift, dl, MVT::i8));
14005 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14006 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14007 DAG.getConstant(31, dl, MVT::i8));
14008 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14009 return DAG.getNode(ISD::BITCAST, dl, VT, Ext);
14015 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14016 SelectionDAG &DAG) {
14017 MVT VT = Op->getSimpleValueType(0);
14018 SDValue In = Op->getOperand(0);
14019 MVT InVT = In.getSimpleValueType();
14022 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14023 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14025 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14026 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14027 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14030 if (Subtarget->hasInt256())
14031 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14033 // Optimize vectors in AVX mode
14034 // Sign extend v8i16 to v8i32 and
14037 // Divide input vector into two parts
14038 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14039 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14040 // concat the vectors to original VT
14042 unsigned NumElems = InVT.getVectorNumElements();
14043 SDValue Undef = DAG.getUNDEF(InVT);
14045 SmallVector<int,8> ShufMask1(NumElems, -1);
14046 for (unsigned i = 0; i != NumElems/2; ++i)
14049 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14051 SmallVector<int,8> ShufMask2(NumElems, -1);
14052 for (unsigned i = 0; i != NumElems/2; ++i)
14053 ShufMask2[i] = i + NumElems/2;
14055 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14057 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14058 VT.getVectorNumElements()/2);
14060 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14061 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14063 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14066 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14067 // may emit an illegal shuffle but the expansion is still better than scalar
14068 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14069 // we'll emit a shuffle and a arithmetic shift.
14070 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14071 // TODO: It is possible to support ZExt by zeroing the undef values during
14072 // the shuffle phase or after the shuffle.
14073 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14074 SelectionDAG &DAG) {
14075 MVT RegVT = Op.getSimpleValueType();
14076 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14077 assert(RegVT.isInteger() &&
14078 "We only custom lower integer vector sext loads.");
14080 // Nothing useful we can do without SSE2 shuffles.
14081 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14083 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14085 EVT MemVT = Ld->getMemoryVT();
14086 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14087 unsigned RegSz = RegVT.getSizeInBits();
14089 ISD::LoadExtType Ext = Ld->getExtensionType();
14091 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14092 && "Only anyext and sext are currently implemented.");
14093 assert(MemVT != RegVT && "Cannot extend to the same type");
14094 assert(MemVT.isVector() && "Must load a vector from memory");
14096 unsigned NumElems = RegVT.getVectorNumElements();
14097 unsigned MemSz = MemVT.getSizeInBits();
14098 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14100 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14101 // The only way in which we have a legal 256-bit vector result but not the
14102 // integer 256-bit operations needed to directly lower a sextload is if we
14103 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14104 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14105 // correctly legalized. We do this late to allow the canonical form of
14106 // sextload to persist throughout the rest of the DAG combiner -- it wants
14107 // to fold together any extensions it can, and so will fuse a sign_extend
14108 // of an sextload into a sextload targeting a wider value.
14110 if (MemSz == 128) {
14111 // Just switch this to a normal load.
14112 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14113 "it must be a legal 128-bit vector "
14115 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14116 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14117 Ld->isInvariant(), Ld->getAlignment());
14119 assert(MemSz < 128 &&
14120 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14121 // Do an sext load to a 128-bit vector type. We want to use the same
14122 // number of elements, but elements half as wide. This will end up being
14123 // recursively lowered by this routine, but will succeed as we definitely
14124 // have all the necessary features if we're using AVX1.
14126 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14127 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14129 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14130 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14131 Ld->isNonTemporal(), Ld->isInvariant(),
14132 Ld->getAlignment());
14135 // Replace chain users with the new chain.
14136 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14137 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14139 // Finally, do a normal sign-extend to the desired register.
14140 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14143 // All sizes must be a power of two.
14144 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14145 "Non-power-of-two elements are not custom lowered!");
14147 // Attempt to load the original value using scalar loads.
14148 // Find the largest scalar type that divides the total loaded size.
14149 MVT SclrLoadTy = MVT::i8;
14150 for (MVT Tp : MVT::integer_valuetypes()) {
14151 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14156 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14157 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14159 SclrLoadTy = MVT::f64;
14161 // Calculate the number of scalar loads that we need to perform
14162 // in order to load our vector from memory.
14163 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14165 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14166 "Can only lower sext loads with a single scalar load!");
14168 unsigned loadRegZize = RegSz;
14169 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14172 // Represent our vector as a sequence of elements which are the
14173 // largest scalar that we can load.
14174 EVT LoadUnitVecVT = EVT::getVectorVT(
14175 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14177 // Represent the data using the same element type that is stored in
14178 // memory. In practice, we ''widen'' MemVT.
14180 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14181 loadRegZize / MemVT.getScalarType().getSizeInBits());
14183 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14184 "Invalid vector type");
14186 // We can't shuffle using an illegal type.
14187 assert(TLI.isTypeLegal(WideVecVT) &&
14188 "We only lower types that form legal widened vector types");
14190 SmallVector<SDValue, 8> Chains;
14191 SDValue Ptr = Ld->getBasePtr();
14192 SDValue Increment =
14193 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14194 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14196 for (unsigned i = 0; i < NumLoads; ++i) {
14197 // Perform a single load.
14198 SDValue ScalarLoad =
14199 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14200 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14201 Ld->getAlignment());
14202 Chains.push_back(ScalarLoad.getValue(1));
14203 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14204 // another round of DAGCombining.
14206 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14208 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14209 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14211 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14214 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14216 // Bitcast the loaded value to a vector of the original element type, in
14217 // the size of the target vector type.
14218 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14219 unsigned SizeRatio = RegSz / MemSz;
14221 if (Ext == ISD::SEXTLOAD) {
14222 // If we have SSE4.1, we can directly emit a VSEXT node.
14223 if (Subtarget->hasSSE41()) {
14224 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14225 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14229 // Otherwise we'll shuffle the small elements in the high bits of the
14230 // larger type and perform an arithmetic shift. If the shift is not legal
14231 // it's better to scalarize.
14232 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14233 "We can't implement a sext load without an arithmetic right shift!");
14235 // Redistribute the loaded elements into the different locations.
14236 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14237 for (unsigned i = 0; i != NumElems; ++i)
14238 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14240 SDValue Shuff = DAG.getVectorShuffle(
14241 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14243 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14245 // Build the arithmetic shift.
14246 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14247 MemVT.getVectorElementType().getSizeInBits();
14249 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14250 DAG.getConstant(Amt, dl, RegVT));
14252 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14256 // Redistribute the loaded elements into the different locations.
14257 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14258 for (unsigned i = 0; i != NumElems; ++i)
14259 ShuffleVec[i * SizeRatio] = i;
14261 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14262 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14264 // Bitcast to the requested type.
14265 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14266 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14270 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14271 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14272 // from the AND / OR.
14273 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14274 Opc = Op.getOpcode();
14275 if (Opc != ISD::OR && Opc != ISD::AND)
14277 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14278 Op.getOperand(0).hasOneUse() &&
14279 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14280 Op.getOperand(1).hasOneUse());
14283 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14284 // 1 and that the SETCC node has a single use.
14285 static bool isXor1OfSetCC(SDValue Op) {
14286 if (Op.getOpcode() != ISD::XOR)
14288 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14289 if (N1C && N1C->getAPIntValue() == 1) {
14290 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14291 Op.getOperand(0).hasOneUse();
14296 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14297 bool addTest = true;
14298 SDValue Chain = Op.getOperand(0);
14299 SDValue Cond = Op.getOperand(1);
14300 SDValue Dest = Op.getOperand(2);
14303 bool Inverted = false;
14305 if (Cond.getOpcode() == ISD::SETCC) {
14306 // Check for setcc([su]{add,sub,mul}o == 0).
14307 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14308 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14309 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14310 Cond.getOperand(0).getResNo() == 1 &&
14311 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14312 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14313 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14314 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14315 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14316 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14318 Cond = Cond.getOperand(0);
14320 SDValue NewCond = LowerSETCC(Cond, DAG);
14321 if (NewCond.getNode())
14326 // FIXME: LowerXALUO doesn't handle these!!
14327 else if (Cond.getOpcode() == X86ISD::ADD ||
14328 Cond.getOpcode() == X86ISD::SUB ||
14329 Cond.getOpcode() == X86ISD::SMUL ||
14330 Cond.getOpcode() == X86ISD::UMUL)
14331 Cond = LowerXALUO(Cond, DAG);
14334 // Look pass (and (setcc_carry (cmp ...)), 1).
14335 if (Cond.getOpcode() == ISD::AND &&
14336 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14337 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14338 if (C && C->getAPIntValue() == 1)
14339 Cond = Cond.getOperand(0);
14342 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14343 // setting operand in place of the X86ISD::SETCC.
14344 unsigned CondOpcode = Cond.getOpcode();
14345 if (CondOpcode == X86ISD::SETCC ||
14346 CondOpcode == X86ISD::SETCC_CARRY) {
14347 CC = Cond.getOperand(0);
14349 SDValue Cmp = Cond.getOperand(1);
14350 unsigned Opc = Cmp.getOpcode();
14351 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14352 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14356 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14360 // These can only come from an arithmetic instruction with overflow,
14361 // e.g. SADDO, UADDO.
14362 Cond = Cond.getNode()->getOperand(1);
14368 CondOpcode = Cond.getOpcode();
14369 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14370 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14371 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14372 Cond.getOperand(0).getValueType() != MVT::i8)) {
14373 SDValue LHS = Cond.getOperand(0);
14374 SDValue RHS = Cond.getOperand(1);
14375 unsigned X86Opcode;
14378 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14379 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14381 switch (CondOpcode) {
14382 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14386 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14389 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14390 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14392 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14394 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14397 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14398 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14399 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14400 default: llvm_unreachable("unexpected overflowing operator");
14403 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14404 if (CondOpcode == ISD::UMULO)
14405 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14408 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14410 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14412 if (CondOpcode == ISD::UMULO)
14413 Cond = X86Op.getValue(2);
14415 Cond = X86Op.getValue(1);
14417 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14421 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14422 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14423 if (CondOpc == ISD::OR) {
14424 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14425 // two branches instead of an explicit OR instruction with a
14427 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14428 isX86LogicalCmp(Cmp)) {
14429 CC = Cond.getOperand(0).getOperand(0);
14430 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14431 Chain, Dest, CC, Cmp);
14432 CC = Cond.getOperand(1).getOperand(0);
14436 } else { // ISD::AND
14437 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14438 // two branches instead of an explicit AND instruction with a
14439 // separate test. However, we only do this if this block doesn't
14440 // have a fall-through edge, because this requires an explicit
14441 // jmp when the condition is false.
14442 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14443 isX86LogicalCmp(Cmp) &&
14444 Op.getNode()->hasOneUse()) {
14445 X86::CondCode CCode =
14446 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14447 CCode = X86::GetOppositeBranchCondition(CCode);
14448 CC = DAG.getConstant(CCode, dl, MVT::i8);
14449 SDNode *User = *Op.getNode()->use_begin();
14450 // Look for an unconditional branch following this conditional branch.
14451 // We need this because we need to reverse the successors in order
14452 // to implement FCMP_OEQ.
14453 if (User->getOpcode() == ISD::BR) {
14454 SDValue FalseBB = User->getOperand(1);
14456 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14457 assert(NewBR == User);
14461 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14462 Chain, Dest, CC, Cmp);
14463 X86::CondCode CCode =
14464 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14465 CCode = X86::GetOppositeBranchCondition(CCode);
14466 CC = DAG.getConstant(CCode, dl, MVT::i8);
14472 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14473 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14474 // It should be transformed during dag combiner except when the condition
14475 // is set by a arithmetics with overflow node.
14476 X86::CondCode CCode =
14477 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14478 CCode = X86::GetOppositeBranchCondition(CCode);
14479 CC = DAG.getConstant(CCode, dl, MVT::i8);
14480 Cond = Cond.getOperand(0).getOperand(1);
14482 } else if (Cond.getOpcode() == ISD::SETCC &&
14483 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14484 // For FCMP_OEQ, we can emit
14485 // two branches instead of an explicit AND instruction with a
14486 // separate test. However, we only do this if this block doesn't
14487 // have a fall-through edge, because this requires an explicit
14488 // jmp when the condition is false.
14489 if (Op.getNode()->hasOneUse()) {
14490 SDNode *User = *Op.getNode()->use_begin();
14491 // Look for an unconditional branch following this conditional branch.
14492 // We need this because we need to reverse the successors in order
14493 // to implement FCMP_OEQ.
14494 if (User->getOpcode() == ISD::BR) {
14495 SDValue FalseBB = User->getOperand(1);
14497 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14498 assert(NewBR == User);
14502 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14503 Cond.getOperand(0), Cond.getOperand(1));
14504 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14505 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14506 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14507 Chain, Dest, CC, Cmp);
14508 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14513 } else if (Cond.getOpcode() == ISD::SETCC &&
14514 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14515 // For FCMP_UNE, we can emit
14516 // two branches instead of an explicit AND instruction with a
14517 // separate test. However, we only do this if this block doesn't
14518 // have a fall-through edge, because this requires an explicit
14519 // jmp when the condition is false.
14520 if (Op.getNode()->hasOneUse()) {
14521 SDNode *User = *Op.getNode()->use_begin();
14522 // Look for an unconditional branch following this conditional branch.
14523 // We need this because we need to reverse the successors in order
14524 // to implement FCMP_UNE.
14525 if (User->getOpcode() == ISD::BR) {
14526 SDValue FalseBB = User->getOperand(1);
14528 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14529 assert(NewBR == User);
14532 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14533 Cond.getOperand(0), Cond.getOperand(1));
14534 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14535 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14536 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14537 Chain, Dest, CC, Cmp);
14538 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14548 // Look pass the truncate if the high bits are known zero.
14549 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14550 Cond = Cond.getOperand(0);
14552 // We know the result of AND is compared against zero. Try to match
14554 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14555 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14556 if (NewSetCC.getNode()) {
14557 CC = NewSetCC.getOperand(0);
14558 Cond = NewSetCC.getOperand(1);
14565 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14566 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14567 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14569 Cond = ConvertCmpIfNecessary(Cond, DAG);
14570 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14571 Chain, Dest, CC, Cond);
14574 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14575 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14576 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14577 // that the guard pages used by the OS virtual memory manager are allocated in
14578 // correct sequence.
14580 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14581 SelectionDAG &DAG) const {
14582 MachineFunction &MF = DAG.getMachineFunction();
14583 bool SplitStack = MF.shouldSplitStack();
14584 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14589 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14590 SDNode* Node = Op.getNode();
14592 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14593 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14594 " not tell us which reg is the stack pointer!");
14595 EVT VT = Node->getValueType(0);
14596 SDValue Tmp1 = SDValue(Node, 0);
14597 SDValue Tmp2 = SDValue(Node, 1);
14598 SDValue Tmp3 = Node->getOperand(2);
14599 SDValue Chain = Tmp1.getOperand(0);
14601 // Chain the dynamic stack allocation so that it doesn't modify the stack
14602 // pointer when other instructions are using the stack.
14603 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14606 SDValue Size = Tmp2.getOperand(1);
14607 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14608 Chain = SP.getValue(1);
14609 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14610 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14611 unsigned StackAlign = TFI.getStackAlignment();
14612 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14613 if (Align > StackAlign)
14614 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14615 DAG.getConstant(-(uint64_t)Align, dl, VT));
14616 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14618 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14619 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14622 SDValue Ops[2] = { Tmp1, Tmp2 };
14623 return DAG.getMergeValues(Ops, dl);
14627 SDValue Chain = Op.getOperand(0);
14628 SDValue Size = Op.getOperand(1);
14629 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14630 EVT VT = Op.getNode()->getValueType(0);
14632 bool Is64Bit = Subtarget->is64Bit();
14633 EVT SPTy = getPointerTy();
14636 MachineRegisterInfo &MRI = MF.getRegInfo();
14639 // The 64 bit implementation of segmented stacks needs to clobber both r10
14640 // r11. This makes it impossible to use it along with nested parameters.
14641 const Function *F = MF.getFunction();
14643 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14645 if (I->hasNestAttr())
14646 report_fatal_error("Cannot use segmented stacks with functions that "
14647 "have nested arguments.");
14650 const TargetRegisterClass *AddrRegClass =
14651 getRegClassFor(getPointerTy());
14652 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14653 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14654 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14655 DAG.getRegister(Vreg, SPTy));
14656 SDValue Ops1[2] = { Value, Chain };
14657 return DAG.getMergeValues(Ops1, dl);
14660 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14662 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14663 Flag = Chain.getValue(1);
14664 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14666 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14668 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14669 unsigned SPReg = RegInfo->getStackRegister();
14670 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14671 Chain = SP.getValue(1);
14674 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14675 DAG.getConstant(-(uint64_t)Align, dl, VT));
14676 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14679 SDValue Ops1[2] = { SP, Chain };
14680 return DAG.getMergeValues(Ops1, dl);
14684 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14685 MachineFunction &MF = DAG.getMachineFunction();
14686 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14688 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14691 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14692 // vastart just stores the address of the VarArgsFrameIndex slot into the
14693 // memory location argument.
14694 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14696 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14697 MachinePointerInfo(SV), false, false, 0);
14701 // gp_offset (0 - 6 * 8)
14702 // fp_offset (48 - 48 + 8 * 16)
14703 // overflow_arg_area (point to parameters coming in memory).
14705 SmallVector<SDValue, 8> MemOps;
14706 SDValue FIN = Op.getOperand(1);
14708 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14709 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14711 FIN, MachinePointerInfo(SV), false, false, 0);
14712 MemOps.push_back(Store);
14715 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14716 FIN, DAG.getIntPtrConstant(4, DL));
14717 Store = DAG.getStore(Op.getOperand(0), DL,
14718 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14720 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14721 MemOps.push_back(Store);
14723 // Store ptr to overflow_arg_area
14724 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14725 FIN, DAG.getIntPtrConstant(4, DL));
14726 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14728 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14729 MachinePointerInfo(SV, 8),
14731 MemOps.push_back(Store);
14733 // Store ptr to reg_save_area.
14734 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14735 FIN, DAG.getIntPtrConstant(8, DL));
14736 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14738 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14739 MachinePointerInfo(SV, 16), false, false, 0);
14740 MemOps.push_back(Store);
14741 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14744 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14745 assert(Subtarget->is64Bit() &&
14746 "LowerVAARG only handles 64-bit va_arg!");
14747 assert((Subtarget->isTargetLinux() ||
14748 Subtarget->isTargetDarwin()) &&
14749 "Unhandled target in LowerVAARG");
14750 assert(Op.getNode()->getNumOperands() == 4);
14751 SDValue Chain = Op.getOperand(0);
14752 SDValue SrcPtr = Op.getOperand(1);
14753 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14754 unsigned Align = Op.getConstantOperandVal(3);
14757 EVT ArgVT = Op.getNode()->getValueType(0);
14758 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14759 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14762 // Decide which area this value should be read from.
14763 // TODO: Implement the AMD64 ABI in its entirety. This simple
14764 // selection mechanism works only for the basic types.
14765 if (ArgVT == MVT::f80) {
14766 llvm_unreachable("va_arg for f80 not yet implemented");
14767 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14768 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14769 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14770 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14772 llvm_unreachable("Unhandled argument type in LowerVAARG");
14775 if (ArgMode == 2) {
14776 // Sanity Check: Make sure using fp_offset makes sense.
14777 assert(!Subtarget->useSoftFloat() &&
14778 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14779 Attribute::NoImplicitFloat)) &&
14780 Subtarget->hasSSE1());
14783 // Insert VAARG_64 node into the DAG
14784 // VAARG_64 returns two values: Variable Argument Address, Chain
14785 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14786 DAG.getConstant(ArgMode, dl, MVT::i8),
14787 DAG.getConstant(Align, dl, MVT::i32)};
14788 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14789 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14790 VTs, InstOps, MVT::i64,
14791 MachinePointerInfo(SV),
14793 /*Volatile=*/false,
14795 /*WriteMem=*/true);
14796 Chain = VAARG.getValue(1);
14798 // Load the next argument and return it
14799 return DAG.getLoad(ArgVT, dl,
14802 MachinePointerInfo(),
14803 false, false, false, 0);
14806 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14807 SelectionDAG &DAG) {
14808 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14809 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14810 SDValue Chain = Op.getOperand(0);
14811 SDValue DstPtr = Op.getOperand(1);
14812 SDValue SrcPtr = Op.getOperand(2);
14813 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14814 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14817 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14818 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14820 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14823 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14824 // amount is a constant. Takes immediate version of shift as input.
14825 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14826 SDValue SrcOp, uint64_t ShiftAmt,
14827 SelectionDAG &DAG) {
14828 MVT ElementType = VT.getVectorElementType();
14830 // Fold this packed shift into its first operand if ShiftAmt is 0.
14834 // Check for ShiftAmt >= element width
14835 if (ShiftAmt >= ElementType.getSizeInBits()) {
14836 if (Opc == X86ISD::VSRAI)
14837 ShiftAmt = ElementType.getSizeInBits() - 1;
14839 return DAG.getConstant(0, dl, VT);
14842 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14843 && "Unknown target vector shift-by-constant node");
14845 // Fold this packed vector shift into a build vector if SrcOp is a
14846 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14847 if (VT == SrcOp.getSimpleValueType() &&
14848 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14849 SmallVector<SDValue, 8> Elts;
14850 unsigned NumElts = SrcOp->getNumOperands();
14851 ConstantSDNode *ND;
14854 default: llvm_unreachable(nullptr);
14855 case X86ISD::VSHLI:
14856 for (unsigned i=0; i!=NumElts; ++i) {
14857 SDValue CurrentOp = SrcOp->getOperand(i);
14858 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14859 Elts.push_back(CurrentOp);
14862 ND = cast<ConstantSDNode>(CurrentOp);
14863 const APInt &C = ND->getAPIntValue();
14864 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14867 case X86ISD::VSRLI:
14868 for (unsigned i=0; i!=NumElts; ++i) {
14869 SDValue CurrentOp = SrcOp->getOperand(i);
14870 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14871 Elts.push_back(CurrentOp);
14874 ND = cast<ConstantSDNode>(CurrentOp);
14875 const APInt &C = ND->getAPIntValue();
14876 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14879 case X86ISD::VSRAI:
14880 for (unsigned i=0; i!=NumElts; ++i) {
14881 SDValue CurrentOp = SrcOp->getOperand(i);
14882 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14883 Elts.push_back(CurrentOp);
14886 ND = cast<ConstantSDNode>(CurrentOp);
14887 const APInt &C = ND->getAPIntValue();
14888 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14893 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14896 return DAG.getNode(Opc, dl, VT, SrcOp,
14897 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14900 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14901 // may or may not be a constant. Takes immediate version of shift as input.
14902 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14903 SDValue SrcOp, SDValue ShAmt,
14904 SelectionDAG &DAG) {
14905 MVT SVT = ShAmt.getSimpleValueType();
14906 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14908 // Catch shift-by-constant.
14909 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14910 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14911 CShAmt->getZExtValue(), DAG);
14913 // Change opcode to non-immediate version
14915 default: llvm_unreachable("Unknown target vector shift node");
14916 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14917 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14918 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14921 const X86Subtarget &Subtarget =
14922 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14923 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14924 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14925 // Let the shuffle legalizer expand this shift amount node.
14926 SDValue Op0 = ShAmt.getOperand(0);
14927 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14928 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14930 // Need to build a vector containing shift amount.
14931 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14932 SmallVector<SDValue, 4> ShOps;
14933 ShOps.push_back(ShAmt);
14934 if (SVT == MVT::i32) {
14935 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14936 ShOps.push_back(DAG.getUNDEF(SVT));
14938 ShOps.push_back(DAG.getUNDEF(SVT));
14940 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14941 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14944 // The return type has to be a 128-bit type with the same element
14945 // type as the input type.
14946 MVT EltVT = VT.getVectorElementType();
14947 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14949 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14950 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14953 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14954 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14955 /// necessary casting for \p Mask when lowering masking intrinsics.
14956 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14957 SDValue PreservedSrc,
14958 const X86Subtarget *Subtarget,
14959 SelectionDAG &DAG) {
14960 EVT VT = Op.getValueType();
14961 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14962 MVT::i1, VT.getVectorNumElements());
14963 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14964 Mask.getValueType().getSizeInBits());
14967 assert(MaskVT.isSimple() && "invalid mask type");
14969 if (isAllOnes(Mask))
14972 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14973 // are extracted by EXTRACT_SUBVECTOR.
14974 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14975 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14976 DAG.getIntPtrConstant(0, dl));
14978 switch (Op.getOpcode()) {
14980 case X86ISD::PCMPEQM:
14981 case X86ISD::PCMPGTM:
14983 case X86ISD::CMPMU:
14984 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14986 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14987 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14988 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14991 /// \brief Creates an SDNode for a predicated scalar operation.
14992 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14993 /// The mask is comming as MVT::i8 and it should be truncated
14994 /// to MVT::i1 while lowering masking intrinsics.
14995 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14996 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14997 /// a scalar instruction.
14998 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14999 SDValue PreservedSrc,
15000 const X86Subtarget *Subtarget,
15001 SelectionDAG &DAG) {
15002 if (isAllOnes(Mask))
15005 EVT VT = Op.getValueType();
15007 // The mask should be of type MVT::i1
15008 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15010 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15011 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15012 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15015 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15016 SelectionDAG &DAG) {
15018 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15019 EVT VT = Op.getValueType();
15020 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15022 switch(IntrData->Type) {
15023 case INTR_TYPE_1OP:
15024 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15025 case INTR_TYPE_2OP:
15026 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15028 case INTR_TYPE_3OP:
15029 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15030 Op.getOperand(2), Op.getOperand(3));
15031 case INTR_TYPE_1OP_MASK_RM: {
15032 SDValue Src = Op.getOperand(1);
15033 SDValue Src0 = Op.getOperand(2);
15034 SDValue Mask = Op.getOperand(3);
15035 SDValue RoundingMode = Op.getOperand(4);
15036 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15038 Mask, Src0, Subtarget, DAG);
15040 case INTR_TYPE_SCALAR_MASK_RM: {
15041 SDValue Src1 = Op.getOperand(1);
15042 SDValue Src2 = Op.getOperand(2);
15043 SDValue Src0 = Op.getOperand(3);
15044 SDValue Mask = Op.getOperand(4);
15045 // There are 2 kinds of intrinsics in this group:
15046 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15047 // (2) With rounding mode and sae - 7 operands.
15048 if (Op.getNumOperands() == 6) {
15049 SDValue Sae = Op.getOperand(5);
15050 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15051 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15053 Mask, Src0, Subtarget, DAG);
15055 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15056 SDValue RoundingMode = Op.getOperand(5);
15057 SDValue Sae = Op.getOperand(6);
15058 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15059 RoundingMode, Sae),
15060 Mask, Src0, Subtarget, DAG);
15062 case INTR_TYPE_2OP_MASK: {
15063 SDValue Src1 = Op.getOperand(1);
15064 SDValue Src2 = Op.getOperand(2);
15065 SDValue PassThru = Op.getOperand(3);
15066 SDValue Mask = Op.getOperand(4);
15067 // We specify 2 possible opcodes for intrinsics with rounding modes.
15068 // First, we check if the intrinsic may have non-default rounding mode,
15069 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15070 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15071 if (IntrWithRoundingModeOpcode != 0) {
15072 SDValue Rnd = Op.getOperand(5);
15073 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15074 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15075 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15076 dl, Op.getValueType(),
15078 Mask, PassThru, Subtarget, DAG);
15081 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15083 Mask, PassThru, Subtarget, DAG);
15085 case FMA_OP_MASK: {
15086 SDValue Src1 = Op.getOperand(1);
15087 SDValue Src2 = Op.getOperand(2);
15088 SDValue Src3 = Op.getOperand(3);
15089 SDValue Mask = Op.getOperand(4);
15090 // We specify 2 possible opcodes for intrinsics with rounding modes.
15091 // First, we check if the intrinsic may have non-default rounding mode,
15092 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15093 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15094 if (IntrWithRoundingModeOpcode != 0) {
15095 SDValue Rnd = Op.getOperand(5);
15096 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15097 X86::STATIC_ROUNDING::CUR_DIRECTION)
15098 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15099 dl, Op.getValueType(),
15100 Src1, Src2, Src3, Rnd),
15101 Mask, Src1, Subtarget, DAG);
15103 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15104 dl, Op.getValueType(),
15106 Mask, Src1, Subtarget, DAG);
15109 case CMP_MASK_CC: {
15110 // Comparison intrinsics with masks.
15111 // Example of transformation:
15112 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15113 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15115 // (v8i1 (insert_subvector undef,
15116 // (v2i1 (and (PCMPEQM %a, %b),
15117 // (extract_subvector
15118 // (v8i1 (bitcast %mask)), 0))), 0))))
15119 EVT VT = Op.getOperand(1).getValueType();
15120 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15121 VT.getVectorNumElements());
15122 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15123 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15124 Mask.getValueType().getSizeInBits());
15126 if (IntrData->Type == CMP_MASK_CC) {
15127 SDValue CC = Op.getOperand(3);
15128 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15129 // We specify 2 possible opcodes for intrinsics with rounding modes.
15130 // First, we check if the intrinsic may have non-default rounding mode,
15131 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15132 if (IntrData->Opc1 != 0) {
15133 SDValue Rnd = Op.getOperand(5);
15134 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15135 X86::STATIC_ROUNDING::CUR_DIRECTION)
15136 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15137 Op.getOperand(2), CC, Rnd);
15139 //default rounding mode
15141 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15142 Op.getOperand(2), CC);
15145 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15146 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15149 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15150 DAG.getTargetConstant(0, dl,
15153 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15154 DAG.getUNDEF(BitcastVT), CmpMask,
15155 DAG.getIntPtrConstant(0, dl));
15156 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
15158 case COMI: { // Comparison intrinsics
15159 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15160 SDValue LHS = Op.getOperand(1);
15161 SDValue RHS = Op.getOperand(2);
15162 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15163 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15164 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15165 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15166 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15167 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15170 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15171 Op.getOperand(1), Op.getOperand(2), DAG);
15173 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15174 Op.getSimpleValueType(),
15176 Op.getOperand(2), DAG),
15177 Op.getOperand(4), Op.getOperand(3), Subtarget,
15179 case COMPRESS_EXPAND_IN_REG: {
15180 SDValue Mask = Op.getOperand(3);
15181 SDValue DataToCompress = Op.getOperand(1);
15182 SDValue PassThru = Op.getOperand(2);
15183 if (isAllOnes(Mask)) // return data as is
15184 return Op.getOperand(1);
15185 EVT VT = Op.getValueType();
15186 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15187 VT.getVectorNumElements());
15188 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15189 Mask.getValueType().getSizeInBits());
15191 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15192 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15193 DAG.getIntPtrConstant(0, dl));
15195 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15199 SDValue Mask = Op.getOperand(3);
15200 EVT VT = Op.getValueType();
15201 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15202 VT.getVectorNumElements());
15203 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15204 Mask.getValueType().getSizeInBits());
15206 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15207 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15208 DAG.getIntPtrConstant(0, dl));
15209 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15218 default: return SDValue(); // Don't custom lower most intrinsics.
15220 case Intrinsic::x86_avx2_permd:
15221 case Intrinsic::x86_avx2_permps:
15222 // Operands intentionally swapped. Mask is last operand to intrinsic,
15223 // but second operand for node/instruction.
15224 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15225 Op.getOperand(2), Op.getOperand(1));
15227 case Intrinsic::x86_avx512_mask_valign_q_512:
15228 case Intrinsic::x86_avx512_mask_valign_d_512:
15229 // Vector source operands are swapped.
15230 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15231 Op.getValueType(), Op.getOperand(2),
15234 Op.getOperand(5), Op.getOperand(4),
15237 // ptest and testp intrinsics. The intrinsic these come from are designed to
15238 // return an integer value, not just an instruction so lower it to the ptest
15239 // or testp pattern and a setcc for the result.
15240 case Intrinsic::x86_sse41_ptestz:
15241 case Intrinsic::x86_sse41_ptestc:
15242 case Intrinsic::x86_sse41_ptestnzc:
15243 case Intrinsic::x86_avx_ptestz_256:
15244 case Intrinsic::x86_avx_ptestc_256:
15245 case Intrinsic::x86_avx_ptestnzc_256:
15246 case Intrinsic::x86_avx_vtestz_ps:
15247 case Intrinsic::x86_avx_vtestc_ps:
15248 case Intrinsic::x86_avx_vtestnzc_ps:
15249 case Intrinsic::x86_avx_vtestz_pd:
15250 case Intrinsic::x86_avx_vtestc_pd:
15251 case Intrinsic::x86_avx_vtestnzc_pd:
15252 case Intrinsic::x86_avx_vtestz_ps_256:
15253 case Intrinsic::x86_avx_vtestc_ps_256:
15254 case Intrinsic::x86_avx_vtestnzc_ps_256:
15255 case Intrinsic::x86_avx_vtestz_pd_256:
15256 case Intrinsic::x86_avx_vtestc_pd_256:
15257 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15258 bool IsTestPacked = false;
15261 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15262 case Intrinsic::x86_avx_vtestz_ps:
15263 case Intrinsic::x86_avx_vtestz_pd:
15264 case Intrinsic::x86_avx_vtestz_ps_256:
15265 case Intrinsic::x86_avx_vtestz_pd_256:
15266 IsTestPacked = true; // Fallthrough
15267 case Intrinsic::x86_sse41_ptestz:
15268 case Intrinsic::x86_avx_ptestz_256:
15270 X86CC = X86::COND_E;
15272 case Intrinsic::x86_avx_vtestc_ps:
15273 case Intrinsic::x86_avx_vtestc_pd:
15274 case Intrinsic::x86_avx_vtestc_ps_256:
15275 case Intrinsic::x86_avx_vtestc_pd_256:
15276 IsTestPacked = true; // Fallthrough
15277 case Intrinsic::x86_sse41_ptestc:
15278 case Intrinsic::x86_avx_ptestc_256:
15280 X86CC = X86::COND_B;
15282 case Intrinsic::x86_avx_vtestnzc_ps:
15283 case Intrinsic::x86_avx_vtestnzc_pd:
15284 case Intrinsic::x86_avx_vtestnzc_ps_256:
15285 case Intrinsic::x86_avx_vtestnzc_pd_256:
15286 IsTestPacked = true; // Fallthrough
15287 case Intrinsic::x86_sse41_ptestnzc:
15288 case Intrinsic::x86_avx_ptestnzc_256:
15290 X86CC = X86::COND_A;
15294 SDValue LHS = Op.getOperand(1);
15295 SDValue RHS = Op.getOperand(2);
15296 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15297 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15298 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15299 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15300 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15302 case Intrinsic::x86_avx512_kortestz_w:
15303 case Intrinsic::x86_avx512_kortestc_w: {
15304 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15305 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15306 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15307 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15308 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15309 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15310 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15313 case Intrinsic::x86_sse42_pcmpistria128:
15314 case Intrinsic::x86_sse42_pcmpestria128:
15315 case Intrinsic::x86_sse42_pcmpistric128:
15316 case Intrinsic::x86_sse42_pcmpestric128:
15317 case Intrinsic::x86_sse42_pcmpistrio128:
15318 case Intrinsic::x86_sse42_pcmpestrio128:
15319 case Intrinsic::x86_sse42_pcmpistris128:
15320 case Intrinsic::x86_sse42_pcmpestris128:
15321 case Intrinsic::x86_sse42_pcmpistriz128:
15322 case Intrinsic::x86_sse42_pcmpestriz128: {
15326 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15327 case Intrinsic::x86_sse42_pcmpistria128:
15328 Opcode = X86ISD::PCMPISTRI;
15329 X86CC = X86::COND_A;
15331 case Intrinsic::x86_sse42_pcmpestria128:
15332 Opcode = X86ISD::PCMPESTRI;
15333 X86CC = X86::COND_A;
15335 case Intrinsic::x86_sse42_pcmpistric128:
15336 Opcode = X86ISD::PCMPISTRI;
15337 X86CC = X86::COND_B;
15339 case Intrinsic::x86_sse42_pcmpestric128:
15340 Opcode = X86ISD::PCMPESTRI;
15341 X86CC = X86::COND_B;
15343 case Intrinsic::x86_sse42_pcmpistrio128:
15344 Opcode = X86ISD::PCMPISTRI;
15345 X86CC = X86::COND_O;
15347 case Intrinsic::x86_sse42_pcmpestrio128:
15348 Opcode = X86ISD::PCMPESTRI;
15349 X86CC = X86::COND_O;
15351 case Intrinsic::x86_sse42_pcmpistris128:
15352 Opcode = X86ISD::PCMPISTRI;
15353 X86CC = X86::COND_S;
15355 case Intrinsic::x86_sse42_pcmpestris128:
15356 Opcode = X86ISD::PCMPESTRI;
15357 X86CC = X86::COND_S;
15359 case Intrinsic::x86_sse42_pcmpistriz128:
15360 Opcode = X86ISD::PCMPISTRI;
15361 X86CC = X86::COND_E;
15363 case Intrinsic::x86_sse42_pcmpestriz128:
15364 Opcode = X86ISD::PCMPESTRI;
15365 X86CC = X86::COND_E;
15368 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15369 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15370 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15371 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15372 DAG.getConstant(X86CC, dl, MVT::i8),
15373 SDValue(PCMP.getNode(), 1));
15374 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15377 case Intrinsic::x86_sse42_pcmpistri128:
15378 case Intrinsic::x86_sse42_pcmpestri128: {
15380 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15381 Opcode = X86ISD::PCMPISTRI;
15383 Opcode = X86ISD::PCMPESTRI;
15385 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15386 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15387 return DAG.getNode(Opcode, dl, VTs, NewOps);
15390 case Intrinsic::x86_seh_lsda: {
15391 // Compute the symbol for the LSDA. We know it'll get emitted later.
15392 MachineFunction &MF = DAG.getMachineFunction();
15393 SDValue Op1 = Op.getOperand(1);
15394 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15395 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15396 GlobalValue::getRealLinkageName(Fn->getName()));
15397 StringRef Name = LSDASym->getName();
15398 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
15400 // Generate a simple absolute symbol reference. This intrinsic is only
15401 // supported on 32-bit Windows, which isn't PIC.
15403 DAG.getTargetExternalSymbol(Name.data(), VT, X86II::MO_NOPREFIX);
15404 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15409 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15410 SDValue Src, SDValue Mask, SDValue Base,
15411 SDValue Index, SDValue ScaleOp, SDValue Chain,
15412 const X86Subtarget * Subtarget) {
15414 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15415 assert(C && "Invalid scale type");
15416 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15417 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15418 Index.getSimpleValueType().getVectorNumElements());
15420 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15422 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15424 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15425 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15426 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15427 SDValue Segment = DAG.getRegister(0, MVT::i32);
15428 if (Src.getOpcode() == ISD::UNDEF)
15429 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15430 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15431 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15432 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15433 return DAG.getMergeValues(RetOps, dl);
15436 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15437 SDValue Src, SDValue Mask, SDValue Base,
15438 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15440 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15441 assert(C && "Invalid scale type");
15442 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15443 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15444 SDValue Segment = DAG.getRegister(0, MVT::i32);
15445 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15446 Index.getSimpleValueType().getVectorNumElements());
15448 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15450 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15452 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15453 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15454 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15455 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15456 return SDValue(Res, 1);
15459 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15460 SDValue Mask, SDValue Base, SDValue Index,
15461 SDValue ScaleOp, SDValue Chain) {
15463 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15464 assert(C && "Invalid scale type");
15465 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15466 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15467 SDValue Segment = DAG.getRegister(0, MVT::i32);
15469 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15471 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15473 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15475 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15476 //SDVTList VTs = DAG.getVTList(MVT::Other);
15477 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15478 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15479 return SDValue(Res, 0);
15482 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15483 // read performance monitor counters (x86_rdpmc).
15484 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15485 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15486 SmallVectorImpl<SDValue> &Results) {
15487 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15488 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15491 // The ECX register is used to select the index of the performance counter
15493 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15495 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15497 // Reads the content of a 64-bit performance counter and returns it in the
15498 // registers EDX:EAX.
15499 if (Subtarget->is64Bit()) {
15500 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15501 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15504 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15505 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15508 Chain = HI.getValue(1);
15510 if (Subtarget->is64Bit()) {
15511 // The EAX register is loaded with the low-order 32 bits. The EDX register
15512 // is loaded with the supported high-order bits of the counter.
15513 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15514 DAG.getConstant(32, DL, MVT::i8));
15515 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15516 Results.push_back(Chain);
15520 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15521 SDValue Ops[] = { LO, HI };
15522 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15523 Results.push_back(Pair);
15524 Results.push_back(Chain);
15527 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15528 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15529 // also used to custom lower READCYCLECOUNTER nodes.
15530 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15531 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15532 SmallVectorImpl<SDValue> &Results) {
15533 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15534 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15537 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15538 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15539 // and the EAX register is loaded with the low-order 32 bits.
15540 if (Subtarget->is64Bit()) {
15541 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15542 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15545 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15546 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15549 SDValue Chain = HI.getValue(1);
15551 if (Opcode == X86ISD::RDTSCP_DAG) {
15552 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15554 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15555 // the ECX register. Add 'ecx' explicitly to the chain.
15556 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15558 // Explicitly store the content of ECX at the location passed in input
15559 // to the 'rdtscp' intrinsic.
15560 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15561 MachinePointerInfo(), false, false, 0);
15564 if (Subtarget->is64Bit()) {
15565 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15566 // the EAX register is loaded with the low-order 32 bits.
15567 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15568 DAG.getConstant(32, DL, MVT::i8));
15569 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15570 Results.push_back(Chain);
15574 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15575 SDValue Ops[] = { LO, HI };
15576 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15577 Results.push_back(Pair);
15578 Results.push_back(Chain);
15581 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15582 SelectionDAG &DAG) {
15583 SmallVector<SDValue, 2> Results;
15585 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15587 return DAG.getMergeValues(Results, DL);
15591 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15592 SelectionDAG &DAG) {
15593 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15595 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15600 switch(IntrData->Type) {
15602 llvm_unreachable("Unknown Intrinsic Type");
15606 // Emit the node with the right value type.
15607 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15608 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15610 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15611 // Otherwise return the value from Rand, which is always 0, casted to i32.
15612 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15613 DAG.getConstant(1, dl, Op->getValueType(1)),
15614 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15615 SDValue(Result.getNode(), 1) };
15616 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15617 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15620 // Return { result, isValid, chain }.
15621 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15622 SDValue(Result.getNode(), 2));
15625 //gather(v1, mask, index, base, scale);
15626 SDValue Chain = Op.getOperand(0);
15627 SDValue Src = Op.getOperand(2);
15628 SDValue Base = Op.getOperand(3);
15629 SDValue Index = Op.getOperand(4);
15630 SDValue Mask = Op.getOperand(5);
15631 SDValue Scale = Op.getOperand(6);
15632 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15636 //scatter(base, mask, index, v1, scale);
15637 SDValue Chain = Op.getOperand(0);
15638 SDValue Base = Op.getOperand(2);
15639 SDValue Mask = Op.getOperand(3);
15640 SDValue Index = Op.getOperand(4);
15641 SDValue Src = Op.getOperand(5);
15642 SDValue Scale = Op.getOperand(6);
15643 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15647 SDValue Hint = Op.getOperand(6);
15648 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15649 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15650 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15651 SDValue Chain = Op.getOperand(0);
15652 SDValue Mask = Op.getOperand(2);
15653 SDValue Index = Op.getOperand(3);
15654 SDValue Base = Op.getOperand(4);
15655 SDValue Scale = Op.getOperand(5);
15656 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15658 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15660 SmallVector<SDValue, 2> Results;
15661 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15663 return DAG.getMergeValues(Results, dl);
15665 // Read Performance Monitoring Counters.
15667 SmallVector<SDValue, 2> Results;
15668 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15669 return DAG.getMergeValues(Results, dl);
15671 // XTEST intrinsics.
15673 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15674 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15675 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15676 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15678 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15679 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15680 Ret, SDValue(InTrans.getNode(), 1));
15684 SmallVector<SDValue, 2> Results;
15685 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15686 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15687 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15688 DAG.getConstant(-1, dl, MVT::i8));
15689 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15690 Op.getOperand(4), GenCF.getValue(1));
15691 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15692 Op.getOperand(5), MachinePointerInfo(),
15694 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15695 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15697 Results.push_back(SetCC);
15698 Results.push_back(Store);
15699 return DAG.getMergeValues(Results, dl);
15701 case COMPRESS_TO_MEM: {
15703 SDValue Mask = Op.getOperand(4);
15704 SDValue DataToCompress = Op.getOperand(3);
15705 SDValue Addr = Op.getOperand(2);
15706 SDValue Chain = Op.getOperand(0);
15708 if (isAllOnes(Mask)) // return just a store
15709 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15710 MachinePointerInfo(), false, false, 0);
15712 EVT VT = DataToCompress.getValueType();
15713 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15714 VT.getVectorNumElements());
15715 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15716 Mask.getValueType().getSizeInBits());
15717 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15718 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15719 DAG.getIntPtrConstant(0, dl));
15721 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15722 DataToCompress, DAG.getUNDEF(VT));
15723 return DAG.getStore(Chain, dl, Compressed, Addr,
15724 MachinePointerInfo(), false, false, 0);
15726 case EXPAND_FROM_MEM: {
15728 SDValue Mask = Op.getOperand(4);
15729 SDValue PathThru = Op.getOperand(3);
15730 SDValue Addr = Op.getOperand(2);
15731 SDValue Chain = Op.getOperand(0);
15732 EVT VT = Op.getValueType();
15734 if (isAllOnes(Mask)) // return just a load
15735 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15737 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15738 VT.getVectorNumElements());
15739 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15740 Mask.getValueType().getSizeInBits());
15741 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15742 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15743 DAG.getIntPtrConstant(0, dl));
15745 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15746 false, false, false, 0);
15748 SDValue Results[] = {
15749 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15751 return DAG.getMergeValues(Results, dl);
15756 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15757 SelectionDAG &DAG) const {
15758 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15759 MFI->setReturnAddressIsTaken(true);
15761 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15764 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15766 EVT PtrVT = getPointerTy();
15769 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15770 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15771 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15772 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15773 DAG.getNode(ISD::ADD, dl, PtrVT,
15774 FrameAddr, Offset),
15775 MachinePointerInfo(), false, false, false, 0);
15778 // Just load the return address.
15779 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15780 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15781 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15784 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15785 MachineFunction &MF = DAG.getMachineFunction();
15786 MachineFrameInfo *MFI = MF.getFrameInfo();
15787 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15788 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15789 EVT VT = Op.getValueType();
15791 MFI->setFrameAddressIsTaken(true);
15793 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15794 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15795 // is not possible to crawl up the stack without looking at the unwind codes
15797 int FrameAddrIndex = FuncInfo->getFAIndex();
15798 if (!FrameAddrIndex) {
15799 // Set up a frame object for the return address.
15800 unsigned SlotSize = RegInfo->getSlotSize();
15801 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15802 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15803 FuncInfo->setFAIndex(FrameAddrIndex);
15805 return DAG.getFrameIndex(FrameAddrIndex, VT);
15808 unsigned FrameReg =
15809 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15810 SDLoc dl(Op); // FIXME probably not meaningful
15811 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15812 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15813 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15814 "Invalid Frame Register!");
15815 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15817 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15818 MachinePointerInfo(),
15819 false, false, false, 0);
15823 // FIXME? Maybe this could be a TableGen attribute on some registers and
15824 // this table could be generated automatically from RegInfo.
15825 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15827 unsigned Reg = StringSwitch<unsigned>(RegName)
15828 .Case("esp", X86::ESP)
15829 .Case("rsp", X86::RSP)
15833 report_fatal_error("Invalid register name global variable");
15836 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15837 SelectionDAG &DAG) const {
15838 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15839 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15842 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15843 SDValue Chain = Op.getOperand(0);
15844 SDValue Offset = Op.getOperand(1);
15845 SDValue Handler = Op.getOperand(2);
15848 EVT PtrVT = getPointerTy();
15849 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15850 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15851 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15852 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15853 "Invalid Frame Register!");
15854 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15855 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15857 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15858 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15860 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15861 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15863 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15865 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15866 DAG.getRegister(StoreAddrReg, PtrVT));
15869 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15870 SelectionDAG &DAG) const {
15872 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15873 DAG.getVTList(MVT::i32, MVT::Other),
15874 Op.getOperand(0), Op.getOperand(1));
15877 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15878 SelectionDAG &DAG) const {
15880 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15881 Op.getOperand(0), Op.getOperand(1));
15884 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15885 return Op.getOperand(0);
15888 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15889 SelectionDAG &DAG) const {
15890 SDValue Root = Op.getOperand(0);
15891 SDValue Trmp = Op.getOperand(1); // trampoline
15892 SDValue FPtr = Op.getOperand(2); // nested function
15893 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15896 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15897 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15899 if (Subtarget->is64Bit()) {
15900 SDValue OutChains[6];
15902 // Large code-model.
15903 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15904 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15906 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15907 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15909 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15911 // Load the pointer to the nested function into R11.
15912 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15913 SDValue Addr = Trmp;
15914 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15915 Addr, MachinePointerInfo(TrmpAddr),
15918 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15919 DAG.getConstant(2, dl, MVT::i64));
15920 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15921 MachinePointerInfo(TrmpAddr, 2),
15924 // Load the 'nest' parameter value into R10.
15925 // R10 is specified in X86CallingConv.td
15926 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15927 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15928 DAG.getConstant(10, dl, MVT::i64));
15929 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15930 Addr, MachinePointerInfo(TrmpAddr, 10),
15933 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15934 DAG.getConstant(12, dl, MVT::i64));
15935 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15936 MachinePointerInfo(TrmpAddr, 12),
15939 // Jump to the nested function.
15940 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15941 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15942 DAG.getConstant(20, dl, MVT::i64));
15943 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15944 Addr, MachinePointerInfo(TrmpAddr, 20),
15947 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15948 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15949 DAG.getConstant(22, dl, MVT::i64));
15950 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
15951 Addr, MachinePointerInfo(TrmpAddr, 22),
15954 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15956 const Function *Func =
15957 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15958 CallingConv::ID CC = Func->getCallingConv();
15963 llvm_unreachable("Unsupported calling convention");
15964 case CallingConv::C:
15965 case CallingConv::X86_StdCall: {
15966 // Pass 'nest' parameter in ECX.
15967 // Must be kept in sync with X86CallingConv.td
15968 NestReg = X86::ECX;
15970 // Check that ECX wasn't needed by an 'inreg' parameter.
15971 FunctionType *FTy = Func->getFunctionType();
15972 const AttributeSet &Attrs = Func->getAttributes();
15974 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15975 unsigned InRegCount = 0;
15978 for (FunctionType::param_iterator I = FTy->param_begin(),
15979 E = FTy->param_end(); I != E; ++I, ++Idx)
15980 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15981 // FIXME: should only count parameters that are lowered to integers.
15982 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15984 if (InRegCount > 2) {
15985 report_fatal_error("Nest register in use - reduce number of inreg"
15991 case CallingConv::X86_FastCall:
15992 case CallingConv::X86_ThisCall:
15993 case CallingConv::Fast:
15994 // Pass 'nest' parameter in EAX.
15995 // Must be kept in sync with X86CallingConv.td
15996 NestReg = X86::EAX;
16000 SDValue OutChains[4];
16001 SDValue Addr, Disp;
16003 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16004 DAG.getConstant(10, dl, MVT::i32));
16005 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16007 // This is storing the opcode for MOV32ri.
16008 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16009 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16010 OutChains[0] = DAG.getStore(Root, dl,
16011 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16012 Trmp, MachinePointerInfo(TrmpAddr),
16015 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16016 DAG.getConstant(1, dl, MVT::i32));
16017 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16018 MachinePointerInfo(TrmpAddr, 1),
16021 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16022 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16023 DAG.getConstant(5, dl, MVT::i32));
16024 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16025 Addr, MachinePointerInfo(TrmpAddr, 5),
16028 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16029 DAG.getConstant(6, dl, MVT::i32));
16030 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16031 MachinePointerInfo(TrmpAddr, 6),
16034 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16038 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16039 SelectionDAG &DAG) const {
16041 The rounding mode is in bits 11:10 of FPSR, and has the following
16043 00 Round to nearest
16048 FLT_ROUNDS, on the other hand, expects the following:
16055 To perform the conversion, we do:
16056 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16059 MachineFunction &MF = DAG.getMachineFunction();
16060 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16061 unsigned StackAlignment = TFI.getStackAlignment();
16062 MVT VT = Op.getSimpleValueType();
16065 // Save FP Control Word to stack slot
16066 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16067 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16069 MachineMemOperand *MMO =
16070 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16071 MachineMemOperand::MOStore, 2, 2);
16073 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16074 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16075 DAG.getVTList(MVT::Other),
16076 Ops, MVT::i16, MMO);
16078 // Load FP Control Word from stack slot
16079 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16080 MachinePointerInfo(), false, false, false, 0);
16082 // Transform as necessary
16084 DAG.getNode(ISD::SRL, DL, MVT::i16,
16085 DAG.getNode(ISD::AND, DL, MVT::i16,
16086 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16087 DAG.getConstant(11, DL, MVT::i8));
16089 DAG.getNode(ISD::SRL, DL, MVT::i16,
16090 DAG.getNode(ISD::AND, DL, MVT::i16,
16091 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16092 DAG.getConstant(9, DL, MVT::i8));
16095 DAG.getNode(ISD::AND, DL, MVT::i16,
16096 DAG.getNode(ISD::ADD, DL, MVT::i16,
16097 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16098 DAG.getConstant(1, DL, MVT::i16)),
16099 DAG.getConstant(3, DL, MVT::i16));
16101 return DAG.getNode((VT.getSizeInBits() < 16 ?
16102 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16105 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16106 MVT VT = Op.getSimpleValueType();
16108 unsigned NumBits = VT.getSizeInBits();
16111 Op = Op.getOperand(0);
16112 if (VT == MVT::i8) {
16113 // Zero extend to i32 since there is not an i8 bsr.
16115 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16118 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16119 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16120 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16122 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16125 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16126 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16129 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16131 // Finally xor with NumBits-1.
16132 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16133 DAG.getConstant(NumBits - 1, dl, OpVT));
16136 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16140 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16141 MVT VT = Op.getSimpleValueType();
16143 unsigned NumBits = VT.getSizeInBits();
16146 Op = Op.getOperand(0);
16147 if (VT == MVT::i8) {
16148 // Zero extend to i32 since there is not an i8 bsr.
16150 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16153 // Issue a bsr (scan bits in reverse).
16154 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16155 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16157 // And xor with NumBits-1.
16158 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16159 DAG.getConstant(NumBits - 1, dl, OpVT));
16162 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16166 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16167 MVT VT = Op.getSimpleValueType();
16168 unsigned NumBits = VT.getSizeInBits();
16170 Op = Op.getOperand(0);
16172 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16173 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16174 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16176 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16179 DAG.getConstant(NumBits, dl, VT),
16180 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16183 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16186 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16187 // ones, and then concatenate the result back.
16188 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16189 MVT VT = Op.getSimpleValueType();
16191 assert(VT.is256BitVector() && VT.isInteger() &&
16192 "Unsupported value type for operation");
16194 unsigned NumElems = VT.getVectorNumElements();
16197 // Extract the LHS vectors
16198 SDValue LHS = Op.getOperand(0);
16199 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16200 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16202 // Extract the RHS vectors
16203 SDValue RHS = Op.getOperand(1);
16204 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16205 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16207 MVT EltVT = VT.getVectorElementType();
16208 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16210 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16211 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16212 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16215 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16216 if (Op.getValueType() == MVT::i1)
16217 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16218 Op.getOperand(0), Op.getOperand(1));
16219 assert(Op.getSimpleValueType().is256BitVector() &&
16220 Op.getSimpleValueType().isInteger() &&
16221 "Only handle AVX 256-bit vector integer operation");
16222 return Lower256IntArith(Op, DAG);
16225 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16226 if (Op.getValueType() == MVT::i1)
16227 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16228 Op.getOperand(0), Op.getOperand(1));
16229 assert(Op.getSimpleValueType().is256BitVector() &&
16230 Op.getSimpleValueType().isInteger() &&
16231 "Only handle AVX 256-bit vector integer operation");
16232 return Lower256IntArith(Op, DAG);
16235 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16236 SelectionDAG &DAG) {
16238 MVT VT = Op.getSimpleValueType();
16241 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16243 // Decompose 256-bit ops into smaller 128-bit ops.
16244 if (VT.is256BitVector() && !Subtarget->hasInt256())
16245 return Lower256IntArith(Op, DAG);
16247 SDValue A = Op.getOperand(0);
16248 SDValue B = Op.getOperand(1);
16250 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16251 // pairs, multiply and truncate.
16252 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16253 if (Subtarget->hasInt256()) {
16254 if (VT == MVT::v32i8) {
16255 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16256 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16257 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16258 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16259 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16260 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16261 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16262 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16263 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16264 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16267 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16268 return DAG.getNode(
16269 ISD::TRUNCATE, dl, VT,
16270 DAG.getNode(ISD::MUL, dl, ExVT,
16271 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16272 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16275 assert(VT == MVT::v16i8 &&
16276 "Pre-AVX2 support only supports v16i8 multiplication");
16277 MVT ExVT = MVT::v8i16;
16279 // Extract the lo parts and sign extend to i16
16281 if (Subtarget->hasSSE41()) {
16282 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16283 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16285 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16286 -1, 4, -1, 5, -1, 6, -1, 7};
16287 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16288 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16289 ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);
16290 BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);
16291 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16292 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16295 // Extract the hi parts and sign extend to i16
16297 if (Subtarget->hasSSE41()) {
16298 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16299 -1, -1, -1, -1, -1, -1, -1, -1};
16300 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16301 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16302 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16303 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16305 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16306 -1, 12, -1, 13, -1, 14, -1, 15};
16307 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16308 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16309 AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);
16310 BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);
16311 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16312 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16315 // Multiply, mask the lower 8bits of the lo/hi results and pack
16316 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16317 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16318 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16319 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16320 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16323 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16324 if (VT == MVT::v4i32) {
16325 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16326 "Should not custom lower when pmuldq is available!");
16328 // Extract the odd parts.
16329 static const int UnpackMask[] = { 1, -1, 3, -1 };
16330 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16331 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16333 // Multiply the even parts.
16334 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16335 // Now multiply odd parts.
16336 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16338 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16339 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16341 // Merge the two vectors back together with a shuffle. This expands into 2
16343 static const int ShufMask[] = { 0, 4, 2, 6 };
16344 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16347 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16348 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16350 // Ahi = psrlqi(a, 32);
16351 // Bhi = psrlqi(b, 32);
16353 // AloBlo = pmuludq(a, b);
16354 // AloBhi = pmuludq(a, Bhi);
16355 // AhiBlo = pmuludq(Ahi, b);
16357 // AloBhi = psllqi(AloBhi, 32);
16358 // AhiBlo = psllqi(AhiBlo, 32);
16359 // return AloBlo + AloBhi + AhiBlo;
16361 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16362 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16364 // Bit cast to 32-bit vectors for MULUDQ
16365 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16366 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16367 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16368 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16369 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16370 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16372 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16373 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16374 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16376 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16377 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16379 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16380 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16383 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16384 assert(Subtarget->isTargetWin64() && "Unexpected target");
16385 EVT VT = Op.getValueType();
16386 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16387 "Unexpected return type for lowering");
16391 switch (Op->getOpcode()) {
16392 default: llvm_unreachable("Unexpected request for libcall!");
16393 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16394 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16395 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16396 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16397 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16398 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16402 SDValue InChain = DAG.getEntryNode();
16404 TargetLowering::ArgListTy Args;
16405 TargetLowering::ArgListEntry Entry;
16406 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16407 EVT ArgVT = Op->getOperand(i).getValueType();
16408 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16409 "Unexpected argument type for lowering");
16410 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16411 Entry.Node = StackPtr;
16412 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16414 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16415 Entry.Ty = PointerType::get(ArgTy,0);
16416 Entry.isSExt = false;
16417 Entry.isZExt = false;
16418 Args.push_back(Entry);
16421 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16424 TargetLowering::CallLoweringInfo CLI(DAG);
16425 CLI.setDebugLoc(dl).setChain(InChain)
16426 .setCallee(getLibcallCallingConv(LC),
16427 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16428 Callee, std::move(Args), 0)
16429 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16431 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16432 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16435 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16436 SelectionDAG &DAG) {
16437 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16438 EVT VT = Op0.getValueType();
16441 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16442 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16444 // PMULxD operations multiply each even value (starting at 0) of LHS with
16445 // the related value of RHS and produce a widen result.
16446 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16447 // => <2 x i64> <ae|cg>
16449 // In other word, to have all the results, we need to perform two PMULxD:
16450 // 1. one with the even values.
16451 // 2. one with the odd values.
16452 // To achieve #2, with need to place the odd values at an even position.
16454 // Place the odd value at an even position (basically, shift all values 1
16455 // step to the left):
16456 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16457 // <a|b|c|d> => <b|undef|d|undef>
16458 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16459 // <e|f|g|h> => <f|undef|h|undef>
16460 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16462 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16464 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16465 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16467 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16468 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16469 // => <2 x i64> <ae|cg>
16470 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16471 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16472 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16473 // => <2 x i64> <bf|dh>
16474 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16475 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16477 // Shuffle it back into the right order.
16478 SDValue Highs, Lows;
16479 if (VT == MVT::v8i32) {
16480 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16481 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16482 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16483 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16485 const int HighMask[] = {1, 5, 3, 7};
16486 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16487 const int LowMask[] = {0, 4, 2, 6};
16488 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16491 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16492 // unsigned multiply.
16493 if (IsSigned && !Subtarget->hasSSE41()) {
16495 DAG.getConstant(31, dl,
16496 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16497 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16498 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16499 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16500 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16502 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16503 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16506 // The first result of MUL_LOHI is actually the low value, followed by the
16508 SDValue Ops[] = {Lows, Highs};
16509 return DAG.getMergeValues(Ops, dl);
16512 // Return true if the requred (according to Opcode) shift-imm form is natively
16513 // supported by the Subtarget
16514 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16516 if (VT.getScalarSizeInBits() < 16)
16519 if (VT.is512BitVector() &&
16520 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16523 bool LShift = VT.is128BitVector() ||
16524 (VT.is256BitVector() && Subtarget->hasInt256());
16526 bool AShift = LShift && (Subtarget->hasVLX() ||
16527 (VT != MVT::v2i64 && VT != MVT::v4i64));
16528 return (Opcode == ISD::SRA) ? AShift : LShift;
16531 // The shift amount is a variable, but it is the same for all vector lanes.
16532 // These instrcutions are defined together with shift-immediate.
16534 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16536 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16539 // Return true if the requred (according to Opcode) variable-shift form is
16540 // natively supported by the Subtarget
16541 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16544 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16547 // vXi16 supported only on AVX-512, BWI
16548 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16551 if (VT.is512BitVector() || Subtarget->hasVLX())
16554 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16555 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16556 return (Opcode == ISD::SRA) ? AShift : LShift;
16559 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16560 const X86Subtarget *Subtarget) {
16561 MVT VT = Op.getSimpleValueType();
16563 SDValue R = Op.getOperand(0);
16564 SDValue Amt = Op.getOperand(1);
16566 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16567 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16569 // Optimize shl/srl/sra with constant shift amount.
16570 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16571 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16572 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16574 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16575 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16577 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16578 unsigned NumElts = VT.getVectorNumElements();
16579 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16581 if (Op.getOpcode() == ISD::SHL) {
16582 // Simple i8 add case
16584 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16586 // Make a large shift.
16587 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16589 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16590 // Zero out the rightmost bits.
16591 SmallVector<SDValue, 32> V(
16592 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16593 return DAG.getNode(ISD::AND, dl, VT, SHL,
16594 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16596 if (Op.getOpcode() == ISD::SRL) {
16597 // Make a large shift.
16598 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16600 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16601 // Zero out the leftmost bits.
16602 SmallVector<SDValue, 32> V(
16603 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16604 return DAG.getNode(ISD::AND, dl, VT, SRL,
16605 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16607 if (Op.getOpcode() == ISD::SRA) {
16608 if (ShiftAmt == 7) {
16609 // R s>> 7 === R s< 0
16610 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16611 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16614 // R s>> a === ((R u>> a) ^ m) - m
16615 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16616 SmallVector<SDValue, 32> V(NumElts,
16617 DAG.getConstant(128 >> ShiftAmt, dl,
16619 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16620 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16621 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16624 llvm_unreachable("Unknown shift opcode.");
16629 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16630 if (!Subtarget->is64Bit() &&
16631 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16632 Amt.getOpcode() == ISD::BITCAST &&
16633 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16634 Amt = Amt.getOperand(0);
16635 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16636 VT.getVectorNumElements();
16637 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16638 uint64_t ShiftAmt = 0;
16639 for (unsigned i = 0; i != Ratio; ++i) {
16640 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16644 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16646 // Check remaining shift amounts.
16647 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16648 uint64_t ShAmt = 0;
16649 for (unsigned j = 0; j != Ratio; ++j) {
16650 ConstantSDNode *C =
16651 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16655 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16657 if (ShAmt != ShiftAmt)
16660 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16666 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16667 const X86Subtarget* Subtarget) {
16668 MVT VT = Op.getSimpleValueType();
16670 SDValue R = Op.getOperand(0);
16671 SDValue Amt = Op.getOperand(1);
16673 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16674 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16676 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16677 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16679 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16681 EVT EltVT = VT.getVectorElementType();
16683 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16684 // Check if this build_vector node is doing a splat.
16685 // If so, then set BaseShAmt equal to the splat value.
16686 BaseShAmt = BV->getSplatValue();
16687 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16688 BaseShAmt = SDValue();
16690 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16691 Amt = Amt.getOperand(0);
16693 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16694 if (SVN && SVN->isSplat()) {
16695 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16696 SDValue InVec = Amt.getOperand(0);
16697 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16698 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16699 "Unexpected shuffle index found!");
16700 BaseShAmt = InVec.getOperand(SplatIdx);
16701 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16702 if (ConstantSDNode *C =
16703 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16704 if (C->getZExtValue() == SplatIdx)
16705 BaseShAmt = InVec.getOperand(1);
16710 // Avoid introducing an extract element from a shuffle.
16711 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16712 DAG.getIntPtrConstant(SplatIdx, dl));
16716 if (BaseShAmt.getNode()) {
16717 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16718 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16719 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16720 else if (EltVT.bitsLT(MVT::i32))
16721 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16723 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16727 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16728 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16729 Amt.getOpcode() == ISD::BITCAST &&
16730 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16731 Amt = Amt.getOperand(0);
16732 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16733 VT.getVectorNumElements();
16734 std::vector<SDValue> Vals(Ratio);
16735 for (unsigned i = 0; i != Ratio; ++i)
16736 Vals[i] = Amt.getOperand(i);
16737 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16738 for (unsigned j = 0; j != Ratio; ++j)
16739 if (Vals[j] != Amt.getOperand(i + j))
16742 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16747 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16748 SelectionDAG &DAG) {
16749 MVT VT = Op.getSimpleValueType();
16751 SDValue R = Op.getOperand(0);
16752 SDValue Amt = Op.getOperand(1);
16754 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16755 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16757 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16760 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16763 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16766 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16767 // shifts per-lane and then shuffle the partial results back together.
16768 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16769 // Splat the shift amounts so the scalar shifts above will catch it.
16770 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16771 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16772 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16773 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16774 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16777 // If possible, lower this packed shift into a vector multiply instead of
16778 // expanding it into a sequence of scalar shifts.
16779 // Do this only if the vector shift count is a constant build_vector.
16780 if (Op.getOpcode() == ISD::SHL &&
16781 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16782 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16783 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16784 SmallVector<SDValue, 8> Elts;
16785 EVT SVT = VT.getScalarType();
16786 unsigned SVTBits = SVT.getSizeInBits();
16787 const APInt &One = APInt(SVTBits, 1);
16788 unsigned NumElems = VT.getVectorNumElements();
16790 for (unsigned i=0; i !=NumElems; ++i) {
16791 SDValue Op = Amt->getOperand(i);
16792 if (Op->getOpcode() == ISD::UNDEF) {
16793 Elts.push_back(Op);
16797 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16798 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16799 uint64_t ShAmt = C.getZExtValue();
16800 if (ShAmt >= SVTBits) {
16801 Elts.push_back(DAG.getUNDEF(SVT));
16804 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16806 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16807 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16810 // Lower SHL with variable shift amount.
16811 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16812 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16814 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16815 DAG.getConstant(0x3f800000U, dl, VT));
16816 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16817 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16818 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16821 // If possible, lower this shift as a sequence of two shifts by
16822 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16824 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16826 // Could be rewritten as:
16827 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16829 // The advantage is that the two shifts from the example would be
16830 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16831 // the vector shift into four scalar shifts plus four pairs of vector
16833 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16834 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16835 unsigned TargetOpcode = X86ISD::MOVSS;
16836 bool CanBeSimplified;
16837 // The splat value for the first packed shift (the 'X' from the example).
16838 SDValue Amt1 = Amt->getOperand(0);
16839 // The splat value for the second packed shift (the 'Y' from the example).
16840 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16841 Amt->getOperand(2);
16843 // See if it is possible to replace this node with a sequence of
16844 // two shifts followed by a MOVSS/MOVSD
16845 if (VT == MVT::v4i32) {
16846 // Check if it is legal to use a MOVSS.
16847 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16848 Amt2 == Amt->getOperand(3);
16849 if (!CanBeSimplified) {
16850 // Otherwise, check if we can still simplify this node using a MOVSD.
16851 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16852 Amt->getOperand(2) == Amt->getOperand(3);
16853 TargetOpcode = X86ISD::MOVSD;
16854 Amt2 = Amt->getOperand(2);
16857 // Do similar checks for the case where the machine value type
16859 CanBeSimplified = Amt1 == Amt->getOperand(1);
16860 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16861 CanBeSimplified = Amt2 == Amt->getOperand(i);
16863 if (!CanBeSimplified) {
16864 TargetOpcode = X86ISD::MOVSD;
16865 CanBeSimplified = true;
16866 Amt2 = Amt->getOperand(4);
16867 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16868 CanBeSimplified = Amt1 == Amt->getOperand(i);
16869 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16870 CanBeSimplified = Amt2 == Amt->getOperand(j);
16874 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16875 isa<ConstantSDNode>(Amt2)) {
16876 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16877 EVT CastVT = MVT::v4i32;
16879 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16880 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16882 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16883 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16884 if (TargetOpcode == X86ISD::MOVSD)
16885 CastVT = MVT::v2i64;
16886 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16887 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16888 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16890 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16894 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16895 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
16896 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
16898 SDValue VSelM = DAG.getConstant(0x80, dl, VT);
16899 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16900 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16902 // r = VSELECT(r, shl(r, 4), a);
16903 SDValue M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(4, dl, VT));
16904 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16907 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16908 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16909 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16911 // r = VSELECT(r, shl(r, 2), a);
16912 M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(2, dl, VT));
16913 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16916 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16917 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16918 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16920 // return VSELECT(r, r+r, a);
16921 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16922 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16926 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16927 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16928 // solution better.
16929 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16930 MVT ExtVT = MVT::v8i32;
16932 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16933 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
16934 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
16935 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16936 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
16939 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
16940 MVT ExtVT = MVT::v8i32;
16941 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
16942 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
16943 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
16944 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
16945 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
16946 ALo = DAG.getNode(ISD::BITCAST, dl, ExtVT, ALo);
16947 AHi = DAG.getNode(ISD::BITCAST, dl, ExtVT, AHi);
16948 RLo = DAG.getNode(ISD::BITCAST, dl, ExtVT, RLo);
16949 RHi = DAG.getNode(ISD::BITCAST, dl, ExtVT, RHi);
16950 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
16951 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
16952 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
16953 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
16954 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
16957 // Decompose 256-bit shifts into smaller 128-bit shifts.
16958 if (VT.is256BitVector()) {
16959 unsigned NumElems = VT.getVectorNumElements();
16960 MVT EltVT = VT.getVectorElementType();
16961 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16963 // Extract the two vectors
16964 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16965 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16967 // Recreate the shift amount vectors
16968 SDValue Amt1, Amt2;
16969 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16970 // Constant shift amount
16971 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16972 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16973 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16975 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16976 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16978 // Variable shift amount
16979 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16980 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16983 // Issue new vector shifts for the smaller types
16984 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16985 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16987 // Concatenate the result back
16988 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16994 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16995 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16996 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16997 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16998 // has only one use.
16999 SDNode *N = Op.getNode();
17000 SDValue LHS = N->getOperand(0);
17001 SDValue RHS = N->getOperand(1);
17002 unsigned BaseOp = 0;
17005 switch (Op.getOpcode()) {
17006 default: llvm_unreachable("Unknown ovf instruction!");
17008 // A subtract of one will be selected as a INC. Note that INC doesn't
17009 // set CF, so we can't do this for UADDO.
17010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17012 BaseOp = X86ISD::INC;
17013 Cond = X86::COND_O;
17016 BaseOp = X86ISD::ADD;
17017 Cond = X86::COND_O;
17020 BaseOp = X86ISD::ADD;
17021 Cond = X86::COND_B;
17024 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17025 // set CF, so we can't do this for USUBO.
17026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17028 BaseOp = X86ISD::DEC;
17029 Cond = X86::COND_O;
17032 BaseOp = X86ISD::SUB;
17033 Cond = X86::COND_O;
17036 BaseOp = X86ISD::SUB;
17037 Cond = X86::COND_B;
17040 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17041 Cond = X86::COND_O;
17043 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17044 if (N->getValueType(0) == MVT::i8) {
17045 BaseOp = X86ISD::UMUL8;
17046 Cond = X86::COND_O;
17049 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17051 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17054 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17055 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17056 SDValue(Sum.getNode(), 2));
17058 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17062 // Also sets EFLAGS.
17063 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17064 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17067 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17068 DAG.getConstant(Cond, DL, MVT::i32),
17069 SDValue(Sum.getNode(), 1));
17071 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17074 /// Returns true if the operand type is exactly twice the native width, and
17075 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17076 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17077 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17078 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17079 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17082 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17083 else if (OpWidth == 128)
17084 return Subtarget->hasCmpxchg16b();
17089 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17090 return needsCmpXchgNb(SI->getValueOperand()->getType());
17093 // Note: this turns large loads into lock cmpxchg8b/16b.
17094 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17095 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17096 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17097 return needsCmpXchgNb(PTy->getElementType());
17100 TargetLoweringBase::AtomicRMWExpansionKind
17101 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17102 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17103 const Type *MemType = AI->getType();
17105 // If the operand is too big, we must see if cmpxchg8/16b is available
17106 // and default to library calls otherwise.
17107 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17108 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17109 : AtomicRMWExpansionKind::None;
17112 AtomicRMWInst::BinOp Op = AI->getOperation();
17115 llvm_unreachable("Unknown atomic operation");
17116 case AtomicRMWInst::Xchg:
17117 case AtomicRMWInst::Add:
17118 case AtomicRMWInst::Sub:
17119 // It's better to use xadd, xsub or xchg for these in all cases.
17120 return AtomicRMWExpansionKind::None;
17121 case AtomicRMWInst::Or:
17122 case AtomicRMWInst::And:
17123 case AtomicRMWInst::Xor:
17124 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17125 // prefix to a normal instruction for these operations.
17126 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17127 : AtomicRMWExpansionKind::None;
17128 case AtomicRMWInst::Nand:
17129 case AtomicRMWInst::Max:
17130 case AtomicRMWInst::Min:
17131 case AtomicRMWInst::UMax:
17132 case AtomicRMWInst::UMin:
17133 // These always require a non-trivial set of data operations on x86. We must
17134 // use a cmpxchg loop.
17135 return AtomicRMWExpansionKind::CmpXChg;
17139 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17140 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17141 // no-sse2). There isn't any reason to disable it if the target processor
17143 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17147 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17148 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17149 const Type *MemType = AI->getType();
17150 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17151 // there is no benefit in turning such RMWs into loads, and it is actually
17152 // harmful as it introduces a mfence.
17153 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17156 auto Builder = IRBuilder<>(AI);
17157 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17158 auto SynchScope = AI->getSynchScope();
17159 // We must restrict the ordering to avoid generating loads with Release or
17160 // ReleaseAcquire orderings.
17161 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17162 auto Ptr = AI->getPointerOperand();
17164 // Before the load we need a fence. Here is an example lifted from
17165 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17168 // x.store(1, relaxed);
17169 // r1 = y.fetch_add(0, release);
17171 // y.fetch_add(42, acquire);
17172 // r2 = x.load(relaxed);
17173 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17174 // lowered to just a load without a fence. A mfence flushes the store buffer,
17175 // making the optimization clearly correct.
17176 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17177 // otherwise, we might be able to be more agressive on relaxed idempotent
17178 // rmw. In practice, they do not look useful, so we don't try to be
17179 // especially clever.
17180 if (SynchScope == SingleThread)
17181 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17182 // the IR level, so we must wrap it in an intrinsic.
17185 if (!hasMFENCE(*Subtarget))
17186 // FIXME: it might make sense to use a locked operation here but on a
17187 // different cache-line to prevent cache-line bouncing. In practice it
17188 // is probably a small win, and x86 processors without mfence are rare
17189 // enough that we do not bother.
17193 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17194 Builder.CreateCall(MFence, {});
17196 // Finally we can emit the atomic load.
17197 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17198 AI->getType()->getPrimitiveSizeInBits());
17199 Loaded->setAtomic(Order, SynchScope);
17200 AI->replaceAllUsesWith(Loaded);
17201 AI->eraseFromParent();
17205 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17206 SelectionDAG &DAG) {
17208 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17209 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17210 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17211 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17213 // The only fence that needs an instruction is a sequentially-consistent
17214 // cross-thread fence.
17215 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17216 if (hasMFENCE(*Subtarget))
17217 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17219 SDValue Chain = Op.getOperand(0);
17220 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17222 DAG.getRegister(X86::ESP, MVT::i32), // Base
17223 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17224 DAG.getRegister(0, MVT::i32), // Index
17225 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17226 DAG.getRegister(0, MVT::i32), // Segment.
17230 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17231 return SDValue(Res, 0);
17234 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17235 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17238 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17239 SelectionDAG &DAG) {
17240 MVT T = Op.getSimpleValueType();
17244 switch(T.SimpleTy) {
17245 default: llvm_unreachable("Invalid value type!");
17246 case MVT::i8: Reg = X86::AL; size = 1; break;
17247 case MVT::i16: Reg = X86::AX; size = 2; break;
17248 case MVT::i32: Reg = X86::EAX; size = 4; break;
17250 assert(Subtarget->is64Bit() && "Node not type legal!");
17251 Reg = X86::RAX; size = 8;
17254 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17255 Op.getOperand(2), SDValue());
17256 SDValue Ops[] = { cpIn.getValue(0),
17259 DAG.getTargetConstant(size, DL, MVT::i8),
17260 cpIn.getValue(1) };
17261 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17262 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17263 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17267 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17268 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17269 MVT::i32, cpOut.getValue(2));
17270 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17271 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17274 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17275 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17276 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17280 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17281 SelectionDAG &DAG) {
17282 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17283 MVT DstVT = Op.getSimpleValueType();
17285 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17286 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17287 if (DstVT != MVT::f64)
17288 // This conversion needs to be expanded.
17291 SDValue InVec = Op->getOperand(0);
17293 unsigned NumElts = SrcVT.getVectorNumElements();
17294 EVT SVT = SrcVT.getVectorElementType();
17296 // Widen the vector in input in the case of MVT::v2i32.
17297 // Example: from MVT::v2i32 to MVT::v4i32.
17298 SmallVector<SDValue, 16> Elts;
17299 for (unsigned i = 0, e = NumElts; i != e; ++i)
17300 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17301 DAG.getIntPtrConstant(i, dl)));
17303 // Explicitly mark the extra elements as Undef.
17304 Elts.append(NumElts, DAG.getUNDEF(SVT));
17306 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17307 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17308 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17309 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17310 DAG.getIntPtrConstant(0, dl));
17313 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17314 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17315 assert((DstVT == MVT::i64 ||
17316 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17317 "Unexpected custom BITCAST");
17318 // i64 <=> MMX conversions are Legal.
17319 if (SrcVT==MVT::i64 && DstVT.isVector())
17321 if (DstVT==MVT::i64 && SrcVT.isVector())
17323 // MMX <=> MMX conversions are Legal.
17324 if (SrcVT.isVector() && DstVT.isVector())
17326 // All other conversions need to be expanded.
17330 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17331 SelectionDAG &DAG) {
17332 SDNode *Node = Op.getNode();
17335 Op = Op.getOperand(0);
17336 EVT VT = Op.getValueType();
17337 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17338 "CTPOP lowering only implemented for 128/256-bit wide vector types");
17340 unsigned NumElts = VT.getVectorNumElements();
17341 EVT EltVT = VT.getVectorElementType();
17342 unsigned Len = EltVT.getSizeInBits();
17344 // This is the vectorized version of the "best" algorithm from
17345 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17346 // with a minor tweak to use a series of adds + shifts instead of vector
17347 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
17349 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
17350 // v8i32 => Always profitable
17352 // FIXME: There a couple of possible improvements:
17354 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
17355 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
17357 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
17358 "CTPOP not implemented for this vector element type.");
17360 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
17361 // extra legalization.
17362 bool NeedsBitcast = EltVT == MVT::i32;
17363 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
17365 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl,
17367 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl,
17369 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl,
17372 // v = v - ((v >> 1) & 0x55555555...)
17373 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, dl, EltVT));
17374 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
17375 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
17377 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17379 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
17380 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
17382 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
17384 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
17385 if (VT != And.getValueType())
17386 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17387 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
17389 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17390 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
17391 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
17392 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, dl, EltVT));
17393 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
17395 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
17396 if (NeedsBitcast) {
17397 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17398 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
17399 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
17402 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
17403 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
17404 if (VT != AndRHS.getValueType()) {
17405 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
17406 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
17408 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
17410 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17411 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, dl, EltVT));
17412 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
17413 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
17414 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17416 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
17417 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
17418 if (NeedsBitcast) {
17419 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17420 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
17422 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
17423 if (VT != And.getValueType())
17424 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17426 // The algorithm mentioned above uses:
17427 // v = (v * 0x01010101...) >> (Len - 8)
17429 // Change it to use vector adds + vector shifts which yield faster results on
17430 // Haswell than using vector integer multiplication.
17432 // For i32 elements:
17433 // v = v + (v >> 8)
17434 // v = v + (v >> 16)
17436 // For i64 elements:
17437 // v = v + (v >> 8)
17438 // v = v + (v >> 16)
17439 // v = v + (v >> 32)
17442 SmallVector<SDValue, 8> Csts;
17443 for (unsigned i = 8; i <= Len/2; i *= 2) {
17444 Csts.assign(NumElts, DAG.getConstant(i, dl, EltVT));
17445 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
17446 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
17447 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17451 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
17452 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), dl,
17454 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
17455 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
17456 if (NeedsBitcast) {
17457 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17458 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
17460 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
17461 if (VT != And.getValueType())
17462 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17467 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17468 SDNode *Node = Op.getNode();
17470 EVT T = Node->getValueType(0);
17471 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17472 DAG.getConstant(0, dl, T), Node->getOperand(2));
17473 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17474 cast<AtomicSDNode>(Node)->getMemoryVT(),
17475 Node->getOperand(0),
17476 Node->getOperand(1), negOp,
17477 cast<AtomicSDNode>(Node)->getMemOperand(),
17478 cast<AtomicSDNode>(Node)->getOrdering(),
17479 cast<AtomicSDNode>(Node)->getSynchScope());
17482 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17483 SDNode *Node = Op.getNode();
17485 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17487 // Convert seq_cst store -> xchg
17488 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17489 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17490 // (The only way to get a 16-byte store is cmpxchg16b)
17491 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17492 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17493 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17494 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17495 cast<AtomicSDNode>(Node)->getMemoryVT(),
17496 Node->getOperand(0),
17497 Node->getOperand(1), Node->getOperand(2),
17498 cast<AtomicSDNode>(Node)->getMemOperand(),
17499 cast<AtomicSDNode>(Node)->getOrdering(),
17500 cast<AtomicSDNode>(Node)->getSynchScope());
17501 return Swap.getValue(1);
17503 // Other atomic stores have a simple pattern.
17507 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17508 EVT VT = Op.getNode()->getSimpleValueType(0);
17510 // Let legalize expand this if it isn't a legal type yet.
17511 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17514 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17517 bool ExtraOp = false;
17518 switch (Op.getOpcode()) {
17519 default: llvm_unreachable("Invalid code");
17520 case ISD::ADDC: Opc = X86ISD::ADD; break;
17521 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17522 case ISD::SUBC: Opc = X86ISD::SUB; break;
17523 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17527 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17529 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17530 Op.getOperand(1), Op.getOperand(2));
17533 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17534 SelectionDAG &DAG) {
17535 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17537 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17538 // which returns the values as { float, float } (in XMM0) or
17539 // { double, double } (which is returned in XMM0, XMM1).
17541 SDValue Arg = Op.getOperand(0);
17542 EVT ArgVT = Arg.getValueType();
17543 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17545 TargetLowering::ArgListTy Args;
17546 TargetLowering::ArgListEntry Entry;
17550 Entry.isSExt = false;
17551 Entry.isZExt = false;
17552 Args.push_back(Entry);
17554 bool isF64 = ArgVT == MVT::f64;
17555 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17556 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17557 // the results are returned via SRet in memory.
17558 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17560 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17562 Type *RetTy = isF64
17563 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17564 : (Type*)VectorType::get(ArgTy, 4);
17566 TargetLowering::CallLoweringInfo CLI(DAG);
17567 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17568 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17570 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17573 // Returned in xmm0 and xmm1.
17574 return CallResult.first;
17576 // Returned in bits 0:31 and 32:64 xmm0.
17577 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17578 CallResult.first, DAG.getIntPtrConstant(0, dl));
17579 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17580 CallResult.first, DAG.getIntPtrConstant(1, dl));
17581 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17582 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17585 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17586 SelectionDAG &DAG) {
17587 assert(Subtarget->hasAVX512() &&
17588 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17590 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17591 EVT VT = N->getValue().getValueType();
17592 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17595 // X86 scatter kills mask register, so its type should be added to
17596 // the list of return values
17597 if (N->getNumValues() == 1) {
17598 SDValue Index = N->getIndex();
17599 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17600 !Index.getValueType().is512BitVector())
17601 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17603 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17604 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17605 N->getOperand(3), Index };
17607 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17608 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17609 return SDValue(NewScatter.getNode(), 0);
17614 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17615 SelectionDAG &DAG) {
17616 assert(Subtarget->hasAVX512() &&
17617 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17619 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17620 EVT VT = Op.getValueType();
17621 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17624 SDValue Index = N->getIndex();
17625 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17626 !Index.getValueType().is512BitVector()) {
17627 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17628 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17629 N->getOperand(3), Index };
17630 DAG.UpdateNodeOperands(N, Ops);
17635 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
17636 SelectionDAG &DAG) const {
17637 // TODO: Eventually, the lowering of these nodes should be informed by or
17638 // deferred to the GC strategy for the function in which they appear. For
17639 // now, however, they must be lowered to something. Since they are logically
17640 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17641 // require special handling for these nodes), lower them as literal NOOPs for
17643 SmallVector<SDValue, 2> Ops;
17645 Ops.push_back(Op.getOperand(0));
17646 if (Op->getGluedNode())
17647 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17650 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17651 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17656 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
17657 SelectionDAG &DAG) const {
17658 // TODO: Eventually, the lowering of these nodes should be informed by or
17659 // deferred to the GC strategy for the function in which they appear. For
17660 // now, however, they must be lowered to something. Since they are logically
17661 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17662 // require special handling for these nodes), lower them as literal NOOPs for
17664 SmallVector<SDValue, 2> Ops;
17666 Ops.push_back(Op.getOperand(0));
17667 if (Op->getGluedNode())
17668 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17671 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17672 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17677 /// LowerOperation - Provide custom lowering hooks for some operations.
17679 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17680 switch (Op.getOpcode()) {
17681 default: llvm_unreachable("Should not custom lower this!");
17682 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17683 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17684 return LowerCMP_SWAP(Op, Subtarget, DAG);
17685 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17686 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17687 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17688 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17689 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17690 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17691 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17692 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17693 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17694 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17695 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17696 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17697 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17698 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17699 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17700 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17701 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17702 case ISD::SHL_PARTS:
17703 case ISD::SRA_PARTS:
17704 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17705 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17706 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17707 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17708 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17709 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17710 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17711 case ISD::SIGN_EXTEND_VECTOR_INREG:
17712 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
17713 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17714 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17715 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17716 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17718 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17719 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17720 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17721 case ISD::SETCC: return LowerSETCC(Op, DAG);
17722 case ISD::SELECT: return LowerSELECT(Op, DAG);
17723 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17724 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17725 case ISD::VASTART: return LowerVASTART(Op, DAG);
17726 case ISD::VAARG: return LowerVAARG(Op, DAG);
17727 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17728 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17729 case ISD::INTRINSIC_VOID:
17730 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17731 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17732 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17733 case ISD::FRAME_TO_ARGS_OFFSET:
17734 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17735 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17736 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17737 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17738 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17739 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17740 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17741 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17742 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17743 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17744 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17745 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17746 case ISD::UMUL_LOHI:
17747 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17750 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17756 case ISD::UMULO: return LowerXALUO(Op, DAG);
17757 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17758 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17762 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17763 case ISD::ADD: return LowerADD(Op, DAG);
17764 case ISD::SUB: return LowerSUB(Op, DAG);
17765 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17766 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
17767 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
17768 case ISD::GC_TRANSITION_START:
17769 return LowerGC_TRANSITION_START(Op, DAG);
17770 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
17774 /// ReplaceNodeResults - Replace a node with an illegal result type
17775 /// with a new node built out of custom code.
17776 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17777 SmallVectorImpl<SDValue>&Results,
17778 SelectionDAG &DAG) const {
17780 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17781 switch (N->getOpcode()) {
17783 llvm_unreachable("Do not know how to custom type legalize this operation!");
17784 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17785 case X86ISD::FMINC:
17787 case X86ISD::FMAXC:
17788 case X86ISD::FMAX: {
17789 EVT VT = N->getValueType(0);
17790 if (VT != MVT::v2f32)
17791 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17792 SDValue UNDEF = DAG.getUNDEF(VT);
17793 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17794 N->getOperand(0), UNDEF);
17795 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17796 N->getOperand(1), UNDEF);
17797 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17800 case ISD::SIGN_EXTEND_INREG:
17805 // We don't want to expand or promote these.
17812 case ISD::UDIVREM: {
17813 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17814 Results.push_back(V);
17817 case ISD::FP_TO_SINT:
17818 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
17819 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
17820 if (N->getOperand(0).getValueType() == MVT::f16)
17823 case ISD::FP_TO_UINT: {
17824 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17826 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17829 std::pair<SDValue,SDValue> Vals =
17830 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17831 SDValue FIST = Vals.first, StackSlot = Vals.second;
17832 if (FIST.getNode()) {
17833 EVT VT = N->getValueType(0);
17834 // Return a load from the stack slot.
17835 if (StackSlot.getNode())
17836 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17837 MachinePointerInfo(),
17838 false, false, false, 0));
17840 Results.push_back(FIST);
17844 case ISD::UINT_TO_FP: {
17845 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17846 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17847 N->getValueType(0) != MVT::v2f32)
17849 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17851 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
17853 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17854 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17855 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17856 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17857 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17858 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17861 case ISD::FP_ROUND: {
17862 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17864 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17865 Results.push_back(V);
17868 case ISD::FP_EXTEND: {
17869 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
17870 // No other ValueType for FP_EXTEND should reach this point.
17871 assert(N->getValueType(0) == MVT::v2f32 &&
17872 "Do not know how to legalize this Node");
17875 case ISD::INTRINSIC_W_CHAIN: {
17876 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17878 default : llvm_unreachable("Do not know how to custom type "
17879 "legalize this intrinsic operation!");
17880 case Intrinsic::x86_rdtsc:
17881 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17883 case Intrinsic::x86_rdtscp:
17884 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17886 case Intrinsic::x86_rdpmc:
17887 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17890 case ISD::READCYCLECOUNTER: {
17891 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17894 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17895 EVT T = N->getValueType(0);
17896 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17897 bool Regs64bit = T == MVT::i128;
17898 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17899 SDValue cpInL, cpInH;
17900 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17901 DAG.getConstant(0, dl, HalfT));
17902 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17903 DAG.getConstant(1, dl, HalfT));
17904 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17905 Regs64bit ? X86::RAX : X86::EAX,
17907 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17908 Regs64bit ? X86::RDX : X86::EDX,
17909 cpInH, cpInL.getValue(1));
17910 SDValue swapInL, swapInH;
17911 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17912 DAG.getConstant(0, dl, HalfT));
17913 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17914 DAG.getConstant(1, dl, HalfT));
17915 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17916 Regs64bit ? X86::RBX : X86::EBX,
17917 swapInL, cpInH.getValue(1));
17918 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17919 Regs64bit ? X86::RCX : X86::ECX,
17920 swapInH, swapInL.getValue(1));
17921 SDValue Ops[] = { swapInH.getValue(0),
17923 swapInH.getValue(1) };
17924 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17925 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17926 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17927 X86ISD::LCMPXCHG8_DAG;
17928 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17929 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17930 Regs64bit ? X86::RAX : X86::EAX,
17931 HalfT, Result.getValue(1));
17932 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17933 Regs64bit ? X86::RDX : X86::EDX,
17934 HalfT, cpOutL.getValue(2));
17935 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17937 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17938 MVT::i32, cpOutH.getValue(2));
17940 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17941 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
17942 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17944 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17945 Results.push_back(Success);
17946 Results.push_back(EFLAGS.getValue(1));
17949 case ISD::ATOMIC_SWAP:
17950 case ISD::ATOMIC_LOAD_ADD:
17951 case ISD::ATOMIC_LOAD_SUB:
17952 case ISD::ATOMIC_LOAD_AND:
17953 case ISD::ATOMIC_LOAD_OR:
17954 case ISD::ATOMIC_LOAD_XOR:
17955 case ISD::ATOMIC_LOAD_NAND:
17956 case ISD::ATOMIC_LOAD_MIN:
17957 case ISD::ATOMIC_LOAD_MAX:
17958 case ISD::ATOMIC_LOAD_UMIN:
17959 case ISD::ATOMIC_LOAD_UMAX:
17960 case ISD::ATOMIC_LOAD: {
17961 // Delegate to generic TypeLegalization. Situations we can really handle
17962 // should have already been dealt with by AtomicExpandPass.cpp.
17965 case ISD::BITCAST: {
17966 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17967 EVT DstVT = N->getValueType(0);
17968 EVT SrcVT = N->getOperand(0)->getValueType(0);
17970 if (SrcVT != MVT::f64 ||
17971 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17974 unsigned NumElts = DstVT.getVectorNumElements();
17975 EVT SVT = DstVT.getVectorElementType();
17976 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17977 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17978 MVT::v2f64, N->getOperand(0));
17979 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17981 if (ExperimentalVectorWideningLegalization) {
17982 // If we are legalizing vectors by widening, we already have the desired
17983 // legal vector type, just return it.
17984 Results.push_back(ToVecInt);
17988 SmallVector<SDValue, 8> Elts;
17989 for (unsigned i = 0, e = NumElts; i != e; ++i)
17990 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17991 ToVecInt, DAG.getIntPtrConstant(i, dl)));
17993 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17998 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17999 switch ((X86ISD::NodeType)Opcode) {
18000 case X86ISD::FIRST_NUMBER: break;
18001 case X86ISD::BSF: return "X86ISD::BSF";
18002 case X86ISD::BSR: return "X86ISD::BSR";
18003 case X86ISD::SHLD: return "X86ISD::SHLD";
18004 case X86ISD::SHRD: return "X86ISD::SHRD";
18005 case X86ISD::FAND: return "X86ISD::FAND";
18006 case X86ISD::FANDN: return "X86ISD::FANDN";
18007 case X86ISD::FOR: return "X86ISD::FOR";
18008 case X86ISD::FXOR: return "X86ISD::FXOR";
18009 case X86ISD::FSRL: return "X86ISD::FSRL";
18010 case X86ISD::FILD: return "X86ISD::FILD";
18011 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18012 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18013 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18014 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18015 case X86ISD::FLD: return "X86ISD::FLD";
18016 case X86ISD::FST: return "X86ISD::FST";
18017 case X86ISD::CALL: return "X86ISD::CALL";
18018 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18019 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18020 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18021 case X86ISD::BT: return "X86ISD::BT";
18022 case X86ISD::CMP: return "X86ISD::CMP";
18023 case X86ISD::COMI: return "X86ISD::COMI";
18024 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18025 case X86ISD::CMPM: return "X86ISD::CMPM";
18026 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18027 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18028 case X86ISD::SETCC: return "X86ISD::SETCC";
18029 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18030 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18031 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18032 case X86ISD::CMOV: return "X86ISD::CMOV";
18033 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18034 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18035 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18036 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18037 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18038 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18039 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18040 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18041 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18042 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18043 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18044 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18045 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18046 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18047 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18048 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18049 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18050 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18051 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18052 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18053 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18054 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18055 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18056 case X86ISD::HADD: return "X86ISD::HADD";
18057 case X86ISD::HSUB: return "X86ISD::HSUB";
18058 case X86ISD::FHADD: return "X86ISD::FHADD";
18059 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18060 case X86ISD::UMAX: return "X86ISD::UMAX";
18061 case X86ISD::UMIN: return "X86ISD::UMIN";
18062 case X86ISD::SMAX: return "X86ISD::SMAX";
18063 case X86ISD::SMIN: return "X86ISD::SMIN";
18064 case X86ISD::FMAX: return "X86ISD::FMAX";
18065 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18066 case X86ISD::FMIN: return "X86ISD::FMIN";
18067 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18068 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18069 case X86ISD::FMINC: return "X86ISD::FMINC";
18070 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18071 case X86ISD::FRCP: return "X86ISD::FRCP";
18072 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18073 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18074 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18075 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18076 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18077 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18078 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18079 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18080 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18081 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18082 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18083 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18084 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18085 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18086 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18087 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18088 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18089 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18090 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18091 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18092 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18093 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18094 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18095 case X86ISD::VSHL: return "X86ISD::VSHL";
18096 case X86ISD::VSRL: return "X86ISD::VSRL";
18097 case X86ISD::VSRA: return "X86ISD::VSRA";
18098 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18099 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18100 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18101 case X86ISD::CMPP: return "X86ISD::CMPP";
18102 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18103 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18104 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18105 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18106 case X86ISD::ADD: return "X86ISD::ADD";
18107 case X86ISD::SUB: return "X86ISD::SUB";
18108 case X86ISD::ADC: return "X86ISD::ADC";
18109 case X86ISD::SBB: return "X86ISD::SBB";
18110 case X86ISD::SMUL: return "X86ISD::SMUL";
18111 case X86ISD::UMUL: return "X86ISD::UMUL";
18112 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18113 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18114 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18115 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18116 case X86ISD::INC: return "X86ISD::INC";
18117 case X86ISD::DEC: return "X86ISD::DEC";
18118 case X86ISD::OR: return "X86ISD::OR";
18119 case X86ISD::XOR: return "X86ISD::XOR";
18120 case X86ISD::AND: return "X86ISD::AND";
18121 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18122 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18123 case X86ISD::PTEST: return "X86ISD::PTEST";
18124 case X86ISD::TESTP: return "X86ISD::TESTP";
18125 case X86ISD::TESTM: return "X86ISD::TESTM";
18126 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18127 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18128 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18129 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18130 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18131 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18132 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18133 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18134 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18135 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18136 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18137 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18138 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18139 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18140 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18141 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18142 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18143 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18144 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18145 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18146 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18147 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18148 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18149 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18150 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18151 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18152 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18153 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18154 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18155 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18156 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18157 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18158 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18159 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18160 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18161 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18162 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18163 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18164 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18165 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18166 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18167 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18168 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18169 case X86ISD::SAHF: return "X86ISD::SAHF";
18170 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18171 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18172 case X86ISD::FMADD: return "X86ISD::FMADD";
18173 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18174 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18175 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18176 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18177 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18178 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18179 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18180 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18181 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18182 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18183 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18184 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18185 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18186 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18187 case X86ISD::XTEST: return "X86ISD::XTEST";
18188 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18189 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18190 case X86ISD::SELECT: return "X86ISD::SELECT";
18191 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18192 case X86ISD::RCP28: return "X86ISD::RCP28";
18193 case X86ISD::EXP2: return "X86ISD::EXP2";
18194 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18195 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18196 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18197 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18198 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18199 case X86ISD::ADDS: return "X86ISD::ADDS";
18200 case X86ISD::SUBS: return "X86ISD::SUBS";
18205 // isLegalAddressingMode - Return true if the addressing mode represented
18206 // by AM is legal for this target, for a load/store of the specified type.
18207 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18209 // X86 supports extremely general addressing modes.
18210 CodeModel::Model M = getTargetMachine().getCodeModel();
18211 Reloc::Model R = getTargetMachine().getRelocationModel();
18213 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18214 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18219 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18221 // If a reference to this global requires an extra load, we can't fold it.
18222 if (isGlobalStubReference(GVFlags))
18225 // If BaseGV requires a register for the PIC base, we cannot also have a
18226 // BaseReg specified.
18227 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18230 // If lower 4G is not available, then we must use rip-relative addressing.
18231 if ((M != CodeModel::Small || R != Reloc::Static) &&
18232 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18236 switch (AM.Scale) {
18242 // These scales always work.
18247 // These scales are formed with basereg+scalereg. Only accept if there is
18252 default: // Other stuff never works.
18259 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18260 unsigned Bits = Ty->getScalarSizeInBits();
18262 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18263 // particularly cheaper than those without.
18267 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18268 // variable shifts just as cheap as scalar ones.
18269 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18272 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18273 // fully general vector.
18277 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18278 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18280 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18281 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18282 return NumBits1 > NumBits2;
18285 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18286 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18289 if (!isTypeLegal(EVT::getEVT(Ty1)))
18292 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18294 // Assuming the caller doesn't have a zeroext or signext return parameter,
18295 // truncation all the way down to i1 is valid.
18299 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18300 return isInt<32>(Imm);
18303 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18304 // Can also use sub to handle negated immediates.
18305 return isInt<32>(Imm);
18308 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18309 if (!VT1.isInteger() || !VT2.isInteger())
18311 unsigned NumBits1 = VT1.getSizeInBits();
18312 unsigned NumBits2 = VT2.getSizeInBits();
18313 return NumBits1 > NumBits2;
18316 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18317 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18318 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18321 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18322 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18323 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18326 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18327 EVT VT1 = Val.getValueType();
18328 if (isZExtFree(VT1, VT2))
18331 if (Val.getOpcode() != ISD::LOAD)
18334 if (!VT1.isSimple() || !VT1.isInteger() ||
18335 !VT2.isSimple() || !VT2.isInteger())
18338 switch (VT1.getSimpleVT().SimpleTy) {
18343 // X86 has 8, 16, and 32-bit zero-extending loads.
18350 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18353 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18354 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18357 VT = VT.getScalarType();
18359 if (!VT.isSimple())
18362 switch (VT.getSimpleVT().SimpleTy) {
18373 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18374 // i16 instructions are longer (0x66 prefix) and potentially slower.
18375 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18378 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18379 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18380 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18381 /// are assumed to be legal.
18383 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18385 if (!VT.isSimple())
18388 // Not for i1 vectors
18389 if (VT.getScalarType() == MVT::i1)
18392 // Very little shuffling can be done for 64-bit vectors right now.
18393 if (VT.getSizeInBits() == 64)
18396 // We only care that the types being shuffled are legal. The lowering can
18397 // handle any possible shuffle mask that results.
18398 return isTypeLegal(VT.getSimpleVT());
18402 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18404 // Just delegate to the generic legality, clear masks aren't special.
18405 return isShuffleMaskLegal(Mask, VT);
18408 //===----------------------------------------------------------------------===//
18409 // X86 Scheduler Hooks
18410 //===----------------------------------------------------------------------===//
18412 /// Utility function to emit xbegin specifying the start of an RTM region.
18413 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18414 const TargetInstrInfo *TII) {
18415 DebugLoc DL = MI->getDebugLoc();
18417 const BasicBlock *BB = MBB->getBasicBlock();
18418 MachineFunction::iterator I = MBB;
18421 // For the v = xbegin(), we generate
18432 MachineBasicBlock *thisMBB = MBB;
18433 MachineFunction *MF = MBB->getParent();
18434 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18435 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18436 MF->insert(I, mainMBB);
18437 MF->insert(I, sinkMBB);
18439 // Transfer the remainder of BB and its successor edges to sinkMBB.
18440 sinkMBB->splice(sinkMBB->begin(), MBB,
18441 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18442 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18446 // # fallthrough to mainMBB
18447 // # abortion to sinkMBB
18448 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18449 thisMBB->addSuccessor(mainMBB);
18450 thisMBB->addSuccessor(sinkMBB);
18454 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18455 mainMBB->addSuccessor(sinkMBB);
18458 // EAX is live into the sinkMBB
18459 sinkMBB->addLiveIn(X86::EAX);
18460 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18461 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18464 MI->eraseFromParent();
18468 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18469 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18470 // in the .td file.
18471 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18472 const TargetInstrInfo *TII) {
18474 switch (MI->getOpcode()) {
18475 default: llvm_unreachable("illegal opcode!");
18476 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18477 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18478 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18479 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18480 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18481 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18482 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18483 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18486 DebugLoc dl = MI->getDebugLoc();
18487 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18489 unsigned NumArgs = MI->getNumOperands();
18490 for (unsigned i = 1; i < NumArgs; ++i) {
18491 MachineOperand &Op = MI->getOperand(i);
18492 if (!(Op.isReg() && Op.isImplicit()))
18493 MIB.addOperand(Op);
18495 if (MI->hasOneMemOperand())
18496 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18498 BuildMI(*BB, MI, dl,
18499 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18500 .addReg(X86::XMM0);
18502 MI->eraseFromParent();
18506 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18507 // defs in an instruction pattern
18508 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18509 const TargetInstrInfo *TII) {
18511 switch (MI->getOpcode()) {
18512 default: llvm_unreachable("illegal opcode!");
18513 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18514 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18515 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18516 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18517 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18518 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18519 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18520 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18523 DebugLoc dl = MI->getDebugLoc();
18524 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18526 unsigned NumArgs = MI->getNumOperands(); // remove the results
18527 for (unsigned i = 1; i < NumArgs; ++i) {
18528 MachineOperand &Op = MI->getOperand(i);
18529 if (!(Op.isReg() && Op.isImplicit()))
18530 MIB.addOperand(Op);
18532 if (MI->hasOneMemOperand())
18533 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18535 BuildMI(*BB, MI, dl,
18536 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18539 MI->eraseFromParent();
18543 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18544 const X86Subtarget *Subtarget) {
18545 DebugLoc dl = MI->getDebugLoc();
18546 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18547 // Address into RAX/EAX, other two args into ECX, EDX.
18548 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18549 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18550 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18551 for (int i = 0; i < X86::AddrNumOperands; ++i)
18552 MIB.addOperand(MI->getOperand(i));
18554 unsigned ValOps = X86::AddrNumOperands;
18555 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18556 .addReg(MI->getOperand(ValOps).getReg());
18557 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18558 .addReg(MI->getOperand(ValOps+1).getReg());
18560 // The instruction doesn't actually take any operands though.
18561 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18563 MI->eraseFromParent(); // The pseudo is gone now.
18567 MachineBasicBlock *
18568 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18569 MachineBasicBlock *MBB) const {
18570 // Emit va_arg instruction on X86-64.
18572 // Operands to this pseudo-instruction:
18573 // 0 ) Output : destination address (reg)
18574 // 1-5) Input : va_list address (addr, i64mem)
18575 // 6 ) ArgSize : Size (in bytes) of vararg type
18576 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18577 // 8 ) Align : Alignment of type
18578 // 9 ) EFLAGS (implicit-def)
18580 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18581 static_assert(X86::AddrNumOperands == 5,
18582 "VAARG_64 assumes 5 address operands");
18584 unsigned DestReg = MI->getOperand(0).getReg();
18585 MachineOperand &Base = MI->getOperand(1);
18586 MachineOperand &Scale = MI->getOperand(2);
18587 MachineOperand &Index = MI->getOperand(3);
18588 MachineOperand &Disp = MI->getOperand(4);
18589 MachineOperand &Segment = MI->getOperand(5);
18590 unsigned ArgSize = MI->getOperand(6).getImm();
18591 unsigned ArgMode = MI->getOperand(7).getImm();
18592 unsigned Align = MI->getOperand(8).getImm();
18594 // Memory Reference
18595 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18596 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18597 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18599 // Machine Information
18600 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18601 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18602 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18603 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18604 DebugLoc DL = MI->getDebugLoc();
18606 // struct va_list {
18609 // i64 overflow_area (address)
18610 // i64 reg_save_area (address)
18612 // sizeof(va_list) = 24
18613 // alignment(va_list) = 8
18615 unsigned TotalNumIntRegs = 6;
18616 unsigned TotalNumXMMRegs = 8;
18617 bool UseGPOffset = (ArgMode == 1);
18618 bool UseFPOffset = (ArgMode == 2);
18619 unsigned MaxOffset = TotalNumIntRegs * 8 +
18620 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18622 /* Align ArgSize to a multiple of 8 */
18623 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18624 bool NeedsAlign = (Align > 8);
18626 MachineBasicBlock *thisMBB = MBB;
18627 MachineBasicBlock *overflowMBB;
18628 MachineBasicBlock *offsetMBB;
18629 MachineBasicBlock *endMBB;
18631 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18632 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18633 unsigned OffsetReg = 0;
18635 if (!UseGPOffset && !UseFPOffset) {
18636 // If we only pull from the overflow region, we don't create a branch.
18637 // We don't need to alter control flow.
18638 OffsetDestReg = 0; // unused
18639 OverflowDestReg = DestReg;
18641 offsetMBB = nullptr;
18642 overflowMBB = thisMBB;
18645 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18646 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18647 // If not, pull from overflow_area. (branch to overflowMBB)
18652 // offsetMBB overflowMBB
18657 // Registers for the PHI in endMBB
18658 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18659 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18661 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18662 MachineFunction *MF = MBB->getParent();
18663 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18664 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18665 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18667 MachineFunction::iterator MBBIter = MBB;
18670 // Insert the new basic blocks
18671 MF->insert(MBBIter, offsetMBB);
18672 MF->insert(MBBIter, overflowMBB);
18673 MF->insert(MBBIter, endMBB);
18675 // Transfer the remainder of MBB and its successor edges to endMBB.
18676 endMBB->splice(endMBB->begin(), thisMBB,
18677 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18678 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18680 // Make offsetMBB and overflowMBB successors of thisMBB
18681 thisMBB->addSuccessor(offsetMBB);
18682 thisMBB->addSuccessor(overflowMBB);
18684 // endMBB is a successor of both offsetMBB and overflowMBB
18685 offsetMBB->addSuccessor(endMBB);
18686 overflowMBB->addSuccessor(endMBB);
18688 // Load the offset value into a register
18689 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18690 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18694 .addDisp(Disp, UseFPOffset ? 4 : 0)
18695 .addOperand(Segment)
18696 .setMemRefs(MMOBegin, MMOEnd);
18698 // Check if there is enough room left to pull this argument.
18699 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18701 .addImm(MaxOffset + 8 - ArgSizeA8);
18703 // Branch to "overflowMBB" if offset >= max
18704 // Fall through to "offsetMBB" otherwise
18705 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18706 .addMBB(overflowMBB);
18709 // In offsetMBB, emit code to use the reg_save_area.
18711 assert(OffsetReg != 0);
18713 // Read the reg_save_area address.
18714 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18715 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18720 .addOperand(Segment)
18721 .setMemRefs(MMOBegin, MMOEnd);
18723 // Zero-extend the offset
18724 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18725 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18728 .addImm(X86::sub_32bit);
18730 // Add the offset to the reg_save_area to get the final address.
18731 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18732 .addReg(OffsetReg64)
18733 .addReg(RegSaveReg);
18735 // Compute the offset for the next argument
18736 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18737 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18739 .addImm(UseFPOffset ? 16 : 8);
18741 // Store it back into the va_list.
18742 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18746 .addDisp(Disp, UseFPOffset ? 4 : 0)
18747 .addOperand(Segment)
18748 .addReg(NextOffsetReg)
18749 .setMemRefs(MMOBegin, MMOEnd);
18752 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18757 // Emit code to use overflow area
18760 // Load the overflow_area address into a register.
18761 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18762 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18767 .addOperand(Segment)
18768 .setMemRefs(MMOBegin, MMOEnd);
18770 // If we need to align it, do so. Otherwise, just copy the address
18771 // to OverflowDestReg.
18773 // Align the overflow address
18774 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18775 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18777 // aligned_addr = (addr + (align-1)) & ~(align-1)
18778 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18779 .addReg(OverflowAddrReg)
18782 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18784 .addImm(~(uint64_t)(Align-1));
18786 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18787 .addReg(OverflowAddrReg);
18790 // Compute the next overflow address after this argument.
18791 // (the overflow address should be kept 8-byte aligned)
18792 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18793 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18794 .addReg(OverflowDestReg)
18795 .addImm(ArgSizeA8);
18797 // Store the new overflow address.
18798 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18803 .addOperand(Segment)
18804 .addReg(NextAddrReg)
18805 .setMemRefs(MMOBegin, MMOEnd);
18807 // If we branched, emit the PHI to the front of endMBB.
18809 BuildMI(*endMBB, endMBB->begin(), DL,
18810 TII->get(X86::PHI), DestReg)
18811 .addReg(OffsetDestReg).addMBB(offsetMBB)
18812 .addReg(OverflowDestReg).addMBB(overflowMBB);
18815 // Erase the pseudo instruction
18816 MI->eraseFromParent();
18821 MachineBasicBlock *
18822 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18824 MachineBasicBlock *MBB) const {
18825 // Emit code to save XMM registers to the stack. The ABI says that the
18826 // number of registers to save is given in %al, so it's theoretically
18827 // possible to do an indirect jump trick to avoid saving all of them,
18828 // however this code takes a simpler approach and just executes all
18829 // of the stores if %al is non-zero. It's less code, and it's probably
18830 // easier on the hardware branch predictor, and stores aren't all that
18831 // expensive anyway.
18833 // Create the new basic blocks. One block contains all the XMM stores,
18834 // and one block is the final destination regardless of whether any
18835 // stores were performed.
18836 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18837 MachineFunction *F = MBB->getParent();
18838 MachineFunction::iterator MBBIter = MBB;
18840 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18841 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18842 F->insert(MBBIter, XMMSaveMBB);
18843 F->insert(MBBIter, EndMBB);
18845 // Transfer the remainder of MBB and its successor edges to EndMBB.
18846 EndMBB->splice(EndMBB->begin(), MBB,
18847 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18848 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18850 // The original block will now fall through to the XMM save block.
18851 MBB->addSuccessor(XMMSaveMBB);
18852 // The XMMSaveMBB will fall through to the end block.
18853 XMMSaveMBB->addSuccessor(EndMBB);
18855 // Now add the instructions.
18856 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18857 DebugLoc DL = MI->getDebugLoc();
18859 unsigned CountReg = MI->getOperand(0).getReg();
18860 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18861 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18863 if (!Subtarget->isTargetWin64()) {
18864 // If %al is 0, branch around the XMM save block.
18865 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18866 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18867 MBB->addSuccessor(EndMBB);
18870 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18871 // that was just emitted, but clearly shouldn't be "saved".
18872 assert((MI->getNumOperands() <= 3 ||
18873 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18874 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18875 && "Expected last argument to be EFLAGS");
18876 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18877 // In the XMM save block, save all the XMM argument registers.
18878 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18879 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18880 MachineMemOperand *MMO =
18881 F->getMachineMemOperand(
18882 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18883 MachineMemOperand::MOStore,
18884 /*Size=*/16, /*Align=*/16);
18885 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18886 .addFrameIndex(RegSaveFrameIndex)
18887 .addImm(/*Scale=*/1)
18888 .addReg(/*IndexReg=*/0)
18889 .addImm(/*Disp=*/Offset)
18890 .addReg(/*Segment=*/0)
18891 .addReg(MI->getOperand(i).getReg())
18892 .addMemOperand(MMO);
18895 MI->eraseFromParent(); // The pseudo instruction is gone now.
18900 // The EFLAGS operand of SelectItr might be missing a kill marker
18901 // because there were multiple uses of EFLAGS, and ISel didn't know
18902 // which to mark. Figure out whether SelectItr should have had a
18903 // kill marker, and set it if it should. Returns the correct kill
18905 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18906 MachineBasicBlock* BB,
18907 const TargetRegisterInfo* TRI) {
18908 // Scan forward through BB for a use/def of EFLAGS.
18909 MachineBasicBlock::iterator miI(std::next(SelectItr));
18910 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18911 const MachineInstr& mi = *miI;
18912 if (mi.readsRegister(X86::EFLAGS))
18914 if (mi.definesRegister(X86::EFLAGS))
18915 break; // Should have kill-flag - update below.
18918 // If we hit the end of the block, check whether EFLAGS is live into a
18920 if (miI == BB->end()) {
18921 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18922 sEnd = BB->succ_end();
18923 sItr != sEnd; ++sItr) {
18924 MachineBasicBlock* succ = *sItr;
18925 if (succ->isLiveIn(X86::EFLAGS))
18930 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18931 // out. SelectMI should have a kill flag on EFLAGS.
18932 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18936 MachineBasicBlock *
18937 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18938 MachineBasicBlock *BB) const {
18939 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18940 DebugLoc DL = MI->getDebugLoc();
18942 // To "insert" a SELECT_CC instruction, we actually have to insert the
18943 // diamond control-flow pattern. The incoming instruction knows the
18944 // destination vreg to set, the condition code register to branch on, the
18945 // true/false values to select between, and a branch opcode to use.
18946 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18947 MachineFunction::iterator It = BB;
18953 // cmpTY ccX, r1, r2
18955 // fallthrough --> copy0MBB
18956 MachineBasicBlock *thisMBB = BB;
18957 MachineFunction *F = BB->getParent();
18959 // We also lower double CMOVs:
18960 // (CMOV (CMOV F, T, cc1), T, cc2)
18961 // to two successives branches. For that, we look for another CMOV as the
18962 // following instruction.
18964 // Without this, we would add a PHI between the two jumps, which ends up
18965 // creating a few copies all around. For instance, for
18967 // (sitofp (zext (fcmp une)))
18969 // we would generate:
18971 // ucomiss %xmm1, %xmm0
18972 // movss <1.0f>, %xmm0
18973 // movaps %xmm0, %xmm1
18975 // xorps %xmm1, %xmm1
18978 // movaps %xmm1, %xmm0
18982 // because this custom-inserter would have generated:
18994 // A: X = ...; Y = ...
18996 // C: Z = PHI [X, A], [Y, B]
18998 // E: PHI [X, C], [Z, D]
19000 // If we lower both CMOVs in a single step, we can instead generate:
19012 // A: X = ...; Y = ...
19014 // E: PHI [X, A], [X, C], [Y, D]
19016 // Which, in our sitofp/fcmp example, gives us something like:
19018 // ucomiss %xmm1, %xmm0
19019 // movss <1.0f>, %xmm0
19022 // xorps %xmm0, %xmm0
19026 MachineInstr *NextCMOV = nullptr;
19027 MachineBasicBlock::iterator NextMIIt =
19028 std::next(MachineBasicBlock::iterator(MI));
19029 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19030 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19031 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19032 NextCMOV = &*NextMIIt;
19034 MachineBasicBlock *jcc1MBB = nullptr;
19036 // If we have a double CMOV, we lower it to two successive branches to
19037 // the same block. EFLAGS is used by both, so mark it as live in the second.
19039 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19040 F->insert(It, jcc1MBB);
19041 jcc1MBB->addLiveIn(X86::EFLAGS);
19044 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19045 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19046 F->insert(It, copy0MBB);
19047 F->insert(It, sinkMBB);
19049 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19050 // live into the sink and copy blocks.
19051 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19053 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19054 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19055 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19056 copy0MBB->addLiveIn(X86::EFLAGS);
19057 sinkMBB->addLiveIn(X86::EFLAGS);
19060 // Transfer the remainder of BB and its successor edges to sinkMBB.
19061 sinkMBB->splice(sinkMBB->begin(), BB,
19062 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19063 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19065 // Add the true and fallthrough blocks as its successors.
19067 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19068 BB->addSuccessor(jcc1MBB);
19070 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19071 // jump to the sinkMBB.
19072 jcc1MBB->addSuccessor(copy0MBB);
19073 jcc1MBB->addSuccessor(sinkMBB);
19075 BB->addSuccessor(copy0MBB);
19078 // The true block target of the first (or only) branch is always sinkMBB.
19079 BB->addSuccessor(sinkMBB);
19081 // Create the conditional branch instruction.
19083 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19084 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19087 unsigned Opc2 = X86::GetCondBranchFromCond(
19088 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19089 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19093 // %FalseValue = ...
19094 // # fallthrough to sinkMBB
19095 copy0MBB->addSuccessor(sinkMBB);
19098 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19100 MachineInstrBuilder MIB =
19101 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19102 MI->getOperand(0).getReg())
19103 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19104 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19106 // If we have a double CMOV, the second Jcc provides the same incoming
19107 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19109 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19110 // Copy the PHI result to the register defined by the second CMOV.
19111 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19112 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19113 .addReg(MI->getOperand(0).getReg());
19114 NextCMOV->eraseFromParent();
19117 MI->eraseFromParent(); // The pseudo instruction is gone now.
19121 MachineBasicBlock *
19122 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19123 MachineBasicBlock *BB) const {
19124 MachineFunction *MF = BB->getParent();
19125 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19126 DebugLoc DL = MI->getDebugLoc();
19127 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19129 assert(MF->shouldSplitStack());
19131 const bool Is64Bit = Subtarget->is64Bit();
19132 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19134 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19135 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19138 // ... [Till the alloca]
19139 // If stacklet is not large enough, jump to mallocMBB
19142 // Allocate by subtracting from RSP
19143 // Jump to continueMBB
19146 // Allocate by call to runtime
19150 // [rest of original BB]
19153 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19154 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19155 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19157 MachineRegisterInfo &MRI = MF->getRegInfo();
19158 const TargetRegisterClass *AddrRegClass =
19159 getRegClassFor(getPointerTy());
19161 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19162 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19163 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19164 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19165 sizeVReg = MI->getOperand(1).getReg(),
19166 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19168 MachineFunction::iterator MBBIter = BB;
19171 MF->insert(MBBIter, bumpMBB);
19172 MF->insert(MBBIter, mallocMBB);
19173 MF->insert(MBBIter, continueMBB);
19175 continueMBB->splice(continueMBB->begin(), BB,
19176 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19177 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19179 // Add code to the main basic block to check if the stack limit has been hit,
19180 // and if so, jump to mallocMBB otherwise to bumpMBB.
19181 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19182 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19183 .addReg(tmpSPVReg).addReg(sizeVReg);
19184 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19185 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19186 .addReg(SPLimitVReg);
19187 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19189 // bumpMBB simply decreases the stack pointer, since we know the current
19190 // stacklet has enough space.
19191 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19192 .addReg(SPLimitVReg);
19193 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19194 .addReg(SPLimitVReg);
19195 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19197 // Calls into a routine in libgcc to allocate more space from the heap.
19198 const uint32_t *RegMask =
19199 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19201 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19203 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19204 .addExternalSymbol("__morestack_allocate_stack_space")
19205 .addRegMask(RegMask)
19206 .addReg(X86::RDI, RegState::Implicit)
19207 .addReg(X86::RAX, RegState::ImplicitDefine);
19208 } else if (Is64Bit) {
19209 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19211 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19212 .addExternalSymbol("__morestack_allocate_stack_space")
19213 .addRegMask(RegMask)
19214 .addReg(X86::EDI, RegState::Implicit)
19215 .addReg(X86::EAX, RegState::ImplicitDefine);
19217 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19219 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19220 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19221 .addExternalSymbol("__morestack_allocate_stack_space")
19222 .addRegMask(RegMask)
19223 .addReg(X86::EAX, RegState::ImplicitDefine);
19227 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19230 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19231 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19232 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19234 // Set up the CFG correctly.
19235 BB->addSuccessor(bumpMBB);
19236 BB->addSuccessor(mallocMBB);
19237 mallocMBB->addSuccessor(continueMBB);
19238 bumpMBB->addSuccessor(continueMBB);
19240 // Take care of the PHI nodes.
19241 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19242 MI->getOperand(0).getReg())
19243 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19244 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19246 // Delete the original pseudo instruction.
19247 MI->eraseFromParent();
19250 return continueMBB;
19253 MachineBasicBlock *
19254 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19255 MachineBasicBlock *BB) const {
19256 DebugLoc DL = MI->getDebugLoc();
19258 assert(!Subtarget->isTargetMachO());
19260 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19262 MI->eraseFromParent(); // The pseudo instruction is gone now.
19266 MachineBasicBlock *
19267 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19268 MachineBasicBlock *BB) const {
19269 // This is pretty easy. We're taking the value that we received from
19270 // our load from the relocation, sticking it in either RDI (x86-64)
19271 // or EAX and doing an indirect call. The return value will then
19272 // be in the normal return register.
19273 MachineFunction *F = BB->getParent();
19274 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19275 DebugLoc DL = MI->getDebugLoc();
19277 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19278 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19280 // Get a register mask for the lowered call.
19281 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19282 // proper register mask.
19283 const uint32_t *RegMask =
19284 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19285 if (Subtarget->is64Bit()) {
19286 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19287 TII->get(X86::MOV64rm), X86::RDI)
19289 .addImm(0).addReg(0)
19290 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19291 MI->getOperand(3).getTargetFlags())
19293 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19294 addDirectMem(MIB, X86::RDI);
19295 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19296 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19297 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19298 TII->get(X86::MOV32rm), X86::EAX)
19300 .addImm(0).addReg(0)
19301 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19302 MI->getOperand(3).getTargetFlags())
19304 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19305 addDirectMem(MIB, X86::EAX);
19306 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19308 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19309 TII->get(X86::MOV32rm), X86::EAX)
19310 .addReg(TII->getGlobalBaseReg(F))
19311 .addImm(0).addReg(0)
19312 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19313 MI->getOperand(3).getTargetFlags())
19315 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19316 addDirectMem(MIB, X86::EAX);
19317 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19320 MI->eraseFromParent(); // The pseudo instruction is gone now.
19324 MachineBasicBlock *
19325 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19326 MachineBasicBlock *MBB) const {
19327 DebugLoc DL = MI->getDebugLoc();
19328 MachineFunction *MF = MBB->getParent();
19329 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19330 MachineRegisterInfo &MRI = MF->getRegInfo();
19332 const BasicBlock *BB = MBB->getBasicBlock();
19333 MachineFunction::iterator I = MBB;
19336 // Memory Reference
19337 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19338 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19341 unsigned MemOpndSlot = 0;
19343 unsigned CurOp = 0;
19345 DstReg = MI->getOperand(CurOp++).getReg();
19346 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19347 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19348 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19349 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19351 MemOpndSlot = CurOp;
19353 MVT PVT = getPointerTy();
19354 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19355 "Invalid Pointer Size!");
19357 // For v = setjmp(buf), we generate
19360 // buf[LabelOffset] = restoreMBB
19361 // SjLjSetup restoreMBB
19367 // v = phi(main, restore)
19370 // if base pointer being used, load it from frame
19373 MachineBasicBlock *thisMBB = MBB;
19374 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19375 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19376 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19377 MF->insert(I, mainMBB);
19378 MF->insert(I, sinkMBB);
19379 MF->push_back(restoreMBB);
19381 MachineInstrBuilder MIB;
19383 // Transfer the remainder of BB and its successor edges to sinkMBB.
19384 sinkMBB->splice(sinkMBB->begin(), MBB,
19385 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19386 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19389 unsigned PtrStoreOpc = 0;
19390 unsigned LabelReg = 0;
19391 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19392 Reloc::Model RM = MF->getTarget().getRelocationModel();
19393 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19394 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19396 // Prepare IP either in reg or imm.
19397 if (!UseImmLabel) {
19398 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19399 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19400 LabelReg = MRI.createVirtualRegister(PtrRC);
19401 if (Subtarget->is64Bit()) {
19402 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19406 .addMBB(restoreMBB)
19409 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19410 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19411 .addReg(XII->getGlobalBaseReg(MF))
19414 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19418 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19420 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19421 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19422 if (i == X86::AddrDisp)
19423 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19425 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19428 MIB.addReg(LabelReg);
19430 MIB.addMBB(restoreMBB);
19431 MIB.setMemRefs(MMOBegin, MMOEnd);
19433 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19434 .addMBB(restoreMBB);
19436 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19437 MIB.addRegMask(RegInfo->getNoPreservedMask());
19438 thisMBB->addSuccessor(mainMBB);
19439 thisMBB->addSuccessor(restoreMBB);
19443 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19444 mainMBB->addSuccessor(sinkMBB);
19447 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19448 TII->get(X86::PHI), DstReg)
19449 .addReg(mainDstReg).addMBB(mainMBB)
19450 .addReg(restoreDstReg).addMBB(restoreMBB);
19453 if (RegInfo->hasBasePointer(*MF)) {
19454 const bool Uses64BitFramePtr =
19455 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19456 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19457 X86FI->setRestoreBasePointer(MF);
19458 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19459 unsigned BasePtr = RegInfo->getBaseRegister();
19460 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19461 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19462 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19463 .setMIFlag(MachineInstr::FrameSetup);
19465 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19466 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19467 restoreMBB->addSuccessor(sinkMBB);
19469 MI->eraseFromParent();
19473 MachineBasicBlock *
19474 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19475 MachineBasicBlock *MBB) const {
19476 DebugLoc DL = MI->getDebugLoc();
19477 MachineFunction *MF = MBB->getParent();
19478 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19479 MachineRegisterInfo &MRI = MF->getRegInfo();
19481 // Memory Reference
19482 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19483 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19485 MVT PVT = getPointerTy();
19486 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19487 "Invalid Pointer Size!");
19489 const TargetRegisterClass *RC =
19490 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19491 unsigned Tmp = MRI.createVirtualRegister(RC);
19492 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19493 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19494 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19495 unsigned SP = RegInfo->getStackRegister();
19497 MachineInstrBuilder MIB;
19499 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19500 const int64_t SPOffset = 2 * PVT.getStoreSize();
19502 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19503 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19506 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19507 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19508 MIB.addOperand(MI->getOperand(i));
19509 MIB.setMemRefs(MMOBegin, MMOEnd);
19511 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19512 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19513 if (i == X86::AddrDisp)
19514 MIB.addDisp(MI->getOperand(i), LabelOffset);
19516 MIB.addOperand(MI->getOperand(i));
19518 MIB.setMemRefs(MMOBegin, MMOEnd);
19520 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19521 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19522 if (i == X86::AddrDisp)
19523 MIB.addDisp(MI->getOperand(i), SPOffset);
19525 MIB.addOperand(MI->getOperand(i));
19527 MIB.setMemRefs(MMOBegin, MMOEnd);
19529 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19531 MI->eraseFromParent();
19535 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19536 // accumulator loops. Writing back to the accumulator allows the coalescer
19537 // to remove extra copies in the loop.
19538 MachineBasicBlock *
19539 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19540 MachineBasicBlock *MBB) const {
19541 MachineOperand &AddendOp = MI->getOperand(3);
19543 // Bail out early if the addend isn't a register - we can't switch these.
19544 if (!AddendOp.isReg())
19547 MachineFunction &MF = *MBB->getParent();
19548 MachineRegisterInfo &MRI = MF.getRegInfo();
19550 // Check whether the addend is defined by a PHI:
19551 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19552 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19553 if (!AddendDef.isPHI())
19556 // Look for the following pattern:
19558 // %addend = phi [%entry, 0], [%loop, %result]
19560 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19564 // %addend = phi [%entry, 0], [%loop, %result]
19566 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19568 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19569 assert(AddendDef.getOperand(i).isReg());
19570 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19571 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19572 if (&PHISrcInst == MI) {
19573 // Found a matching instruction.
19574 unsigned NewFMAOpc = 0;
19575 switch (MI->getOpcode()) {
19576 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19577 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19578 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19579 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19580 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19581 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19582 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19583 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19584 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19585 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19586 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19587 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19588 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19589 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19590 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19591 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19592 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19593 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19594 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19595 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19597 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19598 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19599 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19600 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19601 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19602 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19603 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19604 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19605 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19606 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19607 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19608 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19609 default: llvm_unreachable("Unrecognized FMA variant.");
19612 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19613 MachineInstrBuilder MIB =
19614 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19615 .addOperand(MI->getOperand(0))
19616 .addOperand(MI->getOperand(3))
19617 .addOperand(MI->getOperand(2))
19618 .addOperand(MI->getOperand(1));
19619 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19620 MI->eraseFromParent();
19627 MachineBasicBlock *
19628 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19629 MachineBasicBlock *BB) const {
19630 switch (MI->getOpcode()) {
19631 default: llvm_unreachable("Unexpected instr type to insert");
19632 case X86::TAILJMPd64:
19633 case X86::TAILJMPr64:
19634 case X86::TAILJMPm64:
19635 case X86::TAILJMPd64_REX:
19636 case X86::TAILJMPr64_REX:
19637 case X86::TAILJMPm64_REX:
19638 llvm_unreachable("TAILJMP64 would not be touched here.");
19639 case X86::TCRETURNdi64:
19640 case X86::TCRETURNri64:
19641 case X86::TCRETURNmi64:
19643 case X86::WIN_ALLOCA:
19644 return EmitLoweredWinAlloca(MI, BB);
19645 case X86::SEG_ALLOCA_32:
19646 case X86::SEG_ALLOCA_64:
19647 return EmitLoweredSegAlloca(MI, BB);
19648 case X86::TLSCall_32:
19649 case X86::TLSCall_64:
19650 return EmitLoweredTLSCall(MI, BB);
19651 case X86::CMOV_GR8:
19652 case X86::CMOV_FR32:
19653 case X86::CMOV_FR64:
19654 case X86::CMOV_V4F32:
19655 case X86::CMOV_V2F64:
19656 case X86::CMOV_V2I64:
19657 case X86::CMOV_V8F32:
19658 case X86::CMOV_V4F64:
19659 case X86::CMOV_V4I64:
19660 case X86::CMOV_V16F32:
19661 case X86::CMOV_V8F64:
19662 case X86::CMOV_V8I64:
19663 case X86::CMOV_GR16:
19664 case X86::CMOV_GR32:
19665 case X86::CMOV_RFP32:
19666 case X86::CMOV_RFP64:
19667 case X86::CMOV_RFP80:
19668 case X86::CMOV_V8I1:
19669 case X86::CMOV_V16I1:
19670 case X86::CMOV_V32I1:
19671 case X86::CMOV_V64I1:
19672 return EmitLoweredSelect(MI, BB);
19674 case X86::FP32_TO_INT16_IN_MEM:
19675 case X86::FP32_TO_INT32_IN_MEM:
19676 case X86::FP32_TO_INT64_IN_MEM:
19677 case X86::FP64_TO_INT16_IN_MEM:
19678 case X86::FP64_TO_INT32_IN_MEM:
19679 case X86::FP64_TO_INT64_IN_MEM:
19680 case X86::FP80_TO_INT16_IN_MEM:
19681 case X86::FP80_TO_INT32_IN_MEM:
19682 case X86::FP80_TO_INT64_IN_MEM: {
19683 MachineFunction *F = BB->getParent();
19684 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19685 DebugLoc DL = MI->getDebugLoc();
19687 // Change the floating point control register to use "round towards zero"
19688 // mode when truncating to an integer value.
19689 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19690 addFrameReference(BuildMI(*BB, MI, DL,
19691 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19693 // Load the old value of the high byte of the control word...
19695 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19696 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19699 // Set the high part to be round to zero...
19700 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19703 // Reload the modified control word now...
19704 addFrameReference(BuildMI(*BB, MI, DL,
19705 TII->get(X86::FLDCW16m)), CWFrameIdx);
19707 // Restore the memory image of control word to original value
19708 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19711 // Get the X86 opcode to use.
19713 switch (MI->getOpcode()) {
19714 default: llvm_unreachable("illegal opcode!");
19715 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19716 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19717 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19718 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19719 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19720 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19721 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19722 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19723 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19727 MachineOperand &Op = MI->getOperand(0);
19729 AM.BaseType = X86AddressMode::RegBase;
19730 AM.Base.Reg = Op.getReg();
19732 AM.BaseType = X86AddressMode::FrameIndexBase;
19733 AM.Base.FrameIndex = Op.getIndex();
19735 Op = MI->getOperand(1);
19737 AM.Scale = Op.getImm();
19738 Op = MI->getOperand(2);
19740 AM.IndexReg = Op.getImm();
19741 Op = MI->getOperand(3);
19742 if (Op.isGlobal()) {
19743 AM.GV = Op.getGlobal();
19745 AM.Disp = Op.getImm();
19747 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19748 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19750 // Reload the original control word now.
19751 addFrameReference(BuildMI(*BB, MI, DL,
19752 TII->get(X86::FLDCW16m)), CWFrameIdx);
19754 MI->eraseFromParent(); // The pseudo instruction is gone now.
19757 // String/text processing lowering.
19758 case X86::PCMPISTRM128REG:
19759 case X86::VPCMPISTRM128REG:
19760 case X86::PCMPISTRM128MEM:
19761 case X86::VPCMPISTRM128MEM:
19762 case X86::PCMPESTRM128REG:
19763 case X86::VPCMPESTRM128REG:
19764 case X86::PCMPESTRM128MEM:
19765 case X86::VPCMPESTRM128MEM:
19766 assert(Subtarget->hasSSE42() &&
19767 "Target must have SSE4.2 or AVX features enabled");
19768 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19770 // String/text processing lowering.
19771 case X86::PCMPISTRIREG:
19772 case X86::VPCMPISTRIREG:
19773 case X86::PCMPISTRIMEM:
19774 case X86::VPCMPISTRIMEM:
19775 case X86::PCMPESTRIREG:
19776 case X86::VPCMPESTRIREG:
19777 case X86::PCMPESTRIMEM:
19778 case X86::VPCMPESTRIMEM:
19779 assert(Subtarget->hasSSE42() &&
19780 "Target must have SSE4.2 or AVX features enabled");
19781 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19783 // Thread synchronization.
19785 return EmitMonitor(MI, BB, Subtarget);
19789 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19791 case X86::VASTART_SAVE_XMM_REGS:
19792 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19794 case X86::VAARG_64:
19795 return EmitVAARG64WithCustomInserter(MI, BB);
19797 case X86::EH_SjLj_SetJmp32:
19798 case X86::EH_SjLj_SetJmp64:
19799 return emitEHSjLjSetJmp(MI, BB);
19801 case X86::EH_SjLj_LongJmp32:
19802 case X86::EH_SjLj_LongJmp64:
19803 return emitEHSjLjLongJmp(MI, BB);
19805 case TargetOpcode::STATEPOINT:
19806 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19807 // this point in the process. We diverge later.
19808 return emitPatchPoint(MI, BB);
19810 case TargetOpcode::STACKMAP:
19811 case TargetOpcode::PATCHPOINT:
19812 return emitPatchPoint(MI, BB);
19814 case X86::VFMADDPDr213r:
19815 case X86::VFMADDPSr213r:
19816 case X86::VFMADDSDr213r:
19817 case X86::VFMADDSSr213r:
19818 case X86::VFMSUBPDr213r:
19819 case X86::VFMSUBPSr213r:
19820 case X86::VFMSUBSDr213r:
19821 case X86::VFMSUBSSr213r:
19822 case X86::VFNMADDPDr213r:
19823 case X86::VFNMADDPSr213r:
19824 case X86::VFNMADDSDr213r:
19825 case X86::VFNMADDSSr213r:
19826 case X86::VFNMSUBPDr213r:
19827 case X86::VFNMSUBPSr213r:
19828 case X86::VFNMSUBSDr213r:
19829 case X86::VFNMSUBSSr213r:
19830 case X86::VFMADDSUBPDr213r:
19831 case X86::VFMADDSUBPSr213r:
19832 case X86::VFMSUBADDPDr213r:
19833 case X86::VFMSUBADDPSr213r:
19834 case X86::VFMADDPDr213rY:
19835 case X86::VFMADDPSr213rY:
19836 case X86::VFMSUBPDr213rY:
19837 case X86::VFMSUBPSr213rY:
19838 case X86::VFNMADDPDr213rY:
19839 case X86::VFNMADDPSr213rY:
19840 case X86::VFNMSUBPDr213rY:
19841 case X86::VFNMSUBPSr213rY:
19842 case X86::VFMADDSUBPDr213rY:
19843 case X86::VFMADDSUBPSr213rY:
19844 case X86::VFMSUBADDPDr213rY:
19845 case X86::VFMSUBADDPSr213rY:
19846 return emitFMA3Instr(MI, BB);
19850 //===----------------------------------------------------------------------===//
19851 // X86 Optimization Hooks
19852 //===----------------------------------------------------------------------===//
19854 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19857 const SelectionDAG &DAG,
19858 unsigned Depth) const {
19859 unsigned BitWidth = KnownZero.getBitWidth();
19860 unsigned Opc = Op.getOpcode();
19861 assert((Opc >= ISD::BUILTIN_OP_END ||
19862 Opc == ISD::INTRINSIC_WO_CHAIN ||
19863 Opc == ISD::INTRINSIC_W_CHAIN ||
19864 Opc == ISD::INTRINSIC_VOID) &&
19865 "Should use MaskedValueIsZero if you don't know whether Op"
19866 " is a target node!");
19868 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19882 // These nodes' second result is a boolean.
19883 if (Op.getResNo() == 0)
19886 case X86ISD::SETCC:
19887 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19889 case ISD::INTRINSIC_WO_CHAIN: {
19890 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19891 unsigned NumLoBits = 0;
19894 case Intrinsic::x86_sse_movmsk_ps:
19895 case Intrinsic::x86_avx_movmsk_ps_256:
19896 case Intrinsic::x86_sse2_movmsk_pd:
19897 case Intrinsic::x86_avx_movmsk_pd_256:
19898 case Intrinsic::x86_mmx_pmovmskb:
19899 case Intrinsic::x86_sse2_pmovmskb_128:
19900 case Intrinsic::x86_avx2_pmovmskb: {
19901 // High bits of movmskp{s|d}, pmovmskb are known zero.
19903 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19904 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19905 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19906 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19907 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19908 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19909 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19910 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19912 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19921 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19923 const SelectionDAG &,
19924 unsigned Depth) const {
19925 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19926 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19927 return Op.getValueType().getScalarType().getSizeInBits();
19933 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19934 /// node is a GlobalAddress + offset.
19935 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19936 const GlobalValue* &GA,
19937 int64_t &Offset) const {
19938 if (N->getOpcode() == X86ISD::Wrapper) {
19939 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19940 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19941 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19945 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19948 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19949 /// same as extracting the high 128-bit part of 256-bit vector and then
19950 /// inserting the result into the low part of a new 256-bit vector
19951 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19952 EVT VT = SVOp->getValueType(0);
19953 unsigned NumElems = VT.getVectorNumElements();
19955 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19956 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19957 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19958 SVOp->getMaskElt(j) >= 0)
19964 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19965 /// same as extracting the low 128-bit part of 256-bit vector and then
19966 /// inserting the result into the high part of a new 256-bit vector
19967 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19968 EVT VT = SVOp->getValueType(0);
19969 unsigned NumElems = VT.getVectorNumElements();
19971 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19972 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19973 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19974 SVOp->getMaskElt(j) >= 0)
19980 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19981 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19982 TargetLowering::DAGCombinerInfo &DCI,
19983 const X86Subtarget* Subtarget) {
19985 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19986 SDValue V1 = SVOp->getOperand(0);
19987 SDValue V2 = SVOp->getOperand(1);
19988 EVT VT = SVOp->getValueType(0);
19989 unsigned NumElems = VT.getVectorNumElements();
19991 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19992 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19996 // V UNDEF BUILD_VECTOR UNDEF
19998 // CONCAT_VECTOR CONCAT_VECTOR
20001 // RESULT: V + zero extended
20003 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20004 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20005 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20008 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20011 // To match the shuffle mask, the first half of the mask should
20012 // be exactly the first vector, and all the rest a splat with the
20013 // first element of the second one.
20014 for (unsigned i = 0; i != NumElems/2; ++i)
20015 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20016 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20019 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20020 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20021 if (Ld->hasNUsesOfValue(1, 0)) {
20022 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20023 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20025 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20027 Ld->getPointerInfo(),
20028 Ld->getAlignment(),
20029 false/*isVolatile*/, true/*ReadMem*/,
20030 false/*WriteMem*/);
20032 // Make sure the newly-created LOAD is in the same position as Ld in
20033 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20034 // and update uses of Ld's output chain to use the TokenFactor.
20035 if (Ld->hasAnyUseOfValue(1)) {
20036 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20037 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20038 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20039 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20040 SDValue(ResNode.getNode(), 1));
20043 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20047 // Emit a zeroed vector and insert the desired subvector on its
20049 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20050 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20051 return DCI.CombineTo(N, InsV);
20054 //===--------------------------------------------------------------------===//
20055 // Combine some shuffles into subvector extracts and inserts:
20058 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20059 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20060 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20061 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20062 return DCI.CombineTo(N, InsV);
20065 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20066 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20067 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20068 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20069 return DCI.CombineTo(N, InsV);
20075 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20078 /// This is the leaf of the recursive combinine below. When we have found some
20079 /// chain of single-use x86 shuffle instructions and accumulated the combined
20080 /// shuffle mask represented by them, this will try to pattern match that mask
20081 /// into either a single instruction if there is a special purpose instruction
20082 /// for this operation, or into a PSHUFB instruction which is a fully general
20083 /// instruction but should only be used to replace chains over a certain depth.
20084 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20085 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20086 TargetLowering::DAGCombinerInfo &DCI,
20087 const X86Subtarget *Subtarget) {
20088 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20090 // Find the operand that enters the chain. Note that multiple uses are OK
20091 // here, we're not going to remove the operand we find.
20092 SDValue Input = Op.getOperand(0);
20093 while (Input.getOpcode() == ISD::BITCAST)
20094 Input = Input.getOperand(0);
20096 MVT VT = Input.getSimpleValueType();
20097 MVT RootVT = Root.getSimpleValueType();
20100 // Just remove no-op shuffle masks.
20101 if (Mask.size() == 1) {
20102 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20107 // Use the float domain if the operand type is a floating point type.
20108 bool FloatDomain = VT.isFloatingPoint();
20110 // For floating point shuffles, we don't have free copies in the shuffle
20111 // instructions or the ability to load as part of the instruction, so
20112 // canonicalize their shuffles to UNPCK or MOV variants.
20114 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20115 // vectors because it can have a load folded into it that UNPCK cannot. This
20116 // doesn't preclude something switching to the shorter encoding post-RA.
20118 // FIXME: Should teach these routines about AVX vector widths.
20119 if (FloatDomain && VT.getSizeInBits() == 128) {
20120 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20121 bool Lo = Mask.equals({0, 0});
20124 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20125 // is no slower than UNPCKLPD but has the option to fold the input operand
20126 // into even an unaligned memory load.
20127 if (Lo && Subtarget->hasSSE3()) {
20128 Shuffle = X86ISD::MOVDDUP;
20129 ShuffleVT = MVT::v2f64;
20131 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20132 // than the UNPCK variants.
20133 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20134 ShuffleVT = MVT::v4f32;
20136 if (Depth == 1 && Root->getOpcode() == Shuffle)
20137 return false; // Nothing to do!
20138 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20139 DCI.AddToWorklist(Op.getNode());
20140 if (Shuffle == X86ISD::MOVDDUP)
20141 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20143 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20144 DCI.AddToWorklist(Op.getNode());
20145 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20149 if (Subtarget->hasSSE3() &&
20150 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20151 bool Lo = Mask.equals({0, 0, 2, 2});
20152 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20153 MVT ShuffleVT = MVT::v4f32;
20154 if (Depth == 1 && Root->getOpcode() == Shuffle)
20155 return false; // Nothing to do!
20156 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20157 DCI.AddToWorklist(Op.getNode());
20158 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20159 DCI.AddToWorklist(Op.getNode());
20160 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20164 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20165 bool Lo = Mask.equals({0, 0, 1, 1});
20166 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20167 MVT ShuffleVT = MVT::v4f32;
20168 if (Depth == 1 && Root->getOpcode() == Shuffle)
20169 return false; // Nothing to do!
20170 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20171 DCI.AddToWorklist(Op.getNode());
20172 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20173 DCI.AddToWorklist(Op.getNode());
20174 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20180 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20181 // variants as none of these have single-instruction variants that are
20182 // superior to the UNPCK formulation.
20183 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20184 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20185 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20186 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20188 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20189 bool Lo = Mask[0] == 0;
20190 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20191 if (Depth == 1 && Root->getOpcode() == Shuffle)
20192 return false; // Nothing to do!
20194 switch (Mask.size()) {
20196 ShuffleVT = MVT::v8i16;
20199 ShuffleVT = MVT::v16i8;
20202 llvm_unreachable("Impossible mask size!");
20204 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20205 DCI.AddToWorklist(Op.getNode());
20206 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20207 DCI.AddToWorklist(Op.getNode());
20208 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20213 // Don't try to re-form single instruction chains under any circumstances now
20214 // that we've done encoding canonicalization for them.
20218 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20219 // can replace them with a single PSHUFB instruction profitably. Intel's
20220 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20221 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20222 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20223 SmallVector<SDValue, 16> PSHUFBMask;
20224 int NumBytes = VT.getSizeInBits() / 8;
20225 int Ratio = NumBytes / Mask.size();
20226 for (int i = 0; i < NumBytes; ++i) {
20227 if (Mask[i / Ratio] == SM_SentinelUndef) {
20228 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20231 int M = Mask[i / Ratio] != SM_SentinelZero
20232 ? Ratio * Mask[i / Ratio] + i % Ratio
20234 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20236 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20237 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
20238 DCI.AddToWorklist(Op.getNode());
20239 SDValue PSHUFBMaskOp =
20240 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20241 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20242 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20243 DCI.AddToWorklist(Op.getNode());
20244 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20249 // Failed to find any combines.
20253 /// \brief Fully generic combining of x86 shuffle instructions.
20255 /// This should be the last combine run over the x86 shuffle instructions. Once
20256 /// they have been fully optimized, this will recursively consider all chains
20257 /// of single-use shuffle instructions, build a generic model of the cumulative
20258 /// shuffle operation, and check for simpler instructions which implement this
20259 /// operation. We use this primarily for two purposes:
20261 /// 1) Collapse generic shuffles to specialized single instructions when
20262 /// equivalent. In most cases, this is just an encoding size win, but
20263 /// sometimes we will collapse multiple generic shuffles into a single
20264 /// special-purpose shuffle.
20265 /// 2) Look for sequences of shuffle instructions with 3 or more total
20266 /// instructions, and replace them with the slightly more expensive SSSE3
20267 /// PSHUFB instruction if available. We do this as the last combining step
20268 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20269 /// a suitable short sequence of other instructions. The PHUFB will either
20270 /// use a register or have to read from memory and so is slightly (but only
20271 /// slightly) more expensive than the other shuffle instructions.
20273 /// Because this is inherently a quadratic operation (for each shuffle in
20274 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20275 /// This should never be an issue in practice as the shuffle lowering doesn't
20276 /// produce sequences of more than 8 instructions.
20278 /// FIXME: We will currently miss some cases where the redundant shuffling
20279 /// would simplify under the threshold for PSHUFB formation because of
20280 /// combine-ordering. To fix this, we should do the redundant instruction
20281 /// combining in this recursive walk.
20282 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20283 ArrayRef<int> RootMask,
20284 int Depth, bool HasPSHUFB,
20286 TargetLowering::DAGCombinerInfo &DCI,
20287 const X86Subtarget *Subtarget) {
20288 // Bound the depth of our recursive combine because this is ultimately
20289 // quadratic in nature.
20293 // Directly rip through bitcasts to find the underlying operand.
20294 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20295 Op = Op.getOperand(0);
20297 MVT VT = Op.getSimpleValueType();
20298 if (!VT.isVector())
20299 return false; // Bail if we hit a non-vector.
20301 assert(Root.getSimpleValueType().isVector() &&
20302 "Shuffles operate on vector types!");
20303 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20304 "Can only combine shuffles of the same vector register size.");
20306 if (!isTargetShuffle(Op.getOpcode()))
20308 SmallVector<int, 16> OpMask;
20310 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20311 // We only can combine unary shuffles which we can decode the mask for.
20312 if (!HaveMask || !IsUnary)
20315 assert(VT.getVectorNumElements() == OpMask.size() &&
20316 "Different mask size from vector size!");
20317 assert(((RootMask.size() > OpMask.size() &&
20318 RootMask.size() % OpMask.size() == 0) ||
20319 (OpMask.size() > RootMask.size() &&
20320 OpMask.size() % RootMask.size() == 0) ||
20321 OpMask.size() == RootMask.size()) &&
20322 "The smaller number of elements must divide the larger.");
20323 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20324 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20325 assert(((RootRatio == 1 && OpRatio == 1) ||
20326 (RootRatio == 1) != (OpRatio == 1)) &&
20327 "Must not have a ratio for both incoming and op masks!");
20329 SmallVector<int, 16> Mask;
20330 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20332 // Merge this shuffle operation's mask into our accumulated mask. Note that
20333 // this shuffle's mask will be the first applied to the input, followed by the
20334 // root mask to get us all the way to the root value arrangement. The reason
20335 // for this order is that we are recursing up the operation chain.
20336 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20337 int RootIdx = i / RootRatio;
20338 if (RootMask[RootIdx] < 0) {
20339 // This is a zero or undef lane, we're done.
20340 Mask.push_back(RootMask[RootIdx]);
20344 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20345 int OpIdx = RootMaskedIdx / OpRatio;
20346 if (OpMask[OpIdx] < 0) {
20347 // The incoming lanes are zero or undef, it doesn't matter which ones we
20349 Mask.push_back(OpMask[OpIdx]);
20353 // Ok, we have non-zero lanes, map them through.
20354 Mask.push_back(OpMask[OpIdx] * OpRatio +
20355 RootMaskedIdx % OpRatio);
20358 // See if we can recurse into the operand to combine more things.
20359 switch (Op.getOpcode()) {
20360 case X86ISD::PSHUFB:
20362 case X86ISD::PSHUFD:
20363 case X86ISD::PSHUFHW:
20364 case X86ISD::PSHUFLW:
20365 if (Op.getOperand(0).hasOneUse() &&
20366 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20367 HasPSHUFB, DAG, DCI, Subtarget))
20371 case X86ISD::UNPCKL:
20372 case X86ISD::UNPCKH:
20373 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20374 // We can't check for single use, we have to check that this shuffle is the only user.
20375 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20376 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20377 HasPSHUFB, DAG, DCI, Subtarget))
20382 // Minor canonicalization of the accumulated shuffle mask to make it easier
20383 // to match below. All this does is detect masks with squential pairs of
20384 // elements, and shrink them to the half-width mask. It does this in a loop
20385 // so it will reduce the size of the mask to the minimal width mask which
20386 // performs an equivalent shuffle.
20387 SmallVector<int, 16> WidenedMask;
20388 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20389 Mask = std::move(WidenedMask);
20390 WidenedMask.clear();
20393 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20397 /// \brief Get the PSHUF-style mask from PSHUF node.
20399 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20400 /// PSHUF-style masks that can be reused with such instructions.
20401 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20402 MVT VT = N.getSimpleValueType();
20403 SmallVector<int, 4> Mask;
20405 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20409 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20410 // matter. Check that the upper masks are repeats and remove them.
20411 if (VT.getSizeInBits() > 128) {
20412 int LaneElts = 128 / VT.getScalarSizeInBits();
20414 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20415 for (int j = 0; j < LaneElts; ++j)
20416 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
20417 "Mask doesn't repeat in high 128-bit lanes!");
20419 Mask.resize(LaneElts);
20422 switch (N.getOpcode()) {
20423 case X86ISD::PSHUFD:
20425 case X86ISD::PSHUFLW:
20428 case X86ISD::PSHUFHW:
20429 Mask.erase(Mask.begin(), Mask.begin() + 4);
20430 for (int &M : Mask)
20434 llvm_unreachable("No valid shuffle instruction found!");
20438 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20440 /// We walk up the chain and look for a combinable shuffle, skipping over
20441 /// shuffles that we could hoist this shuffle's transformation past without
20442 /// altering anything.
20444 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20446 TargetLowering::DAGCombinerInfo &DCI) {
20447 assert(N.getOpcode() == X86ISD::PSHUFD &&
20448 "Called with something other than an x86 128-bit half shuffle!");
20451 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20452 // of the shuffles in the chain so that we can form a fresh chain to replace
20454 SmallVector<SDValue, 8> Chain;
20455 SDValue V = N.getOperand(0);
20456 for (; V.hasOneUse(); V = V.getOperand(0)) {
20457 switch (V.getOpcode()) {
20459 return SDValue(); // Nothing combined!
20462 // Skip bitcasts as we always know the type for the target specific
20466 case X86ISD::PSHUFD:
20467 // Found another dword shuffle.
20470 case X86ISD::PSHUFLW:
20471 // Check that the low words (being shuffled) are the identity in the
20472 // dword shuffle, and the high words are self-contained.
20473 if (Mask[0] != 0 || Mask[1] != 1 ||
20474 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20477 Chain.push_back(V);
20480 case X86ISD::PSHUFHW:
20481 // Check that the high words (being shuffled) are the identity in the
20482 // dword shuffle, and the low words are self-contained.
20483 if (Mask[2] != 2 || Mask[3] != 3 ||
20484 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20487 Chain.push_back(V);
20490 case X86ISD::UNPCKL:
20491 case X86ISD::UNPCKH:
20492 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20493 // shuffle into a preceding word shuffle.
20494 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20495 V.getSimpleValueType().getScalarType() != MVT::i16)
20498 // Search for a half-shuffle which we can combine with.
20499 unsigned CombineOp =
20500 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20501 if (V.getOperand(0) != V.getOperand(1) ||
20502 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20504 Chain.push_back(V);
20505 V = V.getOperand(0);
20507 switch (V.getOpcode()) {
20509 return SDValue(); // Nothing to combine.
20511 case X86ISD::PSHUFLW:
20512 case X86ISD::PSHUFHW:
20513 if (V.getOpcode() == CombineOp)
20516 Chain.push_back(V);
20520 V = V.getOperand(0);
20524 } while (V.hasOneUse());
20527 // Break out of the loop if we break out of the switch.
20531 if (!V.hasOneUse())
20532 // We fell out of the loop without finding a viable combining instruction.
20535 // Merge this node's mask and our incoming mask.
20536 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20537 for (int &M : Mask)
20539 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20540 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20542 // Rebuild the chain around this new shuffle.
20543 while (!Chain.empty()) {
20544 SDValue W = Chain.pop_back_val();
20546 if (V.getValueType() != W.getOperand(0).getValueType())
20547 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20549 switch (W.getOpcode()) {
20551 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20553 case X86ISD::UNPCKL:
20554 case X86ISD::UNPCKH:
20555 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20558 case X86ISD::PSHUFD:
20559 case X86ISD::PSHUFLW:
20560 case X86ISD::PSHUFHW:
20561 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20565 if (V.getValueType() != N.getValueType())
20566 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20568 // Return the new chain to replace N.
20572 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20574 /// We walk up the chain, skipping shuffles of the other half and looking
20575 /// through shuffles which switch halves trying to find a shuffle of the same
20576 /// pair of dwords.
20577 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20579 TargetLowering::DAGCombinerInfo &DCI) {
20581 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20582 "Called with something other than an x86 128-bit half shuffle!");
20584 unsigned CombineOpcode = N.getOpcode();
20586 // Walk up a single-use chain looking for a combinable shuffle.
20587 SDValue V = N.getOperand(0);
20588 for (; V.hasOneUse(); V = V.getOperand(0)) {
20589 switch (V.getOpcode()) {
20591 return false; // Nothing combined!
20594 // Skip bitcasts as we always know the type for the target specific
20598 case X86ISD::PSHUFLW:
20599 case X86ISD::PSHUFHW:
20600 if (V.getOpcode() == CombineOpcode)
20603 // Other-half shuffles are no-ops.
20606 // Break out of the loop if we break out of the switch.
20610 if (!V.hasOneUse())
20611 // We fell out of the loop without finding a viable combining instruction.
20614 // Combine away the bottom node as its shuffle will be accumulated into
20615 // a preceding shuffle.
20616 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20618 // Record the old value.
20621 // Merge this node's mask and our incoming mask (adjusted to account for all
20622 // the pshufd instructions encountered).
20623 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20624 for (int &M : Mask)
20626 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20627 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20629 // Check that the shuffles didn't cancel each other out. If not, we need to
20630 // combine to the new one.
20632 // Replace the combinable shuffle with the combined one, updating all users
20633 // so that we re-evaluate the chain here.
20634 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20639 /// \brief Try to combine x86 target specific shuffles.
20640 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20641 TargetLowering::DAGCombinerInfo &DCI,
20642 const X86Subtarget *Subtarget) {
20644 MVT VT = N.getSimpleValueType();
20645 SmallVector<int, 4> Mask;
20647 switch (N.getOpcode()) {
20648 case X86ISD::PSHUFD:
20649 case X86ISD::PSHUFLW:
20650 case X86ISD::PSHUFHW:
20651 Mask = getPSHUFShuffleMask(N);
20652 assert(Mask.size() == 4);
20658 // Nuke no-op shuffles that show up after combining.
20659 if (isNoopShuffleMask(Mask))
20660 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20662 // Look for simplifications involving one or two shuffle instructions.
20663 SDValue V = N.getOperand(0);
20664 switch (N.getOpcode()) {
20667 case X86ISD::PSHUFLW:
20668 case X86ISD::PSHUFHW:
20669 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20671 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20672 return SDValue(); // We combined away this shuffle, so we're done.
20674 // See if this reduces to a PSHUFD which is no more expensive and can
20675 // combine with more operations. Note that it has to at least flip the
20676 // dwords as otherwise it would have been removed as a no-op.
20677 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20678 int DMask[] = {0, 1, 2, 3};
20679 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20680 DMask[DOffset + 0] = DOffset + 1;
20681 DMask[DOffset + 1] = DOffset + 0;
20682 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20683 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20684 DCI.AddToWorklist(V.getNode());
20685 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20686 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20687 DCI.AddToWorklist(V.getNode());
20688 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20691 // Look for shuffle patterns which can be implemented as a single unpack.
20692 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20693 // only works when we have a PSHUFD followed by two half-shuffles.
20694 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20695 (V.getOpcode() == X86ISD::PSHUFLW ||
20696 V.getOpcode() == X86ISD::PSHUFHW) &&
20697 V.getOpcode() != N.getOpcode() &&
20699 SDValue D = V.getOperand(0);
20700 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20701 D = D.getOperand(0);
20702 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20703 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20704 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20705 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20706 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20708 for (int i = 0; i < 4; ++i) {
20709 WordMask[i + NOffset] = Mask[i] + NOffset;
20710 WordMask[i + VOffset] = VMask[i] + VOffset;
20712 // Map the word mask through the DWord mask.
20714 for (int i = 0; i < 8; ++i)
20715 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20716 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20717 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20718 // We can replace all three shuffles with an unpack.
20719 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20720 DCI.AddToWorklist(V.getNode());
20721 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20730 case X86ISD::PSHUFD:
20731 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20740 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20742 /// We combine this directly on the abstract vector shuffle nodes so it is
20743 /// easier to generically match. We also insert dummy vector shuffle nodes for
20744 /// the operands which explicitly discard the lanes which are unused by this
20745 /// operation to try to flow through the rest of the combiner the fact that
20746 /// they're unused.
20747 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20749 EVT VT = N->getValueType(0);
20751 // We only handle target-independent shuffles.
20752 // FIXME: It would be easy and harmless to use the target shuffle mask
20753 // extraction tool to support more.
20754 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20757 auto *SVN = cast<ShuffleVectorSDNode>(N);
20758 ArrayRef<int> Mask = SVN->getMask();
20759 SDValue V1 = N->getOperand(0);
20760 SDValue V2 = N->getOperand(1);
20762 // We require the first shuffle operand to be the SUB node, and the second to
20763 // be the ADD node.
20764 // FIXME: We should support the commuted patterns.
20765 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20768 // If there are other uses of these operations we can't fold them.
20769 if (!V1->hasOneUse() || !V2->hasOneUse())
20772 // Ensure that both operations have the same operands. Note that we can
20773 // commute the FADD operands.
20774 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20775 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20776 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20779 // We're looking for blends between FADD and FSUB nodes. We insist on these
20780 // nodes being lined up in a specific expected pattern.
20781 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20782 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20783 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20786 // Only specific types are legal at this point, assert so we notice if and
20787 // when these change.
20788 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20789 VT == MVT::v4f64) &&
20790 "Unknown vector type encountered!");
20792 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20795 /// PerformShuffleCombine - Performs several different shuffle combines.
20796 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20797 TargetLowering::DAGCombinerInfo &DCI,
20798 const X86Subtarget *Subtarget) {
20800 SDValue N0 = N->getOperand(0);
20801 SDValue N1 = N->getOperand(1);
20802 EVT VT = N->getValueType(0);
20804 // Don't create instructions with illegal types after legalize types has run.
20805 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20806 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20809 // If we have legalized the vector types, look for blends of FADD and FSUB
20810 // nodes that we can fuse into an ADDSUB node.
20811 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20812 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20815 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20816 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20817 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20818 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20820 // During Type Legalization, when promoting illegal vector types,
20821 // the backend might introduce new shuffle dag nodes and bitcasts.
20823 // This code performs the following transformation:
20824 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20825 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20827 // We do this only if both the bitcast and the BINOP dag nodes have
20828 // one use. Also, perform this transformation only if the new binary
20829 // operation is legal. This is to avoid introducing dag nodes that
20830 // potentially need to be further expanded (or custom lowered) into a
20831 // less optimal sequence of dag nodes.
20832 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20833 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20834 N0.getOpcode() == ISD::BITCAST) {
20835 SDValue BC0 = N0.getOperand(0);
20836 EVT SVT = BC0.getValueType();
20837 unsigned Opcode = BC0.getOpcode();
20838 unsigned NumElts = VT.getVectorNumElements();
20840 if (BC0.hasOneUse() && SVT.isVector() &&
20841 SVT.getVectorNumElements() * 2 == NumElts &&
20842 TLI.isOperationLegal(Opcode, VT)) {
20843 bool CanFold = false;
20855 unsigned SVTNumElts = SVT.getVectorNumElements();
20856 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20857 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20858 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20859 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20860 CanFold = SVOp->getMaskElt(i) < 0;
20863 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20864 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20865 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20866 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20871 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20872 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20873 // consecutive, non-overlapping, and in the right order.
20874 SmallVector<SDValue, 16> Elts;
20875 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20876 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20878 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20882 if (isTargetShuffle(N->getOpcode())) {
20884 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20885 if (Shuffle.getNode())
20888 // Try recursively combining arbitrary sequences of x86 shuffle
20889 // instructions into higher-order shuffles. We do this after combining
20890 // specific PSHUF instruction sequences into their minimal form so that we
20891 // can evaluate how many specialized shuffle instructions are involved in
20892 // a particular chain.
20893 SmallVector<int, 1> NonceMask; // Just a placeholder.
20894 NonceMask.push_back(0);
20895 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20896 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20898 return SDValue(); // This routine will use CombineTo to replace N.
20904 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20905 /// specific shuffle of a load can be folded into a single element load.
20906 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20907 /// shuffles have been custom lowered so we need to handle those here.
20908 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20909 TargetLowering::DAGCombinerInfo &DCI) {
20910 if (DCI.isBeforeLegalizeOps())
20913 SDValue InVec = N->getOperand(0);
20914 SDValue EltNo = N->getOperand(1);
20916 if (!isa<ConstantSDNode>(EltNo))
20919 EVT OriginalVT = InVec.getValueType();
20921 if (InVec.getOpcode() == ISD::BITCAST) {
20922 // Don't duplicate a load with other uses.
20923 if (!InVec.hasOneUse())
20925 EVT BCVT = InVec.getOperand(0).getValueType();
20926 if (!BCVT.isVector() ||
20927 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20929 InVec = InVec.getOperand(0);
20932 EVT CurrentVT = InVec.getValueType();
20934 if (!isTargetShuffle(InVec.getOpcode()))
20937 // Don't duplicate a load with other uses.
20938 if (!InVec.hasOneUse())
20941 SmallVector<int, 16> ShuffleMask;
20943 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20944 ShuffleMask, UnaryShuffle))
20947 // Select the input vector, guarding against out of range extract vector.
20948 unsigned NumElems = CurrentVT.getVectorNumElements();
20949 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20950 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20951 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20952 : InVec.getOperand(1);
20954 // If inputs to shuffle are the same for both ops, then allow 2 uses
20955 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20956 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20958 if (LdNode.getOpcode() == ISD::BITCAST) {
20959 // Don't duplicate a load with other uses.
20960 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20963 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20964 LdNode = LdNode.getOperand(0);
20967 if (!ISD::isNormalLoad(LdNode.getNode()))
20970 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20972 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20975 EVT EltVT = N->getValueType(0);
20976 // If there's a bitcast before the shuffle, check if the load type and
20977 // alignment is valid.
20978 unsigned Align = LN0->getAlignment();
20979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20980 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20981 EltVT.getTypeForEVT(*DAG.getContext()));
20983 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20986 // All checks match so transform back to vector_shuffle so that DAG combiner
20987 // can finish the job
20990 // Create shuffle node taking into account the case that its a unary shuffle
20991 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20992 : InVec.getOperand(1);
20993 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20994 InVec.getOperand(0), Shuffle,
20996 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20997 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21001 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21002 /// special and don't usually play with other vector types, it's better to
21003 /// handle them early to be sure we emit efficient code by avoiding
21004 /// store-load conversions.
21005 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21006 if (N->getValueType(0) != MVT::x86mmx ||
21007 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21008 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21011 SDValue V = N->getOperand(0);
21012 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21013 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21014 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21015 N->getValueType(0), V.getOperand(0));
21020 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21021 /// generation and convert it from being a bunch of shuffles and extracts
21022 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21023 /// storing the value and loading scalars back, while for x64 we should
21024 /// use 64-bit extracts and shifts.
21025 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21026 TargetLowering::DAGCombinerInfo &DCI) {
21027 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21028 if (NewOp.getNode())
21031 SDValue InputVector = N->getOperand(0);
21032 SDLoc dl(InputVector);
21033 // Detect mmx to i32 conversion through a v2i32 elt extract.
21034 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21035 N->getValueType(0) == MVT::i32 &&
21036 InputVector.getValueType() == MVT::v2i32) {
21038 // The bitcast source is a direct mmx result.
21039 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21040 if (MMXSrc.getValueType() == MVT::x86mmx)
21041 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21042 N->getValueType(0),
21043 InputVector.getNode()->getOperand(0));
21045 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21046 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21047 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21048 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21049 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21050 MMXSrcOp.getValueType() == MVT::v1i64 &&
21051 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21052 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21053 N->getValueType(0),
21054 MMXSrcOp.getOperand(0));
21057 EVT VT = N->getValueType(0);
21059 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21060 InputVector.getOpcode() == ISD::BITCAST &&
21061 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21062 uint64_t ExtractedElt =
21063 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21064 uint64_t InputValue =
21065 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21066 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21067 return DAG.getConstant(Res, dl, MVT::i1);
21069 // Only operate on vectors of 4 elements, where the alternative shuffling
21070 // gets to be more expensive.
21071 if (InputVector.getValueType() != MVT::v4i32)
21074 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21075 // single use which is a sign-extend or zero-extend, and all elements are
21077 SmallVector<SDNode *, 4> Uses;
21078 unsigned ExtractedElements = 0;
21079 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21080 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21081 if (UI.getUse().getResNo() != InputVector.getResNo())
21084 SDNode *Extract = *UI;
21085 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21088 if (Extract->getValueType(0) != MVT::i32)
21090 if (!Extract->hasOneUse())
21092 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21093 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21095 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21098 // Record which element was extracted.
21099 ExtractedElements |=
21100 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21102 Uses.push_back(Extract);
21105 // If not all the elements were used, this may not be worthwhile.
21106 if (ExtractedElements != 15)
21109 // Ok, we've now decided to do the transformation.
21110 // If 64-bit shifts are legal, use the extract-shift sequence,
21111 // otherwise bounce the vector off the cache.
21112 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21115 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21116 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
21117 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21118 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21119 DAG.getConstant(0, dl, VecIdxTy));
21120 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21121 DAG.getConstant(1, dl, VecIdxTy));
21123 SDValue ShAmt = DAG.getConstant(32, dl,
21124 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21125 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21126 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21127 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21128 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21129 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21130 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21132 // Store the value to a temporary stack slot.
21133 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21134 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21135 MachinePointerInfo(), false, false, 0);
21137 EVT ElementType = InputVector.getValueType().getVectorElementType();
21138 unsigned EltSize = ElementType.getSizeInBits() / 8;
21140 // Replace each use (extract) with a load of the appropriate element.
21141 for (unsigned i = 0; i < 4; ++i) {
21142 uint64_t Offset = EltSize * i;
21143 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21145 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21146 StackPtr, OffsetVal);
21148 // Load the scalar.
21149 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21150 ScalarAddr, MachinePointerInfo(),
21151 false, false, false, 0);
21156 // Replace the extracts
21157 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21158 UE = Uses.end(); UI != UE; ++UI) {
21159 SDNode *Extract = *UI;
21161 SDValue Idx = Extract->getOperand(1);
21162 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21163 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21166 // The replacement was made in place; don't return anything.
21170 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21171 static std::pair<unsigned, bool>
21172 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21173 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21174 if (!VT.isVector())
21175 return std::make_pair(0, false);
21177 bool NeedSplit = false;
21178 switch (VT.getSimpleVT().SimpleTy) {
21179 default: return std::make_pair(0, false);
21182 if (!Subtarget->hasVLX())
21183 return std::make_pair(0, false);
21187 if (!Subtarget->hasBWI())
21188 return std::make_pair(0, false);
21192 if (!Subtarget->hasAVX512())
21193 return std::make_pair(0, false);
21198 if (!Subtarget->hasAVX2())
21200 if (!Subtarget->hasAVX())
21201 return std::make_pair(0, false);
21206 if (!Subtarget->hasSSE2())
21207 return std::make_pair(0, false);
21210 // SSE2 has only a small subset of the operations.
21211 bool hasUnsigned = Subtarget->hasSSE41() ||
21212 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21213 bool hasSigned = Subtarget->hasSSE41() ||
21214 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21216 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21219 // Check for x CC y ? x : y.
21220 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21221 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21226 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21229 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21232 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21235 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21237 // Check for x CC y ? y : x -- a min/max with reversed arms.
21238 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21239 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21244 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21247 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21250 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21253 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21257 return std::make_pair(Opc, NeedSplit);
21261 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21262 const X86Subtarget *Subtarget) {
21264 SDValue Cond = N->getOperand(0);
21265 SDValue LHS = N->getOperand(1);
21266 SDValue RHS = N->getOperand(2);
21268 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21269 SDValue CondSrc = Cond->getOperand(0);
21270 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21271 Cond = CondSrc->getOperand(0);
21274 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21277 // A vselect where all conditions and data are constants can be optimized into
21278 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21279 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21280 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21283 unsigned MaskValue = 0;
21284 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21287 MVT VT = N->getSimpleValueType(0);
21288 unsigned NumElems = VT.getVectorNumElements();
21289 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21290 for (unsigned i = 0; i < NumElems; ++i) {
21291 // Be sure we emit undef where we can.
21292 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21293 ShuffleMask[i] = -1;
21295 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21299 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21301 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21304 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21306 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21307 TargetLowering::DAGCombinerInfo &DCI,
21308 const X86Subtarget *Subtarget) {
21310 SDValue Cond = N->getOperand(0);
21311 // Get the LHS/RHS of the select.
21312 SDValue LHS = N->getOperand(1);
21313 SDValue RHS = N->getOperand(2);
21314 EVT VT = LHS.getValueType();
21315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21317 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21318 // instructions match the semantics of the common C idiom x<y?x:y but not
21319 // x<=y?x:y, because of how they handle negative zero (which can be
21320 // ignored in unsafe-math mode).
21321 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21322 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21323 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21324 (Subtarget->hasSSE2() ||
21325 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21326 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21328 unsigned Opcode = 0;
21329 // Check for x CC y ? x : y.
21330 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21331 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21335 // Converting this to a min would handle NaNs incorrectly, and swapping
21336 // the operands would cause it to handle comparisons between positive
21337 // and negative zero incorrectly.
21338 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21339 if (!DAG.getTarget().Options.UnsafeFPMath &&
21340 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21342 std::swap(LHS, RHS);
21344 Opcode = X86ISD::FMIN;
21347 // Converting this to a min would handle comparisons between positive
21348 // and negative zero incorrectly.
21349 if (!DAG.getTarget().Options.UnsafeFPMath &&
21350 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21352 Opcode = X86ISD::FMIN;
21355 // Converting this to a min would handle both negative zeros and NaNs
21356 // incorrectly, but we can swap the operands to fix both.
21357 std::swap(LHS, RHS);
21361 Opcode = X86ISD::FMIN;
21365 // Converting this to a max would handle comparisons between positive
21366 // and negative zero incorrectly.
21367 if (!DAG.getTarget().Options.UnsafeFPMath &&
21368 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21370 Opcode = X86ISD::FMAX;
21373 // Converting this to a max would handle NaNs incorrectly, and swapping
21374 // the operands would cause it to handle comparisons between positive
21375 // and negative zero incorrectly.
21376 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21377 if (!DAG.getTarget().Options.UnsafeFPMath &&
21378 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21380 std::swap(LHS, RHS);
21382 Opcode = X86ISD::FMAX;
21385 // Converting this to a max would handle both negative zeros and NaNs
21386 // incorrectly, but we can swap the operands to fix both.
21387 std::swap(LHS, RHS);
21391 Opcode = X86ISD::FMAX;
21394 // Check for x CC y ? y : x -- a min/max with reversed arms.
21395 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21396 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21400 // Converting this to a min would handle comparisons between positive
21401 // and negative zero incorrectly, and swapping the operands would
21402 // cause it to handle NaNs incorrectly.
21403 if (!DAG.getTarget().Options.UnsafeFPMath &&
21404 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21405 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21407 std::swap(LHS, RHS);
21409 Opcode = X86ISD::FMIN;
21412 // Converting this to a min would handle NaNs incorrectly.
21413 if (!DAG.getTarget().Options.UnsafeFPMath &&
21414 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21416 Opcode = X86ISD::FMIN;
21419 // Converting this to a min would handle both negative zeros and NaNs
21420 // incorrectly, but we can swap the operands to fix both.
21421 std::swap(LHS, RHS);
21425 Opcode = X86ISD::FMIN;
21429 // Converting this to a max would handle NaNs incorrectly.
21430 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21432 Opcode = X86ISD::FMAX;
21435 // Converting this to a max would handle comparisons between positive
21436 // and negative zero incorrectly, and swapping the operands would
21437 // cause it to handle NaNs incorrectly.
21438 if (!DAG.getTarget().Options.UnsafeFPMath &&
21439 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21440 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21442 std::swap(LHS, RHS);
21444 Opcode = X86ISD::FMAX;
21447 // Converting this to a max would handle both negative zeros and NaNs
21448 // incorrectly, but we can swap the operands to fix both.
21449 std::swap(LHS, RHS);
21453 Opcode = X86ISD::FMAX;
21459 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21462 EVT CondVT = Cond.getValueType();
21463 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21464 CondVT.getVectorElementType() == MVT::i1) {
21465 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21466 // lowering on KNL. In this case we convert it to
21467 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21468 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21469 // Since SKX these selects have a proper lowering.
21470 EVT OpVT = LHS.getValueType();
21471 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21472 (OpVT.getVectorElementType() == MVT::i8 ||
21473 OpVT.getVectorElementType() == MVT::i16) &&
21474 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21475 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21476 DCI.AddToWorklist(Cond.getNode());
21477 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21480 // If this is a select between two integer constants, try to do some
21482 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21483 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21484 // Don't do this for crazy integer types.
21485 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21486 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21487 // so that TrueC (the true value) is larger than FalseC.
21488 bool NeedsCondInvert = false;
21490 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21491 // Efficiently invertible.
21492 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21493 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21494 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21495 NeedsCondInvert = true;
21496 std::swap(TrueC, FalseC);
21499 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21500 if (FalseC->getAPIntValue() == 0 &&
21501 TrueC->getAPIntValue().isPowerOf2()) {
21502 if (NeedsCondInvert) // Invert the condition if needed.
21503 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21504 DAG.getConstant(1, DL, Cond.getValueType()));
21506 // Zero extend the condition if needed.
21507 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21509 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21510 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21511 DAG.getConstant(ShAmt, DL, MVT::i8));
21514 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21515 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21516 if (NeedsCondInvert) // Invert the condition if needed.
21517 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21518 DAG.getConstant(1, DL, Cond.getValueType()));
21520 // Zero extend the condition if needed.
21521 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21522 FalseC->getValueType(0), Cond);
21523 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21524 SDValue(FalseC, 0));
21527 // Optimize cases that will turn into an LEA instruction. This requires
21528 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21529 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21530 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21531 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21533 bool isFastMultiplier = false;
21535 switch ((unsigned char)Diff) {
21537 case 1: // result = add base, cond
21538 case 2: // result = lea base( , cond*2)
21539 case 3: // result = lea base(cond, cond*2)
21540 case 4: // result = lea base( , cond*4)
21541 case 5: // result = lea base(cond, cond*4)
21542 case 8: // result = lea base( , cond*8)
21543 case 9: // result = lea base(cond, cond*8)
21544 isFastMultiplier = true;
21549 if (isFastMultiplier) {
21550 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21551 if (NeedsCondInvert) // Invert the condition if needed.
21552 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21553 DAG.getConstant(1, DL, Cond.getValueType()));
21555 // Zero extend the condition if needed.
21556 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21558 // Scale the condition by the difference.
21560 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21561 DAG.getConstant(Diff, DL,
21562 Cond.getValueType()));
21564 // Add the base if non-zero.
21565 if (FalseC->getAPIntValue() != 0)
21566 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21567 SDValue(FalseC, 0));
21574 // Canonicalize max and min:
21575 // (x > y) ? x : y -> (x >= y) ? x : y
21576 // (x < y) ? x : y -> (x <= y) ? x : y
21577 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21578 // the need for an extra compare
21579 // against zero. e.g.
21580 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21582 // testl %edi, %edi
21584 // cmovgl %edi, %eax
21588 // cmovsl %eax, %edi
21589 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21590 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21591 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21592 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21597 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21598 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21599 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21600 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21605 // Early exit check
21606 if (!TLI.isTypeLegal(VT))
21609 // Match VSELECTs into subs with unsigned saturation.
21610 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21611 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21612 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21613 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21614 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21616 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21617 // left side invert the predicate to simplify logic below.
21619 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21621 CC = ISD::getSetCCInverse(CC, true);
21622 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21626 if (Other.getNode() && Other->getNumOperands() == 2 &&
21627 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21628 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21629 SDValue CondRHS = Cond->getOperand(1);
21631 // Look for a general sub with unsigned saturation first.
21632 // x >= y ? x-y : 0 --> subus x, y
21633 // x > y ? x-y : 0 --> subus x, y
21634 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21635 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21636 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21638 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21639 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21640 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21641 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21642 // If the RHS is a constant we have to reverse the const
21643 // canonicalization.
21644 // x > C-1 ? x+-C : 0 --> subus x, C
21645 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21646 CondRHSConst->getAPIntValue() ==
21647 (-OpRHSConst->getAPIntValue() - 1))
21648 return DAG.getNode(
21649 X86ISD::SUBUS, DL, VT, OpLHS,
21650 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21652 // Another special case: If C was a sign bit, the sub has been
21653 // canonicalized into a xor.
21654 // FIXME: Would it be better to use computeKnownBits to determine
21655 // whether it's safe to decanonicalize the xor?
21656 // x s< 0 ? x^C : 0 --> subus x, C
21657 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21658 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21659 OpRHSConst->getAPIntValue().isSignBit())
21660 // Note that we have to rebuild the RHS constant here to ensure we
21661 // don't rely on particular values of undef lanes.
21662 return DAG.getNode(
21663 X86ISD::SUBUS, DL, VT, OpLHS,
21664 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21669 // Try to match a min/max vector operation.
21670 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21671 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21672 unsigned Opc = ret.first;
21673 bool NeedSplit = ret.second;
21675 if (Opc && NeedSplit) {
21676 unsigned NumElems = VT.getVectorNumElements();
21677 // Extract the LHS vectors
21678 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21679 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21681 // Extract the RHS vectors
21682 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21683 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21685 // Create min/max for each subvector
21686 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21687 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21689 // Merge the result
21690 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21692 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21695 // Simplify vector selection if condition value type matches vselect
21697 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21698 assert(Cond.getValueType().isVector() &&
21699 "vector select expects a vector selector!");
21701 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21702 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21704 // Try invert the condition if true value is not all 1s and false value
21706 if (!TValIsAllOnes && !FValIsAllZeros &&
21707 // Check if the selector will be produced by CMPP*/PCMP*
21708 Cond.getOpcode() == ISD::SETCC &&
21709 // Check if SETCC has already been promoted
21710 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21711 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21712 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21714 if (TValIsAllZeros || FValIsAllOnes) {
21715 SDValue CC = Cond.getOperand(2);
21716 ISD::CondCode NewCC =
21717 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21718 Cond.getOperand(0).getValueType().isInteger());
21719 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21720 std::swap(LHS, RHS);
21721 TValIsAllOnes = FValIsAllOnes;
21722 FValIsAllZeros = TValIsAllZeros;
21726 if (TValIsAllOnes || FValIsAllZeros) {
21729 if (TValIsAllOnes && FValIsAllZeros)
21731 else if (TValIsAllOnes)
21732 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21733 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21734 else if (FValIsAllZeros)
21735 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21736 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21738 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21742 // We should generate an X86ISD::BLENDI from a vselect if its argument
21743 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21744 // constants. This specific pattern gets generated when we split a
21745 // selector for a 512 bit vector in a machine without AVX512 (but with
21746 // 256-bit vectors), during legalization:
21748 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21750 // Iff we find this pattern and the build_vectors are built from
21751 // constants, we translate the vselect into a shuffle_vector that we
21752 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21753 if ((N->getOpcode() == ISD::VSELECT ||
21754 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21755 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
21756 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21757 if (Shuffle.getNode())
21761 // If this is a *dynamic* select (non-constant condition) and we can match
21762 // this node with one of the variable blend instructions, restructure the
21763 // condition so that the blends can use the high bit of each element and use
21764 // SimplifyDemandedBits to simplify the condition operand.
21765 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21766 !DCI.isBeforeLegalize() &&
21767 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21768 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21770 // Don't optimize vector selects that map to mask-registers.
21774 // We can only handle the cases where VSELECT is directly legal on the
21775 // subtarget. We custom lower VSELECT nodes with constant conditions and
21776 // this makes it hard to see whether a dynamic VSELECT will correctly
21777 // lower, so we both check the operation's status and explicitly handle the
21778 // cases where a *dynamic* blend will fail even though a constant-condition
21779 // blend could be custom lowered.
21780 // FIXME: We should find a better way to handle this class of problems.
21781 // Potentially, we should combine constant-condition vselect nodes
21782 // pre-legalization into shuffles and not mark as many types as custom
21784 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21786 // FIXME: We don't support i16-element blends currently. We could and
21787 // should support them by making *all* the bits in the condition be set
21788 // rather than just the high bit and using an i8-element blend.
21789 if (VT.getScalarType() == MVT::i16)
21791 // Dynamic blending was only available from SSE4.1 onward.
21792 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21794 // Byte blends are only available in AVX2
21795 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21796 !Subtarget->hasAVX2())
21799 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21800 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21802 APInt KnownZero, KnownOne;
21803 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21804 DCI.isBeforeLegalizeOps());
21805 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21806 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21808 // If we changed the computation somewhere in the DAG, this change
21809 // will affect all users of Cond.
21810 // Make sure it is fine and update all the nodes so that we do not
21811 // use the generic VSELECT anymore. Otherwise, we may perform
21812 // wrong optimizations as we messed up with the actual expectation
21813 // for the vector boolean values.
21814 if (Cond != TLO.Old) {
21815 // Check all uses of that condition operand to check whether it will be
21816 // consumed by non-BLEND instructions, which may depend on all bits are
21818 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21820 if (I->getOpcode() != ISD::VSELECT)
21821 // TODO: Add other opcodes eventually lowered into BLEND.
21824 // Update all the users of the condition, before committing the change,
21825 // so that the VSELECT optimizations that expect the correct vector
21826 // boolean value will not be triggered.
21827 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21829 DAG.ReplaceAllUsesOfValueWith(
21831 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21832 Cond, I->getOperand(1), I->getOperand(2)));
21833 DCI.CommitTargetLoweringOpt(TLO);
21836 // At this point, only Cond is changed. Change the condition
21837 // just for N to keep the opportunity to optimize all other
21838 // users their own way.
21839 DAG.ReplaceAllUsesOfValueWith(
21841 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21842 TLO.New, N->getOperand(1), N->getOperand(2)));
21850 // Check whether a boolean test is testing a boolean value generated by
21851 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21854 // Simplify the following patterns:
21855 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21856 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21857 // to (Op EFLAGS Cond)
21859 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21860 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21861 // to (Op EFLAGS !Cond)
21863 // where Op could be BRCOND or CMOV.
21865 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21866 // Quit if not CMP and SUB with its value result used.
21867 if (Cmp.getOpcode() != X86ISD::CMP &&
21868 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21871 // Quit if not used as a boolean value.
21872 if (CC != X86::COND_E && CC != X86::COND_NE)
21875 // Check CMP operands. One of them should be 0 or 1 and the other should be
21876 // an SetCC or extended from it.
21877 SDValue Op1 = Cmp.getOperand(0);
21878 SDValue Op2 = Cmp.getOperand(1);
21881 const ConstantSDNode* C = nullptr;
21882 bool needOppositeCond = (CC == X86::COND_E);
21883 bool checkAgainstTrue = false; // Is it a comparison against 1?
21885 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21887 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21889 else // Quit if all operands are not constants.
21892 if (C->getZExtValue() == 1) {
21893 needOppositeCond = !needOppositeCond;
21894 checkAgainstTrue = true;
21895 } else if (C->getZExtValue() != 0)
21896 // Quit if the constant is neither 0 or 1.
21899 bool truncatedToBoolWithAnd = false;
21900 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21901 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21902 SetCC.getOpcode() == ISD::TRUNCATE ||
21903 SetCC.getOpcode() == ISD::AND) {
21904 if (SetCC.getOpcode() == ISD::AND) {
21906 ConstantSDNode *CS;
21907 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21908 CS->getZExtValue() == 1)
21910 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21911 CS->getZExtValue() == 1)
21915 SetCC = SetCC.getOperand(OpIdx);
21916 truncatedToBoolWithAnd = true;
21918 SetCC = SetCC.getOperand(0);
21921 switch (SetCC.getOpcode()) {
21922 case X86ISD::SETCC_CARRY:
21923 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21924 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21925 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21926 // truncated to i1 using 'and'.
21927 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21929 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21930 "Invalid use of SETCC_CARRY!");
21932 case X86ISD::SETCC:
21933 // Set the condition code or opposite one if necessary.
21934 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21935 if (needOppositeCond)
21936 CC = X86::GetOppositeBranchCondition(CC);
21937 return SetCC.getOperand(1);
21938 case X86ISD::CMOV: {
21939 // Check whether false/true value has canonical one, i.e. 0 or 1.
21940 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21941 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21942 // Quit if true value is not a constant.
21945 // Quit if false value is not a constant.
21947 SDValue Op = SetCC.getOperand(0);
21948 // Skip 'zext' or 'trunc' node.
21949 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21950 Op.getOpcode() == ISD::TRUNCATE)
21951 Op = Op.getOperand(0);
21952 // A special case for rdrand/rdseed, where 0 is set if false cond is
21954 if ((Op.getOpcode() != X86ISD::RDRAND &&
21955 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21958 // Quit if false value is not the constant 0 or 1.
21959 bool FValIsFalse = true;
21960 if (FVal && FVal->getZExtValue() != 0) {
21961 if (FVal->getZExtValue() != 1)
21963 // If FVal is 1, opposite cond is needed.
21964 needOppositeCond = !needOppositeCond;
21965 FValIsFalse = false;
21967 // Quit if TVal is not the constant opposite of FVal.
21968 if (FValIsFalse && TVal->getZExtValue() != 1)
21970 if (!FValIsFalse && TVal->getZExtValue() != 0)
21972 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21973 if (needOppositeCond)
21974 CC = X86::GetOppositeBranchCondition(CC);
21975 return SetCC.getOperand(3);
21982 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21984 /// (X86or (X86setcc) (X86setcc))
21985 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21986 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21987 X86::CondCode &CC1, SDValue &Flags,
21989 if (Cond->getOpcode() == X86ISD::CMP) {
21990 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21991 if (!CondOp1C || !CondOp1C->isNullValue())
21994 Cond = Cond->getOperand(0);
21999 SDValue SetCC0, SetCC1;
22000 switch (Cond->getOpcode()) {
22001 default: return false;
22008 SetCC0 = Cond->getOperand(0);
22009 SetCC1 = Cond->getOperand(1);
22013 // Make sure we have SETCC nodes, using the same flags value.
22014 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22015 SetCC1.getOpcode() != X86ISD::SETCC ||
22016 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22019 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22020 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22021 Flags = SetCC0->getOperand(1);
22025 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22026 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22027 TargetLowering::DAGCombinerInfo &DCI,
22028 const X86Subtarget *Subtarget) {
22031 // If the flag operand isn't dead, don't touch this CMOV.
22032 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22035 SDValue FalseOp = N->getOperand(0);
22036 SDValue TrueOp = N->getOperand(1);
22037 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22038 SDValue Cond = N->getOperand(3);
22040 if (CC == X86::COND_E || CC == X86::COND_NE) {
22041 switch (Cond.getOpcode()) {
22045 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22046 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22047 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22053 Flags = checkBoolTestSetCCCombine(Cond, CC);
22054 if (Flags.getNode() &&
22055 // Extra check as FCMOV only supports a subset of X86 cond.
22056 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22057 SDValue Ops[] = { FalseOp, TrueOp,
22058 DAG.getConstant(CC, DL, MVT::i8), Flags };
22059 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22062 // If this is a select between two integer constants, try to do some
22063 // optimizations. Note that the operands are ordered the opposite of SELECT
22065 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22066 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22067 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22068 // larger than FalseC (the false value).
22069 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22070 CC = X86::GetOppositeBranchCondition(CC);
22071 std::swap(TrueC, FalseC);
22072 std::swap(TrueOp, FalseOp);
22075 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22076 // This is efficient for any integer data type (including i8/i16) and
22078 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22079 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22080 DAG.getConstant(CC, DL, MVT::i8), Cond);
22082 // Zero extend the condition if needed.
22083 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22085 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22086 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22087 DAG.getConstant(ShAmt, DL, MVT::i8));
22088 if (N->getNumValues() == 2) // Dead flag value?
22089 return DCI.CombineTo(N, Cond, SDValue());
22093 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22094 // for any integer data type, including i8/i16.
22095 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22096 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22097 DAG.getConstant(CC, DL, MVT::i8), Cond);
22099 // Zero extend the condition if needed.
22100 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22101 FalseC->getValueType(0), Cond);
22102 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22103 SDValue(FalseC, 0));
22105 if (N->getNumValues() == 2) // Dead flag value?
22106 return DCI.CombineTo(N, Cond, SDValue());
22110 // Optimize cases that will turn into an LEA instruction. This requires
22111 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22112 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22113 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22114 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22116 bool isFastMultiplier = false;
22118 switch ((unsigned char)Diff) {
22120 case 1: // result = add base, cond
22121 case 2: // result = lea base( , cond*2)
22122 case 3: // result = lea base(cond, cond*2)
22123 case 4: // result = lea base( , cond*4)
22124 case 5: // result = lea base(cond, cond*4)
22125 case 8: // result = lea base( , cond*8)
22126 case 9: // result = lea base(cond, cond*8)
22127 isFastMultiplier = true;
22132 if (isFastMultiplier) {
22133 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22134 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22135 DAG.getConstant(CC, DL, MVT::i8), Cond);
22136 // Zero extend the condition if needed.
22137 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22139 // Scale the condition by the difference.
22141 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22142 DAG.getConstant(Diff, DL, Cond.getValueType()));
22144 // Add the base if non-zero.
22145 if (FalseC->getAPIntValue() != 0)
22146 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22147 SDValue(FalseC, 0));
22148 if (N->getNumValues() == 2) // Dead flag value?
22149 return DCI.CombineTo(N, Cond, SDValue());
22156 // Handle these cases:
22157 // (select (x != c), e, c) -> select (x != c), e, x),
22158 // (select (x == c), c, e) -> select (x == c), x, e)
22159 // where the c is an integer constant, and the "select" is the combination
22160 // of CMOV and CMP.
22162 // The rationale for this change is that the conditional-move from a constant
22163 // needs two instructions, however, conditional-move from a register needs
22164 // only one instruction.
22166 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22167 // some instruction-combining opportunities. This opt needs to be
22168 // postponed as late as possible.
22170 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22171 // the DCI.xxxx conditions are provided to postpone the optimization as
22172 // late as possible.
22174 ConstantSDNode *CmpAgainst = nullptr;
22175 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22176 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22177 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22179 if (CC == X86::COND_NE &&
22180 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22181 CC = X86::GetOppositeBranchCondition(CC);
22182 std::swap(TrueOp, FalseOp);
22185 if (CC == X86::COND_E &&
22186 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22187 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22188 DAG.getConstant(CC, DL, MVT::i8), Cond };
22189 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22194 // Fold and/or of setcc's to double CMOV:
22195 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22196 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22198 // This combine lets us generate:
22199 // cmovcc1 (jcc1 if we don't have CMOV)
22205 // cmovne (jne if we don't have CMOV)
22206 // When we can't use the CMOV instruction, it might increase branch
22208 // When we can use CMOV, or when there is no mispredict, this improves
22209 // throughput and reduces register pressure.
22211 if (CC == X86::COND_NE) {
22213 X86::CondCode CC0, CC1;
22215 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22217 std::swap(FalseOp, TrueOp);
22218 CC0 = X86::GetOppositeBranchCondition(CC0);
22219 CC1 = X86::GetOppositeBranchCondition(CC1);
22222 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22224 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22225 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22226 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22227 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22235 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22236 const X86Subtarget *Subtarget) {
22237 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22239 default: return SDValue();
22240 // SSE/AVX/AVX2 blend intrinsics.
22241 case Intrinsic::x86_avx2_pblendvb:
22242 // Don't try to simplify this intrinsic if we don't have AVX2.
22243 if (!Subtarget->hasAVX2())
22246 case Intrinsic::x86_avx_blendv_pd_256:
22247 case Intrinsic::x86_avx_blendv_ps_256:
22248 // Don't try to simplify this intrinsic if we don't have AVX.
22249 if (!Subtarget->hasAVX())
22252 case Intrinsic::x86_sse41_blendvps:
22253 case Intrinsic::x86_sse41_blendvpd:
22254 case Intrinsic::x86_sse41_pblendvb: {
22255 SDValue Op0 = N->getOperand(1);
22256 SDValue Op1 = N->getOperand(2);
22257 SDValue Mask = N->getOperand(3);
22259 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22260 if (!Subtarget->hasSSE41())
22263 // fold (blend A, A, Mask) -> A
22266 // fold (blend A, B, allZeros) -> A
22267 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22269 // fold (blend A, B, allOnes) -> B
22270 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22273 // Simplify the case where the mask is a constant i32 value.
22274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22275 if (C->isNullValue())
22277 if (C->isAllOnesValue())
22284 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22285 case Intrinsic::x86_sse2_psrai_w:
22286 case Intrinsic::x86_sse2_psrai_d:
22287 case Intrinsic::x86_avx2_psrai_w:
22288 case Intrinsic::x86_avx2_psrai_d:
22289 case Intrinsic::x86_sse2_psra_w:
22290 case Intrinsic::x86_sse2_psra_d:
22291 case Intrinsic::x86_avx2_psra_w:
22292 case Intrinsic::x86_avx2_psra_d: {
22293 SDValue Op0 = N->getOperand(1);
22294 SDValue Op1 = N->getOperand(2);
22295 EVT VT = Op0.getValueType();
22296 assert(VT.isVector() && "Expected a vector type!");
22298 if (isa<BuildVectorSDNode>(Op1))
22299 Op1 = Op1.getOperand(0);
22301 if (!isa<ConstantSDNode>(Op1))
22304 EVT SVT = VT.getVectorElementType();
22305 unsigned SVTBits = SVT.getSizeInBits();
22307 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22308 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22309 uint64_t ShAmt = C.getZExtValue();
22311 // Don't try to convert this shift into a ISD::SRA if the shift
22312 // count is bigger than or equal to the element size.
22313 if (ShAmt >= SVTBits)
22316 // Trivial case: if the shift count is zero, then fold this
22317 // into the first operand.
22321 // Replace this packed shift intrinsic with a target independent
22324 SDValue Splat = DAG.getConstant(C, DL, VT);
22325 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22330 /// PerformMulCombine - Optimize a single multiply with constant into two
22331 /// in order to implement it with two cheaper instructions, e.g.
22332 /// LEA + SHL, LEA + LEA.
22333 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22334 TargetLowering::DAGCombinerInfo &DCI) {
22335 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22338 EVT VT = N->getValueType(0);
22339 if (VT != MVT::i64 && VT != MVT::i32)
22342 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22345 uint64_t MulAmt = C->getZExtValue();
22346 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22349 uint64_t MulAmt1 = 0;
22350 uint64_t MulAmt2 = 0;
22351 if ((MulAmt % 9) == 0) {
22353 MulAmt2 = MulAmt / 9;
22354 } else if ((MulAmt % 5) == 0) {
22356 MulAmt2 = MulAmt / 5;
22357 } else if ((MulAmt % 3) == 0) {
22359 MulAmt2 = MulAmt / 3;
22362 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22365 if (isPowerOf2_64(MulAmt2) &&
22366 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22367 // If second multiplifer is pow2, issue it first. We want the multiply by
22368 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22370 std::swap(MulAmt1, MulAmt2);
22373 if (isPowerOf2_64(MulAmt1))
22374 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22375 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22377 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22378 DAG.getConstant(MulAmt1, DL, VT));
22380 if (isPowerOf2_64(MulAmt2))
22381 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22382 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22384 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22385 DAG.getConstant(MulAmt2, DL, VT));
22387 // Do not add new nodes to DAG combiner worklist.
22388 DCI.CombineTo(N, NewMul, false);
22393 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22394 SDValue N0 = N->getOperand(0);
22395 SDValue N1 = N->getOperand(1);
22396 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22397 EVT VT = N0.getValueType();
22399 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22400 // since the result of setcc_c is all zero's or all ones.
22401 if (VT.isInteger() && !VT.isVector() &&
22402 N1C && N0.getOpcode() == ISD::AND &&
22403 N0.getOperand(1).getOpcode() == ISD::Constant) {
22404 SDValue N00 = N0.getOperand(0);
22405 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22406 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22407 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22408 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22409 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22410 APInt ShAmt = N1C->getAPIntValue();
22411 Mask = Mask.shl(ShAmt);
22414 return DAG.getNode(ISD::AND, DL, VT,
22415 N00, DAG.getConstant(Mask, DL, VT));
22420 // Hardware support for vector shifts is sparse which makes us scalarize the
22421 // vector operations in many cases. Also, on sandybridge ADD is faster than
22423 // (shl V, 1) -> add V,V
22424 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22425 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22426 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22427 // We shift all of the values by one. In many cases we do not have
22428 // hardware support for this operation. This is better expressed as an ADD
22430 if (N1SplatC->getZExtValue() == 1)
22431 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22437 /// \brief Returns a vector of 0s if the node in input is a vector logical
22438 /// shift by a constant amount which is known to be bigger than or equal
22439 /// to the vector element size in bits.
22440 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22441 const X86Subtarget *Subtarget) {
22442 EVT VT = N->getValueType(0);
22444 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22445 (!Subtarget->hasInt256() ||
22446 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22449 SDValue Amt = N->getOperand(1);
22451 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22452 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22453 APInt ShiftAmt = AmtSplat->getAPIntValue();
22454 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22456 // SSE2/AVX2 logical shifts always return a vector of 0s
22457 // if the shift amount is bigger than or equal to
22458 // the element size. The constant shift amount will be
22459 // encoded as a 8-bit immediate.
22460 if (ShiftAmt.trunc(8).uge(MaxAmount))
22461 return getZeroVector(VT, Subtarget, DAG, DL);
22467 /// PerformShiftCombine - Combine shifts.
22468 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22469 TargetLowering::DAGCombinerInfo &DCI,
22470 const X86Subtarget *Subtarget) {
22471 if (N->getOpcode() == ISD::SHL) {
22472 SDValue V = PerformSHLCombine(N, DAG);
22473 if (V.getNode()) return V;
22476 if (N->getOpcode() != ISD::SRA) {
22477 // Try to fold this logical shift into a zero vector.
22478 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22479 if (V.getNode()) return V;
22485 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22486 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22487 // and friends. Likewise for OR -> CMPNEQSS.
22488 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22489 TargetLowering::DAGCombinerInfo &DCI,
22490 const X86Subtarget *Subtarget) {
22493 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22494 // we're requiring SSE2 for both.
22495 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22496 SDValue N0 = N->getOperand(0);
22497 SDValue N1 = N->getOperand(1);
22498 SDValue CMP0 = N0->getOperand(1);
22499 SDValue CMP1 = N1->getOperand(1);
22502 // The SETCCs should both refer to the same CMP.
22503 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22506 SDValue CMP00 = CMP0->getOperand(0);
22507 SDValue CMP01 = CMP0->getOperand(1);
22508 EVT VT = CMP00.getValueType();
22510 if (VT == MVT::f32 || VT == MVT::f64) {
22511 bool ExpectingFlags = false;
22512 // Check for any users that want flags:
22513 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22514 !ExpectingFlags && UI != UE; ++UI)
22515 switch (UI->getOpcode()) {
22520 ExpectingFlags = true;
22522 case ISD::CopyToReg:
22523 case ISD::SIGN_EXTEND:
22524 case ISD::ZERO_EXTEND:
22525 case ISD::ANY_EXTEND:
22529 if (!ExpectingFlags) {
22530 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22531 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22533 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22534 X86::CondCode tmp = cc0;
22539 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22540 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22541 // FIXME: need symbolic constants for these magic numbers.
22542 // See X86ATTInstPrinter.cpp:printSSECC().
22543 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22544 if (Subtarget->hasAVX512()) {
22545 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22547 DAG.getConstant(x86cc, DL, MVT::i8));
22548 if (N->getValueType(0) != MVT::i1)
22549 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22553 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22554 CMP00.getValueType(), CMP00, CMP01,
22555 DAG.getConstant(x86cc, DL,
22558 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22559 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22561 if (is64BitFP && !Subtarget->is64Bit()) {
22562 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22563 // 64-bit integer, since that's not a legal type. Since
22564 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22565 // bits, but can do this little dance to extract the lowest 32 bits
22566 // and work with those going forward.
22567 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22569 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22571 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22572 Vector32, DAG.getIntPtrConstant(0, DL));
22576 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
22578 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22579 DAG.getConstant(1, DL, IntVT));
22580 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22582 return OneBitOfTruth;
22590 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22591 /// so it can be folded inside ANDNP.
22592 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22593 EVT VT = N->getValueType(0);
22595 // Match direct AllOnes for 128 and 256-bit vectors
22596 if (ISD::isBuildVectorAllOnes(N))
22599 // Look through a bit convert.
22600 if (N->getOpcode() == ISD::BITCAST)
22601 N = N->getOperand(0).getNode();
22603 // Sometimes the operand may come from a insert_subvector building a 256-bit
22605 if (VT.is256BitVector() &&
22606 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22607 SDValue V1 = N->getOperand(0);
22608 SDValue V2 = N->getOperand(1);
22610 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22611 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22612 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22613 ISD::isBuildVectorAllOnes(V2.getNode()))
22620 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22621 // register. In most cases we actually compare or select YMM-sized registers
22622 // and mixing the two types creates horrible code. This method optimizes
22623 // some of the transition sequences.
22624 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22625 TargetLowering::DAGCombinerInfo &DCI,
22626 const X86Subtarget *Subtarget) {
22627 EVT VT = N->getValueType(0);
22628 if (!VT.is256BitVector())
22631 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22632 N->getOpcode() == ISD::ZERO_EXTEND ||
22633 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22635 SDValue Narrow = N->getOperand(0);
22636 EVT NarrowVT = Narrow->getValueType(0);
22637 if (!NarrowVT.is128BitVector())
22640 if (Narrow->getOpcode() != ISD::XOR &&
22641 Narrow->getOpcode() != ISD::AND &&
22642 Narrow->getOpcode() != ISD::OR)
22645 SDValue N0 = Narrow->getOperand(0);
22646 SDValue N1 = Narrow->getOperand(1);
22649 // The Left side has to be a trunc.
22650 if (N0.getOpcode() != ISD::TRUNCATE)
22653 // The type of the truncated inputs.
22654 EVT WideVT = N0->getOperand(0)->getValueType(0);
22658 // The right side has to be a 'trunc' or a constant vector.
22659 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22660 ConstantSDNode *RHSConstSplat = nullptr;
22661 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22662 RHSConstSplat = RHSBV->getConstantSplatNode();
22663 if (!RHSTrunc && !RHSConstSplat)
22666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22668 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22671 // Set N0 and N1 to hold the inputs to the new wide operation.
22672 N0 = N0->getOperand(0);
22673 if (RHSConstSplat) {
22674 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22675 SDValue(RHSConstSplat, 0));
22676 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22677 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22678 } else if (RHSTrunc) {
22679 N1 = N1->getOperand(0);
22682 // Generate the wide operation.
22683 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22684 unsigned Opcode = N->getOpcode();
22686 case ISD::ANY_EXTEND:
22688 case ISD::ZERO_EXTEND: {
22689 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22690 APInt Mask = APInt::getAllOnesValue(InBits);
22691 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22692 return DAG.getNode(ISD::AND, DL, VT,
22693 Op, DAG.getConstant(Mask, DL, VT));
22695 case ISD::SIGN_EXTEND:
22696 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22697 Op, DAG.getValueType(NarrowVT));
22699 llvm_unreachable("Unexpected opcode");
22703 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22704 TargetLowering::DAGCombinerInfo &DCI,
22705 const X86Subtarget *Subtarget) {
22706 SDValue N0 = N->getOperand(0);
22707 SDValue N1 = N->getOperand(1);
22710 // A vector zext_in_reg may be represented as a shuffle,
22711 // feeding into a bitcast (this represents anyext) feeding into
22712 // an and with a mask.
22713 // We'd like to try to combine that into a shuffle with zero
22714 // plus a bitcast, removing the and.
22715 if (N0.getOpcode() != ISD::BITCAST ||
22716 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22719 // The other side of the AND should be a splat of 2^C, where C
22720 // is the number of bits in the source type.
22721 if (N1.getOpcode() == ISD::BITCAST)
22722 N1 = N1.getOperand(0);
22723 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22725 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22727 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22728 EVT SrcType = Shuffle->getValueType(0);
22730 // We expect a single-source shuffle
22731 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22734 unsigned SrcSize = SrcType.getScalarSizeInBits();
22736 APInt SplatValue, SplatUndef;
22737 unsigned SplatBitSize;
22739 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22740 SplatBitSize, HasAnyUndefs))
22743 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22744 // Make sure the splat matches the mask we expect
22745 if (SplatBitSize > ResSize ||
22746 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22749 // Make sure the input and output size make sense
22750 if (SrcSize >= ResSize || ResSize % SrcSize)
22753 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22754 // The number of u's between each two values depends on the ratio between
22755 // the source and dest type.
22756 unsigned ZextRatio = ResSize / SrcSize;
22757 bool IsZext = true;
22758 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22759 if (i % ZextRatio) {
22760 if (Shuffle->getMaskElt(i) > 0) {
22766 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22767 // Expected element number
22777 // Ok, perform the transformation - replace the shuffle with
22778 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22779 // (instead of undef) where the k elements come from the zero vector.
22780 SmallVector<int, 8> Mask;
22781 unsigned NumElems = SrcType.getVectorNumElements();
22782 for (unsigned i = 0; i < NumElems; ++i)
22784 Mask.push_back(NumElems);
22786 Mask.push_back(i / ZextRatio);
22788 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22789 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
22790 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22793 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22794 TargetLowering::DAGCombinerInfo &DCI,
22795 const X86Subtarget *Subtarget) {
22796 if (DCI.isBeforeLegalizeOps())
22799 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22802 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22805 EVT VT = N->getValueType(0);
22806 SDValue N0 = N->getOperand(0);
22807 SDValue N1 = N->getOperand(1);
22810 // Create BEXTR instructions
22811 // BEXTR is ((X >> imm) & (2**size-1))
22812 if (VT == MVT::i32 || VT == MVT::i64) {
22813 // Check for BEXTR.
22814 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22815 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22816 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22817 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22818 if (MaskNode && ShiftNode) {
22819 uint64_t Mask = MaskNode->getZExtValue();
22820 uint64_t Shift = ShiftNode->getZExtValue();
22821 if (isMask_64(Mask)) {
22822 uint64_t MaskSize = countPopulation(Mask);
22823 if (Shift + MaskSize <= VT.getSizeInBits())
22824 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22825 DAG.getConstant(Shift | (MaskSize << 8), DL,
22834 // Want to form ANDNP nodes:
22835 // 1) In the hopes of then easily combining them with OR and AND nodes
22836 // to form PBLEND/PSIGN.
22837 // 2) To match ANDN packed intrinsics
22838 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22841 // Check LHS for vnot
22842 if (N0.getOpcode() == ISD::XOR &&
22843 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22844 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22845 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22847 // Check RHS for vnot
22848 if (N1.getOpcode() == ISD::XOR &&
22849 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22850 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22851 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22856 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22857 TargetLowering::DAGCombinerInfo &DCI,
22858 const X86Subtarget *Subtarget) {
22859 if (DCI.isBeforeLegalizeOps())
22862 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22866 SDValue N0 = N->getOperand(0);
22867 SDValue N1 = N->getOperand(1);
22868 EVT VT = N->getValueType(0);
22870 // look for psign/blend
22871 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22872 if (!Subtarget->hasSSSE3() ||
22873 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22876 // Canonicalize pandn to RHS
22877 if (N0.getOpcode() == X86ISD::ANDNP)
22879 // or (and (m, y), (pandn m, x))
22880 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22881 SDValue Mask = N1.getOperand(0);
22882 SDValue X = N1.getOperand(1);
22884 if (N0.getOperand(0) == Mask)
22885 Y = N0.getOperand(1);
22886 if (N0.getOperand(1) == Mask)
22887 Y = N0.getOperand(0);
22889 // Check to see if the mask appeared in both the AND and ANDNP and
22893 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22894 // Look through mask bitcast.
22895 if (Mask.getOpcode() == ISD::BITCAST)
22896 Mask = Mask.getOperand(0);
22897 if (X.getOpcode() == ISD::BITCAST)
22898 X = X.getOperand(0);
22899 if (Y.getOpcode() == ISD::BITCAST)
22900 Y = Y.getOperand(0);
22902 EVT MaskVT = Mask.getValueType();
22904 // Validate that the Mask operand is a vector sra node.
22905 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22906 // there is no psrai.b
22907 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22908 unsigned SraAmt = ~0;
22909 if (Mask.getOpcode() == ISD::SRA) {
22910 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22911 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22912 SraAmt = AmtConst->getZExtValue();
22913 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22914 SDValue SraC = Mask.getOperand(1);
22915 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22917 if ((SraAmt + 1) != EltBits)
22922 // Now we know we at least have a plendvb with the mask val. See if
22923 // we can form a psignb/w/d.
22924 // psign = x.type == y.type == mask.type && y = sub(0, x);
22925 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22926 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22927 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22928 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22929 "Unsupported VT for PSIGN");
22930 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22931 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22933 // PBLENDVB only available on SSE 4.1
22934 if (!Subtarget->hasSSE41())
22937 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22939 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22940 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22941 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22942 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22943 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22947 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22950 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22951 MachineFunction &MF = DAG.getMachineFunction();
22953 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22955 // SHLD/SHRD instructions have lower register pressure, but on some
22956 // platforms they have higher latency than the equivalent
22957 // series of shifts/or that would otherwise be generated.
22958 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22959 // have higher latencies and we are not optimizing for size.
22960 if (!OptForSize && Subtarget->isSHLDSlow())
22963 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22965 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22967 if (!N0.hasOneUse() || !N1.hasOneUse())
22970 SDValue ShAmt0 = N0.getOperand(1);
22971 if (ShAmt0.getValueType() != MVT::i8)
22973 SDValue ShAmt1 = N1.getOperand(1);
22974 if (ShAmt1.getValueType() != MVT::i8)
22976 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22977 ShAmt0 = ShAmt0.getOperand(0);
22978 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22979 ShAmt1 = ShAmt1.getOperand(0);
22982 unsigned Opc = X86ISD::SHLD;
22983 SDValue Op0 = N0.getOperand(0);
22984 SDValue Op1 = N1.getOperand(0);
22985 if (ShAmt0.getOpcode() == ISD::SUB) {
22986 Opc = X86ISD::SHRD;
22987 std::swap(Op0, Op1);
22988 std::swap(ShAmt0, ShAmt1);
22991 unsigned Bits = VT.getSizeInBits();
22992 if (ShAmt1.getOpcode() == ISD::SUB) {
22993 SDValue Sum = ShAmt1.getOperand(0);
22994 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22995 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22996 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22997 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22998 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22999 return DAG.getNode(Opc, DL, VT,
23001 DAG.getNode(ISD::TRUNCATE, DL,
23004 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23005 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23007 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23008 return DAG.getNode(Opc, DL, VT,
23009 N0.getOperand(0), N1.getOperand(0),
23010 DAG.getNode(ISD::TRUNCATE, DL,
23017 // Generate NEG and CMOV for integer abs.
23018 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23019 EVT VT = N->getValueType(0);
23021 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23022 // 8-bit integer abs to NEG and CMOV.
23023 if (VT.isInteger() && VT.getSizeInBits() == 8)
23026 SDValue N0 = N->getOperand(0);
23027 SDValue N1 = N->getOperand(1);
23030 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23031 // and change it to SUB and CMOV.
23032 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23033 N0.getOpcode() == ISD::ADD &&
23034 N0.getOperand(1) == N1 &&
23035 N1.getOpcode() == ISD::SRA &&
23036 N1.getOperand(0) == N0.getOperand(0))
23037 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23038 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23039 // Generate SUB & CMOV.
23040 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23041 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23043 SDValue Ops[] = { N0.getOperand(0), Neg,
23044 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23045 SDValue(Neg.getNode(), 1) };
23046 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23051 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23052 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23053 TargetLowering::DAGCombinerInfo &DCI,
23054 const X86Subtarget *Subtarget) {
23055 if (DCI.isBeforeLegalizeOps())
23058 if (Subtarget->hasCMov()) {
23059 SDValue RV = performIntegerAbsCombine(N, DAG);
23067 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23068 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23069 TargetLowering::DAGCombinerInfo &DCI,
23070 const X86Subtarget *Subtarget) {
23071 LoadSDNode *Ld = cast<LoadSDNode>(N);
23072 EVT RegVT = Ld->getValueType(0);
23073 EVT MemVT = Ld->getMemoryVT();
23075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23077 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23078 // into two 16-byte operations.
23079 ISD::LoadExtType Ext = Ld->getExtensionType();
23080 unsigned Alignment = Ld->getAlignment();
23081 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23082 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23083 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23084 unsigned NumElems = RegVT.getVectorNumElements();
23088 SDValue Ptr = Ld->getBasePtr();
23089 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23091 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23093 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23094 Ld->getPointerInfo(), Ld->isVolatile(),
23095 Ld->isNonTemporal(), Ld->isInvariant(),
23097 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23098 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23099 Ld->getPointerInfo(), Ld->isVolatile(),
23100 Ld->isNonTemporal(), Ld->isInvariant(),
23101 std::min(16U, Alignment));
23102 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23104 Load2.getValue(1));
23106 SDValue NewVec = DAG.getUNDEF(RegVT);
23107 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23108 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23109 return DCI.CombineTo(N, NewVec, TF, true);
23115 /// PerformMLOADCombine - Resolve extending loads
23116 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23117 TargetLowering::DAGCombinerInfo &DCI,
23118 const X86Subtarget *Subtarget) {
23119 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23120 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23123 EVT VT = Mld->getValueType(0);
23124 unsigned NumElems = VT.getVectorNumElements();
23125 EVT LdVT = Mld->getMemoryVT();
23128 assert(LdVT != VT && "Cannot extend to the same type");
23129 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23130 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23131 // From, To sizes and ElemCount must be pow of two
23132 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23133 "Unexpected size for extending masked load");
23135 unsigned SizeRatio = ToSz / FromSz;
23136 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23138 // Create a type on which we perform the shuffle
23139 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23140 LdVT.getScalarType(), NumElems*SizeRatio);
23141 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23143 // Convert Src0 value
23144 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
23145 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23146 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23147 for (unsigned i = 0; i != NumElems; ++i)
23148 ShuffleVec[i] = i * SizeRatio;
23150 // Can't shuffle using an illegal type.
23151 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23152 && "WideVecVT should be legal");
23153 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23154 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23156 // Prepare the new mask
23158 SDValue Mask = Mld->getMask();
23159 if (Mask.getValueType() == VT) {
23160 // Mask and original value have the same type
23161 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23162 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23163 for (unsigned i = 0; i != NumElems; ++i)
23164 ShuffleVec[i] = i * SizeRatio;
23165 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23166 ShuffleVec[i] = NumElems*SizeRatio;
23167 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23168 DAG.getConstant(0, dl, WideVecVT),
23172 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23173 unsigned WidenNumElts = NumElems*SizeRatio;
23174 unsigned MaskNumElts = VT.getVectorNumElements();
23175 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23178 unsigned NumConcat = WidenNumElts / MaskNumElts;
23179 SmallVector<SDValue, 16> Ops(NumConcat);
23180 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23182 for (unsigned i = 1; i != NumConcat; ++i)
23185 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23188 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23189 Mld->getBasePtr(), NewMask, WideSrc0,
23190 Mld->getMemoryVT(), Mld->getMemOperand(),
23192 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23193 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23196 /// PerformMSTORECombine - Resolve truncating stores
23197 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23198 const X86Subtarget *Subtarget) {
23199 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23200 if (!Mst->isTruncatingStore())
23203 EVT VT = Mst->getValue().getValueType();
23204 unsigned NumElems = VT.getVectorNumElements();
23205 EVT StVT = Mst->getMemoryVT();
23208 assert(StVT != VT && "Cannot truncate to the same type");
23209 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23210 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23212 // From, To sizes and ElemCount must be pow of two
23213 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23214 "Unexpected size for truncating masked store");
23215 // We are going to use the original vector elt for storing.
23216 // Accumulated smaller vector elements must be a multiple of the store size.
23217 assert (((NumElems * FromSz) % ToSz) == 0 &&
23218 "Unexpected ratio for truncating masked store");
23220 unsigned SizeRatio = FromSz / ToSz;
23221 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23223 // Create a type on which we perform the shuffle
23224 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23225 StVT.getScalarType(), NumElems*SizeRatio);
23227 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23229 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
23230 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23231 for (unsigned i = 0; i != NumElems; ++i)
23232 ShuffleVec[i] = i * SizeRatio;
23234 // Can't shuffle using an illegal type.
23235 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23236 && "WideVecVT should be legal");
23238 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23239 DAG.getUNDEF(WideVecVT),
23243 SDValue Mask = Mst->getMask();
23244 if (Mask.getValueType() == VT) {
23245 // Mask and original value have the same type
23246 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23247 for (unsigned i = 0; i != NumElems; ++i)
23248 ShuffleVec[i] = i * SizeRatio;
23249 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23250 ShuffleVec[i] = NumElems*SizeRatio;
23251 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23252 DAG.getConstant(0, dl, WideVecVT),
23256 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23257 unsigned WidenNumElts = NumElems*SizeRatio;
23258 unsigned MaskNumElts = VT.getVectorNumElements();
23259 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23262 unsigned NumConcat = WidenNumElts / MaskNumElts;
23263 SmallVector<SDValue, 16> Ops(NumConcat);
23264 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23266 for (unsigned i = 1; i != NumConcat; ++i)
23269 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23272 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23273 NewMask, StVT, Mst->getMemOperand(), false);
23275 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23276 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23277 const X86Subtarget *Subtarget) {
23278 StoreSDNode *St = cast<StoreSDNode>(N);
23279 EVT VT = St->getValue().getValueType();
23280 EVT StVT = St->getMemoryVT();
23282 SDValue StoredVal = St->getOperand(1);
23283 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23285 // If we are saving a concatenation of two XMM registers and 32-byte stores
23286 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23287 unsigned Alignment = St->getAlignment();
23288 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23289 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23290 StVT == VT && !IsAligned) {
23291 unsigned NumElems = VT.getVectorNumElements();
23295 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23296 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23298 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23299 SDValue Ptr0 = St->getBasePtr();
23300 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23302 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23303 St->getPointerInfo(), St->isVolatile(),
23304 St->isNonTemporal(), Alignment);
23305 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23306 St->getPointerInfo(), St->isVolatile(),
23307 St->isNonTemporal(),
23308 std::min(16U, Alignment));
23309 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23312 // Optimize trunc store (of multiple scalars) to shuffle and store.
23313 // First, pack all of the elements in one place. Next, store to memory
23314 // in fewer chunks.
23315 if (St->isTruncatingStore() && VT.isVector()) {
23316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23317 unsigned NumElems = VT.getVectorNumElements();
23318 assert(StVT != VT && "Cannot truncate to the same type");
23319 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23320 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23322 // From, To sizes and ElemCount must be pow of two
23323 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23324 // We are going to use the original vector elt for storing.
23325 // Accumulated smaller vector elements must be a multiple of the store size.
23326 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23328 unsigned SizeRatio = FromSz / ToSz;
23330 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23332 // Create a type on which we perform the shuffle
23333 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23334 StVT.getScalarType(), NumElems*SizeRatio);
23336 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23338 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23339 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23340 for (unsigned i = 0; i != NumElems; ++i)
23341 ShuffleVec[i] = i * SizeRatio;
23343 // Can't shuffle using an illegal type.
23344 if (!TLI.isTypeLegal(WideVecVT))
23347 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23348 DAG.getUNDEF(WideVecVT),
23350 // At this point all of the data is stored at the bottom of the
23351 // register. We now need to save it to mem.
23353 // Find the largest store unit
23354 MVT StoreType = MVT::i8;
23355 for (MVT Tp : MVT::integer_valuetypes()) {
23356 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23360 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23361 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23362 (64 <= NumElems * ToSz))
23363 StoreType = MVT::f64;
23365 // Bitcast the original vector into a vector of store-size units
23366 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23367 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23368 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23369 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23370 SmallVector<SDValue, 8> Chains;
23371 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23372 TLI.getPointerTy());
23373 SDValue Ptr = St->getBasePtr();
23375 // Perform one or more big stores into memory.
23376 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23377 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23378 StoreType, ShuffWide,
23379 DAG.getIntPtrConstant(i, dl));
23380 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23381 St->getPointerInfo(), St->isVolatile(),
23382 St->isNonTemporal(), St->getAlignment());
23383 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23384 Chains.push_back(Ch);
23387 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23390 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23391 // the FP state in cases where an emms may be missing.
23392 // A preferable solution to the general problem is to figure out the right
23393 // places to insert EMMS. This qualifies as a quick hack.
23395 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23396 if (VT.getSizeInBits() != 64)
23399 const Function *F = DAG.getMachineFunction().getFunction();
23400 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23402 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23403 if ((VT.isVector() ||
23404 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23405 isa<LoadSDNode>(St->getValue()) &&
23406 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23407 St->getChain().hasOneUse() && !St->isVolatile()) {
23408 SDNode* LdVal = St->getValue().getNode();
23409 LoadSDNode *Ld = nullptr;
23410 int TokenFactorIndex = -1;
23411 SmallVector<SDValue, 8> Ops;
23412 SDNode* ChainVal = St->getChain().getNode();
23413 // Must be a store of a load. We currently handle two cases: the load
23414 // is a direct child, and it's under an intervening TokenFactor. It is
23415 // possible to dig deeper under nested TokenFactors.
23416 if (ChainVal == LdVal)
23417 Ld = cast<LoadSDNode>(St->getChain());
23418 else if (St->getValue().hasOneUse() &&
23419 ChainVal->getOpcode() == ISD::TokenFactor) {
23420 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23421 if (ChainVal->getOperand(i).getNode() == LdVal) {
23422 TokenFactorIndex = i;
23423 Ld = cast<LoadSDNode>(St->getValue());
23425 Ops.push_back(ChainVal->getOperand(i));
23429 if (!Ld || !ISD::isNormalLoad(Ld))
23432 // If this is not the MMX case, i.e. we are just turning i64 load/store
23433 // into f64 load/store, avoid the transformation if there are multiple
23434 // uses of the loaded value.
23435 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23440 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23441 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23443 if (Subtarget->is64Bit() || F64IsLegal) {
23444 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23445 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23446 Ld->getPointerInfo(), Ld->isVolatile(),
23447 Ld->isNonTemporal(), Ld->isInvariant(),
23448 Ld->getAlignment());
23449 SDValue NewChain = NewLd.getValue(1);
23450 if (TokenFactorIndex != -1) {
23451 Ops.push_back(NewChain);
23452 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23454 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23455 St->getPointerInfo(),
23456 St->isVolatile(), St->isNonTemporal(),
23457 St->getAlignment());
23460 // Otherwise, lower to two pairs of 32-bit loads / stores.
23461 SDValue LoAddr = Ld->getBasePtr();
23462 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23463 DAG.getConstant(4, LdDL, MVT::i32));
23465 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23466 Ld->getPointerInfo(),
23467 Ld->isVolatile(), Ld->isNonTemporal(),
23468 Ld->isInvariant(), Ld->getAlignment());
23469 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23470 Ld->getPointerInfo().getWithOffset(4),
23471 Ld->isVolatile(), Ld->isNonTemporal(),
23473 MinAlign(Ld->getAlignment(), 4));
23475 SDValue NewChain = LoLd.getValue(1);
23476 if (TokenFactorIndex != -1) {
23477 Ops.push_back(LoLd);
23478 Ops.push_back(HiLd);
23479 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23482 LoAddr = St->getBasePtr();
23483 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23484 DAG.getConstant(4, StDL, MVT::i32));
23486 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23487 St->getPointerInfo(),
23488 St->isVolatile(), St->isNonTemporal(),
23489 St->getAlignment());
23490 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23491 St->getPointerInfo().getWithOffset(4),
23493 St->isNonTemporal(),
23494 MinAlign(St->getAlignment(), 4));
23495 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23498 // This is similar to the above case, but here we handle a scalar 64-bit
23499 // integer store that is extracted from a vector on a 32-bit target.
23500 // If we have SSE2, then we can treat it like a floating-point double
23501 // to get past legalization. The execution dependencies fixup pass will
23502 // choose the optimal machine instruction for the store if this really is
23503 // an integer or v2f32 rather than an f64.
23504 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23505 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23506 SDValue OldExtract = St->getOperand(1);
23507 SDValue ExtOp0 = OldExtract.getOperand(0);
23508 unsigned VecSize = ExtOp0.getValueSizeInBits();
23509 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23510 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
23511 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23512 BitCast, OldExtract.getOperand(1));
23513 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23514 St->getPointerInfo(), St->isVolatile(),
23515 St->isNonTemporal(), St->getAlignment());
23521 /// Return 'true' if this vector operation is "horizontal"
23522 /// and return the operands for the horizontal operation in LHS and RHS. A
23523 /// horizontal operation performs the binary operation on successive elements
23524 /// of its first operand, then on successive elements of its second operand,
23525 /// returning the resulting values in a vector. For example, if
23526 /// A = < float a0, float a1, float a2, float a3 >
23528 /// B = < float b0, float b1, float b2, float b3 >
23529 /// then the result of doing a horizontal operation on A and B is
23530 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23531 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23532 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23533 /// set to A, RHS to B, and the routine returns 'true'.
23534 /// Note that the binary operation should have the property that if one of the
23535 /// operands is UNDEF then the result is UNDEF.
23536 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23537 // Look for the following pattern: if
23538 // A = < float a0, float a1, float a2, float a3 >
23539 // B = < float b0, float b1, float b2, float b3 >
23541 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23542 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23543 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23544 // which is A horizontal-op B.
23546 // At least one of the operands should be a vector shuffle.
23547 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23548 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23551 MVT VT = LHS.getSimpleValueType();
23553 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23554 "Unsupported vector type for horizontal add/sub");
23556 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23557 // operate independently on 128-bit lanes.
23558 unsigned NumElts = VT.getVectorNumElements();
23559 unsigned NumLanes = VT.getSizeInBits()/128;
23560 unsigned NumLaneElts = NumElts / NumLanes;
23561 assert((NumLaneElts % 2 == 0) &&
23562 "Vector type should have an even number of elements in each lane");
23563 unsigned HalfLaneElts = NumLaneElts/2;
23565 // View LHS in the form
23566 // LHS = VECTOR_SHUFFLE A, B, LMask
23567 // If LHS is not a shuffle then pretend it is the shuffle
23568 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23569 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23572 SmallVector<int, 16> LMask(NumElts);
23573 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23574 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23575 A = LHS.getOperand(0);
23576 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23577 B = LHS.getOperand(1);
23578 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23579 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23581 if (LHS.getOpcode() != ISD::UNDEF)
23583 for (unsigned i = 0; i != NumElts; ++i)
23587 // Likewise, view RHS in the form
23588 // RHS = VECTOR_SHUFFLE C, D, RMask
23590 SmallVector<int, 16> RMask(NumElts);
23591 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23592 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23593 C = RHS.getOperand(0);
23594 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23595 D = RHS.getOperand(1);
23596 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23597 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23599 if (RHS.getOpcode() != ISD::UNDEF)
23601 for (unsigned i = 0; i != NumElts; ++i)
23605 // Check that the shuffles are both shuffling the same vectors.
23606 if (!(A == C && B == D) && !(A == D && B == C))
23609 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23610 if (!A.getNode() && !B.getNode())
23613 // If A and B occur in reverse order in RHS, then "swap" them (which means
23614 // rewriting the mask).
23616 ShuffleVectorSDNode::commuteMask(RMask);
23618 // At this point LHS and RHS are equivalent to
23619 // LHS = VECTOR_SHUFFLE A, B, LMask
23620 // RHS = VECTOR_SHUFFLE A, B, RMask
23621 // Check that the masks correspond to performing a horizontal operation.
23622 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23623 for (unsigned i = 0; i != NumLaneElts; ++i) {
23624 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23626 // Ignore any UNDEF components.
23627 if (LIdx < 0 || RIdx < 0 ||
23628 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23629 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23632 // Check that successive elements are being operated on. If not, this is
23633 // not a horizontal operation.
23634 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23635 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23636 if (!(LIdx == Index && RIdx == Index + 1) &&
23637 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23642 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23643 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23647 /// Do target-specific dag combines on floating point adds.
23648 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23649 const X86Subtarget *Subtarget) {
23650 EVT VT = N->getValueType(0);
23651 SDValue LHS = N->getOperand(0);
23652 SDValue RHS = N->getOperand(1);
23654 // Try to synthesize horizontal adds from adds of shuffles.
23655 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23656 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23657 isHorizontalBinOp(LHS, RHS, true))
23658 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23662 /// Do target-specific dag combines on floating point subs.
23663 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23664 const X86Subtarget *Subtarget) {
23665 EVT VT = N->getValueType(0);
23666 SDValue LHS = N->getOperand(0);
23667 SDValue RHS = N->getOperand(1);
23669 // Try to synthesize horizontal subs from subs of shuffles.
23670 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23671 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23672 isHorizontalBinOp(LHS, RHS, false))
23673 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23677 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23678 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23679 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23681 // F[X]OR(0.0, x) -> x
23682 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23683 if (C->getValueAPF().isPosZero())
23684 return N->getOperand(1);
23686 // F[X]OR(x, 0.0) -> x
23687 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23688 if (C->getValueAPF().isPosZero())
23689 return N->getOperand(0);
23693 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23694 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23695 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23697 // Only perform optimizations if UnsafeMath is used.
23698 if (!DAG.getTarget().Options.UnsafeFPMath)
23701 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23702 // into FMINC and FMAXC, which are Commutative operations.
23703 unsigned NewOp = 0;
23704 switch (N->getOpcode()) {
23705 default: llvm_unreachable("unknown opcode");
23706 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23707 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23710 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23711 N->getOperand(0), N->getOperand(1));
23714 /// Do target-specific dag combines on X86ISD::FAND nodes.
23715 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23716 // FAND(0.0, x) -> 0.0
23717 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23718 if (C->getValueAPF().isPosZero())
23719 return N->getOperand(0);
23721 // FAND(x, 0.0) -> 0.0
23722 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23723 if (C->getValueAPF().isPosZero())
23724 return N->getOperand(1);
23729 /// Do target-specific dag combines on X86ISD::FANDN nodes
23730 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23731 // FANDN(0.0, x) -> x
23732 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23733 if (C->getValueAPF().isPosZero())
23734 return N->getOperand(1);
23736 // FANDN(x, 0.0) -> 0.0
23737 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23738 if (C->getValueAPF().isPosZero())
23739 return N->getOperand(1);
23744 static SDValue PerformBTCombine(SDNode *N,
23746 TargetLowering::DAGCombinerInfo &DCI) {
23747 // BT ignores high bits in the bit index operand.
23748 SDValue Op1 = N->getOperand(1);
23749 if (Op1.hasOneUse()) {
23750 unsigned BitWidth = Op1.getValueSizeInBits();
23751 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23752 APInt KnownZero, KnownOne;
23753 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23754 !DCI.isBeforeLegalizeOps());
23755 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23756 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23757 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23758 DCI.CommitTargetLoweringOpt(TLO);
23763 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23764 SDValue Op = N->getOperand(0);
23765 if (Op.getOpcode() == ISD::BITCAST)
23766 Op = Op.getOperand(0);
23767 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23768 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23769 VT.getVectorElementType().getSizeInBits() ==
23770 OpVT.getVectorElementType().getSizeInBits()) {
23771 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23776 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23777 const X86Subtarget *Subtarget) {
23778 EVT VT = N->getValueType(0);
23779 if (!VT.isVector())
23782 SDValue N0 = N->getOperand(0);
23783 SDValue N1 = N->getOperand(1);
23784 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23787 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23788 // both SSE and AVX2 since there is no sign-extended shift right
23789 // operation on a vector with 64-bit elements.
23790 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23791 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23792 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23793 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23794 SDValue N00 = N0.getOperand(0);
23796 // EXTLOAD has a better solution on AVX2,
23797 // it may be replaced with X86ISD::VSEXT node.
23798 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23799 if (!ISD::isNormalLoad(N00.getNode()))
23802 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23803 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23805 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23811 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23812 TargetLowering::DAGCombinerInfo &DCI,
23813 const X86Subtarget *Subtarget) {
23814 SDValue N0 = N->getOperand(0);
23815 EVT VT = N->getValueType(0);
23816 EVT SVT = VT.getScalarType();
23817 EVT InVT = N0->getValueType(0);
23818 EVT InSVT = InVT.getScalarType();
23821 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23822 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23823 // This exposes the sext to the sdivrem lowering, so that it directly extends
23824 // from AH (which we otherwise need to do contortions to access).
23825 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23826 InVT == MVT::i8 && VT == MVT::i32) {
23827 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23828 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
23829 N0.getOperand(0), N0.getOperand(1));
23830 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23831 return R.getValue(1);
23834 if (!DCI.isBeforeLegalizeOps()) {
23835 if (N0.getValueType() == MVT::i1) {
23836 SDValue Zero = DAG.getConstant(0, DL, VT);
23838 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
23839 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
23844 if (VT.isVector()) {
23845 auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
23846 EVT InVT = N->getValueType(0);
23847 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
23848 128 / InVT.getScalarSizeInBits());
23849 SmallVector<SDValue, 8> Opnds(128 / InVT.getSizeInBits(),
23850 DAG.getUNDEF(InVT));
23852 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
23855 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
23856 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
23857 if (VT.getSizeInBits() == 128 &&
23858 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
23859 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
23860 SDValue ExOp = ExtendToVec128(DL, N0);
23861 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
23864 // On pre-AVX2 targets, split into 128-bit nodes of
23865 // ISD::SIGN_EXTEND_VECTOR_INREG.
23866 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
23867 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
23868 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
23869 unsigned NumVecs = VT.getSizeInBits() / 128;
23870 unsigned NumSubElts = 128 / SVT.getSizeInBits();
23871 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
23872 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
23874 SmallVector<SDValue, 8> Opnds;
23875 for (unsigned i = 0, Offset = 0; i != NumVecs;
23876 ++i, Offset += NumSubElts) {
23877 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
23878 DAG.getIntPtrConstant(Offset, DL));
23879 SrcVec = ExtendToVec128(DL, SrcVec);
23880 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
23881 Opnds.push_back(SrcVec);
23883 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
23887 if (!Subtarget->hasFp256())
23890 if (VT.isVector() && VT.getSizeInBits() == 256) {
23891 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23899 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23900 const X86Subtarget* Subtarget) {
23902 EVT VT = N->getValueType(0);
23904 // Let legalize expand this if it isn't a legal type yet.
23905 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23908 EVT ScalarVT = VT.getScalarType();
23909 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23910 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23913 SDValue A = N->getOperand(0);
23914 SDValue B = N->getOperand(1);
23915 SDValue C = N->getOperand(2);
23917 bool NegA = (A.getOpcode() == ISD::FNEG);
23918 bool NegB = (B.getOpcode() == ISD::FNEG);
23919 bool NegC = (C.getOpcode() == ISD::FNEG);
23921 // Negative multiplication when NegA xor NegB
23922 bool NegMul = (NegA != NegB);
23924 A = A.getOperand(0);
23926 B = B.getOperand(0);
23928 C = C.getOperand(0);
23932 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23934 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23936 return DAG.getNode(Opcode, dl, VT, A, B, C);
23939 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23940 TargetLowering::DAGCombinerInfo &DCI,
23941 const X86Subtarget *Subtarget) {
23942 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23943 // (and (i32 x86isd::setcc_carry), 1)
23944 // This eliminates the zext. This transformation is necessary because
23945 // ISD::SETCC is always legalized to i8.
23947 SDValue N0 = N->getOperand(0);
23948 EVT VT = N->getValueType(0);
23950 if (N0.getOpcode() == ISD::AND &&
23952 N0.getOperand(0).hasOneUse()) {
23953 SDValue N00 = N0.getOperand(0);
23954 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23956 if (!C || C->getZExtValue() != 1)
23958 return DAG.getNode(ISD::AND, dl, VT,
23959 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23960 N00.getOperand(0), N00.getOperand(1)),
23961 DAG.getConstant(1, dl, VT));
23965 if (N0.getOpcode() == ISD::TRUNCATE &&
23967 N0.getOperand(0).hasOneUse()) {
23968 SDValue N00 = N0.getOperand(0);
23969 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23970 return DAG.getNode(ISD::AND, dl, VT,
23971 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23972 N00.getOperand(0), N00.getOperand(1)),
23973 DAG.getConstant(1, dl, VT));
23976 if (VT.is256BitVector()) {
23977 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23982 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23983 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23984 // This exposes the zext to the udivrem lowering, so that it directly extends
23985 // from AH (which we otherwise need to do contortions to access).
23986 if (N0.getOpcode() == ISD::UDIVREM &&
23987 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23988 (VT == MVT::i32 || VT == MVT::i64)) {
23989 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23990 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23991 N0.getOperand(0), N0.getOperand(1));
23992 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23993 return R.getValue(1);
23999 // Optimize x == -y --> x+y == 0
24000 // x != -y --> x+y != 0
24001 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24002 const X86Subtarget* Subtarget) {
24003 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24004 SDValue LHS = N->getOperand(0);
24005 SDValue RHS = N->getOperand(1);
24006 EVT VT = N->getValueType(0);
24009 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24011 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24012 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24013 LHS.getOperand(1));
24014 return DAG.getSetCC(DL, N->getValueType(0), addV,
24015 DAG.getConstant(0, DL, addV.getValueType()), CC);
24017 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24018 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24019 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24020 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24021 RHS.getOperand(1));
24022 return DAG.getSetCC(DL, N->getValueType(0), addV,
24023 DAG.getConstant(0, DL, addV.getValueType()), CC);
24026 if (VT.getScalarType() == MVT::i1 &&
24027 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24029 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24030 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24031 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24033 if (!IsSEXT0 || !IsVZero1) {
24034 // Swap the operands and update the condition code.
24035 std::swap(LHS, RHS);
24036 CC = ISD::getSetCCSwappedOperands(CC);
24038 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24039 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24040 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24043 if (IsSEXT0 && IsVZero1) {
24044 assert(VT == LHS.getOperand(0).getValueType() &&
24045 "Uexpected operand type");
24046 if (CC == ISD::SETGT)
24047 return DAG.getConstant(0, DL, VT);
24048 if (CC == ISD::SETLE)
24049 return DAG.getConstant(1, DL, VT);
24050 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24051 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24053 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24054 "Unexpected condition code!");
24055 return LHS.getOperand(0);
24062 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24063 SelectionDAG &DAG) {
24065 MVT VT = Load->getSimpleValueType(0);
24066 MVT EVT = VT.getVectorElementType();
24067 SDValue Addr = Load->getOperand(1);
24068 SDValue NewAddr = DAG.getNode(
24069 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24070 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24071 Addr.getSimpleValueType()));
24074 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24075 DAG.getMachineFunction().getMachineMemOperand(
24076 Load->getMemOperand(), 0, EVT.getStoreSize()));
24080 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24081 const X86Subtarget *Subtarget) {
24083 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24084 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24085 "X86insertps is only defined for v4x32");
24087 SDValue Ld = N->getOperand(1);
24088 if (MayFoldLoad(Ld)) {
24089 // Extract the countS bits from the immediate so we can get the proper
24090 // address when narrowing the vector load to a specific element.
24091 // When the second source op is a memory address, insertps doesn't use
24092 // countS and just gets an f32 from that address.
24093 unsigned DestIndex =
24094 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24096 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24098 // Create this as a scalar to vector to match the instruction pattern.
24099 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24100 // countS bits are ignored when loading from memory on insertps, which
24101 // means we don't need to explicitly set them to 0.
24102 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24103 LoadScalarToVector, N->getOperand(2));
24108 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24109 SDValue V0 = N->getOperand(0);
24110 SDValue V1 = N->getOperand(1);
24112 EVT VT = N->getValueType(0);
24114 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24115 // operands and changing the mask to 1. This saves us a bunch of
24116 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24117 // x86InstrInfo knows how to commute this back after instruction selection
24118 // if it would help register allocation.
24120 // TODO: If optimizing for size or a processor that doesn't suffer from
24121 // partial register update stalls, this should be transformed into a MOVSD
24122 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24124 if (VT == MVT::v2f64)
24125 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24126 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24127 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24128 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24134 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24135 // as "sbb reg,reg", since it can be extended without zext and produces
24136 // an all-ones bit which is more useful than 0/1 in some cases.
24137 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24140 return DAG.getNode(ISD::AND, DL, VT,
24141 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24142 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24144 DAG.getConstant(1, DL, VT));
24145 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24146 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24147 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24148 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24152 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24153 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24154 TargetLowering::DAGCombinerInfo &DCI,
24155 const X86Subtarget *Subtarget) {
24157 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24158 SDValue EFLAGS = N->getOperand(1);
24160 if (CC == X86::COND_A) {
24161 // Try to convert COND_A into COND_B in an attempt to facilitate
24162 // materializing "setb reg".
24164 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24165 // cannot take an immediate as its first operand.
24167 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24168 EFLAGS.getValueType().isInteger() &&
24169 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24170 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24171 EFLAGS.getNode()->getVTList(),
24172 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24173 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24174 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24178 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24179 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24181 if (CC == X86::COND_B)
24182 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24186 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24187 if (Flags.getNode()) {
24188 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24189 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24195 // Optimize branch condition evaluation.
24197 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24198 TargetLowering::DAGCombinerInfo &DCI,
24199 const X86Subtarget *Subtarget) {
24201 SDValue Chain = N->getOperand(0);
24202 SDValue Dest = N->getOperand(1);
24203 SDValue EFLAGS = N->getOperand(3);
24204 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24208 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24209 if (Flags.getNode()) {
24210 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24211 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24218 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24219 SelectionDAG &DAG) {
24220 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24221 // optimize away operation when it's from a constant.
24223 // The general transformation is:
24224 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24225 // AND(VECTOR_CMP(x,y), constant2)
24226 // constant2 = UNARYOP(constant)
24228 // Early exit if this isn't a vector operation, the operand of the
24229 // unary operation isn't a bitwise AND, or if the sizes of the operations
24230 // aren't the same.
24231 EVT VT = N->getValueType(0);
24232 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24233 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24234 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24237 // Now check that the other operand of the AND is a constant. We could
24238 // make the transformation for non-constant splats as well, but it's unclear
24239 // that would be a benefit as it would not eliminate any operations, just
24240 // perform one more step in scalar code before moving to the vector unit.
24241 if (BuildVectorSDNode *BV =
24242 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24243 // Bail out if the vector isn't a constant.
24244 if (!BV->isConstant())
24247 // Everything checks out. Build up the new and improved node.
24249 EVT IntVT = BV->getValueType(0);
24250 // Create a new constant of the appropriate type for the transformed
24252 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24253 // The AND node needs bitcasts to/from an integer vector type around it.
24254 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24255 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24256 N->getOperand(0)->getOperand(0), MaskConst);
24257 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24264 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24265 const X86Subtarget *Subtarget) {
24266 // First try to optimize away the conversion entirely when it's
24267 // conditionally from a constant. Vectors only.
24268 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24269 if (Res != SDValue())
24272 // Now move on to more general possibilities.
24273 SDValue Op0 = N->getOperand(0);
24274 EVT InVT = Op0->getValueType(0);
24276 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24277 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24279 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24280 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24281 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24284 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24285 // a 32-bit target where SSE doesn't support i64->FP operations.
24286 if (Op0.getOpcode() == ISD::LOAD) {
24287 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24288 EVT VT = Ld->getValueType(0);
24290 // This transformation is not supported if the result type is f16
24291 if (N->getValueType(0) == MVT::f16)
24294 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24295 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24296 !Subtarget->is64Bit() && VT == MVT::i64) {
24297 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24298 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24299 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24306 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24307 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24308 X86TargetLowering::DAGCombinerInfo &DCI) {
24309 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24310 // the result is either zero or one (depending on the input carry bit).
24311 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24312 if (X86::isZeroNode(N->getOperand(0)) &&
24313 X86::isZeroNode(N->getOperand(1)) &&
24314 // We don't have a good way to replace an EFLAGS use, so only do this when
24316 SDValue(N, 1).use_empty()) {
24318 EVT VT = N->getValueType(0);
24319 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24320 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24321 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24322 DAG.getConstant(X86::COND_B, DL,
24325 DAG.getConstant(1, DL, VT));
24326 return DCI.CombineTo(N, Res1, CarryOut);
24332 // fold (add Y, (sete X, 0)) -> adc 0, Y
24333 // (add Y, (setne X, 0)) -> sbb -1, Y
24334 // (sub (sete X, 0), Y) -> sbb 0, Y
24335 // (sub (setne X, 0), Y) -> adc -1, Y
24336 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24339 // Look through ZExts.
24340 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24341 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24344 SDValue SetCC = Ext.getOperand(0);
24345 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24348 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24349 if (CC != X86::COND_E && CC != X86::COND_NE)
24352 SDValue Cmp = SetCC.getOperand(1);
24353 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24354 !X86::isZeroNode(Cmp.getOperand(1)) ||
24355 !Cmp.getOperand(0).getValueType().isInteger())
24358 SDValue CmpOp0 = Cmp.getOperand(0);
24359 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24360 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24362 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24363 if (CC == X86::COND_NE)
24364 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24365 DL, OtherVal.getValueType(), OtherVal,
24366 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24368 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24369 DL, OtherVal.getValueType(), OtherVal,
24370 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24373 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24374 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24375 const X86Subtarget *Subtarget) {
24376 EVT VT = N->getValueType(0);
24377 SDValue Op0 = N->getOperand(0);
24378 SDValue Op1 = N->getOperand(1);
24380 // Try to synthesize horizontal adds from adds of shuffles.
24381 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24382 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24383 isHorizontalBinOp(Op0, Op1, true))
24384 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24386 return OptimizeConditionalInDecrement(N, DAG);
24389 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24390 const X86Subtarget *Subtarget) {
24391 SDValue Op0 = N->getOperand(0);
24392 SDValue Op1 = N->getOperand(1);
24394 // X86 can't encode an immediate LHS of a sub. See if we can push the
24395 // negation into a preceding instruction.
24396 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24397 // If the RHS of the sub is a XOR with one use and a constant, invert the
24398 // immediate. Then add one to the LHS of the sub so we can turn
24399 // X-Y -> X+~Y+1, saving one register.
24400 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24401 isa<ConstantSDNode>(Op1.getOperand(1))) {
24402 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24403 EVT VT = Op0.getValueType();
24404 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24406 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24407 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24408 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24412 // Try to synthesize horizontal adds from adds of shuffles.
24413 EVT VT = N->getValueType(0);
24414 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24415 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24416 isHorizontalBinOp(Op0, Op1, true))
24417 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24419 return OptimizeConditionalInDecrement(N, DAG);
24422 /// performVZEXTCombine - Performs build vector combines
24423 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24424 TargetLowering::DAGCombinerInfo &DCI,
24425 const X86Subtarget *Subtarget) {
24427 MVT VT = N->getSimpleValueType(0);
24428 SDValue Op = N->getOperand(0);
24429 MVT OpVT = Op.getSimpleValueType();
24430 MVT OpEltVT = OpVT.getVectorElementType();
24431 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24433 // (vzext (bitcast (vzext (x)) -> (vzext x)
24435 while (V.getOpcode() == ISD::BITCAST)
24436 V = V.getOperand(0);
24438 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24439 MVT InnerVT = V.getSimpleValueType();
24440 MVT InnerEltVT = InnerVT.getVectorElementType();
24442 // If the element sizes match exactly, we can just do one larger vzext. This
24443 // is always an exact type match as vzext operates on integer types.
24444 if (OpEltVT == InnerEltVT) {
24445 assert(OpVT == InnerVT && "Types must match for vzext!");
24446 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24449 // The only other way we can combine them is if only a single element of the
24450 // inner vzext is used in the input to the outer vzext.
24451 if (InnerEltVT.getSizeInBits() < InputBits)
24454 // In this case, the inner vzext is completely dead because we're going to
24455 // only look at bits inside of the low element. Just do the outer vzext on
24456 // a bitcast of the input to the inner.
24457 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24458 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24461 // Check if we can bypass extracting and re-inserting an element of an input
24462 // vector. Essentialy:
24463 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24464 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24465 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24466 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24467 SDValue ExtractedV = V.getOperand(0);
24468 SDValue OrigV = ExtractedV.getOperand(0);
24469 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24470 if (ExtractIdx->getZExtValue() == 0) {
24471 MVT OrigVT = OrigV.getSimpleValueType();
24472 // Extract a subvector if necessary...
24473 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24474 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24475 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24476 OrigVT.getVectorNumElements() / Ratio);
24477 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24478 DAG.getIntPtrConstant(0, DL));
24480 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24481 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24488 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24489 DAGCombinerInfo &DCI) const {
24490 SelectionDAG &DAG = DCI.DAG;
24491 switch (N->getOpcode()) {
24493 case ISD::EXTRACT_VECTOR_ELT:
24494 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24497 case X86ISD::SHRUNKBLEND:
24498 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24499 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24500 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24501 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24502 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24503 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24504 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24507 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24508 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24509 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24510 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24511 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24512 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24513 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24514 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24515 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24516 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24517 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24519 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24521 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24522 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24523 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24524 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24525 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24526 case ISD::ANY_EXTEND:
24527 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24528 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24529 case ISD::SIGN_EXTEND_INREG:
24530 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24531 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24532 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24533 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24534 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24535 case X86ISD::SHUFP: // Handle all target specific shuffles
24536 case X86ISD::PALIGNR:
24537 case X86ISD::UNPCKH:
24538 case X86ISD::UNPCKL:
24539 case X86ISD::MOVHLPS:
24540 case X86ISD::MOVLHPS:
24541 case X86ISD::PSHUFB:
24542 case X86ISD::PSHUFD:
24543 case X86ISD::PSHUFHW:
24544 case X86ISD::PSHUFLW:
24545 case X86ISD::MOVSS:
24546 case X86ISD::MOVSD:
24547 case X86ISD::VPERMILPI:
24548 case X86ISD::VPERM2X128:
24549 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24550 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24551 case ISD::INTRINSIC_WO_CHAIN:
24552 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24553 case X86ISD::INSERTPS: {
24554 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24555 return PerformINSERTPSCombine(N, DAG, Subtarget);
24558 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24564 /// isTypeDesirableForOp - Return true if the target has native support for
24565 /// the specified value type and it is 'desirable' to use the type for the
24566 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24567 /// instruction encodings are longer and some i16 instructions are slow.
24568 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24569 if (!isTypeLegal(VT))
24571 if (VT != MVT::i16)
24578 case ISD::SIGN_EXTEND:
24579 case ISD::ZERO_EXTEND:
24580 case ISD::ANY_EXTEND:
24593 /// IsDesirableToPromoteOp - This method query the target whether it is
24594 /// beneficial for dag combiner to promote the specified node. If true, it
24595 /// should return the desired promotion type by reference.
24596 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24597 EVT VT = Op.getValueType();
24598 if (VT != MVT::i16)
24601 bool Promote = false;
24602 bool Commute = false;
24603 switch (Op.getOpcode()) {
24606 LoadSDNode *LD = cast<LoadSDNode>(Op);
24607 // If the non-extending load has a single use and it's not live out, then it
24608 // might be folded.
24609 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24610 Op.hasOneUse()*/) {
24611 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24612 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24613 // The only case where we'd want to promote LOAD (rather then it being
24614 // promoted as an operand is when it's only use is liveout.
24615 if (UI->getOpcode() != ISD::CopyToReg)
24622 case ISD::SIGN_EXTEND:
24623 case ISD::ZERO_EXTEND:
24624 case ISD::ANY_EXTEND:
24629 SDValue N0 = Op.getOperand(0);
24630 // Look out for (store (shl (load), x)).
24631 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24644 SDValue N0 = Op.getOperand(0);
24645 SDValue N1 = Op.getOperand(1);
24646 if (!Commute && MayFoldLoad(N1))
24648 // Avoid disabling potential load folding opportunities.
24649 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24651 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24661 //===----------------------------------------------------------------------===//
24662 // X86 Inline Assembly Support
24663 //===----------------------------------------------------------------------===//
24665 // Helper to match a string separated by whitespace.
24666 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24667 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24669 for (StringRef Piece : Pieces) {
24670 if (!S.startswith(Piece)) // Check if the piece matches.
24673 S = S.substr(Piece.size());
24674 StringRef::size_type Pos = S.find_first_not_of(" \t");
24675 if (Pos == 0) // We matched a prefix.
24684 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24686 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24687 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24688 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24689 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24691 if (AsmPieces.size() == 3)
24693 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24700 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24701 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24703 std::string AsmStr = IA->getAsmString();
24705 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24706 if (!Ty || Ty->getBitWidth() % 16 != 0)
24709 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24710 SmallVector<StringRef, 4> AsmPieces;
24711 SplitString(AsmStr, AsmPieces, ";\n");
24713 switch (AsmPieces.size()) {
24714 default: return false;
24716 // FIXME: this should verify that we are targeting a 486 or better. If not,
24717 // we will turn this bswap into something that will be lowered to logical
24718 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24719 // lower so don't worry about this.
24721 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24722 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24723 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24724 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24725 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24726 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24727 // No need to check constraints, nothing other than the equivalent of
24728 // "=r,0" would be valid here.
24729 return IntrinsicLowering::LowerToByteSwap(CI);
24732 // rorw $$8, ${0:w} --> llvm.bswap.i16
24733 if (CI->getType()->isIntegerTy(16) &&
24734 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24735 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24736 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24738 const std::string &ConstraintsStr = IA->getConstraintString();
24739 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24740 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24741 if (clobbersFlagRegisters(AsmPieces))
24742 return IntrinsicLowering::LowerToByteSwap(CI);
24746 if (CI->getType()->isIntegerTy(32) &&
24747 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24748 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24749 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24750 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24752 const std::string &ConstraintsStr = IA->getConstraintString();
24753 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24754 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24755 if (clobbersFlagRegisters(AsmPieces))
24756 return IntrinsicLowering::LowerToByteSwap(CI);
24759 if (CI->getType()->isIntegerTy(64)) {
24760 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24761 if (Constraints.size() >= 2 &&
24762 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24763 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24764 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24765 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24766 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24767 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24768 return IntrinsicLowering::LowerToByteSwap(CI);
24776 /// getConstraintType - Given a constraint letter, return the type of
24777 /// constraint it is for this target.
24778 X86TargetLowering::ConstraintType
24779 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24780 if (Constraint.size() == 1) {
24781 switch (Constraint[0]) {
24792 return C_RegisterClass;
24816 return TargetLowering::getConstraintType(Constraint);
24819 /// Examine constraint type and operand type and determine a weight value.
24820 /// This object must already have been set up with the operand type
24821 /// and the current alternative constraint selected.
24822 TargetLowering::ConstraintWeight
24823 X86TargetLowering::getSingleConstraintMatchWeight(
24824 AsmOperandInfo &info, const char *constraint) const {
24825 ConstraintWeight weight = CW_Invalid;
24826 Value *CallOperandVal = info.CallOperandVal;
24827 // If we don't have a value, we can't do a match,
24828 // but allow it at the lowest weight.
24829 if (!CallOperandVal)
24831 Type *type = CallOperandVal->getType();
24832 // Look at the constraint type.
24833 switch (*constraint) {
24835 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24846 if (CallOperandVal->getType()->isIntegerTy())
24847 weight = CW_SpecificReg;
24852 if (type->isFloatingPointTy())
24853 weight = CW_SpecificReg;
24856 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24857 weight = CW_SpecificReg;
24861 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24862 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24863 weight = CW_Register;
24866 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24867 if (C->getZExtValue() <= 31)
24868 weight = CW_Constant;
24872 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24873 if (C->getZExtValue() <= 63)
24874 weight = CW_Constant;
24878 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24879 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24880 weight = CW_Constant;
24884 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24885 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24886 weight = CW_Constant;
24890 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24891 if (C->getZExtValue() <= 3)
24892 weight = CW_Constant;
24896 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24897 if (C->getZExtValue() <= 0xff)
24898 weight = CW_Constant;
24903 if (isa<ConstantFP>(CallOperandVal)) {
24904 weight = CW_Constant;
24908 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24909 if ((C->getSExtValue() >= -0x80000000LL) &&
24910 (C->getSExtValue() <= 0x7fffffffLL))
24911 weight = CW_Constant;
24915 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24916 if (C->getZExtValue() <= 0xffffffff)
24917 weight = CW_Constant;
24924 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24925 /// with another that has more specific requirements based on the type of the
24926 /// corresponding operand.
24927 const char *X86TargetLowering::
24928 LowerXConstraint(EVT ConstraintVT) const {
24929 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24930 // 'f' like normal targets.
24931 if (ConstraintVT.isFloatingPoint()) {
24932 if (Subtarget->hasSSE2())
24934 if (Subtarget->hasSSE1())
24938 return TargetLowering::LowerXConstraint(ConstraintVT);
24941 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24942 /// vector. If it is invalid, don't add anything to Ops.
24943 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24944 std::string &Constraint,
24945 std::vector<SDValue>&Ops,
24946 SelectionDAG &DAG) const {
24949 // Only support length 1 constraints for now.
24950 if (Constraint.length() > 1) return;
24952 char ConstraintLetter = Constraint[0];
24953 switch (ConstraintLetter) {
24956 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24957 if (C->getZExtValue() <= 31) {
24958 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24959 Op.getValueType());
24965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24966 if (C->getZExtValue() <= 63) {
24967 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24968 Op.getValueType());
24974 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24975 if (isInt<8>(C->getSExtValue())) {
24976 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24977 Op.getValueType());
24983 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24984 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24985 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24986 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
24987 Op.getValueType());
24993 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24994 if (C->getZExtValue() <= 3) {
24995 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24996 Op.getValueType());
25002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25003 if (C->getZExtValue() <= 255) {
25004 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25005 Op.getValueType());
25011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25012 if (C->getZExtValue() <= 127) {
25013 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25014 Op.getValueType());
25020 // 32-bit signed value
25021 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25022 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25023 C->getSExtValue())) {
25024 // Widen to 64 bits here to get it sign extended.
25025 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25028 // FIXME gcc accepts some relocatable values here too, but only in certain
25029 // memory models; it's complicated.
25034 // 32-bit unsigned value
25035 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25036 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25037 C->getZExtValue())) {
25038 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25039 Op.getValueType());
25043 // FIXME gcc accepts some relocatable values here too, but only in certain
25044 // memory models; it's complicated.
25048 // Literal immediates are always ok.
25049 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25050 // Widen to 64 bits here to get it sign extended.
25051 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25055 // In any sort of PIC mode addresses need to be computed at runtime by
25056 // adding in a register or some sort of table lookup. These can't
25057 // be used as immediates.
25058 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25061 // If we are in non-pic codegen mode, we allow the address of a global (with
25062 // an optional displacement) to be used with 'i'.
25063 GlobalAddressSDNode *GA = nullptr;
25064 int64_t Offset = 0;
25066 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25068 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25069 Offset += GA->getOffset();
25071 } else if (Op.getOpcode() == ISD::ADD) {
25072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25073 Offset += C->getZExtValue();
25074 Op = Op.getOperand(0);
25077 } else if (Op.getOpcode() == ISD::SUB) {
25078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25079 Offset += -C->getZExtValue();
25080 Op = Op.getOperand(0);
25085 // Otherwise, this isn't something we can handle, reject it.
25089 const GlobalValue *GV = GA->getGlobal();
25090 // If we require an extra load to get this address, as in PIC mode, we
25091 // can't accept it.
25092 if (isGlobalStubReference(
25093 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25096 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25097 GA->getValueType(0), Offset);
25102 if (Result.getNode()) {
25103 Ops.push_back(Result);
25106 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25109 std::pair<unsigned, const TargetRegisterClass *>
25110 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25111 const std::string &Constraint,
25113 // First, see if this is a constraint that directly corresponds to an LLVM
25115 if (Constraint.size() == 1) {
25116 // GCC Constraint Letters
25117 switch (Constraint[0]) {
25119 // TODO: Slight differences here in allocation order and leaving
25120 // RIP in the class. Do they matter any more here than they do
25121 // in the normal allocation?
25122 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25123 if (Subtarget->is64Bit()) {
25124 if (VT == MVT::i32 || VT == MVT::f32)
25125 return std::make_pair(0U, &X86::GR32RegClass);
25126 if (VT == MVT::i16)
25127 return std::make_pair(0U, &X86::GR16RegClass);
25128 if (VT == MVT::i8 || VT == MVT::i1)
25129 return std::make_pair(0U, &X86::GR8RegClass);
25130 if (VT == MVT::i64 || VT == MVT::f64)
25131 return std::make_pair(0U, &X86::GR64RegClass);
25134 // 32-bit fallthrough
25135 case 'Q': // Q_REGS
25136 if (VT == MVT::i32 || VT == MVT::f32)
25137 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25138 if (VT == MVT::i16)
25139 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25140 if (VT == MVT::i8 || VT == MVT::i1)
25141 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25142 if (VT == MVT::i64)
25143 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25145 case 'r': // GENERAL_REGS
25146 case 'l': // INDEX_REGS
25147 if (VT == MVT::i8 || VT == MVT::i1)
25148 return std::make_pair(0U, &X86::GR8RegClass);
25149 if (VT == MVT::i16)
25150 return std::make_pair(0U, &X86::GR16RegClass);
25151 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25152 return std::make_pair(0U, &X86::GR32RegClass);
25153 return std::make_pair(0U, &X86::GR64RegClass);
25154 case 'R': // LEGACY_REGS
25155 if (VT == MVT::i8 || VT == MVT::i1)
25156 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25157 if (VT == MVT::i16)
25158 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25159 if (VT == MVT::i32 || !Subtarget->is64Bit())
25160 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25161 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25162 case 'f': // FP Stack registers.
25163 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25164 // value to the correct fpstack register class.
25165 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25166 return std::make_pair(0U, &X86::RFP32RegClass);
25167 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25168 return std::make_pair(0U, &X86::RFP64RegClass);
25169 return std::make_pair(0U, &X86::RFP80RegClass);
25170 case 'y': // MMX_REGS if MMX allowed.
25171 if (!Subtarget->hasMMX()) break;
25172 return std::make_pair(0U, &X86::VR64RegClass);
25173 case 'Y': // SSE_REGS if SSE2 allowed
25174 if (!Subtarget->hasSSE2()) break;
25176 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25177 if (!Subtarget->hasSSE1()) break;
25179 switch (VT.SimpleTy) {
25181 // Scalar SSE types.
25184 return std::make_pair(0U, &X86::FR32RegClass);
25187 return std::make_pair(0U, &X86::FR64RegClass);
25195 return std::make_pair(0U, &X86::VR128RegClass);
25203 return std::make_pair(0U, &X86::VR256RegClass);
25208 return std::make_pair(0U, &X86::VR512RegClass);
25214 // Use the default implementation in TargetLowering to convert the register
25215 // constraint into a member of a register class.
25216 std::pair<unsigned, const TargetRegisterClass*> Res;
25217 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25219 // Not found as a standard register?
25221 // Map st(0) -> st(7) -> ST0
25222 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25223 tolower(Constraint[1]) == 's' &&
25224 tolower(Constraint[2]) == 't' &&
25225 Constraint[3] == '(' &&
25226 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25227 Constraint[5] == ')' &&
25228 Constraint[6] == '}') {
25230 Res.first = X86::FP0+Constraint[4]-'0';
25231 Res.second = &X86::RFP80RegClass;
25235 // GCC allows "st(0)" to be called just plain "st".
25236 if (StringRef("{st}").equals_lower(Constraint)) {
25237 Res.first = X86::FP0;
25238 Res.second = &X86::RFP80RegClass;
25243 if (StringRef("{flags}").equals_lower(Constraint)) {
25244 Res.first = X86::EFLAGS;
25245 Res.second = &X86::CCRRegClass;
25249 // 'A' means EAX + EDX.
25250 if (Constraint == "A") {
25251 Res.first = X86::EAX;
25252 Res.second = &X86::GR32_ADRegClass;
25258 // Otherwise, check to see if this is a register class of the wrong value
25259 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25260 // turn into {ax},{dx}.
25261 if (Res.second->hasType(VT))
25262 return Res; // Correct type already, nothing to do.
25264 // All of the single-register GCC register classes map their values onto
25265 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25266 // really want an 8-bit or 32-bit register, map to the appropriate register
25267 // class and return the appropriate register.
25268 if (Res.second == &X86::GR16RegClass) {
25269 if (VT == MVT::i8 || VT == MVT::i1) {
25270 unsigned DestReg = 0;
25271 switch (Res.first) {
25273 case X86::AX: DestReg = X86::AL; break;
25274 case X86::DX: DestReg = X86::DL; break;
25275 case X86::CX: DestReg = X86::CL; break;
25276 case X86::BX: DestReg = X86::BL; break;
25279 Res.first = DestReg;
25280 Res.second = &X86::GR8RegClass;
25282 } else if (VT == MVT::i32 || VT == MVT::f32) {
25283 unsigned DestReg = 0;
25284 switch (Res.first) {
25286 case X86::AX: DestReg = X86::EAX; break;
25287 case X86::DX: DestReg = X86::EDX; break;
25288 case X86::CX: DestReg = X86::ECX; break;
25289 case X86::BX: DestReg = X86::EBX; break;
25290 case X86::SI: DestReg = X86::ESI; break;
25291 case X86::DI: DestReg = X86::EDI; break;
25292 case X86::BP: DestReg = X86::EBP; break;
25293 case X86::SP: DestReg = X86::ESP; break;
25296 Res.first = DestReg;
25297 Res.second = &X86::GR32RegClass;
25299 } else if (VT == MVT::i64 || VT == MVT::f64) {
25300 unsigned DestReg = 0;
25301 switch (Res.first) {
25303 case X86::AX: DestReg = X86::RAX; break;
25304 case X86::DX: DestReg = X86::RDX; break;
25305 case X86::CX: DestReg = X86::RCX; break;
25306 case X86::BX: DestReg = X86::RBX; break;
25307 case X86::SI: DestReg = X86::RSI; break;
25308 case X86::DI: DestReg = X86::RDI; break;
25309 case X86::BP: DestReg = X86::RBP; break;
25310 case X86::SP: DestReg = X86::RSP; break;
25313 Res.first = DestReg;
25314 Res.second = &X86::GR64RegClass;
25317 } else if (Res.second == &X86::FR32RegClass ||
25318 Res.second == &X86::FR64RegClass ||
25319 Res.second == &X86::VR128RegClass ||
25320 Res.second == &X86::VR256RegClass ||
25321 Res.second == &X86::FR32XRegClass ||
25322 Res.second == &X86::FR64XRegClass ||
25323 Res.second == &X86::VR128XRegClass ||
25324 Res.second == &X86::VR256XRegClass ||
25325 Res.second == &X86::VR512RegClass) {
25326 // Handle references to XMM physical registers that got mapped into the
25327 // wrong class. This can happen with constraints like {xmm0} where the
25328 // target independent register mapper will just pick the first match it can
25329 // find, ignoring the required type.
25331 if (VT == MVT::f32 || VT == MVT::i32)
25332 Res.second = &X86::FR32RegClass;
25333 else if (VT == MVT::f64 || VT == MVT::i64)
25334 Res.second = &X86::FR64RegClass;
25335 else if (X86::VR128RegClass.hasType(VT))
25336 Res.second = &X86::VR128RegClass;
25337 else if (X86::VR256RegClass.hasType(VT))
25338 Res.second = &X86::VR256RegClass;
25339 else if (X86::VR512RegClass.hasType(VT))
25340 Res.second = &X86::VR512RegClass;
25346 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25348 // Scaling factors are not free at all.
25349 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25350 // will take 2 allocations in the out of order engine instead of 1
25351 // for plain addressing mode, i.e. inst (reg1).
25353 // vaddps (%rsi,%drx), %ymm0, %ymm1
25354 // Requires two allocations (one for the load, one for the computation)
25356 // vaddps (%rsi), %ymm0, %ymm1
25357 // Requires just 1 allocation, i.e., freeing allocations for other operations
25358 // and having less micro operations to execute.
25360 // For some X86 architectures, this is even worse because for instance for
25361 // stores, the complex addressing mode forces the instruction to use the
25362 // "load" ports instead of the dedicated "store" port.
25363 // E.g., on Haswell:
25364 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25365 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25366 if (isLegalAddressingMode(AM, Ty))
25367 // Scale represents reg2 * scale, thus account for 1
25368 // as soon as we use a second register.
25369 return AM.Scale != 0;
25373 bool X86TargetLowering::isTargetFTOL() const {
25374 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();