1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::PSHUFB:
3543 case X86ISD::PSHUFD:
3544 case X86ISD::PSHUFHW:
3545 case X86ISD::PSHUFLW:
3547 case X86ISD::PALIGNR:
3548 case X86ISD::MOVLHPS:
3549 case X86ISD::MOVLHPD:
3550 case X86ISD::MOVHLPS:
3551 case X86ISD::MOVLPS:
3552 case X86ISD::MOVLPD:
3553 case X86ISD::MOVSHDUP:
3554 case X86ISD::MOVSLDUP:
3555 case X86ISD::MOVDDUP:
3558 case X86ISD::UNPCKL:
3559 case X86ISD::UNPCKH:
3560 case X86ISD::VPERMILP:
3561 case X86ISD::VPERM2X128:
3562 case X86ISD::VPERMI:
3567 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3568 SDValue V1, SelectionDAG &DAG) {
3570 default: llvm_unreachable("Unknown x86 shuffle node");
3571 case X86ISD::MOVSHDUP:
3572 case X86ISD::MOVSLDUP:
3573 case X86ISD::MOVDDUP:
3574 return DAG.getNode(Opc, dl, VT, V1);
3578 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3579 SDValue V1, unsigned TargetMask,
3580 SelectionDAG &DAG) {
3582 default: llvm_unreachable("Unknown x86 shuffle node");
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3586 case X86ISD::VPERMILP:
3587 case X86ISD::VPERMI:
3588 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3592 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3593 SDValue V1, SDValue V2, unsigned TargetMask,
3594 SelectionDAG &DAG) {
3596 default: llvm_unreachable("Unknown x86 shuffle node");
3597 case X86ISD::PALIGNR:
3598 case X86ISD::VALIGN:
3600 case X86ISD::VPERM2X128:
3601 return DAG.getNode(Opc, dl, VT, V1, V2,
3602 DAG.getConstant(TargetMask, MVT::i8));
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::MOVLHPS:
3611 case X86ISD::MOVLHPD:
3612 case X86ISD::MOVHLPS:
3613 case X86ISD::MOVLPS:
3614 case X86ISD::MOVLPD:
3617 case X86ISD::UNPCKL:
3618 case X86ISD::UNPCKH:
3619 return DAG.getNode(Opc, dl, VT, V1, V2);
3623 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3626 DAG.getSubtarget().getRegisterInfo());
3627 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3628 int ReturnAddrIndex = FuncInfo->getRAIndex();
3630 if (ReturnAddrIndex == 0) {
3631 // Set up a frame object for the return address.
3632 unsigned SlotSize = RegInfo->getSlotSize();
3633 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3643 bool hasSymbolicDisplacement) {
3644 // Offset should fit into 32 bit immediate field.
3645 if (!isInt<32>(Offset))
3648 // If we don't have a symbolic displacement - we don't have any extra
3650 if (!hasSymbolicDisplacement)
3653 // FIXME: Some tweaks might be needed for medium code model.
3654 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 // For small code model we assume that latest object is 16MB before end of 31
3658 // bits boundary. We may also accept pretty large negative constants knowing
3659 // that all objects are in the positive half of address space.
3660 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 // For kernel code model we know that all object resist in the negative half
3664 // of 32bits address space. We may not accept negative offsets, since they may
3665 // be just off and we may accept pretty large positive ones.
3666 if (M == CodeModel::Kernel && Offset > 0)
3672 /// isCalleePop - Determines whether the callee is required to pop its
3673 /// own arguments. Callee pop is necessary to support tail calls.
3674 bool X86::isCalleePop(CallingConv::ID CallingConv,
3675 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3676 switch (CallingConv) {
3679 case CallingConv::X86_StdCall:
3680 case CallingConv::X86_FastCall:
3681 case CallingConv::X86_ThisCall:
3683 case CallingConv::Fast:
3684 case CallingConv::GHC:
3685 case CallingConv::HiPE:
3692 /// \brief Return true if the condition is an unsigned comparison operation.
3693 static bool isX86CCUnsigned(unsigned X86CC) {
3695 default: llvm_unreachable("Invalid integer condition!");
3696 case X86::COND_E: return true;
3697 case X86::COND_G: return false;
3698 case X86::COND_GE: return false;
3699 case X86::COND_L: return false;
3700 case X86::COND_LE: return false;
3701 case X86::COND_NE: return true;
3702 case X86::COND_B: return true;
3703 case X86::COND_A: return true;
3704 case X86::COND_BE: return true;
3705 case X86::COND_AE: return true;
3707 llvm_unreachable("covered switch fell through?!");
3710 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3711 /// specific condition code, returning the condition code and the LHS/RHS of the
3712 /// comparison to make.
3713 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3714 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3717 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3718 // X > -1 -> X == 0, jump !sign.
3719 RHS = DAG.getConstant(0, RHS.getValueType());
3720 return X86::COND_NS;
3722 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3723 // X < 0 -> X == 0, jump on sign.
3726 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_LE;
3733 switch (SetCCOpcode) {
3734 default: llvm_unreachable("Invalid integer condition!");
3735 case ISD::SETEQ: return X86::COND_E;
3736 case ISD::SETGT: return X86::COND_G;
3737 case ISD::SETGE: return X86::COND_GE;
3738 case ISD::SETLT: return X86::COND_L;
3739 case ISD::SETLE: return X86::COND_LE;
3740 case ISD::SETNE: return X86::COND_NE;
3741 case ISD::SETULT: return X86::COND_B;
3742 case ISD::SETUGT: return X86::COND_A;
3743 case ISD::SETULE: return X86::COND_BE;
3744 case ISD::SETUGE: return X86::COND_AE;
3748 // First determine if it is required or is profitable to flip the operands.
3750 // If LHS is a foldable load, but RHS is not, flip the condition.
3751 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3752 !ISD::isNON_EXTLoad(RHS.getNode())) {
3753 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3754 std::swap(LHS, RHS);
3757 switch (SetCCOpcode) {
3763 std::swap(LHS, RHS);
3767 // On a floating point condition, the flags are set as follows:
3769 // 0 | 0 | 0 | X > Y
3770 // 0 | 0 | 1 | X < Y
3771 // 1 | 0 | 0 | X == Y
3772 // 1 | 1 | 1 | unordered
3773 switch (SetCCOpcode) {
3774 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETOLT: // flipped
3779 case ISD::SETGT: return X86::COND_A;
3780 case ISD::SETOLE: // flipped
3782 case ISD::SETGE: return X86::COND_AE;
3783 case ISD::SETUGT: // flipped
3785 case ISD::SETLT: return X86::COND_B;
3786 case ISD::SETUGE: // flipped
3788 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETNE: return X86::COND_NE;
3791 case ISD::SETUO: return X86::COND_P;
3792 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETUNE: return X86::COND_INVALID;
3798 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3799 /// code. Current x86 isa includes the following FP cmov instructions:
3800 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3801 static bool hasFPCMov(unsigned X86CC) {
3817 /// isFPImmLegal - Returns true if the target can instruction select the
3818 /// specified FP immediate natively. If false, the legalizer will
3819 /// materialize the FP immediate as a load from a constant pool.
3820 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3821 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3822 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3828 /// \brief Returns true if it is beneficial to convert a load of a constant
3829 /// to just the constant itself.
3830 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 assert(Ty->isIntegerTy());
3834 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3835 if (BitSize == 0 || BitSize > 64)
3840 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3841 /// the specified range (L, H].
3842 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3843 return (Val < 0) || (Val >= Low && Val < Hi);
3846 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3847 /// specified value.
3848 static bool isUndefOrEqual(int Val, int CmpVal) {
3849 return (Val < 0 || Val == CmpVal);
3852 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3853 /// from position Pos and ending in Pos+Size, falls within the specified
3854 /// sequential range (L, L+Pos]. or is undef.
3855 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3856 unsigned Pos, unsigned Size, int Low) {
3857 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3858 if (!isUndefOrEqual(Mask[i], Low))
3863 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3864 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3865 /// the second operand.
3866 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3867 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3868 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3869 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3870 return (Mask[0] < 2 && Mask[1] < 2);
3874 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3875 /// is suitable for input to PSHUFHW.
3876 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3877 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 // Lower quadword copied in order or undef.
3881 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 // Upper quadword shuffled.
3885 for (unsigned i = 4; i != 8; ++i)
3886 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 if (VT == MVT::v16i16) {
3890 // Lower quadword copied in order or undef.
3891 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 // Upper quadword shuffled.
3895 for (unsigned i = 12; i != 16; ++i)
3896 if (!isUndefOrInRange(Mask[i], 12, 16))
3903 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3904 /// is suitable for input to PSHUFLW.
3905 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3906 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 // Upper quadword copied in order.
3910 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 // Lower quadword shuffled.
3914 for (unsigned i = 0; i != 4; ++i)
3915 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 if (VT == MVT::v16i16) {
3919 // Upper quadword copied in order.
3920 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 // Lower quadword shuffled.
3924 for (unsigned i = 8; i != 12; ++i)
3925 if (!isUndefOrInRange(Mask[i], 8, 12))
3932 /// \brief Return true if the mask specifies a shuffle of elements that is
3933 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3936 unsigned NumElts = VT.getVectorNumElements();
3937 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3938 unsigned NumLaneElts = NumElts/NumLanes;
3940 // Do not handle 64-bit element shuffles with palignr.
3941 if (NumLaneElts == 2)
3944 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 for (i = 0; i != NumLaneElts; ++i) {
3951 // Lane is all undef, go to next lane
3952 if (i == NumLaneElts)
3955 int Start = Mask[i+l];
3957 // Make sure its in this lane in one of the sources
3958 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3959 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 // If not lane 0, then we must match lane 0
3963 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 // Correct second source to be contiguous with first source
3967 if (Start >= (int)NumElts)
3968 Start -= NumElts - NumLaneElts;
3970 // Make sure we're shifting in the right direction.
3971 if (Start <= (int)(i+l))
3976 // Check the rest of the elements to see if they are consecutive.
3977 for (++i; i != NumLaneElts; ++i) {
3978 int Idx = Mask[i+l];
3980 // Make sure its in this lane
3981 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3982 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 // If not lane 0, then we must match lane 0
3986 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 if (Idx >= (int)NumElts)
3990 Idx -= NumElts - NumLaneElts;
3992 if (!isUndefOrEqual(Idx, Start+i))
4001 /// \brief Return true if the node specifies a shuffle of elements that is
4002 /// suitable for input to PALIGNR.
4003 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4004 const X86Subtarget *Subtarget) {
4005 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4006 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4007 VT.is512BitVector())
4008 // FIXME: Add AVX512BW.
4011 return isAlignrMask(Mask, VT, false);
4014 /// \brief Return true if the node specifies a shuffle of elements that is
4015 /// suitable for input to VALIGN.
4016 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4017 const X86Subtarget *Subtarget) {
4018 // FIXME: Add AVX512VL.
4019 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return isAlignrMask(Mask, VT, true);
4024 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4025 /// the two vector operands have swapped position.
4026 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4027 unsigned NumElems) {
4028 for (unsigned i = 0; i != NumElems; ++i) {
4032 else if (idx < (int)NumElems)
4033 Mask[i] = idx + NumElems;
4035 Mask[i] = idx - NumElems;
4039 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4040 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4041 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4042 /// reverse of what x86 shuffles want.
4043 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4045 unsigned NumElems = VT.getVectorNumElements();
4046 unsigned NumLanes = VT.getSizeInBits()/128;
4047 unsigned NumLaneElems = NumElems/NumLanes;
4049 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4053 bool symetricMaskRequired =
4054 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4056 // VSHUFPSY divides the resulting vector into 4 chunks.
4057 // The sources are also splitted into 4 chunks, and each destination
4058 // chunk must come from a different source chunk.
4060 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4061 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4064 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 // VSHUFPDY divides the resulting vector into 4 chunks.
4067 // The sources are also splitted into 4 chunks, and each destination
4068 // chunk must come from a different source chunk.
4070 // SRC1 => X3 X2 X1 X0
4071 // SRC2 => Y3 Y2 Y1 Y0
4073 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4076 unsigned HalfLaneElems = NumLaneElems/2;
4077 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4078 for (unsigned i = 0; i != NumLaneElems; ++i) {
4079 int Idx = Mask[i+l];
4080 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4081 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 // For VSHUFPSY, the mask of the second half must be the same as the
4084 // first but with the appropriate offsets. This works in the same way as
4085 // VPERMILPS works with masks.
4086 if (!symetricMaskRequired || Idx < 0)
4088 if (MaskVal[i] < 0) {
4089 MaskVal[i] = Idx - l;
4092 if ((signed)(Idx - l) != MaskVal[i])
4100 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4101 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4102 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4103 if (!VT.is128BitVector())
4106 unsigned NumElems = VT.getVectorNumElements();
4111 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4112 return isUndefOrEqual(Mask[0], 6) &&
4113 isUndefOrEqual(Mask[1], 7) &&
4114 isUndefOrEqual(Mask[2], 2) &&
4115 isUndefOrEqual(Mask[3], 3);
4118 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4119 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4122 if (!VT.is128BitVector())
4125 unsigned NumElems = VT.getVectorNumElements();
4130 return isUndefOrEqual(Mask[0], 2) &&
4131 isUndefOrEqual(Mask[1], 3) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4136 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4137 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4138 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4139 if (!VT.is128BitVector())
4142 unsigned NumElems = VT.getVectorNumElements();
4144 if (NumElems != 2 && NumElems != 4)
4147 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i))
4158 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4160 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4173 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4180 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4182 /// i. e: If all but one element come from the same vector.
4183 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4184 // TODO: Deal with AVX's VINSERTPS
4185 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 unsigned CorrectPosV1 = 0;
4189 unsigned CorrectPosV2 = 0;
4190 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4191 if (Mask[i] == -1) {
4199 else if (Mask[i] == i + 4)
4203 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4204 // We have 3 elements (undefs count as elements from any vector) from one
4205 // vector, and one from another.
4212 // Some special combinations that can be optimized.
4215 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4216 SelectionDAG &DAG) {
4217 MVT VT = SVOp->getSimpleValueType(0);
4220 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 ArrayRef<int> Mask = SVOp->getMask();
4225 // These are the special masks that may be optimized.
4226 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4227 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4228 bool MatchEvenMask = true;
4229 bool MatchOddMask = true;
4230 for (int i=0; i<8; ++i) {
4231 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4232 MatchEvenMask = false;
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4234 MatchOddMask = false;
4237 if (!MatchEvenMask && !MatchOddMask)
4240 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4242 SDValue Op0 = SVOp->getOperand(0);
4243 SDValue Op1 = SVOp->getOperand(1);
4245 if (MatchEvenMask) {
4246 // Shift the second operand right to 32 bits.
4247 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4248 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 // Shift the first operand left to 32 bits.
4251 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4252 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4255 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4259 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4260 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4261 bool HasInt256, bool V2IsSplat = false) {
4263 assert(VT.getSizeInBits() >= 128 &&
4264 "Unsupported vector type for unpckl");
4266 unsigned NumElts = VT.getVectorNumElements();
4267 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4272 "Unsupported vector type for unpckh");
4274 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4275 unsigned NumLanes = VT.getSizeInBits()/128;
4276 unsigned NumLaneElts = NumElts/NumLanes;
4278 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4279 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4280 int BitI = Mask[l+i];
4281 int BitI1 = Mask[l+i+1];
4282 if (!isUndefOrEqual(BitI, j))
4285 if (!isUndefOrEqual(BitI1, NumElts))
4288 if (!isUndefOrEqual(BitI1, j + NumElts))
4297 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4298 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4299 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4300 bool HasInt256, bool V2IsSplat = false) {
4301 assert(VT.getSizeInBits() >= 128 &&
4302 "Unsupported vector type for unpckh");
4304 unsigned NumElts = VT.getVectorNumElements();
4305 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4306 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4310 "Unsupported vector type for unpckh");
4312 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4313 unsigned NumLanes = VT.getSizeInBits()/128;
4314 unsigned NumLaneElts = NumElts/NumLanes;
4316 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4317 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4318 int BitI = Mask[l+i];
4319 int BitI1 = Mask[l+i+1];
4320 if (!isUndefOrEqual(BitI, j))
4323 if (isUndefOrEqual(BitI1, NumElts))
4326 if (!isUndefOrEqual(BitI1, j+NumElts))
4334 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4335 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4338 unsigned NumElts = VT.getVectorNumElements();
4339 bool Is256BitVec = VT.is256BitVector();
4341 if (VT.is512BitVector())
4343 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4344 "Unsupported vector type for unpckh");
4346 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4347 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4351 // FIXME: Need a better way to get rid of this, there's no latency difference
4352 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4353 // the former later. We should also remove the "_undef" special mask.
4354 if (NumElts == 4 && Is256BitVec)
4357 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4358 // independently on 128-bit lanes.
4359 unsigned NumLanes = VT.getSizeInBits()/128;
4360 unsigned NumLaneElts = NumElts/NumLanes;
4362 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4363 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4364 int BitI = Mask[l+i];
4365 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4369 if (!isUndefOrEqual(BitI1, j))
4377 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4378 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4381 unsigned NumElts = VT.getVectorNumElements();
4383 if (VT.is512BitVector())
4386 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4387 "Unsupported vector type for unpckh");
4389 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4390 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4394 // independently on 128-bit lanes.
4395 unsigned NumLanes = VT.getSizeInBits()/128;
4396 unsigned NumLaneElts = NumElts/NumLanes;
4398 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4399 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4400 int BitI = Mask[l+i];
4401 int BitI1 = Mask[l+i+1];
4402 if (!isUndefOrEqual(BitI, j))
4404 if (!isUndefOrEqual(BitI1, j))
4411 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4412 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4413 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4414 if (!VT.is512BitVector())
4417 unsigned NumElts = VT.getVectorNumElements();
4418 unsigned HalfSize = NumElts/2;
4419 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4420 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4425 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4434 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4435 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4436 /// MOVSD, and MOVD, i.e. setting the lowest element.
4437 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4438 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 if (!VT.is128BitVector())
4443 unsigned NumElts = VT.getVectorNumElements();
4445 if (!isUndefOrEqual(Mask[0], NumElts))
4448 for (unsigned i = 1; i != NumElts; ++i)
4449 if (!isUndefOrEqual(Mask[i], i))
4455 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4456 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4459 /// The first half comes from the second half of V1 and the second half from the
4460 /// the second half of V2.
4461 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4462 if (!HasFp256 || !VT.is256BitVector())
4465 // The shuffle result is divided into half A and half B. In total the two
4466 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4467 // B must come from C, D, E or F.
4468 unsigned HalfSize = VT.getVectorNumElements()/2;
4469 bool MatchA = false, MatchB = false;
4471 // Check if A comes from one of C, D, E, F.
4472 for (unsigned Half = 0; Half != 4; ++Half) {
4473 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4479 // Check if B comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4487 return MatchA && MatchB;
4490 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4491 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4492 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4493 MVT VT = SVOp->getSimpleValueType(0);
4495 unsigned HalfSize = VT.getVectorNumElements()/2;
4497 unsigned FstHalf = 0, SndHalf = 0;
4498 for (unsigned i = 0; i < HalfSize; ++i) {
4499 if (SVOp->getMaskElt(i) > 0) {
4500 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4504 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4505 if (SVOp->getMaskElt(i) > 0) {
4506 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4511 return (FstHalf | (SndHalf << 4));
4514 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4515 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4520 unsigned NumElts = VT.getVectorNumElements();
4522 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4523 for (unsigned i = 0; i != NumElts; ++i) {
4526 Imm8 |= Mask[i] << (i*2);
4531 unsigned LaneSize = 4;
4532 SmallVector<int, 4> MaskVal(LaneSize, -1);
4534 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4535 for (unsigned i = 0; i != LaneSize; ++i) {
4536 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4540 if (MaskVal[i] < 0) {
4541 MaskVal[i] = Mask[i+l] - l;
4542 Imm8 |= MaskVal[i] << (i*2);
4545 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4552 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4554 /// Note that VPERMIL mask matching is different depending whether theunderlying
4555 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4556 /// to the same elements of the low, but to the higher half of the source.
4557 /// In VPERMILPD the two lanes could be shuffled independently of each other
4558 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4559 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4560 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4561 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 bool symetricMaskRequired = (EltSize == 32);
4564 unsigned NumElts = VT.getVectorNumElements();
4566 unsigned NumLanes = VT.getSizeInBits()/128;
4567 unsigned LaneSize = NumElts/NumLanes;
4568 // 2 or 4 elements in one lane
4570 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4571 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4572 for (unsigned i = 0; i != LaneSize; ++i) {
4573 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 if (symetricMaskRequired) {
4576 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4577 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4588 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4589 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4590 /// element of vector 2 and the other elements to come from vector 1 in order.
4591 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4592 bool V2IsSplat = false, bool V2IsUndef = false) {
4593 if (!VT.is128BitVector())
4596 unsigned NumOps = VT.getVectorNumElements();
4597 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 if (!isUndefOrEqual(Mask[0], 0))
4603 for (unsigned i = 1; i != NumOps; ++i)
4604 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4605 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4606 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4612 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4613 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4614 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4615 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4616 const X86Subtarget *Subtarget) {
4617 if (!Subtarget->hasSSE3())
4620 unsigned NumElems = VT.getVectorNumElements();
4622 if ((VT.is128BitVector() && NumElems != 4) ||
4623 (VT.is256BitVector() && NumElems != 8) ||
4624 (VT.is512BitVector() && NumElems != 16))
4627 // "i+1" is the value the indexed mask element must have
4628 for (unsigned i = 0; i != NumElems; i += 2)
4629 if (!isUndefOrEqual(Mask[i], i+1) ||
4630 !isUndefOrEqual(Mask[i+1], i+1))
4636 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4637 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4638 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4639 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4640 const X86Subtarget *Subtarget) {
4641 if (!Subtarget->hasSSE3())
4644 unsigned NumElems = VT.getVectorNumElements();
4646 if ((VT.is128BitVector() && NumElems != 4) ||
4647 (VT.is256BitVector() && NumElems != 8) ||
4648 (VT.is512BitVector() && NumElems != 16))
4651 // "i" is the value the indexed mask element must have
4652 for (unsigned i = 0; i != NumElems; i += 2)
4653 if (!isUndefOrEqual(Mask[i], i) ||
4654 !isUndefOrEqual(Mask[i+1], i))
4660 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4661 /// specifies a shuffle of elements that is suitable for input to 256-bit
4662 /// version of MOVDDUP.
4663 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4664 if (!HasFp256 || !VT.is256BitVector())
4667 unsigned NumElts = VT.getVectorNumElements();
4671 for (unsigned i = 0; i != NumElts/2; ++i)
4672 if (!isUndefOrEqual(Mask[i], 0))
4674 for (unsigned i = NumElts/2; i != NumElts; ++i)
4675 if (!isUndefOrEqual(Mask[i], NumElts/2))
4680 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4681 /// specifies a shuffle of elements that is suitable for input to 128-bit
4682 /// version of MOVDDUP.
4683 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4684 if (!VT.is128BitVector())
4687 unsigned e = VT.getVectorNumElements() / 2;
4688 for (unsigned i = 0; i != e; ++i)
4689 if (!isUndefOrEqual(Mask[i], i))
4691 for (unsigned i = 0; i != e; ++i)
4692 if (!isUndefOrEqual(Mask[e+i], i))
4697 /// isVEXTRACTIndex - Return true if the specified
4698 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4699 /// suitable for instruction that extract 128 or 256 bit vectors
4700 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4701 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4702 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 // The index should be aligned on a vecWidth-bit boundary.
4707 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4709 MVT VT = N->getSimpleValueType(0);
4710 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4711 bool Result = (Index * ElSize) % vecWidth == 0;
4716 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4717 /// operand specifies a subvector insert that is suitable for input to
4718 /// insertion of 128 or 256-bit subvectors
4719 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4720 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4721 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 // The index should be aligned on a vecWidth-bit boundary.
4725 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4734 bool X86::isVINSERT128Index(SDNode *N) {
4735 return isVINSERTIndex(N, 128);
4738 bool X86::isVINSERT256Index(SDNode *N) {
4739 return isVINSERTIndex(N, 256);
4742 bool X86::isVEXTRACT128Index(SDNode *N) {
4743 return isVEXTRACTIndex(N, 128);
4746 bool X86::isVEXTRACT256Index(SDNode *N) {
4747 return isVEXTRACTIndex(N, 256);
4750 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4751 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4752 /// Handles 128-bit and 256-bit.
4753 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4754 MVT VT = N->getSimpleValueType(0);
4756 assert((VT.getSizeInBits() >= 128) &&
4757 "Unsupported vector type for PSHUF/SHUFP");
4759 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4760 // independently on 128-bit lanes.
4761 unsigned NumElts = VT.getVectorNumElements();
4762 unsigned NumLanes = VT.getSizeInBits()/128;
4763 unsigned NumLaneElts = NumElts/NumLanes;
4765 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4766 "Only supports 2, 4 or 8 elements per lane");
4768 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 for (unsigned i = 0; i != NumElts; ++i) {
4771 int Elt = N->getMaskElt(i);
4772 if (Elt < 0) continue;
4773 Elt &= NumLaneElts - 1;
4774 unsigned ShAmt = (i << Shift) % 8;
4775 Mask |= Elt << ShAmt;
4781 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4782 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4783 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4784 MVT VT = N->getSimpleValueType(0);
4786 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4787 "Unsupported vector type for PSHUFHW");
4789 unsigned NumElts = VT.getVectorNumElements();
4792 for (unsigned l = 0; l != NumElts; l += 8) {
4793 // 8 nodes per lane, but we only care about the last 4.
4794 for (unsigned i = 0; i < 4; ++i) {
4795 int Elt = N->getMaskElt(l+i+4);
4796 if (Elt < 0) continue;
4797 Elt &= 0x3; // only 2-bits.
4798 Mask |= Elt << (i * 2);
4805 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4806 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4807 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4808 MVT VT = N->getSimpleValueType(0);
4810 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4811 "Unsupported vector type for PSHUFHW");
4813 unsigned NumElts = VT.getVectorNumElements();
4816 for (unsigned l = 0; l != NumElts; l += 8) {
4817 // 8 nodes per lane, but we only care about the first 4.
4818 for (unsigned i = 0; i < 4; ++i) {
4819 int Elt = N->getMaskElt(l+i);
4820 if (Elt < 0) continue;
4821 Elt &= 0x3; // only 2-bits
4822 Mask |= Elt << (i * 2);
4829 /// \brief Return the appropriate immediate to shuffle the specified
4830 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4831 /// VALIGN (if Interlane is true) instructions.
4832 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 MVT VT = SVOp->getSimpleValueType(0);
4835 unsigned EltSize = InterLane ? 1 :
4836 VT.getVectorElementType().getSizeInBits() >> 3;
4838 unsigned NumElts = VT.getVectorNumElements();
4839 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4840 unsigned NumLaneElts = NumElts/NumLanes;
4844 for (i = 0; i != NumElts; ++i) {
4845 Val = SVOp->getMaskElt(i);
4849 if (Val >= (int)NumElts)
4850 Val -= NumElts - NumLaneElts;
4852 assert(Val - i > 0 && "PALIGNR imm should be positive");
4853 return (Val - i) * EltSize;
4856 /// \brief Return the appropriate immediate to shuffle the specified
4857 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4858 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4859 return getShuffleAlignrImmediate(SVOp, false);
4862 /// \brief Return the appropriate immediate to shuffle the specified
4863 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4864 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4865 return getShuffleAlignrImmediate(SVOp, true);
4869 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4870 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4872 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4877 MVT VecVT = N->getOperand(0).getSimpleValueType();
4878 MVT ElVT = VecVT.getVectorElementType();
4880 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4881 return Index / NumElemsPerChunk;
4884 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4887 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4892 MVT VecVT = N->getSimpleValueType(0);
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4900 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4901 /// and VINSERTI128 instructions.
4902 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4903 return getExtractVEXTRACTImmediate(N, 128);
4906 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4908 /// and VINSERTI64x4 instructions.
4909 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 256);
4913 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4914 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4915 /// and VINSERTI128 instructions.
4916 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4917 return getInsertVINSERTImmediate(N, 128);
4920 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4922 /// and VINSERTI64x4 instructions.
4923 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 256);
4927 /// isZero - Returns true if Elt is a constant integer zero
4928 static bool isZero(SDValue V) {
4929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4930 return C && C->isNullValue();
4933 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 bool X86::isZeroNode(SDValue Elt) {
4938 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4939 return CFP->getValueAPF().isPosZero();
4943 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4944 /// match movhlps. The lower half elements should come from upper half of
4945 /// V1 (and in order), and the upper half elements should come from the upper
4946 /// half of V2 (and in order).
4947 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4948 if (!VT.is128BitVector())
4950 if (VT.getVectorNumElements() != 4)
4952 for (unsigned i = 0, e = 2; i != e; ++i)
4953 if (!isUndefOrEqual(Mask[i], i+2))
4955 for (unsigned i = 2; i != 4; ++i)
4956 if (!isUndefOrEqual(Mask[i], i+4))
4961 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4962 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4965 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 N = N->getOperand(0).getNode();
4968 if (!ISD::isNON_EXTLoad(N))
4971 *LD = cast<LoadSDNode>(N);
4975 // Test whether the given value is a vector value which will be legalized
4977 static bool WillBeConstantPoolLoad(SDNode *N) {
4978 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 // Check for any non-constant elements.
4982 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4983 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::ConstantFP:
4992 // Vectors of all-zeros and all-ones are materialized with special
4993 // instructions rather than being loaded.
4994 return !ISD::isBuildVectorAllZeros(N) &&
4995 !ISD::isBuildVectorAllOnes(N);
4998 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4999 /// match movlp{s|d}. The lower half elements should come from lower half of
5000 /// V1 (and in order), and the upper half elements should come from the upper
5001 /// half of V2 (and in order). And since V1 will become the source of the
5002 /// MOVLP, it must be either a vector load or a scalar load to vector.
5003 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5004 ArrayRef<int> Mask, MVT VT) {
5005 if (!VT.is128BitVector())
5008 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 // Is V2 is a vector load, don't do this transformation. We will try to use
5011 // load folding shufps op.
5012 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 unsigned NumElems = VT.getVectorNumElements();
5017 if (NumElems != 2 && NumElems != 4)
5019 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5020 if (!isUndefOrEqual(Mask[i], i))
5022 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5023 if (!isUndefOrEqual(Mask[i], i+NumElems))
5028 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5029 /// to an zero vector.
5030 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5031 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5032 SDValue V1 = N->getOperand(0);
5033 SDValue V2 = N->getOperand(1);
5034 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5035 for (unsigned i = 0; i != NumElems; ++i) {
5036 int Idx = N->getMaskElt(i);
5037 if (Idx >= (int)NumElems) {
5038 unsigned Opc = V2.getOpcode();
5039 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 if (Opc != ISD::BUILD_VECTOR ||
5042 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 } else if (Idx >= 0) {
5045 unsigned Opc = V1.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V1.getOperand(Idx)))
5056 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5059 SelectionDAG &DAG, SDLoc dl) {
5060 assert(VT.isVector() && "Expected a vector type");
5062 // Always build SSE zero vectors as <4 x i32> bitcasted
5063 // to their dest type. This ensures they get CSE'd.
5065 if (VT.is128BitVector()) { // SSE
5066 if (Subtarget->hasSSE2()) { // SSE2
5067 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5071 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 } else if (VT.is256BitVector()) { // AVX
5074 if (Subtarget->hasInt256()) { // AVX2
5075 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 // 256-bit logic and arithmetic instructions in AVX are all
5080 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5081 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 } else if (VT.is512BitVector()) { // AVX-512
5086 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5088 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5090 } else if (VT.getScalarType() == MVT::i1) {
5091 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5092 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5093 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5094 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 llvm_unreachable("Unexpected vector type");
5098 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 /// getOnesVector - Returns a vector of specified type with all bits set.
5102 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5103 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5104 /// Then bitcast to their original type, ensuring they get CSE'd.
5105 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 assert(VT.isVector() && "Expected a vector type");
5109 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 if (VT.is256BitVector()) {
5112 if (HasInt256) { // AVX2
5113 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5117 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 } else if (VT.is128BitVector()) {
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 llvm_unreachable("Unexpected vector type");
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5128 /// that point to V2 points to its first element.
5129 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5130 for (unsigned i = 0; i != NumElems; ++i) {
5131 if (Mask[i] > (int)NumElems) {
5137 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5138 /// operation of specified width.
5139 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 unsigned NumElems = VT.getVectorNumElements();
5142 SmallVector<int, 8> Mask;
5143 Mask.push_back(NumElems);
5144 for (unsigned i = 1; i != NumElems; ++i)
5146 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5150 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 unsigned NumElems = VT.getVectorNumElements();
5153 SmallVector<int, 8> Mask;
5154 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i + NumElems);
5158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5162 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5167 Mask.push_back(i + Half);
5168 Mask.push_back(i + NumElems + Half);
5170 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5174 // a generic shuffle instruction because the target has no such instructions.
5175 // Generate shuffles which repeat i16 and i8 several times until they can be
5176 // represented by v4f32 and then be manipulated by target suported shuffles.
5177 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5178 MVT VT = V.getSimpleValueType();
5179 int NumElems = VT.getVectorNumElements();
5182 while (NumElems > 4) {
5183 if (EltNo < NumElems/2) {
5184 V = getUnpackl(DAG, dl, VT, V, V);
5186 V = getUnpackh(DAG, dl, VT, V, V);
5187 EltNo -= NumElems/2;
5194 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5195 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5196 MVT VT = V.getSimpleValueType();
5199 if (VT.is128BitVector()) {
5200 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5201 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5202 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 } else if (VT.is256BitVector()) {
5205 // To use VPERMILPS to splat scalars, the second half of indicies must
5206 // refer to the higher part, which is a duplication of the lower one,
5207 // because VPERMILPS can only handle in-lane permutations.
5208 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5209 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5211 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5212 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 llvm_unreachable("Vector size not supported");
5217 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5221 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5222 MVT SrcVT = SV->getSimpleValueType(0);
5223 SDValue V1 = SV->getOperand(0);
5226 int EltNo = SV->getSplatIndex();
5227 int NumElems = SrcVT.getVectorNumElements();
5228 bool Is256BitVec = SrcVT.is256BitVector();
5230 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5231 "Unknown how to promote splat for type");
5233 // Extract the 128-bit part containing the splat element and update
5234 // the splat element index when it refers to the higher register.
5236 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5237 if (EltNo >= NumElems/2)
5238 EltNo -= NumElems/2;
5241 // All i16 and i8 vector types can't be used directly by a generic shuffle
5242 // instruction because the target has no such instruction. Generate shuffles
5243 // which repeat i16 and i8 several times until they fit in i32, and then can
5244 // be manipulated by target suported shuffles.
5245 MVT EltVT = SrcVT.getVectorElementType();
5246 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5247 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5249 // Recreate the 256-bit vector and place the same 128-bit vector
5250 // into the low and high part. This is necessary because we want
5251 // to use VPERM* to shuffle the vectors
5253 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 return getLegalSplat(DAG, V1, EltNo);
5259 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5260 /// vector of zero or undef vector. This produces a shuffle where the low
5261 /// element of V2 is swizzled into the zero/undef vector, landing at element
5262 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5263 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 const X86Subtarget *Subtarget,
5266 SelectionDAG &DAG) {
5267 MVT VT = V2.getSimpleValueType();
5269 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5270 unsigned NumElems = VT.getVectorNumElements();
5271 SmallVector<int, 16> MaskVec;
5272 for (unsigned i = 0; i != NumElems; ++i)
5273 // If this is the insertion idx, put the low elt of V2 here.
5274 MaskVec.push_back(i == Idx ? NumElems : i);
5275 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5279 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5280 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5281 /// shuffles which use a single input multiple times, and in those cases it will
5282 /// adjust the mask to only have indices within that single input.
5283 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5284 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5285 unsigned NumElems = VT.getVectorNumElements();
5289 bool IsFakeUnary = false;
5290 switch(N->getOpcode()) {
5292 ImmN = N->getOperand(N->getNumOperands()-1);
5293 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5294 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5296 case X86ISD::UNPCKH:
5297 DecodeUNPCKHMask(VT, Mask);
5298 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 case X86ISD::UNPCKL:
5301 DecodeUNPCKLMask(VT, Mask);
5302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 case X86ISD::MOVHLPS:
5305 DecodeMOVHLPSMask(NumElems, Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::MOVLHPS:
5309 DecodeMOVLHPSMask(NumElems, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::PALIGNR:
5313 ImmN = N->getOperand(N->getNumOperands()-1);
5314 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 case X86ISD::PSHUFD:
5317 case X86ISD::VPERMILP:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFHW:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFLW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFB: {
5334 SDValue MaskNode = N->getOperand(1);
5335 while (MaskNode->getOpcode() == ISD::BITCAST)
5336 MaskNode = MaskNode->getOperand(0);
5338 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5339 // If we have a build-vector, then things are easy.
5340 EVT VT = MaskNode.getValueType();
5341 assert(VT.isVector() &&
5342 "Can't produce a non-vector with a build_vector!");
5343 if (!VT.isInteger())
5346 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5348 SmallVector<uint64_t, 32> RawMask;
5349 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5350 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5353 APInt MaskElement = CN->getAPIntValue();
5355 // We now have to decode the element which could be any integer size and
5356 // extract each byte of it.
5357 for (int j = 0; j < NumBytesPerElement; ++j) {
5358 // Note that this is x86 and so always little endian: the low byte is
5359 // the first byte of the mask.
5360 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5361 MaskElement = MaskElement.lshr(8);
5364 DecodePSHUFBMask(RawMask, Mask);
5368 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5372 SDValue Ptr = MaskLoad->getBasePtr();
5373 if (Ptr->getOpcode() == X86ISD::Wrapper)
5374 Ptr = Ptr->getOperand(0);
5376 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5377 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5380 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5381 // FIXME: Support AVX-512 here.
5382 if (!C->getType()->isVectorTy() ||
5383 (C->getNumElements() != 16 && C->getNumElements() != 32))
5386 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5387 DecodePSHUFBMask(C, Mask);
5393 case X86ISD::VPERMI:
5394 ImmN = N->getOperand(N->getNumOperands()-1);
5395 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5399 case X86ISD::MOVSD: {
5400 // The index 0 always comes from the first element of the second source,
5401 // this is why MOVSS and MOVSD are used in the first place. The other
5402 // elements come from the other positions of the first source vector
5403 Mask.push_back(NumElems);
5404 for (unsigned i = 1; i != NumElems; ++i) {
5409 case X86ISD::VPERM2X128:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5412 if (Mask.empty()) return false;
5414 case X86ISD::MOVSLDUP:
5415 DecodeMOVSLDUPMask(VT, Mask);
5417 case X86ISD::MOVSHDUP:
5418 DecodeMOVSHDUPMask(VT, Mask);
5420 case X86ISD::MOVDDUP:
5421 case X86ISD::MOVLHPD:
5422 case X86ISD::MOVLPD:
5423 case X86ISD::MOVLPS:
5424 // Not yet implemented
5426 default: llvm_unreachable("unknown target shuffle node");
5429 // If we have a fake unary shuffle, the shuffle mask is spread across two
5430 // inputs that are actually the same node. Re-map the mask to always point
5431 // into the first input.
5434 if (M >= (int)Mask.size())
5440 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5441 /// element of the result of the vector shuffle.
5442 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5445 return SDValue(); // Limit search depth.
5447 SDValue V = SDValue(N, 0);
5448 EVT VT = V.getValueType();
5449 unsigned Opcode = V.getOpcode();
5451 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5452 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5453 int Elt = SV->getMaskElt(Index);
5456 return DAG.getUNDEF(VT.getVectorElementType());
5458 unsigned NumElems = VT.getVectorNumElements();
5459 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5460 : SV->getOperand(1);
5461 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5464 // Recurse into target specific vector shuffles to find scalars.
5465 if (isTargetShuffle(Opcode)) {
5466 MVT ShufVT = V.getSimpleValueType();
5467 unsigned NumElems = ShufVT.getVectorNumElements();
5468 SmallVector<int, 16> ShuffleMask;
5471 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5474 int Elt = ShuffleMask[Index];
5476 return DAG.getUNDEF(ShufVT.getVectorElementType());
5478 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5480 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5484 // Actual nodes that may contain scalar elements
5485 if (Opcode == ISD::BITCAST) {
5486 V = V.getOperand(0);
5487 EVT SrcVT = V.getValueType();
5488 unsigned NumElems = VT.getVectorNumElements();
5490 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5494 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5495 return (Index == 0) ? V.getOperand(0)
5496 : DAG.getUNDEF(VT.getVectorElementType());
5498 if (V.getOpcode() == ISD::BUILD_VECTOR)
5499 return V.getOperand(Index);
5504 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5505 /// shuffle operation which come from a consecutively from a zero. The
5506 /// search can start in two different directions, from left or right.
5507 /// We count undefs as zeros until PreferredNum is reached.
5508 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5509 unsigned NumElems, bool ZerosFromLeft,
5511 unsigned PreferredNum = -1U) {
5512 unsigned NumZeros = 0;
5513 for (unsigned i = 0; i != NumElems; ++i) {
5514 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5515 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5519 if (X86::isZeroNode(Elt))
5521 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5522 NumZeros = std::min(NumZeros + 1, PreferredNum);
5530 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5531 /// correspond consecutively to elements from one of the vector operands,
5532 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5534 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5535 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5536 unsigned NumElems, unsigned &OpNum) {
5537 bool SeenV1 = false;
5538 bool SeenV2 = false;
5540 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5541 int Idx = SVOp->getMaskElt(i);
5542 // Ignore undef indicies
5546 if (Idx < (int)NumElems)
5551 // Only accept consecutive elements from the same vector
5552 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5556 OpNum = SeenV1 ? 0 : 1;
5560 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5561 /// logical left shift of a vector.
5562 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5563 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5565 SVOp->getSimpleValueType(0).getVectorNumElements();
5566 unsigned NumZeros = getNumOfConsecutiveZeros(
5567 SVOp, NumElems, false /* check zeros from right */, DAG,
5568 SVOp->getMaskElt(0));
5574 // Considering the elements in the mask that are not consecutive zeros,
5575 // check if they consecutively come from only one of the source vectors.
5577 // V1 = {X, A, B, C} 0
5579 // vector_shuffle V1, V2 <1, 2, 3, X>
5581 if (!isShuffleMaskConsecutive(SVOp,
5582 0, // Mask Start Index
5583 NumElems-NumZeros, // Mask End Index(exclusive)
5584 NumZeros, // Where to start looking in the src vector
5585 NumElems, // Number of elements in vector
5586 OpSrc)) // Which source operand ?
5591 ShVal = SVOp->getOperand(OpSrc);
5595 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5596 /// logical left shift of a vector.
5597 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5598 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5600 SVOp->getSimpleValueType(0).getVectorNumElements();
5601 unsigned NumZeros = getNumOfConsecutiveZeros(
5602 SVOp, NumElems, true /* check zeros from left */, DAG,
5603 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5609 // Considering the elements in the mask that are not consecutive zeros,
5610 // check if they consecutively come from only one of the source vectors.
5612 // 0 { A, B, X, X } = V2
5614 // vector_shuffle V1, V2 <X, X, 4, 5>
5616 if (!isShuffleMaskConsecutive(SVOp,
5617 NumZeros, // Mask Start Index
5618 NumElems, // Mask End Index(exclusive)
5619 0, // Where to start looking in the src vector
5620 NumElems, // Number of elements in vector
5621 OpSrc)) // Which source operand ?
5626 ShVal = SVOp->getOperand(OpSrc);
5630 /// isVectorShift - Returns true if the shuffle can be implemented as a
5631 /// logical left or right shift of a vector.
5632 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5633 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5634 // Although the logic below support any bitwidth size, there are no
5635 // shift instructions which handle more than 128-bit vectors.
5636 if (!SVOp->getSimpleValueType(0).is128BitVector())
5639 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5640 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5646 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5648 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5649 unsigned NumNonZero, unsigned NumZero,
5651 const X86Subtarget* Subtarget,
5652 const TargetLowering &TLI) {
5659 for (unsigned i = 0; i < 16; ++i) {
5660 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5661 if (ThisIsNonZero && First) {
5663 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5665 V = DAG.getUNDEF(MVT::v8i16);
5670 SDValue ThisElt, LastElt;
5671 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5672 if (LastIsNonZero) {
5673 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5674 MVT::i16, Op.getOperand(i-1));
5676 if (ThisIsNonZero) {
5677 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5678 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5679 ThisElt, DAG.getConstant(8, MVT::i8));
5681 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5685 if (ThisElt.getNode())
5686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5687 DAG.getIntPtrConstant(i/2));
5691 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5694 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5696 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5697 unsigned NumNonZero, unsigned NumZero,
5699 const X86Subtarget* Subtarget,
5700 const TargetLowering &TLI) {
5707 for (unsigned i = 0; i < 8; ++i) {
5708 bool isNonZero = (NonZeros & (1 << i)) != 0;
5712 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5714 V = DAG.getUNDEF(MVT::v8i16);
5717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5718 MVT::v8i16, V, Op.getOperand(i),
5719 DAG.getIntPtrConstant(i));
5726 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5727 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5728 unsigned NonZeros, unsigned NumNonZero,
5729 unsigned NumZero, SelectionDAG &DAG,
5730 const X86Subtarget *Subtarget,
5731 const TargetLowering &TLI) {
5732 // We know there's at least one non-zero element
5733 unsigned FirstNonZeroIdx = 0;
5734 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5735 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5736 X86::isZeroNode(FirstNonZero)) {
5738 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5741 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5742 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5745 SDValue V = FirstNonZero.getOperand(0);
5746 MVT VVT = V.getSimpleValueType();
5747 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5750 unsigned FirstNonZeroDst =
5751 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5752 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5753 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5754 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5756 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5757 SDValue Elem = Op.getOperand(Idx);
5758 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5761 // TODO: What else can be here? Deal with it.
5762 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5765 // TODO: Some optimizations are still possible here
5766 // ex: Getting one element from a vector, and the rest from another.
5767 if (Elem.getOperand(0) != V)
5770 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5773 else if (IncorrectIdx == -1U) {
5777 // There was already one element with an incorrect index.
5778 // We can't optimize this case to an insertps.
5782 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5784 EVT VT = Op.getSimpleValueType();
5785 unsigned ElementMoveMask = 0;
5786 if (IncorrectIdx == -1U)
5787 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5789 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5791 SDValue InsertpsMask =
5792 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5793 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5799 /// getVShift - Return a vector logical shift node.
5801 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5802 unsigned NumBits, SelectionDAG &DAG,
5803 const TargetLowering &TLI, SDLoc dl) {
5804 assert(VT.is128BitVector() && "Unknown type for VShift");
5805 EVT ShVT = MVT::v2i64;
5806 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5807 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5808 return DAG.getNode(ISD::BITCAST, dl, VT,
5809 DAG.getNode(Opc, dl, ShVT, SrcOp,
5810 DAG.getConstant(NumBits,
5811 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5815 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5817 // Check if the scalar load can be widened into a vector load. And if
5818 // the address is "base + cst" see if the cst can be "absorbed" into
5819 // the shuffle mask.
5820 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5821 SDValue Ptr = LD->getBasePtr();
5822 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5824 EVT PVT = LD->getValueType(0);
5825 if (PVT != MVT::i32 && PVT != MVT::f32)
5830 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5831 FI = FINode->getIndex();
5833 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5834 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5835 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5836 Offset = Ptr.getConstantOperandVal(1);
5837 Ptr = Ptr.getOperand(0);
5842 // FIXME: 256-bit vector instructions don't require a strict alignment,
5843 // improve this code to support it better.
5844 unsigned RequiredAlign = VT.getSizeInBits()/8;
5845 SDValue Chain = LD->getChain();
5846 // Make sure the stack object alignment is at least 16 or 32.
5847 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5848 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5849 if (MFI->isFixedObjectIndex(FI)) {
5850 // Can't change the alignment. FIXME: It's possible to compute
5851 // the exact stack offset and reference FI + adjust offset instead.
5852 // If someone *really* cares about this. That's the way to implement it.
5855 MFI->setObjectAlignment(FI, RequiredAlign);
5859 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5860 // Ptr + (Offset & ~15).
5863 if ((Offset % RequiredAlign) & 3)
5865 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5867 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5868 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5870 int EltNo = (Offset - StartOffset) >> 2;
5871 unsigned NumElems = VT.getVectorNumElements();
5873 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5874 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5875 LD->getPointerInfo().getWithOffset(StartOffset),
5876 false, false, false, 0);
5878 SmallVector<int, 8> Mask;
5879 for (unsigned i = 0; i != NumElems; ++i)
5880 Mask.push_back(EltNo);
5882 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5888 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5889 /// vector of type 'VT', see if the elements can be replaced by a single large
5890 /// load which has the same value as a build_vector whose operands are 'elts'.
5892 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5894 /// FIXME: we'd also like to handle the case where the last elements are zero
5895 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5896 /// There's even a handy isZeroNode for that purpose.
5897 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5898 SDLoc &DL, SelectionDAG &DAG,
5899 bool isAfterLegalize) {
5900 EVT EltVT = VT.getVectorElementType();
5901 unsigned NumElems = Elts.size();
5903 LoadSDNode *LDBase = nullptr;
5904 unsigned LastLoadedElt = -1U;
5906 // For each element in the initializer, see if we've found a load or an undef.
5907 // If we don't find an initial load element, or later load elements are
5908 // non-consecutive, bail out.
5909 for (unsigned i = 0; i < NumElems; ++i) {
5910 SDValue Elt = Elts[i];
5912 if (!Elt.getNode() ||
5913 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5916 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5918 LDBase = cast<LoadSDNode>(Elt.getNode());
5922 if (Elt.getOpcode() == ISD::UNDEF)
5925 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5926 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5931 // If we have found an entire vector of loads and undefs, then return a large
5932 // load of the entire vector width starting at the base pointer. If we found
5933 // consecutive loads for the low half, generate a vzext_load node.
5934 if (LastLoadedElt == NumElems - 1) {
5936 if (isAfterLegalize &&
5937 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5940 SDValue NewLd = SDValue();
5942 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5943 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5944 LDBase->getPointerInfo(),
5945 LDBase->isVolatile(), LDBase->isNonTemporal(),
5946 LDBase->isInvariant(), 0);
5947 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5948 LDBase->getPointerInfo(),
5949 LDBase->isVolatile(), LDBase->isNonTemporal(),
5950 LDBase->isInvariant(), LDBase->getAlignment());
5952 if (LDBase->hasAnyUseOfValue(1)) {
5953 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5955 SDValue(NewLd.getNode(), 1));
5956 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5957 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5958 SDValue(NewLd.getNode(), 1));
5963 if (NumElems == 4 && LastLoadedElt == 1 &&
5964 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5965 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5966 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5968 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5969 LDBase->getPointerInfo(),
5970 LDBase->getAlignment(),
5971 false/*isVolatile*/, true/*ReadMem*/,
5974 // Make sure the newly-created LOAD is in the same position as LDBase in
5975 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5976 // update uses of LDBase's output chain to use the TokenFactor.
5977 if (LDBase->hasAnyUseOfValue(1)) {
5978 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5979 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5980 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5981 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5982 SDValue(ResNode.getNode(), 1));
5985 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5990 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5991 /// to generate a splat value for the following cases:
5992 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5993 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5994 /// a scalar load, or a constant.
5995 /// The VBROADCAST node is returned when a pattern is found,
5996 /// or SDValue() otherwise.
5997 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5998 SelectionDAG &DAG) {
5999 if (!Subtarget->hasFp256())
6002 MVT VT = Op.getSimpleValueType();
6005 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6006 "Unsupported vector type for broadcast.");
6011 switch (Op.getOpcode()) {
6013 // Unknown pattern found.
6016 case ISD::BUILD_VECTOR: {
6017 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6018 BitVector UndefElements;
6019 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6021 // We need a splat of a single value to use broadcast, and it doesn't
6022 // make any sense if the value is only in one element of the vector.
6023 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6027 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6028 Ld.getOpcode() == ISD::ConstantFP);
6030 // Make sure that all of the users of a non-constant load are from the
6031 // BUILD_VECTOR node.
6032 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6037 case ISD::VECTOR_SHUFFLE: {
6038 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6040 // Shuffles must have a splat mask where the first element is
6042 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6045 SDValue Sc = Op.getOperand(0);
6046 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6047 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6049 if (!Subtarget->hasInt256())
6052 // Use the register form of the broadcast instruction available on AVX2.
6053 if (VT.getSizeInBits() >= 256)
6054 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6055 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6058 Ld = Sc.getOperand(0);
6059 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6060 Ld.getOpcode() == ISD::ConstantFP);
6062 // The scalar_to_vector node and the suspected
6063 // load node must have exactly one user.
6064 // Constants may have multiple users.
6066 // AVX-512 has register version of the broadcast
6067 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6068 Ld.getValueType().getSizeInBits() >= 32;
6069 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6076 bool IsGE256 = (VT.getSizeInBits() >= 256);
6078 // Handle the broadcasting a single constant scalar from the constant pool
6079 // into a vector. On Sandybridge it is still better to load a constant vector
6080 // from the constant pool and not to broadcast it from a scalar.
6081 if (ConstSplatVal && Subtarget->hasInt256()) {
6082 EVT CVT = Ld.getValueType();
6083 assert(!CVT.isVector() && "Must not broadcast a vector type");
6084 unsigned ScalarSize = CVT.getSizeInBits();
6086 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
6087 const Constant *C = nullptr;
6088 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6089 C = CI->getConstantIntValue();
6090 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6091 C = CF->getConstantFPValue();
6093 assert(C && "Invalid constant type");
6095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6096 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6097 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6098 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6099 MachinePointerInfo::getConstantPool(),
6100 false, false, false, Alignment);
6102 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6106 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6107 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6109 // Handle AVX2 in-register broadcasts.
6110 if (!IsLoad && Subtarget->hasInt256() &&
6111 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6112 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6114 // The scalar source must be a normal load.
6118 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6119 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6121 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6122 // double since there is no vbroadcastsd xmm
6123 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6124 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6125 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6128 // Unsupported broadcast.
6132 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6133 /// underlying vector and index.
6135 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6137 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6139 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6140 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6143 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6145 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6147 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6148 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6151 // In this case the vector is the extract_subvector expression and the index
6152 // is 2, as specified by the shuffle.
6153 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6154 SDValue ShuffleVec = SVOp->getOperand(0);
6155 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6156 assert(ShuffleVecVT.getVectorElementType() ==
6157 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6159 int ShuffleIdx = SVOp->getMaskElt(Idx);
6160 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6161 ExtractedFromVec = ShuffleVec;
6167 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6168 MVT VT = Op.getSimpleValueType();
6170 // Skip if insert_vec_elt is not supported.
6171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6172 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6176 unsigned NumElems = Op.getNumOperands();
6180 SmallVector<unsigned, 4> InsertIndices;
6181 SmallVector<int, 8> Mask(NumElems, -1);
6183 for (unsigned i = 0; i != NumElems; ++i) {
6184 unsigned Opc = Op.getOperand(i).getOpcode();
6186 if (Opc == ISD::UNDEF)
6189 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6190 // Quit if more than 1 elements need inserting.
6191 if (InsertIndices.size() > 1)
6194 InsertIndices.push_back(i);
6198 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6199 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6200 // Quit if non-constant index.
6201 if (!isa<ConstantSDNode>(ExtIdx))
6203 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6205 // Quit if extracted from vector of different type.
6206 if (ExtractedFromVec.getValueType() != VT)
6209 if (!VecIn1.getNode())
6210 VecIn1 = ExtractedFromVec;
6211 else if (VecIn1 != ExtractedFromVec) {
6212 if (!VecIn2.getNode())
6213 VecIn2 = ExtractedFromVec;
6214 else if (VecIn2 != ExtractedFromVec)
6215 // Quit if more than 2 vectors to shuffle
6219 if (ExtractedFromVec == VecIn1)
6221 else if (ExtractedFromVec == VecIn2)
6222 Mask[i] = Idx + NumElems;
6225 if (!VecIn1.getNode())
6228 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6229 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6230 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6231 unsigned Idx = InsertIndices[i];
6232 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6233 DAG.getIntPtrConstant(Idx));
6239 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6241 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6243 MVT VT = Op.getSimpleValueType();
6244 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6245 "Unexpected type in LowerBUILD_VECTORvXi1!");
6248 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6249 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6250 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6251 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6254 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6255 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6256 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6257 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6260 bool AllContants = true;
6261 uint64_t Immediate = 0;
6262 int NonConstIdx = -1;
6263 bool IsSplat = true;
6264 unsigned NumNonConsts = 0;
6265 unsigned NumConsts = 0;
6266 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6267 SDValue In = Op.getOperand(idx);
6268 if (In.getOpcode() == ISD::UNDEF)
6270 if (!isa<ConstantSDNode>(In)) {
6271 AllContants = false;
6277 if (cast<ConstantSDNode>(In)->getZExtValue())
6278 Immediate |= (1ULL << idx);
6280 if (In != Op.getOperand(0))
6285 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6286 DAG.getConstant(Immediate, MVT::i16));
6287 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6288 DAG.getIntPtrConstant(0));
6291 if (NumNonConsts == 1 && NonConstIdx != 0) {
6294 SDValue VecAsImm = DAG.getConstant(Immediate,
6295 MVT::getIntegerVT(VT.getSizeInBits()));
6296 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6299 DstVec = DAG.getUNDEF(VT);
6300 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6301 Op.getOperand(NonConstIdx),
6302 DAG.getIntPtrConstant(NonConstIdx));
6304 if (!IsSplat && (NonConstIdx != 0))
6305 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6306 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6309 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6310 DAG.getConstant(-1, SelectVT),
6311 DAG.getConstant(0, SelectVT));
6313 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6314 DAG.getConstant((Immediate | 1), SelectVT),
6315 DAG.getConstant(Immediate, SelectVT));
6316 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6319 /// \brief Return true if \p N implements a horizontal binop and return the
6320 /// operands for the horizontal binop into V0 and V1.
6322 /// This is a helper function of PerformBUILD_VECTORCombine.
6323 /// This function checks that the build_vector \p N in input implements a
6324 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6325 /// operation to match.
6326 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6327 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6328 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6331 /// This function only analyzes elements of \p N whose indices are
6332 /// in range [BaseIdx, LastIdx).
6333 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6335 unsigned BaseIdx, unsigned LastIdx,
6336 SDValue &V0, SDValue &V1) {
6337 EVT VT = N->getValueType(0);
6339 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6340 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6341 "Invalid Vector in input!");
6343 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6344 bool CanFold = true;
6345 unsigned ExpectedVExtractIdx = BaseIdx;
6346 unsigned NumElts = LastIdx - BaseIdx;
6347 V0 = DAG.getUNDEF(VT);
6348 V1 = DAG.getUNDEF(VT);
6350 // Check if N implements a horizontal binop.
6351 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6352 SDValue Op = N->getOperand(i + BaseIdx);
6355 if (Op->getOpcode() == ISD::UNDEF) {
6356 // Update the expected vector extract index.
6357 if (i * 2 == NumElts)
6358 ExpectedVExtractIdx = BaseIdx;
6359 ExpectedVExtractIdx += 2;
6363 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6368 SDValue Op0 = Op.getOperand(0);
6369 SDValue Op1 = Op.getOperand(1);
6371 // Try to match the following pattern:
6372 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6373 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6374 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6375 Op0.getOperand(0) == Op1.getOperand(0) &&
6376 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6377 isa<ConstantSDNode>(Op1.getOperand(1)));
6381 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6382 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6384 if (i * 2 < NumElts) {
6385 if (V0.getOpcode() == ISD::UNDEF)
6386 V0 = Op0.getOperand(0);
6388 if (V1.getOpcode() == ISD::UNDEF)
6389 V1 = Op0.getOperand(0);
6390 if (i * 2 == NumElts)
6391 ExpectedVExtractIdx = BaseIdx;
6394 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6395 if (I0 == ExpectedVExtractIdx)
6396 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6397 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6398 // Try to match the following dag sequence:
6399 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6400 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6404 ExpectedVExtractIdx += 2;
6410 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6411 /// a concat_vector.
6413 /// This is a helper function of PerformBUILD_VECTORCombine.
6414 /// This function expects two 256-bit vectors called V0 and V1.
6415 /// At first, each vector is split into two separate 128-bit vectors.
6416 /// Then, the resulting 128-bit vectors are used to implement two
6417 /// horizontal binary operations.
6419 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6421 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6422 /// the two new horizontal binop.
6423 /// When Mode is set, the first horizontal binop dag node would take as input
6424 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6425 /// horizontal binop dag node would take as input the lower 128-bit of V1
6426 /// and the upper 128-bit of V1.
6428 /// HADD V0_LO, V0_HI
6429 /// HADD V1_LO, V1_HI
6431 /// Otherwise, the first horizontal binop dag node takes as input the lower
6432 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6433 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6435 /// HADD V0_LO, V1_LO
6436 /// HADD V0_HI, V1_HI
6438 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6439 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6440 /// the upper 128-bits of the result.
6441 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6442 SDLoc DL, SelectionDAG &DAG,
6443 unsigned X86Opcode, bool Mode,
6444 bool isUndefLO, bool isUndefHI) {
6445 EVT VT = V0.getValueType();
6446 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6447 "Invalid nodes in input!");
6449 unsigned NumElts = VT.getVectorNumElements();
6450 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6451 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6452 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6453 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6454 EVT NewVT = V0_LO.getValueType();
6456 SDValue LO = DAG.getUNDEF(NewVT);
6457 SDValue HI = DAG.getUNDEF(NewVT);
6460 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6461 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6462 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6463 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6464 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6466 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6467 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6468 V1_LO->getOpcode() != ISD::UNDEF))
6469 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6471 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6472 V1_HI->getOpcode() != ISD::UNDEF))
6473 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6476 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6479 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6480 /// sequence of 'vadd + vsub + blendi'.
6481 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6482 const X86Subtarget *Subtarget) {
6484 EVT VT = BV->getValueType(0);
6485 unsigned NumElts = VT.getVectorNumElements();
6486 SDValue InVec0 = DAG.getUNDEF(VT);
6487 SDValue InVec1 = DAG.getUNDEF(VT);
6489 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6490 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6492 // Odd-numbered elements in the input build vector are obtained from
6493 // adding two integer/float elements.
6494 // Even-numbered elements in the input build vector are obtained from
6495 // subtracting two integer/float elements.
6496 unsigned ExpectedOpcode = ISD::FSUB;
6497 unsigned NextExpectedOpcode = ISD::FADD;
6498 bool AddFound = false;
6499 bool SubFound = false;
6501 for (unsigned i = 0, e = NumElts; i != e; i++) {
6502 SDValue Op = BV->getOperand(i);
6504 // Skip 'undef' values.
6505 unsigned Opcode = Op.getOpcode();
6506 if (Opcode == ISD::UNDEF) {
6507 std::swap(ExpectedOpcode, NextExpectedOpcode);
6511 // Early exit if we found an unexpected opcode.
6512 if (Opcode != ExpectedOpcode)
6515 SDValue Op0 = Op.getOperand(0);
6516 SDValue Op1 = Op.getOperand(1);
6518 // Try to match the following pattern:
6519 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6520 // Early exit if we cannot match that sequence.
6521 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6522 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6523 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6524 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6525 Op0.getOperand(1) != Op1.getOperand(1))
6528 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6532 // We found a valid add/sub node. Update the information accordingly.
6538 // Update InVec0 and InVec1.
6539 if (InVec0.getOpcode() == ISD::UNDEF)
6540 InVec0 = Op0.getOperand(0);
6541 if (InVec1.getOpcode() == ISD::UNDEF)
6542 InVec1 = Op1.getOperand(0);
6544 // Make sure that operands in input to each add/sub node always
6545 // come from a same pair of vectors.
6546 if (InVec0 != Op0.getOperand(0)) {
6547 if (ExpectedOpcode == ISD::FSUB)
6550 // FADD is commutable. Try to commute the operands
6551 // and then test again.
6552 std::swap(Op0, Op1);
6553 if (InVec0 != Op0.getOperand(0))
6557 if (InVec1 != Op1.getOperand(0))
6560 // Update the pair of expected opcodes.
6561 std::swap(ExpectedOpcode, NextExpectedOpcode);
6564 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6565 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6566 InVec1.getOpcode() != ISD::UNDEF)
6567 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6572 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6573 const X86Subtarget *Subtarget) {
6575 EVT VT = N->getValueType(0);
6576 unsigned NumElts = VT.getVectorNumElements();
6577 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6578 SDValue InVec0, InVec1;
6580 // Try to match an ADDSUB.
6581 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6582 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6583 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6584 if (Value.getNode())
6588 // Try to match horizontal ADD/SUB.
6589 unsigned NumUndefsLO = 0;
6590 unsigned NumUndefsHI = 0;
6591 unsigned Half = NumElts/2;
6593 // Count the number of UNDEF operands in the build_vector in input.
6594 for (unsigned i = 0, e = Half; i != e; ++i)
6595 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6598 for (unsigned i = Half, e = NumElts; i != e; ++i)
6599 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6602 // Early exit if this is either a build_vector of all UNDEFs or all the
6603 // operands but one are UNDEF.
6604 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6607 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6608 // Try to match an SSE3 float HADD/HSUB.
6609 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6610 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6612 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6613 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6614 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6615 // Try to match an SSSE3 integer HADD/HSUB.
6616 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6617 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6619 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6620 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6623 if (!Subtarget->hasAVX())
6626 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6627 // Try to match an AVX horizontal add/sub of packed single/double
6628 // precision floating point values from 256-bit vectors.
6629 SDValue InVec2, InVec3;
6630 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6631 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6632 ((InVec0.getOpcode() == ISD::UNDEF ||
6633 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6634 ((InVec1.getOpcode() == ISD::UNDEF ||
6635 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6636 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6638 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6639 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6640 ((InVec0.getOpcode() == ISD::UNDEF ||
6641 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6642 ((InVec1.getOpcode() == ISD::UNDEF ||
6643 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6644 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6645 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6646 // Try to match an AVX2 horizontal add/sub of signed integers.
6647 SDValue InVec2, InVec3;
6649 bool CanFold = true;
6651 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6652 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6653 ((InVec0.getOpcode() == ISD::UNDEF ||
6654 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6655 ((InVec1.getOpcode() == ISD::UNDEF ||
6656 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6657 X86Opcode = X86ISD::HADD;
6658 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6659 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6660 ((InVec0.getOpcode() == ISD::UNDEF ||
6661 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6662 ((InVec1.getOpcode() == ISD::UNDEF ||
6663 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6664 X86Opcode = X86ISD::HSUB;
6669 // Fold this build_vector into a single horizontal add/sub.
6670 // Do this only if the target has AVX2.
6671 if (Subtarget->hasAVX2())
6672 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6674 // Do not try to expand this build_vector into a pair of horizontal
6675 // add/sub if we can emit a pair of scalar add/sub.
6676 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6679 // Convert this build_vector into a pair of horizontal binop followed by
6681 bool isUndefLO = NumUndefsLO == Half;
6682 bool isUndefHI = NumUndefsHI == Half;
6683 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6684 isUndefLO, isUndefHI);
6688 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6689 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6691 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6692 X86Opcode = X86ISD::HADD;
6693 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6694 X86Opcode = X86ISD::HSUB;
6695 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6696 X86Opcode = X86ISD::FHADD;
6697 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6698 X86Opcode = X86ISD::FHSUB;
6702 // Don't try to expand this build_vector into a pair of horizontal add/sub
6703 // if we can simply emit a pair of scalar add/sub.
6704 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6707 // Convert this build_vector into two horizontal add/sub followed by
6709 bool isUndefLO = NumUndefsLO == Half;
6710 bool isUndefHI = NumUndefsHI == Half;
6711 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6712 isUndefLO, isUndefHI);
6719 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6722 MVT VT = Op.getSimpleValueType();
6723 MVT ExtVT = VT.getVectorElementType();
6724 unsigned NumElems = Op.getNumOperands();
6726 // Generate vectors for predicate vectors.
6727 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6728 return LowerBUILD_VECTORvXi1(Op, DAG);
6730 // Vectors containing all zeros can be matched by pxor and xorps later
6731 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6732 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6733 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6734 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6737 return getZeroVector(VT, Subtarget, DAG, dl);
6740 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6741 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6742 // vpcmpeqd on 256-bit vectors.
6743 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6744 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6747 if (!VT.is512BitVector())
6748 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6751 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6752 if (Broadcast.getNode())
6755 unsigned EVTBits = ExtVT.getSizeInBits();
6757 unsigned NumZero = 0;
6758 unsigned NumNonZero = 0;
6759 unsigned NonZeros = 0;
6760 bool IsAllConstants = true;
6761 SmallSet<SDValue, 8> Values;
6762 for (unsigned i = 0; i < NumElems; ++i) {
6763 SDValue Elt = Op.getOperand(i);
6764 if (Elt.getOpcode() == ISD::UNDEF)
6767 if (Elt.getOpcode() != ISD::Constant &&
6768 Elt.getOpcode() != ISD::ConstantFP)
6769 IsAllConstants = false;
6770 if (X86::isZeroNode(Elt))
6773 NonZeros |= (1 << i);
6778 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6779 if (NumNonZero == 0)
6780 return DAG.getUNDEF(VT);
6782 // Special case for single non-zero, non-undef, element.
6783 if (NumNonZero == 1) {
6784 unsigned Idx = countTrailingZeros(NonZeros);
6785 SDValue Item = Op.getOperand(Idx);
6787 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6788 // the value are obviously zero, truncate the value to i32 and do the
6789 // insertion that way. Only do this if the value is non-constant or if the
6790 // value is a constant being inserted into element 0. It is cheaper to do
6791 // a constant pool load than it is to do a movd + shuffle.
6792 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6793 (!IsAllConstants || Idx == 0)) {
6794 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6796 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6797 EVT VecVT = MVT::v4i32;
6798 unsigned VecElts = 4;
6800 // Truncate the value (which may itself be a constant) to i32, and
6801 // convert it to a vector with movd (S2V+shuffle to zero extend).
6802 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6803 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6805 // If using the new shuffle lowering, just directly insert this.
6806 if (ExperimentalVectorShuffleLowering)
6808 ISD::BITCAST, dl, VT,
6809 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6811 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6813 // Now we have our 32-bit value zero extended in the low element of
6814 // a vector. If Idx != 0, swizzle it into place.
6816 SmallVector<int, 4> Mask;
6817 Mask.push_back(Idx);
6818 for (unsigned i = 1; i != VecElts; ++i)
6820 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6823 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6827 // If we have a constant or non-constant insertion into the low element of
6828 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6829 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6830 // depending on what the source datatype is.
6833 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6835 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6836 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6837 if (VT.is256BitVector() || VT.is512BitVector()) {
6838 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6839 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6840 Item, DAG.getIntPtrConstant(0));
6842 assert(VT.is128BitVector() && "Expected an SSE value type!");
6843 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6844 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6845 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6848 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6849 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6850 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6851 if (VT.is256BitVector()) {
6852 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6853 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6855 assert(VT.is128BitVector() && "Expected an SSE value type!");
6856 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6858 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6862 // Is it a vector logical left shift?
6863 if (NumElems == 2 && Idx == 1 &&
6864 X86::isZeroNode(Op.getOperand(0)) &&
6865 !X86::isZeroNode(Op.getOperand(1))) {
6866 unsigned NumBits = VT.getSizeInBits();
6867 return getVShift(true, VT,
6868 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6869 VT, Op.getOperand(1)),
6870 NumBits/2, DAG, *this, dl);
6873 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6876 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6877 // is a non-constant being inserted into an element other than the low one,
6878 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6879 // movd/movss) to move this into the low element, then shuffle it into
6881 if (EVTBits == 32) {
6882 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6884 // If using the new shuffle lowering, just directly insert this.
6885 if (ExperimentalVectorShuffleLowering)
6886 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6888 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6889 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6890 SmallVector<int, 8> MaskVec;
6891 for (unsigned i = 0; i != NumElems; ++i)
6892 MaskVec.push_back(i == Idx ? 0 : 1);
6893 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6897 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6898 if (Values.size() == 1) {
6899 if (EVTBits == 32) {
6900 // Instead of a shuffle like this:
6901 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6902 // Check if it's possible to issue this instead.
6903 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6904 unsigned Idx = countTrailingZeros(NonZeros);
6905 SDValue Item = Op.getOperand(Idx);
6906 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6907 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6912 // A vector full of immediates; various special cases are already
6913 // handled, so this is best done with a single constant-pool load.
6917 // For AVX-length vectors, build the individual 128-bit pieces and use
6918 // shuffles to put them in place.
6919 if (VT.is256BitVector() || VT.is512BitVector()) {
6920 SmallVector<SDValue, 64> V;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 V.push_back(Op.getOperand(i));
6924 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6926 // Build both the lower and upper subvector.
6927 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6928 makeArrayRef(&V[0], NumElems/2));
6929 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6930 makeArrayRef(&V[NumElems / 2], NumElems/2));
6932 // Recreate the wider vector with the lower and upper part.
6933 if (VT.is256BitVector())
6934 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6935 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6938 // Let legalizer expand 2-wide build_vectors.
6939 if (EVTBits == 64) {
6940 if (NumNonZero == 1) {
6941 // One half is zero or undef.
6942 unsigned Idx = countTrailingZeros(NonZeros);
6943 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6944 Op.getOperand(Idx));
6945 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6950 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6951 if (EVTBits == 8 && NumElems == 16) {
6952 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6954 if (V.getNode()) return V;
6957 if (EVTBits == 16 && NumElems == 8) {
6958 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6960 if (V.getNode()) return V;
6963 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6964 if (EVTBits == 32 && NumElems == 4) {
6965 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6966 NumZero, DAG, Subtarget, *this);
6971 // If element VT is == 32 bits, turn it into a number of shuffles.
6972 SmallVector<SDValue, 8> V(NumElems);
6973 if (NumElems == 4 && NumZero > 0) {
6974 for (unsigned i = 0; i < 4; ++i) {
6975 bool isZero = !(NonZeros & (1 << i));
6977 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6979 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6982 for (unsigned i = 0; i < 2; ++i) {
6983 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6986 V[i] = V[i*2]; // Must be a zero vector.
6989 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6992 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6995 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7000 bool Reverse1 = (NonZeros & 0x3) == 2;
7001 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7005 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7006 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7008 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7011 if (Values.size() > 1 && VT.is128BitVector()) {
7012 // Check for a build vector of consecutive loads.
7013 for (unsigned i = 0; i < NumElems; ++i)
7014 V[i] = Op.getOperand(i);
7016 // Check for elements which are consecutive loads.
7017 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7021 // Check for a build vector from mostly shuffle plus few inserting.
7022 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7026 // For SSE 4.1, use insertps to put the high elements into the low element.
7027 if (getSubtarget()->hasSSE41()) {
7029 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7030 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7032 Result = DAG.getUNDEF(VT);
7034 for (unsigned i = 1; i < NumElems; ++i) {
7035 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7036 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7037 Op.getOperand(i), DAG.getIntPtrConstant(i));
7042 // Otherwise, expand into a number of unpckl*, start by extending each of
7043 // our (non-undef) elements to the full vector width with the element in the
7044 // bottom slot of the vector (which generates no code for SSE).
7045 for (unsigned i = 0; i < NumElems; ++i) {
7046 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7049 V[i] = DAG.getUNDEF(VT);
7052 // Next, we iteratively mix elements, e.g. for v4f32:
7053 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7054 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7055 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7056 unsigned EltStride = NumElems >> 1;
7057 while (EltStride != 0) {
7058 for (unsigned i = 0; i < EltStride; ++i) {
7059 // If V[i+EltStride] is undef and this is the first round of mixing,
7060 // then it is safe to just drop this shuffle: V[i] is already in the
7061 // right place, the one element (since it's the first round) being
7062 // inserted as undef can be dropped. This isn't safe for successive
7063 // rounds because they will permute elements within both vectors.
7064 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7065 EltStride == NumElems/2)
7068 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7077 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7078 // to create 256-bit vectors from two other 128-bit ones.
7079 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7081 MVT ResVT = Op.getSimpleValueType();
7083 assert((ResVT.is256BitVector() ||
7084 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7086 SDValue V1 = Op.getOperand(0);
7087 SDValue V2 = Op.getOperand(1);
7088 unsigned NumElems = ResVT.getVectorNumElements();
7089 if(ResVT.is256BitVector())
7090 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7092 if (Op.getNumOperands() == 4) {
7093 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7094 ResVT.getVectorNumElements()/2);
7095 SDValue V3 = Op.getOperand(2);
7096 SDValue V4 = Op.getOperand(3);
7097 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7098 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7100 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7103 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7104 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7105 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7106 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7107 Op.getNumOperands() == 4)));
7109 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7110 // from two other 128-bit ones.
7112 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7113 return LowerAVXCONCAT_VECTORS(Op, DAG);
7117 //===----------------------------------------------------------------------===//
7118 // Vector shuffle lowering
7120 // This is an experimental code path for lowering vector shuffles on x86. It is
7121 // designed to handle arbitrary vector shuffles and blends, gracefully
7122 // degrading performance as necessary. It works hard to recognize idiomatic
7123 // shuffles and lower them to optimal instruction patterns without leaving
7124 // a framework that allows reasonably efficient handling of all vector shuffle
7126 //===----------------------------------------------------------------------===//
7128 /// \brief Tiny helper function to identify a no-op mask.
7130 /// This is a somewhat boring predicate function. It checks whether the mask
7131 /// array input, which is assumed to be a single-input shuffle mask of the kind
7132 /// used by the X86 shuffle instructions (not a fully general
7133 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7134 /// in-place shuffle are 'no-op's.
7135 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7136 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7137 if (Mask[i] != -1 && Mask[i] != i)
7142 /// \brief Helper function to classify a mask as a single-input mask.
7144 /// This isn't a generic single-input test because in the vector shuffle
7145 /// lowering we canonicalize single inputs to be the first input operand. This
7146 /// means we can more quickly test for a single input by only checking whether
7147 /// an input from the second operand exists. We also assume that the size of
7148 /// mask corresponds to the size of the input vectors which isn't true in the
7149 /// fully general case.
7150 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7152 if (M >= (int)Mask.size())
7157 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7158 // 2013 will allow us to use it as a non-type template parameter.
7161 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7163 /// See its documentation for details.
7164 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7165 if (Mask.size() != Args.size())
7167 for (int i = 0, e = Mask.size(); i < e; ++i) {
7168 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7169 assert(*Args[i] < (int)Args.size() * 2 &&
7170 "Argument outside the range of possible shuffle inputs!");
7171 if (Mask[i] != -1 && Mask[i] != *Args[i])
7179 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7182 /// This is a fast way to test a shuffle mask against a fixed pattern:
7184 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7186 /// It returns true if the mask is exactly as wide as the argument list, and
7187 /// each element of the mask is either -1 (signifying undef) or the value given
7188 /// in the argument.
7189 static const VariadicFunction1<
7190 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7192 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7194 /// This helper function produces an 8-bit shuffle immediate corresponding to
7195 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7196 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7199 /// NB: We rely heavily on "undef" masks preserving the input lane.
7200 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7201 SelectionDAG &DAG) {
7202 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7203 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7204 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7205 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7206 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7209 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7210 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7211 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7212 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7213 return DAG.getConstant(Imm, MVT::i8);
7216 /// \brief Try to emit a blend instruction for a shuffle.
7218 /// This doesn't do any checks for the availability of instructions for blending
7219 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7220 /// be matched in the backend with the type given. What it does check for is
7221 /// that the shuffle mask is in fact a blend.
7222 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7223 SDValue V2, ArrayRef<int> Mask,
7224 SelectionDAG &DAG) {
7226 unsigned BlendMask = 0;
7227 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7228 if (Mask[i] >= Size) {
7229 if (Mask[i] != i + Size)
7230 return SDValue(); // Shuffled V2 input!
7231 BlendMask |= 1u << i;
7234 if (Mask[i] >= 0 && Mask[i] != i)
7235 return SDValue(); // Shuffled V1 input!
7237 switch (VT.SimpleTy) {
7241 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7242 DAG.getConstant(BlendMask, MVT::i8));
7247 // For integer shuffles we need to expand the mask and cast the inputs to
7248 // v8i16s prior to blending.
7249 int Scale = 8 / VT.getVectorNumElements();
7251 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7252 if (Mask[i] >= Size)
7253 for (int j = 0; j < Scale; ++j)
7254 BlendMask |= 1u << (i * Scale + j);
7256 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7257 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7258 return DAG.getNode(ISD::BITCAST, DL, VT,
7259 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7260 DAG.getConstant(BlendMask, MVT::i8)));
7264 llvm_unreachable("Not a supported integer vector type!");
7268 /// \brief Try to lower a vector shuffle as a byte rotation.
7270 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7271 /// byte-rotation of a the concatentation of two vectors. This routine will
7272 /// try to generically lower a vector shuffle through such an instruction. It
7273 /// does not check for the availability of PALIGNR-based lowerings, only the
7274 /// applicability of this strategy to the given mask. This matches shuffle
7275 /// vectors that look like:
7277 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7279 /// Essentially it concatenates V1 and V2, shifts right by some number of
7280 /// elements, and takes the low elements as the result. Note that while this is
7281 /// specified as a *right shift* because x86 is little-endian, it is a *left
7282 /// rotate* of the vector lanes.
7284 /// Note that this only handles 128-bit vector widths currently.
7285 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7288 SelectionDAG &DAG) {
7289 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7291 // We need to detect various ways of spelling a rotation:
7292 // [11, 12, 13, 14, 15, 0, 1, 2]
7293 // [-1, 12, 13, 14, -1, -1, 1, -1]
7294 // [-1, -1, -1, -1, -1, -1, 1, 2]
7295 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7296 // [-1, 4, 5, 6, -1, -1, 9, -1]
7297 // [-1, 4, 5, 6, -1, -1, -1, -1]
7300 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7303 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7305 // Based on the mod-Size value of this mask element determine where
7306 // a rotated vector would have started.
7307 int StartIdx = i - (Mask[i] % Size);
7309 // The identity rotation isn't interesting, stop.
7312 // If we found the tail of a vector the rotation must be the missing
7313 // front. If we found the head of a vector, it must be how much of the head.
7314 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7317 Rotation = CandidateRotation;
7318 else if (Rotation != CandidateRotation)
7319 // The rotations don't match, so we can't match this mask.
7322 // Compute which value this mask is pointing at.
7323 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7325 // Compute which of the two target values this index should be assigned to.
7326 // This reflects whether the high elements are remaining or the low elements
7328 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7330 // Either set up this value if we've not encountered it before, or check
7331 // that it remains consistent.
7334 else if (TargetV != MaskV)
7335 // This may be a rotation, but it pulls from the inputs in some
7336 // unsupported interleaving.
7340 // Check that we successfully analyzed the mask, and normalize the results.
7341 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7342 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7348 // Cast the inputs to v16i8 to match PALIGNR.
7349 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7350 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7352 assert(VT.getSizeInBits() == 128 &&
7353 "Rotate-based lowering only supports 128-bit lowering!");
7354 assert(Mask.size() <= 16 &&
7355 "Can shuffle at most 16 bytes in a 128-bit vector!");
7356 // The actual rotate instruction rotates bytes, so we need to scale the
7357 // rotation based on how many bytes are in the vector.
7358 int Scale = 16 / Mask.size();
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7362 DAG.getConstant(Rotation * Scale, MVT::i8)));
7365 /// \brief Compute whether each element of a shuffle is zeroable.
7367 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7368 /// Either it is an undef element in the shuffle mask, the element of the input
7369 /// referenced is undef, or the element of the input referenced is known to be
7370 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7371 /// as many lanes with this technique as possible to simplify the remaining
7373 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7374 SDValue V1, SDValue V2) {
7375 SmallBitVector Zeroable(Mask.size(), false);
7377 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7378 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7380 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7382 // Handle the easy cases.
7383 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7388 // If this is an index into a build_vector node, dig out the input value and
7390 SDValue V = M < Size ? V1 : V2;
7391 if (V.getOpcode() != ISD::BUILD_VECTOR)
7394 SDValue Input = V.getOperand(M % Size);
7395 // The UNDEF opcode check really should be dead code here, but not quite
7396 // worth asserting on (it isn't invalid, just unexpected).
7397 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7404 /// \brief Lower a vector shuffle as a zero or any extension.
7406 /// Given a specific number of elements, element bit width, and extension
7407 /// stride, produce either a zero or any extension based on the available
7408 /// features of the subtarget.
7409 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7410 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7411 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7412 assert(Scale > 1 && "Need a scale to extend.");
7413 int EltBits = VT.getSizeInBits() / NumElements;
7414 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7415 "Only 8, 16, and 32 bit elements can be extended.");
7416 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7418 // Found a valid zext mask! Try various lowering strategies based on the
7419 // input type and available ISA extensions.
7420 if (Subtarget->hasSSE41()) {
7421 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7422 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7423 NumElements / Scale);
7424 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7425 return DAG.getNode(ISD::BITCAST, DL, VT,
7426 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7429 // For any extends we can cheat for larger element sizes and use shuffle
7430 // instructions that can fold with a load and/or copy.
7431 if (AnyExt && EltBits == 32) {
7432 int PSHUFDMask[4] = {0, -1, 1, -1};
7434 ISD::BITCAST, DL, VT,
7435 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7436 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7437 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7439 if (AnyExt && EltBits == 16 && Scale > 2) {
7440 int PSHUFDMask[4] = {0, -1, 0, -1};
7441 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7442 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7443 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7444 int PSHUFHWMask[4] = {1, -1, -1, -1};
7446 ISD::BITCAST, DL, VT,
7447 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7448 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7449 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7452 // If this would require more than 2 unpack instructions to expand, use
7453 // pshufb when available. We can only use more than 2 unpack instructions
7454 // when zero extending i8 elements which also makes it easier to use pshufb.
7455 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7456 assert(NumElements == 16 && "Unexpected byte vector width!");
7457 SDValue PSHUFBMask[16];
7458 for (int i = 0; i < 16; ++i)
7460 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7461 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7462 return DAG.getNode(ISD::BITCAST, DL, VT,
7463 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7464 DAG.getNode(ISD::BUILD_VECTOR, DL,
7465 MVT::v16i8, PSHUFBMask)));
7468 // Otherwise emit a sequence of unpacks.
7470 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7471 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7472 : getZeroVector(InputVT, Subtarget, DAG, DL);
7473 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7474 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7478 } while (Scale > 1);
7479 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7482 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7484 /// This routine will try to do everything in its power to cleverly lower
7485 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7486 /// check for the profitability of this lowering, it tries to aggressively
7487 /// match this pattern. It will use all of the micro-architectural details it
7488 /// can to emit an efficient lowering. It handles both blends with all-zero
7489 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7490 /// masking out later).
7492 /// The reason we have dedicated lowering for zext-style shuffles is that they
7493 /// are both incredibly common and often quite performance sensitive.
7494 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7495 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7496 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7497 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7499 int Bits = VT.getSizeInBits();
7500 int NumElements = Mask.size();
7502 // Define a helper function to check a particular ext-scale and lower to it if
7504 auto Lower = [&](int Scale) -> SDValue {
7507 for (int i = 0; i < NumElements; ++i) {
7509 continue; // Valid anywhere but doesn't tell us anything.
7510 if (i % Scale != 0) {
7511 // Each of the extend elements needs to be zeroable.
7515 // We no lorger are in the anyext case.
7520 // Each of the base elements needs to be consecutive indices into the
7521 // same input vector.
7522 SDValue V = Mask[i] < NumElements ? V1 : V2;
7525 else if (InputV != V)
7526 return SDValue(); // Flip-flopping inputs.
7528 if (Mask[i] % NumElements != i / Scale)
7529 return SDValue(); // Non-consecutive strided elemenst.
7532 // If we fail to find an input, we have a zero-shuffle which should always
7533 // have already been handled.
7534 // FIXME: Maybe handle this here in case during blending we end up with one?
7538 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7539 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7542 // The widest scale possible for extending is to a 64-bit integer.
7543 assert(Bits % 64 == 0 &&
7544 "The number of bits in a vector must be divisible by 64 on x86!");
7545 int NumExtElements = Bits / 64;
7547 // Each iteration, try extending the elements half as much, but into twice as
7549 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7550 assert(NumElements % NumExtElements == 0 &&
7551 "The input vector size must be divisble by the extended size.");
7552 if (SDValue V = Lower(NumElements / NumExtElements))
7556 // No viable ext lowering found.
7560 /// \brief Try to lower insertion of a single element into a zero vector.
7562 /// This is a common pattern that we have especially efficient patterns to lower
7563 /// across all subtarget feature sets.
7564 static SDValue lowerVectorShuffleAsElementInsertion(
7565 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7566 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7567 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7569 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7570 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7572 if (Mask.size() == 2) {
7573 if (!Zeroable[V2Index ^ 1]) {
7574 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7575 // with 2 to flip from {2,3} to {0,1} and vice versa.
7576 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7577 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7578 if (Zeroable[V2Index])
7579 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7585 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7586 if (i != V2Index && !Zeroable[i])
7587 return SDValue(); // Not inserting into a zero vector.
7590 // Step over any bitcasts on either input so we can scan the actual
7591 // BUILD_VECTOR nodes.
7592 while (V1.getOpcode() == ISD::BITCAST)
7593 V1 = V1.getOperand(0);
7594 while (V2.getOpcode() == ISD::BITCAST)
7595 V2 = V2.getOperand(0);
7597 // Check for a single input from a SCALAR_TO_VECTOR node.
7598 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7599 // all the smarts here sunk into that routine. However, the current
7600 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7601 // vector shuffle lowering is dead.
7602 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7603 Mask[V2Index] == (int)Mask.size()) ||
7604 V2.getOpcode() == ISD::BUILD_VECTOR))
7607 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7609 // First, we need to zext the scalar if it is smaller than an i32.
7611 MVT EltVT = VT.getVectorElementType();
7612 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7613 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7614 // Zero-extend directly to i32.
7616 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7619 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7620 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7622 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7625 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7626 // the desired position. Otherwise it is more efficient to do a vector
7627 // shift left. We know that we can do a vector shift left because all
7628 // the inputs are zero.
7629 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7630 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7631 V2Shuffle[V2Index] = 0;
7632 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7634 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7636 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7638 V2Index * EltVT.getSizeInBits(),
7639 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7640 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7646 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7648 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7649 /// support for floating point shuffles but not integer shuffles. These
7650 /// instructions will incur a domain crossing penalty on some chips though so
7651 /// it is better to avoid lowering through this for integer vectors where
7653 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7654 const X86Subtarget *Subtarget,
7655 SelectionDAG &DAG) {
7657 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7658 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7659 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7660 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7661 ArrayRef<int> Mask = SVOp->getMask();
7662 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7664 if (isSingleInputShuffleMask(Mask)) {
7665 // Straight shuffle of a single input vector. Simulate this by using the
7666 // single input as both of the "inputs" to this instruction..
7667 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7669 if (Subtarget->hasAVX()) {
7670 // If we have AVX, we can use VPERMILPS which will allow folding a load
7671 // into the shuffle.
7672 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v2f64, V1,
7673 DAG.getConstant(SHUFPDMask, MVT::i8));
7676 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7677 DAG.getConstant(SHUFPDMask, MVT::i8));
7679 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7680 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7682 // Use dedicated unpack instructions for masks that match their pattern.
7683 if (isShuffleEquivalent(Mask, 0, 2))
7684 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7685 if (isShuffleEquivalent(Mask, 1, 3))
7686 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7688 // If we have a single input, insert that into V1 if we can do so cheaply.
7689 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7690 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7691 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7694 if (Subtarget->hasSSE41())
7696 lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask, DAG))
7699 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7700 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7701 DAG.getConstant(SHUFPDMask, MVT::i8));
7704 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7706 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7707 /// the integer unit to minimize domain crossing penalties. However, for blends
7708 /// it falls back to the floating point shuffle operation with appropriate bit
7710 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7711 const X86Subtarget *Subtarget,
7712 SelectionDAG &DAG) {
7714 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7715 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7716 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7717 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7718 ArrayRef<int> Mask = SVOp->getMask();
7719 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7721 if (isSingleInputShuffleMask(Mask)) {
7722 // Straight shuffle of a single input vector. For everything from SSE2
7723 // onward this has a single fast instruction with no scary immediates.
7724 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7725 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7726 int WidenedMask[4] = {
7727 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7728 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7730 ISD::BITCAST, DL, MVT::v2i64,
7731 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7732 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7735 // Use dedicated unpack instructions for masks that match their pattern.
7736 if (isShuffleEquivalent(Mask, 0, 2))
7737 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7738 if (isShuffleEquivalent(Mask, 1, 3))
7739 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7741 // If we have a single input from V2 insert that into V1 if we can do so
7743 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7744 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7745 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7748 if (Subtarget->hasSSE41())
7750 lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask, DAG))
7753 // Try to use rotation instructions if available.
7754 if (Subtarget->hasSSSE3())
7755 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7756 DL, MVT::v2i64, V1, V2, Mask, DAG))
7759 // We implement this with SHUFPD which is pretty lame because it will likely
7760 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7761 // However, all the alternatives are still more cycles and newer chips don't
7762 // have this problem. It would be really nice if x86 had better shuffles here.
7763 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7764 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7765 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7766 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7769 /// \brief Lower 4-lane 32-bit floating point shuffles.
7771 /// Uses instructions exclusively from the floating point unit to minimize
7772 /// domain crossing penalties, as these are sufficient to implement all v4f32
7774 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7775 const X86Subtarget *Subtarget,
7776 SelectionDAG &DAG) {
7778 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7779 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7780 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7781 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7782 ArrayRef<int> Mask = SVOp->getMask();
7783 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7785 SDValue LowV = V1, HighV = V2;
7786 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7789 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7791 if (NumV2Elements == 0) {
7792 if (Subtarget->hasAVX()) {
7793 // If we have AVX, we can use VPERMILPS which will allow folding a load
7794 // into the shuffle.
7795 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f32, V1,
7796 getV4X86ShuffleImm8ForMask(Mask, DAG));
7799 // Otherwise, use a straight shuffle of a single input vector. We pass the
7800 // input vector to both operands to simulate this with a SHUFPS.
7801 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7802 getV4X86ShuffleImm8ForMask(Mask, DAG));
7805 // Use dedicated unpack instructions for masks that match their pattern.
7806 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7807 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7808 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7809 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7811 // There are special ways we can lower some single-element blends. However, we
7812 // have custom ways we can lower more complex single-element blends below that
7813 // we defer to if both this and BLENDPS fail to match, so restrict this to
7814 // when the V2 input is targeting element 0 of the mask -- that is the fast
7816 if (NumV2Elements == 1 && Mask[0] >= 4)
7817 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7818 Mask, Subtarget, DAG))
7821 if (Subtarget->hasSSE41())
7823 lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask, DAG))
7826 if (NumV2Elements == 1) {
7828 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7831 // Check for whether we can use INSERTPS to perform the blend. We only use
7832 // INSERTPS when the V1 elements are already in the correct locations
7833 // because otherwise we can just always use two SHUFPS instructions which
7834 // are much smaller to encode than a SHUFPS and an INSERTPS.
7835 if (Subtarget->hasSSE41()) {
7836 // When using INSERTPS we can zero any lane of the destination. Collect
7837 // the zero inputs into a mask and drop them from the lanes of V1 which
7838 // actually need to be present as inputs to the INSERTPS.
7839 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7841 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7842 bool InsertNeedsShuffle = false;
7844 for (int i = 0; i < 4; ++i)
7848 } else if (Mask[i] != i) {
7849 InsertNeedsShuffle = true;
7854 // We don't want to use INSERTPS or other insertion techniques if it will
7855 // require shuffling anyways.
7856 if (!InsertNeedsShuffle) {
7857 // If all of V1 is zeroable, replace it with undef.
7858 if ((ZMask | 1 << V2Index) == 0xF)
7859 V1 = DAG.getUNDEF(MVT::v4f32);
7861 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7862 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7864 // Insert the V2 element into the desired position.
7865 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7866 DAG.getConstant(InsertPSMask, MVT::i8));
7870 // Compute the index adjacent to V2Index and in the same half by toggling
7872 int V2AdjIndex = V2Index ^ 1;
7874 if (Mask[V2AdjIndex] == -1) {
7875 // Handles all the cases where we have a single V2 element and an undef.
7876 // This will only ever happen in the high lanes because we commute the
7877 // vector otherwise.
7879 std::swap(LowV, HighV);
7880 NewMask[V2Index] -= 4;
7882 // Handle the case where the V2 element ends up adjacent to a V1 element.
7883 // To make this work, blend them together as the first step.
7884 int V1Index = V2AdjIndex;
7885 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7886 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7887 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7889 // Now proceed to reconstruct the final blend as we have the necessary
7890 // high or low half formed.
7897 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7898 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7900 } else if (NumV2Elements == 2) {
7901 if (Mask[0] < 4 && Mask[1] < 4) {
7902 // Handle the easy case where we have V1 in the low lanes and V2 in the
7903 // high lanes. We never see this reversed because we sort the shuffle.
7907 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7908 // trying to place elements directly, just blend them and set up the final
7909 // shuffle to place them.
7911 // The first two blend mask elements are for V1, the second two are for
7913 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7914 Mask[2] < 4 ? Mask[2] : Mask[3],
7915 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7916 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7917 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7918 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7920 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7923 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7924 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7925 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7926 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7929 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7930 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7933 /// \brief Lower 4-lane i32 vector shuffles.
7935 /// We try to handle these with integer-domain shuffles where we can, but for
7936 /// blends we use the floating point domain blend instructions.
7937 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7938 const X86Subtarget *Subtarget,
7939 SelectionDAG &DAG) {
7941 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7942 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7943 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7944 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7945 ArrayRef<int> Mask = SVOp->getMask();
7946 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7949 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7951 if (NumV2Elements == 0) {
7952 // Straight shuffle of a single input vector. For everything from SSE2
7953 // onward this has a single fast instruction with no scary immediates.
7954 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7955 // but we aren't actually going to use the UNPCK instruction because doing
7956 // so prevents folding a load into this instruction or making a copy.
7957 const int UnpackLoMask[] = {0, 0, 1, 1};
7958 const int UnpackHiMask[] = {2, 2, 3, 3};
7959 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
7960 Mask = UnpackLoMask;
7961 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
7962 Mask = UnpackHiMask;
7964 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7965 getV4X86ShuffleImm8ForMask(Mask, DAG));
7968 // Whenever we can lower this as a zext, that instruction is strictly faster
7969 // than any alternative.
7970 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7971 Mask, Subtarget, DAG))
7974 // Use dedicated unpack instructions for masks that match their pattern.
7975 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7976 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7977 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7978 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7980 // There are special ways we can lower some single-element blends.
7981 if (NumV2Elements == 1)
7982 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
7983 Mask, Subtarget, DAG))
7986 if (Subtarget->hasSSE41())
7988 lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask, DAG))
7991 // Try to use rotation instructions if available.
7992 if (Subtarget->hasSSSE3())
7993 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7994 DL, MVT::v4i32, V1, V2, Mask, DAG))
7997 // We implement this with SHUFPS because it can blend from two vectors.
7998 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7999 // up the inputs, bypassing domain shift penalties that we would encur if we
8000 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8002 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8003 DAG.getVectorShuffle(
8005 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8006 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8009 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8010 /// shuffle lowering, and the most complex part.
8012 /// The lowering strategy is to try to form pairs of input lanes which are
8013 /// targeted at the same half of the final vector, and then use a dword shuffle
8014 /// to place them onto the right half, and finally unpack the paired lanes into
8015 /// their final position.
8017 /// The exact breakdown of how to form these dword pairs and align them on the
8018 /// correct sides is really tricky. See the comments within the function for
8019 /// more of the details.
8020 static SDValue lowerV8I16SingleInputVectorShuffle(
8021 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8022 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8023 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8024 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8025 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8027 SmallVector<int, 4> LoInputs;
8028 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8029 [](int M) { return M >= 0; });
8030 std::sort(LoInputs.begin(), LoInputs.end());
8031 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8032 SmallVector<int, 4> HiInputs;
8033 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8034 [](int M) { return M >= 0; });
8035 std::sort(HiInputs.begin(), HiInputs.end());
8036 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8038 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8039 int NumHToL = LoInputs.size() - NumLToL;
8041 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8042 int NumHToH = HiInputs.size() - NumLToH;
8043 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8044 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8045 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8046 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8048 // Use dedicated unpack instructions for masks that match their pattern.
8049 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8050 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8051 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8052 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8054 // Try to use rotation instructions if available.
8055 if (Subtarget->hasSSSE3())
8056 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8057 DL, MVT::v8i16, V, V, Mask, DAG))
8060 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8061 // such inputs we can swap two of the dwords across the half mark and end up
8062 // with <=2 inputs to each half in each half. Once there, we can fall through
8063 // to the generic code below. For example:
8065 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8066 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8068 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8069 // and an existing 2-into-2 on the other half. In this case we may have to
8070 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8071 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8072 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8073 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8074 // half than the one we target for fixing) will be fixed when we re-enter this
8075 // path. We will also combine away any sequence of PSHUFD instructions that
8076 // result into a single instruction. Here is an example of the tricky case:
8078 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8079 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8081 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8083 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8084 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8086 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8087 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8089 // The result is fine to be handled by the generic logic.
8090 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8091 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8092 int AOffset, int BOffset) {
8093 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8094 "Must call this with A having 3 or 1 inputs from the A half.");
8095 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8096 "Must call this with B having 1 or 3 inputs from the B half.");
8097 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8098 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8100 // Compute the index of dword with only one word among the three inputs in
8101 // a half by taking the sum of the half with three inputs and subtracting
8102 // the sum of the actual three inputs. The difference is the remaining
8105 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8106 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8107 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8108 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8109 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8110 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8111 int TripleNonInputIdx =
8112 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8113 TripleDWord = TripleNonInputIdx / 2;
8115 // We use xor with one to compute the adjacent DWord to whichever one the
8117 OneInputDWord = (OneInput / 2) ^ 1;
8119 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8120 // and BToA inputs. If there is also such a problem with the BToB and AToB
8121 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8122 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8123 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8124 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8125 // Compute how many inputs will be flipped by swapping these DWords. We
8127 // to balance this to ensure we don't form a 3-1 shuffle in the other
8129 int NumFlippedAToBInputs =
8130 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8131 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8132 int NumFlippedBToBInputs =
8133 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8134 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8135 if ((NumFlippedAToBInputs == 1 &&
8136 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8137 (NumFlippedBToBInputs == 1 &&
8138 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8139 // We choose whether to fix the A half or B half based on whether that
8140 // half has zero flipped inputs. At zero, we may not be able to fix it
8141 // with that half. We also bias towards fixing the B half because that
8142 // will more commonly be the high half, and we have to bias one way.
8143 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8144 ArrayRef<int> Inputs) {
8145 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8146 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8147 PinnedIdx ^ 1) != Inputs.end();
8148 // Determine whether the free index is in the flipped dword or the
8149 // unflipped dword based on where the pinned index is. We use this bit
8150 // in an xor to conditionally select the adjacent dword.
8151 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8152 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8153 FixFreeIdx) != Inputs.end();
8154 if (IsFixIdxInput == IsFixFreeIdxInput)
8156 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8157 FixFreeIdx) != Inputs.end();
8158 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8159 "We need to be changing the number of flipped inputs!");
8160 int PSHUFHalfMask[] = {0, 1, 2, 3};
8161 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8162 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8164 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8167 if (M != -1 && M == FixIdx)
8169 else if (M != -1 && M == FixFreeIdx)
8172 if (NumFlippedBToBInputs != 0) {
8174 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8175 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8177 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8179 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8180 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8185 int PSHUFDMask[] = {0, 1, 2, 3};
8186 PSHUFDMask[ADWord] = BDWord;
8187 PSHUFDMask[BDWord] = ADWord;
8188 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8189 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8190 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8191 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8193 // Adjust the mask to match the new locations of A and B.
8195 if (M != -1 && M/2 == ADWord)
8196 M = 2 * BDWord + M % 2;
8197 else if (M != -1 && M/2 == BDWord)
8198 M = 2 * ADWord + M % 2;
8200 // Recurse back into this routine to re-compute state now that this isn't
8201 // a 3 and 1 problem.
8202 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8205 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8206 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8207 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8208 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8210 // At this point there are at most two inputs to the low and high halves from
8211 // each half. That means the inputs can always be grouped into dwords and
8212 // those dwords can then be moved to the correct half with a dword shuffle.
8213 // We use at most one low and one high word shuffle to collect these paired
8214 // inputs into dwords, and finally a dword shuffle to place them.
8215 int PSHUFLMask[4] = {-1, -1, -1, -1};
8216 int PSHUFHMask[4] = {-1, -1, -1, -1};
8217 int PSHUFDMask[4] = {-1, -1, -1, -1};
8219 // First fix the masks for all the inputs that are staying in their
8220 // original halves. This will then dictate the targets of the cross-half
8222 auto fixInPlaceInputs =
8223 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8224 MutableArrayRef<int> SourceHalfMask,
8225 MutableArrayRef<int> HalfMask, int HalfOffset) {
8226 if (InPlaceInputs.empty())
8228 if (InPlaceInputs.size() == 1) {
8229 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8230 InPlaceInputs[0] - HalfOffset;
8231 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8234 if (IncomingInputs.empty()) {
8235 // Just fix all of the in place inputs.
8236 for (int Input : InPlaceInputs) {
8237 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8238 PSHUFDMask[Input / 2] = Input / 2;
8243 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8244 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8245 InPlaceInputs[0] - HalfOffset;
8246 // Put the second input next to the first so that they are packed into
8247 // a dword. We find the adjacent index by toggling the low bit.
8248 int AdjIndex = InPlaceInputs[0] ^ 1;
8249 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8250 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8251 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8253 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8254 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8256 // Now gather the cross-half inputs and place them into a free dword of
8257 // their target half.
8258 // FIXME: This operation could almost certainly be simplified dramatically to
8259 // look more like the 3-1 fixing operation.
8260 auto moveInputsToRightHalf = [&PSHUFDMask](
8261 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8262 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8263 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8265 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8266 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8268 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8270 int LowWord = Word & ~1;
8271 int HighWord = Word | 1;
8272 return isWordClobbered(SourceHalfMask, LowWord) ||
8273 isWordClobbered(SourceHalfMask, HighWord);
8276 if (IncomingInputs.empty())
8279 if (ExistingInputs.empty()) {
8280 // Map any dwords with inputs from them into the right half.
8281 for (int Input : IncomingInputs) {
8282 // If the source half mask maps over the inputs, turn those into
8283 // swaps and use the swapped lane.
8284 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8285 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8286 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8287 Input - SourceOffset;
8288 // We have to swap the uses in our half mask in one sweep.
8289 for (int &M : HalfMask)
8290 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8292 else if (M == Input)
8293 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8295 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8296 Input - SourceOffset &&
8297 "Previous placement doesn't match!");
8299 // Note that this correctly re-maps both when we do a swap and when
8300 // we observe the other side of the swap above. We rely on that to
8301 // avoid swapping the members of the input list directly.
8302 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8305 // Map the input's dword into the correct half.
8306 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8307 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8309 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8311 "Previous placement doesn't match!");
8314 // And just directly shift any other-half mask elements to be same-half
8315 // as we will have mirrored the dword containing the element into the
8316 // same position within that half.
8317 for (int &M : HalfMask)
8318 if (M >= SourceOffset && M < SourceOffset + 4) {
8319 M = M - SourceOffset + DestOffset;
8320 assert(M >= 0 && "This should never wrap below zero!");
8325 // Ensure we have the input in a viable dword of its current half. This
8326 // is particularly tricky because the original position may be clobbered
8327 // by inputs being moved and *staying* in that half.
8328 if (IncomingInputs.size() == 1) {
8329 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8330 int InputFixed = std::find(std::begin(SourceHalfMask),
8331 std::end(SourceHalfMask), -1) -
8332 std::begin(SourceHalfMask) + SourceOffset;
8333 SourceHalfMask[InputFixed - SourceOffset] =
8334 IncomingInputs[0] - SourceOffset;
8335 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8337 IncomingInputs[0] = InputFixed;
8339 } else if (IncomingInputs.size() == 2) {
8340 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8341 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8342 // We have two non-adjacent or clobbered inputs we need to extract from
8343 // the source half. To do this, we need to map them into some adjacent
8344 // dword slot in the source mask.
8345 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8346 IncomingInputs[1] - SourceOffset};
8348 // If there is a free slot in the source half mask adjacent to one of
8349 // the inputs, place the other input in it. We use (Index XOR 1) to
8350 // compute an adjacent index.
8351 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8352 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8353 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8354 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8355 InputsFixed[1] = InputsFixed[0] ^ 1;
8356 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8357 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8358 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8359 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8360 InputsFixed[0] = InputsFixed[1] ^ 1;
8361 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8362 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8363 // The two inputs are in the same DWord but it is clobbered and the
8364 // adjacent DWord isn't used at all. Move both inputs to the free
8366 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8367 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8368 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8369 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8371 // The only way we hit this point is if there is no clobbering
8372 // (because there are no off-half inputs to this half) and there is no
8373 // free slot adjacent to one of the inputs. In this case, we have to
8374 // swap an input with a non-input.
8375 for (int i = 0; i < 4; ++i)
8376 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8377 "We can't handle any clobbers here!");
8378 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8379 "Cannot have adjacent inputs here!");
8381 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8382 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8384 // We also have to update the final source mask in this case because
8385 // it may need to undo the above swap.
8386 for (int &M : FinalSourceHalfMask)
8387 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8388 M = InputsFixed[1] + SourceOffset;
8389 else if (M == InputsFixed[1] + SourceOffset)
8390 M = (InputsFixed[0] ^ 1) + SourceOffset;
8392 InputsFixed[1] = InputsFixed[0] ^ 1;
8395 // Point everything at the fixed inputs.
8396 for (int &M : HalfMask)
8397 if (M == IncomingInputs[0])
8398 M = InputsFixed[0] + SourceOffset;
8399 else if (M == IncomingInputs[1])
8400 M = InputsFixed[1] + SourceOffset;
8402 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8403 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8406 llvm_unreachable("Unhandled input size!");
8409 // Now hoist the DWord down to the right half.
8410 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8411 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8412 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8413 for (int &M : HalfMask)
8414 for (int Input : IncomingInputs)
8416 M = FreeDWord * 2 + Input % 2;
8418 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8419 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8420 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8421 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8423 // Now enact all the shuffles we've computed to move the inputs into their
8425 if (!isNoopShuffleMask(PSHUFLMask))
8426 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8427 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8428 if (!isNoopShuffleMask(PSHUFHMask))
8429 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8430 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8431 if (!isNoopShuffleMask(PSHUFDMask))
8432 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8433 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8434 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8435 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8437 // At this point, each half should contain all its inputs, and we can then
8438 // just shuffle them into their final position.
8439 assert(std::count_if(LoMask.begin(), LoMask.end(),
8440 [](int M) { return M >= 4; }) == 0 &&
8441 "Failed to lift all the high half inputs to the low mask!");
8442 assert(std::count_if(HiMask.begin(), HiMask.end(),
8443 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8444 "Failed to lift all the low half inputs to the high mask!");
8446 // Do a half shuffle for the low mask.
8447 if (!isNoopShuffleMask(LoMask))
8448 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8449 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8451 // Do a half shuffle with the high mask after shifting its values down.
8452 for (int &M : HiMask)
8455 if (!isNoopShuffleMask(HiMask))
8456 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8457 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8462 /// \brief Detect whether the mask pattern should be lowered through
8465 /// This essentially tests whether viewing the mask as an interleaving of two
8466 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8467 /// lowering it through interleaving is a significantly better strategy.
8468 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8469 int NumEvenInputs[2] = {0, 0};
8470 int NumOddInputs[2] = {0, 0};
8471 int NumLoInputs[2] = {0, 0};
8472 int NumHiInputs[2] = {0, 0};
8473 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8477 int InputIdx = Mask[i] >= Size;
8480 ++NumLoInputs[InputIdx];
8482 ++NumHiInputs[InputIdx];
8485 ++NumEvenInputs[InputIdx];
8487 ++NumOddInputs[InputIdx];
8490 // The minimum number of cross-input results for both the interleaved and
8491 // split cases. If interleaving results in fewer cross-input results, return
8493 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8494 NumEvenInputs[0] + NumOddInputs[1]);
8495 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8496 NumLoInputs[0] + NumHiInputs[1]);
8497 return InterleavedCrosses < SplitCrosses;
8500 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8502 /// This strategy only works when the inputs from each vector fit into a single
8503 /// half of that vector, and generally there are not so many inputs as to leave
8504 /// the in-place shuffles required highly constrained (and thus expensive). It
8505 /// shifts all the inputs into a single side of both input vectors and then
8506 /// uses an unpack to interleave these inputs in a single vector. At that
8507 /// point, we will fall back on the generic single input shuffle lowering.
8508 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8510 MutableArrayRef<int> Mask,
8511 const X86Subtarget *Subtarget,
8512 SelectionDAG &DAG) {
8513 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8514 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8515 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8516 for (int i = 0; i < 8; ++i)
8517 if (Mask[i] >= 0 && Mask[i] < 4)
8518 LoV1Inputs.push_back(i);
8519 else if (Mask[i] >= 4 && Mask[i] < 8)
8520 HiV1Inputs.push_back(i);
8521 else if (Mask[i] >= 8 && Mask[i] < 12)
8522 LoV2Inputs.push_back(i);
8523 else if (Mask[i] >= 12)
8524 HiV2Inputs.push_back(i);
8526 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8527 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8530 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8531 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8532 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8534 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8535 HiV1Inputs.size() + HiV2Inputs.size();
8537 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8538 ArrayRef<int> HiInputs, bool MoveToLo,
8540 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8541 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8542 if (BadInputs.empty())
8545 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8546 int MoveOffset = MoveToLo ? 0 : 4;
8548 if (GoodInputs.empty()) {
8549 for (int BadInput : BadInputs) {
8550 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8551 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8554 if (GoodInputs.size() == 2) {
8555 // If the low inputs are spread across two dwords, pack them into
8557 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8558 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8559 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8560 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8562 // Otherwise pin the good inputs.
8563 for (int GoodInput : GoodInputs)
8564 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8567 if (BadInputs.size() == 2) {
8568 // If we have two bad inputs then there may be either one or two good
8569 // inputs fixed in place. Find a fixed input, and then find the *other*
8570 // two adjacent indices by using modular arithmetic.
8572 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8573 [](int M) { return M >= 0; }) -
8574 std::begin(MoveMask);
8576 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8577 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8578 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8579 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8580 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8581 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8582 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8584 assert(BadInputs.size() == 1 && "All sizes handled");
8585 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8586 std::end(MoveMask), -1) -
8587 std::begin(MoveMask);
8588 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8589 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8593 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8596 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8598 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8601 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8602 // cross-half traffic in the final shuffle.
8604 // Munge the mask to be a single-input mask after the unpack merges the
8608 M = 2 * (M % 4) + (M / 8);
8610 return DAG.getVectorShuffle(
8611 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8612 DL, MVT::v8i16, V1, V2),
8613 DAG.getUNDEF(MVT::v8i16), Mask);
8616 /// \brief Generic lowering of 8-lane i16 shuffles.
8618 /// This handles both single-input shuffles and combined shuffle/blends with
8619 /// two inputs. The single input shuffles are immediately delegated to
8620 /// a dedicated lowering routine.
8622 /// The blends are lowered in one of three fundamental ways. If there are few
8623 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8624 /// of the input is significantly cheaper when lowered as an interleaving of
8625 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8626 /// halves of the inputs separately (making them have relatively few inputs)
8627 /// and then concatenate them.
8628 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8629 const X86Subtarget *Subtarget,
8630 SelectionDAG &DAG) {
8632 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8633 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8634 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8635 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8636 ArrayRef<int> OrigMask = SVOp->getMask();
8637 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8638 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8639 MutableArrayRef<int> Mask(MaskStorage);
8641 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8643 // Whenever we can lower this as a zext, that instruction is strictly faster
8644 // than any alternative.
8645 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8646 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8649 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8650 auto isV2 = [](int M) { return M >= 8; };
8652 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8653 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8655 if (NumV2Inputs == 0)
8656 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8658 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8659 "to be V1-input shuffles.");
8661 // There are special ways we can lower some single-element blends.
8662 if (NumV2Inputs == 1)
8663 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8664 Mask, Subtarget, DAG))
8667 if (Subtarget->hasSSE41())
8669 lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8672 // Try to use rotation instructions if available.
8673 if (Subtarget->hasSSSE3())
8674 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8677 if (NumV1Inputs + NumV2Inputs <= 4)
8678 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8680 // Check whether an interleaving lowering is likely to be more efficient.
8681 // This isn't perfect but it is a strong heuristic that tends to work well on
8682 // the kinds of shuffles that show up in practice.
8684 // FIXME: Handle 1x, 2x, and 4x interleaving.
8685 if (shouldLowerAsInterleaving(Mask)) {
8686 // FIXME: Figure out whether we should pack these into the low or high
8689 int EMask[8], OMask[8];
8690 for (int i = 0; i < 4; ++i) {
8691 EMask[i] = Mask[2*i];
8692 OMask[i] = Mask[2*i + 1];
8697 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8698 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8700 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8703 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8704 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8706 for (int i = 0; i < 4; ++i) {
8707 LoBlendMask[i] = Mask[i];
8708 HiBlendMask[i] = Mask[i + 4];
8711 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8712 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8713 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8714 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8716 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8717 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8720 /// \brief Check whether a compaction lowering can be done by dropping even
8721 /// elements and compute how many times even elements must be dropped.
8723 /// This handles shuffles which take every Nth element where N is a power of
8724 /// two. Example shuffle masks:
8726 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8727 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8728 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8729 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8730 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8731 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8733 /// Any of these lanes can of course be undef.
8735 /// This routine only supports N <= 3.
8736 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8739 /// \returns N above, or the number of times even elements must be dropped if
8740 /// there is such a number. Otherwise returns zero.
8741 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8742 // Figure out whether we're looping over two inputs or just one.
8743 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8745 // The modulus for the shuffle vector entries is based on whether this is
8746 // a single input or not.
8747 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8748 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8749 "We should only be called with masks with a power-of-2 size!");
8751 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8753 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8754 // and 2^3 simultaneously. This is because we may have ambiguity with
8755 // partially undef inputs.
8756 bool ViableForN[3] = {true, true, true};
8758 for (int i = 0, e = Mask.size(); i < e; ++i) {
8759 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8764 bool IsAnyViable = false;
8765 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8766 if (ViableForN[j]) {
8769 // The shuffle mask must be equal to (i * 2^N) % M.
8770 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8773 ViableForN[j] = false;
8775 // Early exit if we exhaust the possible powers of two.
8780 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8784 // Return 0 as there is no viable power of two.
8788 /// \brief Generic lowering of v16i8 shuffles.
8790 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8791 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8792 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8793 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8795 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8796 const X86Subtarget *Subtarget,
8797 SelectionDAG &DAG) {
8799 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8800 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8801 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8802 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8803 ArrayRef<int> OrigMask = SVOp->getMask();
8804 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8806 // Try to use rotation instructions if available.
8807 if (Subtarget->hasSSSE3())
8808 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8812 // Try to use a zext lowering.
8813 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8814 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8817 int MaskStorage[16] = {
8818 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8819 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8820 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8821 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8822 MutableArrayRef<int> Mask(MaskStorage);
8823 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8824 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8827 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8829 // For single-input shuffles, there are some nicer lowering tricks we can use.
8830 if (NumV2Elements == 0) {
8831 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8832 // Notably, this handles splat and partial-splat shuffles more efficiently.
8833 // However, it only makes sense if the pre-duplication shuffle simplifies
8834 // things significantly. Currently, this means we need to be able to
8835 // express the pre-duplication shuffle as an i16 shuffle.
8837 // FIXME: We should check for other patterns which can be widened into an
8838 // i16 shuffle as well.
8839 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8840 for (int i = 0; i < 16; i += 2)
8841 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8846 auto tryToWidenViaDuplication = [&]() -> SDValue {
8847 if (!canWidenViaDuplication(Mask))
8849 SmallVector<int, 4> LoInputs;
8850 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8851 [](int M) { return M >= 0 && M < 8; });
8852 std::sort(LoInputs.begin(), LoInputs.end());
8853 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8855 SmallVector<int, 4> HiInputs;
8856 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8857 [](int M) { return M >= 8; });
8858 std::sort(HiInputs.begin(), HiInputs.end());
8859 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8862 bool TargetLo = LoInputs.size() >= HiInputs.size();
8863 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8864 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8866 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8867 SmallDenseMap<int, int, 8> LaneMap;
8868 for (int I : InPlaceInputs) {
8869 PreDupI16Shuffle[I/2] = I/2;
8872 int j = TargetLo ? 0 : 4, je = j + 4;
8873 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8874 // Check if j is already a shuffle of this input. This happens when
8875 // there are two adjacent bytes after we move the low one.
8876 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8877 // If we haven't yet mapped the input, search for a slot into which
8879 while (j < je && PreDupI16Shuffle[j] != -1)
8883 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8886 // Map this input with the i16 shuffle.
8887 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8890 // Update the lane map based on the mapping we ended up with.
8891 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8894 ISD::BITCAST, DL, MVT::v16i8,
8895 DAG.getVectorShuffle(MVT::v8i16, DL,
8896 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8897 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8899 // Unpack the bytes to form the i16s that will be shuffled into place.
8900 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8901 MVT::v16i8, V1, V1);
8903 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8904 for (int i = 0; i < 16; i += 2) {
8906 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8907 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8910 ISD::BITCAST, DL, MVT::v16i8,
8911 DAG.getVectorShuffle(MVT::v8i16, DL,
8912 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8913 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8915 if (SDValue V = tryToWidenViaDuplication())
8919 // Check whether an interleaving lowering is likely to be more efficient.
8920 // This isn't perfect but it is a strong heuristic that tends to work well on
8921 // the kinds of shuffles that show up in practice.
8923 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8924 if (shouldLowerAsInterleaving(Mask)) {
8925 // FIXME: Figure out whether we should pack these into the low or high
8928 int EMask[16], OMask[16];
8929 for (int i = 0; i < 8; ++i) {
8930 EMask[i] = Mask[2*i];
8931 OMask[i] = Mask[2*i + 1];
8936 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8937 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8939 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8942 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8943 // with PSHUFB. It is important to do this before we attempt to generate any
8944 // blends but after all of the single-input lowerings. If the single input
8945 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8946 // want to preserve that and we can DAG combine any longer sequences into
8947 // a PSHUFB in the end. But once we start blending from multiple inputs,
8948 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8949 // and there are *very* few patterns that would actually be faster than the
8950 // PSHUFB approach because of its ability to zero lanes.
8952 // FIXME: The only exceptions to the above are blends which are exact
8953 // interleavings with direct instructions supporting them. We currently don't
8954 // handle those well here.
8955 if (Subtarget->hasSSSE3()) {
8958 for (int i = 0; i < 16; ++i)
8959 if (Mask[i] == -1) {
8960 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8962 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8964 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8966 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8967 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8968 if (isSingleInputShuffleMask(Mask))
8969 return V1; // Single inputs are easy.
8971 // Otherwise, blend the two.
8972 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8973 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8974 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8977 // There are special ways we can lower some single-element blends.
8978 if (NumV2Elements == 1)
8979 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
8980 Mask, Subtarget, DAG))
8983 // Check whether a compaction lowering can be done. This handles shuffles
8984 // which take every Nth element for some even N. See the helper function for
8987 // We special case these as they can be particularly efficiently handled with
8988 // the PACKUSB instruction on x86 and they show up in common patterns of
8989 // rearranging bytes to truncate wide elements.
8990 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8991 // NumEvenDrops is the power of two stride of the elements. Another way of
8992 // thinking about it is that we need to drop the even elements this many
8993 // times to get the original input.
8994 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8996 // First we need to zero all the dropped bytes.
8997 assert(NumEvenDrops <= 3 &&
8998 "No support for dropping even elements more than 3 times.");
8999 // We use the mask type to pick which bytes are preserved based on how many
9000 // elements are dropped.
9001 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9002 SDValue ByteClearMask =
9003 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9004 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9005 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9007 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9009 // Now pack things back together.
9010 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9011 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9012 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9013 for (int i = 1; i < NumEvenDrops; ++i) {
9014 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9015 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9021 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9022 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9023 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9024 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9026 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9027 MutableArrayRef<int> V1HalfBlendMask,
9028 MutableArrayRef<int> V2HalfBlendMask) {
9029 for (int i = 0; i < 8; ++i)
9030 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9031 V1HalfBlendMask[i] = HalfMask[i];
9033 } else if (HalfMask[i] >= 16) {
9034 V2HalfBlendMask[i] = HalfMask[i] - 16;
9035 HalfMask[i] = i + 8;
9038 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9039 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9041 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9043 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9044 MutableArrayRef<int> HiBlendMask) {
9046 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9047 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9049 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9050 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9051 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9052 [](int M) { return M >= 0 && M % 2 == 1; })) {
9053 // Use a mask to drop the high bytes.
9054 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9055 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9056 DAG.getConstant(0x00FF, MVT::v8i16));
9058 // This will be a single vector shuffle instead of a blend so nuke V2.
9059 V2 = DAG.getUNDEF(MVT::v8i16);
9061 // Squash the masks to point directly into V1.
9062 for (int &M : LoBlendMask)
9065 for (int &M : HiBlendMask)
9069 // Otherwise just unpack the low half of V into V1 and the high half into
9070 // V2 so that we can blend them as i16s.
9071 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9072 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9073 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9074 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9077 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9078 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9079 return std::make_pair(BlendedLo, BlendedHi);
9081 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9082 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9083 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9085 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9086 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9088 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9091 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9093 /// This routine breaks down the specific type of 128-bit shuffle and
9094 /// dispatches to the lowering routines accordingly.
9095 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9096 MVT VT, const X86Subtarget *Subtarget,
9097 SelectionDAG &DAG) {
9098 switch (VT.SimpleTy) {
9100 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9102 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9104 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9106 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9108 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9110 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9113 llvm_unreachable("Unimplemented!");
9117 /// \brief Test whether there are elements crossing 128-bit lanes in this
9120 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
9121 /// and we routinely test for these.
9122 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
9123 int LaneSize = 128 / VT.getScalarSizeInBits();
9124 int Size = Mask.size();
9125 for (int i = 0; i < Size; ++i)
9126 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9131 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9134 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9135 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9136 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9137 /// we encode the logic here for specific shuffle lowering routines to bail to
9138 /// when they exhaust the features avaible to more directly handle the shuffle.
9139 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9141 const X86Subtarget *Subtarget,
9142 SelectionDAG &DAG) {
9144 MVT VT = Op.getSimpleValueType();
9145 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9146 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9147 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9148 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9149 ArrayRef<int> Mask = SVOp->getMask();
9151 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9152 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9154 int NumElements = VT.getVectorNumElements();
9155 int SplitNumElements = NumElements / 2;
9156 MVT ScalarVT = VT.getScalarType();
9157 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9159 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9160 DAG.getIntPtrConstant(0));
9161 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9162 DAG.getIntPtrConstant(SplitNumElements));
9163 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9164 DAG.getIntPtrConstant(0));
9165 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9166 DAG.getIntPtrConstant(SplitNumElements));
9168 // Now create two 4-way blends of these half-width vectors.
9169 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9170 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9171 for (int i = 0; i < SplitNumElements; ++i) {
9172 int M = HalfMask[i];
9173 if (M >= NumElements) {
9174 V2BlendMask.push_back(M - NumElements);
9175 V1BlendMask.push_back(-1);
9176 BlendMask.push_back(SplitNumElements + i);
9177 } else if (M >= 0) {
9178 V2BlendMask.push_back(-1);
9179 V1BlendMask.push_back(M);
9180 BlendMask.push_back(i);
9182 V2BlendMask.push_back(-1);
9183 V1BlendMask.push_back(-1);
9184 BlendMask.push_back(-1);
9187 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9188 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9189 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9191 SDValue Lo = HalfBlend(LoMask);
9192 SDValue Hi = HalfBlend(HiMask);
9193 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9196 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9198 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9199 /// isn't available.
9200 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9201 const X86Subtarget *Subtarget,
9202 SelectionDAG &DAG) {
9204 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9205 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9206 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9207 ArrayRef<int> Mask = SVOp->getMask();
9208 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9210 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9211 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9213 if (isSingleInputShuffleMask(Mask)) {
9214 // Non-half-crossing single input shuffles can be lowerid with an
9215 // interleaved permutation.
9216 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9217 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9218 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
9219 DAG.getConstant(VPERMILPMask, MVT::i8));
9222 // X86 has dedicated unpack instructions that can handle specific blend
9223 // operations: UNPCKH and UNPCKL.
9224 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9225 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9226 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9227 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9228 if (isShuffleEquivalent(Mask, 4, 0, 6, 2))
9229 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9230 if (isShuffleEquivalent(Mask, 5, 1, 7, 3))
9231 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9234 lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask, DAG))
9237 // Check if the blend happens to exactly fit that of SHUFPD.
9238 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9239 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9240 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9241 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9242 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9243 DAG.getConstant(SHUFPDMask, MVT::i8));
9245 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9246 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9247 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9248 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9249 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9250 DAG.getConstant(SHUFPDMask, MVT::i8));
9253 // Shuffle the input elements into the desired positions in V1 and V2 and
9254 // blend them together.
9255 int V1Mask[] = {-1, -1, -1, -1};
9256 int V2Mask[] = {-1, -1, -1, -1};
9257 for (int i = 0; i < 4; ++i)
9258 if (Mask[i] >= 0 && Mask[i] < 4)
9259 V1Mask[i] = Mask[i];
9260 else if (Mask[i] >= 4)
9261 V2Mask[i] = Mask[i] - 4;
9263 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9264 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9266 unsigned BlendMask = 0;
9267 for (int i = 0; i < 4; ++i)
9269 BlendMask |= 1 << i;
9271 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9272 DAG.getConstant(BlendMask, MVT::i8));
9275 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9277 /// Largely delegates to common code when we have AVX2 and to the floating-point
9278 /// code when we only have AVX.
9279 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9280 const X86Subtarget *Subtarget,
9281 SelectionDAG &DAG) {
9283 assert(Op.getSimpleValueType() == MVT::v4i64 && "Bad shuffle type!");
9284 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9285 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9286 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9287 ArrayRef<int> Mask = SVOp->getMask();
9288 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9290 // FIXME: If we have AVX2, we should delegate to generic code as crossing
9291 // shuffles aren't a problem and FP and int have the same patterns.
9293 if (is128BitLaneCrossingShuffleMask(MVT::v4i64, Mask))
9294 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9296 // AVX1 doesn't provide any facilities for v4i64 shuffles, bitcast and
9297 // delegate to floating point code.
9298 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
9299 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
9300 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
9301 lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG));
9304 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9306 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9307 /// isn't available.
9308 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9309 const X86Subtarget *Subtarget,
9310 SelectionDAG &DAG) {
9312 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9313 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9314 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9315 ArrayRef<int> Mask = SVOp->getMask();
9316 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9318 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask) ||
9319 isSingleInputShuffleMask(Mask))
9320 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9322 // Shuffle the input elements into the desired positions in V1 and V2 and
9323 // blend them together.
9324 int V1Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9325 int V2Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9326 unsigned BlendMask = 0;
9327 for (int i = 0; i < 8; ++i)
9328 if (Mask[i] >= 0 && Mask[i] < 8) {
9329 V1Mask[i] = Mask[i];
9330 } else if (Mask[i] >= 8) {
9331 V2Mask[i] = Mask[i] - 8;
9332 BlendMask |= 1 << i;
9335 V1 = DAG.getVectorShuffle(MVT::v8f32, DL, V1, DAG.getUNDEF(MVT::v8f32), V1Mask);
9336 V2 = DAG.getVectorShuffle(MVT::v8f32, DL, V2, DAG.getUNDEF(MVT::v8f32), V2Mask);
9338 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v8f32, V1, V2,
9339 DAG.getConstant(BlendMask, MVT::i8));
9342 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9344 /// This routine either breaks down the specific type of a 256-bit x86 vector
9345 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9346 /// together based on the available instructions.
9347 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9348 MVT VT, const X86Subtarget *Subtarget,
9349 SelectionDAG &DAG) {
9350 switch (VT.SimpleTy) {
9352 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9354 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9356 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9360 // Fall back to the basic pattern of extracting the high half and forming
9362 // FIXME: Add targeted lowering for each type that can document rationale
9363 // for delegating to this when necessary.
9364 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9367 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9371 /// \brief Tiny helper function to test whether a shuffle mask could be
9372 /// simplified by widening the elements being shuffled.
9373 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9374 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9375 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9376 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9377 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9383 /// \brief Top-level lowering for x86 vector shuffles.
9385 /// This handles decomposition, canonicalization, and lowering of all x86
9386 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9387 /// above in helper routines. The canonicalization attempts to widen shuffles
9388 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9389 /// s.t. only one of the two inputs needs to be tested, etc.
9390 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9391 SelectionDAG &DAG) {
9392 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9393 ArrayRef<int> Mask = SVOp->getMask();
9394 SDValue V1 = Op.getOperand(0);
9395 SDValue V2 = Op.getOperand(1);
9396 MVT VT = Op.getSimpleValueType();
9397 int NumElements = VT.getVectorNumElements();
9400 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9402 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9403 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9404 if (V1IsUndef && V2IsUndef)
9405 return DAG.getUNDEF(VT);
9407 // When we create a shuffle node we put the UNDEF node to second operand,
9408 // but in some cases the first operand may be transformed to UNDEF.
9409 // In this case we should just commute the node.
9411 return DAG.getCommutedVectorShuffle(*SVOp);
9413 // Check for non-undef masks pointing at an undef vector and make the masks
9414 // undef as well. This makes it easier to match the shuffle based solely on
9418 if (M >= NumElements) {
9419 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9420 for (int &M : NewMask)
9421 if (M >= NumElements)
9423 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9426 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9427 // lanes but wider integers. We cap this to not form integers larger than i64
9428 // but it might be interesting to form i128 integers to handle flipping the
9429 // low and high halves of AVX 256-bit vectors.
9430 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9431 canWidenShuffleElements(Mask)) {
9432 SmallVector<int, 8> NewMask;
9433 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9434 NewMask.push_back(Mask[i] != -1
9436 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9438 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9439 VT.getVectorNumElements() / 2);
9440 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9441 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9442 return DAG.getNode(ISD::BITCAST, dl, VT,
9443 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9446 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9447 for (int M : SVOp->getMask())
9450 else if (M < NumElements)
9455 // Commute the shuffle as needed such that more elements come from V1 than
9456 // V2. This allows us to match the shuffle pattern strictly on how many
9457 // elements come from V1 without handling the symmetric cases.
9458 if (NumV2Elements > NumV1Elements)
9459 return DAG.getCommutedVectorShuffle(*SVOp);
9461 // When the number of V1 and V2 elements are the same, try to minimize the
9462 // number of uses of V2 in the low half of the vector.
9463 if (NumV1Elements == NumV2Elements) {
9464 int LowV1Elements = 0, LowV2Elements = 0;
9465 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9466 if (M >= NumElements)
9470 if (LowV2Elements > LowV1Elements)
9471 return DAG.getCommutedVectorShuffle(*SVOp);
9474 // For each vector width, delegate to a specialized lowering routine.
9475 if (VT.getSizeInBits() == 128)
9476 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9478 if (VT.getSizeInBits() == 256)
9479 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9481 llvm_unreachable("Unimplemented!");
9485 //===----------------------------------------------------------------------===//
9486 // Legacy vector shuffle lowering
9488 // This code is the legacy code handling vector shuffles until the above
9489 // replaces its functionality and performance.
9490 //===----------------------------------------------------------------------===//
9492 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9493 bool hasInt256, unsigned *MaskOut = nullptr) {
9494 MVT EltVT = VT.getVectorElementType();
9496 // There is no blend with immediate in AVX-512.
9497 if (VT.is512BitVector())
9500 if (!hasSSE41 || EltVT == MVT::i8)
9502 if (!hasInt256 && VT == MVT::v16i16)
9505 unsigned MaskValue = 0;
9506 unsigned NumElems = VT.getVectorNumElements();
9507 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9508 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9509 unsigned NumElemsInLane = NumElems / NumLanes;
9511 // Blend for v16i16 should be symetric for the both lanes.
9512 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9514 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9515 int EltIdx = MaskVals[i];
9517 if ((EltIdx < 0 || EltIdx == (int)i) &&
9518 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9521 if (((unsigned)EltIdx == (i + NumElems)) &&
9522 (SndLaneEltIdx < 0 ||
9523 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9524 MaskValue |= (1 << i);
9530 *MaskOut = MaskValue;
9534 // Try to lower a shuffle node into a simple blend instruction.
9535 // This function assumes isBlendMask returns true for this
9536 // SuffleVectorSDNode
9537 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9539 const X86Subtarget *Subtarget,
9540 SelectionDAG &DAG) {
9541 MVT VT = SVOp->getSimpleValueType(0);
9542 MVT EltVT = VT.getVectorElementType();
9543 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9544 Subtarget->hasInt256() && "Trying to lower a "
9545 "VECTOR_SHUFFLE to a Blend but "
9546 "with the wrong mask"));
9547 SDValue V1 = SVOp->getOperand(0);
9548 SDValue V2 = SVOp->getOperand(1);
9550 unsigned NumElems = VT.getVectorNumElements();
9552 // Convert i32 vectors to floating point if it is not AVX2.
9553 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9555 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9556 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9558 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9559 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9562 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9563 DAG.getConstant(MaskValue, MVT::i32));
9564 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9567 /// In vector type \p VT, return true if the element at index \p InputIdx
9568 /// falls on a different 128-bit lane than \p OutputIdx.
9569 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9570 unsigned OutputIdx) {
9571 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9572 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9575 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9576 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9577 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9578 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9580 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9581 SelectionDAG &DAG) {
9582 MVT VT = V1.getSimpleValueType();
9583 assert(VT.is128BitVector() || VT.is256BitVector());
9585 MVT EltVT = VT.getVectorElementType();
9586 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9587 unsigned NumElts = VT.getVectorNumElements();
9589 SmallVector<SDValue, 32> PshufbMask;
9590 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9591 int InputIdx = MaskVals[OutputIdx];
9592 unsigned InputByteIdx;
9594 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9595 InputByteIdx = 0x80;
9597 // Cross lane is not allowed.
9598 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9600 InputByteIdx = InputIdx * EltSizeInBytes;
9601 // Index is an byte offset within the 128-bit lane.
9602 InputByteIdx &= 0xf;
9605 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9606 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9607 if (InputByteIdx != 0x80)
9612 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9614 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9615 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9616 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9619 // v8i16 shuffles - Prefer shuffles in the following order:
9620 // 1. [all] pshuflw, pshufhw, optional move
9621 // 2. [ssse3] 1 x pshufb
9622 // 3. [ssse3] 2 x pshufb + 1 x por
9623 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9625 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9626 SelectionDAG &DAG) {
9627 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9628 SDValue V1 = SVOp->getOperand(0);
9629 SDValue V2 = SVOp->getOperand(1);
9631 SmallVector<int, 8> MaskVals;
9633 // Determine if more than 1 of the words in each of the low and high quadwords
9634 // of the result come from the same quadword of one of the two inputs. Undef
9635 // mask values count as coming from any quadword, for better codegen.
9637 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9638 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9639 unsigned LoQuad[] = { 0, 0, 0, 0 };
9640 unsigned HiQuad[] = { 0, 0, 0, 0 };
9641 // Indices of quads used.
9642 std::bitset<4> InputQuads;
9643 for (unsigned i = 0; i < 8; ++i) {
9644 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9645 int EltIdx = SVOp->getMaskElt(i);
9646 MaskVals.push_back(EltIdx);
9655 InputQuads.set(EltIdx / 4);
9658 int BestLoQuad = -1;
9659 unsigned MaxQuad = 1;
9660 for (unsigned i = 0; i < 4; ++i) {
9661 if (LoQuad[i] > MaxQuad) {
9663 MaxQuad = LoQuad[i];
9667 int BestHiQuad = -1;
9669 for (unsigned i = 0; i < 4; ++i) {
9670 if (HiQuad[i] > MaxQuad) {
9672 MaxQuad = HiQuad[i];
9676 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9677 // of the two input vectors, shuffle them into one input vector so only a
9678 // single pshufb instruction is necessary. If there are more than 2 input
9679 // quads, disable the next transformation since it does not help SSSE3.
9680 bool V1Used = InputQuads[0] || InputQuads[1];
9681 bool V2Used = InputQuads[2] || InputQuads[3];
9682 if (Subtarget->hasSSSE3()) {
9683 if (InputQuads.count() == 2 && V1Used && V2Used) {
9684 BestLoQuad = InputQuads[0] ? 0 : 1;
9685 BestHiQuad = InputQuads[2] ? 2 : 3;
9687 if (InputQuads.count() > 2) {
9693 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9694 // the shuffle mask. If a quad is scored as -1, that means that it contains
9695 // words from all 4 input quadwords.
9697 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9699 BestLoQuad < 0 ? 0 : BestLoQuad,
9700 BestHiQuad < 0 ? 1 : BestHiQuad
9702 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9703 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9704 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9705 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9707 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9708 // source words for the shuffle, to aid later transformations.
9709 bool AllWordsInNewV = true;
9710 bool InOrder[2] = { true, true };
9711 for (unsigned i = 0; i != 8; ++i) {
9712 int idx = MaskVals[i];
9714 InOrder[i/4] = false;
9715 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9717 AllWordsInNewV = false;
9721 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9722 if (AllWordsInNewV) {
9723 for (int i = 0; i != 8; ++i) {
9724 int idx = MaskVals[i];
9727 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9728 if ((idx != i) && idx < 4)
9730 if ((idx != i) && idx > 3)
9739 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9740 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9741 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9742 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9743 unsigned TargetMask = 0;
9744 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9745 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9746 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9747 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9748 getShufflePSHUFLWImmediate(SVOp);
9749 V1 = NewV.getOperand(0);
9750 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9754 // Promote splats to a larger type which usually leads to more efficient code.
9755 // FIXME: Is this true if pshufb is available?
9756 if (SVOp->isSplat())
9757 return PromoteSplat(SVOp, DAG);
9759 // If we have SSSE3, and all words of the result are from 1 input vector,
9760 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9761 // is present, fall back to case 4.
9762 if (Subtarget->hasSSSE3()) {
9763 SmallVector<SDValue,16> pshufbMask;
9765 // If we have elements from both input vectors, set the high bit of the
9766 // shuffle mask element to zero out elements that come from V2 in the V1
9767 // mask, and elements that come from V1 in the V2 mask, so that the two
9768 // results can be OR'd together.
9769 bool TwoInputs = V1Used && V2Used;
9770 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9772 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9774 // Calculate the shuffle mask for the second input, shuffle it, and
9775 // OR it with the first shuffled input.
9776 CommuteVectorShuffleMask(MaskVals, 8);
9777 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9778 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9779 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9782 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9783 // and update MaskVals with new element order.
9784 std::bitset<8> InOrder;
9785 if (BestLoQuad >= 0) {
9786 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9787 for (int i = 0; i != 4; ++i) {
9788 int idx = MaskVals[i];
9791 } else if ((idx / 4) == BestLoQuad) {
9796 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9799 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9800 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9801 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9803 getShufflePSHUFLWImmediate(SVOp), DAG);
9807 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9808 // and update MaskVals with the new element order.
9809 if (BestHiQuad >= 0) {
9810 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9811 for (unsigned i = 4; i != 8; ++i) {
9812 int idx = MaskVals[i];
9815 } else if ((idx / 4) == BestHiQuad) {
9816 MaskV[i] = (idx & 3) + 4;
9820 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9823 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9824 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9825 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
9827 getShufflePSHUFHWImmediate(SVOp), DAG);
9831 // In case BestHi & BestLo were both -1, which means each quadword has a word
9832 // from each of the four input quadwords, calculate the InOrder bitvector now
9833 // before falling through to the insert/extract cleanup.
9834 if (BestLoQuad == -1 && BestHiQuad == -1) {
9836 for (int i = 0; i != 8; ++i)
9837 if (MaskVals[i] < 0 || MaskVals[i] == i)
9841 // The other elements are put in the right place using pextrw and pinsrw.
9842 for (unsigned i = 0; i != 8; ++i) {
9845 int EltIdx = MaskVals[i];
9848 SDValue ExtOp = (EltIdx < 8) ?
9849 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
9850 DAG.getIntPtrConstant(EltIdx)) :
9851 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
9852 DAG.getIntPtrConstant(EltIdx - 8));
9853 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
9854 DAG.getIntPtrConstant(i));
9859 /// \brief v16i16 shuffles
9861 /// FIXME: We only support generation of a single pshufb currently. We can
9862 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
9863 /// well (e.g 2 x pshufb + 1 x por).
9865 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
9866 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9867 SDValue V1 = SVOp->getOperand(0);
9868 SDValue V2 = SVOp->getOperand(1);
9871 if (V2.getOpcode() != ISD::UNDEF)
9874 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9875 return getPSHUFB(MaskVals, V1, dl, DAG);
9878 // v16i8 shuffles - Prefer shuffles in the following order:
9879 // 1. [ssse3] 1 x pshufb
9880 // 2. [ssse3] 2 x pshufb + 1 x por
9881 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
9882 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
9883 const X86Subtarget* Subtarget,
9884 SelectionDAG &DAG) {
9885 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9886 SDValue V1 = SVOp->getOperand(0);
9887 SDValue V2 = SVOp->getOperand(1);
9889 ArrayRef<int> MaskVals = SVOp->getMask();
9891 // Promote splats to a larger type which usually leads to more efficient code.
9892 // FIXME: Is this true if pshufb is available?
9893 if (SVOp->isSplat())
9894 return PromoteSplat(SVOp, DAG);
9896 // If we have SSSE3, case 1 is generated when all result bytes come from
9897 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
9898 // present, fall back to case 3.
9900 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
9901 if (Subtarget->hasSSSE3()) {
9902 SmallVector<SDValue,16> pshufbMask;
9904 // If all result elements are from one input vector, then only translate
9905 // undef mask values to 0x80 (zero out result) in the pshufb mask.
9907 // Otherwise, we have elements from both input vectors, and must zero out
9908 // elements that come from V2 in the first mask, and V1 in the second mask
9909 // so that we can OR them together.
9910 for (unsigned i = 0; i != 16; ++i) {
9911 int EltIdx = MaskVals[i];
9912 if (EltIdx < 0 || EltIdx >= 16)
9914 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9916 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
9917 DAG.getNode(ISD::BUILD_VECTOR, dl,
9918 MVT::v16i8, pshufbMask));
9920 // As PSHUFB will zero elements with negative indices, it's safe to ignore
9921 // the 2nd operand if it's undefined or zero.
9922 if (V2.getOpcode() == ISD::UNDEF ||
9923 ISD::isBuildVectorAllZeros(V2.getNode()))
9926 // Calculate the shuffle mask for the second input, shuffle it, and
9927 // OR it with the first shuffled input.
9929 for (unsigned i = 0; i != 16; ++i) {
9930 int EltIdx = MaskVals[i];
9931 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
9932 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9934 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
9935 DAG.getNode(ISD::BUILD_VECTOR, dl,
9936 MVT::v16i8, pshufbMask));
9937 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9940 // No SSSE3 - Calculate in place words and then fix all out of place words
9941 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
9942 // the 16 different words that comprise the two doublequadword input vectors.
9943 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9944 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
9946 for (int i = 0; i != 8; ++i) {
9947 int Elt0 = MaskVals[i*2];
9948 int Elt1 = MaskVals[i*2+1];
9950 // This word of the result is all undef, skip it.
9951 if (Elt0 < 0 && Elt1 < 0)
9954 // This word of the result is already in the correct place, skip it.
9955 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9958 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9959 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9962 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9963 // using a single extract together, load it and store it.
9964 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9965 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9966 DAG.getIntPtrConstant(Elt1 / 2));
9967 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9968 DAG.getIntPtrConstant(i));
9972 // If Elt1 is defined, extract it from the appropriate source. If the
9973 // source byte is not also odd, shift the extracted word left 8 bits
9974 // otherwise clear the bottom 8 bits if we need to do an or.
9976 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9977 DAG.getIntPtrConstant(Elt1 / 2));
9978 if ((Elt1 & 1) == 0)
9979 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9981 TLI.getShiftAmountTy(InsElt.getValueType())));
9983 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9984 DAG.getConstant(0xFF00, MVT::i16));
9986 // If Elt0 is defined, extract it from the appropriate source. If the
9987 // source byte is not also even, shift the extracted word right 8 bits. If
9988 // Elt1 was also defined, OR the extracted values together before
9989 // inserting them in the result.
9991 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9992 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9993 if ((Elt0 & 1) != 0)
9994 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9996 TLI.getShiftAmountTy(InsElt0.getValueType())));
9998 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9999 DAG.getConstant(0x00FF, MVT::i16));
10000 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10003 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10004 DAG.getIntPtrConstant(i));
10006 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10009 // v32i8 shuffles - Translate to VPSHUFB if possible.
10011 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10012 const X86Subtarget *Subtarget,
10013 SelectionDAG &DAG) {
10014 MVT VT = SVOp->getSimpleValueType(0);
10015 SDValue V1 = SVOp->getOperand(0);
10016 SDValue V2 = SVOp->getOperand(1);
10018 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10020 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10021 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10022 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10024 // VPSHUFB may be generated if
10025 // (1) one of input vector is undefined or zeroinitializer.
10026 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10027 // And (2) the mask indexes don't cross the 128-bit lane.
10028 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10029 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10032 if (V1IsAllZero && !V2IsAllZero) {
10033 CommuteVectorShuffleMask(MaskVals, 32);
10036 return getPSHUFB(MaskVals, V1, dl, DAG);
10039 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10040 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10041 /// done when every pair / quad of shuffle mask elements point to elements in
10042 /// the right sequence. e.g.
10043 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10045 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10046 SelectionDAG &DAG) {
10047 MVT VT = SVOp->getSimpleValueType(0);
10049 unsigned NumElems = VT.getVectorNumElements();
10052 switch (VT.SimpleTy) {
10053 default: llvm_unreachable("Unexpected!");
10056 return SDValue(SVOp, 0);
10057 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10058 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10059 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10060 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10061 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10062 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10065 SmallVector<int, 8> MaskVec;
10066 for (unsigned i = 0; i != NumElems; i += Scale) {
10068 for (unsigned j = 0; j != Scale; ++j) {
10069 int EltIdx = SVOp->getMaskElt(i+j);
10073 StartIdx = (EltIdx / Scale);
10074 if (EltIdx != (int)(StartIdx*Scale + j))
10077 MaskVec.push_back(StartIdx);
10080 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10081 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10082 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10085 /// getVZextMovL - Return a zero-extending vector move low node.
10087 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10088 SDValue SrcOp, SelectionDAG &DAG,
10089 const X86Subtarget *Subtarget, SDLoc dl) {
10090 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10091 LoadSDNode *LD = nullptr;
10092 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10093 LD = dyn_cast<LoadSDNode>(SrcOp);
10095 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10097 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10098 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10099 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10100 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10101 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10103 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10104 return DAG.getNode(ISD::BITCAST, dl, VT,
10105 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10106 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10108 SrcOp.getOperand(0)
10114 return DAG.getNode(ISD::BITCAST, dl, VT,
10115 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10116 DAG.getNode(ISD::BITCAST, dl,
10120 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10121 /// which could not be matched by any known target speficic shuffle
10123 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10125 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10126 if (NewOp.getNode())
10129 MVT VT = SVOp->getSimpleValueType(0);
10131 unsigned NumElems = VT.getVectorNumElements();
10132 unsigned NumLaneElems = NumElems / 2;
10135 MVT EltVT = VT.getVectorElementType();
10136 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10139 SmallVector<int, 16> Mask;
10140 for (unsigned l = 0; l < 2; ++l) {
10141 // Build a shuffle mask for the output, discovering on the fly which
10142 // input vectors to use as shuffle operands (recorded in InputUsed).
10143 // If building a suitable shuffle vector proves too hard, then bail
10144 // out with UseBuildVector set.
10145 bool UseBuildVector = false;
10146 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10147 unsigned LaneStart = l * NumLaneElems;
10148 for (unsigned i = 0; i != NumLaneElems; ++i) {
10149 // The mask element. This indexes into the input.
10150 int Idx = SVOp->getMaskElt(i+LaneStart);
10152 // the mask element does not index into any input vector.
10153 Mask.push_back(-1);
10157 // The input vector this mask element indexes into.
10158 int Input = Idx / NumLaneElems;
10160 // Turn the index into an offset from the start of the input vector.
10161 Idx -= Input * NumLaneElems;
10163 // Find or create a shuffle vector operand to hold this input.
10165 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10166 if (InputUsed[OpNo] == Input)
10167 // This input vector is already an operand.
10169 if (InputUsed[OpNo] < 0) {
10170 // Create a new operand for this input vector.
10171 InputUsed[OpNo] = Input;
10176 if (OpNo >= array_lengthof(InputUsed)) {
10177 // More than two input vectors used! Give up on trying to create a
10178 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10179 UseBuildVector = true;
10183 // Add the mask index for the new shuffle vector.
10184 Mask.push_back(Idx + OpNo * NumLaneElems);
10187 if (UseBuildVector) {
10188 SmallVector<SDValue, 16> SVOps;
10189 for (unsigned i = 0; i != NumLaneElems; ++i) {
10190 // The mask element. This indexes into the input.
10191 int Idx = SVOp->getMaskElt(i+LaneStart);
10193 SVOps.push_back(DAG.getUNDEF(EltVT));
10197 // The input vector this mask element indexes into.
10198 int Input = Idx / NumElems;
10200 // Turn the index into an offset from the start of the input vector.
10201 Idx -= Input * NumElems;
10203 // Extract the vector element by hand.
10204 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10205 SVOp->getOperand(Input),
10206 DAG.getIntPtrConstant(Idx)));
10209 // Construct the output using a BUILD_VECTOR.
10210 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10211 } else if (InputUsed[0] < 0) {
10212 // No input vectors were used! The result is undefined.
10213 Output[l] = DAG.getUNDEF(NVT);
10215 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10216 (InputUsed[0] % 2) * NumLaneElems,
10218 // If only one input was used, use an undefined vector for the other.
10219 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10220 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10221 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10222 // At least one input vector was used. Create a new shuffle vector.
10223 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10229 // Concatenate the result back
10230 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10233 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10234 /// 4 elements, and match them with several different shuffle types.
10236 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10237 SDValue V1 = SVOp->getOperand(0);
10238 SDValue V2 = SVOp->getOperand(1);
10240 MVT VT = SVOp->getSimpleValueType(0);
10242 assert(VT.is128BitVector() && "Unsupported vector size");
10244 std::pair<int, int> Locs[4];
10245 int Mask1[] = { -1, -1, -1, -1 };
10246 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10248 unsigned NumHi = 0;
10249 unsigned NumLo = 0;
10250 for (unsigned i = 0; i != 4; ++i) {
10251 int Idx = PermMask[i];
10253 Locs[i] = std::make_pair(-1, -1);
10255 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10257 Locs[i] = std::make_pair(0, NumLo);
10258 Mask1[NumLo] = Idx;
10261 Locs[i] = std::make_pair(1, NumHi);
10263 Mask1[2+NumHi] = Idx;
10269 if (NumLo <= 2 && NumHi <= 2) {
10270 // If no more than two elements come from either vector. This can be
10271 // implemented with two shuffles. First shuffle gather the elements.
10272 // The second shuffle, which takes the first shuffle as both of its
10273 // vector operands, put the elements into the right order.
10274 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10276 int Mask2[] = { -1, -1, -1, -1 };
10278 for (unsigned i = 0; i != 4; ++i)
10279 if (Locs[i].first != -1) {
10280 unsigned Idx = (i < 2) ? 0 : 4;
10281 Idx += Locs[i].first * 2 + Locs[i].second;
10285 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10288 if (NumLo == 3 || NumHi == 3) {
10289 // Otherwise, we must have three elements from one vector, call it X, and
10290 // one element from the other, call it Y. First, use a shufps to build an
10291 // intermediate vector with the one element from Y and the element from X
10292 // that will be in the same half in the final destination (the indexes don't
10293 // matter). Then, use a shufps to build the final vector, taking the half
10294 // containing the element from Y from the intermediate, and the other half
10297 // Normalize it so the 3 elements come from V1.
10298 CommuteVectorShuffleMask(PermMask, 4);
10302 // Find the element from V2.
10304 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10305 int Val = PermMask[HiIndex];
10312 Mask1[0] = PermMask[HiIndex];
10314 Mask1[2] = PermMask[HiIndex^1];
10316 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10318 if (HiIndex >= 2) {
10319 Mask1[0] = PermMask[0];
10320 Mask1[1] = PermMask[1];
10321 Mask1[2] = HiIndex & 1 ? 6 : 4;
10322 Mask1[3] = HiIndex & 1 ? 4 : 6;
10323 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10326 Mask1[0] = HiIndex & 1 ? 2 : 0;
10327 Mask1[1] = HiIndex & 1 ? 0 : 2;
10328 Mask1[2] = PermMask[2];
10329 Mask1[3] = PermMask[3];
10334 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10337 // Break it into (shuffle shuffle_hi, shuffle_lo).
10338 int LoMask[] = { -1, -1, -1, -1 };
10339 int HiMask[] = { -1, -1, -1, -1 };
10341 int *MaskPtr = LoMask;
10342 unsigned MaskIdx = 0;
10343 unsigned LoIdx = 0;
10344 unsigned HiIdx = 2;
10345 for (unsigned i = 0; i != 4; ++i) {
10352 int Idx = PermMask[i];
10354 Locs[i] = std::make_pair(-1, -1);
10355 } else if (Idx < 4) {
10356 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10357 MaskPtr[LoIdx] = Idx;
10360 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10361 MaskPtr[HiIdx] = Idx;
10366 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10367 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10368 int MaskOps[] = { -1, -1, -1, -1 };
10369 for (unsigned i = 0; i != 4; ++i)
10370 if (Locs[i].first != -1)
10371 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10372 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10375 static bool MayFoldVectorLoad(SDValue V) {
10376 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10377 V = V.getOperand(0);
10379 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10380 V = V.getOperand(0);
10381 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10382 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10383 // BUILD_VECTOR (load), undef
10384 V = V.getOperand(0);
10386 return MayFoldLoad(V);
10390 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10391 MVT VT = Op.getSimpleValueType();
10393 // Canonizalize to v2f64.
10394 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10395 return DAG.getNode(ISD::BITCAST, dl, VT,
10396 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10401 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10403 SDValue V1 = Op.getOperand(0);
10404 SDValue V2 = Op.getOperand(1);
10405 MVT VT = Op.getSimpleValueType();
10407 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10409 if (HasSSE2 && VT == MVT::v2f64)
10410 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10412 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10413 return DAG.getNode(ISD::BITCAST, dl, VT,
10414 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10415 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10416 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10420 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10421 SDValue V1 = Op.getOperand(0);
10422 SDValue V2 = Op.getOperand(1);
10423 MVT VT = Op.getSimpleValueType();
10425 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10426 "unsupported shuffle type");
10428 if (V2.getOpcode() == ISD::UNDEF)
10432 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10436 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10437 SDValue V1 = Op.getOperand(0);
10438 SDValue V2 = Op.getOperand(1);
10439 MVT VT = Op.getSimpleValueType();
10440 unsigned NumElems = VT.getVectorNumElements();
10442 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10443 // operand of these instructions is only memory, so check if there's a
10444 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10446 bool CanFoldLoad = false;
10448 // Trivial case, when V2 comes from a load.
10449 if (MayFoldVectorLoad(V2))
10450 CanFoldLoad = true;
10452 // When V1 is a load, it can be folded later into a store in isel, example:
10453 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10455 // (MOVLPSmr addr:$src1, VR128:$src2)
10456 // So, recognize this potential and also use MOVLPS or MOVLPD
10457 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10458 CanFoldLoad = true;
10460 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10462 if (HasSSE2 && NumElems == 2)
10463 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10466 // If we don't care about the second element, proceed to use movss.
10467 if (SVOp->getMaskElt(1) != -1)
10468 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10471 // movl and movlp will both match v2i64, but v2i64 is never matched by
10472 // movl earlier because we make it strict to avoid messing with the movlp load
10473 // folding logic (see the code above getMOVLP call). Match it here then,
10474 // this is horrible, but will stay like this until we move all shuffle
10475 // matching to x86 specific nodes. Note that for the 1st condition all
10476 // types are matched with movsd.
10478 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10479 // as to remove this logic from here, as much as possible
10480 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10481 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10482 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10485 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10487 // Invert the operand order and use SHUFPS to match it.
10488 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10489 getShuffleSHUFImmediate(SVOp), DAG);
10492 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10493 SelectionDAG &DAG) {
10495 MVT VT = Load->getSimpleValueType(0);
10496 MVT EVT = VT.getVectorElementType();
10497 SDValue Addr = Load->getOperand(1);
10498 SDValue NewAddr = DAG.getNode(
10499 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10500 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10503 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10504 DAG.getMachineFunction().getMachineMemOperand(
10505 Load->getMemOperand(), 0, EVT.getStoreSize()));
10509 // It is only safe to call this function if isINSERTPSMask is true for
10510 // this shufflevector mask.
10511 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10512 SelectionDAG &DAG) {
10513 // Generate an insertps instruction when inserting an f32 from memory onto a
10514 // v4f32 or when copying a member from one v4f32 to another.
10515 // We also use it for transferring i32 from one register to another,
10516 // since it simply copies the same bits.
10517 // If we're transferring an i32 from memory to a specific element in a
10518 // register, we output a generic DAG that will match the PINSRD
10520 MVT VT = SVOp->getSimpleValueType(0);
10521 MVT EVT = VT.getVectorElementType();
10522 SDValue V1 = SVOp->getOperand(0);
10523 SDValue V2 = SVOp->getOperand(1);
10524 auto Mask = SVOp->getMask();
10525 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10526 "unsupported vector type for insertps/pinsrd");
10528 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10529 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10530 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10534 unsigned DestIndex;
10538 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10541 // If we have 1 element from each vector, we have to check if we're
10542 // changing V1's element's place. If so, we're done. Otherwise, we
10543 // should assume we're changing V2's element's place and behave
10545 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10546 assert(DestIndex <= INT32_MAX && "truncated destination index");
10547 if (FromV1 == FromV2 &&
10548 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10552 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10555 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10556 "More than one element from V1 and from V2, or no elements from one "
10557 "of the vectors. This case should not have returned true from "
10562 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10565 // Get an index into the source vector in the range [0,4) (the mask is
10566 // in the range [0,8) because it can address V1 and V2)
10567 unsigned SrcIndex = Mask[DestIndex] % 4;
10568 if (MayFoldLoad(From)) {
10569 // Trivial case, when From comes from a load and is only used by the
10570 // shuffle. Make it use insertps from the vector that we need from that
10573 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10574 if (!NewLoad.getNode())
10577 if (EVT == MVT::f32) {
10578 // Create this as a scalar to vector to match the instruction pattern.
10579 SDValue LoadScalarToVector =
10580 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10581 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10582 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10584 } else { // EVT == MVT::i32
10585 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10586 // instruction, to match the PINSRD instruction, which loads an i32 to a
10587 // certain vector element.
10588 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10589 DAG.getConstant(DestIndex, MVT::i32));
10593 // Vector-element-to-vector
10594 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10595 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10598 // Reduce a vector shuffle to zext.
10599 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10600 SelectionDAG &DAG) {
10601 // PMOVZX is only available from SSE41.
10602 if (!Subtarget->hasSSE41())
10605 MVT VT = Op.getSimpleValueType();
10607 // Only AVX2 support 256-bit vector integer extending.
10608 if (!Subtarget->hasInt256() && VT.is256BitVector())
10611 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10613 SDValue V1 = Op.getOperand(0);
10614 SDValue V2 = Op.getOperand(1);
10615 unsigned NumElems = VT.getVectorNumElements();
10617 // Extending is an unary operation and the element type of the source vector
10618 // won't be equal to or larger than i64.
10619 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10620 VT.getVectorElementType() == MVT::i64)
10623 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10624 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10625 while ((1U << Shift) < NumElems) {
10626 if (SVOp->getMaskElt(1U << Shift) == 1)
10629 // The maximal ratio is 8, i.e. from i8 to i64.
10634 // Check the shuffle mask.
10635 unsigned Mask = (1U << Shift) - 1;
10636 for (unsigned i = 0; i != NumElems; ++i) {
10637 int EltIdx = SVOp->getMaskElt(i);
10638 if ((i & Mask) != 0 && EltIdx != -1)
10640 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10644 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10645 MVT NeVT = MVT::getIntegerVT(NBits);
10646 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10648 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10651 // Simplify the operand as it's prepared to be fed into shuffle.
10652 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10653 if (V1.getOpcode() == ISD::BITCAST &&
10654 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10655 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10656 V1.getOperand(0).getOperand(0)
10657 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10658 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10659 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10660 ConstantSDNode *CIdx =
10661 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10662 // If it's foldable, i.e. normal load with single use, we will let code
10663 // selection to fold it. Otherwise, we will short the conversion sequence.
10664 if (CIdx && CIdx->getZExtValue() == 0 &&
10665 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10666 MVT FullVT = V.getSimpleValueType();
10667 MVT V1VT = V1.getSimpleValueType();
10668 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10669 // The "ext_vec_elt" node is wider than the result node.
10670 // In this case we should extract subvector from V.
10671 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10672 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10673 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10674 FullVT.getVectorNumElements()/Ratio);
10675 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10676 DAG.getIntPtrConstant(0));
10678 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10682 return DAG.getNode(ISD::BITCAST, DL, VT,
10683 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10686 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10687 SelectionDAG &DAG) {
10688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10689 MVT VT = Op.getSimpleValueType();
10691 SDValue V1 = Op.getOperand(0);
10692 SDValue V2 = Op.getOperand(1);
10694 if (isZeroShuffle(SVOp))
10695 return getZeroVector(VT, Subtarget, DAG, dl);
10697 // Handle splat operations
10698 if (SVOp->isSplat()) {
10699 // Use vbroadcast whenever the splat comes from a foldable load
10700 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10701 if (Broadcast.getNode())
10705 // Check integer expanding shuffles.
10706 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10707 if (NewOp.getNode())
10710 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10712 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10713 VT == MVT::v32i8) {
10714 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10715 if (NewOp.getNode())
10716 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10717 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10718 // FIXME: Figure out a cleaner way to do this.
10719 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10720 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10721 if (NewOp.getNode()) {
10722 MVT NewVT = NewOp.getSimpleValueType();
10723 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10724 NewVT, true, false))
10725 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10728 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10729 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10730 if (NewOp.getNode()) {
10731 MVT NewVT = NewOp.getSimpleValueType();
10732 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10733 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10742 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10743 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10744 SDValue V1 = Op.getOperand(0);
10745 SDValue V2 = Op.getOperand(1);
10746 MVT VT = Op.getSimpleValueType();
10748 unsigned NumElems = VT.getVectorNumElements();
10749 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10750 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10751 bool V1IsSplat = false;
10752 bool V2IsSplat = false;
10753 bool HasSSE2 = Subtarget->hasSSE2();
10754 bool HasFp256 = Subtarget->hasFp256();
10755 bool HasInt256 = Subtarget->hasInt256();
10756 MachineFunction &MF = DAG.getMachineFunction();
10757 bool OptForSize = MF.getFunction()->getAttributes().
10758 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10760 // Check if we should use the experimental vector shuffle lowering. If so,
10761 // delegate completely to that code path.
10762 if (ExperimentalVectorShuffleLowering)
10763 return lowerVectorShuffle(Op, Subtarget, DAG);
10765 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10767 if (V1IsUndef && V2IsUndef)
10768 return DAG.getUNDEF(VT);
10770 // When we create a shuffle node we put the UNDEF node to second operand,
10771 // but in some cases the first operand may be transformed to UNDEF.
10772 // In this case we should just commute the node.
10774 return DAG.getCommutedVectorShuffle(*SVOp);
10776 // Vector shuffle lowering takes 3 steps:
10778 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10779 // narrowing and commutation of operands should be handled.
10780 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10782 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10783 // so the shuffle can be broken into other shuffles and the legalizer can
10784 // try the lowering again.
10786 // The general idea is that no vector_shuffle operation should be left to
10787 // be matched during isel, all of them must be converted to a target specific
10790 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10791 // narrowing and commutation of operands should be handled. The actual code
10792 // doesn't include all of those, work in progress...
10793 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10794 if (NewOp.getNode())
10797 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10799 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10800 // unpckh_undef). Only use pshufd if speed is more important than size.
10801 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10802 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10803 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10804 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10806 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10807 V2IsUndef && MayFoldVectorLoad(V1))
10808 return getMOVDDup(Op, dl, V1, DAG);
10810 if (isMOVHLPS_v_undef_Mask(M, VT))
10811 return getMOVHighToLow(Op, dl, DAG);
10813 // Use to match splats
10814 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
10815 (VT == MVT::v2f64 || VT == MVT::v2i64))
10816 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10818 if (isPSHUFDMask(M, VT)) {
10819 // The actual implementation will match the mask in the if above and then
10820 // during isel it can match several different instructions, not only pshufd
10821 // as its name says, sad but true, emulate the behavior for now...
10822 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
10823 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
10825 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
10827 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
10828 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
10830 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
10831 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
10834 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
10838 if (isPALIGNRMask(M, VT, Subtarget))
10839 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
10840 getShufflePALIGNRImmediate(SVOp),
10843 if (isVALIGNMask(M, VT, Subtarget))
10844 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
10845 getShuffleVALIGNImmediate(SVOp),
10848 // Check if this can be converted into a logical shift.
10849 bool isLeft = false;
10850 unsigned ShAmt = 0;
10852 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
10853 if (isShift && ShVal.hasOneUse()) {
10854 // If the shifted value has multiple uses, it may be cheaper to use
10855 // v_set0 + movlhps or movhlps, etc.
10856 MVT EltVT = VT.getVectorElementType();
10857 ShAmt *= EltVT.getSizeInBits();
10858 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10861 if (isMOVLMask(M, VT)) {
10862 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10863 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
10864 if (!isMOVLPMask(M, VT)) {
10865 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
10866 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10868 if (VT == MVT::v4i32 || VT == MVT::v4f32)
10869 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10873 // FIXME: fold these into legal mask.
10874 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
10875 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
10877 if (isMOVHLPSMask(M, VT))
10878 return getMOVHighToLow(Op, dl, DAG);
10880 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
10881 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
10883 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
10884 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
10886 if (isMOVLPMask(M, VT))
10887 return getMOVLP(Op, dl, DAG, HasSSE2);
10889 if (ShouldXformToMOVHLPS(M, VT) ||
10890 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
10891 return DAG.getCommutedVectorShuffle(*SVOp);
10894 // No better options. Use a vshldq / vsrldq.
10895 MVT EltVT = VT.getVectorElementType();
10896 ShAmt *= EltVT.getSizeInBits();
10897 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10900 bool Commuted = false;
10901 // FIXME: This should also accept a bitcast of a splat? Be careful, not
10902 // 1,1,1,1 -> v8i16 though.
10903 BitVector UndefElements;
10904 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
10905 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10907 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
10908 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10911 // Canonicalize the splat or undef, if present, to be on the RHS.
10912 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
10913 CommuteVectorShuffleMask(M, NumElems);
10915 std::swap(V1IsSplat, V2IsSplat);
10919 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
10920 // Shuffling low element of v1 into undef, just return v1.
10923 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
10924 // the instruction selector will not match, so get a canonical MOVL with
10925 // swapped operands to undo the commute.
10926 return getMOVL(DAG, dl, VT, V2, V1);
10929 if (isUNPCKLMask(M, VT, HasInt256))
10930 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10932 if (isUNPCKHMask(M, VT, HasInt256))
10933 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10936 // Normalize mask so all entries that point to V2 points to its first
10937 // element then try to match unpck{h|l} again. If match, return a
10938 // new vector_shuffle with the corrected mask.p
10939 SmallVector<int, 8> NewMask(M.begin(), M.end());
10940 NormalizeMask(NewMask, NumElems);
10941 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
10942 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10943 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
10944 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10948 // Commute is back and try unpck* again.
10949 // FIXME: this seems wrong.
10950 CommuteVectorShuffleMask(M, NumElems);
10952 std::swap(V1IsSplat, V2IsSplat);
10954 if (isUNPCKLMask(M, VT, HasInt256))
10955 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10957 if (isUNPCKHMask(M, VT, HasInt256))
10958 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10961 // Normalize the node to match x86 shuffle ops if needed
10962 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10963 return DAG.getCommutedVectorShuffle(*SVOp);
10965 // The checks below are all present in isShuffleMaskLegal, but they are
10966 // inlined here right now to enable us to directly emit target specific
10967 // nodes, and remove one by one until they don't return Op anymore.
10969 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10970 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10971 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10972 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10975 if (isPSHUFHWMask(M, VT, HasInt256))
10976 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10977 getShufflePSHUFHWImmediate(SVOp),
10980 if (isPSHUFLWMask(M, VT, HasInt256))
10981 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10982 getShufflePSHUFLWImmediate(SVOp),
10985 unsigned MaskValue;
10986 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10988 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10990 if (isSHUFPMask(M, VT))
10991 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10992 getShuffleSHUFImmediate(SVOp), DAG);
10994 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10995 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10996 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10997 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10999 //===--------------------------------------------------------------------===//
11000 // Generate target specific nodes for 128 or 256-bit shuffles only
11001 // supported in the AVX instruction set.
11004 // Handle VMOVDDUPY permutations
11005 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11006 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11008 // Handle VPERMILPS/D* permutations
11009 if (isVPERMILPMask(M, VT)) {
11010 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11011 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11012 getShuffleSHUFImmediate(SVOp), DAG);
11013 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
11014 getShuffleSHUFImmediate(SVOp), DAG);
11018 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11019 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11020 Idx*(NumElems/2), DAG, dl);
11022 // Handle VPERM2F128/VPERM2I128 permutations
11023 if (isVPERM2X128Mask(M, VT, HasFp256))
11024 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11025 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11027 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11028 return getINSERTPS(SVOp, dl, DAG);
11031 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11032 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11034 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11035 VT.is512BitVector()) {
11036 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11037 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11038 SmallVector<SDValue, 16> permclMask;
11039 for (unsigned i = 0; i != NumElems; ++i) {
11040 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11043 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11045 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11046 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11047 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11048 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11049 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11052 //===--------------------------------------------------------------------===//
11053 // Since no target specific shuffle was selected for this generic one,
11054 // lower it into other known shuffles. FIXME: this isn't true yet, but
11055 // this is the plan.
11058 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11059 if (VT == MVT::v8i16) {
11060 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11061 if (NewOp.getNode())
11065 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11066 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11067 if (NewOp.getNode())
11071 if (VT == MVT::v16i8) {
11072 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11073 if (NewOp.getNode())
11077 if (VT == MVT::v32i8) {
11078 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11079 if (NewOp.getNode())
11083 // Handle all 128-bit wide vectors with 4 elements, and match them with
11084 // several different shuffle types.
11085 if (NumElems == 4 && VT.is128BitVector())
11086 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11088 // Handle general 256-bit shuffles
11089 if (VT.is256BitVector())
11090 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11095 // This function assumes its argument is a BUILD_VECTOR of constants or
11096 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11098 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11099 unsigned &MaskValue) {
11101 unsigned NumElems = BuildVector->getNumOperands();
11102 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11103 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11104 unsigned NumElemsInLane = NumElems / NumLanes;
11106 // Blend for v16i16 should be symetric for the both lanes.
11107 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11108 SDValue EltCond = BuildVector->getOperand(i);
11109 SDValue SndLaneEltCond =
11110 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11112 int Lane1Cond = -1, Lane2Cond = -1;
11113 if (isa<ConstantSDNode>(EltCond))
11114 Lane1Cond = !isZero(EltCond);
11115 if (isa<ConstantSDNode>(SndLaneEltCond))
11116 Lane2Cond = !isZero(SndLaneEltCond);
11118 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11119 // Lane1Cond != 0, means we want the first argument.
11120 // Lane1Cond == 0, means we want the second argument.
11121 // The encoding of this argument is 0 for the first argument, 1
11122 // for the second. Therefore, invert the condition.
11123 MaskValue |= !Lane1Cond << i;
11124 else if (Lane1Cond < 0)
11125 MaskValue |= !Lane2Cond << i;
11132 // Try to lower a vselect node into a simple blend instruction.
11133 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11134 SelectionDAG &DAG) {
11135 SDValue Cond = Op.getOperand(0);
11136 SDValue LHS = Op.getOperand(1);
11137 SDValue RHS = Op.getOperand(2);
11139 MVT VT = Op.getSimpleValueType();
11140 MVT EltVT = VT.getVectorElementType();
11141 unsigned NumElems = VT.getVectorNumElements();
11143 // There is no blend with immediate in AVX-512.
11144 if (VT.is512BitVector())
11147 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11149 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11152 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11155 // Check the mask for BLEND and build the value.
11156 unsigned MaskValue = 0;
11157 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11160 // Convert i32 vectors to floating point if it is not AVX2.
11161 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11163 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11164 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11166 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11167 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11170 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11171 DAG.getConstant(MaskValue, MVT::i32));
11172 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11175 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11176 // A vselect where all conditions and data are constants can be optimized into
11177 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11178 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11179 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11180 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11183 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11184 if (BlendOp.getNode())
11187 // Some types for vselect were previously set to Expand, not Legal or
11188 // Custom. Return an empty SDValue so we fall-through to Expand, after
11189 // the Custom lowering phase.
11190 MVT VT = Op.getSimpleValueType();
11191 switch (VT.SimpleTy) {
11196 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11201 // We couldn't create a "Blend with immediate" node.
11202 // This node should still be legal, but we'll have to emit a blendv*
11207 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11208 MVT VT = Op.getSimpleValueType();
11211 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11214 if (VT.getSizeInBits() == 8) {
11215 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11216 Op.getOperand(0), Op.getOperand(1));
11217 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11218 DAG.getValueType(VT));
11219 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11222 if (VT.getSizeInBits() == 16) {
11223 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11224 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11226 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11227 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11228 DAG.getNode(ISD::BITCAST, dl,
11231 Op.getOperand(1)));
11232 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11233 Op.getOperand(0), Op.getOperand(1));
11234 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11235 DAG.getValueType(VT));
11236 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11239 if (VT == MVT::f32) {
11240 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11241 // the result back to FR32 register. It's only worth matching if the
11242 // result has a single use which is a store or a bitcast to i32. And in
11243 // the case of a store, it's not worth it if the index is a constant 0,
11244 // because a MOVSSmr can be used instead, which is smaller and faster.
11245 if (!Op.hasOneUse())
11247 SDNode *User = *Op.getNode()->use_begin();
11248 if ((User->getOpcode() != ISD::STORE ||
11249 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11250 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11251 (User->getOpcode() != ISD::BITCAST ||
11252 User->getValueType(0) != MVT::i32))
11254 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11255 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11258 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11261 if (VT == MVT::i32 || VT == MVT::i64) {
11262 // ExtractPS/pextrq works with constant index.
11263 if (isa<ConstantSDNode>(Op.getOperand(1)))
11269 /// Extract one bit from mask vector, like v16i1 or v8i1.
11270 /// AVX-512 feature.
11272 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11273 SDValue Vec = Op.getOperand(0);
11275 MVT VecVT = Vec.getSimpleValueType();
11276 SDValue Idx = Op.getOperand(1);
11277 MVT EltVT = Op.getSimpleValueType();
11279 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11281 // variable index can't be handled in mask registers,
11282 // extend vector to VR512
11283 if (!isa<ConstantSDNode>(Idx)) {
11284 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11285 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11286 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11287 ExtVT.getVectorElementType(), Ext, Idx);
11288 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11291 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11292 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11293 unsigned MaxSift = rc->getSize()*8 - 1;
11294 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11295 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11296 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11297 DAG.getConstant(MaxSift, MVT::i8));
11298 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11299 DAG.getIntPtrConstant(0));
11303 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11304 SelectionDAG &DAG) const {
11306 SDValue Vec = Op.getOperand(0);
11307 MVT VecVT = Vec.getSimpleValueType();
11308 SDValue Idx = Op.getOperand(1);
11310 if (Op.getSimpleValueType() == MVT::i1)
11311 return ExtractBitFromMaskVector(Op, DAG);
11313 if (!isa<ConstantSDNode>(Idx)) {
11314 if (VecVT.is512BitVector() ||
11315 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11316 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11319 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11320 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11321 MaskEltVT.getSizeInBits());
11323 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11324 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11325 getZeroVector(MaskVT, Subtarget, DAG, dl),
11326 Idx, DAG.getConstant(0, getPointerTy()));
11327 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11328 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11329 Perm, DAG.getConstant(0, getPointerTy()));
11334 // If this is a 256-bit vector result, first extract the 128-bit vector and
11335 // then extract the element from the 128-bit vector.
11336 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11338 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11339 // Get the 128-bit vector.
11340 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11341 MVT EltVT = VecVT.getVectorElementType();
11343 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11345 //if (IdxVal >= NumElems/2)
11346 // IdxVal -= NumElems/2;
11347 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11348 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11349 DAG.getConstant(IdxVal, MVT::i32));
11352 assert(VecVT.is128BitVector() && "Unexpected vector length");
11354 if (Subtarget->hasSSE41()) {
11355 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11360 MVT VT = Op.getSimpleValueType();
11361 // TODO: handle v16i8.
11362 if (VT.getSizeInBits() == 16) {
11363 SDValue Vec = Op.getOperand(0);
11364 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11366 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11367 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11368 DAG.getNode(ISD::BITCAST, dl,
11370 Op.getOperand(1)));
11371 // Transform it so it match pextrw which produces a 32-bit result.
11372 MVT EltVT = MVT::i32;
11373 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11374 Op.getOperand(0), Op.getOperand(1));
11375 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11376 DAG.getValueType(VT));
11377 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11380 if (VT.getSizeInBits() == 32) {
11381 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11385 // SHUFPS the element to the lowest double word, then movss.
11386 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11387 MVT VVT = Op.getOperand(0).getSimpleValueType();
11388 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11389 DAG.getUNDEF(VVT), Mask);
11390 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11391 DAG.getIntPtrConstant(0));
11394 if (VT.getSizeInBits() == 64) {
11395 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11396 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11397 // to match extract_elt for f64.
11398 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11402 // UNPCKHPD the element to the lowest double word, then movsd.
11403 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11404 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11405 int Mask[2] = { 1, -1 };
11406 MVT VVT = Op.getOperand(0).getSimpleValueType();
11407 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11408 DAG.getUNDEF(VVT), Mask);
11409 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11410 DAG.getIntPtrConstant(0));
11416 /// Insert one bit to mask vector, like v16i1 or v8i1.
11417 /// AVX-512 feature.
11419 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11421 SDValue Vec = Op.getOperand(0);
11422 SDValue Elt = Op.getOperand(1);
11423 SDValue Idx = Op.getOperand(2);
11424 MVT VecVT = Vec.getSimpleValueType();
11426 if (!isa<ConstantSDNode>(Idx)) {
11427 // Non constant index. Extend source and destination,
11428 // insert element and then truncate the result.
11429 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11430 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11431 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11432 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11433 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11434 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11437 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11438 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11439 if (Vec.getOpcode() == ISD::UNDEF)
11440 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11441 DAG.getConstant(IdxVal, MVT::i8));
11442 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11443 unsigned MaxSift = rc->getSize()*8 - 1;
11444 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11445 DAG.getConstant(MaxSift, MVT::i8));
11446 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11447 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11448 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11451 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11452 SelectionDAG &DAG) const {
11453 MVT VT = Op.getSimpleValueType();
11454 MVT EltVT = VT.getVectorElementType();
11456 if (EltVT == MVT::i1)
11457 return InsertBitToMaskVector(Op, DAG);
11460 SDValue N0 = Op.getOperand(0);
11461 SDValue N1 = Op.getOperand(1);
11462 SDValue N2 = Op.getOperand(2);
11463 if (!isa<ConstantSDNode>(N2))
11465 auto *N2C = cast<ConstantSDNode>(N2);
11466 unsigned IdxVal = N2C->getZExtValue();
11468 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11469 // into that, and then insert the subvector back into the result.
11470 if (VT.is256BitVector() || VT.is512BitVector()) {
11471 // Get the desired 128-bit vector half.
11472 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11474 // Insert the element into the desired half.
11475 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11476 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11478 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11479 DAG.getConstant(IdxIn128, MVT::i32));
11481 // Insert the changed part back to the 256-bit vector
11482 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11484 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11486 if (Subtarget->hasSSE41()) {
11487 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11489 if (VT == MVT::v8i16) {
11490 Opc = X86ISD::PINSRW;
11492 assert(VT == MVT::v16i8);
11493 Opc = X86ISD::PINSRB;
11496 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11498 if (N1.getValueType() != MVT::i32)
11499 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11500 if (N2.getValueType() != MVT::i32)
11501 N2 = DAG.getIntPtrConstant(IdxVal);
11502 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11505 if (EltVT == MVT::f32) {
11506 // Bits [7:6] of the constant are the source select. This will always be
11507 // zero here. The DAG Combiner may combine an extract_elt index into
11509 // bits. For example (insert (extract, 3), 2) could be matched by
11511 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11512 // Bits [5:4] of the constant are the destination select. This is the
11513 // value of the incoming immediate.
11514 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11515 // combine either bitwise AND or insert of float 0.0 to set these bits.
11516 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11517 // Create this as a scalar to vector..
11518 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11519 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11522 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11523 // PINSR* works with constant index.
11528 if (EltVT == MVT::i8)
11531 if (EltVT.getSizeInBits() == 16) {
11532 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11533 // as its second argument.
11534 if (N1.getValueType() != MVT::i32)
11535 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11536 if (N2.getValueType() != MVT::i32)
11537 N2 = DAG.getIntPtrConstant(IdxVal);
11538 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11543 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11545 MVT OpVT = Op.getSimpleValueType();
11547 // If this is a 256-bit vector result, first insert into a 128-bit
11548 // vector and then insert into the 256-bit vector.
11549 if (!OpVT.is128BitVector()) {
11550 // Insert into a 128-bit vector.
11551 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11552 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11553 OpVT.getVectorNumElements() / SizeFactor);
11555 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11557 // Insert the 128-bit vector.
11558 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11561 if (OpVT == MVT::v1i64 &&
11562 Op.getOperand(0).getValueType() == MVT::i64)
11563 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11565 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11566 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11567 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11568 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11571 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11572 // a simple subregister reference or explicit instructions to grab
11573 // upper bits of a vector.
11574 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11575 SelectionDAG &DAG) {
11577 SDValue In = Op.getOperand(0);
11578 SDValue Idx = Op.getOperand(1);
11579 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11580 MVT ResVT = Op.getSimpleValueType();
11581 MVT InVT = In.getSimpleValueType();
11583 if (Subtarget->hasFp256()) {
11584 if (ResVT.is128BitVector() &&
11585 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11586 isa<ConstantSDNode>(Idx)) {
11587 return Extract128BitVector(In, IdxVal, DAG, dl);
11589 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11590 isa<ConstantSDNode>(Idx)) {
11591 return Extract256BitVector(In, IdxVal, DAG, dl);
11597 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11598 // simple superregister reference or explicit instructions to insert
11599 // the upper bits of a vector.
11600 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11601 SelectionDAG &DAG) {
11602 if (Subtarget->hasFp256()) {
11603 SDLoc dl(Op.getNode());
11604 SDValue Vec = Op.getNode()->getOperand(0);
11605 SDValue SubVec = Op.getNode()->getOperand(1);
11606 SDValue Idx = Op.getNode()->getOperand(2);
11608 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11609 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11610 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11611 isa<ConstantSDNode>(Idx)) {
11612 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11613 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11616 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11617 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11618 isa<ConstantSDNode>(Idx)) {
11619 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11620 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11626 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11627 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11628 // one of the above mentioned nodes. It has to be wrapped because otherwise
11629 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11630 // be used to form addressing mode. These wrapped nodes will be selected
11633 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11634 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11636 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11637 // global base reg.
11638 unsigned char OpFlag = 0;
11639 unsigned WrapperKind = X86ISD::Wrapper;
11640 CodeModel::Model M = DAG.getTarget().getCodeModel();
11642 if (Subtarget->isPICStyleRIPRel() &&
11643 (M == CodeModel::Small || M == CodeModel::Kernel))
11644 WrapperKind = X86ISD::WrapperRIP;
11645 else if (Subtarget->isPICStyleGOT())
11646 OpFlag = X86II::MO_GOTOFF;
11647 else if (Subtarget->isPICStyleStubPIC())
11648 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11650 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11651 CP->getAlignment(),
11652 CP->getOffset(), OpFlag);
11654 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11655 // With PIC, the address is actually $g + Offset.
11657 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11658 DAG.getNode(X86ISD::GlobalBaseReg,
11659 SDLoc(), getPointerTy()),
11666 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11667 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11669 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11670 // global base reg.
11671 unsigned char OpFlag = 0;
11672 unsigned WrapperKind = X86ISD::Wrapper;
11673 CodeModel::Model M = DAG.getTarget().getCodeModel();
11675 if (Subtarget->isPICStyleRIPRel() &&
11676 (M == CodeModel::Small || M == CodeModel::Kernel))
11677 WrapperKind = X86ISD::WrapperRIP;
11678 else if (Subtarget->isPICStyleGOT())
11679 OpFlag = X86II::MO_GOTOFF;
11680 else if (Subtarget->isPICStyleStubPIC())
11681 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11683 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11686 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11688 // With PIC, the address is actually $g + Offset.
11690 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11691 DAG.getNode(X86ISD::GlobalBaseReg,
11692 SDLoc(), getPointerTy()),
11699 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11700 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11702 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11703 // global base reg.
11704 unsigned char OpFlag = 0;
11705 unsigned WrapperKind = X86ISD::Wrapper;
11706 CodeModel::Model M = DAG.getTarget().getCodeModel();
11708 if (Subtarget->isPICStyleRIPRel() &&
11709 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11710 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11711 OpFlag = X86II::MO_GOTPCREL;
11712 WrapperKind = X86ISD::WrapperRIP;
11713 } else if (Subtarget->isPICStyleGOT()) {
11714 OpFlag = X86II::MO_GOT;
11715 } else if (Subtarget->isPICStyleStubPIC()) {
11716 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11717 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11718 OpFlag = X86II::MO_DARWIN_NONLAZY;
11721 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11724 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11726 // With PIC, the address is actually $g + Offset.
11727 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11728 !Subtarget->is64Bit()) {
11729 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11730 DAG.getNode(X86ISD::GlobalBaseReg,
11731 SDLoc(), getPointerTy()),
11735 // For symbols that require a load from a stub to get the address, emit the
11737 if (isGlobalStubReference(OpFlag))
11738 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11739 MachinePointerInfo::getGOT(), false, false, false, 0);
11745 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11746 // Create the TargetBlockAddressAddress node.
11747 unsigned char OpFlags =
11748 Subtarget->ClassifyBlockAddressReference();
11749 CodeModel::Model M = DAG.getTarget().getCodeModel();
11750 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11751 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11753 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11756 if (Subtarget->isPICStyleRIPRel() &&
11757 (M == CodeModel::Small || M == CodeModel::Kernel))
11758 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11760 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11762 // With PIC, the address is actually $g + Offset.
11763 if (isGlobalRelativeToPICBase(OpFlags)) {
11764 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11765 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11773 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11774 int64_t Offset, SelectionDAG &DAG) const {
11775 // Create the TargetGlobalAddress node, folding in the constant
11776 // offset if it is legal.
11777 unsigned char OpFlags =
11778 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11779 CodeModel::Model M = DAG.getTarget().getCodeModel();
11781 if (OpFlags == X86II::MO_NO_FLAG &&
11782 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11783 // A direct static reference to a global.
11784 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11787 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11790 if (Subtarget->isPICStyleRIPRel() &&
11791 (M == CodeModel::Small || M == CodeModel::Kernel))
11792 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11794 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11796 // With PIC, the address is actually $g + Offset.
11797 if (isGlobalRelativeToPICBase(OpFlags)) {
11798 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11799 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11803 // For globals that require a load from a stub to get the address, emit the
11805 if (isGlobalStubReference(OpFlags))
11806 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11807 MachinePointerInfo::getGOT(), false, false, false, 0);
11809 // If there was a non-zero offset that we didn't fold, create an explicit
11810 // addition for it.
11812 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11813 DAG.getConstant(Offset, getPointerTy()));
11819 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11820 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11821 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11822 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11826 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11827 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11828 unsigned char OperandFlags, bool LocalDynamic = false) {
11829 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11830 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11832 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11833 GA->getValueType(0),
11837 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11841 SDValue Ops[] = { Chain, TGA, *InFlag };
11842 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11844 SDValue Ops[] = { Chain, TGA };
11845 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11848 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11849 MFI->setAdjustsStack(true);
11851 SDValue Flag = Chain.getValue(1);
11852 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11855 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11857 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11860 SDLoc dl(GA); // ? function entry point might be better
11861 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11862 DAG.getNode(X86ISD::GlobalBaseReg,
11863 SDLoc(), PtrVT), InFlag);
11864 InFlag = Chain.getValue(1);
11866 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11869 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11871 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11873 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11874 X86::RAX, X86II::MO_TLSGD);
11877 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11883 // Get the start address of the TLS block for this module.
11884 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11885 .getInfo<X86MachineFunctionInfo>();
11886 MFI->incNumLocalDynamicTLSAccesses();
11890 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11891 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11894 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11895 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11896 InFlag = Chain.getValue(1);
11897 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11898 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11901 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11905 unsigned char OperandFlags = X86II::MO_DTPOFF;
11906 unsigned WrapperKind = X86ISD::Wrapper;
11907 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11908 GA->getValueType(0),
11909 GA->getOffset(), OperandFlags);
11910 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11912 // Add x@dtpoff with the base.
11913 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11916 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11917 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11918 const EVT PtrVT, TLSModel::Model model,
11919 bool is64Bit, bool isPIC) {
11922 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11923 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11924 is64Bit ? 257 : 256));
11926 SDValue ThreadPointer =
11927 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11928 MachinePointerInfo(Ptr), false, false, false, 0);
11930 unsigned char OperandFlags = 0;
11931 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11933 unsigned WrapperKind = X86ISD::Wrapper;
11934 if (model == TLSModel::LocalExec) {
11935 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11936 } else if (model == TLSModel::InitialExec) {
11938 OperandFlags = X86II::MO_GOTTPOFF;
11939 WrapperKind = X86ISD::WrapperRIP;
11941 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11944 llvm_unreachable("Unexpected model");
11947 // emit "addl x@ntpoff,%eax" (local exec)
11948 // or "addl x@indntpoff,%eax" (initial exec)
11949 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11951 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11952 GA->getOffset(), OperandFlags);
11953 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11955 if (model == TLSModel::InitialExec) {
11956 if (isPIC && !is64Bit) {
11957 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11958 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11962 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11963 MachinePointerInfo::getGOT(), false, false, false, 0);
11966 // The address of the thread local variable is the add of the thread
11967 // pointer with the offset of the variable.
11968 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11972 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11974 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11975 const GlobalValue *GV = GA->getGlobal();
11977 if (Subtarget->isTargetELF()) {
11978 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11981 case TLSModel::GeneralDynamic:
11982 if (Subtarget->is64Bit())
11983 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11984 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11985 case TLSModel::LocalDynamic:
11986 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11987 Subtarget->is64Bit());
11988 case TLSModel::InitialExec:
11989 case TLSModel::LocalExec:
11990 return LowerToTLSExecModel(
11991 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11992 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11994 llvm_unreachable("Unknown TLS model.");
11997 if (Subtarget->isTargetDarwin()) {
11998 // Darwin only has one model of TLS. Lower to that.
11999 unsigned char OpFlag = 0;
12000 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12001 X86ISD::WrapperRIP : X86ISD::Wrapper;
12003 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12004 // global base reg.
12005 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12006 !Subtarget->is64Bit();
12008 OpFlag = X86II::MO_TLVP_PIC_BASE;
12010 OpFlag = X86II::MO_TLVP;
12012 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12013 GA->getValueType(0),
12014 GA->getOffset(), OpFlag);
12015 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12017 // With PIC32, the address is actually $g + Offset.
12019 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12020 DAG.getNode(X86ISD::GlobalBaseReg,
12021 SDLoc(), getPointerTy()),
12024 // Lowering the machine isd will make sure everything is in the right
12026 SDValue Chain = DAG.getEntryNode();
12027 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12028 SDValue Args[] = { Chain, Offset };
12029 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12031 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12032 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12033 MFI->setAdjustsStack(true);
12035 // And our return value (tls address) is in the standard call return value
12037 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12038 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12039 Chain.getValue(1));
12042 if (Subtarget->isTargetKnownWindowsMSVC() ||
12043 Subtarget->isTargetWindowsGNU()) {
12044 // Just use the implicit TLS architecture
12045 // Need to generate someting similar to:
12046 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12048 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12049 // mov rcx, qword [rdx+rcx*8]
12050 // mov eax, .tls$:tlsvar
12051 // [rax+rcx] contains the address
12052 // Windows 64bit: gs:0x58
12053 // Windows 32bit: fs:__tls_array
12056 SDValue Chain = DAG.getEntryNode();
12058 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12059 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12060 // use its literal value of 0x2C.
12061 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12062 ? Type::getInt8PtrTy(*DAG.getContext(),
12064 : Type::getInt32PtrTy(*DAG.getContext(),
12068 Subtarget->is64Bit()
12069 ? DAG.getIntPtrConstant(0x58)
12070 : (Subtarget->isTargetWindowsGNU()
12071 ? DAG.getIntPtrConstant(0x2C)
12072 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12074 SDValue ThreadPointer =
12075 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12076 MachinePointerInfo(Ptr), false, false, false, 0);
12078 // Load the _tls_index variable
12079 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12080 if (Subtarget->is64Bit())
12081 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12082 IDX, MachinePointerInfo(), MVT::i32,
12083 false, false, false, 0);
12085 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12086 false, false, false, 0);
12088 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12090 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12092 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12093 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12094 false, false, false, 0);
12096 // Get the offset of start of .tls section
12097 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12098 GA->getValueType(0),
12099 GA->getOffset(), X86II::MO_SECREL);
12100 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12102 // The address of the thread local variable is the add of the thread
12103 // pointer with the offset of the variable.
12104 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12107 llvm_unreachable("TLS not implemented for this target.");
12110 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12111 /// and take a 2 x i32 value to shift plus a shift amount.
12112 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12113 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12114 MVT VT = Op.getSimpleValueType();
12115 unsigned VTBits = VT.getSizeInBits();
12117 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12118 SDValue ShOpLo = Op.getOperand(0);
12119 SDValue ShOpHi = Op.getOperand(1);
12120 SDValue ShAmt = Op.getOperand(2);
12121 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12122 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12124 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12125 DAG.getConstant(VTBits - 1, MVT::i8));
12126 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12127 DAG.getConstant(VTBits - 1, MVT::i8))
12128 : DAG.getConstant(0, VT);
12130 SDValue Tmp2, Tmp3;
12131 if (Op.getOpcode() == ISD::SHL_PARTS) {
12132 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12133 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12135 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12136 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12139 // If the shift amount is larger or equal than the width of a part we can't
12140 // rely on the results of shld/shrd. Insert a test and select the appropriate
12141 // values for large shift amounts.
12142 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12143 DAG.getConstant(VTBits, MVT::i8));
12144 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12145 AndNode, DAG.getConstant(0, MVT::i8));
12148 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12149 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12150 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12152 if (Op.getOpcode() == ISD::SHL_PARTS) {
12153 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12154 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12156 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12157 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12160 SDValue Ops[2] = { Lo, Hi };
12161 return DAG.getMergeValues(Ops, dl);
12164 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12165 SelectionDAG &DAG) const {
12166 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12168 if (SrcVT.isVector())
12171 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12172 "Unknown SINT_TO_FP to lower!");
12174 // These are really Legal; return the operand so the caller accepts it as
12176 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12178 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12179 Subtarget->is64Bit()) {
12184 unsigned Size = SrcVT.getSizeInBits()/8;
12185 MachineFunction &MF = DAG.getMachineFunction();
12186 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12187 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12188 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12190 MachinePointerInfo::getFixedStack(SSFI),
12192 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12195 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12197 SelectionDAG &DAG) const {
12201 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12203 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12205 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12207 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12209 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12210 MachineMemOperand *MMO;
12212 int SSFI = FI->getIndex();
12214 DAG.getMachineFunction()
12215 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12216 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12218 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12219 StackSlot = StackSlot.getOperand(1);
12221 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12222 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12224 Tys, Ops, SrcVT, MMO);
12227 Chain = Result.getValue(1);
12228 SDValue InFlag = Result.getValue(2);
12230 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12231 // shouldn't be necessary except that RFP cannot be live across
12232 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12233 MachineFunction &MF = DAG.getMachineFunction();
12234 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12235 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12236 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12237 Tys = DAG.getVTList(MVT::Other);
12239 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12241 MachineMemOperand *MMO =
12242 DAG.getMachineFunction()
12243 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12244 MachineMemOperand::MOStore, SSFISize, SSFISize);
12246 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12247 Ops, Op.getValueType(), MMO);
12248 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12249 MachinePointerInfo::getFixedStack(SSFI),
12250 false, false, false, 0);
12256 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12257 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12258 SelectionDAG &DAG) const {
12259 // This algorithm is not obvious. Here it is what we're trying to output:
12262 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12263 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12265 haddpd %xmm0, %xmm0
12267 pshufd $0x4e, %xmm0, %xmm1
12273 LLVMContext *Context = DAG.getContext();
12275 // Build some magic constants.
12276 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12277 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12278 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12280 SmallVector<Constant*,2> CV1;
12282 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12283 APInt(64, 0x4330000000000000ULL))));
12285 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12286 APInt(64, 0x4530000000000000ULL))));
12287 Constant *C1 = ConstantVector::get(CV1);
12288 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12290 // Load the 64-bit value into an XMM register.
12291 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12293 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12294 MachinePointerInfo::getConstantPool(),
12295 false, false, false, 16);
12296 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12297 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12300 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12301 MachinePointerInfo::getConstantPool(),
12302 false, false, false, 16);
12303 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12304 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12307 if (Subtarget->hasSSE3()) {
12308 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12309 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12311 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12312 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12314 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12315 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12319 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12320 DAG.getIntPtrConstant(0));
12323 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12324 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12325 SelectionDAG &DAG) const {
12327 // FP constant to bias correct the final result.
12328 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12331 // Load the 32-bit value into an XMM register.
12332 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12335 // Zero out the upper parts of the register.
12336 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12338 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12339 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12340 DAG.getIntPtrConstant(0));
12342 // Or the load with the bias.
12343 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12344 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12345 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12346 MVT::v2f64, Load)),
12347 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12348 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12349 MVT::v2f64, Bias)));
12350 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12351 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12352 DAG.getIntPtrConstant(0));
12354 // Subtract the bias.
12355 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12357 // Handle final rounding.
12358 EVT DestVT = Op.getValueType();
12360 if (DestVT.bitsLT(MVT::f64))
12361 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12362 DAG.getIntPtrConstant(0));
12363 if (DestVT.bitsGT(MVT::f64))
12364 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12366 // Handle final rounding.
12370 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12371 SelectionDAG &DAG) const {
12372 SDValue N0 = Op.getOperand(0);
12373 MVT SVT = N0.getSimpleValueType();
12376 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12377 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12378 "Custom UINT_TO_FP is not supported!");
12380 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12381 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12382 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12385 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12386 SelectionDAG &DAG) const {
12387 SDValue N0 = Op.getOperand(0);
12390 if (Op.getValueType().isVector())
12391 return lowerUINT_TO_FP_vec(Op, DAG);
12393 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12394 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12395 // the optimization here.
12396 if (DAG.SignBitIsZero(N0))
12397 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12399 MVT SrcVT = N0.getSimpleValueType();
12400 MVT DstVT = Op.getSimpleValueType();
12401 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12402 return LowerUINT_TO_FP_i64(Op, DAG);
12403 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12404 return LowerUINT_TO_FP_i32(Op, DAG);
12405 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12408 // Make a 64-bit buffer, and use it to build an FILD.
12409 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12410 if (SrcVT == MVT::i32) {
12411 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12412 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12413 getPointerTy(), StackSlot, WordOff);
12414 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12415 StackSlot, MachinePointerInfo(),
12417 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12418 OffsetSlot, MachinePointerInfo(),
12420 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12424 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12425 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12426 StackSlot, MachinePointerInfo(),
12428 // For i64 source, we need to add the appropriate power of 2 if the input
12429 // was negative. This is the same as the optimization in
12430 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12431 // we must be careful to do the computation in x87 extended precision, not
12432 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12433 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12434 MachineMemOperand *MMO =
12435 DAG.getMachineFunction()
12436 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12437 MachineMemOperand::MOLoad, 8, 8);
12439 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12440 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12441 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12444 APInt FF(32, 0x5F800000ULL);
12446 // Check whether the sign bit is set.
12447 SDValue SignSet = DAG.getSetCC(dl,
12448 getSetCCResultType(*DAG.getContext(), MVT::i64),
12449 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12452 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12453 SDValue FudgePtr = DAG.getConstantPool(
12454 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12457 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12458 SDValue Zero = DAG.getIntPtrConstant(0);
12459 SDValue Four = DAG.getIntPtrConstant(4);
12460 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12462 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12464 // Load the value out, extending it from f32 to f80.
12465 // FIXME: Avoid the extend by constructing the right constant pool?
12466 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12467 FudgePtr, MachinePointerInfo::getConstantPool(),
12468 MVT::f32, false, false, false, 4);
12469 // Extend everything to 80 bits to force it to be done on x87.
12470 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12471 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12474 std::pair<SDValue,SDValue>
12475 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12476 bool IsSigned, bool IsReplace) const {
12479 EVT DstTy = Op.getValueType();
12481 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12482 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12486 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12487 DstTy.getSimpleVT() >= MVT::i16 &&
12488 "Unknown FP_TO_INT to lower!");
12490 // These are really Legal.
12491 if (DstTy == MVT::i32 &&
12492 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12493 return std::make_pair(SDValue(), SDValue());
12494 if (Subtarget->is64Bit() &&
12495 DstTy == MVT::i64 &&
12496 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12497 return std::make_pair(SDValue(), SDValue());
12499 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12500 // stack slot, or into the FTOL runtime function.
12501 MachineFunction &MF = DAG.getMachineFunction();
12502 unsigned MemSize = DstTy.getSizeInBits()/8;
12503 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12504 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12507 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12508 Opc = X86ISD::WIN_FTOL;
12510 switch (DstTy.getSimpleVT().SimpleTy) {
12511 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12512 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12513 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12514 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12517 SDValue Chain = DAG.getEntryNode();
12518 SDValue Value = Op.getOperand(0);
12519 EVT TheVT = Op.getOperand(0).getValueType();
12520 // FIXME This causes a redundant load/store if the SSE-class value is already
12521 // in memory, such as if it is on the callstack.
12522 if (isScalarFPTypeInSSEReg(TheVT)) {
12523 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12524 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12525 MachinePointerInfo::getFixedStack(SSFI),
12527 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12529 Chain, StackSlot, DAG.getValueType(TheVT)
12532 MachineMemOperand *MMO =
12533 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12534 MachineMemOperand::MOLoad, MemSize, MemSize);
12535 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12536 Chain = Value.getValue(1);
12537 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12538 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12541 MachineMemOperand *MMO =
12542 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12543 MachineMemOperand::MOStore, MemSize, MemSize);
12545 if (Opc != X86ISD::WIN_FTOL) {
12546 // Build the FP_TO_INT*_IN_MEM
12547 SDValue Ops[] = { Chain, Value, StackSlot };
12548 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12550 return std::make_pair(FIST, StackSlot);
12552 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12553 DAG.getVTList(MVT::Other, MVT::Glue),
12555 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12556 MVT::i32, ftol.getValue(1));
12557 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12558 MVT::i32, eax.getValue(2));
12559 SDValue Ops[] = { eax, edx };
12560 SDValue pair = IsReplace
12561 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12562 : DAG.getMergeValues(Ops, DL);
12563 return std::make_pair(pair, SDValue());
12567 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12568 const X86Subtarget *Subtarget) {
12569 MVT VT = Op->getSimpleValueType(0);
12570 SDValue In = Op->getOperand(0);
12571 MVT InVT = In.getSimpleValueType();
12574 // Optimize vectors in AVX mode:
12577 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12578 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12579 // Concat upper and lower parts.
12582 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12583 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12584 // Concat upper and lower parts.
12587 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12588 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12589 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12592 if (Subtarget->hasInt256())
12593 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12595 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12596 SDValue Undef = DAG.getUNDEF(InVT);
12597 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12598 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12599 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12601 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12602 VT.getVectorNumElements()/2);
12604 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12605 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12607 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12610 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12611 SelectionDAG &DAG) {
12612 MVT VT = Op->getSimpleValueType(0);
12613 SDValue In = Op->getOperand(0);
12614 MVT InVT = In.getSimpleValueType();
12616 unsigned int NumElts = VT.getVectorNumElements();
12617 if (NumElts != 8 && NumElts != 16)
12620 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12621 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12623 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12624 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12625 // Now we have only mask extension
12626 assert(InVT.getVectorElementType() == MVT::i1);
12627 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12628 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12629 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12630 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12631 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12632 MachinePointerInfo::getConstantPool(),
12633 false, false, false, Alignment);
12635 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12636 if (VT.is512BitVector())
12638 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12641 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12642 SelectionDAG &DAG) {
12643 if (Subtarget->hasFp256()) {
12644 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12652 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12653 SelectionDAG &DAG) {
12655 MVT VT = Op.getSimpleValueType();
12656 SDValue In = Op.getOperand(0);
12657 MVT SVT = In.getSimpleValueType();
12659 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12660 return LowerZERO_EXTEND_AVX512(Op, DAG);
12662 if (Subtarget->hasFp256()) {
12663 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12668 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12669 VT.getVectorNumElements() != SVT.getVectorNumElements());
12673 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12675 MVT VT = Op.getSimpleValueType();
12676 SDValue In = Op.getOperand(0);
12677 MVT InVT = In.getSimpleValueType();
12679 if (VT == MVT::i1) {
12680 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12681 "Invalid scalar TRUNCATE operation");
12682 if (InVT.getSizeInBits() >= 32)
12684 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12685 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12687 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12688 "Invalid TRUNCATE operation");
12690 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12691 if (VT.getVectorElementType().getSizeInBits() >=8)
12692 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12694 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12695 unsigned NumElts = InVT.getVectorNumElements();
12696 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12697 if (InVT.getSizeInBits() < 512) {
12698 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12699 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12703 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12704 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12705 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12706 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12707 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12708 MachinePointerInfo::getConstantPool(),
12709 false, false, false, Alignment);
12710 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12711 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12712 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12715 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12716 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12717 if (Subtarget->hasInt256()) {
12718 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12719 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12720 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12722 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12723 DAG.getIntPtrConstant(0));
12726 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12727 DAG.getIntPtrConstant(0));
12728 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12729 DAG.getIntPtrConstant(2));
12730 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12731 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12732 static const int ShufMask[] = {0, 2, 4, 6};
12733 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12736 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12737 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12738 if (Subtarget->hasInt256()) {
12739 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12741 SmallVector<SDValue,32> pshufbMask;
12742 for (unsigned i = 0; i < 2; ++i) {
12743 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12744 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12745 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12746 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12747 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12748 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12749 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12750 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12751 for (unsigned j = 0; j < 8; ++j)
12752 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12754 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12755 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12756 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12758 static const int ShufMask[] = {0, 2, -1, -1};
12759 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12761 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12762 DAG.getIntPtrConstant(0));
12763 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12766 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12767 DAG.getIntPtrConstant(0));
12769 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12770 DAG.getIntPtrConstant(4));
12772 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12773 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12775 // The PSHUFB mask:
12776 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12777 -1, -1, -1, -1, -1, -1, -1, -1};
12779 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12780 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12781 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12783 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12784 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12786 // The MOVLHPS Mask:
12787 static const int ShufMask2[] = {0, 1, 4, 5};
12788 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12789 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12792 // Handle truncation of V256 to V128 using shuffles.
12793 if (!VT.is128BitVector() || !InVT.is256BitVector())
12796 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12798 unsigned NumElems = VT.getVectorNumElements();
12799 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12801 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12802 // Prepare truncation shuffle mask
12803 for (unsigned i = 0; i != NumElems; ++i)
12804 MaskVec[i] = i * 2;
12805 SDValue V = DAG.getVectorShuffle(NVT, DL,
12806 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12807 DAG.getUNDEF(NVT), &MaskVec[0]);
12808 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12809 DAG.getIntPtrConstant(0));
12812 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12813 SelectionDAG &DAG) const {
12814 assert(!Op.getSimpleValueType().isVector());
12816 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12817 /*IsSigned=*/ true, /*IsReplace=*/ false);
12818 SDValue FIST = Vals.first, StackSlot = Vals.second;
12819 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12820 if (!FIST.getNode()) return Op;
12822 if (StackSlot.getNode())
12823 // Load the result.
12824 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12825 FIST, StackSlot, MachinePointerInfo(),
12826 false, false, false, 0);
12828 // The node is the result.
12832 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12833 SelectionDAG &DAG) const {
12834 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12835 /*IsSigned=*/ false, /*IsReplace=*/ false);
12836 SDValue FIST = Vals.first, StackSlot = Vals.second;
12837 assert(FIST.getNode() && "Unexpected failure");
12839 if (StackSlot.getNode())
12840 // Load the result.
12841 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12842 FIST, StackSlot, MachinePointerInfo(),
12843 false, false, false, 0);
12845 // The node is the result.
12849 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12851 MVT VT = Op.getSimpleValueType();
12852 SDValue In = Op.getOperand(0);
12853 MVT SVT = In.getSimpleValueType();
12855 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12857 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12858 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12859 In, DAG.getUNDEF(SVT)));
12862 // The only differences between FABS and FNEG are the mask and the logic op.
12863 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12864 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12865 "Wrong opcode for lowering FABS or FNEG.");
12867 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12869 MVT VT = Op.getSimpleValueType();
12870 // Assume scalar op for initialization; update for vector if needed.
12871 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12872 // generate a 16-byte vector constant and logic op even for the scalar case.
12873 // Using a 16-byte mask allows folding the load of the mask with
12874 // the logic op, so it can save (~4 bytes) on code size.
12876 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12877 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12878 // decide if we should generate a 16-byte constant mask when we only need 4 or
12879 // 8 bytes for the scalar case.
12880 if (VT.isVector()) {
12881 EltVT = VT.getVectorElementType();
12882 NumElts = VT.getVectorNumElements();
12885 unsigned EltBits = EltVT.getSizeInBits();
12886 LLVMContext *Context = DAG.getContext();
12887 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12889 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12890 Constant *C = ConstantInt::get(*Context, MaskElt);
12891 C = ConstantVector::getSplat(NumElts, C);
12892 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12893 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12894 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12895 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12896 MachinePointerInfo::getConstantPool(),
12897 false, false, false, Alignment);
12899 if (VT.isVector()) {
12900 // For a vector, cast operands to a vector type, perform the logic op,
12901 // and cast the result back to the original value type.
12902 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12903 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
12904 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12905 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
12906 return DAG.getNode(ISD::BITCAST, dl, VT,
12907 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
12909 // If not vector, then scalar.
12910 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
12911 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
12914 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12915 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12916 LLVMContext *Context = DAG.getContext();
12917 SDValue Op0 = Op.getOperand(0);
12918 SDValue Op1 = Op.getOperand(1);
12920 MVT VT = Op.getSimpleValueType();
12921 MVT SrcVT = Op1.getSimpleValueType();
12923 // If second operand is smaller, extend it first.
12924 if (SrcVT.bitsLT(VT)) {
12925 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12928 // And if it is bigger, shrink it first.
12929 if (SrcVT.bitsGT(VT)) {
12930 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12934 // At this point the operands and the result should have the same
12935 // type, and that won't be f80 since that is not custom lowered.
12937 // First get the sign bit of second operand.
12938 SmallVector<Constant*,4> CV;
12939 if (SrcVT == MVT::f64) {
12940 const fltSemantics &Sem = APFloat::IEEEdouble;
12941 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12942 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12944 const fltSemantics &Sem = APFloat::IEEEsingle;
12945 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12946 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12947 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12948 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12950 Constant *C = ConstantVector::get(CV);
12951 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12952 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12953 MachinePointerInfo::getConstantPool(),
12954 false, false, false, 16);
12955 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12957 // Shift sign bit right or left if the two operands have different types.
12958 if (SrcVT.bitsGT(VT)) {
12959 // Op0 is MVT::f32, Op1 is MVT::f64.
12960 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12961 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12962 DAG.getConstant(32, MVT::i32));
12963 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12964 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12965 DAG.getIntPtrConstant(0));
12968 // Clear first operand sign bit.
12970 if (VT == MVT::f64) {
12971 const fltSemantics &Sem = APFloat::IEEEdouble;
12972 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12973 APInt(64, ~(1ULL << 63)))));
12974 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12976 const fltSemantics &Sem = APFloat::IEEEsingle;
12977 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12978 APInt(32, ~(1U << 31)))));
12979 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12980 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12981 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12983 C = ConstantVector::get(CV);
12984 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12985 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12986 MachinePointerInfo::getConstantPool(),
12987 false, false, false, 16);
12988 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12990 // Or the value with the sign bit.
12991 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12994 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12995 SDValue N0 = Op.getOperand(0);
12997 MVT VT = Op.getSimpleValueType();
12999 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13000 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13001 DAG.getConstant(1, VT));
13002 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13005 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13007 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13008 SelectionDAG &DAG) {
13009 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13011 if (!Subtarget->hasSSE41())
13014 if (!Op->hasOneUse())
13017 SDNode *N = Op.getNode();
13020 SmallVector<SDValue, 8> Opnds;
13021 DenseMap<SDValue, unsigned> VecInMap;
13022 SmallVector<SDValue, 8> VecIns;
13023 EVT VT = MVT::Other;
13025 // Recognize a special case where a vector is casted into wide integer to
13027 Opnds.push_back(N->getOperand(0));
13028 Opnds.push_back(N->getOperand(1));
13030 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13031 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13032 // BFS traverse all OR'd operands.
13033 if (I->getOpcode() == ISD::OR) {
13034 Opnds.push_back(I->getOperand(0));
13035 Opnds.push_back(I->getOperand(1));
13036 // Re-evaluate the number of nodes to be traversed.
13037 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13041 // Quit if a non-EXTRACT_VECTOR_ELT
13042 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13045 // Quit if without a constant index.
13046 SDValue Idx = I->getOperand(1);
13047 if (!isa<ConstantSDNode>(Idx))
13050 SDValue ExtractedFromVec = I->getOperand(0);
13051 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13052 if (M == VecInMap.end()) {
13053 VT = ExtractedFromVec.getValueType();
13054 // Quit if not 128/256-bit vector.
13055 if (!VT.is128BitVector() && !VT.is256BitVector())
13057 // Quit if not the same type.
13058 if (VecInMap.begin() != VecInMap.end() &&
13059 VT != VecInMap.begin()->first.getValueType())
13061 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13062 VecIns.push_back(ExtractedFromVec);
13064 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13067 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13068 "Not extracted from 128-/256-bit vector.");
13070 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13072 for (DenseMap<SDValue, unsigned>::const_iterator
13073 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13074 // Quit if not all elements are used.
13075 if (I->second != FullMask)
13079 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13081 // Cast all vectors into TestVT for PTEST.
13082 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13083 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13085 // If more than one full vectors are evaluated, OR them first before PTEST.
13086 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13087 // Each iteration will OR 2 nodes and append the result until there is only
13088 // 1 node left, i.e. the final OR'd value of all vectors.
13089 SDValue LHS = VecIns[Slot];
13090 SDValue RHS = VecIns[Slot + 1];
13091 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13094 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13095 VecIns.back(), VecIns.back());
13098 /// \brief return true if \c Op has a use that doesn't just read flags.
13099 static bool hasNonFlagsUse(SDValue Op) {
13100 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13102 SDNode *User = *UI;
13103 unsigned UOpNo = UI.getOperandNo();
13104 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13105 // Look pass truncate.
13106 UOpNo = User->use_begin().getOperandNo();
13107 User = *User->use_begin();
13110 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13111 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13117 /// Emit nodes that will be selected as "test Op0,Op0", or something
13119 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13120 SelectionDAG &DAG) const {
13121 if (Op.getValueType() == MVT::i1)
13122 // KORTEST instruction should be selected
13123 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13124 DAG.getConstant(0, Op.getValueType()));
13126 // CF and OF aren't always set the way we want. Determine which
13127 // of these we need.
13128 bool NeedCF = false;
13129 bool NeedOF = false;
13132 case X86::COND_A: case X86::COND_AE:
13133 case X86::COND_B: case X86::COND_BE:
13136 case X86::COND_G: case X86::COND_GE:
13137 case X86::COND_L: case X86::COND_LE:
13138 case X86::COND_O: case X86::COND_NO: {
13139 // Check if we really need to set the
13140 // Overflow flag. If NoSignedWrap is present
13141 // that is not actually needed.
13142 switch (Op->getOpcode()) {
13147 const BinaryWithFlagsSDNode *BinNode =
13148 cast<BinaryWithFlagsSDNode>(Op.getNode());
13149 if (BinNode->hasNoSignedWrap())
13159 // See if we can use the EFLAGS value from the operand instead of
13160 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13161 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13162 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13163 // Emit a CMP with 0, which is the TEST pattern.
13164 //if (Op.getValueType() == MVT::i1)
13165 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13166 // DAG.getConstant(0, MVT::i1));
13167 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13168 DAG.getConstant(0, Op.getValueType()));
13170 unsigned Opcode = 0;
13171 unsigned NumOperands = 0;
13173 // Truncate operations may prevent the merge of the SETCC instruction
13174 // and the arithmetic instruction before it. Attempt to truncate the operands
13175 // of the arithmetic instruction and use a reduced bit-width instruction.
13176 bool NeedTruncation = false;
13177 SDValue ArithOp = Op;
13178 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13179 SDValue Arith = Op->getOperand(0);
13180 // Both the trunc and the arithmetic op need to have one user each.
13181 if (Arith->hasOneUse())
13182 switch (Arith.getOpcode()) {
13189 NeedTruncation = true;
13195 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13196 // which may be the result of a CAST. We use the variable 'Op', which is the
13197 // non-casted variable when we check for possible users.
13198 switch (ArithOp.getOpcode()) {
13200 // Due to an isel shortcoming, be conservative if this add is likely to be
13201 // selected as part of a load-modify-store instruction. When the root node
13202 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13203 // uses of other nodes in the match, such as the ADD in this case. This
13204 // leads to the ADD being left around and reselected, with the result being
13205 // two adds in the output. Alas, even if none our users are stores, that
13206 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13207 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13208 // climbing the DAG back to the root, and it doesn't seem to be worth the
13210 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13211 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13212 if (UI->getOpcode() != ISD::CopyToReg &&
13213 UI->getOpcode() != ISD::SETCC &&
13214 UI->getOpcode() != ISD::STORE)
13217 if (ConstantSDNode *C =
13218 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13219 // An add of one will be selected as an INC.
13220 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13221 Opcode = X86ISD::INC;
13226 // An add of negative one (subtract of one) will be selected as a DEC.
13227 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13228 Opcode = X86ISD::DEC;
13234 // Otherwise use a regular EFLAGS-setting add.
13235 Opcode = X86ISD::ADD;
13240 // If we have a constant logical shift that's only used in a comparison
13241 // against zero turn it into an equivalent AND. This allows turning it into
13242 // a TEST instruction later.
13243 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13244 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13245 EVT VT = Op.getValueType();
13246 unsigned BitWidth = VT.getSizeInBits();
13247 unsigned ShAmt = Op->getConstantOperandVal(1);
13248 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13250 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13251 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13252 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13253 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13255 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13256 DAG.getConstant(Mask, VT));
13257 DAG.ReplaceAllUsesWith(Op, New);
13263 // If the primary and result isn't used, don't bother using X86ISD::AND,
13264 // because a TEST instruction will be better.
13265 if (!hasNonFlagsUse(Op))
13271 // Due to the ISEL shortcoming noted above, be conservative if this op is
13272 // likely to be selected as part of a load-modify-store instruction.
13273 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13274 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13275 if (UI->getOpcode() == ISD::STORE)
13278 // Otherwise use a regular EFLAGS-setting instruction.
13279 switch (ArithOp.getOpcode()) {
13280 default: llvm_unreachable("unexpected operator!");
13281 case ISD::SUB: Opcode = X86ISD::SUB; break;
13282 case ISD::XOR: Opcode = X86ISD::XOR; break;
13283 case ISD::AND: Opcode = X86ISD::AND; break;
13285 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13286 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13287 if (EFLAGS.getNode())
13290 Opcode = X86ISD::OR;
13304 return SDValue(Op.getNode(), 1);
13310 // If we found that truncation is beneficial, perform the truncation and
13312 if (NeedTruncation) {
13313 EVT VT = Op.getValueType();
13314 SDValue WideVal = Op->getOperand(0);
13315 EVT WideVT = WideVal.getValueType();
13316 unsigned ConvertedOp = 0;
13317 // Use a target machine opcode to prevent further DAGCombine
13318 // optimizations that may separate the arithmetic operations
13319 // from the setcc node.
13320 switch (WideVal.getOpcode()) {
13322 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13323 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13324 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13325 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13326 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13330 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13331 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13332 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13333 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13334 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13340 // Emit a CMP with 0, which is the TEST pattern.
13341 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13342 DAG.getConstant(0, Op.getValueType()));
13344 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13345 SmallVector<SDValue, 4> Ops;
13346 for (unsigned i = 0; i != NumOperands; ++i)
13347 Ops.push_back(Op.getOperand(i));
13349 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13350 DAG.ReplaceAllUsesWith(Op, New);
13351 return SDValue(New.getNode(), 1);
13354 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13356 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13357 SDLoc dl, SelectionDAG &DAG) const {
13358 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13359 if (C->getAPIntValue() == 0)
13360 return EmitTest(Op0, X86CC, dl, DAG);
13362 if (Op0.getValueType() == MVT::i1)
13363 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13366 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13367 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13368 // Do the comparison at i32 if it's smaller, besides the Atom case.
13369 // This avoids subregister aliasing issues. Keep the smaller reference
13370 // if we're optimizing for size, however, as that'll allow better folding
13371 // of memory operations.
13372 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13373 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13374 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13375 !Subtarget->isAtom()) {
13376 unsigned ExtendOp =
13377 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13378 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13379 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13381 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13382 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13383 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13385 return SDValue(Sub.getNode(), 1);
13387 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13390 /// Convert a comparison if required by the subtarget.
13391 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13392 SelectionDAG &DAG) const {
13393 // If the subtarget does not support the FUCOMI instruction, floating-point
13394 // comparisons have to be converted.
13395 if (Subtarget->hasCMov() ||
13396 Cmp.getOpcode() != X86ISD::CMP ||
13397 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13398 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13401 // The instruction selector will select an FUCOM instruction instead of
13402 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13403 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13404 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13406 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13407 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13408 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13409 DAG.getConstant(8, MVT::i8));
13410 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13411 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13414 static bool isAllOnes(SDValue V) {
13415 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13416 return C && C->isAllOnesValue();
13419 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13420 /// if it's possible.
13421 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13422 SDLoc dl, SelectionDAG &DAG) const {
13423 SDValue Op0 = And.getOperand(0);
13424 SDValue Op1 = And.getOperand(1);
13425 if (Op0.getOpcode() == ISD::TRUNCATE)
13426 Op0 = Op0.getOperand(0);
13427 if (Op1.getOpcode() == ISD::TRUNCATE)
13428 Op1 = Op1.getOperand(0);
13431 if (Op1.getOpcode() == ISD::SHL)
13432 std::swap(Op0, Op1);
13433 if (Op0.getOpcode() == ISD::SHL) {
13434 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13435 if (And00C->getZExtValue() == 1) {
13436 // If we looked past a truncate, check that it's only truncating away
13438 unsigned BitWidth = Op0.getValueSizeInBits();
13439 unsigned AndBitWidth = And.getValueSizeInBits();
13440 if (BitWidth > AndBitWidth) {
13442 DAG.computeKnownBits(Op0, Zeros, Ones);
13443 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13447 RHS = Op0.getOperand(1);
13449 } else if (Op1.getOpcode() == ISD::Constant) {
13450 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13451 uint64_t AndRHSVal = AndRHS->getZExtValue();
13452 SDValue AndLHS = Op0;
13454 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13455 LHS = AndLHS.getOperand(0);
13456 RHS = AndLHS.getOperand(1);
13459 // Use BT if the immediate can't be encoded in a TEST instruction.
13460 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13462 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13466 if (LHS.getNode()) {
13467 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13468 // instruction. Since the shift amount is in-range-or-undefined, we know
13469 // that doing a bittest on the i32 value is ok. We extend to i32 because
13470 // the encoding for the i16 version is larger than the i32 version.
13471 // Also promote i16 to i32 for performance / code size reason.
13472 if (LHS.getValueType() == MVT::i8 ||
13473 LHS.getValueType() == MVT::i16)
13474 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13476 // If the operand types disagree, extend the shift amount to match. Since
13477 // BT ignores high bits (like shifts) we can use anyextend.
13478 if (LHS.getValueType() != RHS.getValueType())
13479 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13481 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13482 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13483 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13484 DAG.getConstant(Cond, MVT::i8), BT);
13490 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13492 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13497 // SSE Condition code mapping:
13506 switch (SetCCOpcode) {
13507 default: llvm_unreachable("Unexpected SETCC condition");
13509 case ISD::SETEQ: SSECC = 0; break;
13511 case ISD::SETGT: Swap = true; // Fallthrough
13513 case ISD::SETOLT: SSECC = 1; break;
13515 case ISD::SETGE: Swap = true; // Fallthrough
13517 case ISD::SETOLE: SSECC = 2; break;
13518 case ISD::SETUO: SSECC = 3; break;
13520 case ISD::SETNE: SSECC = 4; break;
13521 case ISD::SETULE: Swap = true; // Fallthrough
13522 case ISD::SETUGE: SSECC = 5; break;
13523 case ISD::SETULT: Swap = true; // Fallthrough
13524 case ISD::SETUGT: SSECC = 6; break;
13525 case ISD::SETO: SSECC = 7; break;
13527 case ISD::SETONE: SSECC = 8; break;
13530 std::swap(Op0, Op1);
13535 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13536 // ones, and then concatenate the result back.
13537 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13538 MVT VT = Op.getSimpleValueType();
13540 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13541 "Unsupported value type for operation");
13543 unsigned NumElems = VT.getVectorNumElements();
13545 SDValue CC = Op.getOperand(2);
13547 // Extract the LHS vectors
13548 SDValue LHS = Op.getOperand(0);
13549 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13550 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13552 // Extract the RHS vectors
13553 SDValue RHS = Op.getOperand(1);
13554 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13555 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13557 // Issue the operation on the smaller types and concatenate the result back
13558 MVT EltVT = VT.getVectorElementType();
13559 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13560 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13561 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13562 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13565 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13566 const X86Subtarget *Subtarget) {
13567 SDValue Op0 = Op.getOperand(0);
13568 SDValue Op1 = Op.getOperand(1);
13569 SDValue CC = Op.getOperand(2);
13570 MVT VT = Op.getSimpleValueType();
13573 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13574 Op.getValueType().getScalarType() == MVT::i1 &&
13575 "Cannot set masked compare for this operation");
13577 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13579 bool Unsigned = false;
13582 switch (SetCCOpcode) {
13583 default: llvm_unreachable("Unexpected SETCC condition");
13584 case ISD::SETNE: SSECC = 4; break;
13585 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13586 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13587 case ISD::SETLT: Swap = true; //fall-through
13588 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13589 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13590 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13591 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13592 case ISD::SETULE: Unsigned = true; //fall-through
13593 case ISD::SETLE: SSECC = 2; break;
13597 std::swap(Op0, Op1);
13599 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13600 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13601 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13602 DAG.getConstant(SSECC, MVT::i8));
13605 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13606 /// operand \p Op1. If non-trivial (for example because it's not constant)
13607 /// return an empty value.
13608 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13610 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13614 MVT VT = Op1.getSimpleValueType();
13615 MVT EVT = VT.getVectorElementType();
13616 unsigned n = VT.getVectorNumElements();
13617 SmallVector<SDValue, 8> ULTOp1;
13619 for (unsigned i = 0; i < n; ++i) {
13620 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13621 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13624 // Avoid underflow.
13625 APInt Val = Elt->getAPIntValue();
13629 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13632 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13635 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13636 SelectionDAG &DAG) {
13637 SDValue Op0 = Op.getOperand(0);
13638 SDValue Op1 = Op.getOperand(1);
13639 SDValue CC = Op.getOperand(2);
13640 MVT VT = Op.getSimpleValueType();
13641 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13642 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13647 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13648 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13651 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13652 unsigned Opc = X86ISD::CMPP;
13653 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13654 assert(VT.getVectorNumElements() <= 16);
13655 Opc = X86ISD::CMPM;
13657 // In the two special cases we can't handle, emit two comparisons.
13660 unsigned CombineOpc;
13661 if (SetCCOpcode == ISD::SETUEQ) {
13662 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13664 assert(SetCCOpcode == ISD::SETONE);
13665 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13668 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13669 DAG.getConstant(CC0, MVT::i8));
13670 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13671 DAG.getConstant(CC1, MVT::i8));
13672 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13674 // Handle all other FP comparisons here.
13675 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13676 DAG.getConstant(SSECC, MVT::i8));
13679 // Break 256-bit integer vector compare into smaller ones.
13680 if (VT.is256BitVector() && !Subtarget->hasInt256())
13681 return Lower256IntVSETCC(Op, DAG);
13683 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13684 EVT OpVT = Op1.getValueType();
13685 if (Subtarget->hasAVX512()) {
13686 if (Op1.getValueType().is512BitVector() ||
13687 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13688 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13689 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13691 // In AVX-512 architecture setcc returns mask with i1 elements,
13692 // But there is no compare instruction for i8 and i16 elements in KNL.
13693 // We are not talking about 512-bit operands in this case, these
13694 // types are illegal.
13696 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13697 OpVT.getVectorElementType().getSizeInBits() >= 8))
13698 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13699 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13702 // We are handling one of the integer comparisons here. Since SSE only has
13703 // GT and EQ comparisons for integer, swapping operands and multiple
13704 // operations may be required for some comparisons.
13706 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13707 bool Subus = false;
13709 switch (SetCCOpcode) {
13710 default: llvm_unreachable("Unexpected SETCC condition");
13711 case ISD::SETNE: Invert = true;
13712 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13713 case ISD::SETLT: Swap = true;
13714 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13715 case ISD::SETGE: Swap = true;
13716 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13717 Invert = true; break;
13718 case ISD::SETULT: Swap = true;
13719 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13720 FlipSigns = true; break;
13721 case ISD::SETUGE: Swap = true;
13722 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13723 FlipSigns = true; Invert = true; break;
13726 // Special case: Use min/max operations for SETULE/SETUGE
13727 MVT VET = VT.getVectorElementType();
13729 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13730 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13733 switch (SetCCOpcode) {
13735 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13736 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13739 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13742 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13743 if (!MinMax && hasSubus) {
13744 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13746 // t = psubus Op0, Op1
13747 // pcmpeq t, <0..0>
13748 switch (SetCCOpcode) {
13750 case ISD::SETULT: {
13751 // If the comparison is against a constant we can turn this into a
13752 // setule. With psubus, setule does not require a swap. This is
13753 // beneficial because the constant in the register is no longer
13754 // destructed as the destination so it can be hoisted out of a loop.
13755 // Only do this pre-AVX since vpcmp* is no longer destructive.
13756 if (Subtarget->hasAVX())
13758 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13759 if (ULEOp1.getNode()) {
13761 Subus = true; Invert = false; Swap = false;
13765 // Psubus is better than flip-sign because it requires no inversion.
13766 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13767 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13771 Opc = X86ISD::SUBUS;
13777 std::swap(Op0, Op1);
13779 // Check that the operation in question is available (most are plain SSE2,
13780 // but PCMPGTQ and PCMPEQQ have different requirements).
13781 if (VT == MVT::v2i64) {
13782 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13783 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13785 // First cast everything to the right type.
13786 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13787 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13789 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13790 // bits of the inputs before performing those operations. The lower
13791 // compare is always unsigned.
13794 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13796 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13797 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13798 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13799 Sign, Zero, Sign, Zero);
13801 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13802 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13804 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13805 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13806 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13808 // Create masks for only the low parts/high parts of the 64 bit integers.
13809 static const int MaskHi[] = { 1, 1, 3, 3 };
13810 static const int MaskLo[] = { 0, 0, 2, 2 };
13811 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13812 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13813 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13815 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13816 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13819 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13821 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13824 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13825 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13826 // pcmpeqd + pshufd + pand.
13827 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13829 // First cast everything to the right type.
13830 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13831 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13834 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13836 // Make sure the lower and upper halves are both all-ones.
13837 static const int Mask[] = { 1, 0, 3, 2 };
13838 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13839 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13842 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13844 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13848 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13849 // bits of the inputs before performing those operations.
13851 EVT EltVT = VT.getVectorElementType();
13852 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13853 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13854 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13857 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13859 // If the logical-not of the result is required, perform that now.
13861 Result = DAG.getNOT(dl, Result, VT);
13864 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13867 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13868 getZeroVector(VT, Subtarget, DAG, dl));
13873 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13875 MVT VT = Op.getSimpleValueType();
13877 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13879 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13880 && "SetCC type must be 8-bit or 1-bit integer");
13881 SDValue Op0 = Op.getOperand(0);
13882 SDValue Op1 = Op.getOperand(1);
13884 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13886 // Optimize to BT if possible.
13887 // Lower (X & (1 << N)) == 0 to BT(X, N).
13888 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13889 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13890 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13891 Op1.getOpcode() == ISD::Constant &&
13892 cast<ConstantSDNode>(Op1)->isNullValue() &&
13893 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13894 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13895 if (NewSetCC.getNode())
13899 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13901 if (Op1.getOpcode() == ISD::Constant &&
13902 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13903 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13904 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13906 // If the input is a setcc, then reuse the input setcc or use a new one with
13907 // the inverted condition.
13908 if (Op0.getOpcode() == X86ISD::SETCC) {
13909 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13910 bool Invert = (CC == ISD::SETNE) ^
13911 cast<ConstantSDNode>(Op1)->isNullValue();
13915 CCode = X86::GetOppositeBranchCondition(CCode);
13916 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13917 DAG.getConstant(CCode, MVT::i8),
13918 Op0.getOperand(1));
13920 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13924 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13925 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13926 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13928 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13929 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13932 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13933 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13934 if (X86CC == X86::COND_INVALID)
13937 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13938 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13939 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13940 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13942 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13946 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13947 static bool isX86LogicalCmp(SDValue Op) {
13948 unsigned Opc = Op.getNode()->getOpcode();
13949 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13950 Opc == X86ISD::SAHF)
13952 if (Op.getResNo() == 1 &&
13953 (Opc == X86ISD::ADD ||
13954 Opc == X86ISD::SUB ||
13955 Opc == X86ISD::ADC ||
13956 Opc == X86ISD::SBB ||
13957 Opc == X86ISD::SMUL ||
13958 Opc == X86ISD::UMUL ||
13959 Opc == X86ISD::INC ||
13960 Opc == X86ISD::DEC ||
13961 Opc == X86ISD::OR ||
13962 Opc == X86ISD::XOR ||
13963 Opc == X86ISD::AND))
13966 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13972 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13973 if (V.getOpcode() != ISD::TRUNCATE)
13976 SDValue VOp0 = V.getOperand(0);
13977 unsigned InBits = VOp0.getValueSizeInBits();
13978 unsigned Bits = V.getValueSizeInBits();
13979 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13982 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13983 bool addTest = true;
13984 SDValue Cond = Op.getOperand(0);
13985 SDValue Op1 = Op.getOperand(1);
13986 SDValue Op2 = Op.getOperand(2);
13988 EVT VT = Op1.getValueType();
13991 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13992 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13993 // sequence later on.
13994 if (Cond.getOpcode() == ISD::SETCC &&
13995 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13996 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13997 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13998 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13999 int SSECC = translateX86FSETCC(
14000 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14003 if (Subtarget->hasAVX512()) {
14004 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14005 DAG.getConstant(SSECC, MVT::i8));
14006 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14008 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14009 DAG.getConstant(SSECC, MVT::i8));
14010 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14011 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14012 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14016 if (Cond.getOpcode() == ISD::SETCC) {
14017 SDValue NewCond = LowerSETCC(Cond, DAG);
14018 if (NewCond.getNode())
14022 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14023 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14024 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14025 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14026 if (Cond.getOpcode() == X86ISD::SETCC &&
14027 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14028 isZero(Cond.getOperand(1).getOperand(1))) {
14029 SDValue Cmp = Cond.getOperand(1);
14031 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14033 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14034 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14035 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14037 SDValue CmpOp0 = Cmp.getOperand(0);
14038 // Apply further optimizations for special cases
14039 // (select (x != 0), -1, 0) -> neg & sbb
14040 // (select (x == 0), 0, -1) -> neg & sbb
14041 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14042 if (YC->isNullValue() &&
14043 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14044 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14045 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14046 DAG.getConstant(0, CmpOp0.getValueType()),
14048 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14049 DAG.getConstant(X86::COND_B, MVT::i8),
14050 SDValue(Neg.getNode(), 1));
14054 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14055 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14056 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14058 SDValue Res = // Res = 0 or -1.
14059 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14060 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14062 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14063 Res = DAG.getNOT(DL, Res, Res.getValueType());
14065 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14066 if (!N2C || !N2C->isNullValue())
14067 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14072 // Look past (and (setcc_carry (cmp ...)), 1).
14073 if (Cond.getOpcode() == ISD::AND &&
14074 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14075 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14076 if (C && C->getAPIntValue() == 1)
14077 Cond = Cond.getOperand(0);
14080 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14081 // setting operand in place of the X86ISD::SETCC.
14082 unsigned CondOpcode = Cond.getOpcode();
14083 if (CondOpcode == X86ISD::SETCC ||
14084 CondOpcode == X86ISD::SETCC_CARRY) {
14085 CC = Cond.getOperand(0);
14087 SDValue Cmp = Cond.getOperand(1);
14088 unsigned Opc = Cmp.getOpcode();
14089 MVT VT = Op.getSimpleValueType();
14091 bool IllegalFPCMov = false;
14092 if (VT.isFloatingPoint() && !VT.isVector() &&
14093 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14094 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14096 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14097 Opc == X86ISD::BT) { // FIXME
14101 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14102 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14103 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14104 Cond.getOperand(0).getValueType() != MVT::i8)) {
14105 SDValue LHS = Cond.getOperand(0);
14106 SDValue RHS = Cond.getOperand(1);
14107 unsigned X86Opcode;
14110 switch (CondOpcode) {
14111 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14112 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14113 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14114 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14115 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14116 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14117 default: llvm_unreachable("unexpected overflowing operator");
14119 if (CondOpcode == ISD::UMULO)
14120 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14123 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14125 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14127 if (CondOpcode == ISD::UMULO)
14128 Cond = X86Op.getValue(2);
14130 Cond = X86Op.getValue(1);
14132 CC = DAG.getConstant(X86Cond, MVT::i8);
14137 // Look pass the truncate if the high bits are known zero.
14138 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14139 Cond = Cond.getOperand(0);
14141 // We know the result of AND is compared against zero. Try to match
14143 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14144 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14145 if (NewSetCC.getNode()) {
14146 CC = NewSetCC.getOperand(0);
14147 Cond = NewSetCC.getOperand(1);
14154 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14155 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14158 // a < b ? -1 : 0 -> RES = ~setcc_carry
14159 // a < b ? 0 : -1 -> RES = setcc_carry
14160 // a >= b ? -1 : 0 -> RES = setcc_carry
14161 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14162 if (Cond.getOpcode() == X86ISD::SUB) {
14163 Cond = ConvertCmpIfNecessary(Cond, DAG);
14164 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14166 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14167 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14168 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14169 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14170 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14171 return DAG.getNOT(DL, Res, Res.getValueType());
14176 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14177 // widen the cmov and push the truncate through. This avoids introducing a new
14178 // branch during isel and doesn't add any extensions.
14179 if (Op.getValueType() == MVT::i8 &&
14180 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14181 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14182 if (T1.getValueType() == T2.getValueType() &&
14183 // Blacklist CopyFromReg to avoid partial register stalls.
14184 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14185 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14186 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14187 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14191 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14192 // condition is true.
14193 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14194 SDValue Ops[] = { Op2, Op1, CC, Cond };
14195 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14198 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14199 MVT VT = Op->getSimpleValueType(0);
14200 SDValue In = Op->getOperand(0);
14201 MVT InVT = In.getSimpleValueType();
14204 unsigned int NumElts = VT.getVectorNumElements();
14205 if (NumElts != 8 && NumElts != 16)
14208 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14209 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14211 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14212 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14214 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14215 Constant *C = ConstantInt::get(*DAG.getContext(),
14216 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14218 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14219 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14220 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14221 MachinePointerInfo::getConstantPool(),
14222 false, false, false, Alignment);
14223 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14224 if (VT.is512BitVector())
14226 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14229 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14230 SelectionDAG &DAG) {
14231 MVT VT = Op->getSimpleValueType(0);
14232 SDValue In = Op->getOperand(0);
14233 MVT InVT = In.getSimpleValueType();
14236 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14237 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14239 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14240 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14241 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14244 if (Subtarget->hasInt256())
14245 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14247 // Optimize vectors in AVX mode
14248 // Sign extend v8i16 to v8i32 and
14251 // Divide input vector into two parts
14252 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14253 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14254 // concat the vectors to original VT
14256 unsigned NumElems = InVT.getVectorNumElements();
14257 SDValue Undef = DAG.getUNDEF(InVT);
14259 SmallVector<int,8> ShufMask1(NumElems, -1);
14260 for (unsigned i = 0; i != NumElems/2; ++i)
14263 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14265 SmallVector<int,8> ShufMask2(NumElems, -1);
14266 for (unsigned i = 0; i != NumElems/2; ++i)
14267 ShufMask2[i] = i + NumElems/2;
14269 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14271 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14272 VT.getVectorNumElements()/2);
14274 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14275 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14277 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14280 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14281 // may emit an illegal shuffle but the expansion is still better than scalar
14282 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14283 // we'll emit a shuffle and a arithmetic shift.
14284 // TODO: It is possible to support ZExt by zeroing the undef values during
14285 // the shuffle phase or after the shuffle.
14286 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14287 SelectionDAG &DAG) {
14288 MVT RegVT = Op.getSimpleValueType();
14289 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14290 assert(RegVT.isInteger() &&
14291 "We only custom lower integer vector sext loads.");
14293 // Nothing useful we can do without SSE2 shuffles.
14294 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14296 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14298 EVT MemVT = Ld->getMemoryVT();
14299 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14300 unsigned RegSz = RegVT.getSizeInBits();
14302 ISD::LoadExtType Ext = Ld->getExtensionType();
14304 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14305 && "Only anyext and sext are currently implemented.");
14306 assert(MemVT != RegVT && "Cannot extend to the same type");
14307 assert(MemVT.isVector() && "Must load a vector from memory");
14309 unsigned NumElems = RegVT.getVectorNumElements();
14310 unsigned MemSz = MemVT.getSizeInBits();
14311 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14313 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14314 // The only way in which we have a legal 256-bit vector result but not the
14315 // integer 256-bit operations needed to directly lower a sextload is if we
14316 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14317 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14318 // correctly legalized. We do this late to allow the canonical form of
14319 // sextload to persist throughout the rest of the DAG combiner -- it wants
14320 // to fold together any extensions it can, and so will fuse a sign_extend
14321 // of an sextload into a sextload targeting a wider value.
14323 if (MemSz == 128) {
14324 // Just switch this to a normal load.
14325 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14326 "it must be a legal 128-bit vector "
14328 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14329 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14330 Ld->isInvariant(), Ld->getAlignment());
14332 assert(MemSz < 128 &&
14333 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14334 // Do an sext load to a 128-bit vector type. We want to use the same
14335 // number of elements, but elements half as wide. This will end up being
14336 // recursively lowered by this routine, but will succeed as we definitely
14337 // have all the necessary features if we're using AVX1.
14339 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14340 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14342 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14343 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14344 Ld->isNonTemporal(), Ld->isInvariant(),
14345 Ld->getAlignment());
14348 // Replace chain users with the new chain.
14349 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14350 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14352 // Finally, do a normal sign-extend to the desired register.
14353 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14356 // All sizes must be a power of two.
14357 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14358 "Non-power-of-two elements are not custom lowered!");
14360 // Attempt to load the original value using scalar loads.
14361 // Find the largest scalar type that divides the total loaded size.
14362 MVT SclrLoadTy = MVT::i8;
14363 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14364 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14365 MVT Tp = (MVT::SimpleValueType)tp;
14366 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14371 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14372 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14374 SclrLoadTy = MVT::f64;
14376 // Calculate the number of scalar loads that we need to perform
14377 // in order to load our vector from memory.
14378 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14380 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14381 "Can only lower sext loads with a single scalar load!");
14383 unsigned loadRegZize = RegSz;
14384 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14387 // Represent our vector as a sequence of elements which are the
14388 // largest scalar that we can load.
14389 EVT LoadUnitVecVT = EVT::getVectorVT(
14390 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14392 // Represent the data using the same element type that is stored in
14393 // memory. In practice, we ''widen'' MemVT.
14395 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14396 loadRegZize / MemVT.getScalarType().getSizeInBits());
14398 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14399 "Invalid vector type");
14401 // We can't shuffle using an illegal type.
14402 assert(TLI.isTypeLegal(WideVecVT) &&
14403 "We only lower types that form legal widened vector types");
14405 SmallVector<SDValue, 8> Chains;
14406 SDValue Ptr = Ld->getBasePtr();
14407 SDValue Increment =
14408 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14409 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14411 for (unsigned i = 0; i < NumLoads; ++i) {
14412 // Perform a single load.
14413 SDValue ScalarLoad =
14414 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14415 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14416 Ld->getAlignment());
14417 Chains.push_back(ScalarLoad.getValue(1));
14418 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14419 // another round of DAGCombining.
14421 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14423 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14424 ScalarLoad, DAG.getIntPtrConstant(i));
14426 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14429 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14431 // Bitcast the loaded value to a vector of the original element type, in
14432 // the size of the target vector type.
14433 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14434 unsigned SizeRatio = RegSz / MemSz;
14436 if (Ext == ISD::SEXTLOAD) {
14437 // If we have SSE4.1, we can directly emit a VSEXT node.
14438 if (Subtarget->hasSSE41()) {
14439 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14440 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14444 // Otherwise we'll shuffle the small elements in the high bits of the
14445 // larger type and perform an arithmetic shift. If the shift is not legal
14446 // it's better to scalarize.
14447 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14448 "We can't implement a sext load without an arithmetic right shift!");
14450 // Redistribute the loaded elements into the different locations.
14451 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14452 for (unsigned i = 0; i != NumElems; ++i)
14453 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14455 SDValue Shuff = DAG.getVectorShuffle(
14456 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14458 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14460 // Build the arithmetic shift.
14461 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14462 MemVT.getVectorElementType().getSizeInBits();
14464 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14466 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14470 // Redistribute the loaded elements into the different locations.
14471 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14472 for (unsigned i = 0; i != NumElems; ++i)
14473 ShuffleVec[i * SizeRatio] = i;
14475 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14476 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14478 // Bitcast to the requested type.
14479 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14480 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14484 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14485 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14486 // from the AND / OR.
14487 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14488 Opc = Op.getOpcode();
14489 if (Opc != ISD::OR && Opc != ISD::AND)
14491 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14492 Op.getOperand(0).hasOneUse() &&
14493 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14494 Op.getOperand(1).hasOneUse());
14497 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14498 // 1 and that the SETCC node has a single use.
14499 static bool isXor1OfSetCC(SDValue Op) {
14500 if (Op.getOpcode() != ISD::XOR)
14502 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14503 if (N1C && N1C->getAPIntValue() == 1) {
14504 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14505 Op.getOperand(0).hasOneUse();
14510 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14511 bool addTest = true;
14512 SDValue Chain = Op.getOperand(0);
14513 SDValue Cond = Op.getOperand(1);
14514 SDValue Dest = Op.getOperand(2);
14517 bool Inverted = false;
14519 if (Cond.getOpcode() == ISD::SETCC) {
14520 // Check for setcc([su]{add,sub,mul}o == 0).
14521 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14522 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14523 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14524 Cond.getOperand(0).getResNo() == 1 &&
14525 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14526 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14527 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14528 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14529 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14530 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14532 Cond = Cond.getOperand(0);
14534 SDValue NewCond = LowerSETCC(Cond, DAG);
14535 if (NewCond.getNode())
14540 // FIXME: LowerXALUO doesn't handle these!!
14541 else if (Cond.getOpcode() == X86ISD::ADD ||
14542 Cond.getOpcode() == X86ISD::SUB ||
14543 Cond.getOpcode() == X86ISD::SMUL ||
14544 Cond.getOpcode() == X86ISD::UMUL)
14545 Cond = LowerXALUO(Cond, DAG);
14548 // Look pass (and (setcc_carry (cmp ...)), 1).
14549 if (Cond.getOpcode() == ISD::AND &&
14550 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14551 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14552 if (C && C->getAPIntValue() == 1)
14553 Cond = Cond.getOperand(0);
14556 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14557 // setting operand in place of the X86ISD::SETCC.
14558 unsigned CondOpcode = Cond.getOpcode();
14559 if (CondOpcode == X86ISD::SETCC ||
14560 CondOpcode == X86ISD::SETCC_CARRY) {
14561 CC = Cond.getOperand(0);
14563 SDValue Cmp = Cond.getOperand(1);
14564 unsigned Opc = Cmp.getOpcode();
14565 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14566 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14570 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14574 // These can only come from an arithmetic instruction with overflow,
14575 // e.g. SADDO, UADDO.
14576 Cond = Cond.getNode()->getOperand(1);
14582 CondOpcode = Cond.getOpcode();
14583 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14584 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14585 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14586 Cond.getOperand(0).getValueType() != MVT::i8)) {
14587 SDValue LHS = Cond.getOperand(0);
14588 SDValue RHS = Cond.getOperand(1);
14589 unsigned X86Opcode;
14592 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14593 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14595 switch (CondOpcode) {
14596 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14598 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14600 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14603 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14604 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14608 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14611 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14612 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14613 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14614 default: llvm_unreachable("unexpected overflowing operator");
14617 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14618 if (CondOpcode == ISD::UMULO)
14619 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14622 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14624 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14626 if (CondOpcode == ISD::UMULO)
14627 Cond = X86Op.getValue(2);
14629 Cond = X86Op.getValue(1);
14631 CC = DAG.getConstant(X86Cond, MVT::i8);
14635 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14636 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14637 if (CondOpc == ISD::OR) {
14638 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14639 // two branches instead of an explicit OR instruction with a
14641 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14642 isX86LogicalCmp(Cmp)) {
14643 CC = Cond.getOperand(0).getOperand(0);
14644 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14645 Chain, Dest, CC, Cmp);
14646 CC = Cond.getOperand(1).getOperand(0);
14650 } else { // ISD::AND
14651 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14652 // two branches instead of an explicit AND instruction with a
14653 // separate test. However, we only do this if this block doesn't
14654 // have a fall-through edge, because this requires an explicit
14655 // jmp when the condition is false.
14656 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14657 isX86LogicalCmp(Cmp) &&
14658 Op.getNode()->hasOneUse()) {
14659 X86::CondCode CCode =
14660 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14661 CCode = X86::GetOppositeBranchCondition(CCode);
14662 CC = DAG.getConstant(CCode, MVT::i8);
14663 SDNode *User = *Op.getNode()->use_begin();
14664 // Look for an unconditional branch following this conditional branch.
14665 // We need this because we need to reverse the successors in order
14666 // to implement FCMP_OEQ.
14667 if (User->getOpcode() == ISD::BR) {
14668 SDValue FalseBB = User->getOperand(1);
14670 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14671 assert(NewBR == User);
14675 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14676 Chain, Dest, CC, Cmp);
14677 X86::CondCode CCode =
14678 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14679 CCode = X86::GetOppositeBranchCondition(CCode);
14680 CC = DAG.getConstant(CCode, MVT::i8);
14686 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14687 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14688 // It should be transformed during dag combiner except when the condition
14689 // is set by a arithmetics with overflow node.
14690 X86::CondCode CCode =
14691 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14692 CCode = X86::GetOppositeBranchCondition(CCode);
14693 CC = DAG.getConstant(CCode, MVT::i8);
14694 Cond = Cond.getOperand(0).getOperand(1);
14696 } else if (Cond.getOpcode() == ISD::SETCC &&
14697 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14698 // For FCMP_OEQ, we can emit
14699 // two branches instead of an explicit AND instruction with a
14700 // separate test. However, we only do this if this block doesn't
14701 // have a fall-through edge, because this requires an explicit
14702 // jmp when the condition is false.
14703 if (Op.getNode()->hasOneUse()) {
14704 SDNode *User = *Op.getNode()->use_begin();
14705 // Look for an unconditional branch following this conditional branch.
14706 // We need this because we need to reverse the successors in order
14707 // to implement FCMP_OEQ.
14708 if (User->getOpcode() == ISD::BR) {
14709 SDValue FalseBB = User->getOperand(1);
14711 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14712 assert(NewBR == User);
14716 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14717 Cond.getOperand(0), Cond.getOperand(1));
14718 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14719 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14720 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14721 Chain, Dest, CC, Cmp);
14722 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14727 } else if (Cond.getOpcode() == ISD::SETCC &&
14728 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14729 // For FCMP_UNE, we can emit
14730 // two branches instead of an explicit AND instruction with a
14731 // separate test. However, we only do this if this block doesn't
14732 // have a fall-through edge, because this requires an explicit
14733 // jmp when the condition is false.
14734 if (Op.getNode()->hasOneUse()) {
14735 SDNode *User = *Op.getNode()->use_begin();
14736 // Look for an unconditional branch following this conditional branch.
14737 // We need this because we need to reverse the successors in order
14738 // to implement FCMP_UNE.
14739 if (User->getOpcode() == ISD::BR) {
14740 SDValue FalseBB = User->getOperand(1);
14742 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14743 assert(NewBR == User);
14746 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14747 Cond.getOperand(0), Cond.getOperand(1));
14748 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14749 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14750 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14751 Chain, Dest, CC, Cmp);
14752 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14762 // Look pass the truncate if the high bits are known zero.
14763 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14764 Cond = Cond.getOperand(0);
14766 // We know the result of AND is compared against zero. Try to match
14768 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14769 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14770 if (NewSetCC.getNode()) {
14771 CC = NewSetCC.getOperand(0);
14772 Cond = NewSetCC.getOperand(1);
14779 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14780 CC = DAG.getConstant(X86Cond, MVT::i8);
14781 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14783 Cond = ConvertCmpIfNecessary(Cond, DAG);
14784 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14785 Chain, Dest, CC, Cond);
14788 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14789 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14790 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14791 // that the guard pages used by the OS virtual memory manager are allocated in
14792 // correct sequence.
14794 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14795 SelectionDAG &DAG) const {
14796 MachineFunction &MF = DAG.getMachineFunction();
14797 bool SplitStack = MF.shouldSplitStack();
14798 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14803 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14804 SDNode* Node = Op.getNode();
14806 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14807 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14808 " not tell us which reg is the stack pointer!");
14809 EVT VT = Node->getValueType(0);
14810 SDValue Tmp1 = SDValue(Node, 0);
14811 SDValue Tmp2 = SDValue(Node, 1);
14812 SDValue Tmp3 = Node->getOperand(2);
14813 SDValue Chain = Tmp1.getOperand(0);
14815 // Chain the dynamic stack allocation so that it doesn't modify the stack
14816 // pointer when other instructions are using the stack.
14817 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14820 SDValue Size = Tmp2.getOperand(1);
14821 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14822 Chain = SP.getValue(1);
14823 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14824 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
14825 unsigned StackAlign = TFI.getStackAlignment();
14826 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14827 if (Align > StackAlign)
14828 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14829 DAG.getConstant(-(uint64_t)Align, VT));
14830 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14832 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14833 DAG.getIntPtrConstant(0, true), SDValue(),
14836 SDValue Ops[2] = { Tmp1, Tmp2 };
14837 return DAG.getMergeValues(Ops, dl);
14841 SDValue Chain = Op.getOperand(0);
14842 SDValue Size = Op.getOperand(1);
14843 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14844 EVT VT = Op.getNode()->getValueType(0);
14846 bool Is64Bit = Subtarget->is64Bit();
14847 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
14850 MachineRegisterInfo &MRI = MF.getRegInfo();
14853 // The 64 bit implementation of segmented stacks needs to clobber both r10
14854 // r11. This makes it impossible to use it along with nested parameters.
14855 const Function *F = MF.getFunction();
14857 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14859 if (I->hasNestAttr())
14860 report_fatal_error("Cannot use segmented stacks with functions that "
14861 "have nested arguments.");
14864 const TargetRegisterClass *AddrRegClass =
14865 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
14866 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14867 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14868 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14869 DAG.getRegister(Vreg, SPTy));
14870 SDValue Ops1[2] = { Value, Chain };
14871 return DAG.getMergeValues(Ops1, dl);
14874 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14876 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14877 Flag = Chain.getValue(1);
14878 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14880 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14882 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
14883 DAG.getSubtarget().getRegisterInfo());
14884 unsigned SPReg = RegInfo->getStackRegister();
14885 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14886 Chain = SP.getValue(1);
14889 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14890 DAG.getConstant(-(uint64_t)Align, VT));
14891 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14894 SDValue Ops1[2] = { SP, Chain };
14895 return DAG.getMergeValues(Ops1, dl);
14899 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14900 MachineFunction &MF = DAG.getMachineFunction();
14901 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14903 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14906 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14907 // vastart just stores the address of the VarArgsFrameIndex slot into the
14908 // memory location argument.
14909 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14911 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14912 MachinePointerInfo(SV), false, false, 0);
14916 // gp_offset (0 - 6 * 8)
14917 // fp_offset (48 - 48 + 8 * 16)
14918 // overflow_arg_area (point to parameters coming in memory).
14920 SmallVector<SDValue, 8> MemOps;
14921 SDValue FIN = Op.getOperand(1);
14923 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14924 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14926 FIN, MachinePointerInfo(SV), false, false, 0);
14927 MemOps.push_back(Store);
14930 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14931 FIN, DAG.getIntPtrConstant(4));
14932 Store = DAG.getStore(Op.getOperand(0), DL,
14933 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14935 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14936 MemOps.push_back(Store);
14938 // Store ptr to overflow_arg_area
14939 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14940 FIN, DAG.getIntPtrConstant(4));
14941 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14943 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14944 MachinePointerInfo(SV, 8),
14946 MemOps.push_back(Store);
14948 // Store ptr to reg_save_area.
14949 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14950 FIN, DAG.getIntPtrConstant(8));
14951 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14953 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14954 MachinePointerInfo(SV, 16), false, false, 0);
14955 MemOps.push_back(Store);
14956 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14959 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14960 assert(Subtarget->is64Bit() &&
14961 "LowerVAARG only handles 64-bit va_arg!");
14962 assert((Subtarget->isTargetLinux() ||
14963 Subtarget->isTargetDarwin()) &&
14964 "Unhandled target in LowerVAARG");
14965 assert(Op.getNode()->getNumOperands() == 4);
14966 SDValue Chain = Op.getOperand(0);
14967 SDValue SrcPtr = Op.getOperand(1);
14968 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14969 unsigned Align = Op.getConstantOperandVal(3);
14972 EVT ArgVT = Op.getNode()->getValueType(0);
14973 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14974 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14977 // Decide which area this value should be read from.
14978 // TODO: Implement the AMD64 ABI in its entirety. This simple
14979 // selection mechanism works only for the basic types.
14980 if (ArgVT == MVT::f80) {
14981 llvm_unreachable("va_arg for f80 not yet implemented");
14982 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14983 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14984 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14985 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14987 llvm_unreachable("Unhandled argument type in LowerVAARG");
14990 if (ArgMode == 2) {
14991 // Sanity Check: Make sure using fp_offset makes sense.
14992 assert(!DAG.getTarget().Options.UseSoftFloat &&
14993 !(DAG.getMachineFunction()
14994 .getFunction()->getAttributes()
14995 .hasAttribute(AttributeSet::FunctionIndex,
14996 Attribute::NoImplicitFloat)) &&
14997 Subtarget->hasSSE1());
15000 // Insert VAARG_64 node into the DAG
15001 // VAARG_64 returns two values: Variable Argument Address, Chain
15002 SmallVector<SDValue, 11> InstOps;
15003 InstOps.push_back(Chain);
15004 InstOps.push_back(SrcPtr);
15005 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15006 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15007 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15008 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15009 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15010 VTs, InstOps, MVT::i64,
15011 MachinePointerInfo(SV),
15013 /*Volatile=*/false,
15015 /*WriteMem=*/true);
15016 Chain = VAARG.getValue(1);
15018 // Load the next argument and return it
15019 return DAG.getLoad(ArgVT, dl,
15022 MachinePointerInfo(),
15023 false, false, false, 0);
15026 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15027 SelectionDAG &DAG) {
15028 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15029 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15030 SDValue Chain = Op.getOperand(0);
15031 SDValue DstPtr = Op.getOperand(1);
15032 SDValue SrcPtr = Op.getOperand(2);
15033 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15034 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15037 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15038 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15040 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15043 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15044 // amount is a constant. Takes immediate version of shift as input.
15045 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15046 SDValue SrcOp, uint64_t ShiftAmt,
15047 SelectionDAG &DAG) {
15048 MVT ElementType = VT.getVectorElementType();
15050 // Fold this packed shift into its first operand if ShiftAmt is 0.
15054 // Check for ShiftAmt >= element width
15055 if (ShiftAmt >= ElementType.getSizeInBits()) {
15056 if (Opc == X86ISD::VSRAI)
15057 ShiftAmt = ElementType.getSizeInBits() - 1;
15059 return DAG.getConstant(0, VT);
15062 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15063 && "Unknown target vector shift-by-constant node");
15065 // Fold this packed vector shift into a build vector if SrcOp is a
15066 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15067 if (VT == SrcOp.getSimpleValueType() &&
15068 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15069 SmallVector<SDValue, 8> Elts;
15070 unsigned NumElts = SrcOp->getNumOperands();
15071 ConstantSDNode *ND;
15074 default: llvm_unreachable(nullptr);
15075 case X86ISD::VSHLI:
15076 for (unsigned i=0; i!=NumElts; ++i) {
15077 SDValue CurrentOp = SrcOp->getOperand(i);
15078 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15079 Elts.push_back(CurrentOp);
15082 ND = cast<ConstantSDNode>(CurrentOp);
15083 const APInt &C = ND->getAPIntValue();
15084 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15087 case X86ISD::VSRLI:
15088 for (unsigned i=0; i!=NumElts; ++i) {
15089 SDValue CurrentOp = SrcOp->getOperand(i);
15090 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15091 Elts.push_back(CurrentOp);
15094 ND = cast<ConstantSDNode>(CurrentOp);
15095 const APInt &C = ND->getAPIntValue();
15096 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15099 case X86ISD::VSRAI:
15100 for (unsigned i=0; i!=NumElts; ++i) {
15101 SDValue CurrentOp = SrcOp->getOperand(i);
15102 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15103 Elts.push_back(CurrentOp);
15106 ND = cast<ConstantSDNode>(CurrentOp);
15107 const APInt &C = ND->getAPIntValue();
15108 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15113 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15116 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15119 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15120 // may or may not be a constant. Takes immediate version of shift as input.
15121 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15122 SDValue SrcOp, SDValue ShAmt,
15123 SelectionDAG &DAG) {
15124 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15126 // Catch shift-by-constant.
15127 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15128 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15129 CShAmt->getZExtValue(), DAG);
15131 // Change opcode to non-immediate version
15133 default: llvm_unreachable("Unknown target vector shift node");
15134 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15135 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15136 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15139 // Need to build a vector containing shift amount
15140 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15143 ShOps[1] = DAG.getConstant(0, MVT::i32);
15144 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15145 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15147 // The return type has to be a 128-bit type with the same element
15148 // type as the input type.
15149 MVT EltVT = VT.getVectorElementType();
15150 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15152 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15153 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15156 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15157 /// necessary casting for \p Mask when lowering masking intrinsics.
15158 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15159 SDValue PreservedSrc, SelectionDAG &DAG) {
15160 EVT VT = Op.getValueType();
15161 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15162 MVT::i1, VT.getVectorNumElements());
15165 assert(MaskVT.isSimple() && "invalid mask type");
15166 return DAG.getNode(ISD::VSELECT, dl, VT,
15167 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15171 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15173 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15174 case Intrinsic::x86_fma_vfmadd_ps:
15175 case Intrinsic::x86_fma_vfmadd_pd:
15176 case Intrinsic::x86_fma_vfmadd_ps_256:
15177 case Intrinsic::x86_fma_vfmadd_pd_256:
15178 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15179 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15180 return X86ISD::FMADD;
15181 case Intrinsic::x86_fma_vfmsub_ps:
15182 case Intrinsic::x86_fma_vfmsub_pd:
15183 case Intrinsic::x86_fma_vfmsub_ps_256:
15184 case Intrinsic::x86_fma_vfmsub_pd_256:
15185 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15186 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15187 return X86ISD::FMSUB;
15188 case Intrinsic::x86_fma_vfnmadd_ps:
15189 case Intrinsic::x86_fma_vfnmadd_pd:
15190 case Intrinsic::x86_fma_vfnmadd_ps_256:
15191 case Intrinsic::x86_fma_vfnmadd_pd_256:
15192 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15193 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15194 return X86ISD::FNMADD;
15195 case Intrinsic::x86_fma_vfnmsub_ps:
15196 case Intrinsic::x86_fma_vfnmsub_pd:
15197 case Intrinsic::x86_fma_vfnmsub_ps_256:
15198 case Intrinsic::x86_fma_vfnmsub_pd_256:
15199 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15200 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15201 return X86ISD::FNMSUB;
15202 case Intrinsic::x86_fma_vfmaddsub_ps:
15203 case Intrinsic::x86_fma_vfmaddsub_pd:
15204 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15205 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15206 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15207 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15208 return X86ISD::FMADDSUB;
15209 case Intrinsic::x86_fma_vfmsubadd_ps:
15210 case Intrinsic::x86_fma_vfmsubadd_pd:
15211 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15212 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15213 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15214 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15215 return X86ISD::FMSUBADD;
15219 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15221 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15223 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15225 switch(IntrData->Type) {
15226 case INTR_TYPE_1OP:
15227 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15228 case INTR_TYPE_2OP:
15229 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15231 case INTR_TYPE_3OP:
15232 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15233 Op.getOperand(2), Op.getOperand(3));
15234 case COMI: { // Comparison intrinsics
15235 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15236 SDValue LHS = Op.getOperand(1);
15237 SDValue RHS = Op.getOperand(2);
15238 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15239 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15240 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15241 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15242 DAG.getConstant(X86CC, MVT::i8), Cond);
15243 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15246 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15247 Op.getOperand(1), Op.getOperand(2), DAG);
15254 default: return SDValue(); // Don't custom lower most intrinsics.
15256 // Arithmetic intrinsics.
15257 case Intrinsic::x86_sse2_pmulu_dq:
15258 case Intrinsic::x86_avx2_pmulu_dq:
15259 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15260 Op.getOperand(1), Op.getOperand(2));
15262 case Intrinsic::x86_sse41_pmuldq:
15263 case Intrinsic::x86_avx2_pmul_dq:
15264 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15265 Op.getOperand(1), Op.getOperand(2));
15267 case Intrinsic::x86_sse2_pmulhu_w:
15268 case Intrinsic::x86_avx2_pmulhu_w:
15269 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15270 Op.getOperand(1), Op.getOperand(2));
15272 case Intrinsic::x86_sse2_pmulh_w:
15273 case Intrinsic::x86_avx2_pmulh_w:
15274 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15275 Op.getOperand(1), Op.getOperand(2));
15277 // SSE/SSE2/AVX floating point max/min intrinsics.
15278 case Intrinsic::x86_sse_max_ps:
15279 case Intrinsic::x86_sse2_max_pd:
15280 case Intrinsic::x86_avx_max_ps_256:
15281 case Intrinsic::x86_avx_max_pd_256:
15282 case Intrinsic::x86_sse_min_ps:
15283 case Intrinsic::x86_sse2_min_pd:
15284 case Intrinsic::x86_avx_min_ps_256:
15285 case Intrinsic::x86_avx_min_pd_256: {
15288 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15289 case Intrinsic::x86_sse_max_ps:
15290 case Intrinsic::x86_sse2_max_pd:
15291 case Intrinsic::x86_avx_max_ps_256:
15292 case Intrinsic::x86_avx_max_pd_256:
15293 Opcode = X86ISD::FMAX;
15295 case Intrinsic::x86_sse_min_ps:
15296 case Intrinsic::x86_sse2_min_pd:
15297 case Intrinsic::x86_avx_min_ps_256:
15298 case Intrinsic::x86_avx_min_pd_256:
15299 Opcode = X86ISD::FMIN;
15302 return DAG.getNode(Opcode, dl, Op.getValueType(),
15303 Op.getOperand(1), Op.getOperand(2));
15306 // AVX2 variable shift intrinsics
15307 case Intrinsic::x86_avx2_psllv_d:
15308 case Intrinsic::x86_avx2_psllv_q:
15309 case Intrinsic::x86_avx2_psllv_d_256:
15310 case Intrinsic::x86_avx2_psllv_q_256:
15311 case Intrinsic::x86_avx2_psrlv_d:
15312 case Intrinsic::x86_avx2_psrlv_q:
15313 case Intrinsic::x86_avx2_psrlv_d_256:
15314 case Intrinsic::x86_avx2_psrlv_q_256:
15315 case Intrinsic::x86_avx2_psrav_d:
15316 case Intrinsic::x86_avx2_psrav_d_256: {
15319 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15320 case Intrinsic::x86_avx2_psllv_d:
15321 case Intrinsic::x86_avx2_psllv_q:
15322 case Intrinsic::x86_avx2_psllv_d_256:
15323 case Intrinsic::x86_avx2_psllv_q_256:
15326 case Intrinsic::x86_avx2_psrlv_d:
15327 case Intrinsic::x86_avx2_psrlv_q:
15328 case Intrinsic::x86_avx2_psrlv_d_256:
15329 case Intrinsic::x86_avx2_psrlv_q_256:
15332 case Intrinsic::x86_avx2_psrav_d:
15333 case Intrinsic::x86_avx2_psrav_d_256:
15337 return DAG.getNode(Opcode, dl, Op.getValueType(),
15338 Op.getOperand(1), Op.getOperand(2));
15341 case Intrinsic::x86_sse2_packssdw_128:
15342 case Intrinsic::x86_sse2_packsswb_128:
15343 case Intrinsic::x86_avx2_packssdw:
15344 case Intrinsic::x86_avx2_packsswb:
15345 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15346 Op.getOperand(1), Op.getOperand(2));
15348 case Intrinsic::x86_sse2_packuswb_128:
15349 case Intrinsic::x86_sse41_packusdw:
15350 case Intrinsic::x86_avx2_packuswb:
15351 case Intrinsic::x86_avx2_packusdw:
15352 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15353 Op.getOperand(1), Op.getOperand(2));
15355 case Intrinsic::x86_ssse3_pshuf_b_128:
15356 case Intrinsic::x86_avx2_pshuf_b:
15357 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15358 Op.getOperand(1), Op.getOperand(2));
15360 case Intrinsic::x86_sse2_pshuf_d:
15361 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15362 Op.getOperand(1), Op.getOperand(2));
15364 case Intrinsic::x86_sse2_pshufl_w:
15365 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15366 Op.getOperand(1), Op.getOperand(2));
15368 case Intrinsic::x86_sse2_pshufh_w:
15369 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15370 Op.getOperand(1), Op.getOperand(2));
15372 case Intrinsic::x86_ssse3_psign_b_128:
15373 case Intrinsic::x86_ssse3_psign_w_128:
15374 case Intrinsic::x86_ssse3_psign_d_128:
15375 case Intrinsic::x86_avx2_psign_b:
15376 case Intrinsic::x86_avx2_psign_w:
15377 case Intrinsic::x86_avx2_psign_d:
15378 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15379 Op.getOperand(1), Op.getOperand(2));
15381 case Intrinsic::x86_avx2_permd:
15382 case Intrinsic::x86_avx2_permps:
15383 // Operands intentionally swapped. Mask is last operand to intrinsic,
15384 // but second operand for node/instruction.
15385 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15386 Op.getOperand(2), Op.getOperand(1));
15388 case Intrinsic::x86_avx512_mask_valign_q_512:
15389 case Intrinsic::x86_avx512_mask_valign_d_512:
15390 // Vector source operands are swapped.
15391 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15392 Op.getValueType(), Op.getOperand(2),
15395 Op.getOperand(5), Op.getOperand(4), DAG);
15397 // ptest and testp intrinsics. The intrinsic these come from are designed to
15398 // return an integer value, not just an instruction so lower it to the ptest
15399 // or testp pattern and a setcc for the result.
15400 case Intrinsic::x86_sse41_ptestz:
15401 case Intrinsic::x86_sse41_ptestc:
15402 case Intrinsic::x86_sse41_ptestnzc:
15403 case Intrinsic::x86_avx_ptestz_256:
15404 case Intrinsic::x86_avx_ptestc_256:
15405 case Intrinsic::x86_avx_ptestnzc_256:
15406 case Intrinsic::x86_avx_vtestz_ps:
15407 case Intrinsic::x86_avx_vtestc_ps:
15408 case Intrinsic::x86_avx_vtestnzc_ps:
15409 case Intrinsic::x86_avx_vtestz_pd:
15410 case Intrinsic::x86_avx_vtestc_pd:
15411 case Intrinsic::x86_avx_vtestnzc_pd:
15412 case Intrinsic::x86_avx_vtestz_ps_256:
15413 case Intrinsic::x86_avx_vtestc_ps_256:
15414 case Intrinsic::x86_avx_vtestnzc_ps_256:
15415 case Intrinsic::x86_avx_vtestz_pd_256:
15416 case Intrinsic::x86_avx_vtestc_pd_256:
15417 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15418 bool IsTestPacked = false;
15421 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15422 case Intrinsic::x86_avx_vtestz_ps:
15423 case Intrinsic::x86_avx_vtestz_pd:
15424 case Intrinsic::x86_avx_vtestz_ps_256:
15425 case Intrinsic::x86_avx_vtestz_pd_256:
15426 IsTestPacked = true; // Fallthrough
15427 case Intrinsic::x86_sse41_ptestz:
15428 case Intrinsic::x86_avx_ptestz_256:
15430 X86CC = X86::COND_E;
15432 case Intrinsic::x86_avx_vtestc_ps:
15433 case Intrinsic::x86_avx_vtestc_pd:
15434 case Intrinsic::x86_avx_vtestc_ps_256:
15435 case Intrinsic::x86_avx_vtestc_pd_256:
15436 IsTestPacked = true; // Fallthrough
15437 case Intrinsic::x86_sse41_ptestc:
15438 case Intrinsic::x86_avx_ptestc_256:
15440 X86CC = X86::COND_B;
15442 case Intrinsic::x86_avx_vtestnzc_ps:
15443 case Intrinsic::x86_avx_vtestnzc_pd:
15444 case Intrinsic::x86_avx_vtestnzc_ps_256:
15445 case Intrinsic::x86_avx_vtestnzc_pd_256:
15446 IsTestPacked = true; // Fallthrough
15447 case Intrinsic::x86_sse41_ptestnzc:
15448 case Intrinsic::x86_avx_ptestnzc_256:
15450 X86CC = X86::COND_A;
15454 SDValue LHS = Op.getOperand(1);
15455 SDValue RHS = Op.getOperand(2);
15456 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15457 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15458 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15459 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15460 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15462 case Intrinsic::x86_avx512_kortestz_w:
15463 case Intrinsic::x86_avx512_kortestc_w: {
15464 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15465 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15466 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15467 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15468 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15469 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15470 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15473 case Intrinsic::x86_sse42_pcmpistria128:
15474 case Intrinsic::x86_sse42_pcmpestria128:
15475 case Intrinsic::x86_sse42_pcmpistric128:
15476 case Intrinsic::x86_sse42_pcmpestric128:
15477 case Intrinsic::x86_sse42_pcmpistrio128:
15478 case Intrinsic::x86_sse42_pcmpestrio128:
15479 case Intrinsic::x86_sse42_pcmpistris128:
15480 case Intrinsic::x86_sse42_pcmpestris128:
15481 case Intrinsic::x86_sse42_pcmpistriz128:
15482 case Intrinsic::x86_sse42_pcmpestriz128: {
15486 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15487 case Intrinsic::x86_sse42_pcmpistria128:
15488 Opcode = X86ISD::PCMPISTRI;
15489 X86CC = X86::COND_A;
15491 case Intrinsic::x86_sse42_pcmpestria128:
15492 Opcode = X86ISD::PCMPESTRI;
15493 X86CC = X86::COND_A;
15495 case Intrinsic::x86_sse42_pcmpistric128:
15496 Opcode = X86ISD::PCMPISTRI;
15497 X86CC = X86::COND_B;
15499 case Intrinsic::x86_sse42_pcmpestric128:
15500 Opcode = X86ISD::PCMPESTRI;
15501 X86CC = X86::COND_B;
15503 case Intrinsic::x86_sse42_pcmpistrio128:
15504 Opcode = X86ISD::PCMPISTRI;
15505 X86CC = X86::COND_O;
15507 case Intrinsic::x86_sse42_pcmpestrio128:
15508 Opcode = X86ISD::PCMPESTRI;
15509 X86CC = X86::COND_O;
15511 case Intrinsic::x86_sse42_pcmpistris128:
15512 Opcode = X86ISD::PCMPISTRI;
15513 X86CC = X86::COND_S;
15515 case Intrinsic::x86_sse42_pcmpestris128:
15516 Opcode = X86ISD::PCMPESTRI;
15517 X86CC = X86::COND_S;
15519 case Intrinsic::x86_sse42_pcmpistriz128:
15520 Opcode = X86ISD::PCMPISTRI;
15521 X86CC = X86::COND_E;
15523 case Intrinsic::x86_sse42_pcmpestriz128:
15524 Opcode = X86ISD::PCMPESTRI;
15525 X86CC = X86::COND_E;
15528 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15529 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15530 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15531 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15532 DAG.getConstant(X86CC, MVT::i8),
15533 SDValue(PCMP.getNode(), 1));
15534 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15537 case Intrinsic::x86_sse42_pcmpistri128:
15538 case Intrinsic::x86_sse42_pcmpestri128: {
15540 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15541 Opcode = X86ISD::PCMPISTRI;
15543 Opcode = X86ISD::PCMPESTRI;
15545 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15546 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15547 return DAG.getNode(Opcode, dl, VTs, NewOps);
15550 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15551 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15552 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15553 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15554 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15555 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15556 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15557 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15558 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15559 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15560 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15561 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15562 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15563 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15564 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15565 dl, Op.getValueType(),
15569 Op.getOperand(4), Op.getOperand(1), DAG);
15574 case Intrinsic::x86_fma_vfmadd_ps:
15575 case Intrinsic::x86_fma_vfmadd_pd:
15576 case Intrinsic::x86_fma_vfmsub_ps:
15577 case Intrinsic::x86_fma_vfmsub_pd:
15578 case Intrinsic::x86_fma_vfnmadd_ps:
15579 case Intrinsic::x86_fma_vfnmadd_pd:
15580 case Intrinsic::x86_fma_vfnmsub_ps:
15581 case Intrinsic::x86_fma_vfnmsub_pd:
15582 case Intrinsic::x86_fma_vfmaddsub_ps:
15583 case Intrinsic::x86_fma_vfmaddsub_pd:
15584 case Intrinsic::x86_fma_vfmsubadd_ps:
15585 case Intrinsic::x86_fma_vfmsubadd_pd:
15586 case Intrinsic::x86_fma_vfmadd_ps_256:
15587 case Intrinsic::x86_fma_vfmadd_pd_256:
15588 case Intrinsic::x86_fma_vfmsub_ps_256:
15589 case Intrinsic::x86_fma_vfmsub_pd_256:
15590 case Intrinsic::x86_fma_vfnmadd_ps_256:
15591 case Intrinsic::x86_fma_vfnmadd_pd_256:
15592 case Intrinsic::x86_fma_vfnmsub_ps_256:
15593 case Intrinsic::x86_fma_vfnmsub_pd_256:
15594 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15595 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15596 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15597 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15598 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15599 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15603 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15604 SDValue Src, SDValue Mask, SDValue Base,
15605 SDValue Index, SDValue ScaleOp, SDValue Chain,
15606 const X86Subtarget * Subtarget) {
15608 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15609 assert(C && "Invalid scale type");
15610 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15611 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15612 Index.getSimpleValueType().getVectorNumElements());
15614 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15616 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15618 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15619 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15620 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15621 SDValue Segment = DAG.getRegister(0, MVT::i32);
15622 if (Src.getOpcode() == ISD::UNDEF)
15623 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15624 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15625 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15626 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15627 return DAG.getMergeValues(RetOps, dl);
15630 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15631 SDValue Src, SDValue Mask, SDValue Base,
15632 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15634 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15635 assert(C && "Invalid scale type");
15636 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15637 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15638 SDValue Segment = DAG.getRegister(0, MVT::i32);
15639 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15640 Index.getSimpleValueType().getVectorNumElements());
15642 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15644 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15646 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15647 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15648 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15649 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15650 return SDValue(Res, 1);
15653 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15654 SDValue Mask, SDValue Base, SDValue Index,
15655 SDValue ScaleOp, SDValue Chain) {
15657 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15658 assert(C && "Invalid scale type");
15659 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15660 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15661 SDValue Segment = DAG.getRegister(0, MVT::i32);
15663 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15665 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15667 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15669 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15670 //SDVTList VTs = DAG.getVTList(MVT::Other);
15671 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15672 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15673 return SDValue(Res, 0);
15676 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15677 // read performance monitor counters (x86_rdpmc).
15678 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15679 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15680 SmallVectorImpl<SDValue> &Results) {
15681 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15682 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15685 // The ECX register is used to select the index of the performance counter
15687 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15689 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15691 // Reads the content of a 64-bit performance counter and returns it in the
15692 // registers EDX:EAX.
15693 if (Subtarget->is64Bit()) {
15694 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15695 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15698 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15699 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15702 Chain = HI.getValue(1);
15704 if (Subtarget->is64Bit()) {
15705 // The EAX register is loaded with the low-order 32 bits. The EDX register
15706 // is loaded with the supported high-order bits of the counter.
15707 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15708 DAG.getConstant(32, MVT::i8));
15709 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15710 Results.push_back(Chain);
15714 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15715 SDValue Ops[] = { LO, HI };
15716 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15717 Results.push_back(Pair);
15718 Results.push_back(Chain);
15721 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15722 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15723 // also used to custom lower READCYCLECOUNTER nodes.
15724 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15725 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15726 SmallVectorImpl<SDValue> &Results) {
15727 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15728 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15731 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15732 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15733 // and the EAX register is loaded with the low-order 32 bits.
15734 if (Subtarget->is64Bit()) {
15735 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15736 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15739 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15740 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15743 SDValue Chain = HI.getValue(1);
15745 if (Opcode == X86ISD::RDTSCP_DAG) {
15746 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15748 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15749 // the ECX register. Add 'ecx' explicitly to the chain.
15750 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15752 // Explicitly store the content of ECX at the location passed in input
15753 // to the 'rdtscp' intrinsic.
15754 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15755 MachinePointerInfo(), false, false, 0);
15758 if (Subtarget->is64Bit()) {
15759 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15760 // the EAX register is loaded with the low-order 32 bits.
15761 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15762 DAG.getConstant(32, MVT::i8));
15763 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15764 Results.push_back(Chain);
15768 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15769 SDValue Ops[] = { LO, HI };
15770 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15771 Results.push_back(Pair);
15772 Results.push_back(Chain);
15775 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15776 SelectionDAG &DAG) {
15777 SmallVector<SDValue, 2> Results;
15779 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15781 return DAG.getMergeValues(Results, DL);
15785 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15786 SelectionDAG &DAG) {
15787 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15789 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15794 switch(IntrData->Type) {
15796 llvm_unreachable("Unknown Intrinsic Type");
15800 // Emit the node with the right value type.
15801 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15802 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15804 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15805 // Otherwise return the value from Rand, which is always 0, casted to i32.
15806 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15807 DAG.getConstant(1, Op->getValueType(1)),
15808 DAG.getConstant(X86::COND_B, MVT::i32),
15809 SDValue(Result.getNode(), 1) };
15810 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15811 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15814 // Return { result, isValid, chain }.
15815 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15816 SDValue(Result.getNode(), 2));
15819 //gather(v1, mask, index, base, scale);
15820 SDValue Chain = Op.getOperand(0);
15821 SDValue Src = Op.getOperand(2);
15822 SDValue Base = Op.getOperand(3);
15823 SDValue Index = Op.getOperand(4);
15824 SDValue Mask = Op.getOperand(5);
15825 SDValue Scale = Op.getOperand(6);
15826 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15830 //scatter(base, mask, index, v1, scale);
15831 SDValue Chain = Op.getOperand(0);
15832 SDValue Base = Op.getOperand(2);
15833 SDValue Mask = Op.getOperand(3);
15834 SDValue Index = Op.getOperand(4);
15835 SDValue Src = Op.getOperand(5);
15836 SDValue Scale = Op.getOperand(6);
15837 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15840 SDValue Hint = Op.getOperand(6);
15842 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15843 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15844 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15845 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15846 SDValue Chain = Op.getOperand(0);
15847 SDValue Mask = Op.getOperand(2);
15848 SDValue Index = Op.getOperand(3);
15849 SDValue Base = Op.getOperand(4);
15850 SDValue Scale = Op.getOperand(5);
15851 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15853 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15855 SmallVector<SDValue, 2> Results;
15856 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15857 return DAG.getMergeValues(Results, dl);
15859 // Read Performance Monitoring Counters.
15861 SmallVector<SDValue, 2> Results;
15862 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15863 return DAG.getMergeValues(Results, dl);
15865 // XTEST intrinsics.
15867 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15868 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15869 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15870 DAG.getConstant(X86::COND_NE, MVT::i8),
15872 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15873 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15874 Ret, SDValue(InTrans.getNode(), 1));
15878 SmallVector<SDValue, 2> Results;
15879 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15880 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15881 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15882 DAG.getConstant(-1, MVT::i8));
15883 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15884 Op.getOperand(4), GenCF.getValue(1));
15885 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15886 Op.getOperand(5), MachinePointerInfo(),
15888 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15889 DAG.getConstant(X86::COND_B, MVT::i8),
15891 Results.push_back(SetCC);
15892 Results.push_back(Store);
15893 return DAG.getMergeValues(Results, dl);
15898 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15899 SelectionDAG &DAG) const {
15900 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15901 MFI->setReturnAddressIsTaken(true);
15903 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15906 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15908 EVT PtrVT = getPointerTy();
15911 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15912 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15913 DAG.getSubtarget().getRegisterInfo());
15914 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15915 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15916 DAG.getNode(ISD::ADD, dl, PtrVT,
15917 FrameAddr, Offset),
15918 MachinePointerInfo(), false, false, false, 0);
15921 // Just load the return address.
15922 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15923 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15924 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15927 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15928 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15929 MFI->setFrameAddressIsTaken(true);
15931 EVT VT = Op.getValueType();
15932 SDLoc dl(Op); // FIXME probably not meaningful
15933 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15934 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15935 DAG.getSubtarget().getRegisterInfo());
15936 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15937 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15938 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15939 "Invalid Frame Register!");
15940 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15942 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15943 MachinePointerInfo(),
15944 false, false, false, 0);
15948 // FIXME? Maybe this could be a TableGen attribute on some registers and
15949 // this table could be generated automatically from RegInfo.
15950 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15952 unsigned Reg = StringSwitch<unsigned>(RegName)
15953 .Case("esp", X86::ESP)
15954 .Case("rsp", X86::RSP)
15958 report_fatal_error("Invalid register name global variable");
15961 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15962 SelectionDAG &DAG) const {
15963 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15964 DAG.getSubtarget().getRegisterInfo());
15965 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15968 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15969 SDValue Chain = Op.getOperand(0);
15970 SDValue Offset = Op.getOperand(1);
15971 SDValue Handler = Op.getOperand(2);
15974 EVT PtrVT = getPointerTy();
15975 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15976 DAG.getSubtarget().getRegisterInfo());
15977 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15978 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15979 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15980 "Invalid Frame Register!");
15981 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15982 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15984 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15985 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15986 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15987 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15989 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15991 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15992 DAG.getRegister(StoreAddrReg, PtrVT));
15995 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15996 SelectionDAG &DAG) const {
15998 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15999 DAG.getVTList(MVT::i32, MVT::Other),
16000 Op.getOperand(0), Op.getOperand(1));
16003 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16004 SelectionDAG &DAG) const {
16006 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16007 Op.getOperand(0), Op.getOperand(1));
16010 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16011 return Op.getOperand(0);
16014 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16015 SelectionDAG &DAG) const {
16016 SDValue Root = Op.getOperand(0);
16017 SDValue Trmp = Op.getOperand(1); // trampoline
16018 SDValue FPtr = Op.getOperand(2); // nested function
16019 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16022 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16023 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16025 if (Subtarget->is64Bit()) {
16026 SDValue OutChains[6];
16028 // Large code-model.
16029 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16030 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16032 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16033 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16035 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16037 // Load the pointer to the nested function into R11.
16038 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16039 SDValue Addr = Trmp;
16040 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16041 Addr, MachinePointerInfo(TrmpAddr),
16044 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16045 DAG.getConstant(2, MVT::i64));
16046 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16047 MachinePointerInfo(TrmpAddr, 2),
16050 // Load the 'nest' parameter value into R10.
16051 // R10 is specified in X86CallingConv.td
16052 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16053 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16054 DAG.getConstant(10, MVT::i64));
16055 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16056 Addr, MachinePointerInfo(TrmpAddr, 10),
16059 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16060 DAG.getConstant(12, MVT::i64));
16061 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16062 MachinePointerInfo(TrmpAddr, 12),
16065 // Jump to the nested function.
16066 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16067 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16068 DAG.getConstant(20, MVT::i64));
16069 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16070 Addr, MachinePointerInfo(TrmpAddr, 20),
16073 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16074 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16075 DAG.getConstant(22, MVT::i64));
16076 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16077 MachinePointerInfo(TrmpAddr, 22),
16080 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16082 const Function *Func =
16083 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16084 CallingConv::ID CC = Func->getCallingConv();
16089 llvm_unreachable("Unsupported calling convention");
16090 case CallingConv::C:
16091 case CallingConv::X86_StdCall: {
16092 // Pass 'nest' parameter in ECX.
16093 // Must be kept in sync with X86CallingConv.td
16094 NestReg = X86::ECX;
16096 // Check that ECX wasn't needed by an 'inreg' parameter.
16097 FunctionType *FTy = Func->getFunctionType();
16098 const AttributeSet &Attrs = Func->getAttributes();
16100 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16101 unsigned InRegCount = 0;
16104 for (FunctionType::param_iterator I = FTy->param_begin(),
16105 E = FTy->param_end(); I != E; ++I, ++Idx)
16106 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16107 // FIXME: should only count parameters that are lowered to integers.
16108 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16110 if (InRegCount > 2) {
16111 report_fatal_error("Nest register in use - reduce number of inreg"
16117 case CallingConv::X86_FastCall:
16118 case CallingConv::X86_ThisCall:
16119 case CallingConv::Fast:
16120 // Pass 'nest' parameter in EAX.
16121 // Must be kept in sync with X86CallingConv.td
16122 NestReg = X86::EAX;
16126 SDValue OutChains[4];
16127 SDValue Addr, Disp;
16129 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16130 DAG.getConstant(10, MVT::i32));
16131 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16133 // This is storing the opcode for MOV32ri.
16134 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16135 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16136 OutChains[0] = DAG.getStore(Root, dl,
16137 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16138 Trmp, MachinePointerInfo(TrmpAddr),
16141 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16142 DAG.getConstant(1, MVT::i32));
16143 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16144 MachinePointerInfo(TrmpAddr, 1),
16147 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16148 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16149 DAG.getConstant(5, MVT::i32));
16150 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16151 MachinePointerInfo(TrmpAddr, 5),
16154 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16155 DAG.getConstant(6, MVT::i32));
16156 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16157 MachinePointerInfo(TrmpAddr, 6),
16160 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16164 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16165 SelectionDAG &DAG) const {
16167 The rounding mode is in bits 11:10 of FPSR, and has the following
16169 00 Round to nearest
16174 FLT_ROUNDS, on the other hand, expects the following:
16181 To perform the conversion, we do:
16182 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16185 MachineFunction &MF = DAG.getMachineFunction();
16186 const TargetMachine &TM = MF.getTarget();
16187 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16188 unsigned StackAlignment = TFI.getStackAlignment();
16189 MVT VT = Op.getSimpleValueType();
16192 // Save FP Control Word to stack slot
16193 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16194 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16196 MachineMemOperand *MMO =
16197 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16198 MachineMemOperand::MOStore, 2, 2);
16200 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16201 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16202 DAG.getVTList(MVT::Other),
16203 Ops, MVT::i16, MMO);
16205 // Load FP Control Word from stack slot
16206 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16207 MachinePointerInfo(), false, false, false, 0);
16209 // Transform as necessary
16211 DAG.getNode(ISD::SRL, DL, MVT::i16,
16212 DAG.getNode(ISD::AND, DL, MVT::i16,
16213 CWD, DAG.getConstant(0x800, MVT::i16)),
16214 DAG.getConstant(11, MVT::i8));
16216 DAG.getNode(ISD::SRL, DL, MVT::i16,
16217 DAG.getNode(ISD::AND, DL, MVT::i16,
16218 CWD, DAG.getConstant(0x400, MVT::i16)),
16219 DAG.getConstant(9, MVT::i8));
16222 DAG.getNode(ISD::AND, DL, MVT::i16,
16223 DAG.getNode(ISD::ADD, DL, MVT::i16,
16224 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16225 DAG.getConstant(1, MVT::i16)),
16226 DAG.getConstant(3, MVT::i16));
16228 return DAG.getNode((VT.getSizeInBits() < 16 ?
16229 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16232 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16233 MVT VT = Op.getSimpleValueType();
16235 unsigned NumBits = VT.getSizeInBits();
16238 Op = Op.getOperand(0);
16239 if (VT == MVT::i8) {
16240 // Zero extend to i32 since there is not an i8 bsr.
16242 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16245 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16246 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16247 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16249 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16252 DAG.getConstant(NumBits+NumBits-1, OpVT),
16253 DAG.getConstant(X86::COND_E, MVT::i8),
16256 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16258 // Finally xor with NumBits-1.
16259 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16262 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16266 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16267 MVT VT = Op.getSimpleValueType();
16269 unsigned NumBits = VT.getSizeInBits();
16272 Op = Op.getOperand(0);
16273 if (VT == MVT::i8) {
16274 // Zero extend to i32 since there is not an i8 bsr.
16276 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16279 // Issue a bsr (scan bits in reverse).
16280 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16281 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16283 // And xor with NumBits-1.
16284 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16287 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16291 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16292 MVT VT = Op.getSimpleValueType();
16293 unsigned NumBits = VT.getSizeInBits();
16295 Op = Op.getOperand(0);
16297 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16298 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16299 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16301 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16304 DAG.getConstant(NumBits, VT),
16305 DAG.getConstant(X86::COND_E, MVT::i8),
16308 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16311 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16312 // ones, and then concatenate the result back.
16313 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16314 MVT VT = Op.getSimpleValueType();
16316 assert(VT.is256BitVector() && VT.isInteger() &&
16317 "Unsupported value type for operation");
16319 unsigned NumElems = VT.getVectorNumElements();
16322 // Extract the LHS vectors
16323 SDValue LHS = Op.getOperand(0);
16324 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16325 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16327 // Extract the RHS vectors
16328 SDValue RHS = Op.getOperand(1);
16329 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16330 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16332 MVT EltVT = VT.getVectorElementType();
16333 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16335 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16336 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16337 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16340 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16341 assert(Op.getSimpleValueType().is256BitVector() &&
16342 Op.getSimpleValueType().isInteger() &&
16343 "Only handle AVX 256-bit vector integer operation");
16344 return Lower256IntArith(Op, DAG);
16347 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16348 assert(Op.getSimpleValueType().is256BitVector() &&
16349 Op.getSimpleValueType().isInteger() &&
16350 "Only handle AVX 256-bit vector integer operation");
16351 return Lower256IntArith(Op, DAG);
16354 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16355 SelectionDAG &DAG) {
16357 MVT VT = Op.getSimpleValueType();
16359 // Decompose 256-bit ops into smaller 128-bit ops.
16360 if (VT.is256BitVector() && !Subtarget->hasInt256())
16361 return Lower256IntArith(Op, DAG);
16363 SDValue A = Op.getOperand(0);
16364 SDValue B = Op.getOperand(1);
16366 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16367 if (VT == MVT::v4i32) {
16368 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16369 "Should not custom lower when pmuldq is available!");
16371 // Extract the odd parts.
16372 static const int UnpackMask[] = { 1, -1, 3, -1 };
16373 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16374 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16376 // Multiply the even parts.
16377 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16378 // Now multiply odd parts.
16379 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16381 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16382 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16384 // Merge the two vectors back together with a shuffle. This expands into 2
16386 static const int ShufMask[] = { 0, 4, 2, 6 };
16387 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16390 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16391 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16393 // Ahi = psrlqi(a, 32);
16394 // Bhi = psrlqi(b, 32);
16396 // AloBlo = pmuludq(a, b);
16397 // AloBhi = pmuludq(a, Bhi);
16398 // AhiBlo = pmuludq(Ahi, b);
16400 // AloBhi = psllqi(AloBhi, 32);
16401 // AhiBlo = psllqi(AhiBlo, 32);
16402 // return AloBlo + AloBhi + AhiBlo;
16404 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16405 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16407 // Bit cast to 32-bit vectors for MULUDQ
16408 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16409 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16410 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16411 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16412 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16413 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16415 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16416 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16417 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16419 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16420 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16422 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16423 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16426 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16427 assert(Subtarget->isTargetWin64() && "Unexpected target");
16428 EVT VT = Op.getValueType();
16429 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16430 "Unexpected return type for lowering");
16434 switch (Op->getOpcode()) {
16435 default: llvm_unreachable("Unexpected request for libcall!");
16436 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16437 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16438 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16439 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16440 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16441 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16445 SDValue InChain = DAG.getEntryNode();
16447 TargetLowering::ArgListTy Args;
16448 TargetLowering::ArgListEntry Entry;
16449 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16450 EVT ArgVT = Op->getOperand(i).getValueType();
16451 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16452 "Unexpected argument type for lowering");
16453 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16454 Entry.Node = StackPtr;
16455 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16457 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16458 Entry.Ty = PointerType::get(ArgTy,0);
16459 Entry.isSExt = false;
16460 Entry.isZExt = false;
16461 Args.push_back(Entry);
16464 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16467 TargetLowering::CallLoweringInfo CLI(DAG);
16468 CLI.setDebugLoc(dl).setChain(InChain)
16469 .setCallee(getLibcallCallingConv(LC),
16470 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16471 Callee, std::move(Args), 0)
16472 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16474 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16475 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16478 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16479 SelectionDAG &DAG) {
16480 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16481 EVT VT = Op0.getValueType();
16484 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16485 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16487 // PMULxD operations multiply each even value (starting at 0) of LHS with
16488 // the related value of RHS and produce a widen result.
16489 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16490 // => <2 x i64> <ae|cg>
16492 // In other word, to have all the results, we need to perform two PMULxD:
16493 // 1. one with the even values.
16494 // 2. one with the odd values.
16495 // To achieve #2, with need to place the odd values at an even position.
16497 // Place the odd value at an even position (basically, shift all values 1
16498 // step to the left):
16499 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16500 // <a|b|c|d> => <b|undef|d|undef>
16501 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16502 // <e|f|g|h> => <f|undef|h|undef>
16503 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16505 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16507 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16508 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16510 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16511 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16512 // => <2 x i64> <ae|cg>
16513 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16514 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16515 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16516 // => <2 x i64> <bf|dh>
16517 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16518 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16520 // Shuffle it back into the right order.
16521 SDValue Highs, Lows;
16522 if (VT == MVT::v8i32) {
16523 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16524 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16525 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16526 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16528 const int HighMask[] = {1, 5, 3, 7};
16529 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16530 const int LowMask[] = {0, 4, 2, 6};
16531 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16534 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16535 // unsigned multiply.
16536 if (IsSigned && !Subtarget->hasSSE41()) {
16538 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16539 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16540 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16541 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16542 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16544 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16545 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16548 // The first result of MUL_LOHI is actually the low value, followed by the
16550 SDValue Ops[] = {Lows, Highs};
16551 return DAG.getMergeValues(Ops, dl);
16554 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16555 const X86Subtarget *Subtarget) {
16556 MVT VT = Op.getSimpleValueType();
16558 SDValue R = Op.getOperand(0);
16559 SDValue Amt = Op.getOperand(1);
16561 // Optimize shl/srl/sra with constant shift amount.
16562 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16563 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16564 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16566 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16567 (Subtarget->hasInt256() &&
16568 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16569 (Subtarget->hasAVX512() &&
16570 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16571 if (Op.getOpcode() == ISD::SHL)
16572 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16574 if (Op.getOpcode() == ISD::SRL)
16575 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16577 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16578 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16582 if (VT == MVT::v16i8) {
16583 if (Op.getOpcode() == ISD::SHL) {
16584 // Make a large shift.
16585 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16586 MVT::v8i16, R, ShiftAmt,
16588 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16589 // Zero out the rightmost bits.
16590 SmallVector<SDValue, 16> V(16,
16591 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16593 return DAG.getNode(ISD::AND, dl, VT, SHL,
16594 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16596 if (Op.getOpcode() == ISD::SRL) {
16597 // Make a large shift.
16598 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16599 MVT::v8i16, R, ShiftAmt,
16601 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16602 // Zero out the leftmost bits.
16603 SmallVector<SDValue, 16> V(16,
16604 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16606 return DAG.getNode(ISD::AND, dl, VT, SRL,
16607 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16609 if (Op.getOpcode() == ISD::SRA) {
16610 if (ShiftAmt == 7) {
16611 // R s>> 7 === R s< 0
16612 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16613 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16616 // R s>> a === ((R u>> a) ^ m) - m
16617 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16618 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16620 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16621 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16622 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16625 llvm_unreachable("Unknown shift opcode.");
16628 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16629 if (Op.getOpcode() == ISD::SHL) {
16630 // Make a large shift.
16631 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16632 MVT::v16i16, R, ShiftAmt,
16634 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16635 // Zero out the rightmost bits.
16636 SmallVector<SDValue, 32> V(32,
16637 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16639 return DAG.getNode(ISD::AND, dl, VT, SHL,
16640 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16642 if (Op.getOpcode() == ISD::SRL) {
16643 // Make a large shift.
16644 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16645 MVT::v16i16, R, ShiftAmt,
16647 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16648 // Zero out the leftmost bits.
16649 SmallVector<SDValue, 32> V(32,
16650 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16652 return DAG.getNode(ISD::AND, dl, VT, SRL,
16653 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16655 if (Op.getOpcode() == ISD::SRA) {
16656 if (ShiftAmt == 7) {
16657 // R s>> 7 === R s< 0
16658 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16659 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16662 // R s>> a === ((R u>> a) ^ m) - m
16663 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16664 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16666 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16667 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16668 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16671 llvm_unreachable("Unknown shift opcode.");
16676 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16677 if (!Subtarget->is64Bit() &&
16678 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16679 Amt.getOpcode() == ISD::BITCAST &&
16680 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16681 Amt = Amt.getOperand(0);
16682 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16683 VT.getVectorNumElements();
16684 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16685 uint64_t ShiftAmt = 0;
16686 for (unsigned i = 0; i != Ratio; ++i) {
16687 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16691 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16693 // Check remaining shift amounts.
16694 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16695 uint64_t ShAmt = 0;
16696 for (unsigned j = 0; j != Ratio; ++j) {
16697 ConstantSDNode *C =
16698 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16702 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16704 if (ShAmt != ShiftAmt)
16707 switch (Op.getOpcode()) {
16709 llvm_unreachable("Unknown shift opcode!");
16711 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16714 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16717 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16725 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16726 const X86Subtarget* Subtarget) {
16727 MVT VT = Op.getSimpleValueType();
16729 SDValue R = Op.getOperand(0);
16730 SDValue Amt = Op.getOperand(1);
16732 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16733 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16734 (Subtarget->hasInt256() &&
16735 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16736 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16737 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16739 EVT EltVT = VT.getVectorElementType();
16741 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16742 unsigned NumElts = VT.getVectorNumElements();
16744 for (i = 0; i != NumElts; ++i) {
16745 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16749 for (j = i; j != NumElts; ++j) {
16750 SDValue Arg = Amt.getOperand(j);
16751 if (Arg.getOpcode() == ISD::UNDEF) continue;
16752 if (Arg != Amt.getOperand(i))
16755 if (i != NumElts && j == NumElts)
16756 BaseShAmt = Amt.getOperand(i);
16758 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16759 Amt = Amt.getOperand(0);
16760 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16761 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16762 SDValue InVec = Amt.getOperand(0);
16763 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16764 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16766 for (; i != NumElts; ++i) {
16767 SDValue Arg = InVec.getOperand(i);
16768 if (Arg.getOpcode() == ISD::UNDEF) continue;
16772 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16773 if (ConstantSDNode *C =
16774 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16775 unsigned SplatIdx =
16776 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16777 if (C->getZExtValue() == SplatIdx)
16778 BaseShAmt = InVec.getOperand(1);
16781 if (!BaseShAmt.getNode())
16782 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16783 DAG.getIntPtrConstant(0));
16787 if (BaseShAmt.getNode()) {
16788 if (EltVT.bitsGT(MVT::i32))
16789 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16790 else if (EltVT.bitsLT(MVT::i32))
16791 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16793 switch (Op.getOpcode()) {
16795 llvm_unreachable("Unknown shift opcode!");
16797 switch (VT.SimpleTy) {
16798 default: return SDValue();
16807 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16810 switch (VT.SimpleTy) {
16811 default: return SDValue();
16818 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16821 switch (VT.SimpleTy) {
16822 default: return SDValue();
16831 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16837 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16838 if (!Subtarget->is64Bit() &&
16839 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16840 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16841 Amt.getOpcode() == ISD::BITCAST &&
16842 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16843 Amt = Amt.getOperand(0);
16844 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16845 VT.getVectorNumElements();
16846 std::vector<SDValue> Vals(Ratio);
16847 for (unsigned i = 0; i != Ratio; ++i)
16848 Vals[i] = Amt.getOperand(i);
16849 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16850 for (unsigned j = 0; j != Ratio; ++j)
16851 if (Vals[j] != Amt.getOperand(i + j))
16854 switch (Op.getOpcode()) {
16856 llvm_unreachable("Unknown shift opcode!");
16858 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16860 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16862 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16869 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16870 SelectionDAG &DAG) {
16871 MVT VT = Op.getSimpleValueType();
16873 SDValue R = Op.getOperand(0);
16874 SDValue Amt = Op.getOperand(1);
16877 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16878 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16880 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16884 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16888 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16890 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16891 if (Subtarget->hasInt256()) {
16892 if (Op.getOpcode() == ISD::SRL &&
16893 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16894 VT == MVT::v4i64 || VT == MVT::v8i32))
16896 if (Op.getOpcode() == ISD::SHL &&
16897 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16898 VT == MVT::v4i64 || VT == MVT::v8i32))
16900 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16904 // If possible, lower this packed shift into a vector multiply instead of
16905 // expanding it into a sequence of scalar shifts.
16906 // Do this only if the vector shift count is a constant build_vector.
16907 if (Op.getOpcode() == ISD::SHL &&
16908 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16909 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16910 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16911 SmallVector<SDValue, 8> Elts;
16912 EVT SVT = VT.getScalarType();
16913 unsigned SVTBits = SVT.getSizeInBits();
16914 const APInt &One = APInt(SVTBits, 1);
16915 unsigned NumElems = VT.getVectorNumElements();
16917 for (unsigned i=0; i !=NumElems; ++i) {
16918 SDValue Op = Amt->getOperand(i);
16919 if (Op->getOpcode() == ISD::UNDEF) {
16920 Elts.push_back(Op);
16924 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16925 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16926 uint64_t ShAmt = C.getZExtValue();
16927 if (ShAmt >= SVTBits) {
16928 Elts.push_back(DAG.getUNDEF(SVT));
16931 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16933 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16934 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16937 // Lower SHL with variable shift amount.
16938 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16939 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16941 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16942 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16943 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16944 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16947 // If possible, lower this shift as a sequence of two shifts by
16948 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16950 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16952 // Could be rewritten as:
16953 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16955 // The advantage is that the two shifts from the example would be
16956 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16957 // the vector shift into four scalar shifts plus four pairs of vector
16959 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16960 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16961 unsigned TargetOpcode = X86ISD::MOVSS;
16962 bool CanBeSimplified;
16963 // The splat value for the first packed shift (the 'X' from the example).
16964 SDValue Amt1 = Amt->getOperand(0);
16965 // The splat value for the second packed shift (the 'Y' from the example).
16966 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16967 Amt->getOperand(2);
16969 // See if it is possible to replace this node with a sequence of
16970 // two shifts followed by a MOVSS/MOVSD
16971 if (VT == MVT::v4i32) {
16972 // Check if it is legal to use a MOVSS.
16973 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16974 Amt2 == Amt->getOperand(3);
16975 if (!CanBeSimplified) {
16976 // Otherwise, check if we can still simplify this node using a MOVSD.
16977 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16978 Amt->getOperand(2) == Amt->getOperand(3);
16979 TargetOpcode = X86ISD::MOVSD;
16980 Amt2 = Amt->getOperand(2);
16983 // Do similar checks for the case where the machine value type
16985 CanBeSimplified = Amt1 == Amt->getOperand(1);
16986 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16987 CanBeSimplified = Amt2 == Amt->getOperand(i);
16989 if (!CanBeSimplified) {
16990 TargetOpcode = X86ISD::MOVSD;
16991 CanBeSimplified = true;
16992 Amt2 = Amt->getOperand(4);
16993 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16994 CanBeSimplified = Amt1 == Amt->getOperand(i);
16995 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16996 CanBeSimplified = Amt2 == Amt->getOperand(j);
17000 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17001 isa<ConstantSDNode>(Amt2)) {
17002 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17003 EVT CastVT = MVT::v4i32;
17005 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17006 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17008 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17009 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17010 if (TargetOpcode == X86ISD::MOVSD)
17011 CastVT = MVT::v2i64;
17012 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17013 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17014 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17016 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17020 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17021 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17024 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17025 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17027 // Turn 'a' into a mask suitable for VSELECT
17028 SDValue VSelM = DAG.getConstant(0x80, VT);
17029 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17030 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17032 SDValue CM1 = DAG.getConstant(0x0f, VT);
17033 SDValue CM2 = DAG.getConstant(0x3f, VT);
17035 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17036 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17037 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17038 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17039 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17042 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17043 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17044 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17046 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17047 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17048 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17049 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17050 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17053 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17054 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17055 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17057 // return VSELECT(r, r+r, a);
17058 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17059 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17063 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17064 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17065 // solution better.
17066 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17067 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17069 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17070 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17071 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17072 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17073 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17076 // Decompose 256-bit shifts into smaller 128-bit shifts.
17077 if (VT.is256BitVector()) {
17078 unsigned NumElems = VT.getVectorNumElements();
17079 MVT EltVT = VT.getVectorElementType();
17080 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17082 // Extract the two vectors
17083 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17084 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17086 // Recreate the shift amount vectors
17087 SDValue Amt1, Amt2;
17088 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17089 // Constant shift amount
17090 SmallVector<SDValue, 4> Amt1Csts;
17091 SmallVector<SDValue, 4> Amt2Csts;
17092 for (unsigned i = 0; i != NumElems/2; ++i)
17093 Amt1Csts.push_back(Amt->getOperand(i));
17094 for (unsigned i = NumElems/2; i != NumElems; ++i)
17095 Amt2Csts.push_back(Amt->getOperand(i));
17097 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17098 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17100 // Variable shift amount
17101 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17102 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17105 // Issue new vector shifts for the smaller types
17106 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17107 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17109 // Concatenate the result back
17110 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17116 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17117 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17118 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17119 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17120 // has only one use.
17121 SDNode *N = Op.getNode();
17122 SDValue LHS = N->getOperand(0);
17123 SDValue RHS = N->getOperand(1);
17124 unsigned BaseOp = 0;
17127 switch (Op.getOpcode()) {
17128 default: llvm_unreachable("Unknown ovf instruction!");
17130 // A subtract of one will be selected as a INC. Note that INC doesn't
17131 // set CF, so we can't do this for UADDO.
17132 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17134 BaseOp = X86ISD::INC;
17135 Cond = X86::COND_O;
17138 BaseOp = X86ISD::ADD;
17139 Cond = X86::COND_O;
17142 BaseOp = X86ISD::ADD;
17143 Cond = X86::COND_B;
17146 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17147 // set CF, so we can't do this for USUBO.
17148 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17150 BaseOp = X86ISD::DEC;
17151 Cond = X86::COND_O;
17154 BaseOp = X86ISD::SUB;
17155 Cond = X86::COND_O;
17158 BaseOp = X86ISD::SUB;
17159 Cond = X86::COND_B;
17162 BaseOp = X86ISD::SMUL;
17163 Cond = X86::COND_O;
17165 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17166 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17168 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17171 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17172 DAG.getConstant(X86::COND_O, MVT::i32),
17173 SDValue(Sum.getNode(), 2));
17175 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17179 // Also sets EFLAGS.
17180 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17181 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17184 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17185 DAG.getConstant(Cond, MVT::i32),
17186 SDValue(Sum.getNode(), 1));
17188 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17191 // Sign extension of the low part of vector elements. This may be used either
17192 // when sign extend instructions are not available or if the vector element
17193 // sizes already match the sign-extended size. If the vector elements are in
17194 // their pre-extended size and sign extend instructions are available, that will
17195 // be handled by LowerSIGN_EXTEND.
17196 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17197 SelectionDAG &DAG) const {
17199 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17200 MVT VT = Op.getSimpleValueType();
17202 if (!Subtarget->hasSSE2() || !VT.isVector())
17205 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17206 ExtraVT.getScalarType().getSizeInBits();
17208 switch (VT.SimpleTy) {
17209 default: return SDValue();
17212 if (!Subtarget->hasFp256())
17214 if (!Subtarget->hasInt256()) {
17215 // needs to be split
17216 unsigned NumElems = VT.getVectorNumElements();
17218 // Extract the LHS vectors
17219 SDValue LHS = Op.getOperand(0);
17220 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17221 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17223 MVT EltVT = VT.getVectorElementType();
17224 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17226 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17227 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17228 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17230 SDValue Extra = DAG.getValueType(ExtraVT);
17232 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17233 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17235 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17240 SDValue Op0 = Op.getOperand(0);
17242 // This is a sign extension of some low part of vector elements without
17243 // changing the size of the vector elements themselves:
17244 // Shift-Left + Shift-Right-Algebraic.
17245 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17247 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17253 /// Returns true if the operand type is exactly twice the native width, and
17254 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17255 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17256 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17257 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17258 const X86Subtarget &Subtarget =
17259 getTargetMachine().getSubtarget<X86Subtarget>();
17260 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17263 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17264 else if (OpWidth == 128)
17265 return Subtarget.hasCmpxchg16b();
17270 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17271 return needsCmpXchgNb(SI->getValueOperand()->getType());
17274 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *SI) const {
17275 return false; // FIXME, currently these are expanded separately in this file.
17278 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17279 const X86Subtarget &Subtarget =
17280 getTargetMachine().getSubtarget<X86Subtarget>();
17281 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17282 const Type *MemType = AI->getType();
17284 // If the operand is too big, we must see if cmpxchg8/16b is available
17285 // and default to library calls otherwise.
17286 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17287 return needsCmpXchgNb(MemType);
17289 AtomicRMWInst::BinOp Op = AI->getOperation();
17292 llvm_unreachable("Unknown atomic operation");
17293 case AtomicRMWInst::Xchg:
17294 case AtomicRMWInst::Add:
17295 case AtomicRMWInst::Sub:
17296 // It's better to use xadd, xsub or xchg for these in all cases.
17298 case AtomicRMWInst::Or:
17299 case AtomicRMWInst::And:
17300 case AtomicRMWInst::Xor:
17301 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17302 // prefix to a normal instruction for these operations.
17303 return !AI->use_empty();
17304 case AtomicRMWInst::Nand:
17305 case AtomicRMWInst::Max:
17306 case AtomicRMWInst::Min:
17307 case AtomicRMWInst::UMax:
17308 case AtomicRMWInst::UMin:
17309 // These always require a non-trivial set of data operations on x86. We must
17310 // use a cmpxchg loop.
17315 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17316 SelectionDAG &DAG) {
17318 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17319 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17320 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17321 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17323 // The only fence that needs an instruction is a sequentially-consistent
17324 // cross-thread fence.
17325 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17326 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17327 // no-sse2). There isn't any reason to disable it if the target processor
17329 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17330 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17332 SDValue Chain = Op.getOperand(0);
17333 SDValue Zero = DAG.getConstant(0, MVT::i32);
17335 DAG.getRegister(X86::ESP, MVT::i32), // Base
17336 DAG.getTargetConstant(1, MVT::i8), // Scale
17337 DAG.getRegister(0, MVT::i32), // Index
17338 DAG.getTargetConstant(0, MVT::i32), // Disp
17339 DAG.getRegister(0, MVT::i32), // Segment.
17343 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17344 return SDValue(Res, 0);
17347 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17348 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17351 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17352 SelectionDAG &DAG) {
17353 MVT T = Op.getSimpleValueType();
17357 switch(T.SimpleTy) {
17358 default: llvm_unreachable("Invalid value type!");
17359 case MVT::i8: Reg = X86::AL; size = 1; break;
17360 case MVT::i16: Reg = X86::AX; size = 2; break;
17361 case MVT::i32: Reg = X86::EAX; size = 4; break;
17363 assert(Subtarget->is64Bit() && "Node not type legal!");
17364 Reg = X86::RAX; size = 8;
17367 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17368 Op.getOperand(2), SDValue());
17369 SDValue Ops[] = { cpIn.getValue(0),
17372 DAG.getTargetConstant(size, MVT::i8),
17373 cpIn.getValue(1) };
17374 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17375 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17376 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17380 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17381 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17382 MVT::i32, cpOut.getValue(2));
17383 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17384 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17386 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17387 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17388 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17392 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17393 SelectionDAG &DAG) {
17394 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17395 MVT DstVT = Op.getSimpleValueType();
17397 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17398 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17399 if (DstVT != MVT::f64)
17400 // This conversion needs to be expanded.
17403 SDValue InVec = Op->getOperand(0);
17405 unsigned NumElts = SrcVT.getVectorNumElements();
17406 EVT SVT = SrcVT.getVectorElementType();
17408 // Widen the vector in input in the case of MVT::v2i32.
17409 // Example: from MVT::v2i32 to MVT::v4i32.
17410 SmallVector<SDValue, 16> Elts;
17411 for (unsigned i = 0, e = NumElts; i != e; ++i)
17412 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17413 DAG.getIntPtrConstant(i)));
17415 // Explicitly mark the extra elements as Undef.
17416 SDValue Undef = DAG.getUNDEF(SVT);
17417 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17418 Elts.push_back(Undef);
17420 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17421 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17422 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17423 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17424 DAG.getIntPtrConstant(0));
17427 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17428 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17429 assert((DstVT == MVT::i64 ||
17430 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17431 "Unexpected custom BITCAST");
17432 // i64 <=> MMX conversions are Legal.
17433 if (SrcVT==MVT::i64 && DstVT.isVector())
17435 if (DstVT==MVT::i64 && SrcVT.isVector())
17437 // MMX <=> MMX conversions are Legal.
17438 if (SrcVT.isVector() && DstVT.isVector())
17440 // All other conversions need to be expanded.
17444 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17445 SDNode *Node = Op.getNode();
17447 EVT T = Node->getValueType(0);
17448 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17449 DAG.getConstant(0, T), Node->getOperand(2));
17450 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17451 cast<AtomicSDNode>(Node)->getMemoryVT(),
17452 Node->getOperand(0),
17453 Node->getOperand(1), negOp,
17454 cast<AtomicSDNode>(Node)->getMemOperand(),
17455 cast<AtomicSDNode>(Node)->getOrdering(),
17456 cast<AtomicSDNode>(Node)->getSynchScope());
17459 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17460 SDNode *Node = Op.getNode();
17462 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17464 // Convert seq_cst store -> xchg
17465 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17466 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17467 // (The only way to get a 16-byte store is cmpxchg16b)
17468 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17469 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17470 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17471 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17472 cast<AtomicSDNode>(Node)->getMemoryVT(),
17473 Node->getOperand(0),
17474 Node->getOperand(1), Node->getOperand(2),
17475 cast<AtomicSDNode>(Node)->getMemOperand(),
17476 cast<AtomicSDNode>(Node)->getOrdering(),
17477 cast<AtomicSDNode>(Node)->getSynchScope());
17478 return Swap.getValue(1);
17480 // Other atomic stores have a simple pattern.
17484 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17485 EVT VT = Op.getNode()->getSimpleValueType(0);
17487 // Let legalize expand this if it isn't a legal type yet.
17488 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17491 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17494 bool ExtraOp = false;
17495 switch (Op.getOpcode()) {
17496 default: llvm_unreachable("Invalid code");
17497 case ISD::ADDC: Opc = X86ISD::ADD; break;
17498 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17499 case ISD::SUBC: Opc = X86ISD::SUB; break;
17500 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17504 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17506 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17507 Op.getOperand(1), Op.getOperand(2));
17510 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17511 SelectionDAG &DAG) {
17512 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17514 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17515 // which returns the values as { float, float } (in XMM0) or
17516 // { double, double } (which is returned in XMM0, XMM1).
17518 SDValue Arg = Op.getOperand(0);
17519 EVT ArgVT = Arg.getValueType();
17520 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17522 TargetLowering::ArgListTy Args;
17523 TargetLowering::ArgListEntry Entry;
17527 Entry.isSExt = false;
17528 Entry.isZExt = false;
17529 Args.push_back(Entry);
17531 bool isF64 = ArgVT == MVT::f64;
17532 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17533 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17534 // the results are returned via SRet in memory.
17535 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17537 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17539 Type *RetTy = isF64
17540 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17541 : (Type*)VectorType::get(ArgTy, 4);
17543 TargetLowering::CallLoweringInfo CLI(DAG);
17544 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17545 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17547 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17550 // Returned in xmm0 and xmm1.
17551 return CallResult.first;
17553 // Returned in bits 0:31 and 32:64 xmm0.
17554 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17555 CallResult.first, DAG.getIntPtrConstant(0));
17556 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17557 CallResult.first, DAG.getIntPtrConstant(1));
17558 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17559 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17562 /// LowerOperation - Provide custom lowering hooks for some operations.
17564 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17565 switch (Op.getOpcode()) {
17566 default: llvm_unreachable("Should not custom lower this!");
17567 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17568 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17569 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17570 return LowerCMP_SWAP(Op, Subtarget, DAG);
17571 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17572 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17573 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17574 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17575 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17576 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17577 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17578 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17579 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17580 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17581 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17582 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17583 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17584 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17585 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17586 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17587 case ISD::SHL_PARTS:
17588 case ISD::SRA_PARTS:
17589 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17590 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17591 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17592 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17593 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17594 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17595 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17596 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17597 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17598 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17599 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17601 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17602 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17603 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17604 case ISD::SETCC: return LowerSETCC(Op, DAG);
17605 case ISD::SELECT: return LowerSELECT(Op, DAG);
17606 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17607 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17608 case ISD::VASTART: return LowerVASTART(Op, DAG);
17609 case ISD::VAARG: return LowerVAARG(Op, DAG);
17610 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17611 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17612 case ISD::INTRINSIC_VOID:
17613 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17614 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17615 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17616 case ISD::FRAME_TO_ARGS_OFFSET:
17617 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17618 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17619 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17620 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17621 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17622 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17623 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17624 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17625 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17626 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17627 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17628 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17629 case ISD::UMUL_LOHI:
17630 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17633 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17639 case ISD::UMULO: return LowerXALUO(Op, DAG);
17640 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17641 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17645 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17646 case ISD::ADD: return LowerADD(Op, DAG);
17647 case ISD::SUB: return LowerSUB(Op, DAG);
17648 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17652 static void ReplaceATOMIC_LOAD(SDNode *Node,
17653 SmallVectorImpl<SDValue> &Results,
17654 SelectionDAG &DAG) {
17656 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17658 // Convert wide load -> cmpxchg8b/cmpxchg16b
17659 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17660 // (The only way to get a 16-byte load is cmpxchg16b)
17661 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17662 SDValue Zero = DAG.getConstant(0, VT);
17663 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17665 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17666 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17667 cast<AtomicSDNode>(Node)->getMemOperand(),
17668 cast<AtomicSDNode>(Node)->getOrdering(),
17669 cast<AtomicSDNode>(Node)->getOrdering(),
17670 cast<AtomicSDNode>(Node)->getSynchScope());
17671 Results.push_back(Swap.getValue(0));
17672 Results.push_back(Swap.getValue(2));
17675 /// ReplaceNodeResults - Replace a node with an illegal result type
17676 /// with a new node built out of custom code.
17677 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17678 SmallVectorImpl<SDValue>&Results,
17679 SelectionDAG &DAG) const {
17681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17682 switch (N->getOpcode()) {
17684 llvm_unreachable("Do not know how to custom type legalize this operation!");
17685 case ISD::SIGN_EXTEND_INREG:
17690 // We don't want to expand or promote these.
17697 case ISD::UDIVREM: {
17698 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17699 Results.push_back(V);
17702 case ISD::FP_TO_SINT:
17703 case ISD::FP_TO_UINT: {
17704 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17706 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17709 std::pair<SDValue,SDValue> Vals =
17710 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17711 SDValue FIST = Vals.first, StackSlot = Vals.second;
17712 if (FIST.getNode()) {
17713 EVT VT = N->getValueType(0);
17714 // Return a load from the stack slot.
17715 if (StackSlot.getNode())
17716 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17717 MachinePointerInfo(),
17718 false, false, false, 0));
17720 Results.push_back(FIST);
17724 case ISD::UINT_TO_FP: {
17725 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17726 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17727 N->getValueType(0) != MVT::v2f32)
17729 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17731 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17733 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17734 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17735 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17736 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17737 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17738 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17741 case ISD::FP_ROUND: {
17742 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17744 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17745 Results.push_back(V);
17748 case ISD::INTRINSIC_W_CHAIN: {
17749 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17751 default : llvm_unreachable("Do not know how to custom type "
17752 "legalize this intrinsic operation!");
17753 case Intrinsic::x86_rdtsc:
17754 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17756 case Intrinsic::x86_rdtscp:
17757 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17759 case Intrinsic::x86_rdpmc:
17760 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17763 case ISD::READCYCLECOUNTER: {
17764 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17767 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17768 EVT T = N->getValueType(0);
17769 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17770 bool Regs64bit = T == MVT::i128;
17771 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17772 SDValue cpInL, cpInH;
17773 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17774 DAG.getConstant(0, HalfT));
17775 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17776 DAG.getConstant(1, HalfT));
17777 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17778 Regs64bit ? X86::RAX : X86::EAX,
17780 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17781 Regs64bit ? X86::RDX : X86::EDX,
17782 cpInH, cpInL.getValue(1));
17783 SDValue swapInL, swapInH;
17784 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17785 DAG.getConstant(0, HalfT));
17786 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17787 DAG.getConstant(1, HalfT));
17788 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17789 Regs64bit ? X86::RBX : X86::EBX,
17790 swapInL, cpInH.getValue(1));
17791 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17792 Regs64bit ? X86::RCX : X86::ECX,
17793 swapInH, swapInL.getValue(1));
17794 SDValue Ops[] = { swapInH.getValue(0),
17796 swapInH.getValue(1) };
17797 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17798 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17799 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17800 X86ISD::LCMPXCHG8_DAG;
17801 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17802 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17803 Regs64bit ? X86::RAX : X86::EAX,
17804 HalfT, Result.getValue(1));
17805 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17806 Regs64bit ? X86::RDX : X86::EDX,
17807 HalfT, cpOutL.getValue(2));
17808 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17810 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17811 MVT::i32, cpOutH.getValue(2));
17813 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17814 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17815 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17817 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17818 Results.push_back(Success);
17819 Results.push_back(EFLAGS.getValue(1));
17822 case ISD::ATOMIC_SWAP:
17823 case ISD::ATOMIC_LOAD_ADD:
17824 case ISD::ATOMIC_LOAD_SUB:
17825 case ISD::ATOMIC_LOAD_AND:
17826 case ISD::ATOMIC_LOAD_OR:
17827 case ISD::ATOMIC_LOAD_XOR:
17828 case ISD::ATOMIC_LOAD_NAND:
17829 case ISD::ATOMIC_LOAD_MIN:
17830 case ISD::ATOMIC_LOAD_MAX:
17831 case ISD::ATOMIC_LOAD_UMIN:
17832 case ISD::ATOMIC_LOAD_UMAX:
17833 // Delegate to generic TypeLegalization. Situations we can really handle
17834 // should have already been dealt with by AtomicExpandPass.cpp.
17836 case ISD::ATOMIC_LOAD: {
17837 ReplaceATOMIC_LOAD(N, Results, DAG);
17840 case ISD::BITCAST: {
17841 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17842 EVT DstVT = N->getValueType(0);
17843 EVT SrcVT = N->getOperand(0)->getValueType(0);
17845 if (SrcVT != MVT::f64 ||
17846 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17849 unsigned NumElts = DstVT.getVectorNumElements();
17850 EVT SVT = DstVT.getVectorElementType();
17851 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17852 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17853 MVT::v2f64, N->getOperand(0));
17854 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17856 if (ExperimentalVectorWideningLegalization) {
17857 // If we are legalizing vectors by widening, we already have the desired
17858 // legal vector type, just return it.
17859 Results.push_back(ToVecInt);
17863 SmallVector<SDValue, 8> Elts;
17864 for (unsigned i = 0, e = NumElts; i != e; ++i)
17865 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17866 ToVecInt, DAG.getIntPtrConstant(i)));
17868 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17873 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17875 default: return nullptr;
17876 case X86ISD::BSF: return "X86ISD::BSF";
17877 case X86ISD::BSR: return "X86ISD::BSR";
17878 case X86ISD::SHLD: return "X86ISD::SHLD";
17879 case X86ISD::SHRD: return "X86ISD::SHRD";
17880 case X86ISD::FAND: return "X86ISD::FAND";
17881 case X86ISD::FANDN: return "X86ISD::FANDN";
17882 case X86ISD::FOR: return "X86ISD::FOR";
17883 case X86ISD::FXOR: return "X86ISD::FXOR";
17884 case X86ISD::FSRL: return "X86ISD::FSRL";
17885 case X86ISD::FILD: return "X86ISD::FILD";
17886 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17887 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17888 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17889 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17890 case X86ISD::FLD: return "X86ISD::FLD";
17891 case X86ISD::FST: return "X86ISD::FST";
17892 case X86ISD::CALL: return "X86ISD::CALL";
17893 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17894 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17895 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17896 case X86ISD::BT: return "X86ISD::BT";
17897 case X86ISD::CMP: return "X86ISD::CMP";
17898 case X86ISD::COMI: return "X86ISD::COMI";
17899 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17900 case X86ISD::CMPM: return "X86ISD::CMPM";
17901 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17902 case X86ISD::SETCC: return "X86ISD::SETCC";
17903 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17904 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17905 case X86ISD::CMOV: return "X86ISD::CMOV";
17906 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17907 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17908 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17909 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17910 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17911 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17912 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17913 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17914 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17915 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17916 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17917 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17918 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17919 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17920 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17921 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17922 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17923 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17924 case X86ISD::HADD: return "X86ISD::HADD";
17925 case X86ISD::HSUB: return "X86ISD::HSUB";
17926 case X86ISD::FHADD: return "X86ISD::FHADD";
17927 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17928 case X86ISD::UMAX: return "X86ISD::UMAX";
17929 case X86ISD::UMIN: return "X86ISD::UMIN";
17930 case X86ISD::SMAX: return "X86ISD::SMAX";
17931 case X86ISD::SMIN: return "X86ISD::SMIN";
17932 case X86ISD::FMAX: return "X86ISD::FMAX";
17933 case X86ISD::FMIN: return "X86ISD::FMIN";
17934 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17935 case X86ISD::FMINC: return "X86ISD::FMINC";
17936 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17937 case X86ISD::FRCP: return "X86ISD::FRCP";
17938 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17939 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17940 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17941 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17942 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17943 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17944 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17945 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17946 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17947 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17948 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17949 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17950 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17951 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17952 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17953 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17954 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17955 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17956 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17957 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17958 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17959 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17960 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17961 case X86ISD::VSHL: return "X86ISD::VSHL";
17962 case X86ISD::VSRL: return "X86ISD::VSRL";
17963 case X86ISD::VSRA: return "X86ISD::VSRA";
17964 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17965 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17966 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17967 case X86ISD::CMPP: return "X86ISD::CMPP";
17968 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17969 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17970 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17971 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17972 case X86ISD::ADD: return "X86ISD::ADD";
17973 case X86ISD::SUB: return "X86ISD::SUB";
17974 case X86ISD::ADC: return "X86ISD::ADC";
17975 case X86ISD::SBB: return "X86ISD::SBB";
17976 case X86ISD::SMUL: return "X86ISD::SMUL";
17977 case X86ISD::UMUL: return "X86ISD::UMUL";
17978 case X86ISD::INC: return "X86ISD::INC";
17979 case X86ISD::DEC: return "X86ISD::DEC";
17980 case X86ISD::OR: return "X86ISD::OR";
17981 case X86ISD::XOR: return "X86ISD::XOR";
17982 case X86ISD::AND: return "X86ISD::AND";
17983 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17984 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17985 case X86ISD::PTEST: return "X86ISD::PTEST";
17986 case X86ISD::TESTP: return "X86ISD::TESTP";
17987 case X86ISD::TESTM: return "X86ISD::TESTM";
17988 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17989 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17990 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17991 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17992 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17993 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17994 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17995 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17996 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17997 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17998 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17999 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18000 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18001 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18002 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18003 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18004 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18005 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18006 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18007 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18008 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18009 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18010 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18011 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18012 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18013 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
18014 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18015 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18016 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18017 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18018 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18019 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18020 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18021 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18022 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18023 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18024 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18025 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18026 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18027 case X86ISD::SAHF: return "X86ISD::SAHF";
18028 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18029 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18030 case X86ISD::FMADD: return "X86ISD::FMADD";
18031 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18032 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18033 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18034 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18035 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18036 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18037 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18038 case X86ISD::XTEST: return "X86ISD::XTEST";
18042 // isLegalAddressingMode - Return true if the addressing mode represented
18043 // by AM is legal for this target, for a load/store of the specified type.
18044 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18046 // X86 supports extremely general addressing modes.
18047 CodeModel::Model M = getTargetMachine().getCodeModel();
18048 Reloc::Model R = getTargetMachine().getRelocationModel();
18050 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18051 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18056 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18058 // If a reference to this global requires an extra load, we can't fold it.
18059 if (isGlobalStubReference(GVFlags))
18062 // If BaseGV requires a register for the PIC base, we cannot also have a
18063 // BaseReg specified.
18064 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18067 // If lower 4G is not available, then we must use rip-relative addressing.
18068 if ((M != CodeModel::Small || R != Reloc::Static) &&
18069 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18073 switch (AM.Scale) {
18079 // These scales always work.
18084 // These scales are formed with basereg+scalereg. Only accept if there is
18089 default: // Other stuff never works.
18096 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18097 unsigned Bits = Ty->getScalarSizeInBits();
18099 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18100 // particularly cheaper than those without.
18104 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18105 // variable shifts just as cheap as scalar ones.
18106 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18109 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18110 // fully general vector.
18114 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18115 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18117 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18118 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18119 return NumBits1 > NumBits2;
18122 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18123 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18126 if (!isTypeLegal(EVT::getEVT(Ty1)))
18129 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18131 // Assuming the caller doesn't have a zeroext or signext return parameter,
18132 // truncation all the way down to i1 is valid.
18136 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18137 return isInt<32>(Imm);
18140 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18141 // Can also use sub to handle negated immediates.
18142 return isInt<32>(Imm);
18145 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18146 if (!VT1.isInteger() || !VT2.isInteger())
18148 unsigned NumBits1 = VT1.getSizeInBits();
18149 unsigned NumBits2 = VT2.getSizeInBits();
18150 return NumBits1 > NumBits2;
18153 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18154 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18155 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18158 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18159 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18160 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18163 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18164 EVT VT1 = Val.getValueType();
18165 if (isZExtFree(VT1, VT2))
18168 if (Val.getOpcode() != ISD::LOAD)
18171 if (!VT1.isSimple() || !VT1.isInteger() ||
18172 !VT2.isSimple() || !VT2.isInteger())
18175 switch (VT1.getSimpleVT().SimpleTy) {
18180 // X86 has 8, 16, and 32-bit zero-extending loads.
18188 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18189 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18192 VT = VT.getScalarType();
18194 if (!VT.isSimple())
18197 switch (VT.getSimpleVT().SimpleTy) {
18208 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18209 // i16 instructions are longer (0x66 prefix) and potentially slower.
18210 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18213 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18214 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18215 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18216 /// are assumed to be legal.
18218 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18220 if (!VT.isSimple())
18223 MVT SVT = VT.getSimpleVT();
18225 // Very little shuffling can be done for 64-bit vectors right now.
18226 if (VT.getSizeInBits() == 64)
18229 // If this is a single-input shuffle with no 128 bit lane crossings we can
18230 // lower it into pshufb.
18231 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18232 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18233 bool isLegal = true;
18234 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18235 if (M[I] >= (int)SVT.getVectorNumElements() ||
18236 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18245 // FIXME: blends, shifts.
18246 return (SVT.getVectorNumElements() == 2 ||
18247 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18248 isMOVLMask(M, SVT) ||
18249 isMOVHLPSMask(M, SVT) ||
18250 isSHUFPMask(M, SVT) ||
18251 isPSHUFDMask(M, SVT) ||
18252 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18253 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18254 isPALIGNRMask(M, SVT, Subtarget) ||
18255 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18256 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18257 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18258 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18259 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18263 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18265 if (!VT.isSimple())
18268 MVT SVT = VT.getSimpleVT();
18269 unsigned NumElts = SVT.getVectorNumElements();
18270 // FIXME: This collection of masks seems suspect.
18273 if (NumElts == 4 && SVT.is128BitVector()) {
18274 return (isMOVLMask(Mask, SVT) ||
18275 isCommutedMOVLMask(Mask, SVT, true) ||
18276 isSHUFPMask(Mask, SVT) ||
18277 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18282 //===----------------------------------------------------------------------===//
18283 // X86 Scheduler Hooks
18284 //===----------------------------------------------------------------------===//
18286 /// Utility function to emit xbegin specifying the start of an RTM region.
18287 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18288 const TargetInstrInfo *TII) {
18289 DebugLoc DL = MI->getDebugLoc();
18291 const BasicBlock *BB = MBB->getBasicBlock();
18292 MachineFunction::iterator I = MBB;
18295 // For the v = xbegin(), we generate
18306 MachineBasicBlock *thisMBB = MBB;
18307 MachineFunction *MF = MBB->getParent();
18308 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18309 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18310 MF->insert(I, mainMBB);
18311 MF->insert(I, sinkMBB);
18313 // Transfer the remainder of BB and its successor edges to sinkMBB.
18314 sinkMBB->splice(sinkMBB->begin(), MBB,
18315 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18316 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18320 // # fallthrough to mainMBB
18321 // # abortion to sinkMBB
18322 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18323 thisMBB->addSuccessor(mainMBB);
18324 thisMBB->addSuccessor(sinkMBB);
18328 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18329 mainMBB->addSuccessor(sinkMBB);
18332 // EAX is live into the sinkMBB
18333 sinkMBB->addLiveIn(X86::EAX);
18334 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18335 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18338 MI->eraseFromParent();
18342 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18343 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18344 // in the .td file.
18345 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18346 const TargetInstrInfo *TII) {
18348 switch (MI->getOpcode()) {
18349 default: llvm_unreachable("illegal opcode!");
18350 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18351 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18352 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18353 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18354 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18355 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18356 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18357 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18360 DebugLoc dl = MI->getDebugLoc();
18361 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18363 unsigned NumArgs = MI->getNumOperands();
18364 for (unsigned i = 1; i < NumArgs; ++i) {
18365 MachineOperand &Op = MI->getOperand(i);
18366 if (!(Op.isReg() && Op.isImplicit()))
18367 MIB.addOperand(Op);
18369 if (MI->hasOneMemOperand())
18370 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18372 BuildMI(*BB, MI, dl,
18373 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18374 .addReg(X86::XMM0);
18376 MI->eraseFromParent();
18380 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18381 // defs in an instruction pattern
18382 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18383 const TargetInstrInfo *TII) {
18385 switch (MI->getOpcode()) {
18386 default: llvm_unreachable("illegal opcode!");
18387 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18388 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18389 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18390 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18391 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18392 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18393 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18394 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18397 DebugLoc dl = MI->getDebugLoc();
18398 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18400 unsigned NumArgs = MI->getNumOperands(); // remove the results
18401 for (unsigned i = 1; i < NumArgs; ++i) {
18402 MachineOperand &Op = MI->getOperand(i);
18403 if (!(Op.isReg() && Op.isImplicit()))
18404 MIB.addOperand(Op);
18406 if (MI->hasOneMemOperand())
18407 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18409 BuildMI(*BB, MI, dl,
18410 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18413 MI->eraseFromParent();
18417 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18418 const TargetInstrInfo *TII,
18419 const X86Subtarget* Subtarget) {
18420 DebugLoc dl = MI->getDebugLoc();
18422 // Address into RAX/EAX, other two args into ECX, EDX.
18423 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18424 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18425 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18426 for (int i = 0; i < X86::AddrNumOperands; ++i)
18427 MIB.addOperand(MI->getOperand(i));
18429 unsigned ValOps = X86::AddrNumOperands;
18430 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18431 .addReg(MI->getOperand(ValOps).getReg());
18432 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18433 .addReg(MI->getOperand(ValOps+1).getReg());
18435 // The instruction doesn't actually take any operands though.
18436 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18438 MI->eraseFromParent(); // The pseudo is gone now.
18442 MachineBasicBlock *
18443 X86TargetLowering::EmitVAARG64WithCustomInserter(
18445 MachineBasicBlock *MBB) const {
18446 // Emit va_arg instruction on X86-64.
18448 // Operands to this pseudo-instruction:
18449 // 0 ) Output : destination address (reg)
18450 // 1-5) Input : va_list address (addr, i64mem)
18451 // 6 ) ArgSize : Size (in bytes) of vararg type
18452 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18453 // 8 ) Align : Alignment of type
18454 // 9 ) EFLAGS (implicit-def)
18456 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18457 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18459 unsigned DestReg = MI->getOperand(0).getReg();
18460 MachineOperand &Base = MI->getOperand(1);
18461 MachineOperand &Scale = MI->getOperand(2);
18462 MachineOperand &Index = MI->getOperand(3);
18463 MachineOperand &Disp = MI->getOperand(4);
18464 MachineOperand &Segment = MI->getOperand(5);
18465 unsigned ArgSize = MI->getOperand(6).getImm();
18466 unsigned ArgMode = MI->getOperand(7).getImm();
18467 unsigned Align = MI->getOperand(8).getImm();
18469 // Memory Reference
18470 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18471 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18472 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18474 // Machine Information
18475 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18476 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18477 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18478 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18479 DebugLoc DL = MI->getDebugLoc();
18481 // struct va_list {
18484 // i64 overflow_area (address)
18485 // i64 reg_save_area (address)
18487 // sizeof(va_list) = 24
18488 // alignment(va_list) = 8
18490 unsigned TotalNumIntRegs = 6;
18491 unsigned TotalNumXMMRegs = 8;
18492 bool UseGPOffset = (ArgMode == 1);
18493 bool UseFPOffset = (ArgMode == 2);
18494 unsigned MaxOffset = TotalNumIntRegs * 8 +
18495 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18497 /* Align ArgSize to a multiple of 8 */
18498 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18499 bool NeedsAlign = (Align > 8);
18501 MachineBasicBlock *thisMBB = MBB;
18502 MachineBasicBlock *overflowMBB;
18503 MachineBasicBlock *offsetMBB;
18504 MachineBasicBlock *endMBB;
18506 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18507 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18508 unsigned OffsetReg = 0;
18510 if (!UseGPOffset && !UseFPOffset) {
18511 // If we only pull from the overflow region, we don't create a branch.
18512 // We don't need to alter control flow.
18513 OffsetDestReg = 0; // unused
18514 OverflowDestReg = DestReg;
18516 offsetMBB = nullptr;
18517 overflowMBB = thisMBB;
18520 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18521 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18522 // If not, pull from overflow_area. (branch to overflowMBB)
18527 // offsetMBB overflowMBB
18532 // Registers for the PHI in endMBB
18533 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18534 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18536 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18537 MachineFunction *MF = MBB->getParent();
18538 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18539 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18540 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18542 MachineFunction::iterator MBBIter = MBB;
18545 // Insert the new basic blocks
18546 MF->insert(MBBIter, offsetMBB);
18547 MF->insert(MBBIter, overflowMBB);
18548 MF->insert(MBBIter, endMBB);
18550 // Transfer the remainder of MBB and its successor edges to endMBB.
18551 endMBB->splice(endMBB->begin(), thisMBB,
18552 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18553 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18555 // Make offsetMBB and overflowMBB successors of thisMBB
18556 thisMBB->addSuccessor(offsetMBB);
18557 thisMBB->addSuccessor(overflowMBB);
18559 // endMBB is a successor of both offsetMBB and overflowMBB
18560 offsetMBB->addSuccessor(endMBB);
18561 overflowMBB->addSuccessor(endMBB);
18563 // Load the offset value into a register
18564 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18565 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18569 .addDisp(Disp, UseFPOffset ? 4 : 0)
18570 .addOperand(Segment)
18571 .setMemRefs(MMOBegin, MMOEnd);
18573 // Check if there is enough room left to pull this argument.
18574 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18576 .addImm(MaxOffset + 8 - ArgSizeA8);
18578 // Branch to "overflowMBB" if offset >= max
18579 // Fall through to "offsetMBB" otherwise
18580 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18581 .addMBB(overflowMBB);
18584 // In offsetMBB, emit code to use the reg_save_area.
18586 assert(OffsetReg != 0);
18588 // Read the reg_save_area address.
18589 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18590 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18595 .addOperand(Segment)
18596 .setMemRefs(MMOBegin, MMOEnd);
18598 // Zero-extend the offset
18599 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18600 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18603 .addImm(X86::sub_32bit);
18605 // Add the offset to the reg_save_area to get the final address.
18606 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18607 .addReg(OffsetReg64)
18608 .addReg(RegSaveReg);
18610 // Compute the offset for the next argument
18611 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18612 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18614 .addImm(UseFPOffset ? 16 : 8);
18616 // Store it back into the va_list.
18617 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18621 .addDisp(Disp, UseFPOffset ? 4 : 0)
18622 .addOperand(Segment)
18623 .addReg(NextOffsetReg)
18624 .setMemRefs(MMOBegin, MMOEnd);
18627 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18632 // Emit code to use overflow area
18635 // Load the overflow_area address into a register.
18636 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18637 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18642 .addOperand(Segment)
18643 .setMemRefs(MMOBegin, MMOEnd);
18645 // If we need to align it, do so. Otherwise, just copy the address
18646 // to OverflowDestReg.
18648 // Align the overflow address
18649 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18650 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18652 // aligned_addr = (addr + (align-1)) & ~(align-1)
18653 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18654 .addReg(OverflowAddrReg)
18657 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18659 .addImm(~(uint64_t)(Align-1));
18661 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18662 .addReg(OverflowAddrReg);
18665 // Compute the next overflow address after this argument.
18666 // (the overflow address should be kept 8-byte aligned)
18667 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18668 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18669 .addReg(OverflowDestReg)
18670 .addImm(ArgSizeA8);
18672 // Store the new overflow address.
18673 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18678 .addOperand(Segment)
18679 .addReg(NextAddrReg)
18680 .setMemRefs(MMOBegin, MMOEnd);
18682 // If we branched, emit the PHI to the front of endMBB.
18684 BuildMI(*endMBB, endMBB->begin(), DL,
18685 TII->get(X86::PHI), DestReg)
18686 .addReg(OffsetDestReg).addMBB(offsetMBB)
18687 .addReg(OverflowDestReg).addMBB(overflowMBB);
18690 // Erase the pseudo instruction
18691 MI->eraseFromParent();
18696 MachineBasicBlock *
18697 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18699 MachineBasicBlock *MBB) const {
18700 // Emit code to save XMM registers to the stack. The ABI says that the
18701 // number of registers to save is given in %al, so it's theoretically
18702 // possible to do an indirect jump trick to avoid saving all of them,
18703 // however this code takes a simpler approach and just executes all
18704 // of the stores if %al is non-zero. It's less code, and it's probably
18705 // easier on the hardware branch predictor, and stores aren't all that
18706 // expensive anyway.
18708 // Create the new basic blocks. One block contains all the XMM stores,
18709 // and one block is the final destination regardless of whether any
18710 // stores were performed.
18711 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18712 MachineFunction *F = MBB->getParent();
18713 MachineFunction::iterator MBBIter = MBB;
18715 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18716 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18717 F->insert(MBBIter, XMMSaveMBB);
18718 F->insert(MBBIter, EndMBB);
18720 // Transfer the remainder of MBB and its successor edges to EndMBB.
18721 EndMBB->splice(EndMBB->begin(), MBB,
18722 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18723 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18725 // The original block will now fall through to the XMM save block.
18726 MBB->addSuccessor(XMMSaveMBB);
18727 // The XMMSaveMBB will fall through to the end block.
18728 XMMSaveMBB->addSuccessor(EndMBB);
18730 // Now add the instructions.
18731 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18732 DebugLoc DL = MI->getDebugLoc();
18734 unsigned CountReg = MI->getOperand(0).getReg();
18735 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18736 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18738 if (!Subtarget->isTargetWin64()) {
18739 // If %al is 0, branch around the XMM save block.
18740 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18741 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18742 MBB->addSuccessor(EndMBB);
18745 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18746 // that was just emitted, but clearly shouldn't be "saved".
18747 assert((MI->getNumOperands() <= 3 ||
18748 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18749 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18750 && "Expected last argument to be EFLAGS");
18751 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18752 // In the XMM save block, save all the XMM argument registers.
18753 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18754 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18755 MachineMemOperand *MMO =
18756 F->getMachineMemOperand(
18757 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18758 MachineMemOperand::MOStore,
18759 /*Size=*/16, /*Align=*/16);
18760 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18761 .addFrameIndex(RegSaveFrameIndex)
18762 .addImm(/*Scale=*/1)
18763 .addReg(/*IndexReg=*/0)
18764 .addImm(/*Disp=*/Offset)
18765 .addReg(/*Segment=*/0)
18766 .addReg(MI->getOperand(i).getReg())
18767 .addMemOperand(MMO);
18770 MI->eraseFromParent(); // The pseudo instruction is gone now.
18775 // The EFLAGS operand of SelectItr might be missing a kill marker
18776 // because there were multiple uses of EFLAGS, and ISel didn't know
18777 // which to mark. Figure out whether SelectItr should have had a
18778 // kill marker, and set it if it should. Returns the correct kill
18780 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18781 MachineBasicBlock* BB,
18782 const TargetRegisterInfo* TRI) {
18783 // Scan forward through BB for a use/def of EFLAGS.
18784 MachineBasicBlock::iterator miI(std::next(SelectItr));
18785 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18786 const MachineInstr& mi = *miI;
18787 if (mi.readsRegister(X86::EFLAGS))
18789 if (mi.definesRegister(X86::EFLAGS))
18790 break; // Should have kill-flag - update below.
18793 // If we hit the end of the block, check whether EFLAGS is live into a
18795 if (miI == BB->end()) {
18796 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18797 sEnd = BB->succ_end();
18798 sItr != sEnd; ++sItr) {
18799 MachineBasicBlock* succ = *sItr;
18800 if (succ->isLiveIn(X86::EFLAGS))
18805 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18806 // out. SelectMI should have a kill flag on EFLAGS.
18807 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18811 MachineBasicBlock *
18812 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18813 MachineBasicBlock *BB) const {
18814 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18815 DebugLoc DL = MI->getDebugLoc();
18817 // To "insert" a SELECT_CC instruction, we actually have to insert the
18818 // diamond control-flow pattern. The incoming instruction knows the
18819 // destination vreg to set, the condition code register to branch on, the
18820 // true/false values to select between, and a branch opcode to use.
18821 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18822 MachineFunction::iterator It = BB;
18828 // cmpTY ccX, r1, r2
18830 // fallthrough --> copy0MBB
18831 MachineBasicBlock *thisMBB = BB;
18832 MachineFunction *F = BB->getParent();
18833 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18834 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18835 F->insert(It, copy0MBB);
18836 F->insert(It, sinkMBB);
18838 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18839 // live into the sink and copy blocks.
18840 const TargetRegisterInfo *TRI =
18841 BB->getParent()->getSubtarget().getRegisterInfo();
18842 if (!MI->killsRegister(X86::EFLAGS) &&
18843 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18844 copy0MBB->addLiveIn(X86::EFLAGS);
18845 sinkMBB->addLiveIn(X86::EFLAGS);
18848 // Transfer the remainder of BB and its successor edges to sinkMBB.
18849 sinkMBB->splice(sinkMBB->begin(), BB,
18850 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18851 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18853 // Add the true and fallthrough blocks as its successors.
18854 BB->addSuccessor(copy0MBB);
18855 BB->addSuccessor(sinkMBB);
18857 // Create the conditional branch instruction.
18859 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18860 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18863 // %FalseValue = ...
18864 // # fallthrough to sinkMBB
18865 copy0MBB->addSuccessor(sinkMBB);
18868 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18870 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18871 TII->get(X86::PHI), MI->getOperand(0).getReg())
18872 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18873 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18875 MI->eraseFromParent(); // The pseudo instruction is gone now.
18879 MachineBasicBlock *
18880 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18881 bool Is64Bit) const {
18882 MachineFunction *MF = BB->getParent();
18883 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18884 DebugLoc DL = MI->getDebugLoc();
18885 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18887 assert(MF->shouldSplitStack());
18889 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18890 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18893 // ... [Till the alloca]
18894 // If stacklet is not large enough, jump to mallocMBB
18897 // Allocate by subtracting from RSP
18898 // Jump to continueMBB
18901 // Allocate by call to runtime
18905 // [rest of original BB]
18908 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18909 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18910 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18912 MachineRegisterInfo &MRI = MF->getRegInfo();
18913 const TargetRegisterClass *AddrRegClass =
18914 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18916 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18917 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18918 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18919 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18920 sizeVReg = MI->getOperand(1).getReg(),
18921 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18923 MachineFunction::iterator MBBIter = BB;
18926 MF->insert(MBBIter, bumpMBB);
18927 MF->insert(MBBIter, mallocMBB);
18928 MF->insert(MBBIter, continueMBB);
18930 continueMBB->splice(continueMBB->begin(), BB,
18931 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18932 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18934 // Add code to the main basic block to check if the stack limit has been hit,
18935 // and if so, jump to mallocMBB otherwise to bumpMBB.
18936 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18937 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18938 .addReg(tmpSPVReg).addReg(sizeVReg);
18939 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18940 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18941 .addReg(SPLimitVReg);
18942 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18944 // bumpMBB simply decreases the stack pointer, since we know the current
18945 // stacklet has enough space.
18946 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18947 .addReg(SPLimitVReg);
18948 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18949 .addReg(SPLimitVReg);
18950 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18952 // Calls into a routine in libgcc to allocate more space from the heap.
18953 const uint32_t *RegMask = MF->getTarget()
18954 .getSubtargetImpl()
18955 ->getRegisterInfo()
18956 ->getCallPreservedMask(CallingConv::C);
18958 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18960 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18961 .addExternalSymbol("__morestack_allocate_stack_space")
18962 .addRegMask(RegMask)
18963 .addReg(X86::RDI, RegState::Implicit)
18964 .addReg(X86::RAX, RegState::ImplicitDefine);
18966 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18968 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18969 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18970 .addExternalSymbol("__morestack_allocate_stack_space")
18971 .addRegMask(RegMask)
18972 .addReg(X86::EAX, RegState::ImplicitDefine);
18976 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18979 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18980 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18981 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18983 // Set up the CFG correctly.
18984 BB->addSuccessor(bumpMBB);
18985 BB->addSuccessor(mallocMBB);
18986 mallocMBB->addSuccessor(continueMBB);
18987 bumpMBB->addSuccessor(continueMBB);
18989 // Take care of the PHI nodes.
18990 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18991 MI->getOperand(0).getReg())
18992 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18993 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18995 // Delete the original pseudo instruction.
18996 MI->eraseFromParent();
18999 return continueMBB;
19002 MachineBasicBlock *
19003 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19004 MachineBasicBlock *BB) const {
19005 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19006 DebugLoc DL = MI->getDebugLoc();
19008 assert(!Subtarget->isTargetMacho());
19010 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19011 // non-trivial part is impdef of ESP.
19013 if (Subtarget->isTargetWin64()) {
19014 if (Subtarget->isTargetCygMing()) {
19015 // ___chkstk(Mingw64):
19016 // Clobbers R10, R11, RAX and EFLAGS.
19018 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19019 .addExternalSymbol("___chkstk")
19020 .addReg(X86::RAX, RegState::Implicit)
19021 .addReg(X86::RSP, RegState::Implicit)
19022 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19023 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19024 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19026 // __chkstk(MSVCRT): does not update stack pointer.
19027 // Clobbers R10, R11 and EFLAGS.
19028 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19029 .addExternalSymbol("__chkstk")
19030 .addReg(X86::RAX, RegState::Implicit)
19031 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19032 // RAX has the offset to be subtracted from RSP.
19033 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19038 const char *StackProbeSymbol =
19039 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19041 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19042 .addExternalSymbol(StackProbeSymbol)
19043 .addReg(X86::EAX, RegState::Implicit)
19044 .addReg(X86::ESP, RegState::Implicit)
19045 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19046 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19047 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19050 MI->eraseFromParent(); // The pseudo instruction is gone now.
19054 MachineBasicBlock *
19055 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19056 MachineBasicBlock *BB) const {
19057 // This is pretty easy. We're taking the value that we received from
19058 // our load from the relocation, sticking it in either RDI (x86-64)
19059 // or EAX and doing an indirect call. The return value will then
19060 // be in the normal return register.
19061 MachineFunction *F = BB->getParent();
19062 const X86InstrInfo *TII =
19063 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19064 DebugLoc DL = MI->getDebugLoc();
19066 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19067 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19069 // Get a register mask for the lowered call.
19070 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19071 // proper register mask.
19072 const uint32_t *RegMask = F->getTarget()
19073 .getSubtargetImpl()
19074 ->getRegisterInfo()
19075 ->getCallPreservedMask(CallingConv::C);
19076 if (Subtarget->is64Bit()) {
19077 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19078 TII->get(X86::MOV64rm), X86::RDI)
19080 .addImm(0).addReg(0)
19081 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19082 MI->getOperand(3).getTargetFlags())
19084 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19085 addDirectMem(MIB, X86::RDI);
19086 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19087 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19088 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19089 TII->get(X86::MOV32rm), X86::EAX)
19091 .addImm(0).addReg(0)
19092 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19093 MI->getOperand(3).getTargetFlags())
19095 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19096 addDirectMem(MIB, X86::EAX);
19097 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19099 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19100 TII->get(X86::MOV32rm), X86::EAX)
19101 .addReg(TII->getGlobalBaseReg(F))
19102 .addImm(0).addReg(0)
19103 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19104 MI->getOperand(3).getTargetFlags())
19106 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19107 addDirectMem(MIB, X86::EAX);
19108 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19111 MI->eraseFromParent(); // The pseudo instruction is gone now.
19115 MachineBasicBlock *
19116 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19117 MachineBasicBlock *MBB) const {
19118 DebugLoc DL = MI->getDebugLoc();
19119 MachineFunction *MF = MBB->getParent();
19120 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19121 MachineRegisterInfo &MRI = MF->getRegInfo();
19123 const BasicBlock *BB = MBB->getBasicBlock();
19124 MachineFunction::iterator I = MBB;
19127 // Memory Reference
19128 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19129 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19132 unsigned MemOpndSlot = 0;
19134 unsigned CurOp = 0;
19136 DstReg = MI->getOperand(CurOp++).getReg();
19137 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19138 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19139 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19140 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19142 MemOpndSlot = CurOp;
19144 MVT PVT = getPointerTy();
19145 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19146 "Invalid Pointer Size!");
19148 // For v = setjmp(buf), we generate
19151 // buf[LabelOffset] = restoreMBB
19152 // SjLjSetup restoreMBB
19158 // v = phi(main, restore)
19163 MachineBasicBlock *thisMBB = MBB;
19164 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19165 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19166 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19167 MF->insert(I, mainMBB);
19168 MF->insert(I, sinkMBB);
19169 MF->push_back(restoreMBB);
19171 MachineInstrBuilder MIB;
19173 // Transfer the remainder of BB and its successor edges to sinkMBB.
19174 sinkMBB->splice(sinkMBB->begin(), MBB,
19175 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19176 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19179 unsigned PtrStoreOpc = 0;
19180 unsigned LabelReg = 0;
19181 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19182 Reloc::Model RM = MF->getTarget().getRelocationModel();
19183 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19184 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19186 // Prepare IP either in reg or imm.
19187 if (!UseImmLabel) {
19188 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19189 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19190 LabelReg = MRI.createVirtualRegister(PtrRC);
19191 if (Subtarget->is64Bit()) {
19192 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19196 .addMBB(restoreMBB)
19199 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19200 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19201 .addReg(XII->getGlobalBaseReg(MF))
19204 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19208 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19210 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19211 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19212 if (i == X86::AddrDisp)
19213 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19215 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19218 MIB.addReg(LabelReg);
19220 MIB.addMBB(restoreMBB);
19221 MIB.setMemRefs(MMOBegin, MMOEnd);
19223 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19224 .addMBB(restoreMBB);
19226 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19227 MF->getSubtarget().getRegisterInfo());
19228 MIB.addRegMask(RegInfo->getNoPreservedMask());
19229 thisMBB->addSuccessor(mainMBB);
19230 thisMBB->addSuccessor(restoreMBB);
19234 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19235 mainMBB->addSuccessor(sinkMBB);
19238 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19239 TII->get(X86::PHI), DstReg)
19240 .addReg(mainDstReg).addMBB(mainMBB)
19241 .addReg(restoreDstReg).addMBB(restoreMBB);
19244 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19245 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19246 restoreMBB->addSuccessor(sinkMBB);
19248 MI->eraseFromParent();
19252 MachineBasicBlock *
19253 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19254 MachineBasicBlock *MBB) const {
19255 DebugLoc DL = MI->getDebugLoc();
19256 MachineFunction *MF = MBB->getParent();
19257 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19258 MachineRegisterInfo &MRI = MF->getRegInfo();
19260 // Memory Reference
19261 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19262 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19264 MVT PVT = getPointerTy();
19265 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19266 "Invalid Pointer Size!");
19268 const TargetRegisterClass *RC =
19269 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19270 unsigned Tmp = MRI.createVirtualRegister(RC);
19271 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19272 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19273 MF->getSubtarget().getRegisterInfo());
19274 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19275 unsigned SP = RegInfo->getStackRegister();
19277 MachineInstrBuilder MIB;
19279 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19280 const int64_t SPOffset = 2 * PVT.getStoreSize();
19282 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19283 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19286 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19287 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19288 MIB.addOperand(MI->getOperand(i));
19289 MIB.setMemRefs(MMOBegin, MMOEnd);
19291 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19292 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19293 if (i == X86::AddrDisp)
19294 MIB.addDisp(MI->getOperand(i), LabelOffset);
19296 MIB.addOperand(MI->getOperand(i));
19298 MIB.setMemRefs(MMOBegin, MMOEnd);
19300 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19301 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19302 if (i == X86::AddrDisp)
19303 MIB.addDisp(MI->getOperand(i), SPOffset);
19305 MIB.addOperand(MI->getOperand(i));
19307 MIB.setMemRefs(MMOBegin, MMOEnd);
19309 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19311 MI->eraseFromParent();
19315 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19316 // accumulator loops. Writing back to the accumulator allows the coalescer
19317 // to remove extra copies in the loop.
19318 MachineBasicBlock *
19319 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19320 MachineBasicBlock *MBB) const {
19321 MachineOperand &AddendOp = MI->getOperand(3);
19323 // Bail out early if the addend isn't a register - we can't switch these.
19324 if (!AddendOp.isReg())
19327 MachineFunction &MF = *MBB->getParent();
19328 MachineRegisterInfo &MRI = MF.getRegInfo();
19330 // Check whether the addend is defined by a PHI:
19331 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19332 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19333 if (!AddendDef.isPHI())
19336 // Look for the following pattern:
19338 // %addend = phi [%entry, 0], [%loop, %result]
19340 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19344 // %addend = phi [%entry, 0], [%loop, %result]
19346 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19348 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19349 assert(AddendDef.getOperand(i).isReg());
19350 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19351 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19352 if (&PHISrcInst == MI) {
19353 // Found a matching instruction.
19354 unsigned NewFMAOpc = 0;
19355 switch (MI->getOpcode()) {
19356 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19357 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19358 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19359 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19360 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19361 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19362 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19363 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19364 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19365 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19366 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19367 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19368 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19369 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19370 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19371 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19372 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19373 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19374 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19375 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19376 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19377 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19378 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19379 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19380 default: llvm_unreachable("Unrecognized FMA variant.");
19383 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19384 MachineInstrBuilder MIB =
19385 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19386 .addOperand(MI->getOperand(0))
19387 .addOperand(MI->getOperand(3))
19388 .addOperand(MI->getOperand(2))
19389 .addOperand(MI->getOperand(1));
19390 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19391 MI->eraseFromParent();
19398 MachineBasicBlock *
19399 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19400 MachineBasicBlock *BB) const {
19401 switch (MI->getOpcode()) {
19402 default: llvm_unreachable("Unexpected instr type to insert");
19403 case X86::TAILJMPd64:
19404 case X86::TAILJMPr64:
19405 case X86::TAILJMPm64:
19406 llvm_unreachable("TAILJMP64 would not be touched here.");
19407 case X86::TCRETURNdi64:
19408 case X86::TCRETURNri64:
19409 case X86::TCRETURNmi64:
19411 case X86::WIN_ALLOCA:
19412 return EmitLoweredWinAlloca(MI, BB);
19413 case X86::SEG_ALLOCA_32:
19414 return EmitLoweredSegAlloca(MI, BB, false);
19415 case X86::SEG_ALLOCA_64:
19416 return EmitLoweredSegAlloca(MI, BB, true);
19417 case X86::TLSCall_32:
19418 case X86::TLSCall_64:
19419 return EmitLoweredTLSCall(MI, BB);
19420 case X86::CMOV_GR8:
19421 case X86::CMOV_FR32:
19422 case X86::CMOV_FR64:
19423 case X86::CMOV_V4F32:
19424 case X86::CMOV_V2F64:
19425 case X86::CMOV_V2I64:
19426 case X86::CMOV_V8F32:
19427 case X86::CMOV_V4F64:
19428 case X86::CMOV_V4I64:
19429 case X86::CMOV_V16F32:
19430 case X86::CMOV_V8F64:
19431 case X86::CMOV_V8I64:
19432 case X86::CMOV_GR16:
19433 case X86::CMOV_GR32:
19434 case X86::CMOV_RFP32:
19435 case X86::CMOV_RFP64:
19436 case X86::CMOV_RFP80:
19437 return EmitLoweredSelect(MI, BB);
19439 case X86::FP32_TO_INT16_IN_MEM:
19440 case X86::FP32_TO_INT32_IN_MEM:
19441 case X86::FP32_TO_INT64_IN_MEM:
19442 case X86::FP64_TO_INT16_IN_MEM:
19443 case X86::FP64_TO_INT32_IN_MEM:
19444 case X86::FP64_TO_INT64_IN_MEM:
19445 case X86::FP80_TO_INT16_IN_MEM:
19446 case X86::FP80_TO_INT32_IN_MEM:
19447 case X86::FP80_TO_INT64_IN_MEM: {
19448 MachineFunction *F = BB->getParent();
19449 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19450 DebugLoc DL = MI->getDebugLoc();
19452 // Change the floating point control register to use "round towards zero"
19453 // mode when truncating to an integer value.
19454 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19455 addFrameReference(BuildMI(*BB, MI, DL,
19456 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19458 // Load the old value of the high byte of the control word...
19460 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19461 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19464 // Set the high part to be round to zero...
19465 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19468 // Reload the modified control word now...
19469 addFrameReference(BuildMI(*BB, MI, DL,
19470 TII->get(X86::FLDCW16m)), CWFrameIdx);
19472 // Restore the memory image of control word to original value
19473 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19476 // Get the X86 opcode to use.
19478 switch (MI->getOpcode()) {
19479 default: llvm_unreachable("illegal opcode!");
19480 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19481 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19482 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19483 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19484 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19485 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19486 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19487 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19488 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19492 MachineOperand &Op = MI->getOperand(0);
19494 AM.BaseType = X86AddressMode::RegBase;
19495 AM.Base.Reg = Op.getReg();
19497 AM.BaseType = X86AddressMode::FrameIndexBase;
19498 AM.Base.FrameIndex = Op.getIndex();
19500 Op = MI->getOperand(1);
19502 AM.Scale = Op.getImm();
19503 Op = MI->getOperand(2);
19505 AM.IndexReg = Op.getImm();
19506 Op = MI->getOperand(3);
19507 if (Op.isGlobal()) {
19508 AM.GV = Op.getGlobal();
19510 AM.Disp = Op.getImm();
19512 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19513 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19515 // Reload the original control word now.
19516 addFrameReference(BuildMI(*BB, MI, DL,
19517 TII->get(X86::FLDCW16m)), CWFrameIdx);
19519 MI->eraseFromParent(); // The pseudo instruction is gone now.
19522 // String/text processing lowering.
19523 case X86::PCMPISTRM128REG:
19524 case X86::VPCMPISTRM128REG:
19525 case X86::PCMPISTRM128MEM:
19526 case X86::VPCMPISTRM128MEM:
19527 case X86::PCMPESTRM128REG:
19528 case X86::VPCMPESTRM128REG:
19529 case X86::PCMPESTRM128MEM:
19530 case X86::VPCMPESTRM128MEM:
19531 assert(Subtarget->hasSSE42() &&
19532 "Target must have SSE4.2 or AVX features enabled");
19533 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19535 // String/text processing lowering.
19536 case X86::PCMPISTRIREG:
19537 case X86::VPCMPISTRIREG:
19538 case X86::PCMPISTRIMEM:
19539 case X86::VPCMPISTRIMEM:
19540 case X86::PCMPESTRIREG:
19541 case X86::VPCMPESTRIREG:
19542 case X86::PCMPESTRIMEM:
19543 case X86::VPCMPESTRIMEM:
19544 assert(Subtarget->hasSSE42() &&
19545 "Target must have SSE4.2 or AVX features enabled");
19546 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19548 // Thread synchronization.
19550 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19555 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19557 case X86::VASTART_SAVE_XMM_REGS:
19558 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19560 case X86::VAARG_64:
19561 return EmitVAARG64WithCustomInserter(MI, BB);
19563 case X86::EH_SjLj_SetJmp32:
19564 case X86::EH_SjLj_SetJmp64:
19565 return emitEHSjLjSetJmp(MI, BB);
19567 case X86::EH_SjLj_LongJmp32:
19568 case X86::EH_SjLj_LongJmp64:
19569 return emitEHSjLjLongJmp(MI, BB);
19571 case TargetOpcode::STACKMAP:
19572 case TargetOpcode::PATCHPOINT:
19573 return emitPatchPoint(MI, BB);
19575 case X86::VFMADDPDr213r:
19576 case X86::VFMADDPSr213r:
19577 case X86::VFMADDSDr213r:
19578 case X86::VFMADDSSr213r:
19579 case X86::VFMSUBPDr213r:
19580 case X86::VFMSUBPSr213r:
19581 case X86::VFMSUBSDr213r:
19582 case X86::VFMSUBSSr213r:
19583 case X86::VFNMADDPDr213r:
19584 case X86::VFNMADDPSr213r:
19585 case X86::VFNMADDSDr213r:
19586 case X86::VFNMADDSSr213r:
19587 case X86::VFNMSUBPDr213r:
19588 case X86::VFNMSUBPSr213r:
19589 case X86::VFNMSUBSDr213r:
19590 case X86::VFNMSUBSSr213r:
19591 case X86::VFMADDPDr213rY:
19592 case X86::VFMADDPSr213rY:
19593 case X86::VFMSUBPDr213rY:
19594 case X86::VFMSUBPSr213rY:
19595 case X86::VFNMADDPDr213rY:
19596 case X86::VFNMADDPSr213rY:
19597 case X86::VFNMSUBPDr213rY:
19598 case X86::VFNMSUBPSr213rY:
19599 return emitFMA3Instr(MI, BB);
19603 //===----------------------------------------------------------------------===//
19604 // X86 Optimization Hooks
19605 //===----------------------------------------------------------------------===//
19607 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19610 const SelectionDAG &DAG,
19611 unsigned Depth) const {
19612 unsigned BitWidth = KnownZero.getBitWidth();
19613 unsigned Opc = Op.getOpcode();
19614 assert((Opc >= ISD::BUILTIN_OP_END ||
19615 Opc == ISD::INTRINSIC_WO_CHAIN ||
19616 Opc == ISD::INTRINSIC_W_CHAIN ||
19617 Opc == ISD::INTRINSIC_VOID) &&
19618 "Should use MaskedValueIsZero if you don't know whether Op"
19619 " is a target node!");
19621 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19635 // These nodes' second result is a boolean.
19636 if (Op.getResNo() == 0)
19639 case X86ISD::SETCC:
19640 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19642 case ISD::INTRINSIC_WO_CHAIN: {
19643 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19644 unsigned NumLoBits = 0;
19647 case Intrinsic::x86_sse_movmsk_ps:
19648 case Intrinsic::x86_avx_movmsk_ps_256:
19649 case Intrinsic::x86_sse2_movmsk_pd:
19650 case Intrinsic::x86_avx_movmsk_pd_256:
19651 case Intrinsic::x86_mmx_pmovmskb:
19652 case Intrinsic::x86_sse2_pmovmskb_128:
19653 case Intrinsic::x86_avx2_pmovmskb: {
19654 // High bits of movmskp{s|d}, pmovmskb are known zero.
19656 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19657 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19658 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19659 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19660 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19661 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19662 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19663 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19665 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19674 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19676 const SelectionDAG &,
19677 unsigned Depth) const {
19678 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19679 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19680 return Op.getValueType().getScalarType().getSizeInBits();
19686 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19687 /// node is a GlobalAddress + offset.
19688 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19689 const GlobalValue* &GA,
19690 int64_t &Offset) const {
19691 if (N->getOpcode() == X86ISD::Wrapper) {
19692 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19693 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19694 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19698 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19701 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19702 /// same as extracting the high 128-bit part of 256-bit vector and then
19703 /// inserting the result into the low part of a new 256-bit vector
19704 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19705 EVT VT = SVOp->getValueType(0);
19706 unsigned NumElems = VT.getVectorNumElements();
19708 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19709 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19710 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19711 SVOp->getMaskElt(j) >= 0)
19717 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19718 /// same as extracting the low 128-bit part of 256-bit vector and then
19719 /// inserting the result into the high part of a new 256-bit vector
19720 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19721 EVT VT = SVOp->getValueType(0);
19722 unsigned NumElems = VT.getVectorNumElements();
19724 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19725 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19726 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19727 SVOp->getMaskElt(j) >= 0)
19733 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19734 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19735 TargetLowering::DAGCombinerInfo &DCI,
19736 const X86Subtarget* Subtarget) {
19738 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19739 SDValue V1 = SVOp->getOperand(0);
19740 SDValue V2 = SVOp->getOperand(1);
19741 EVT VT = SVOp->getValueType(0);
19742 unsigned NumElems = VT.getVectorNumElements();
19744 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19745 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19749 // V UNDEF BUILD_VECTOR UNDEF
19751 // CONCAT_VECTOR CONCAT_VECTOR
19754 // RESULT: V + zero extended
19756 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19757 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19758 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19761 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19764 // To match the shuffle mask, the first half of the mask should
19765 // be exactly the first vector, and all the rest a splat with the
19766 // first element of the second one.
19767 for (unsigned i = 0; i != NumElems/2; ++i)
19768 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19769 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19772 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19773 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19774 if (Ld->hasNUsesOfValue(1, 0)) {
19775 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19776 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19778 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19780 Ld->getPointerInfo(),
19781 Ld->getAlignment(),
19782 false/*isVolatile*/, true/*ReadMem*/,
19783 false/*WriteMem*/);
19785 // Make sure the newly-created LOAD is in the same position as Ld in
19786 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19787 // and update uses of Ld's output chain to use the TokenFactor.
19788 if (Ld->hasAnyUseOfValue(1)) {
19789 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19790 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19791 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19792 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19793 SDValue(ResNode.getNode(), 1));
19796 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19800 // Emit a zeroed vector and insert the desired subvector on its
19802 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19803 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19804 return DCI.CombineTo(N, InsV);
19807 //===--------------------------------------------------------------------===//
19808 // Combine some shuffles into subvector extracts and inserts:
19811 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19812 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19813 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19814 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19815 return DCI.CombineTo(N, InsV);
19818 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19819 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19820 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19821 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19822 return DCI.CombineTo(N, InsV);
19828 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19831 /// This is the leaf of the recursive combinine below. When we have found some
19832 /// chain of single-use x86 shuffle instructions and accumulated the combined
19833 /// shuffle mask represented by them, this will try to pattern match that mask
19834 /// into either a single instruction if there is a special purpose instruction
19835 /// for this operation, or into a PSHUFB instruction which is a fully general
19836 /// instruction but should only be used to replace chains over a certain depth.
19837 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19838 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19839 TargetLowering::DAGCombinerInfo &DCI,
19840 const X86Subtarget *Subtarget) {
19841 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19843 // Find the operand that enters the chain. Note that multiple uses are OK
19844 // here, we're not going to remove the operand we find.
19845 SDValue Input = Op.getOperand(0);
19846 while (Input.getOpcode() == ISD::BITCAST)
19847 Input = Input.getOperand(0);
19849 MVT VT = Input.getSimpleValueType();
19850 MVT RootVT = Root.getSimpleValueType();
19853 // Just remove no-op shuffle masks.
19854 if (Mask.size() == 1) {
19855 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19860 // Use the float domain if the operand type is a floating point type.
19861 bool FloatDomain = VT.isFloatingPoint();
19863 // For floating point shuffles, we don't have free copies in the shuffle
19864 // instructions or the ability to load as part of the instruction, so
19865 // canonicalize their shuffles to UNPCK or MOV variants.
19867 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19868 // vectors because it can have a load folded into it that UNPCK cannot. This
19869 // doesn't preclude something switching to the shorter encoding post-RA.
19871 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19872 bool Lo = Mask.equals(0, 0);
19875 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19876 // is no slower than UNPCKLPD but has the option to fold the input operand
19877 // into even an unaligned memory load.
19878 if (Lo && Subtarget->hasSSE3()) {
19879 Shuffle = X86ISD::MOVDDUP;
19880 ShuffleVT = MVT::v2f64;
19882 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19883 // than the UNPCK variants.
19884 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19885 ShuffleVT = MVT::v4f32;
19887 if (Depth == 1 && Root->getOpcode() == Shuffle)
19888 return false; // Nothing to do!
19889 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19890 DCI.AddToWorklist(Op.getNode());
19891 if (Shuffle == X86ISD::MOVDDUP)
19892 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19894 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19895 DCI.AddToWorklist(Op.getNode());
19896 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19900 if (Subtarget->hasSSE3() &&
19901 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
19902 bool Lo = Mask.equals(0, 0, 2, 2);
19903 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19904 MVT ShuffleVT = MVT::v4f32;
19905 if (Depth == 1 && Root->getOpcode() == Shuffle)
19906 return false; // Nothing to do!
19907 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19908 DCI.AddToWorklist(Op.getNode());
19909 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19910 DCI.AddToWorklist(Op.getNode());
19911 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19915 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
19916 bool Lo = Mask.equals(0, 0, 1, 1);
19917 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19918 MVT ShuffleVT = MVT::v4f32;
19919 if (Depth == 1 && Root->getOpcode() == Shuffle)
19920 return false; // Nothing to do!
19921 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19922 DCI.AddToWorklist(Op.getNode());
19923 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19924 DCI.AddToWorklist(Op.getNode());
19925 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19931 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19932 // variants as none of these have single-instruction variants that are
19933 // superior to the UNPCK formulation.
19934 if (!FloatDomain &&
19935 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19936 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19937 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19938 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19940 bool Lo = Mask[0] == 0;
19941 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19942 if (Depth == 1 && Root->getOpcode() == Shuffle)
19943 return false; // Nothing to do!
19945 switch (Mask.size()) {
19947 ShuffleVT = MVT::v8i16;
19950 ShuffleVT = MVT::v16i8;
19953 llvm_unreachable("Impossible mask size!");
19955 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19956 DCI.AddToWorklist(Op.getNode());
19957 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19958 DCI.AddToWorklist(Op.getNode());
19959 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19964 // Don't try to re-form single instruction chains under any circumstances now
19965 // that we've done encoding canonicalization for them.
19969 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19970 // can replace them with a single PSHUFB instruction profitably. Intel's
19971 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19972 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19973 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19974 SmallVector<SDValue, 16> PSHUFBMask;
19975 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19976 int Ratio = 16 / Mask.size();
19977 for (unsigned i = 0; i < 16; ++i) {
19978 int M = Mask[i / Ratio] != SM_SentinelZero
19979 ? Ratio * Mask[i / Ratio] + i % Ratio
19981 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19983 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19984 DCI.AddToWorklist(Op.getNode());
19985 SDValue PSHUFBMaskOp =
19986 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19987 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19988 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19989 DCI.AddToWorklist(Op.getNode());
19990 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19995 // Failed to find any combines.
19999 /// \brief Fully generic combining of x86 shuffle instructions.
20001 /// This should be the last combine run over the x86 shuffle instructions. Once
20002 /// they have been fully optimized, this will recursively consider all chains
20003 /// of single-use shuffle instructions, build a generic model of the cumulative
20004 /// shuffle operation, and check for simpler instructions which implement this
20005 /// operation. We use this primarily for two purposes:
20007 /// 1) Collapse generic shuffles to specialized single instructions when
20008 /// equivalent. In most cases, this is just an encoding size win, but
20009 /// sometimes we will collapse multiple generic shuffles into a single
20010 /// special-purpose shuffle.
20011 /// 2) Look for sequences of shuffle instructions with 3 or more total
20012 /// instructions, and replace them with the slightly more expensive SSSE3
20013 /// PSHUFB instruction if available. We do this as the last combining step
20014 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20015 /// a suitable short sequence of other instructions. The PHUFB will either
20016 /// use a register or have to read from memory and so is slightly (but only
20017 /// slightly) more expensive than the other shuffle instructions.
20019 /// Because this is inherently a quadratic operation (for each shuffle in
20020 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20021 /// This should never be an issue in practice as the shuffle lowering doesn't
20022 /// produce sequences of more than 8 instructions.
20024 /// FIXME: We will currently miss some cases where the redundant shuffling
20025 /// would simplify under the threshold for PSHUFB formation because of
20026 /// combine-ordering. To fix this, we should do the redundant instruction
20027 /// combining in this recursive walk.
20028 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20029 ArrayRef<int> RootMask,
20030 int Depth, bool HasPSHUFB,
20032 TargetLowering::DAGCombinerInfo &DCI,
20033 const X86Subtarget *Subtarget) {
20034 // Bound the depth of our recursive combine because this is ultimately
20035 // quadratic in nature.
20039 // Directly rip through bitcasts to find the underlying operand.
20040 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20041 Op = Op.getOperand(0);
20043 MVT VT = Op.getSimpleValueType();
20044 if (!VT.isVector())
20045 return false; // Bail if we hit a non-vector.
20046 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20047 // version should be added.
20048 if (VT.getSizeInBits() != 128)
20051 assert(Root.getSimpleValueType().isVector() &&
20052 "Shuffles operate on vector types!");
20053 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20054 "Can only combine shuffles of the same vector register size.");
20056 if (!isTargetShuffle(Op.getOpcode()))
20058 SmallVector<int, 16> OpMask;
20060 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20061 // We only can combine unary shuffles which we can decode the mask for.
20062 if (!HaveMask || !IsUnary)
20065 assert(VT.getVectorNumElements() == OpMask.size() &&
20066 "Different mask size from vector size!");
20067 assert(((RootMask.size() > OpMask.size() &&
20068 RootMask.size() % OpMask.size() == 0) ||
20069 (OpMask.size() > RootMask.size() &&
20070 OpMask.size() % RootMask.size() == 0) ||
20071 OpMask.size() == RootMask.size()) &&
20072 "The smaller number of elements must divide the larger.");
20073 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20074 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20075 assert(((RootRatio == 1 && OpRatio == 1) ||
20076 (RootRatio == 1) != (OpRatio == 1)) &&
20077 "Must not have a ratio for both incoming and op masks!");
20079 SmallVector<int, 16> Mask;
20080 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20082 // Merge this shuffle operation's mask into our accumulated mask. Note that
20083 // this shuffle's mask will be the first applied to the input, followed by the
20084 // root mask to get us all the way to the root value arrangement. The reason
20085 // for this order is that we are recursing up the operation chain.
20086 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20087 int RootIdx = i / RootRatio;
20088 if (RootMask[RootIdx] == SM_SentinelZero) {
20089 // This is a zero-ed lane, we're done.
20090 Mask.push_back(SM_SentinelZero);
20094 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20095 int OpIdx = RootMaskedIdx / OpRatio;
20096 if (OpMask[OpIdx] == SM_SentinelZero) {
20097 // The incoming lanes are zero, it doesn't matter which ones we are using.
20098 Mask.push_back(SM_SentinelZero);
20102 // Ok, we have non-zero lanes, map them through.
20103 Mask.push_back(OpMask[OpIdx] * OpRatio +
20104 RootMaskedIdx % OpRatio);
20107 // See if we can recurse into the operand to combine more things.
20108 switch (Op.getOpcode()) {
20109 case X86ISD::PSHUFB:
20111 case X86ISD::PSHUFD:
20112 case X86ISD::PSHUFHW:
20113 case X86ISD::PSHUFLW:
20114 if (Op.getOperand(0).hasOneUse() &&
20115 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20116 HasPSHUFB, DAG, DCI, Subtarget))
20120 case X86ISD::UNPCKL:
20121 case X86ISD::UNPCKH:
20122 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20123 // We can't check for single use, we have to check that this shuffle is the only user.
20124 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20125 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20126 HasPSHUFB, DAG, DCI, Subtarget))
20131 // Minor canonicalization of the accumulated shuffle mask to make it easier
20132 // to match below. All this does is detect masks with squential pairs of
20133 // elements, and shrink them to the half-width mask. It does this in a loop
20134 // so it will reduce the size of the mask to the minimal width mask which
20135 // performs an equivalent shuffle.
20136 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20137 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20138 Mask[i] = Mask[2 * i] / 2;
20139 Mask.resize(Mask.size() / 2);
20142 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20146 /// \brief Get the PSHUF-style mask from PSHUF node.
20148 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20149 /// PSHUF-style masks that can be reused with such instructions.
20150 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20151 SmallVector<int, 4> Mask;
20153 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20157 switch (N.getOpcode()) {
20158 case X86ISD::PSHUFD:
20160 case X86ISD::PSHUFLW:
20163 case X86ISD::PSHUFHW:
20164 Mask.erase(Mask.begin(), Mask.begin() + 4);
20165 for (int &M : Mask)
20169 llvm_unreachable("No valid shuffle instruction found!");
20173 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20175 /// We walk up the chain and look for a combinable shuffle, skipping over
20176 /// shuffles that we could hoist this shuffle's transformation past without
20177 /// altering anything.
20179 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20181 TargetLowering::DAGCombinerInfo &DCI) {
20182 assert(N.getOpcode() == X86ISD::PSHUFD &&
20183 "Called with something other than an x86 128-bit half shuffle!");
20186 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20187 // of the shuffles in the chain so that we can form a fresh chain to replace
20189 SmallVector<SDValue, 8> Chain;
20190 SDValue V = N.getOperand(0);
20191 for (; V.hasOneUse(); V = V.getOperand(0)) {
20192 switch (V.getOpcode()) {
20194 return SDValue(); // Nothing combined!
20197 // Skip bitcasts as we always know the type for the target specific
20201 case X86ISD::PSHUFD:
20202 // Found another dword shuffle.
20205 case X86ISD::PSHUFLW:
20206 // Check that the low words (being shuffled) are the identity in the
20207 // dword shuffle, and the high words are self-contained.
20208 if (Mask[0] != 0 || Mask[1] != 1 ||
20209 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20212 Chain.push_back(V);
20215 case X86ISD::PSHUFHW:
20216 // Check that the high words (being shuffled) are the identity in the
20217 // dword shuffle, and the low words are self-contained.
20218 if (Mask[2] != 2 || Mask[3] != 3 ||
20219 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20222 Chain.push_back(V);
20225 case X86ISD::UNPCKL:
20226 case X86ISD::UNPCKH:
20227 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20228 // shuffle into a preceding word shuffle.
20229 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20232 // Search for a half-shuffle which we can combine with.
20233 unsigned CombineOp =
20234 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20235 if (V.getOperand(0) != V.getOperand(1) ||
20236 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20238 Chain.push_back(V);
20239 V = V.getOperand(0);
20241 switch (V.getOpcode()) {
20243 return SDValue(); // Nothing to combine.
20245 case X86ISD::PSHUFLW:
20246 case X86ISD::PSHUFHW:
20247 if (V.getOpcode() == CombineOp)
20250 Chain.push_back(V);
20254 V = V.getOperand(0);
20258 } while (V.hasOneUse());
20261 // Break out of the loop if we break out of the switch.
20265 if (!V.hasOneUse())
20266 // We fell out of the loop without finding a viable combining instruction.
20269 // Merge this node's mask and our incoming mask.
20270 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20271 for (int &M : Mask)
20273 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20274 getV4X86ShuffleImm8ForMask(Mask, DAG));
20276 // Rebuild the chain around this new shuffle.
20277 while (!Chain.empty()) {
20278 SDValue W = Chain.pop_back_val();
20280 if (V.getValueType() != W.getOperand(0).getValueType())
20281 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20283 switch (W.getOpcode()) {
20285 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20287 case X86ISD::UNPCKL:
20288 case X86ISD::UNPCKH:
20289 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20292 case X86ISD::PSHUFD:
20293 case X86ISD::PSHUFLW:
20294 case X86ISD::PSHUFHW:
20295 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20299 if (V.getValueType() != N.getValueType())
20300 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20302 // Return the new chain to replace N.
20306 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20308 /// We walk up the chain, skipping shuffles of the other half and looking
20309 /// through shuffles which switch halves trying to find a shuffle of the same
20310 /// pair of dwords.
20311 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20313 TargetLowering::DAGCombinerInfo &DCI) {
20315 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20316 "Called with something other than an x86 128-bit half shuffle!");
20318 unsigned CombineOpcode = N.getOpcode();
20320 // Walk up a single-use chain looking for a combinable shuffle.
20321 SDValue V = N.getOperand(0);
20322 for (; V.hasOneUse(); V = V.getOperand(0)) {
20323 switch (V.getOpcode()) {
20325 return false; // Nothing combined!
20328 // Skip bitcasts as we always know the type for the target specific
20332 case X86ISD::PSHUFLW:
20333 case X86ISD::PSHUFHW:
20334 if (V.getOpcode() == CombineOpcode)
20337 // Other-half shuffles are no-ops.
20340 // Break out of the loop if we break out of the switch.
20344 if (!V.hasOneUse())
20345 // We fell out of the loop without finding a viable combining instruction.
20348 // Combine away the bottom node as its shuffle will be accumulated into
20349 // a preceding shuffle.
20350 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20352 // Record the old value.
20355 // Merge this node's mask and our incoming mask (adjusted to account for all
20356 // the pshufd instructions encountered).
20357 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20358 for (int &M : Mask)
20360 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20361 getV4X86ShuffleImm8ForMask(Mask, DAG));
20363 // Check that the shuffles didn't cancel each other out. If not, we need to
20364 // combine to the new one.
20366 // Replace the combinable shuffle with the combined one, updating all users
20367 // so that we re-evaluate the chain here.
20368 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20373 /// \brief Try to combine x86 target specific shuffles.
20374 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20375 TargetLowering::DAGCombinerInfo &DCI,
20376 const X86Subtarget *Subtarget) {
20378 MVT VT = N.getSimpleValueType();
20379 SmallVector<int, 4> Mask;
20381 switch (N.getOpcode()) {
20382 case X86ISD::PSHUFD:
20383 case X86ISD::PSHUFLW:
20384 case X86ISD::PSHUFHW:
20385 Mask = getPSHUFShuffleMask(N);
20386 assert(Mask.size() == 4);
20392 // Nuke no-op shuffles that show up after combining.
20393 if (isNoopShuffleMask(Mask))
20394 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20396 // Look for simplifications involving one or two shuffle instructions.
20397 SDValue V = N.getOperand(0);
20398 switch (N.getOpcode()) {
20401 case X86ISD::PSHUFLW:
20402 case X86ISD::PSHUFHW:
20403 assert(VT == MVT::v8i16);
20406 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20407 return SDValue(); // We combined away this shuffle, so we're done.
20409 // See if this reduces to a PSHUFD which is no more expensive and can
20410 // combine with more operations.
20411 if (canWidenShuffleElements(Mask)) {
20412 int DMask[] = {-1, -1, -1, -1};
20413 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20414 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20415 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20416 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20417 DCI.AddToWorklist(V.getNode());
20418 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20419 getV4X86ShuffleImm8ForMask(DMask, DAG));
20420 DCI.AddToWorklist(V.getNode());
20421 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20424 // Look for shuffle patterns which can be implemented as a single unpack.
20425 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20426 // only works when we have a PSHUFD followed by two half-shuffles.
20427 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20428 (V.getOpcode() == X86ISD::PSHUFLW ||
20429 V.getOpcode() == X86ISD::PSHUFHW) &&
20430 V.getOpcode() != N.getOpcode() &&
20432 SDValue D = V.getOperand(0);
20433 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20434 D = D.getOperand(0);
20435 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20436 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20437 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20438 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20439 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20441 for (int i = 0; i < 4; ++i) {
20442 WordMask[i + NOffset] = Mask[i] + NOffset;
20443 WordMask[i + VOffset] = VMask[i] + VOffset;
20445 // Map the word mask through the DWord mask.
20447 for (int i = 0; i < 8; ++i)
20448 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20449 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20450 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20451 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20452 std::begin(UnpackLoMask)) ||
20453 std::equal(std::begin(MappedMask), std::end(MappedMask),
20454 std::begin(UnpackHiMask))) {
20455 // We can replace all three shuffles with an unpack.
20456 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20457 DCI.AddToWorklist(V.getNode());
20458 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20460 DL, MVT::v8i16, V, V);
20467 case X86ISD::PSHUFD:
20468 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20477 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20479 /// We combine this directly on the abstract vector shuffle nodes so it is
20480 /// easier to generically match. We also insert dummy vector shuffle nodes for
20481 /// the operands which explicitly discard the lanes which are unused by this
20482 /// operation to try to flow through the rest of the combiner the fact that
20483 /// they're unused.
20484 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20486 EVT VT = N->getValueType(0);
20488 // We only handle target-independent shuffles.
20489 // FIXME: It would be easy and harmless to use the target shuffle mask
20490 // extraction tool to support more.
20491 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20494 auto *SVN = cast<ShuffleVectorSDNode>(N);
20495 ArrayRef<int> Mask = SVN->getMask();
20496 SDValue V1 = N->getOperand(0);
20497 SDValue V2 = N->getOperand(1);
20499 // We require the first shuffle operand to be the SUB node, and the second to
20500 // be the ADD node.
20501 // FIXME: We should support the commuted patterns.
20502 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20505 // If there are other uses of these operations we can't fold them.
20506 if (!V1->hasOneUse() || !V2->hasOneUse())
20509 // Ensure that both operations have the same operands. Note that we can
20510 // commute the FADD operands.
20511 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20512 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20513 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20516 // We're looking for blends between FADD and FSUB nodes. We insist on these
20517 // nodes being lined up in a specific expected pattern.
20518 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20519 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20520 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20523 // Only specific types are legal at this point, assert so we notice if and
20524 // when these change.
20525 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20526 VT == MVT::v4f64) &&
20527 "Unknown vector type encountered!");
20529 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20532 /// PerformShuffleCombine - Performs several different shuffle combines.
20533 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20534 TargetLowering::DAGCombinerInfo &DCI,
20535 const X86Subtarget *Subtarget) {
20537 SDValue N0 = N->getOperand(0);
20538 SDValue N1 = N->getOperand(1);
20539 EVT VT = N->getValueType(0);
20541 // Don't create instructions with illegal types after legalize types has run.
20542 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20543 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20546 // If we have legalized the vector types, look for blends of FADD and FSUB
20547 // nodes that we can fuse into an ADDSUB node.
20548 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20549 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20552 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20553 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20554 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20555 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20557 // During Type Legalization, when promoting illegal vector types,
20558 // the backend might introduce new shuffle dag nodes and bitcasts.
20560 // This code performs the following transformation:
20561 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20562 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20564 // We do this only if both the bitcast and the BINOP dag nodes have
20565 // one use. Also, perform this transformation only if the new binary
20566 // operation is legal. This is to avoid introducing dag nodes that
20567 // potentially need to be further expanded (or custom lowered) into a
20568 // less optimal sequence of dag nodes.
20569 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20570 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20571 N0.getOpcode() == ISD::BITCAST) {
20572 SDValue BC0 = N0.getOperand(0);
20573 EVT SVT = BC0.getValueType();
20574 unsigned Opcode = BC0.getOpcode();
20575 unsigned NumElts = VT.getVectorNumElements();
20577 if (BC0.hasOneUse() && SVT.isVector() &&
20578 SVT.getVectorNumElements() * 2 == NumElts &&
20579 TLI.isOperationLegal(Opcode, VT)) {
20580 bool CanFold = false;
20592 unsigned SVTNumElts = SVT.getVectorNumElements();
20593 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20594 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20595 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20596 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20597 CanFold = SVOp->getMaskElt(i) < 0;
20600 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20601 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20602 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20603 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20608 // Only handle 128 wide vector from here on.
20609 if (!VT.is128BitVector())
20612 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20613 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20614 // consecutive, non-overlapping, and in the right order.
20615 SmallVector<SDValue, 16> Elts;
20616 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20617 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20619 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20623 if (isTargetShuffle(N->getOpcode())) {
20625 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20626 if (Shuffle.getNode())
20629 // Try recursively combining arbitrary sequences of x86 shuffle
20630 // instructions into higher-order shuffles. We do this after combining
20631 // specific PSHUF instruction sequences into their minimal form so that we
20632 // can evaluate how many specialized shuffle instructions are involved in
20633 // a particular chain.
20634 SmallVector<int, 1> NonceMask; // Just a placeholder.
20635 NonceMask.push_back(0);
20636 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20637 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20639 return SDValue(); // This routine will use CombineTo to replace N.
20645 /// PerformTruncateCombine - Converts truncate operation to
20646 /// a sequence of vector shuffle operations.
20647 /// It is possible when we truncate 256-bit vector to 128-bit vector
20648 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20649 TargetLowering::DAGCombinerInfo &DCI,
20650 const X86Subtarget *Subtarget) {
20654 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20655 /// specific shuffle of a load can be folded into a single element load.
20656 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20657 /// shuffles have been customed lowered so we need to handle those here.
20658 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20659 TargetLowering::DAGCombinerInfo &DCI) {
20660 if (DCI.isBeforeLegalizeOps())
20663 SDValue InVec = N->getOperand(0);
20664 SDValue EltNo = N->getOperand(1);
20666 if (!isa<ConstantSDNode>(EltNo))
20669 EVT VT = InVec.getValueType();
20671 if (InVec.getOpcode() == ISD::BITCAST) {
20672 // Don't duplicate a load with other uses.
20673 if (!InVec.hasOneUse())
20675 EVT BCVT = InVec.getOperand(0).getValueType();
20676 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20678 InVec = InVec.getOperand(0);
20681 if (!isTargetShuffle(InVec.getOpcode()))
20684 // Don't duplicate a load with other uses.
20685 if (!InVec.hasOneUse())
20688 SmallVector<int, 16> ShuffleMask;
20690 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20694 // Select the input vector, guarding against out of range extract vector.
20695 unsigned NumElems = VT.getVectorNumElements();
20696 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20697 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20698 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20699 : InVec.getOperand(1);
20701 // If inputs to shuffle are the same for both ops, then allow 2 uses
20702 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20704 if (LdNode.getOpcode() == ISD::BITCAST) {
20705 // Don't duplicate a load with other uses.
20706 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20709 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20710 LdNode = LdNode.getOperand(0);
20713 if (!ISD::isNormalLoad(LdNode.getNode()))
20716 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20718 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20721 EVT EltVT = N->getValueType(0);
20722 // If there's a bitcast before the shuffle, check if the load type and
20723 // alignment is valid.
20724 unsigned Align = LN0->getAlignment();
20725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20726 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20727 EltVT.getTypeForEVT(*DAG.getContext()));
20729 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20732 // All checks match so transform back to vector_shuffle so that DAG combiner
20733 // can finish the job
20736 // Create shuffle node taking into account the case that its a unary shuffle
20737 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20738 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20739 InVec.getOperand(0), Shuffle,
20741 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20742 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20746 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20747 /// generation and convert it from being a bunch of shuffles and extracts
20748 /// to a simple store and scalar loads to extract the elements.
20749 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20750 TargetLowering::DAGCombinerInfo &DCI) {
20751 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20752 if (NewOp.getNode())
20755 SDValue InputVector = N->getOperand(0);
20757 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20758 // from mmx to v2i32 has a single usage.
20759 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20760 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20761 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20762 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20763 N->getValueType(0),
20764 InputVector.getNode()->getOperand(0));
20766 // Only operate on vectors of 4 elements, where the alternative shuffling
20767 // gets to be more expensive.
20768 if (InputVector.getValueType() != MVT::v4i32)
20771 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20772 // single use which is a sign-extend or zero-extend, and all elements are
20774 SmallVector<SDNode *, 4> Uses;
20775 unsigned ExtractedElements = 0;
20776 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20777 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20778 if (UI.getUse().getResNo() != InputVector.getResNo())
20781 SDNode *Extract = *UI;
20782 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20785 if (Extract->getValueType(0) != MVT::i32)
20787 if (!Extract->hasOneUse())
20789 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20790 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20792 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20795 // Record which element was extracted.
20796 ExtractedElements |=
20797 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20799 Uses.push_back(Extract);
20802 // If not all the elements were used, this may not be worthwhile.
20803 if (ExtractedElements != 15)
20806 // Ok, we've now decided to do the transformation.
20807 SDLoc dl(InputVector);
20809 // Store the value to a temporary stack slot.
20810 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20811 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20812 MachinePointerInfo(), false, false, 0);
20814 // Replace each use (extract) with a load of the appropriate element.
20815 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20816 UE = Uses.end(); UI != UE; ++UI) {
20817 SDNode *Extract = *UI;
20819 // cOMpute the element's address.
20820 SDValue Idx = Extract->getOperand(1);
20822 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20823 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20824 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20825 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20827 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20828 StackPtr, OffsetVal);
20830 // Load the scalar.
20831 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20832 ScalarAddr, MachinePointerInfo(),
20833 false, false, false, 0);
20835 // Replace the exact with the load.
20836 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20839 // The replacement was made in place; don't return anything.
20843 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20844 static std::pair<unsigned, bool>
20845 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20846 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20847 if (!VT.isVector())
20848 return std::make_pair(0, false);
20850 bool NeedSplit = false;
20851 switch (VT.getSimpleVT().SimpleTy) {
20852 default: return std::make_pair(0, false);
20856 if (!Subtarget->hasAVX2())
20858 if (!Subtarget->hasAVX())
20859 return std::make_pair(0, false);
20864 if (!Subtarget->hasSSE2())
20865 return std::make_pair(0, false);
20868 // SSE2 has only a small subset of the operations.
20869 bool hasUnsigned = Subtarget->hasSSE41() ||
20870 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20871 bool hasSigned = Subtarget->hasSSE41() ||
20872 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20874 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20877 // Check for x CC y ? x : y.
20878 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20879 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20884 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20887 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20890 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20893 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20895 // Check for x CC y ? y : x -- a min/max with reversed arms.
20896 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20897 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20902 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20905 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20908 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20911 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20915 return std::make_pair(Opc, NeedSplit);
20919 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20920 const X86Subtarget *Subtarget) {
20922 SDValue Cond = N->getOperand(0);
20923 SDValue LHS = N->getOperand(1);
20924 SDValue RHS = N->getOperand(2);
20926 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20927 SDValue CondSrc = Cond->getOperand(0);
20928 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20929 Cond = CondSrc->getOperand(0);
20932 MVT VT = N->getSimpleValueType(0);
20933 MVT EltVT = VT.getVectorElementType();
20934 unsigned NumElems = VT.getVectorNumElements();
20935 // There is no blend with immediate in AVX-512.
20936 if (VT.is512BitVector())
20939 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20941 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20944 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20947 // A vselect where all conditions and data are constants can be optimized into
20948 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20949 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20950 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20953 unsigned MaskValue = 0;
20954 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20957 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20958 for (unsigned i = 0; i < NumElems; ++i) {
20959 // Be sure we emit undef where we can.
20960 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20961 ShuffleMask[i] = -1;
20963 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20966 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20969 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20971 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20972 TargetLowering::DAGCombinerInfo &DCI,
20973 const X86Subtarget *Subtarget) {
20975 SDValue Cond = N->getOperand(0);
20976 // Get the LHS/RHS of the select.
20977 SDValue LHS = N->getOperand(1);
20978 SDValue RHS = N->getOperand(2);
20979 EVT VT = LHS.getValueType();
20980 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20982 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20983 // instructions match the semantics of the common C idiom x<y?x:y but not
20984 // x<=y?x:y, because of how they handle negative zero (which can be
20985 // ignored in unsafe-math mode).
20986 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20987 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20988 (Subtarget->hasSSE2() ||
20989 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20990 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20992 unsigned Opcode = 0;
20993 // Check for x CC y ? x : y.
20994 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20995 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20999 // Converting this to a min would handle NaNs incorrectly, and swapping
21000 // the operands would cause it to handle comparisons between positive
21001 // and negative zero incorrectly.
21002 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21003 if (!DAG.getTarget().Options.UnsafeFPMath &&
21004 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21006 std::swap(LHS, RHS);
21008 Opcode = X86ISD::FMIN;
21011 // Converting this to a min would handle comparisons between positive
21012 // and negative zero incorrectly.
21013 if (!DAG.getTarget().Options.UnsafeFPMath &&
21014 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21016 Opcode = X86ISD::FMIN;
21019 // Converting this to a min would handle both negative zeros and NaNs
21020 // incorrectly, but we can swap the operands to fix both.
21021 std::swap(LHS, RHS);
21025 Opcode = X86ISD::FMIN;
21029 // Converting this to a max would handle comparisons between positive
21030 // and negative zero incorrectly.
21031 if (!DAG.getTarget().Options.UnsafeFPMath &&
21032 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21034 Opcode = X86ISD::FMAX;
21037 // Converting this to a max would handle NaNs incorrectly, and swapping
21038 // the operands would cause it to handle comparisons between positive
21039 // and negative zero incorrectly.
21040 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21041 if (!DAG.getTarget().Options.UnsafeFPMath &&
21042 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21044 std::swap(LHS, RHS);
21046 Opcode = X86ISD::FMAX;
21049 // Converting this to a max would handle both negative zeros and NaNs
21050 // incorrectly, but we can swap the operands to fix both.
21051 std::swap(LHS, RHS);
21055 Opcode = X86ISD::FMAX;
21058 // Check for x CC y ? y : x -- a min/max with reversed arms.
21059 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21060 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21064 // Converting this to a min would handle comparisons between positive
21065 // and negative zero incorrectly, and swapping the operands would
21066 // cause it to handle NaNs incorrectly.
21067 if (!DAG.getTarget().Options.UnsafeFPMath &&
21068 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21069 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21071 std::swap(LHS, RHS);
21073 Opcode = X86ISD::FMIN;
21076 // Converting this to a min would handle NaNs incorrectly.
21077 if (!DAG.getTarget().Options.UnsafeFPMath &&
21078 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21080 Opcode = X86ISD::FMIN;
21083 // Converting this to a min would handle both negative zeros and NaNs
21084 // incorrectly, but we can swap the operands to fix both.
21085 std::swap(LHS, RHS);
21089 Opcode = X86ISD::FMIN;
21093 // Converting this to a max would handle NaNs incorrectly.
21094 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21096 Opcode = X86ISD::FMAX;
21099 // Converting this to a max would handle comparisons between positive
21100 // and negative zero incorrectly, and swapping the operands would
21101 // cause it to handle NaNs incorrectly.
21102 if (!DAG.getTarget().Options.UnsafeFPMath &&
21103 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21104 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21106 std::swap(LHS, RHS);
21108 Opcode = X86ISD::FMAX;
21111 // Converting this to a max would handle both negative zeros and NaNs
21112 // incorrectly, but we can swap the operands to fix both.
21113 std::swap(LHS, RHS);
21117 Opcode = X86ISD::FMAX;
21123 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21126 EVT CondVT = Cond.getValueType();
21127 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21128 CondVT.getVectorElementType() == MVT::i1) {
21129 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21130 // lowering on KNL. In this case we convert it to
21131 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21132 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21133 // Since SKX these selects have a proper lowering.
21134 EVT OpVT = LHS.getValueType();
21135 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21136 (OpVT.getVectorElementType() == MVT::i8 ||
21137 OpVT.getVectorElementType() == MVT::i16) &&
21138 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21139 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21140 DCI.AddToWorklist(Cond.getNode());
21141 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21144 // If this is a select between two integer constants, try to do some
21146 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21147 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21148 // Don't do this for crazy integer types.
21149 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21150 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21151 // so that TrueC (the true value) is larger than FalseC.
21152 bool NeedsCondInvert = false;
21154 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21155 // Efficiently invertible.
21156 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21157 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21158 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21159 NeedsCondInvert = true;
21160 std::swap(TrueC, FalseC);
21163 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21164 if (FalseC->getAPIntValue() == 0 &&
21165 TrueC->getAPIntValue().isPowerOf2()) {
21166 if (NeedsCondInvert) // Invert the condition if needed.
21167 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21168 DAG.getConstant(1, Cond.getValueType()));
21170 // Zero extend the condition if needed.
21171 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21173 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21174 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21175 DAG.getConstant(ShAmt, MVT::i8));
21178 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21179 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21180 if (NeedsCondInvert) // Invert the condition if needed.
21181 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21182 DAG.getConstant(1, Cond.getValueType()));
21184 // Zero extend the condition if needed.
21185 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21186 FalseC->getValueType(0), Cond);
21187 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21188 SDValue(FalseC, 0));
21191 // Optimize cases that will turn into an LEA instruction. This requires
21192 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21193 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21194 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21195 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21197 bool isFastMultiplier = false;
21199 switch ((unsigned char)Diff) {
21201 case 1: // result = add base, cond
21202 case 2: // result = lea base( , cond*2)
21203 case 3: // result = lea base(cond, cond*2)
21204 case 4: // result = lea base( , cond*4)
21205 case 5: // result = lea base(cond, cond*4)
21206 case 8: // result = lea base( , cond*8)
21207 case 9: // result = lea base(cond, cond*8)
21208 isFastMultiplier = true;
21213 if (isFastMultiplier) {
21214 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21215 if (NeedsCondInvert) // Invert the condition if needed.
21216 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21217 DAG.getConstant(1, Cond.getValueType()));
21219 // Zero extend the condition if needed.
21220 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21222 // Scale the condition by the difference.
21224 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21225 DAG.getConstant(Diff, Cond.getValueType()));
21227 // Add the base if non-zero.
21228 if (FalseC->getAPIntValue() != 0)
21229 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21230 SDValue(FalseC, 0));
21237 // Canonicalize max and min:
21238 // (x > y) ? x : y -> (x >= y) ? x : y
21239 // (x < y) ? x : y -> (x <= y) ? x : y
21240 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21241 // the need for an extra compare
21242 // against zero. e.g.
21243 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21245 // testl %edi, %edi
21247 // cmovgl %edi, %eax
21251 // cmovsl %eax, %edi
21252 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21253 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21254 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21255 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21260 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21261 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21262 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21263 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21268 // Early exit check
21269 if (!TLI.isTypeLegal(VT))
21272 // Match VSELECTs into subs with unsigned saturation.
21273 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21274 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21275 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21276 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21277 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21279 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21280 // left side invert the predicate to simplify logic below.
21282 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21284 CC = ISD::getSetCCInverse(CC, true);
21285 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21289 if (Other.getNode() && Other->getNumOperands() == 2 &&
21290 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21291 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21292 SDValue CondRHS = Cond->getOperand(1);
21294 // Look for a general sub with unsigned saturation first.
21295 // x >= y ? x-y : 0 --> subus x, y
21296 // x > y ? x-y : 0 --> subus x, y
21297 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21298 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21299 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21301 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21302 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21303 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21304 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21305 // If the RHS is a constant we have to reverse the const
21306 // canonicalization.
21307 // x > C-1 ? x+-C : 0 --> subus x, C
21308 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21309 CondRHSConst->getAPIntValue() ==
21310 (-OpRHSConst->getAPIntValue() - 1))
21311 return DAG.getNode(
21312 X86ISD::SUBUS, DL, VT, OpLHS,
21313 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21315 // Another special case: If C was a sign bit, the sub has been
21316 // canonicalized into a xor.
21317 // FIXME: Would it be better to use computeKnownBits to determine
21318 // whether it's safe to decanonicalize the xor?
21319 // x s< 0 ? x^C : 0 --> subus x, C
21320 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21321 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21322 OpRHSConst->getAPIntValue().isSignBit())
21323 // Note that we have to rebuild the RHS constant here to ensure we
21324 // don't rely on particular values of undef lanes.
21325 return DAG.getNode(
21326 X86ISD::SUBUS, DL, VT, OpLHS,
21327 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21332 // Try to match a min/max vector operation.
21333 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21334 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21335 unsigned Opc = ret.first;
21336 bool NeedSplit = ret.second;
21338 if (Opc && NeedSplit) {
21339 unsigned NumElems = VT.getVectorNumElements();
21340 // Extract the LHS vectors
21341 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21342 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21344 // Extract the RHS vectors
21345 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21346 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21348 // Create min/max for each subvector
21349 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21350 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21352 // Merge the result
21353 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21355 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21358 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21359 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21360 // Check if SETCC has already been promoted
21361 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21362 // Check that condition value type matches vselect operand type
21365 assert(Cond.getValueType().isVector() &&
21366 "vector select expects a vector selector!");
21368 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21369 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21371 if (!TValIsAllOnes && !FValIsAllZeros) {
21372 // Try invert the condition if true value is not all 1s and false value
21374 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21375 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21377 if (TValIsAllZeros || FValIsAllOnes) {
21378 SDValue CC = Cond.getOperand(2);
21379 ISD::CondCode NewCC =
21380 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21381 Cond.getOperand(0).getValueType().isInteger());
21382 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21383 std::swap(LHS, RHS);
21384 TValIsAllOnes = FValIsAllOnes;
21385 FValIsAllZeros = TValIsAllZeros;
21389 if (TValIsAllOnes || FValIsAllZeros) {
21392 if (TValIsAllOnes && FValIsAllZeros)
21394 else if (TValIsAllOnes)
21395 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21396 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21397 else if (FValIsAllZeros)
21398 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21399 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21401 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21405 // Try to fold this VSELECT into a MOVSS/MOVSD
21406 if (N->getOpcode() == ISD::VSELECT &&
21407 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21408 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21409 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21410 bool CanFold = false;
21411 unsigned NumElems = Cond.getNumOperands();
21415 if (isZero(Cond.getOperand(0))) {
21418 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21419 // fold (vselect <0,-1> -> (movsd A, B)
21420 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21421 CanFold = isAllOnes(Cond.getOperand(i));
21422 } else if (isAllOnes(Cond.getOperand(0))) {
21426 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21427 // fold (vselect <-1,0> -> (movsd B, A)
21428 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21429 CanFold = isZero(Cond.getOperand(i));
21433 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21434 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21435 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21438 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21439 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21440 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21441 // (v2i64 (bitcast B)))))
21443 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21444 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21445 // (v2f64 (bitcast B)))))
21447 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21448 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21449 // (v2i64 (bitcast A)))))
21451 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21452 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21453 // (v2f64 (bitcast A)))))
21455 CanFold = (isZero(Cond.getOperand(0)) &&
21456 isZero(Cond.getOperand(1)) &&
21457 isAllOnes(Cond.getOperand(2)) &&
21458 isAllOnes(Cond.getOperand(3)));
21460 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21461 isAllOnes(Cond.getOperand(1)) &&
21462 isZero(Cond.getOperand(2)) &&
21463 isZero(Cond.getOperand(3))) {
21465 std::swap(LHS, RHS);
21469 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21470 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21471 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21472 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21474 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21480 // If we know that this node is legal then we know that it is going to be
21481 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21482 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21483 // to simplify previous instructions.
21484 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21485 !DCI.isBeforeLegalize() &&
21486 // We explicitly check against v8i16 and v16i16 because, although
21487 // they're marked as Custom, they might only be legal when Cond is a
21488 // build_vector of constants. This will be taken care in a later
21490 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21491 VT != MVT::v8i16)) {
21492 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21494 // Don't optimize vector selects that map to mask-registers.
21498 // Check all uses of that condition operand to check whether it will be
21499 // consumed by non-BLEND instructions, which may depend on all bits are set
21501 for (SDNode::use_iterator I = Cond->use_begin(),
21502 E = Cond->use_end(); I != E; ++I)
21503 if (I->getOpcode() != ISD::VSELECT)
21504 // TODO: Add other opcodes eventually lowered into BLEND.
21507 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21508 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21510 APInt KnownZero, KnownOne;
21511 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21512 DCI.isBeforeLegalizeOps());
21513 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21514 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21515 DCI.CommitTargetLoweringOpt(TLO);
21518 // We should generate an X86ISD::BLENDI from a vselect if its argument
21519 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21520 // constants. This specific pattern gets generated when we split a
21521 // selector for a 512 bit vector in a machine without AVX512 (but with
21522 // 256-bit vectors), during legalization:
21524 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21526 // Iff we find this pattern and the build_vectors are built from
21527 // constants, we translate the vselect into a shuffle_vector that we
21528 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21529 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21530 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21531 if (Shuffle.getNode())
21538 // Check whether a boolean test is testing a boolean value generated by
21539 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21542 // Simplify the following patterns:
21543 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21544 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21545 // to (Op EFLAGS Cond)
21547 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21548 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21549 // to (Op EFLAGS !Cond)
21551 // where Op could be BRCOND or CMOV.
21553 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21554 // Quit if not CMP and SUB with its value result used.
21555 if (Cmp.getOpcode() != X86ISD::CMP &&
21556 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21559 // Quit if not used as a boolean value.
21560 if (CC != X86::COND_E && CC != X86::COND_NE)
21563 // Check CMP operands. One of them should be 0 or 1 and the other should be
21564 // an SetCC or extended from it.
21565 SDValue Op1 = Cmp.getOperand(0);
21566 SDValue Op2 = Cmp.getOperand(1);
21569 const ConstantSDNode* C = nullptr;
21570 bool needOppositeCond = (CC == X86::COND_E);
21571 bool checkAgainstTrue = false; // Is it a comparison against 1?
21573 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21575 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21577 else // Quit if all operands are not constants.
21580 if (C->getZExtValue() == 1) {
21581 needOppositeCond = !needOppositeCond;
21582 checkAgainstTrue = true;
21583 } else if (C->getZExtValue() != 0)
21584 // Quit if the constant is neither 0 or 1.
21587 bool truncatedToBoolWithAnd = false;
21588 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21589 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21590 SetCC.getOpcode() == ISD::TRUNCATE ||
21591 SetCC.getOpcode() == ISD::AND) {
21592 if (SetCC.getOpcode() == ISD::AND) {
21594 ConstantSDNode *CS;
21595 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21596 CS->getZExtValue() == 1)
21598 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21599 CS->getZExtValue() == 1)
21603 SetCC = SetCC.getOperand(OpIdx);
21604 truncatedToBoolWithAnd = true;
21606 SetCC = SetCC.getOperand(0);
21609 switch (SetCC.getOpcode()) {
21610 case X86ISD::SETCC_CARRY:
21611 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21612 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21613 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21614 // truncated to i1 using 'and'.
21615 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21617 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21618 "Invalid use of SETCC_CARRY!");
21620 case X86ISD::SETCC:
21621 // Set the condition code or opposite one if necessary.
21622 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21623 if (needOppositeCond)
21624 CC = X86::GetOppositeBranchCondition(CC);
21625 return SetCC.getOperand(1);
21626 case X86ISD::CMOV: {
21627 // Check whether false/true value has canonical one, i.e. 0 or 1.
21628 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21629 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21630 // Quit if true value is not a constant.
21633 // Quit if false value is not a constant.
21635 SDValue Op = SetCC.getOperand(0);
21636 // Skip 'zext' or 'trunc' node.
21637 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21638 Op.getOpcode() == ISD::TRUNCATE)
21639 Op = Op.getOperand(0);
21640 // A special case for rdrand/rdseed, where 0 is set if false cond is
21642 if ((Op.getOpcode() != X86ISD::RDRAND &&
21643 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21646 // Quit if false value is not the constant 0 or 1.
21647 bool FValIsFalse = true;
21648 if (FVal && FVal->getZExtValue() != 0) {
21649 if (FVal->getZExtValue() != 1)
21651 // If FVal is 1, opposite cond is needed.
21652 needOppositeCond = !needOppositeCond;
21653 FValIsFalse = false;
21655 // Quit if TVal is not the constant opposite of FVal.
21656 if (FValIsFalse && TVal->getZExtValue() != 1)
21658 if (!FValIsFalse && TVal->getZExtValue() != 0)
21660 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21661 if (needOppositeCond)
21662 CC = X86::GetOppositeBranchCondition(CC);
21663 return SetCC.getOperand(3);
21670 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21671 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21672 TargetLowering::DAGCombinerInfo &DCI,
21673 const X86Subtarget *Subtarget) {
21676 // If the flag operand isn't dead, don't touch this CMOV.
21677 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21680 SDValue FalseOp = N->getOperand(0);
21681 SDValue TrueOp = N->getOperand(1);
21682 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21683 SDValue Cond = N->getOperand(3);
21685 if (CC == X86::COND_E || CC == X86::COND_NE) {
21686 switch (Cond.getOpcode()) {
21690 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21691 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21692 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21698 Flags = checkBoolTestSetCCCombine(Cond, CC);
21699 if (Flags.getNode() &&
21700 // Extra check as FCMOV only supports a subset of X86 cond.
21701 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21702 SDValue Ops[] = { FalseOp, TrueOp,
21703 DAG.getConstant(CC, MVT::i8), Flags };
21704 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21707 // If this is a select between two integer constants, try to do some
21708 // optimizations. Note that the operands are ordered the opposite of SELECT
21710 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21711 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21712 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21713 // larger than FalseC (the false value).
21714 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21715 CC = X86::GetOppositeBranchCondition(CC);
21716 std::swap(TrueC, FalseC);
21717 std::swap(TrueOp, FalseOp);
21720 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21721 // This is efficient for any integer data type (including i8/i16) and
21723 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21724 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21725 DAG.getConstant(CC, MVT::i8), Cond);
21727 // Zero extend the condition if needed.
21728 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21730 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21731 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21732 DAG.getConstant(ShAmt, MVT::i8));
21733 if (N->getNumValues() == 2) // Dead flag value?
21734 return DCI.CombineTo(N, Cond, SDValue());
21738 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21739 // for any integer data type, including i8/i16.
21740 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21741 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21742 DAG.getConstant(CC, MVT::i8), Cond);
21744 // Zero extend the condition if needed.
21745 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21746 FalseC->getValueType(0), Cond);
21747 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21748 SDValue(FalseC, 0));
21750 if (N->getNumValues() == 2) // Dead flag value?
21751 return DCI.CombineTo(N, Cond, SDValue());
21755 // Optimize cases that will turn into an LEA instruction. This requires
21756 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21757 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21758 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21759 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21761 bool isFastMultiplier = false;
21763 switch ((unsigned char)Diff) {
21765 case 1: // result = add base, cond
21766 case 2: // result = lea base( , cond*2)
21767 case 3: // result = lea base(cond, cond*2)
21768 case 4: // result = lea base( , cond*4)
21769 case 5: // result = lea base(cond, cond*4)
21770 case 8: // result = lea base( , cond*8)
21771 case 9: // result = lea base(cond, cond*8)
21772 isFastMultiplier = true;
21777 if (isFastMultiplier) {
21778 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21779 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21780 DAG.getConstant(CC, MVT::i8), Cond);
21781 // Zero extend the condition if needed.
21782 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21784 // Scale the condition by the difference.
21786 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21787 DAG.getConstant(Diff, Cond.getValueType()));
21789 // Add the base if non-zero.
21790 if (FalseC->getAPIntValue() != 0)
21791 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21792 SDValue(FalseC, 0));
21793 if (N->getNumValues() == 2) // Dead flag value?
21794 return DCI.CombineTo(N, Cond, SDValue());
21801 // Handle these cases:
21802 // (select (x != c), e, c) -> select (x != c), e, x),
21803 // (select (x == c), c, e) -> select (x == c), x, e)
21804 // where the c is an integer constant, and the "select" is the combination
21805 // of CMOV and CMP.
21807 // The rationale for this change is that the conditional-move from a constant
21808 // needs two instructions, however, conditional-move from a register needs
21809 // only one instruction.
21811 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21812 // some instruction-combining opportunities. This opt needs to be
21813 // postponed as late as possible.
21815 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21816 // the DCI.xxxx conditions are provided to postpone the optimization as
21817 // late as possible.
21819 ConstantSDNode *CmpAgainst = nullptr;
21820 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21821 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21822 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21824 if (CC == X86::COND_NE &&
21825 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21826 CC = X86::GetOppositeBranchCondition(CC);
21827 std::swap(TrueOp, FalseOp);
21830 if (CC == X86::COND_E &&
21831 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21832 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21833 DAG.getConstant(CC, MVT::i8), Cond };
21834 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21842 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21843 const X86Subtarget *Subtarget) {
21844 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21846 default: return SDValue();
21847 // SSE/AVX/AVX2 blend intrinsics.
21848 case Intrinsic::x86_avx2_pblendvb:
21849 case Intrinsic::x86_avx2_pblendw:
21850 case Intrinsic::x86_avx2_pblendd_128:
21851 case Intrinsic::x86_avx2_pblendd_256:
21852 // Don't try to simplify this intrinsic if we don't have AVX2.
21853 if (!Subtarget->hasAVX2())
21856 case Intrinsic::x86_avx_blend_pd_256:
21857 case Intrinsic::x86_avx_blend_ps_256:
21858 case Intrinsic::x86_avx_blendv_pd_256:
21859 case Intrinsic::x86_avx_blendv_ps_256:
21860 // Don't try to simplify this intrinsic if we don't have AVX.
21861 if (!Subtarget->hasAVX())
21864 case Intrinsic::x86_sse41_pblendw:
21865 case Intrinsic::x86_sse41_blendpd:
21866 case Intrinsic::x86_sse41_blendps:
21867 case Intrinsic::x86_sse41_blendvps:
21868 case Intrinsic::x86_sse41_blendvpd:
21869 case Intrinsic::x86_sse41_pblendvb: {
21870 SDValue Op0 = N->getOperand(1);
21871 SDValue Op1 = N->getOperand(2);
21872 SDValue Mask = N->getOperand(3);
21874 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21875 if (!Subtarget->hasSSE41())
21878 // fold (blend A, A, Mask) -> A
21881 // fold (blend A, B, allZeros) -> A
21882 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21884 // fold (blend A, B, allOnes) -> B
21885 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21888 // Simplify the case where the mask is a constant i32 value.
21889 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21890 if (C->isNullValue())
21892 if (C->isAllOnesValue())
21899 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21900 case Intrinsic::x86_sse2_psrai_w:
21901 case Intrinsic::x86_sse2_psrai_d:
21902 case Intrinsic::x86_avx2_psrai_w:
21903 case Intrinsic::x86_avx2_psrai_d:
21904 case Intrinsic::x86_sse2_psra_w:
21905 case Intrinsic::x86_sse2_psra_d:
21906 case Intrinsic::x86_avx2_psra_w:
21907 case Intrinsic::x86_avx2_psra_d: {
21908 SDValue Op0 = N->getOperand(1);
21909 SDValue Op1 = N->getOperand(2);
21910 EVT VT = Op0.getValueType();
21911 assert(VT.isVector() && "Expected a vector type!");
21913 if (isa<BuildVectorSDNode>(Op1))
21914 Op1 = Op1.getOperand(0);
21916 if (!isa<ConstantSDNode>(Op1))
21919 EVT SVT = VT.getVectorElementType();
21920 unsigned SVTBits = SVT.getSizeInBits();
21922 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21923 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21924 uint64_t ShAmt = C.getZExtValue();
21926 // Don't try to convert this shift into a ISD::SRA if the shift
21927 // count is bigger than or equal to the element size.
21928 if (ShAmt >= SVTBits)
21931 // Trivial case: if the shift count is zero, then fold this
21932 // into the first operand.
21936 // Replace this packed shift intrinsic with a target independent
21938 SDValue Splat = DAG.getConstant(C, VT);
21939 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21944 /// PerformMulCombine - Optimize a single multiply with constant into two
21945 /// in order to implement it with two cheaper instructions, e.g.
21946 /// LEA + SHL, LEA + LEA.
21947 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21948 TargetLowering::DAGCombinerInfo &DCI) {
21949 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21952 EVT VT = N->getValueType(0);
21953 if (VT != MVT::i64)
21956 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21959 uint64_t MulAmt = C->getZExtValue();
21960 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21963 uint64_t MulAmt1 = 0;
21964 uint64_t MulAmt2 = 0;
21965 if ((MulAmt % 9) == 0) {
21967 MulAmt2 = MulAmt / 9;
21968 } else if ((MulAmt % 5) == 0) {
21970 MulAmt2 = MulAmt / 5;
21971 } else if ((MulAmt % 3) == 0) {
21973 MulAmt2 = MulAmt / 3;
21976 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21979 if (isPowerOf2_64(MulAmt2) &&
21980 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21981 // If second multiplifer is pow2, issue it first. We want the multiply by
21982 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21984 std::swap(MulAmt1, MulAmt2);
21987 if (isPowerOf2_64(MulAmt1))
21988 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21989 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21991 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21992 DAG.getConstant(MulAmt1, VT));
21994 if (isPowerOf2_64(MulAmt2))
21995 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21996 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21998 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21999 DAG.getConstant(MulAmt2, VT));
22001 // Do not add new nodes to DAG combiner worklist.
22002 DCI.CombineTo(N, NewMul, false);
22007 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22008 SDValue N0 = N->getOperand(0);
22009 SDValue N1 = N->getOperand(1);
22010 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22011 EVT VT = N0.getValueType();
22013 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22014 // since the result of setcc_c is all zero's or all ones.
22015 if (VT.isInteger() && !VT.isVector() &&
22016 N1C && N0.getOpcode() == ISD::AND &&
22017 N0.getOperand(1).getOpcode() == ISD::Constant) {
22018 SDValue N00 = N0.getOperand(0);
22019 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22020 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22021 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22022 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22023 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22024 APInt ShAmt = N1C->getAPIntValue();
22025 Mask = Mask.shl(ShAmt);
22027 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22028 N00, DAG.getConstant(Mask, VT));
22032 // Hardware support for vector shifts is sparse which makes us scalarize the
22033 // vector operations in many cases. Also, on sandybridge ADD is faster than
22035 // (shl V, 1) -> add V,V
22036 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22037 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22038 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22039 // We shift all of the values by one. In many cases we do not have
22040 // hardware support for this operation. This is better expressed as an ADD
22042 if (N1SplatC->getZExtValue() == 1)
22043 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22049 /// \brief Returns a vector of 0s if the node in input is a vector logical
22050 /// shift by a constant amount which is known to be bigger than or equal
22051 /// to the vector element size in bits.
22052 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22053 const X86Subtarget *Subtarget) {
22054 EVT VT = N->getValueType(0);
22056 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22057 (!Subtarget->hasInt256() ||
22058 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22061 SDValue Amt = N->getOperand(1);
22063 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22064 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22065 APInt ShiftAmt = AmtSplat->getAPIntValue();
22066 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22068 // SSE2/AVX2 logical shifts always return a vector of 0s
22069 // if the shift amount is bigger than or equal to
22070 // the element size. The constant shift amount will be
22071 // encoded as a 8-bit immediate.
22072 if (ShiftAmt.trunc(8).uge(MaxAmount))
22073 return getZeroVector(VT, Subtarget, DAG, DL);
22079 /// PerformShiftCombine - Combine shifts.
22080 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22081 TargetLowering::DAGCombinerInfo &DCI,
22082 const X86Subtarget *Subtarget) {
22083 if (N->getOpcode() == ISD::SHL) {
22084 SDValue V = PerformSHLCombine(N, DAG);
22085 if (V.getNode()) return V;
22088 if (N->getOpcode() != ISD::SRA) {
22089 // Try to fold this logical shift into a zero vector.
22090 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22091 if (V.getNode()) return V;
22097 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22098 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22099 // and friends. Likewise for OR -> CMPNEQSS.
22100 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22101 TargetLowering::DAGCombinerInfo &DCI,
22102 const X86Subtarget *Subtarget) {
22105 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22106 // we're requiring SSE2 for both.
22107 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22108 SDValue N0 = N->getOperand(0);
22109 SDValue N1 = N->getOperand(1);
22110 SDValue CMP0 = N0->getOperand(1);
22111 SDValue CMP1 = N1->getOperand(1);
22114 // The SETCCs should both refer to the same CMP.
22115 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22118 SDValue CMP00 = CMP0->getOperand(0);
22119 SDValue CMP01 = CMP0->getOperand(1);
22120 EVT VT = CMP00.getValueType();
22122 if (VT == MVT::f32 || VT == MVT::f64) {
22123 bool ExpectingFlags = false;
22124 // Check for any users that want flags:
22125 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22126 !ExpectingFlags && UI != UE; ++UI)
22127 switch (UI->getOpcode()) {
22132 ExpectingFlags = true;
22134 case ISD::CopyToReg:
22135 case ISD::SIGN_EXTEND:
22136 case ISD::ZERO_EXTEND:
22137 case ISD::ANY_EXTEND:
22141 if (!ExpectingFlags) {
22142 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22143 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22145 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22146 X86::CondCode tmp = cc0;
22151 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22152 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22153 // FIXME: need symbolic constants for these magic numbers.
22154 // See X86ATTInstPrinter.cpp:printSSECC().
22155 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22156 if (Subtarget->hasAVX512()) {
22157 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22158 CMP01, DAG.getConstant(x86cc, MVT::i8));
22159 if (N->getValueType(0) != MVT::i1)
22160 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22164 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22165 CMP00.getValueType(), CMP00, CMP01,
22166 DAG.getConstant(x86cc, MVT::i8));
22168 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22169 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22171 if (is64BitFP && !Subtarget->is64Bit()) {
22172 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22173 // 64-bit integer, since that's not a legal type. Since
22174 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22175 // bits, but can do this little dance to extract the lowest 32 bits
22176 // and work with those going forward.
22177 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22179 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22181 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22182 Vector32, DAG.getIntPtrConstant(0));
22186 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22187 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22188 DAG.getConstant(1, IntVT));
22189 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22190 return OneBitOfTruth;
22198 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22199 /// so it can be folded inside ANDNP.
22200 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22201 EVT VT = N->getValueType(0);
22203 // Match direct AllOnes for 128 and 256-bit vectors
22204 if (ISD::isBuildVectorAllOnes(N))
22207 // Look through a bit convert.
22208 if (N->getOpcode() == ISD::BITCAST)
22209 N = N->getOperand(0).getNode();
22211 // Sometimes the operand may come from a insert_subvector building a 256-bit
22213 if (VT.is256BitVector() &&
22214 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22215 SDValue V1 = N->getOperand(0);
22216 SDValue V2 = N->getOperand(1);
22218 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22219 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22220 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22221 ISD::isBuildVectorAllOnes(V2.getNode()))
22228 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22229 // register. In most cases we actually compare or select YMM-sized registers
22230 // and mixing the two types creates horrible code. This method optimizes
22231 // some of the transition sequences.
22232 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22233 TargetLowering::DAGCombinerInfo &DCI,
22234 const X86Subtarget *Subtarget) {
22235 EVT VT = N->getValueType(0);
22236 if (!VT.is256BitVector())
22239 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22240 N->getOpcode() == ISD::ZERO_EXTEND ||
22241 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22243 SDValue Narrow = N->getOperand(0);
22244 EVT NarrowVT = Narrow->getValueType(0);
22245 if (!NarrowVT.is128BitVector())
22248 if (Narrow->getOpcode() != ISD::XOR &&
22249 Narrow->getOpcode() != ISD::AND &&
22250 Narrow->getOpcode() != ISD::OR)
22253 SDValue N0 = Narrow->getOperand(0);
22254 SDValue N1 = Narrow->getOperand(1);
22257 // The Left side has to be a trunc.
22258 if (N0.getOpcode() != ISD::TRUNCATE)
22261 // The type of the truncated inputs.
22262 EVT WideVT = N0->getOperand(0)->getValueType(0);
22266 // The right side has to be a 'trunc' or a constant vector.
22267 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22268 ConstantSDNode *RHSConstSplat = nullptr;
22269 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22270 RHSConstSplat = RHSBV->getConstantSplatNode();
22271 if (!RHSTrunc && !RHSConstSplat)
22274 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22276 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22279 // Set N0 and N1 to hold the inputs to the new wide operation.
22280 N0 = N0->getOperand(0);
22281 if (RHSConstSplat) {
22282 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22283 SDValue(RHSConstSplat, 0));
22284 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22285 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22286 } else if (RHSTrunc) {
22287 N1 = N1->getOperand(0);
22290 // Generate the wide operation.
22291 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22292 unsigned Opcode = N->getOpcode();
22294 case ISD::ANY_EXTEND:
22296 case ISD::ZERO_EXTEND: {
22297 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22298 APInt Mask = APInt::getAllOnesValue(InBits);
22299 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22300 return DAG.getNode(ISD::AND, DL, VT,
22301 Op, DAG.getConstant(Mask, VT));
22303 case ISD::SIGN_EXTEND:
22304 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22305 Op, DAG.getValueType(NarrowVT));
22307 llvm_unreachable("Unexpected opcode");
22311 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22312 TargetLowering::DAGCombinerInfo &DCI,
22313 const X86Subtarget *Subtarget) {
22314 EVT VT = N->getValueType(0);
22315 if (DCI.isBeforeLegalizeOps())
22318 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22322 // Create BEXTR instructions
22323 // BEXTR is ((X >> imm) & (2**size-1))
22324 if (VT == MVT::i32 || VT == MVT::i64) {
22325 SDValue N0 = N->getOperand(0);
22326 SDValue N1 = N->getOperand(1);
22329 // Check for BEXTR.
22330 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22331 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22332 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22333 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22334 if (MaskNode && ShiftNode) {
22335 uint64_t Mask = MaskNode->getZExtValue();
22336 uint64_t Shift = ShiftNode->getZExtValue();
22337 if (isMask_64(Mask)) {
22338 uint64_t MaskSize = CountPopulation_64(Mask);
22339 if (Shift + MaskSize <= VT.getSizeInBits())
22340 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22341 DAG.getConstant(Shift | (MaskSize << 8), VT));
22349 // Want to form ANDNP nodes:
22350 // 1) In the hopes of then easily combining them with OR and AND nodes
22351 // to form PBLEND/PSIGN.
22352 // 2) To match ANDN packed intrinsics
22353 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22356 SDValue N0 = N->getOperand(0);
22357 SDValue N1 = N->getOperand(1);
22360 // Check LHS for vnot
22361 if (N0.getOpcode() == ISD::XOR &&
22362 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22363 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22364 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22366 // Check RHS for vnot
22367 if (N1.getOpcode() == ISD::XOR &&
22368 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22369 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22370 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22375 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22376 TargetLowering::DAGCombinerInfo &DCI,
22377 const X86Subtarget *Subtarget) {
22378 if (DCI.isBeforeLegalizeOps())
22381 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22385 SDValue N0 = N->getOperand(0);
22386 SDValue N1 = N->getOperand(1);
22387 EVT VT = N->getValueType(0);
22389 // look for psign/blend
22390 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22391 if (!Subtarget->hasSSSE3() ||
22392 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22395 // Canonicalize pandn to RHS
22396 if (N0.getOpcode() == X86ISD::ANDNP)
22398 // or (and (m, y), (pandn m, x))
22399 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22400 SDValue Mask = N1.getOperand(0);
22401 SDValue X = N1.getOperand(1);
22403 if (N0.getOperand(0) == Mask)
22404 Y = N0.getOperand(1);
22405 if (N0.getOperand(1) == Mask)
22406 Y = N0.getOperand(0);
22408 // Check to see if the mask appeared in both the AND and ANDNP and
22412 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22413 // Look through mask bitcast.
22414 if (Mask.getOpcode() == ISD::BITCAST)
22415 Mask = Mask.getOperand(0);
22416 if (X.getOpcode() == ISD::BITCAST)
22417 X = X.getOperand(0);
22418 if (Y.getOpcode() == ISD::BITCAST)
22419 Y = Y.getOperand(0);
22421 EVT MaskVT = Mask.getValueType();
22423 // Validate that the Mask operand is a vector sra node.
22424 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22425 // there is no psrai.b
22426 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22427 unsigned SraAmt = ~0;
22428 if (Mask.getOpcode() == ISD::SRA) {
22429 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22430 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22431 SraAmt = AmtConst->getZExtValue();
22432 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22433 SDValue SraC = Mask.getOperand(1);
22434 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22436 if ((SraAmt + 1) != EltBits)
22441 // Now we know we at least have a plendvb with the mask val. See if
22442 // we can form a psignb/w/d.
22443 // psign = x.type == y.type == mask.type && y = sub(0, x);
22444 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22445 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22446 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22447 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22448 "Unsupported VT for PSIGN");
22449 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22450 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22452 // PBLENDVB only available on SSE 4.1
22453 if (!Subtarget->hasSSE41())
22456 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22458 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22459 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22460 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22461 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22462 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22466 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22469 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22470 MachineFunction &MF = DAG.getMachineFunction();
22471 bool OptForSize = MF.getFunction()->getAttributes().
22472 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22474 // SHLD/SHRD instructions have lower register pressure, but on some
22475 // platforms they have higher latency than the equivalent
22476 // series of shifts/or that would otherwise be generated.
22477 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22478 // have higher latencies and we are not optimizing for size.
22479 if (!OptForSize && Subtarget->isSHLDSlow())
22482 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22484 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22486 if (!N0.hasOneUse() || !N1.hasOneUse())
22489 SDValue ShAmt0 = N0.getOperand(1);
22490 if (ShAmt0.getValueType() != MVT::i8)
22492 SDValue ShAmt1 = N1.getOperand(1);
22493 if (ShAmt1.getValueType() != MVT::i8)
22495 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22496 ShAmt0 = ShAmt0.getOperand(0);
22497 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22498 ShAmt1 = ShAmt1.getOperand(0);
22501 unsigned Opc = X86ISD::SHLD;
22502 SDValue Op0 = N0.getOperand(0);
22503 SDValue Op1 = N1.getOperand(0);
22504 if (ShAmt0.getOpcode() == ISD::SUB) {
22505 Opc = X86ISD::SHRD;
22506 std::swap(Op0, Op1);
22507 std::swap(ShAmt0, ShAmt1);
22510 unsigned Bits = VT.getSizeInBits();
22511 if (ShAmt1.getOpcode() == ISD::SUB) {
22512 SDValue Sum = ShAmt1.getOperand(0);
22513 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22514 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22515 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22516 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22517 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22518 return DAG.getNode(Opc, DL, VT,
22520 DAG.getNode(ISD::TRUNCATE, DL,
22523 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22524 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22526 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22527 return DAG.getNode(Opc, DL, VT,
22528 N0.getOperand(0), N1.getOperand(0),
22529 DAG.getNode(ISD::TRUNCATE, DL,
22536 // Generate NEG and CMOV for integer abs.
22537 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22538 EVT VT = N->getValueType(0);
22540 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22541 // 8-bit integer abs to NEG and CMOV.
22542 if (VT.isInteger() && VT.getSizeInBits() == 8)
22545 SDValue N0 = N->getOperand(0);
22546 SDValue N1 = N->getOperand(1);
22549 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22550 // and change it to SUB and CMOV.
22551 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22552 N0.getOpcode() == ISD::ADD &&
22553 N0.getOperand(1) == N1 &&
22554 N1.getOpcode() == ISD::SRA &&
22555 N1.getOperand(0) == N0.getOperand(0))
22556 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22557 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22558 // Generate SUB & CMOV.
22559 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22560 DAG.getConstant(0, VT), N0.getOperand(0));
22562 SDValue Ops[] = { N0.getOperand(0), Neg,
22563 DAG.getConstant(X86::COND_GE, MVT::i8),
22564 SDValue(Neg.getNode(), 1) };
22565 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22570 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22571 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22572 TargetLowering::DAGCombinerInfo &DCI,
22573 const X86Subtarget *Subtarget) {
22574 if (DCI.isBeforeLegalizeOps())
22577 if (Subtarget->hasCMov()) {
22578 SDValue RV = performIntegerAbsCombine(N, DAG);
22586 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22587 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22588 TargetLowering::DAGCombinerInfo &DCI,
22589 const X86Subtarget *Subtarget) {
22590 LoadSDNode *Ld = cast<LoadSDNode>(N);
22591 EVT RegVT = Ld->getValueType(0);
22592 EVT MemVT = Ld->getMemoryVT();
22594 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22596 // On Sandybridge unaligned 256bit loads are inefficient.
22597 ISD::LoadExtType Ext = Ld->getExtensionType();
22598 unsigned Alignment = Ld->getAlignment();
22599 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22600 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22601 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22602 unsigned NumElems = RegVT.getVectorNumElements();
22606 SDValue Ptr = Ld->getBasePtr();
22607 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22609 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22611 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22612 Ld->getPointerInfo(), Ld->isVolatile(),
22613 Ld->isNonTemporal(), Ld->isInvariant(),
22615 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22616 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22617 Ld->getPointerInfo(), Ld->isVolatile(),
22618 Ld->isNonTemporal(), Ld->isInvariant(),
22619 std::min(16U, Alignment));
22620 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22622 Load2.getValue(1));
22624 SDValue NewVec = DAG.getUNDEF(RegVT);
22625 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22626 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22627 return DCI.CombineTo(N, NewVec, TF, true);
22633 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22634 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22635 const X86Subtarget *Subtarget) {
22636 StoreSDNode *St = cast<StoreSDNode>(N);
22637 EVT VT = St->getValue().getValueType();
22638 EVT StVT = St->getMemoryVT();
22640 SDValue StoredVal = St->getOperand(1);
22641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22643 // If we are saving a concatenation of two XMM registers, perform two stores.
22644 // On Sandy Bridge, 256-bit memory operations are executed by two
22645 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22646 // memory operation.
22647 unsigned Alignment = St->getAlignment();
22648 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22649 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22650 StVT == VT && !IsAligned) {
22651 unsigned NumElems = VT.getVectorNumElements();
22655 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22656 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22658 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22659 SDValue Ptr0 = St->getBasePtr();
22660 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22662 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22663 St->getPointerInfo(), St->isVolatile(),
22664 St->isNonTemporal(), Alignment);
22665 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22666 St->getPointerInfo(), St->isVolatile(),
22667 St->isNonTemporal(),
22668 std::min(16U, Alignment));
22669 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22672 // Optimize trunc store (of multiple scalars) to shuffle and store.
22673 // First, pack all of the elements in one place. Next, store to memory
22674 // in fewer chunks.
22675 if (St->isTruncatingStore() && VT.isVector()) {
22676 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22677 unsigned NumElems = VT.getVectorNumElements();
22678 assert(StVT != VT && "Cannot truncate to the same type");
22679 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22680 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22682 // From, To sizes and ElemCount must be pow of two
22683 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22684 // We are going to use the original vector elt for storing.
22685 // Accumulated smaller vector elements must be a multiple of the store size.
22686 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22688 unsigned SizeRatio = FromSz / ToSz;
22690 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22692 // Create a type on which we perform the shuffle
22693 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22694 StVT.getScalarType(), NumElems*SizeRatio);
22696 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22698 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22699 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22700 for (unsigned i = 0; i != NumElems; ++i)
22701 ShuffleVec[i] = i * SizeRatio;
22703 // Can't shuffle using an illegal type.
22704 if (!TLI.isTypeLegal(WideVecVT))
22707 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22708 DAG.getUNDEF(WideVecVT),
22710 // At this point all of the data is stored at the bottom of the
22711 // register. We now need to save it to mem.
22713 // Find the largest store unit
22714 MVT StoreType = MVT::i8;
22715 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22716 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22717 MVT Tp = (MVT::SimpleValueType)tp;
22718 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22722 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22723 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22724 (64 <= NumElems * ToSz))
22725 StoreType = MVT::f64;
22727 // Bitcast the original vector into a vector of store-size units
22728 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22729 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22730 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22731 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22732 SmallVector<SDValue, 8> Chains;
22733 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22734 TLI.getPointerTy());
22735 SDValue Ptr = St->getBasePtr();
22737 // Perform one or more big stores into memory.
22738 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22739 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22740 StoreType, ShuffWide,
22741 DAG.getIntPtrConstant(i));
22742 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22743 St->getPointerInfo(), St->isVolatile(),
22744 St->isNonTemporal(), St->getAlignment());
22745 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22746 Chains.push_back(Ch);
22749 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22752 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22753 // the FP state in cases where an emms may be missing.
22754 // A preferable solution to the general problem is to figure out the right
22755 // places to insert EMMS. This qualifies as a quick hack.
22757 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22758 if (VT.getSizeInBits() != 64)
22761 const Function *F = DAG.getMachineFunction().getFunction();
22762 bool NoImplicitFloatOps = F->getAttributes().
22763 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22764 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22765 && Subtarget->hasSSE2();
22766 if ((VT.isVector() ||
22767 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22768 isa<LoadSDNode>(St->getValue()) &&
22769 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22770 St->getChain().hasOneUse() && !St->isVolatile()) {
22771 SDNode* LdVal = St->getValue().getNode();
22772 LoadSDNode *Ld = nullptr;
22773 int TokenFactorIndex = -1;
22774 SmallVector<SDValue, 8> Ops;
22775 SDNode* ChainVal = St->getChain().getNode();
22776 // Must be a store of a load. We currently handle two cases: the load
22777 // is a direct child, and it's under an intervening TokenFactor. It is
22778 // possible to dig deeper under nested TokenFactors.
22779 if (ChainVal == LdVal)
22780 Ld = cast<LoadSDNode>(St->getChain());
22781 else if (St->getValue().hasOneUse() &&
22782 ChainVal->getOpcode() == ISD::TokenFactor) {
22783 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22784 if (ChainVal->getOperand(i).getNode() == LdVal) {
22785 TokenFactorIndex = i;
22786 Ld = cast<LoadSDNode>(St->getValue());
22788 Ops.push_back(ChainVal->getOperand(i));
22792 if (!Ld || !ISD::isNormalLoad(Ld))
22795 // If this is not the MMX case, i.e. we are just turning i64 load/store
22796 // into f64 load/store, avoid the transformation if there are multiple
22797 // uses of the loaded value.
22798 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22803 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22804 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22806 if (Subtarget->is64Bit() || F64IsLegal) {
22807 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22808 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22809 Ld->getPointerInfo(), Ld->isVolatile(),
22810 Ld->isNonTemporal(), Ld->isInvariant(),
22811 Ld->getAlignment());
22812 SDValue NewChain = NewLd.getValue(1);
22813 if (TokenFactorIndex != -1) {
22814 Ops.push_back(NewChain);
22815 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22817 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22818 St->getPointerInfo(),
22819 St->isVolatile(), St->isNonTemporal(),
22820 St->getAlignment());
22823 // Otherwise, lower to two pairs of 32-bit loads / stores.
22824 SDValue LoAddr = Ld->getBasePtr();
22825 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22826 DAG.getConstant(4, MVT::i32));
22828 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22829 Ld->getPointerInfo(),
22830 Ld->isVolatile(), Ld->isNonTemporal(),
22831 Ld->isInvariant(), Ld->getAlignment());
22832 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22833 Ld->getPointerInfo().getWithOffset(4),
22834 Ld->isVolatile(), Ld->isNonTemporal(),
22836 MinAlign(Ld->getAlignment(), 4));
22838 SDValue NewChain = LoLd.getValue(1);
22839 if (TokenFactorIndex != -1) {
22840 Ops.push_back(LoLd);
22841 Ops.push_back(HiLd);
22842 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22845 LoAddr = St->getBasePtr();
22846 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22847 DAG.getConstant(4, MVT::i32));
22849 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22850 St->getPointerInfo(),
22851 St->isVolatile(), St->isNonTemporal(),
22852 St->getAlignment());
22853 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22854 St->getPointerInfo().getWithOffset(4),
22856 St->isNonTemporal(),
22857 MinAlign(St->getAlignment(), 4));
22858 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22863 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22864 /// and return the operands for the horizontal operation in LHS and RHS. A
22865 /// horizontal operation performs the binary operation on successive elements
22866 /// of its first operand, then on successive elements of its second operand,
22867 /// returning the resulting values in a vector. For example, if
22868 /// A = < float a0, float a1, float a2, float a3 >
22870 /// B = < float b0, float b1, float b2, float b3 >
22871 /// then the result of doing a horizontal operation on A and B is
22872 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22873 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22874 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22875 /// set to A, RHS to B, and the routine returns 'true'.
22876 /// Note that the binary operation should have the property that if one of the
22877 /// operands is UNDEF then the result is UNDEF.
22878 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22879 // Look for the following pattern: if
22880 // A = < float a0, float a1, float a2, float a3 >
22881 // B = < float b0, float b1, float b2, float b3 >
22883 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22884 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22885 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22886 // which is A horizontal-op B.
22888 // At least one of the operands should be a vector shuffle.
22889 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22890 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22893 MVT VT = LHS.getSimpleValueType();
22895 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22896 "Unsupported vector type for horizontal add/sub");
22898 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22899 // operate independently on 128-bit lanes.
22900 unsigned NumElts = VT.getVectorNumElements();
22901 unsigned NumLanes = VT.getSizeInBits()/128;
22902 unsigned NumLaneElts = NumElts / NumLanes;
22903 assert((NumLaneElts % 2 == 0) &&
22904 "Vector type should have an even number of elements in each lane");
22905 unsigned HalfLaneElts = NumLaneElts/2;
22907 // View LHS in the form
22908 // LHS = VECTOR_SHUFFLE A, B, LMask
22909 // If LHS is not a shuffle then pretend it is the shuffle
22910 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22911 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22914 SmallVector<int, 16> LMask(NumElts);
22915 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22916 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22917 A = LHS.getOperand(0);
22918 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22919 B = LHS.getOperand(1);
22920 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22921 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22923 if (LHS.getOpcode() != ISD::UNDEF)
22925 for (unsigned i = 0; i != NumElts; ++i)
22929 // Likewise, view RHS in the form
22930 // RHS = VECTOR_SHUFFLE C, D, RMask
22932 SmallVector<int, 16> RMask(NumElts);
22933 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22934 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22935 C = RHS.getOperand(0);
22936 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22937 D = RHS.getOperand(1);
22938 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22939 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22941 if (RHS.getOpcode() != ISD::UNDEF)
22943 for (unsigned i = 0; i != NumElts; ++i)
22947 // Check that the shuffles are both shuffling the same vectors.
22948 if (!(A == C && B == D) && !(A == D && B == C))
22951 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22952 if (!A.getNode() && !B.getNode())
22955 // If A and B occur in reverse order in RHS, then "swap" them (which means
22956 // rewriting the mask).
22958 CommuteVectorShuffleMask(RMask, NumElts);
22960 // At this point LHS and RHS are equivalent to
22961 // LHS = VECTOR_SHUFFLE A, B, LMask
22962 // RHS = VECTOR_SHUFFLE A, B, RMask
22963 // Check that the masks correspond to performing a horizontal operation.
22964 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22965 for (unsigned i = 0; i != NumLaneElts; ++i) {
22966 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22968 // Ignore any UNDEF components.
22969 if (LIdx < 0 || RIdx < 0 ||
22970 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22971 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22974 // Check that successive elements are being operated on. If not, this is
22975 // not a horizontal operation.
22976 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22977 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22978 if (!(LIdx == Index && RIdx == Index + 1) &&
22979 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22984 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22985 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22989 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22990 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22991 const X86Subtarget *Subtarget) {
22992 EVT VT = N->getValueType(0);
22993 SDValue LHS = N->getOperand(0);
22994 SDValue RHS = N->getOperand(1);
22996 // Try to synthesize horizontal adds from adds of shuffles.
22997 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22998 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22999 isHorizontalBinOp(LHS, RHS, true))
23000 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23004 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23005 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23006 const X86Subtarget *Subtarget) {
23007 EVT VT = N->getValueType(0);
23008 SDValue LHS = N->getOperand(0);
23009 SDValue RHS = N->getOperand(1);
23011 // Try to synthesize horizontal subs from subs of shuffles.
23012 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23013 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23014 isHorizontalBinOp(LHS, RHS, false))
23015 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23019 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23020 /// X86ISD::FXOR nodes.
23021 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23022 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23023 // F[X]OR(0.0, x) -> x
23024 // F[X]OR(x, 0.0) -> x
23025 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23026 if (C->getValueAPF().isPosZero())
23027 return N->getOperand(1);
23028 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23029 if (C->getValueAPF().isPosZero())
23030 return N->getOperand(0);
23034 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23035 /// X86ISD::FMAX nodes.
23036 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23037 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23039 // Only perform optimizations if UnsafeMath is used.
23040 if (!DAG.getTarget().Options.UnsafeFPMath)
23043 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23044 // into FMINC and FMAXC, which are Commutative operations.
23045 unsigned NewOp = 0;
23046 switch (N->getOpcode()) {
23047 default: llvm_unreachable("unknown opcode");
23048 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23049 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23052 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23053 N->getOperand(0), N->getOperand(1));
23056 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23057 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23058 // FAND(0.0, x) -> 0.0
23059 // FAND(x, 0.0) -> 0.0
23060 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23061 if (C->getValueAPF().isPosZero())
23062 return N->getOperand(0);
23063 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23064 if (C->getValueAPF().isPosZero())
23065 return N->getOperand(1);
23069 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23070 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23071 // FANDN(x, 0.0) -> 0.0
23072 // FANDN(0.0, x) -> x
23073 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23074 if (C->getValueAPF().isPosZero())
23075 return N->getOperand(1);
23076 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23077 if (C->getValueAPF().isPosZero())
23078 return N->getOperand(1);
23082 static SDValue PerformBTCombine(SDNode *N,
23084 TargetLowering::DAGCombinerInfo &DCI) {
23085 // BT ignores high bits in the bit index operand.
23086 SDValue Op1 = N->getOperand(1);
23087 if (Op1.hasOneUse()) {
23088 unsigned BitWidth = Op1.getValueSizeInBits();
23089 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23090 APInt KnownZero, KnownOne;
23091 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23092 !DCI.isBeforeLegalizeOps());
23093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23094 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23095 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23096 DCI.CommitTargetLoweringOpt(TLO);
23101 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23102 SDValue Op = N->getOperand(0);
23103 if (Op.getOpcode() == ISD::BITCAST)
23104 Op = Op.getOperand(0);
23105 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23106 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23107 VT.getVectorElementType().getSizeInBits() ==
23108 OpVT.getVectorElementType().getSizeInBits()) {
23109 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23114 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23115 const X86Subtarget *Subtarget) {
23116 EVT VT = N->getValueType(0);
23117 if (!VT.isVector())
23120 SDValue N0 = N->getOperand(0);
23121 SDValue N1 = N->getOperand(1);
23122 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23125 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23126 // both SSE and AVX2 since there is no sign-extended shift right
23127 // operation on a vector with 64-bit elements.
23128 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23129 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23130 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23131 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23132 SDValue N00 = N0.getOperand(0);
23134 // EXTLOAD has a better solution on AVX2,
23135 // it may be replaced with X86ISD::VSEXT node.
23136 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23137 if (!ISD::isNormalLoad(N00.getNode()))
23140 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23141 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23143 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23149 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23150 TargetLowering::DAGCombinerInfo &DCI,
23151 const X86Subtarget *Subtarget) {
23152 if (!DCI.isBeforeLegalizeOps())
23155 if (!Subtarget->hasFp256())
23158 EVT VT = N->getValueType(0);
23159 if (VT.isVector() && VT.getSizeInBits() == 256) {
23160 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23168 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23169 const X86Subtarget* Subtarget) {
23171 EVT VT = N->getValueType(0);
23173 // Let legalize expand this if it isn't a legal type yet.
23174 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23177 EVT ScalarVT = VT.getScalarType();
23178 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23179 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23182 SDValue A = N->getOperand(0);
23183 SDValue B = N->getOperand(1);
23184 SDValue C = N->getOperand(2);
23186 bool NegA = (A.getOpcode() == ISD::FNEG);
23187 bool NegB = (B.getOpcode() == ISD::FNEG);
23188 bool NegC = (C.getOpcode() == ISD::FNEG);
23190 // Negative multiplication when NegA xor NegB
23191 bool NegMul = (NegA != NegB);
23193 A = A.getOperand(0);
23195 B = B.getOperand(0);
23197 C = C.getOperand(0);
23201 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23203 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23205 return DAG.getNode(Opcode, dl, VT, A, B, C);
23208 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23209 TargetLowering::DAGCombinerInfo &DCI,
23210 const X86Subtarget *Subtarget) {
23211 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23212 // (and (i32 x86isd::setcc_carry), 1)
23213 // This eliminates the zext. This transformation is necessary because
23214 // ISD::SETCC is always legalized to i8.
23216 SDValue N0 = N->getOperand(0);
23217 EVT VT = N->getValueType(0);
23219 if (N0.getOpcode() == ISD::AND &&
23221 N0.getOperand(0).hasOneUse()) {
23222 SDValue N00 = N0.getOperand(0);
23223 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23224 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23225 if (!C || C->getZExtValue() != 1)
23227 return DAG.getNode(ISD::AND, dl, VT,
23228 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23229 N00.getOperand(0), N00.getOperand(1)),
23230 DAG.getConstant(1, VT));
23234 if (N0.getOpcode() == ISD::TRUNCATE &&
23236 N0.getOperand(0).hasOneUse()) {
23237 SDValue N00 = N0.getOperand(0);
23238 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23239 return DAG.getNode(ISD::AND, dl, VT,
23240 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23241 N00.getOperand(0), N00.getOperand(1)),
23242 DAG.getConstant(1, VT));
23245 if (VT.is256BitVector()) {
23246 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23254 // Optimize x == -y --> x+y == 0
23255 // x != -y --> x+y != 0
23256 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23257 const X86Subtarget* Subtarget) {
23258 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23259 SDValue LHS = N->getOperand(0);
23260 SDValue RHS = N->getOperand(1);
23261 EVT VT = N->getValueType(0);
23264 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23265 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23266 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23267 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23268 LHS.getValueType(), RHS, LHS.getOperand(1));
23269 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23270 addV, DAG.getConstant(0, addV.getValueType()), CC);
23272 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23273 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23274 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23275 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23276 RHS.getValueType(), LHS, RHS.getOperand(1));
23277 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23278 addV, DAG.getConstant(0, addV.getValueType()), CC);
23281 if (VT.getScalarType() == MVT::i1) {
23282 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23283 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23284 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23285 if (!IsSEXT0 && !IsVZero0)
23287 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23288 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23289 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23291 if (!IsSEXT1 && !IsVZero1)
23294 if (IsSEXT0 && IsVZero1) {
23295 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23296 if (CC == ISD::SETEQ)
23297 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23298 return LHS.getOperand(0);
23300 if (IsSEXT1 && IsVZero0) {
23301 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23302 if (CC == ISD::SETEQ)
23303 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23304 return RHS.getOperand(0);
23311 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23312 const X86Subtarget *Subtarget) {
23314 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23315 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23316 "X86insertps is only defined for v4x32");
23318 SDValue Ld = N->getOperand(1);
23319 if (MayFoldLoad(Ld)) {
23320 // Extract the countS bits from the immediate so we can get the proper
23321 // address when narrowing the vector load to a specific element.
23322 // When the second source op is a memory address, interps doesn't use
23323 // countS and just gets an f32 from that address.
23324 unsigned DestIndex =
23325 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23326 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23330 // Create this as a scalar to vector to match the instruction pattern.
23331 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23332 // countS bits are ignored when loading from memory on insertps, which
23333 // means we don't need to explicitly set them to 0.
23334 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23335 LoadScalarToVector, N->getOperand(2));
23338 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23339 // as "sbb reg,reg", since it can be extended without zext and produces
23340 // an all-ones bit which is more useful than 0/1 in some cases.
23341 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23344 return DAG.getNode(ISD::AND, DL, VT,
23345 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23346 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23347 DAG.getConstant(1, VT));
23348 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23349 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23350 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23351 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23354 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23355 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23356 TargetLowering::DAGCombinerInfo &DCI,
23357 const X86Subtarget *Subtarget) {
23359 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23360 SDValue EFLAGS = N->getOperand(1);
23362 if (CC == X86::COND_A) {
23363 // Try to convert COND_A into COND_B in an attempt to facilitate
23364 // materializing "setb reg".
23366 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23367 // cannot take an immediate as its first operand.
23369 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23370 EFLAGS.getValueType().isInteger() &&
23371 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23372 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23373 EFLAGS.getNode()->getVTList(),
23374 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23375 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23376 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23380 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23381 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23383 if (CC == X86::COND_B)
23384 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23388 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23389 if (Flags.getNode()) {
23390 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23391 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23397 // Optimize branch condition evaluation.
23399 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23400 TargetLowering::DAGCombinerInfo &DCI,
23401 const X86Subtarget *Subtarget) {
23403 SDValue Chain = N->getOperand(0);
23404 SDValue Dest = N->getOperand(1);
23405 SDValue EFLAGS = N->getOperand(3);
23406 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23410 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23411 if (Flags.getNode()) {
23412 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23413 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23420 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23421 SelectionDAG &DAG) {
23422 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23423 // optimize away operation when it's from a constant.
23425 // The general transformation is:
23426 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23427 // AND(VECTOR_CMP(x,y), constant2)
23428 // constant2 = UNARYOP(constant)
23430 // Early exit if this isn't a vector operation, the operand of the
23431 // unary operation isn't a bitwise AND, or if the sizes of the operations
23432 // aren't the same.
23433 EVT VT = N->getValueType(0);
23434 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23435 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23436 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23439 // Now check that the other operand of the AND is a constant. We could
23440 // make the transformation for non-constant splats as well, but it's unclear
23441 // that would be a benefit as it would not eliminate any operations, just
23442 // perform one more step in scalar code before moving to the vector unit.
23443 if (BuildVectorSDNode *BV =
23444 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23445 // Bail out if the vector isn't a constant.
23446 if (!BV->isConstant())
23449 // Everything checks out. Build up the new and improved node.
23451 EVT IntVT = BV->getValueType(0);
23452 // Create a new constant of the appropriate type for the transformed
23454 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23455 // The AND node needs bitcasts to/from an integer vector type around it.
23456 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23457 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23458 N->getOperand(0)->getOperand(0), MaskConst);
23459 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23466 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23467 const X86TargetLowering *XTLI) {
23468 // First try to optimize away the conversion entirely when it's
23469 // conditionally from a constant. Vectors only.
23470 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23471 if (Res != SDValue())
23474 // Now move on to more general possibilities.
23475 SDValue Op0 = N->getOperand(0);
23476 EVT InVT = Op0->getValueType(0);
23478 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23479 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23481 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23482 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23483 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23486 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23487 // a 32-bit target where SSE doesn't support i64->FP operations.
23488 if (Op0.getOpcode() == ISD::LOAD) {
23489 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23490 EVT VT = Ld->getValueType(0);
23491 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23492 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23493 !XTLI->getSubtarget()->is64Bit() &&
23495 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23496 Ld->getChain(), Op0, DAG);
23497 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23504 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23505 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23506 X86TargetLowering::DAGCombinerInfo &DCI) {
23507 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23508 // the result is either zero or one (depending on the input carry bit).
23509 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23510 if (X86::isZeroNode(N->getOperand(0)) &&
23511 X86::isZeroNode(N->getOperand(1)) &&
23512 // We don't have a good way to replace an EFLAGS use, so only do this when
23514 SDValue(N, 1).use_empty()) {
23516 EVT VT = N->getValueType(0);
23517 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23518 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23519 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23520 DAG.getConstant(X86::COND_B,MVT::i8),
23522 DAG.getConstant(1, VT));
23523 return DCI.CombineTo(N, Res1, CarryOut);
23529 // fold (add Y, (sete X, 0)) -> adc 0, Y
23530 // (add Y, (setne X, 0)) -> sbb -1, Y
23531 // (sub (sete X, 0), Y) -> sbb 0, Y
23532 // (sub (setne X, 0), Y) -> adc -1, Y
23533 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23536 // Look through ZExts.
23537 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23538 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23541 SDValue SetCC = Ext.getOperand(0);
23542 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23545 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23546 if (CC != X86::COND_E && CC != X86::COND_NE)
23549 SDValue Cmp = SetCC.getOperand(1);
23550 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23551 !X86::isZeroNode(Cmp.getOperand(1)) ||
23552 !Cmp.getOperand(0).getValueType().isInteger())
23555 SDValue CmpOp0 = Cmp.getOperand(0);
23556 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23557 DAG.getConstant(1, CmpOp0.getValueType()));
23559 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23560 if (CC == X86::COND_NE)
23561 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23562 DL, OtherVal.getValueType(), OtherVal,
23563 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23564 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23565 DL, OtherVal.getValueType(), OtherVal,
23566 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23569 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23570 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23571 const X86Subtarget *Subtarget) {
23572 EVT VT = N->getValueType(0);
23573 SDValue Op0 = N->getOperand(0);
23574 SDValue Op1 = N->getOperand(1);
23576 // Try to synthesize horizontal adds from adds of shuffles.
23577 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23578 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23579 isHorizontalBinOp(Op0, Op1, true))
23580 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23582 return OptimizeConditionalInDecrement(N, DAG);
23585 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23586 const X86Subtarget *Subtarget) {
23587 SDValue Op0 = N->getOperand(0);
23588 SDValue Op1 = N->getOperand(1);
23590 // X86 can't encode an immediate LHS of a sub. See if we can push the
23591 // negation into a preceding instruction.
23592 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23593 // If the RHS of the sub is a XOR with one use and a constant, invert the
23594 // immediate. Then add one to the LHS of the sub so we can turn
23595 // X-Y -> X+~Y+1, saving one register.
23596 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23597 isa<ConstantSDNode>(Op1.getOperand(1))) {
23598 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23599 EVT VT = Op0.getValueType();
23600 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23602 DAG.getConstant(~XorC, VT));
23603 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23604 DAG.getConstant(C->getAPIntValue()+1, VT));
23608 // Try to synthesize horizontal adds from adds of shuffles.
23609 EVT VT = N->getValueType(0);
23610 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23611 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23612 isHorizontalBinOp(Op0, Op1, true))
23613 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23615 return OptimizeConditionalInDecrement(N, DAG);
23618 /// performVZEXTCombine - Performs build vector combines
23619 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23620 TargetLowering::DAGCombinerInfo &DCI,
23621 const X86Subtarget *Subtarget) {
23622 // (vzext (bitcast (vzext (x)) -> (vzext x)
23623 SDValue In = N->getOperand(0);
23624 while (In.getOpcode() == ISD::BITCAST)
23625 In = In.getOperand(0);
23627 if (In.getOpcode() != X86ISD::VZEXT)
23630 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23634 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23635 DAGCombinerInfo &DCI) const {
23636 SelectionDAG &DAG = DCI.DAG;
23637 switch (N->getOpcode()) {
23639 case ISD::EXTRACT_VECTOR_ELT:
23640 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23642 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23643 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23644 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23645 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23646 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23647 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23650 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23651 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23652 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23653 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23654 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23655 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23656 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23657 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23658 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23660 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23662 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23663 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23664 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23665 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23666 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23667 case ISD::ANY_EXTEND:
23668 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23669 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23670 case ISD::SIGN_EXTEND_INREG:
23671 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23672 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23673 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23674 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23675 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23676 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23677 case X86ISD::SHUFP: // Handle all target specific shuffles
23678 case X86ISD::PALIGNR:
23679 case X86ISD::UNPCKH:
23680 case X86ISD::UNPCKL:
23681 case X86ISD::MOVHLPS:
23682 case X86ISD::MOVLHPS:
23683 case X86ISD::PSHUFB:
23684 case X86ISD::PSHUFD:
23685 case X86ISD::PSHUFHW:
23686 case X86ISD::PSHUFLW:
23687 case X86ISD::MOVSS:
23688 case X86ISD::MOVSD:
23689 case X86ISD::VPERMILP:
23690 case X86ISD::VPERM2X128:
23691 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23692 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23693 case ISD::INTRINSIC_WO_CHAIN:
23694 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23695 case X86ISD::INSERTPS:
23696 return PerformINSERTPSCombine(N, DAG, Subtarget);
23697 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23703 /// isTypeDesirableForOp - Return true if the target has native support for
23704 /// the specified value type and it is 'desirable' to use the type for the
23705 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23706 /// instruction encodings are longer and some i16 instructions are slow.
23707 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23708 if (!isTypeLegal(VT))
23710 if (VT != MVT::i16)
23717 case ISD::SIGN_EXTEND:
23718 case ISD::ZERO_EXTEND:
23719 case ISD::ANY_EXTEND:
23732 /// IsDesirableToPromoteOp - This method query the target whether it is
23733 /// beneficial for dag combiner to promote the specified node. If true, it
23734 /// should return the desired promotion type by reference.
23735 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23736 EVT VT = Op.getValueType();
23737 if (VT != MVT::i16)
23740 bool Promote = false;
23741 bool Commute = false;
23742 switch (Op.getOpcode()) {
23745 LoadSDNode *LD = cast<LoadSDNode>(Op);
23746 // If the non-extending load has a single use and it's not live out, then it
23747 // might be folded.
23748 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23749 Op.hasOneUse()*/) {
23750 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23751 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23752 // The only case where we'd want to promote LOAD (rather then it being
23753 // promoted as an operand is when it's only use is liveout.
23754 if (UI->getOpcode() != ISD::CopyToReg)
23761 case ISD::SIGN_EXTEND:
23762 case ISD::ZERO_EXTEND:
23763 case ISD::ANY_EXTEND:
23768 SDValue N0 = Op.getOperand(0);
23769 // Look out for (store (shl (load), x)).
23770 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23783 SDValue N0 = Op.getOperand(0);
23784 SDValue N1 = Op.getOperand(1);
23785 if (!Commute && MayFoldLoad(N1))
23787 // Avoid disabling potential load folding opportunities.
23788 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23790 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23800 //===----------------------------------------------------------------------===//
23801 // X86 Inline Assembly Support
23802 //===----------------------------------------------------------------------===//
23805 // Helper to match a string separated by whitespace.
23806 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23807 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23809 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23810 StringRef piece(*args[i]);
23811 if (!s.startswith(piece)) // Check if the piece matches.
23814 s = s.substr(piece.size());
23815 StringRef::size_type pos = s.find_first_not_of(" \t");
23816 if (pos == 0) // We matched a prefix.
23824 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23827 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23829 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23830 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23831 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23832 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23834 if (AsmPieces.size() == 3)
23836 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23843 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23844 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23846 std::string AsmStr = IA->getAsmString();
23848 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23849 if (!Ty || Ty->getBitWidth() % 16 != 0)
23852 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23853 SmallVector<StringRef, 4> AsmPieces;
23854 SplitString(AsmStr, AsmPieces, ";\n");
23856 switch (AsmPieces.size()) {
23857 default: return false;
23859 // FIXME: this should verify that we are targeting a 486 or better. If not,
23860 // we will turn this bswap into something that will be lowered to logical
23861 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23862 // lower so don't worry about this.
23864 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23865 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23866 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23867 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23868 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23869 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23870 // No need to check constraints, nothing other than the equivalent of
23871 // "=r,0" would be valid here.
23872 return IntrinsicLowering::LowerToByteSwap(CI);
23875 // rorw $$8, ${0:w} --> llvm.bswap.i16
23876 if (CI->getType()->isIntegerTy(16) &&
23877 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23878 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23879 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23881 const std::string &ConstraintsStr = IA->getConstraintString();
23882 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23883 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23884 if (clobbersFlagRegisters(AsmPieces))
23885 return IntrinsicLowering::LowerToByteSwap(CI);
23889 if (CI->getType()->isIntegerTy(32) &&
23890 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23891 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23892 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23893 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23895 const std::string &ConstraintsStr = IA->getConstraintString();
23896 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23897 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23898 if (clobbersFlagRegisters(AsmPieces))
23899 return IntrinsicLowering::LowerToByteSwap(CI);
23902 if (CI->getType()->isIntegerTy(64)) {
23903 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23904 if (Constraints.size() >= 2 &&
23905 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23906 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23907 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23908 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23909 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23910 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23911 return IntrinsicLowering::LowerToByteSwap(CI);
23919 /// getConstraintType - Given a constraint letter, return the type of
23920 /// constraint it is for this target.
23921 X86TargetLowering::ConstraintType
23922 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23923 if (Constraint.size() == 1) {
23924 switch (Constraint[0]) {
23935 return C_RegisterClass;
23959 return TargetLowering::getConstraintType(Constraint);
23962 /// Examine constraint type and operand type and determine a weight value.
23963 /// This object must already have been set up with the operand type
23964 /// and the current alternative constraint selected.
23965 TargetLowering::ConstraintWeight
23966 X86TargetLowering::getSingleConstraintMatchWeight(
23967 AsmOperandInfo &info, const char *constraint) const {
23968 ConstraintWeight weight = CW_Invalid;
23969 Value *CallOperandVal = info.CallOperandVal;
23970 // If we don't have a value, we can't do a match,
23971 // but allow it at the lowest weight.
23972 if (!CallOperandVal)
23974 Type *type = CallOperandVal->getType();
23975 // Look at the constraint type.
23976 switch (*constraint) {
23978 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23989 if (CallOperandVal->getType()->isIntegerTy())
23990 weight = CW_SpecificReg;
23995 if (type->isFloatingPointTy())
23996 weight = CW_SpecificReg;
23999 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24000 weight = CW_SpecificReg;
24004 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24005 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24006 weight = CW_Register;
24009 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24010 if (C->getZExtValue() <= 31)
24011 weight = CW_Constant;
24015 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24016 if (C->getZExtValue() <= 63)
24017 weight = CW_Constant;
24021 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24022 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24023 weight = CW_Constant;
24027 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24028 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24029 weight = CW_Constant;
24033 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24034 if (C->getZExtValue() <= 3)
24035 weight = CW_Constant;
24039 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24040 if (C->getZExtValue() <= 0xff)
24041 weight = CW_Constant;
24046 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24047 weight = CW_Constant;
24051 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24052 if ((C->getSExtValue() >= -0x80000000LL) &&
24053 (C->getSExtValue() <= 0x7fffffffLL))
24054 weight = CW_Constant;
24058 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24059 if (C->getZExtValue() <= 0xffffffff)
24060 weight = CW_Constant;
24067 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24068 /// with another that has more specific requirements based on the type of the
24069 /// corresponding operand.
24070 const char *X86TargetLowering::
24071 LowerXConstraint(EVT ConstraintVT) const {
24072 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24073 // 'f' like normal targets.
24074 if (ConstraintVT.isFloatingPoint()) {
24075 if (Subtarget->hasSSE2())
24077 if (Subtarget->hasSSE1())
24081 return TargetLowering::LowerXConstraint(ConstraintVT);
24084 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24085 /// vector. If it is invalid, don't add anything to Ops.
24086 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24087 std::string &Constraint,
24088 std::vector<SDValue>&Ops,
24089 SelectionDAG &DAG) const {
24092 // Only support length 1 constraints for now.
24093 if (Constraint.length() > 1) return;
24095 char ConstraintLetter = Constraint[0];
24096 switch (ConstraintLetter) {
24099 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24100 if (C->getZExtValue() <= 31) {
24101 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24107 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24108 if (C->getZExtValue() <= 63) {
24109 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24115 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24116 if (isInt<8>(C->getSExtValue())) {
24117 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24123 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24124 if (C->getZExtValue() <= 255) {
24125 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24131 // 32-bit signed value
24132 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24133 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24134 C->getSExtValue())) {
24135 // Widen to 64 bits here to get it sign extended.
24136 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24139 // FIXME gcc accepts some relocatable values here too, but only in certain
24140 // memory models; it's complicated.
24145 // 32-bit unsigned value
24146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24147 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24148 C->getZExtValue())) {
24149 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24153 // FIXME gcc accepts some relocatable values here too, but only in certain
24154 // memory models; it's complicated.
24158 // Literal immediates are always ok.
24159 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24160 // Widen to 64 bits here to get it sign extended.
24161 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24165 // In any sort of PIC mode addresses need to be computed at runtime by
24166 // adding in a register or some sort of table lookup. These can't
24167 // be used as immediates.
24168 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24171 // If we are in non-pic codegen mode, we allow the address of a global (with
24172 // an optional displacement) to be used with 'i'.
24173 GlobalAddressSDNode *GA = nullptr;
24174 int64_t Offset = 0;
24176 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24178 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24179 Offset += GA->getOffset();
24181 } else if (Op.getOpcode() == ISD::ADD) {
24182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24183 Offset += C->getZExtValue();
24184 Op = Op.getOperand(0);
24187 } else if (Op.getOpcode() == ISD::SUB) {
24188 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24189 Offset += -C->getZExtValue();
24190 Op = Op.getOperand(0);
24195 // Otherwise, this isn't something we can handle, reject it.
24199 const GlobalValue *GV = GA->getGlobal();
24200 // If we require an extra load to get this address, as in PIC mode, we
24201 // can't accept it.
24202 if (isGlobalStubReference(
24203 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24206 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24207 GA->getValueType(0), Offset);
24212 if (Result.getNode()) {
24213 Ops.push_back(Result);
24216 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24219 std::pair<unsigned, const TargetRegisterClass*>
24220 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24222 // First, see if this is a constraint that directly corresponds to an LLVM
24224 if (Constraint.size() == 1) {
24225 // GCC Constraint Letters
24226 switch (Constraint[0]) {
24228 // TODO: Slight differences here in allocation order and leaving
24229 // RIP in the class. Do they matter any more here than they do
24230 // in the normal allocation?
24231 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24232 if (Subtarget->is64Bit()) {
24233 if (VT == MVT::i32 || VT == MVT::f32)
24234 return std::make_pair(0U, &X86::GR32RegClass);
24235 if (VT == MVT::i16)
24236 return std::make_pair(0U, &X86::GR16RegClass);
24237 if (VT == MVT::i8 || VT == MVT::i1)
24238 return std::make_pair(0U, &X86::GR8RegClass);
24239 if (VT == MVT::i64 || VT == MVT::f64)
24240 return std::make_pair(0U, &X86::GR64RegClass);
24243 // 32-bit fallthrough
24244 case 'Q': // Q_REGS
24245 if (VT == MVT::i32 || VT == MVT::f32)
24246 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24247 if (VT == MVT::i16)
24248 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24249 if (VT == MVT::i8 || VT == MVT::i1)
24250 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24251 if (VT == MVT::i64)
24252 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24254 case 'r': // GENERAL_REGS
24255 case 'l': // INDEX_REGS
24256 if (VT == MVT::i8 || VT == MVT::i1)
24257 return std::make_pair(0U, &X86::GR8RegClass);
24258 if (VT == MVT::i16)
24259 return std::make_pair(0U, &X86::GR16RegClass);
24260 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24261 return std::make_pair(0U, &X86::GR32RegClass);
24262 return std::make_pair(0U, &X86::GR64RegClass);
24263 case 'R': // LEGACY_REGS
24264 if (VT == MVT::i8 || VT == MVT::i1)
24265 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24266 if (VT == MVT::i16)
24267 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24268 if (VT == MVT::i32 || !Subtarget->is64Bit())
24269 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24270 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24271 case 'f': // FP Stack registers.
24272 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24273 // value to the correct fpstack register class.
24274 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24275 return std::make_pair(0U, &X86::RFP32RegClass);
24276 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24277 return std::make_pair(0U, &X86::RFP64RegClass);
24278 return std::make_pair(0U, &X86::RFP80RegClass);
24279 case 'y': // MMX_REGS if MMX allowed.
24280 if (!Subtarget->hasMMX()) break;
24281 return std::make_pair(0U, &X86::VR64RegClass);
24282 case 'Y': // SSE_REGS if SSE2 allowed
24283 if (!Subtarget->hasSSE2()) break;
24285 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24286 if (!Subtarget->hasSSE1()) break;
24288 switch (VT.SimpleTy) {
24290 // Scalar SSE types.
24293 return std::make_pair(0U, &X86::FR32RegClass);
24296 return std::make_pair(0U, &X86::FR64RegClass);
24304 return std::make_pair(0U, &X86::VR128RegClass);
24312 return std::make_pair(0U, &X86::VR256RegClass);
24317 return std::make_pair(0U, &X86::VR512RegClass);
24323 // Use the default implementation in TargetLowering to convert the register
24324 // constraint into a member of a register class.
24325 std::pair<unsigned, const TargetRegisterClass*> Res;
24326 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24328 // Not found as a standard register?
24330 // Map st(0) -> st(7) -> ST0
24331 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24332 tolower(Constraint[1]) == 's' &&
24333 tolower(Constraint[2]) == 't' &&
24334 Constraint[3] == '(' &&
24335 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24336 Constraint[5] == ')' &&
24337 Constraint[6] == '}') {
24339 Res.first = X86::FP0+Constraint[4]-'0';
24340 Res.second = &X86::RFP80RegClass;
24344 // GCC allows "st(0)" to be called just plain "st".
24345 if (StringRef("{st}").equals_lower(Constraint)) {
24346 Res.first = X86::FP0;
24347 Res.second = &X86::RFP80RegClass;
24352 if (StringRef("{flags}").equals_lower(Constraint)) {
24353 Res.first = X86::EFLAGS;
24354 Res.second = &X86::CCRRegClass;
24358 // 'A' means EAX + EDX.
24359 if (Constraint == "A") {
24360 Res.first = X86::EAX;
24361 Res.second = &X86::GR32_ADRegClass;
24367 // Otherwise, check to see if this is a register class of the wrong value
24368 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24369 // turn into {ax},{dx}.
24370 if (Res.second->hasType(VT))
24371 return Res; // Correct type already, nothing to do.
24373 // All of the single-register GCC register classes map their values onto
24374 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24375 // really want an 8-bit or 32-bit register, map to the appropriate register
24376 // class and return the appropriate register.
24377 if (Res.second == &X86::GR16RegClass) {
24378 if (VT == MVT::i8 || VT == MVT::i1) {
24379 unsigned DestReg = 0;
24380 switch (Res.first) {
24382 case X86::AX: DestReg = X86::AL; break;
24383 case X86::DX: DestReg = X86::DL; break;
24384 case X86::CX: DestReg = X86::CL; break;
24385 case X86::BX: DestReg = X86::BL; break;
24388 Res.first = DestReg;
24389 Res.second = &X86::GR8RegClass;
24391 } else if (VT == MVT::i32 || VT == MVT::f32) {
24392 unsigned DestReg = 0;
24393 switch (Res.first) {
24395 case X86::AX: DestReg = X86::EAX; break;
24396 case X86::DX: DestReg = X86::EDX; break;
24397 case X86::CX: DestReg = X86::ECX; break;
24398 case X86::BX: DestReg = X86::EBX; break;
24399 case X86::SI: DestReg = X86::ESI; break;
24400 case X86::DI: DestReg = X86::EDI; break;
24401 case X86::BP: DestReg = X86::EBP; break;
24402 case X86::SP: DestReg = X86::ESP; break;
24405 Res.first = DestReg;
24406 Res.second = &X86::GR32RegClass;
24408 } else if (VT == MVT::i64 || VT == MVT::f64) {
24409 unsigned DestReg = 0;
24410 switch (Res.first) {
24412 case X86::AX: DestReg = X86::RAX; break;
24413 case X86::DX: DestReg = X86::RDX; break;
24414 case X86::CX: DestReg = X86::RCX; break;
24415 case X86::BX: DestReg = X86::RBX; break;
24416 case X86::SI: DestReg = X86::RSI; break;
24417 case X86::DI: DestReg = X86::RDI; break;
24418 case X86::BP: DestReg = X86::RBP; break;
24419 case X86::SP: DestReg = X86::RSP; break;
24422 Res.first = DestReg;
24423 Res.second = &X86::GR64RegClass;
24426 } else if (Res.second == &X86::FR32RegClass ||
24427 Res.second == &X86::FR64RegClass ||
24428 Res.second == &X86::VR128RegClass ||
24429 Res.second == &X86::VR256RegClass ||
24430 Res.second == &X86::FR32XRegClass ||
24431 Res.second == &X86::FR64XRegClass ||
24432 Res.second == &X86::VR128XRegClass ||
24433 Res.second == &X86::VR256XRegClass ||
24434 Res.second == &X86::VR512RegClass) {
24435 // Handle references to XMM physical registers that got mapped into the
24436 // wrong class. This can happen with constraints like {xmm0} where the
24437 // target independent register mapper will just pick the first match it can
24438 // find, ignoring the required type.
24440 if (VT == MVT::f32 || VT == MVT::i32)
24441 Res.second = &X86::FR32RegClass;
24442 else if (VT == MVT::f64 || VT == MVT::i64)
24443 Res.second = &X86::FR64RegClass;
24444 else if (X86::VR128RegClass.hasType(VT))
24445 Res.second = &X86::VR128RegClass;
24446 else if (X86::VR256RegClass.hasType(VT))
24447 Res.second = &X86::VR256RegClass;
24448 else if (X86::VR512RegClass.hasType(VT))
24449 Res.second = &X86::VR512RegClass;
24455 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24457 // Scaling factors are not free at all.
24458 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24459 // will take 2 allocations in the out of order engine instead of 1
24460 // for plain addressing mode, i.e. inst (reg1).
24462 // vaddps (%rsi,%drx), %ymm0, %ymm1
24463 // Requires two allocations (one for the load, one for the computation)
24465 // vaddps (%rsi), %ymm0, %ymm1
24466 // Requires just 1 allocation, i.e., freeing allocations for other operations
24467 // and having less micro operations to execute.
24469 // For some X86 architectures, this is even worse because for instance for
24470 // stores, the complex addressing mode forces the instruction to use the
24471 // "load" ports instead of the dedicated "store" port.
24472 // E.g., on Haswell:
24473 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24474 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24475 if (isLegalAddressingMode(AM, Ty))
24476 // Scale represents reg2 * scale, thus account for 1
24477 // as soon as we use a second register.
24478 return AM.Scale != 0;
24482 bool X86TargetLowering::isTargetFTOL() const {
24483 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();