1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
526 // There's never any support for operations beyond MVT::f32.
527 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
532 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
537 if (Subtarget->hasPOPCNT()) {
538 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
540 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
547 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
549 if (!Subtarget->hasMOVBE())
550 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
552 // These should be promoted to a larger select which is supported.
553 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554 // X86 wants to expand cmov itself.
555 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567 if (Subtarget->is64Bit()) {
568 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
571 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574 // support continuation, user-level threading, and etc.. As a result, no
575 // other SjLj exception interfaces are implemented and please don't build
576 // your own exception handling based on them.
577 // LLVM/Clang supports zero-cost DWARF exception handling.
578 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
582 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586 if (Subtarget->is64Bit())
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
597 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601 if (Subtarget->is64Bit()) {
602 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
607 if (Subtarget->hasSSE1())
608 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
610 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
612 // Expand certain atomics
613 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
615 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
620 if (Subtarget->hasCmpxchg16b()) {
621 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
624 // FIXME - use subtarget debug flags
625 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
630 if (Subtarget->is64Bit()) {
631 setExceptionPointerRegister(X86::RAX);
632 setExceptionSelectorRegister(X86::RDX);
634 setExceptionPointerRegister(X86::EAX);
635 setExceptionSelectorRegister(X86::EDX);
637 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
640 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
643 setOperationAction(ISD::TRAP, MVT::Other, Legal);
644 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
646 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647 setOperationAction(ISD::VASTART , MVT::Other, Custom);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650 // TargetInfo::X86_64ABIBuiltinVaList
651 setOperationAction(ISD::VAARG , MVT::Other, Custom);
652 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
654 // TargetInfo::CharPtrBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Expand);
656 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
662 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
664 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
665 // f32 and f64 use SSE.
666 // Set up the FP register classes.
667 addRegisterClass(MVT::f32, &X86::FR32RegClass);
668 addRegisterClass(MVT::f64, &X86::FR64RegClass);
670 // Use ANDPD to simulate FABS.
671 setOperationAction(ISD::FABS , MVT::f64, Custom);
672 setOperationAction(ISD::FABS , MVT::f32, Custom);
674 // Use XORP to simulate FNEG.
675 setOperationAction(ISD::FNEG , MVT::f64, Custom);
676 setOperationAction(ISD::FNEG , MVT::f32, Custom);
678 // Use ANDPD and ORPD to simulate FCOPYSIGN.
679 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
680 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
682 // Lower this to FGETSIGNx86 plus an AND.
683 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
684 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
686 // We don't support sin/cos/fmod
687 setOperationAction(ISD::FSIN , MVT::f64, Expand);
688 setOperationAction(ISD::FCOS , MVT::f64, Expand);
689 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
690 setOperationAction(ISD::FSIN , MVT::f32, Expand);
691 setOperationAction(ISD::FCOS , MVT::f32, Expand);
692 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
694 // Expand FP immediates into loads from the stack, except for the special
696 addLegalFPImmediate(APFloat(+0.0)); // xorpd
697 addLegalFPImmediate(APFloat(+0.0f)); // xorps
698 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
699 // Use SSE for f32, x87 for f64.
700 // Set up the FP register classes.
701 addRegisterClass(MVT::f32, &X86::FR32RegClass);
702 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
704 // Use ANDPS to simulate FABS.
705 setOperationAction(ISD::FABS , MVT::f32, Custom);
707 // Use XORP to simulate FNEG.
708 setOperationAction(ISD::FNEG , MVT::f32, Custom);
710 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
712 // Use ANDPS and ORPS to simulate FCOPYSIGN.
713 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
714 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
716 // We don't support sin/cos/fmod
717 setOperationAction(ISD::FSIN , MVT::f32, Expand);
718 setOperationAction(ISD::FCOS , MVT::f32, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
721 // Special cases we handle for FP constants.
722 addLegalFPImmediate(APFloat(+0.0f)); // xorps
723 addLegalFPImmediate(APFloat(+0.0)); // FLD0
724 addLegalFPImmediate(APFloat(+1.0)); // FLD1
725 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
726 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
728 if (!TM.Options.UnsafeFPMath) {
729 setOperationAction(ISD::FSIN , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
733 } else if (!TM.Options.UseSoftFloat) {
734 // f32 and f64 in x87.
735 // Set up the FP register classes.
736 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
737 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
739 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
740 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
741 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
744 if (!TM.Options.UnsafeFPMath) {
745 setOperationAction(ISD::FSIN , MVT::f64, Expand);
746 setOperationAction(ISD::FSIN , MVT::f32, Expand);
747 setOperationAction(ISD::FCOS , MVT::f64, Expand);
748 setOperationAction(ISD::FCOS , MVT::f32, Expand);
749 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
752 addLegalFPImmediate(APFloat(+0.0)); // FLD0
753 addLegalFPImmediate(APFloat(+1.0)); // FLD1
754 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
755 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
756 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
762 // We don't support FMA.
763 setOperationAction(ISD::FMA, MVT::f64, Expand);
764 setOperationAction(ISD::FMA, MVT::f32, Expand);
766 // Long double always uses X87.
767 if (!TM.Options.UseSoftFloat) {
768 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
769 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
770 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
772 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
773 addLegalFPImmediate(TmpFlt); // FLD0
775 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
778 APFloat TmpFlt2(+1.0);
779 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
781 addLegalFPImmediate(TmpFlt2); // FLD1
782 TmpFlt2.changeSign();
783 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
786 if (!TM.Options.UnsafeFPMath) {
787 setOperationAction(ISD::FSIN , MVT::f80, Expand);
788 setOperationAction(ISD::FCOS , MVT::f80, Expand);
789 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
792 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
793 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
794 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
795 setOperationAction(ISD::FRINT, MVT::f80, Expand);
796 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
797 setOperationAction(ISD::FMA, MVT::f80, Expand);
800 // Always use a library call for pow.
801 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
802 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
805 setOperationAction(ISD::FLOG, MVT::f80, Expand);
806 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
808 setOperationAction(ISD::FEXP, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
811 // First set operation action for all vector types to either promote
812 // (for widening) or expand (for scalarization). Then we will selectively
813 // turn on ones that can be effectively codegen'd.
814 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
815 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
816 MVT VT = (MVT::SimpleValueType)i;
817 setOperationAction(ISD::ADD , VT, Expand);
818 setOperationAction(ISD::SUB , VT, Expand);
819 setOperationAction(ISD::FADD, VT, Expand);
820 setOperationAction(ISD::FNEG, VT, Expand);
821 setOperationAction(ISD::FSUB, VT, Expand);
822 setOperationAction(ISD::MUL , VT, Expand);
823 setOperationAction(ISD::FMUL, VT, Expand);
824 setOperationAction(ISD::SDIV, VT, Expand);
825 setOperationAction(ISD::UDIV, VT, Expand);
826 setOperationAction(ISD::FDIV, VT, Expand);
827 setOperationAction(ISD::SREM, VT, Expand);
828 setOperationAction(ISD::UREM, VT, Expand);
829 setOperationAction(ISD::LOAD, VT, Expand);
830 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
833 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
834 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::FABS, VT, Expand);
836 setOperationAction(ISD::FSIN, VT, Expand);
837 setOperationAction(ISD::FSINCOS, VT, Expand);
838 setOperationAction(ISD::FCOS, VT, Expand);
839 setOperationAction(ISD::FSINCOS, VT, Expand);
840 setOperationAction(ISD::FREM, VT, Expand);
841 setOperationAction(ISD::FMA, VT, Expand);
842 setOperationAction(ISD::FPOWI, VT, Expand);
843 setOperationAction(ISD::FSQRT, VT, Expand);
844 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
845 setOperationAction(ISD::FFLOOR, VT, Expand);
846 setOperationAction(ISD::FCEIL, VT, Expand);
847 setOperationAction(ISD::FTRUNC, VT, Expand);
848 setOperationAction(ISD::FRINT, VT, Expand);
849 setOperationAction(ISD::FNEARBYINT, VT, Expand);
850 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
851 setOperationAction(ISD::MULHS, VT, Expand);
852 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
853 setOperationAction(ISD::MULHU, VT, Expand);
854 setOperationAction(ISD::SDIVREM, VT, Expand);
855 setOperationAction(ISD::UDIVREM, VT, Expand);
856 setOperationAction(ISD::FPOW, VT, Expand);
857 setOperationAction(ISD::CTPOP, VT, Expand);
858 setOperationAction(ISD::CTTZ, VT, Expand);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
860 setOperationAction(ISD::CTLZ, VT, Expand);
861 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
862 setOperationAction(ISD::SHL, VT, Expand);
863 setOperationAction(ISD::SRA, VT, Expand);
864 setOperationAction(ISD::SRL, VT, Expand);
865 setOperationAction(ISD::ROTL, VT, Expand);
866 setOperationAction(ISD::ROTR, VT, Expand);
867 setOperationAction(ISD::BSWAP, VT, Expand);
868 setOperationAction(ISD::SETCC, VT, Expand);
869 setOperationAction(ISD::FLOG, VT, Expand);
870 setOperationAction(ISD::FLOG2, VT, Expand);
871 setOperationAction(ISD::FLOG10, VT, Expand);
872 setOperationAction(ISD::FEXP, VT, Expand);
873 setOperationAction(ISD::FEXP2, VT, Expand);
874 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
875 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
876 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
877 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
879 setOperationAction(ISD::TRUNCATE, VT, Expand);
880 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
881 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
882 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
883 setOperationAction(ISD::VSELECT, VT, Expand);
884 setOperationAction(ISD::SELECT_CC, VT, Expand);
885 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
886 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
887 setTruncStoreAction(VT,
888 (MVT::SimpleValueType)InnerVT, Expand);
889 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
890 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
892 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
893 // we have to deal with them whether we ask for Expansion or not. Setting
894 // Expand causes its own optimisation problems though, so leave them legal.
895 if (VT.getVectorElementType() == MVT::i1)
896 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
899 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
900 // with -msoft-float, disable use of MMX as well.
901 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
902 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
903 // No operations on x86mmx supported, everything uses intrinsics.
906 // MMX-sized vectors (other than x86mmx) are expected to be expanded
907 // into smaller operations.
908 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
909 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
910 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
911 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
912 setOperationAction(ISD::AND, MVT::v8i8, Expand);
913 setOperationAction(ISD::AND, MVT::v4i16, Expand);
914 setOperationAction(ISD::AND, MVT::v2i32, Expand);
915 setOperationAction(ISD::AND, MVT::v1i64, Expand);
916 setOperationAction(ISD::OR, MVT::v8i8, Expand);
917 setOperationAction(ISD::OR, MVT::v4i16, Expand);
918 setOperationAction(ISD::OR, MVT::v2i32, Expand);
919 setOperationAction(ISD::OR, MVT::v1i64, Expand);
920 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
921 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
922 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
923 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
929 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
930 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
931 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
932 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
933 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
938 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
939 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
941 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
942 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
943 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
944 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
945 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
946 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
947 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
948 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
949 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
950 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
951 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
952 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
955 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
956 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
959 // registers cannot be used even for integer operations.
960 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
961 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
962 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
963 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
966 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
967 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
968 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
969 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
970 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
971 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
972 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
974 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
975 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
976 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
977 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
978 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
979 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
980 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
981 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
982 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
983 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
984 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
985 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
986 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
990 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
991 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1000 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1001 MVT VT = (MVT::SimpleValueType)i;
1002 // Do not attempt to custom lower non-power-of-2 vectors
1003 if (!isPowerOf2_32(VT.getVectorNumElements()))
1005 // Do not attempt to custom lower non-128-bit vectors
1006 if (!VT.is128BitVector())
1008 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1009 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1013 // We support custom legalizing of sext and anyext loads for specific
1014 // memory vector types which we can load as a scalar (or sequence of
1015 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1016 // loads these must work with a single scalar load.
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1018 if (Subtarget->is64Bit()) {
1019 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1029 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1031 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1033 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1034 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1036 if (Subtarget->is64Bit()) {
1037 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1042 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1043 MVT VT = (MVT::SimpleValueType)i;
1045 // Do not attempt to promote non-128-bit vectors
1046 if (!VT.is128BitVector())
1049 setOperationAction(ISD::AND, VT, Promote);
1050 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1051 setOperationAction(ISD::OR, VT, Promote);
1052 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1053 setOperationAction(ISD::XOR, VT, Promote);
1054 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1055 setOperationAction(ISD::LOAD, VT, Promote);
1056 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1057 setOperationAction(ISD::SELECT, VT, Promote);
1058 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1531 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1534 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1535 // of this type with custom code.
1536 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1537 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1538 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1542 // We want to custom lower some of our intrinsics.
1543 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1544 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1545 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1546 if (!Subtarget->is64Bit())
1547 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1549 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1550 // handle type legalization for these operations here.
1552 // FIXME: We really should do custom legalization for addition and
1553 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1554 // than generic legalization for 64-bit multiplication-with-overflow, though.
1555 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1556 // Add/Sub/Mul with overflow operations are custom lowered.
1558 setOperationAction(ISD::SADDO, VT, Custom);
1559 setOperationAction(ISD::UADDO, VT, Custom);
1560 setOperationAction(ISD::SSUBO, VT, Custom);
1561 setOperationAction(ISD::USUBO, VT, Custom);
1562 setOperationAction(ISD::SMULO, VT, Custom);
1563 setOperationAction(ISD::UMULO, VT, Custom);
1566 // There are no 8-bit 3-address imul/mul instructions
1567 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1568 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1570 if (!Subtarget->is64Bit()) {
1571 // These libcalls are not available in 32-bit.
1572 setLibcallName(RTLIB::SHL_I128, nullptr);
1573 setLibcallName(RTLIB::SRL_I128, nullptr);
1574 setLibcallName(RTLIB::SRA_I128, nullptr);
1577 // Combine sin / cos into one node or libcall if possible.
1578 if (Subtarget->hasSinCos()) {
1579 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1580 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1581 if (Subtarget->isTargetDarwin()) {
1582 // For MacOSX, we don't want to the normal expansion of a libcall to
1583 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1585 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1586 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1590 if (Subtarget->isTargetWin64()) {
1591 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1592 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1593 setOperationAction(ISD::SREM, MVT::i128, Custom);
1594 setOperationAction(ISD::UREM, MVT::i128, Custom);
1595 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1596 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1599 // We have target-specific dag combine patterns for the following nodes:
1600 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1601 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1602 setTargetDAGCombine(ISD::VSELECT);
1603 setTargetDAGCombine(ISD::SELECT);
1604 setTargetDAGCombine(ISD::SHL);
1605 setTargetDAGCombine(ISD::SRA);
1606 setTargetDAGCombine(ISD::SRL);
1607 setTargetDAGCombine(ISD::OR);
1608 setTargetDAGCombine(ISD::AND);
1609 setTargetDAGCombine(ISD::ADD);
1610 setTargetDAGCombine(ISD::FADD);
1611 setTargetDAGCombine(ISD::FSUB);
1612 setTargetDAGCombine(ISD::FMA);
1613 setTargetDAGCombine(ISD::SUB);
1614 setTargetDAGCombine(ISD::LOAD);
1615 setTargetDAGCombine(ISD::STORE);
1616 setTargetDAGCombine(ISD::ZERO_EXTEND);
1617 setTargetDAGCombine(ISD::ANY_EXTEND);
1618 setTargetDAGCombine(ISD::SIGN_EXTEND);
1619 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1620 setTargetDAGCombine(ISD::TRUNCATE);
1621 setTargetDAGCombine(ISD::SINT_TO_FP);
1622 setTargetDAGCombine(ISD::SETCC);
1623 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1624 setTargetDAGCombine(ISD::BUILD_VECTOR);
1625 if (Subtarget->is64Bit())
1626 setTargetDAGCombine(ISD::MUL);
1627 setTargetDAGCombine(ISD::XOR);
1629 computeRegisterProperties();
1631 // On Darwin, -Os means optimize for size without hurting performance,
1632 // do not reduce the limit.
1633 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1634 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1635 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1636 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1637 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1638 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1639 setPrefLoopAlignment(4); // 2^4 bytes.
1641 // Predictable cmov don't hurt on atom because it's in-order.
1642 PredictableSelectIsExpensive = !Subtarget->isAtom();
1644 setPrefFunctionAlignment(4); // 2^4 bytes.
1647 // This has so far only been implemented for 64-bit MachO.
1648 bool X86TargetLowering::useLoadStackGuardNode() const {
1649 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1650 Subtarget->is64Bit();
1653 TargetLoweringBase::LegalizeTypeAction
1654 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1655 if (ExperimentalVectorWideningLegalization &&
1656 VT.getVectorNumElements() != 1 &&
1657 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1658 return TypeWidenVector;
1660 return TargetLoweringBase::getPreferredVectorAction(VT);
1663 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1665 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1667 if (Subtarget->hasAVX512())
1668 switch(VT.getVectorNumElements()) {
1669 case 8: return MVT::v8i1;
1670 case 16: return MVT::v16i1;
1673 return VT.changeVectorElementTypeToInteger();
1676 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1677 /// the desired ByVal argument alignment.
1678 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1681 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1682 if (VTy->getBitWidth() == 128)
1684 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1685 unsigned EltAlign = 0;
1686 getMaxByValAlign(ATy->getElementType(), EltAlign);
1687 if (EltAlign > MaxAlign)
1688 MaxAlign = EltAlign;
1689 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1690 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1691 unsigned EltAlign = 0;
1692 getMaxByValAlign(STy->getElementType(i), EltAlign);
1693 if (EltAlign > MaxAlign)
1694 MaxAlign = EltAlign;
1701 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1702 /// function arguments in the caller parameter area. For X86, aggregates
1703 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1704 /// are at 4-byte boundaries.
1705 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1706 if (Subtarget->is64Bit()) {
1707 // Max of 8 and alignment of type.
1708 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1715 if (Subtarget->hasSSE1())
1716 getMaxByValAlign(Ty, Align);
1720 /// getOptimalMemOpType - Returns the target specific optimal type for load
1721 /// and store operations as a result of memset, memcpy, and memmove
1722 /// lowering. If DstAlign is zero that means it's safe to destination
1723 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1724 /// means there isn't a need to check it against alignment requirement,
1725 /// probably because the source does not need to be loaded. If 'IsMemset' is
1726 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1727 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1728 /// source is constant so it does not need to be loaded.
1729 /// It returns EVT::Other if the type should be determined using generic
1730 /// target-independent logic.
1732 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1733 unsigned DstAlign, unsigned SrcAlign,
1734 bool IsMemset, bool ZeroMemset,
1736 MachineFunction &MF) const {
1737 const Function *F = MF.getFunction();
1738 if ((!IsMemset || ZeroMemset) &&
1739 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1740 Attribute::NoImplicitFloat)) {
1742 (Subtarget->isUnalignedMemAccessFast() ||
1743 ((DstAlign == 0 || DstAlign >= 16) &&
1744 (SrcAlign == 0 || SrcAlign >= 16)))) {
1746 if (Subtarget->hasInt256())
1748 if (Subtarget->hasFp256())
1751 if (Subtarget->hasSSE2())
1753 if (Subtarget->hasSSE1())
1755 } else if (!MemcpyStrSrc && Size >= 8 &&
1756 !Subtarget->is64Bit() &&
1757 Subtarget->hasSSE2()) {
1758 // Do not use f64 to lower memcpy if source is string constant. It's
1759 // better to use i32 to avoid the loads.
1763 if (Subtarget->is64Bit() && Size >= 8)
1768 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1770 return X86ScalarSSEf32;
1771 else if (VT == MVT::f64)
1772 return X86ScalarSSEf64;
1777 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1782 *Fast = Subtarget->isUnalignedMemAccessFast();
1786 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1787 /// current function. The returned value is a member of the
1788 /// MachineJumpTableInfo::JTEntryKind enum.
1789 unsigned X86TargetLowering::getJumpTableEncoding() const {
1790 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1792 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1793 Subtarget->isPICStyleGOT())
1794 return MachineJumpTableInfo::EK_Custom32;
1796 // Otherwise, use the normal jump table encoding heuristics.
1797 return TargetLowering::getJumpTableEncoding();
1801 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1802 const MachineBasicBlock *MBB,
1803 unsigned uid,MCContext &Ctx) const{
1804 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1805 Subtarget->isPICStyleGOT());
1806 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1808 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1809 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1812 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1814 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1815 SelectionDAG &DAG) const {
1816 if (!Subtarget->is64Bit())
1817 // This doesn't have SDLoc associated with it, but is not really the
1818 // same as a Register.
1819 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1823 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1824 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1826 const MCExpr *X86TargetLowering::
1827 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1828 MCContext &Ctx) const {
1829 // X86-64 uses RIP relative addressing based on the jump table label.
1830 if (Subtarget->isPICStyleRIPRel())
1831 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1833 // Otherwise, the reference is relative to the PIC base.
1834 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1837 // FIXME: Why this routine is here? Move to RegInfo!
1838 std::pair<const TargetRegisterClass*, uint8_t>
1839 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1840 const TargetRegisterClass *RRC = nullptr;
1842 switch (VT.SimpleTy) {
1844 return TargetLowering::findRepresentativeClass(VT);
1845 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1846 RRC = Subtarget->is64Bit() ?
1847 (const TargetRegisterClass*)&X86::GR64RegClass :
1848 (const TargetRegisterClass*)&X86::GR32RegClass;
1851 RRC = &X86::VR64RegClass;
1853 case MVT::f32: case MVT::f64:
1854 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1855 case MVT::v4f32: case MVT::v2f64:
1856 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1858 RRC = &X86::VR128RegClass;
1861 return std::make_pair(RRC, Cost);
1864 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1865 unsigned &Offset) const {
1866 if (!Subtarget->isTargetLinux())
1869 if (Subtarget->is64Bit()) {
1870 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1872 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1884 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1885 unsigned DestAS) const {
1886 assert(SrcAS != DestAS && "Expected different address spaces!");
1888 return SrcAS < 256 && DestAS < 256;
1891 //===----------------------------------------------------------------------===//
1892 // Return Value Calling Convention Implementation
1893 //===----------------------------------------------------------------------===//
1895 #include "X86GenCallingConv.inc"
1898 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1899 MachineFunction &MF, bool isVarArg,
1900 const SmallVectorImpl<ISD::OutputArg> &Outs,
1901 LLVMContext &Context) const {
1902 SmallVector<CCValAssign, 16> RVLocs;
1903 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1904 return CCInfo.CheckReturn(Outs, RetCC_X86);
1907 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1908 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1913 X86TargetLowering::LowerReturn(SDValue Chain,
1914 CallingConv::ID CallConv, bool isVarArg,
1915 const SmallVectorImpl<ISD::OutputArg> &Outs,
1916 const SmallVectorImpl<SDValue> &OutVals,
1917 SDLoc dl, SelectionDAG &DAG) const {
1918 MachineFunction &MF = DAG.getMachineFunction();
1919 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1921 SmallVector<CCValAssign, 16> RVLocs;
1922 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1923 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1926 SmallVector<SDValue, 6> RetOps;
1927 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1928 // Operand #1 = Bytes To Pop
1929 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1932 // Copy the result values into the output registers.
1933 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1934 CCValAssign &VA = RVLocs[i];
1935 assert(VA.isRegLoc() && "Can only return in registers!");
1936 SDValue ValToCopy = OutVals[i];
1937 EVT ValVT = ValToCopy.getValueType();
1939 // Promote values to the appropriate types
1940 if (VA.getLocInfo() == CCValAssign::SExt)
1941 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1942 else if (VA.getLocInfo() == CCValAssign::ZExt)
1943 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1944 else if (VA.getLocInfo() == CCValAssign::AExt)
1945 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1946 else if (VA.getLocInfo() == CCValAssign::BCvt)
1947 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1949 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1950 "Unexpected FP-extend for return value.");
1952 // If this is x86-64, and we disabled SSE, we can't return FP values,
1953 // or SSE or MMX vectors.
1954 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1955 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1956 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1957 report_fatal_error("SSE register return with SSE disabled");
1959 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1960 // llvm-gcc has never done it right and no one has noticed, so this
1961 // should be OK for now.
1962 if (ValVT == MVT::f64 &&
1963 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1964 report_fatal_error("SSE2 register return with SSE2 disabled");
1966 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1967 // the RET instruction and handled by the FP Stackifier.
1968 if (VA.getLocReg() == X86::FP0 ||
1969 VA.getLocReg() == X86::FP1) {
1970 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1971 // change the value to the FP stack register class.
1972 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1973 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1974 RetOps.push_back(ValToCopy);
1975 // Don't emit a copytoreg.
1979 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1980 // which is returned in RAX / RDX.
1981 if (Subtarget->is64Bit()) {
1982 if (ValVT == MVT::x86mmx) {
1983 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1984 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1985 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1987 // If we don't have SSE2 available, convert to v4f32 so the generated
1988 // register is legal.
1989 if (!Subtarget->hasSSE2())
1990 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1995 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1996 Flag = Chain.getValue(1);
1997 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2000 // The x86-64 ABIs require that for returning structs by value we copy
2001 // the sret argument into %rax/%eax (depending on ABI) for the return.
2002 // Win32 requires us to put the sret argument to %eax as well.
2003 // We saved the argument into a virtual register in the entry block,
2004 // so now we copy the value out and into %rax/%eax.
2005 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2006 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2007 MachineFunction &MF = DAG.getMachineFunction();
2008 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2009 unsigned Reg = FuncInfo->getSRetReturnReg();
2011 "SRetReturnReg should have been set in LowerFormalArguments().");
2012 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2015 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2016 X86::RAX : X86::EAX;
2017 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2018 Flag = Chain.getValue(1);
2020 // RAX/EAX now acts like a return value.
2021 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2024 RetOps[0] = Chain; // Update chain.
2026 // Add the flag if we have it.
2028 RetOps.push_back(Flag);
2030 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2033 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2034 if (N->getNumValues() != 1)
2036 if (!N->hasNUsesOfValue(1, 0))
2039 SDValue TCChain = Chain;
2040 SDNode *Copy = *N->use_begin();
2041 if (Copy->getOpcode() == ISD::CopyToReg) {
2042 // If the copy has a glue operand, we conservatively assume it isn't safe to
2043 // perform a tail call.
2044 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2046 TCChain = Copy->getOperand(0);
2047 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2050 bool HasRet = false;
2051 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2053 if (UI->getOpcode() != X86ISD::RET_FLAG)
2055 // If we are returning more than one value, we can definitely
2056 // not make a tail call see PR19530
2057 if (UI->getNumOperands() > 4)
2059 if (UI->getNumOperands() == 4 &&
2060 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2073 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2074 ISD::NodeType ExtendKind) const {
2076 // TODO: Is this also valid on 32-bit?
2077 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2078 ReturnMVT = MVT::i8;
2080 ReturnMVT = MVT::i32;
2082 EVT MinVT = getRegisterType(Context, ReturnMVT);
2083 return VT.bitsLT(MinVT) ? MinVT : VT;
2086 /// LowerCallResult - Lower the result values of a call into the
2087 /// appropriate copies out of appropriate physical registers.
2090 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2091 CallingConv::ID CallConv, bool isVarArg,
2092 const SmallVectorImpl<ISD::InputArg> &Ins,
2093 SDLoc dl, SelectionDAG &DAG,
2094 SmallVectorImpl<SDValue> &InVals) const {
2096 // Assign locations to each value returned by this call.
2097 SmallVector<CCValAssign, 16> RVLocs;
2098 bool Is64Bit = Subtarget->is64Bit();
2099 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2101 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2103 // Copy all of the result registers out of their specified physreg.
2104 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2105 CCValAssign &VA = RVLocs[i];
2106 EVT CopyVT = VA.getValVT();
2108 // If this is x86-64, and we disabled SSE, we can't return FP values
2109 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2110 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2111 report_fatal_error("SSE register return with SSE disabled");
2114 // If we prefer to use the value in xmm registers, copy it out as f80 and
2115 // use a truncate to move it from fp stack reg to xmm reg.
2116 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2117 isScalarFPTypeInSSEReg(VA.getValVT()))
2120 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2121 CopyVT, InFlag).getValue(1);
2122 SDValue Val = Chain.getValue(0);
2124 if (CopyVT != VA.getValVT())
2125 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2126 // This truncation won't change the value.
2127 DAG.getIntPtrConstant(1));
2129 InFlag = Chain.getValue(2);
2130 InVals.push_back(Val);
2136 //===----------------------------------------------------------------------===//
2137 // C & StdCall & Fast Calling Convention implementation
2138 //===----------------------------------------------------------------------===//
2139 // StdCall calling convention seems to be standard for many Windows' API
2140 // routines and around. It differs from C calling convention just a little:
2141 // callee should clean up the stack, not caller. Symbols should be also
2142 // decorated in some fancy way :) It doesn't support any vector arguments.
2143 // For info on fast calling convention see Fast Calling Convention (tail call)
2144 // implementation LowerX86_32FastCCCallTo.
2146 /// CallIsStructReturn - Determines whether a call uses struct return
2148 enum StructReturnType {
2153 static StructReturnType
2154 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2156 return NotStructReturn;
2158 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2159 if (!Flags.isSRet())
2160 return NotStructReturn;
2161 if (Flags.isInReg())
2162 return RegStructReturn;
2163 return StackStructReturn;
2166 /// ArgsAreStructReturn - Determines whether a function uses struct
2167 /// return semantics.
2168 static StructReturnType
2169 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2171 return NotStructReturn;
2173 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2174 if (!Flags.isSRet())
2175 return NotStructReturn;
2176 if (Flags.isInReg())
2177 return RegStructReturn;
2178 return StackStructReturn;
2181 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2182 /// by "Src" to address "Dst" with size and alignment information specified by
2183 /// the specific parameter attribute. The copy will be passed as a byval
2184 /// function parameter.
2186 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2187 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2189 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2191 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2192 /*isVolatile*/false, /*AlwaysInline=*/true,
2193 MachinePointerInfo(), MachinePointerInfo());
2196 /// IsTailCallConvention - Return true if the calling convention is one that
2197 /// supports tail call optimization.
2198 static bool IsTailCallConvention(CallingConv::ID CC) {
2199 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2200 CC == CallingConv::HiPE);
2203 /// \brief Return true if the calling convention is a C calling convention.
2204 static bool IsCCallConvention(CallingConv::ID CC) {
2205 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2206 CC == CallingConv::X86_64_SysV);
2209 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2210 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2214 CallingConv::ID CalleeCC = CS.getCallingConv();
2215 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2221 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2222 /// a tailcall target by changing its ABI.
2223 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2224 bool GuaranteedTailCallOpt) {
2225 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2229 X86TargetLowering::LowerMemArgument(SDValue Chain,
2230 CallingConv::ID CallConv,
2231 const SmallVectorImpl<ISD::InputArg> &Ins,
2232 SDLoc dl, SelectionDAG &DAG,
2233 const CCValAssign &VA,
2234 MachineFrameInfo *MFI,
2236 // Create the nodes corresponding to a load from this parameter slot.
2237 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2238 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2239 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2240 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2243 // If value is passed by pointer we have address passed instead of the value
2245 if (VA.getLocInfo() == CCValAssign::Indirect)
2246 ValVT = VA.getLocVT();
2248 ValVT = VA.getValVT();
2250 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2251 // changed with more analysis.
2252 // In case of tail call optimization mark all arguments mutable. Since they
2253 // could be overwritten by lowering of arguments in case of a tail call.
2254 if (Flags.isByVal()) {
2255 unsigned Bytes = Flags.getByValSize();
2256 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2257 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2258 return DAG.getFrameIndex(FI, getPointerTy());
2260 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2261 VA.getLocMemOffset(), isImmutable);
2262 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2263 return DAG.getLoad(ValVT, dl, Chain, FIN,
2264 MachinePointerInfo::getFixedStack(FI),
2265 false, false, false, 0);
2270 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2271 CallingConv::ID CallConv,
2273 const SmallVectorImpl<ISD::InputArg> &Ins,
2276 SmallVectorImpl<SDValue> &InVals)
2278 MachineFunction &MF = DAG.getMachineFunction();
2279 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2281 const Function* Fn = MF.getFunction();
2282 if (Fn->hasExternalLinkage() &&
2283 Subtarget->isTargetCygMing() &&
2284 Fn->getName() == "main")
2285 FuncInfo->setForceFramePointer(true);
2287 MachineFrameInfo *MFI = MF.getFrameInfo();
2288 bool Is64Bit = Subtarget->is64Bit();
2289 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2291 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2292 "Var args not supported with calling convention fastcc, ghc or hipe");
2294 // Assign locations to all of the incoming arguments.
2295 SmallVector<CCValAssign, 16> ArgLocs;
2296 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2298 // Allocate shadow area for Win64
2300 CCInfo.AllocateStack(32, 8);
2302 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2303 CCInfo.AlignStack(Is64Bit ? 8 : 4);
2305 unsigned LastVal = ~0U;
2307 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2308 CCValAssign &VA = ArgLocs[i];
2309 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2311 assert(VA.getValNo() != LastVal &&
2312 "Don't support value assigned to multiple locs yet");
2314 LastVal = VA.getValNo();
2316 if (VA.isRegLoc()) {
2317 EVT RegVT = VA.getLocVT();
2318 const TargetRegisterClass *RC;
2319 if (RegVT == MVT::i32)
2320 RC = &X86::GR32RegClass;
2321 else if (Is64Bit && RegVT == MVT::i64)
2322 RC = &X86::GR64RegClass;
2323 else if (RegVT == MVT::f32)
2324 RC = &X86::FR32RegClass;
2325 else if (RegVT == MVT::f64)
2326 RC = &X86::FR64RegClass;
2327 else if (RegVT.is512BitVector())
2328 RC = &X86::VR512RegClass;
2329 else if (RegVT.is256BitVector())
2330 RC = &X86::VR256RegClass;
2331 else if (RegVT.is128BitVector())
2332 RC = &X86::VR128RegClass;
2333 else if (RegVT == MVT::x86mmx)
2334 RC = &X86::VR64RegClass;
2335 else if (RegVT == MVT::i1)
2336 RC = &X86::VK1RegClass;
2337 else if (RegVT == MVT::v8i1)
2338 RC = &X86::VK8RegClass;
2339 else if (RegVT == MVT::v16i1)
2340 RC = &X86::VK16RegClass;
2341 else if (RegVT == MVT::v32i1)
2342 RC = &X86::VK32RegClass;
2343 else if (RegVT == MVT::v64i1)
2344 RC = &X86::VK64RegClass;
2346 llvm_unreachable("Unknown argument type!");
2348 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2349 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2351 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2352 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2354 if (VA.getLocInfo() == CCValAssign::SExt)
2355 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2356 DAG.getValueType(VA.getValVT()));
2357 else if (VA.getLocInfo() == CCValAssign::ZExt)
2358 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2359 DAG.getValueType(VA.getValVT()));
2360 else if (VA.getLocInfo() == CCValAssign::BCvt)
2361 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2363 if (VA.isExtInLoc()) {
2364 // Handle MMX values passed in XMM regs.
2365 if (RegVT.isVector())
2366 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2368 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2371 assert(VA.isMemLoc());
2372 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2375 // If value is passed via pointer - do a load.
2376 if (VA.getLocInfo() == CCValAssign::Indirect)
2377 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2378 MachinePointerInfo(), false, false, false, 0);
2380 InVals.push_back(ArgValue);
2383 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2384 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2385 // The x86-64 ABIs require that for returning structs by value we copy
2386 // the sret argument into %rax/%eax (depending on ABI) for the return.
2387 // Win32 requires us to put the sret argument to %eax as well.
2388 // Save the argument into a virtual register so that we can access it
2389 // from the return points.
2390 if (Ins[i].Flags.isSRet()) {
2391 unsigned Reg = FuncInfo->getSRetReturnReg();
2393 MVT PtrTy = getPointerTy();
2394 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2395 FuncInfo->setSRetReturnReg(Reg);
2397 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2398 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2404 unsigned StackSize = CCInfo.getNextStackOffset();
2405 // Align stack specially for tail calls.
2406 if (FuncIsMadeTailCallSafe(CallConv,
2407 MF.getTarget().Options.GuaranteedTailCallOpt))
2408 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2410 // If the function takes variable number of arguments, make a frame index for
2411 // the start of the first vararg value... for expansion of llvm.va_start.
2413 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2414 CallConv != CallingConv::X86_ThisCall)) {
2415 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2418 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2420 // FIXME: We should really autogenerate these arrays
2421 static const MCPhysReg GPR64ArgRegsWin64[] = {
2422 X86::RCX, X86::RDX, X86::R8, X86::R9
2424 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2425 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2427 static const MCPhysReg XMMArgRegs64Bit[] = {
2428 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2429 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2431 const MCPhysReg *GPR64ArgRegs;
2432 unsigned NumXMMRegs = 0;
2435 // The XMM registers which might contain var arg parameters are shadowed
2436 // in their paired GPR. So we only need to save the GPR to their home
2438 TotalNumIntRegs = 4;
2439 GPR64ArgRegs = GPR64ArgRegsWin64;
2441 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2442 GPR64ArgRegs = GPR64ArgRegs64Bit;
2444 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2447 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2450 bool NoImplicitFloatOps = Fn->getAttributes().
2451 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2452 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2453 "SSE register cannot be used when SSE is disabled!");
2454 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2455 NoImplicitFloatOps) &&
2456 "SSE register cannot be used when SSE is disabled!");
2457 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2458 !Subtarget->hasSSE1())
2459 // Kernel mode asks for SSE to be disabled, so don't push them
2461 TotalNumXMMRegs = 0;
2464 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2465 // Get to the caller-allocated home save location. Add 8 to account
2466 // for the return address.
2467 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2468 FuncInfo->setRegSaveFrameIndex(
2469 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2470 // Fixup to set vararg frame on shadow area (4 x i64).
2472 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2474 // For X86-64, if there are vararg parameters that are passed via
2475 // registers, then we must store them to their spots on the stack so
2476 // they may be loaded by deferencing the result of va_next.
2477 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2478 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2479 FuncInfo->setRegSaveFrameIndex(
2480 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2484 // Store the integer parameter registers.
2485 SmallVector<SDValue, 8> MemOps;
2486 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2488 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2489 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2490 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2491 DAG.getIntPtrConstant(Offset));
2492 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2493 &X86::GR64RegClass);
2494 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2496 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2497 MachinePointerInfo::getFixedStack(
2498 FuncInfo->getRegSaveFrameIndex(), Offset),
2500 MemOps.push_back(Store);
2504 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2505 // Now store the XMM (fp + vector) parameter registers.
2506 SmallVector<SDValue, 12> SaveXMMOps;
2507 SaveXMMOps.push_back(Chain);
2509 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2510 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2511 SaveXMMOps.push_back(ALVal);
2513 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2514 FuncInfo->getRegSaveFrameIndex()));
2515 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2516 FuncInfo->getVarArgsFPOffset()));
2518 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2519 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2520 &X86::VR128RegClass);
2521 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2522 SaveXMMOps.push_back(Val);
2524 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2525 MVT::Other, SaveXMMOps));
2528 if (!MemOps.empty())
2529 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2533 // Some CCs need callee pop.
2534 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2535 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2536 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2538 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2539 // If this is an sret function, the return should pop the hidden pointer.
2540 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2541 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2542 argsAreStructReturn(Ins) == StackStructReturn)
2543 FuncInfo->setBytesToPopOnReturn(4);
2547 // RegSaveFrameIndex is X86-64 only.
2548 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2549 if (CallConv == CallingConv::X86_FastCall ||
2550 CallConv == CallingConv::X86_ThisCall)
2551 // fastcc functions can't have varargs.
2552 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2555 FuncInfo->setArgumentStackSize(StackSize);
2561 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2562 SDValue StackPtr, SDValue Arg,
2563 SDLoc dl, SelectionDAG &DAG,
2564 const CCValAssign &VA,
2565 ISD::ArgFlagsTy Flags) const {
2566 unsigned LocMemOffset = VA.getLocMemOffset();
2567 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2568 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2569 if (Flags.isByVal())
2570 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2572 return DAG.getStore(Chain, dl, Arg, PtrOff,
2573 MachinePointerInfo::getStack(LocMemOffset),
2577 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2578 /// optimization is performed and it is required.
2580 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2581 SDValue &OutRetAddr, SDValue Chain,
2582 bool IsTailCall, bool Is64Bit,
2583 int FPDiff, SDLoc dl) const {
2584 // Adjust the Return address stack slot.
2585 EVT VT = getPointerTy();
2586 OutRetAddr = getReturnAddressFrameIndex(DAG);
2588 // Load the "old" Return address.
2589 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2590 false, false, false, 0);
2591 return SDValue(OutRetAddr.getNode(), 1);
2594 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2595 /// optimization is performed and it is required (FPDiff!=0).
2596 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2597 SDValue Chain, SDValue RetAddrFrIdx,
2598 EVT PtrVT, unsigned SlotSize,
2599 int FPDiff, SDLoc dl) {
2600 // Store the return address to the appropriate stack slot.
2601 if (!FPDiff) return Chain;
2602 // Calculate the new stack slot for the return address.
2603 int NewReturnAddrFI =
2604 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2606 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2607 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2608 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2614 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2615 SmallVectorImpl<SDValue> &InVals) const {
2616 SelectionDAG &DAG = CLI.DAG;
2618 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2619 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2620 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2621 SDValue Chain = CLI.Chain;
2622 SDValue Callee = CLI.Callee;
2623 CallingConv::ID CallConv = CLI.CallConv;
2624 bool &isTailCall = CLI.IsTailCall;
2625 bool isVarArg = CLI.IsVarArg;
2627 MachineFunction &MF = DAG.getMachineFunction();
2628 bool Is64Bit = Subtarget->is64Bit();
2629 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2630 StructReturnType SR = callIsStructReturn(Outs);
2631 bool IsSibcall = false;
2633 if (MF.getTarget().Options.DisableTailCalls)
2636 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2638 // Force this to be a tail call. The verifier rules are enough to ensure
2639 // that we can lower this successfully without moving the return address
2642 } else if (isTailCall) {
2643 // Check if it's really possible to do a tail call.
2644 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2645 isVarArg, SR != NotStructReturn,
2646 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2647 Outs, OutVals, Ins, DAG);
2649 // Sibcalls are automatically detected tailcalls which do not require
2651 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2658 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2659 "Var args not supported with calling convention fastcc, ghc or hipe");
2661 // Analyze operands of the call, assigning locations to each operand.
2662 SmallVector<CCValAssign, 16> ArgLocs;
2663 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2665 // Allocate shadow area for Win64
2667 CCInfo.AllocateStack(32, 8);
2669 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2671 // Get a count of how many bytes are to be pushed on the stack.
2672 unsigned NumBytes = CCInfo.getNextStackOffset();
2674 // This is a sibcall. The memory operands are available in caller's
2675 // own caller's stack.
2677 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2678 IsTailCallConvention(CallConv))
2679 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2682 if (isTailCall && !IsSibcall && !IsMustTail) {
2683 // Lower arguments at fp - stackoffset + fpdiff.
2684 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2685 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2687 FPDiff = NumBytesCallerPushed - NumBytes;
2689 // Set the delta of movement of the returnaddr stackslot.
2690 // But only set if delta is greater than previous delta.
2691 if (FPDiff < X86Info->getTCReturnAddrDelta())
2692 X86Info->setTCReturnAddrDelta(FPDiff);
2695 unsigned NumBytesToPush = NumBytes;
2696 unsigned NumBytesToPop = NumBytes;
2698 // If we have an inalloca argument, all stack space has already been allocated
2699 // for us and be right at the top of the stack. We don't support multiple
2700 // arguments passed in memory when using inalloca.
2701 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2703 if (!ArgLocs.back().isMemLoc())
2704 report_fatal_error("cannot use inalloca attribute on a register "
2706 if (ArgLocs.back().getLocMemOffset() != 0)
2707 report_fatal_error("any parameter with the inalloca attribute must be "
2708 "the only memory argument");
2712 Chain = DAG.getCALLSEQ_START(
2713 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2715 SDValue RetAddrFrIdx;
2716 // Load return address for tail calls.
2717 if (isTailCall && FPDiff)
2718 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2719 Is64Bit, FPDiff, dl);
2721 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2722 SmallVector<SDValue, 8> MemOpChains;
2725 // Walk the register/memloc assignments, inserting copies/loads. In the case
2726 // of tail call optimization arguments are handle later.
2727 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2728 DAG.getSubtarget().getRegisterInfo());
2729 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2730 // Skip inalloca arguments, they have already been written.
2731 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2732 if (Flags.isInAlloca())
2735 CCValAssign &VA = ArgLocs[i];
2736 EVT RegVT = VA.getLocVT();
2737 SDValue Arg = OutVals[i];
2738 bool isByVal = Flags.isByVal();
2740 // Promote the value if needed.
2741 switch (VA.getLocInfo()) {
2742 default: llvm_unreachable("Unknown loc info!");
2743 case CCValAssign::Full: break;
2744 case CCValAssign::SExt:
2745 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2747 case CCValAssign::ZExt:
2748 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2750 case CCValAssign::AExt:
2751 if (RegVT.is128BitVector()) {
2752 // Special case: passing MMX values in XMM registers.
2753 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2754 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2755 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2757 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2759 case CCValAssign::BCvt:
2760 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2762 case CCValAssign::Indirect: {
2763 // Store the argument.
2764 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2765 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2766 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2767 MachinePointerInfo::getFixedStack(FI),
2774 if (VA.isRegLoc()) {
2775 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2776 if (isVarArg && IsWin64) {
2777 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2778 // shadow reg if callee is a varargs function.
2779 unsigned ShadowReg = 0;
2780 switch (VA.getLocReg()) {
2781 case X86::XMM0: ShadowReg = X86::RCX; break;
2782 case X86::XMM1: ShadowReg = X86::RDX; break;
2783 case X86::XMM2: ShadowReg = X86::R8; break;
2784 case X86::XMM3: ShadowReg = X86::R9; break;
2787 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2789 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2790 assert(VA.isMemLoc());
2791 if (!StackPtr.getNode())
2792 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2794 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2795 dl, DAG, VA, Flags));
2799 if (!MemOpChains.empty())
2800 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2802 if (Subtarget->isPICStyleGOT()) {
2803 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2806 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2807 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2809 // If we are tail calling and generating PIC/GOT style code load the
2810 // address of the callee into ECX. The value in ecx is used as target of
2811 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2812 // for tail calls on PIC/GOT architectures. Normally we would just put the
2813 // address of GOT into ebx and then call target@PLT. But for tail calls
2814 // ebx would be restored (since ebx is callee saved) before jumping to the
2817 // Note: The actual moving to ECX is done further down.
2818 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2819 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2820 !G->getGlobal()->hasProtectedVisibility())
2821 Callee = LowerGlobalAddress(Callee, DAG);
2822 else if (isa<ExternalSymbolSDNode>(Callee))
2823 Callee = LowerExternalSymbol(Callee, DAG);
2827 if (Is64Bit && isVarArg && !IsWin64) {
2828 // From AMD64 ABI document:
2829 // For calls that may call functions that use varargs or stdargs
2830 // (prototype-less calls or calls to functions containing ellipsis (...) in
2831 // the declaration) %al is used as hidden argument to specify the number
2832 // of SSE registers used. The contents of %al do not need to match exactly
2833 // the number of registers, but must be an ubound on the number of SSE
2834 // registers used and is in the range 0 - 8 inclusive.
2836 // Count the number of XMM registers allocated.
2837 static const MCPhysReg XMMArgRegs[] = {
2838 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2839 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2841 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2842 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2843 && "SSE registers cannot be used when SSE is disabled");
2845 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2846 DAG.getConstant(NumXMMRegs, MVT::i8)));
2849 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2850 // don't need this because the eligibility check rejects calls that require
2851 // shuffling arguments passed in memory.
2852 if (!IsSibcall && isTailCall) {
2853 // Force all the incoming stack arguments to be loaded from the stack
2854 // before any new outgoing arguments are stored to the stack, because the
2855 // outgoing stack slots may alias the incoming argument stack slots, and
2856 // the alias isn't otherwise explicit. This is slightly more conservative
2857 // than necessary, because it means that each store effectively depends
2858 // on every argument instead of just those arguments it would clobber.
2859 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2861 SmallVector<SDValue, 8> MemOpChains2;
2864 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2865 CCValAssign &VA = ArgLocs[i];
2868 assert(VA.isMemLoc());
2869 SDValue Arg = OutVals[i];
2870 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2871 // Skip inalloca arguments. They don't require any work.
2872 if (Flags.isInAlloca())
2874 // Create frame index.
2875 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2876 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2877 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2878 FIN = DAG.getFrameIndex(FI, getPointerTy());
2880 if (Flags.isByVal()) {
2881 // Copy relative to framepointer.
2882 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2883 if (!StackPtr.getNode())
2884 StackPtr = DAG.getCopyFromReg(Chain, dl,
2885 RegInfo->getStackRegister(),
2887 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2889 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2893 // Store relative to framepointer.
2894 MemOpChains2.push_back(
2895 DAG.getStore(ArgChain, dl, Arg, FIN,
2896 MachinePointerInfo::getFixedStack(FI),
2901 if (!MemOpChains2.empty())
2902 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2904 // Store the return address to the appropriate stack slot.
2905 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2906 getPointerTy(), RegInfo->getSlotSize(),
2910 // Build a sequence of copy-to-reg nodes chained together with token chain
2911 // and flag operands which copy the outgoing args into registers.
2913 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2914 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2915 RegsToPass[i].second, InFlag);
2916 InFlag = Chain.getValue(1);
2919 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2920 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2921 // In the 64-bit large code model, we have to make all calls
2922 // through a register, since the call instruction's 32-bit
2923 // pc-relative offset may not be large enough to hold the whole
2925 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2926 // If the callee is a GlobalAddress node (quite common, every direct call
2927 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2930 // We should use extra load for direct calls to dllimported functions in
2932 const GlobalValue *GV = G->getGlobal();
2933 if (!GV->hasDLLImportStorageClass()) {
2934 unsigned char OpFlags = 0;
2935 bool ExtraLoad = false;
2936 unsigned WrapperKind = ISD::DELETED_NODE;
2938 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2939 // external symbols most go through the PLT in PIC mode. If the symbol
2940 // has hidden or protected visibility, or if it is static or local, then
2941 // we don't need to use the PLT - we can directly call it.
2942 if (Subtarget->isTargetELF() &&
2943 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2944 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2945 OpFlags = X86II::MO_PLT;
2946 } else if (Subtarget->isPICStyleStubAny() &&
2947 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2948 (!Subtarget->getTargetTriple().isMacOSX() ||
2949 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2950 // PC-relative references to external symbols should go through $stub,
2951 // unless we're building with the leopard linker or later, which
2952 // automatically synthesizes these stubs.
2953 OpFlags = X86II::MO_DARWIN_STUB;
2954 } else if (Subtarget->isPICStyleRIPRel() &&
2955 isa<Function>(GV) &&
2956 cast<Function>(GV)->getAttributes().
2957 hasAttribute(AttributeSet::FunctionIndex,
2958 Attribute::NonLazyBind)) {
2959 // If the function is marked as non-lazy, generate an indirect call
2960 // which loads from the GOT directly. This avoids runtime overhead
2961 // at the cost of eager binding (and one extra byte of encoding).
2962 OpFlags = X86II::MO_GOTPCREL;
2963 WrapperKind = X86ISD::WrapperRIP;
2967 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2968 G->getOffset(), OpFlags);
2970 // Add a wrapper if needed.
2971 if (WrapperKind != ISD::DELETED_NODE)
2972 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2973 // Add extra indirection if needed.
2975 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2976 MachinePointerInfo::getGOT(),
2977 false, false, false, 0);
2979 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2980 unsigned char OpFlags = 0;
2982 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2983 // external symbols should go through the PLT.
2984 if (Subtarget->isTargetELF() &&
2985 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2986 OpFlags = X86II::MO_PLT;
2987 } else if (Subtarget->isPICStyleStubAny() &&
2988 (!Subtarget->getTargetTriple().isMacOSX() ||
2989 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2990 // PC-relative references to external symbols should go through $stub,
2991 // unless we're building with the leopard linker or later, which
2992 // automatically synthesizes these stubs.
2993 OpFlags = X86II::MO_DARWIN_STUB;
2996 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3000 // Returns a chain & a flag for retval copy to use.
3001 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3002 SmallVector<SDValue, 8> Ops;
3004 if (!IsSibcall && isTailCall) {
3005 Chain = DAG.getCALLSEQ_END(Chain,
3006 DAG.getIntPtrConstant(NumBytesToPop, true),
3007 DAG.getIntPtrConstant(0, true), InFlag, dl);
3008 InFlag = Chain.getValue(1);
3011 Ops.push_back(Chain);
3012 Ops.push_back(Callee);
3015 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3017 // Add argument registers to the end of the list so that they are known live
3019 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3020 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3021 RegsToPass[i].second.getValueType()));
3023 // Add a register mask operand representing the call-preserved registers.
3024 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3025 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3026 assert(Mask && "Missing call preserved mask for calling convention");
3027 Ops.push_back(DAG.getRegisterMask(Mask));
3029 if (InFlag.getNode())
3030 Ops.push_back(InFlag);
3034 //// If this is the first return lowered for this function, add the regs
3035 //// to the liveout set for the function.
3036 // This isn't right, although it's probably harmless on x86; liveouts
3037 // should be computed from returns not tail calls. Consider a void
3038 // function making a tail call to a function returning int.
3039 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3042 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3043 InFlag = Chain.getValue(1);
3045 // Create the CALLSEQ_END node.
3046 unsigned NumBytesForCalleeToPop;
3047 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3048 DAG.getTarget().Options.GuaranteedTailCallOpt))
3049 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3050 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3051 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3052 SR == StackStructReturn)
3053 // If this is a call to a struct-return function, the callee
3054 // pops the hidden struct pointer, so we have to push it back.
3055 // This is common for Darwin/X86, Linux & Mingw32 targets.
3056 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3057 NumBytesForCalleeToPop = 4;
3059 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3061 // Returns a flag for retval copy to use.
3063 Chain = DAG.getCALLSEQ_END(Chain,
3064 DAG.getIntPtrConstant(NumBytesToPop, true),
3065 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3068 InFlag = Chain.getValue(1);
3071 // Handle result values, copying them out of physregs into vregs that we
3073 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3074 Ins, dl, DAG, InVals);
3077 //===----------------------------------------------------------------------===//
3078 // Fast Calling Convention (tail call) implementation
3079 //===----------------------------------------------------------------------===//
3081 // Like std call, callee cleans arguments, convention except that ECX is
3082 // reserved for storing the tail called function address. Only 2 registers are
3083 // free for argument passing (inreg). Tail call optimization is performed
3085 // * tailcallopt is enabled
3086 // * caller/callee are fastcc
3087 // On X86_64 architecture with GOT-style position independent code only local
3088 // (within module) calls are supported at the moment.
3089 // To keep the stack aligned according to platform abi the function
3090 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3091 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3092 // If a tail called function callee has more arguments than the caller the
3093 // caller needs to make sure that there is room to move the RETADDR to. This is
3094 // achieved by reserving an area the size of the argument delta right after the
3095 // original RETADDR, but before the saved framepointer or the spilled registers
3096 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3108 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3109 /// for a 16 byte align requirement.
3111 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3112 SelectionDAG& DAG) const {
3113 MachineFunction &MF = DAG.getMachineFunction();
3114 const TargetMachine &TM = MF.getTarget();
3115 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3116 TM.getSubtargetImpl()->getRegisterInfo());
3117 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3118 unsigned StackAlignment = TFI.getStackAlignment();
3119 uint64_t AlignMask = StackAlignment - 1;
3120 int64_t Offset = StackSize;
3121 unsigned SlotSize = RegInfo->getSlotSize();
3122 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3123 // Number smaller than 12 so just add the difference.
3124 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3126 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3127 Offset = ((~AlignMask) & Offset) + StackAlignment +
3128 (StackAlignment-SlotSize);
3133 /// MatchingStackOffset - Return true if the given stack call argument is
3134 /// already available in the same position (relatively) of the caller's
3135 /// incoming argument stack.
3137 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3138 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3139 const X86InstrInfo *TII) {
3140 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3142 if (Arg.getOpcode() == ISD::CopyFromReg) {
3143 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3144 if (!TargetRegisterInfo::isVirtualRegister(VR))
3146 MachineInstr *Def = MRI->getVRegDef(VR);
3149 if (!Flags.isByVal()) {
3150 if (!TII->isLoadFromStackSlot(Def, FI))
3153 unsigned Opcode = Def->getOpcode();
3154 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3155 Def->getOperand(1).isFI()) {
3156 FI = Def->getOperand(1).getIndex();
3157 Bytes = Flags.getByValSize();
3161 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3162 if (Flags.isByVal())
3163 // ByVal argument is passed in as a pointer but it's now being
3164 // dereferenced. e.g.
3165 // define @foo(%struct.X* %A) {
3166 // tail call @bar(%struct.X* byval %A)
3169 SDValue Ptr = Ld->getBasePtr();
3170 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3173 FI = FINode->getIndex();
3174 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3175 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3176 FI = FINode->getIndex();
3177 Bytes = Flags.getByValSize();
3181 assert(FI != INT_MAX);
3182 if (!MFI->isFixedObjectIndex(FI))
3184 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3187 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3188 /// for tail call optimization. Targets which want to do tail call
3189 /// optimization should implement this function.
3191 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3192 CallingConv::ID CalleeCC,
3194 bool isCalleeStructRet,
3195 bool isCallerStructRet,
3197 const SmallVectorImpl<ISD::OutputArg> &Outs,
3198 const SmallVectorImpl<SDValue> &OutVals,
3199 const SmallVectorImpl<ISD::InputArg> &Ins,
3200 SelectionDAG &DAG) const {
3201 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3204 // If -tailcallopt is specified, make fastcc functions tail-callable.
3205 const MachineFunction &MF = DAG.getMachineFunction();
3206 const Function *CallerF = MF.getFunction();
3208 // If the function return type is x86_fp80 and the callee return type is not,
3209 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3210 // perform a tailcall optimization here.
3211 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3214 CallingConv::ID CallerCC = CallerF->getCallingConv();
3215 bool CCMatch = CallerCC == CalleeCC;
3216 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3217 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3219 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3220 if (IsTailCallConvention(CalleeCC) && CCMatch)
3225 // Look for obvious safe cases to perform tail call optimization that do not
3226 // require ABI changes. This is what gcc calls sibcall.
3228 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3229 // emit a special epilogue.
3230 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3231 DAG.getSubtarget().getRegisterInfo());
3232 if (RegInfo->needsStackRealignment(MF))
3235 // Also avoid sibcall optimization if either caller or callee uses struct
3236 // return semantics.
3237 if (isCalleeStructRet || isCallerStructRet)
3240 // An stdcall/thiscall caller is expected to clean up its arguments; the
3241 // callee isn't going to do that.
3242 // FIXME: this is more restrictive than needed. We could produce a tailcall
3243 // when the stack adjustment matches. For example, with a thiscall that takes
3244 // only one argument.
3245 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3246 CallerCC == CallingConv::X86_ThisCall))
3249 // Do not sibcall optimize vararg calls unless all arguments are passed via
3251 if (isVarArg && !Outs.empty()) {
3253 // Optimizing for varargs on Win64 is unlikely to be safe without
3254 // additional testing.
3255 if (IsCalleeWin64 || IsCallerWin64)
3258 SmallVector<CCValAssign, 16> ArgLocs;
3259 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3262 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3263 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3264 if (!ArgLocs[i].isRegLoc())
3268 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3269 // stack. Therefore, if it's not used by the call it is not safe to optimize
3270 // this into a sibcall.
3271 bool Unused = false;
3272 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3279 SmallVector<CCValAssign, 16> RVLocs;
3280 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3282 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3283 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3284 CCValAssign &VA = RVLocs[i];
3285 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3290 // If the calling conventions do not match, then we'd better make sure the
3291 // results are returned in the same way as what the caller expects.
3293 SmallVector<CCValAssign, 16> RVLocs1;
3294 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3296 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3298 SmallVector<CCValAssign, 16> RVLocs2;
3299 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3301 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3303 if (RVLocs1.size() != RVLocs2.size())
3305 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3306 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3308 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3310 if (RVLocs1[i].isRegLoc()) {
3311 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3314 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3320 // If the callee takes no arguments then go on to check the results of the
3322 if (!Outs.empty()) {
3323 // Check if stack adjustment is needed. For now, do not do this if any
3324 // argument is passed on the stack.
3325 SmallVector<CCValAssign, 16> ArgLocs;
3326 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3329 // Allocate shadow area for Win64
3331 CCInfo.AllocateStack(32, 8);
3333 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3334 if (CCInfo.getNextStackOffset()) {
3335 MachineFunction &MF = DAG.getMachineFunction();
3336 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3339 // Check if the arguments are already laid out in the right way as
3340 // the caller's fixed stack objects.
3341 MachineFrameInfo *MFI = MF.getFrameInfo();
3342 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3343 const X86InstrInfo *TII =
3344 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3345 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3346 CCValAssign &VA = ArgLocs[i];
3347 SDValue Arg = OutVals[i];
3348 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3349 if (VA.getLocInfo() == CCValAssign::Indirect)
3351 if (!VA.isRegLoc()) {
3352 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3359 // If the tailcall address may be in a register, then make sure it's
3360 // possible to register allocate for it. In 32-bit, the call address can
3361 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3362 // callee-saved registers are restored. These happen to be the same
3363 // registers used to pass 'inreg' arguments so watch out for those.
3364 if (!Subtarget->is64Bit() &&
3365 ((!isa<GlobalAddressSDNode>(Callee) &&
3366 !isa<ExternalSymbolSDNode>(Callee)) ||
3367 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3368 unsigned NumInRegs = 0;
3369 // In PIC we need an extra register to formulate the address computation
3371 unsigned MaxInRegs =
3372 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3374 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3375 CCValAssign &VA = ArgLocs[i];
3378 unsigned Reg = VA.getLocReg();
3381 case X86::EAX: case X86::EDX: case X86::ECX:
3382 if (++NumInRegs == MaxInRegs)
3394 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3395 const TargetLibraryInfo *libInfo) const {
3396 return X86::createFastISel(funcInfo, libInfo);
3399 //===----------------------------------------------------------------------===//
3400 // Other Lowering Hooks
3401 //===----------------------------------------------------------------------===//
3403 static bool MayFoldLoad(SDValue Op) {
3404 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3407 static bool MayFoldIntoStore(SDValue Op) {
3408 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3411 static bool isTargetShuffle(unsigned Opcode) {
3413 default: return false;
3414 case X86ISD::PSHUFB:
3415 case X86ISD::PSHUFD:
3416 case X86ISD::PSHUFHW:
3417 case X86ISD::PSHUFLW:
3419 case X86ISD::PALIGNR:
3420 case X86ISD::MOVLHPS:
3421 case X86ISD::MOVLHPD:
3422 case X86ISD::MOVHLPS:
3423 case X86ISD::MOVLPS:
3424 case X86ISD::MOVLPD:
3425 case X86ISD::MOVSHDUP:
3426 case X86ISD::MOVSLDUP:
3427 case X86ISD::MOVDDUP:
3430 case X86ISD::UNPCKL:
3431 case X86ISD::UNPCKH:
3432 case X86ISD::VPERMILP:
3433 case X86ISD::VPERM2X128:
3434 case X86ISD::VPERMI:
3439 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3440 SDValue V1, SelectionDAG &DAG) {
3442 default: llvm_unreachable("Unknown x86 shuffle node");
3443 case X86ISD::MOVSHDUP:
3444 case X86ISD::MOVSLDUP:
3445 case X86ISD::MOVDDUP:
3446 return DAG.getNode(Opc, dl, VT, V1);
3450 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3451 SDValue V1, unsigned TargetMask,
3452 SelectionDAG &DAG) {
3454 default: llvm_unreachable("Unknown x86 shuffle node");
3455 case X86ISD::PSHUFD:
3456 case X86ISD::PSHUFHW:
3457 case X86ISD::PSHUFLW:
3458 case X86ISD::VPERMILP:
3459 case X86ISD::VPERMI:
3460 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3464 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3465 SDValue V1, SDValue V2, unsigned TargetMask,
3466 SelectionDAG &DAG) {
3468 default: llvm_unreachable("Unknown x86 shuffle node");
3469 case X86ISD::PALIGNR:
3470 case X86ISD::VALIGN:
3472 case X86ISD::VPERM2X128:
3473 return DAG.getNode(Opc, dl, VT, V1, V2,
3474 DAG.getConstant(TargetMask, MVT::i8));
3478 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3479 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3481 default: llvm_unreachable("Unknown x86 shuffle node");
3482 case X86ISD::MOVLHPS:
3483 case X86ISD::MOVLHPD:
3484 case X86ISD::MOVHLPS:
3485 case X86ISD::MOVLPS:
3486 case X86ISD::MOVLPD:
3489 case X86ISD::UNPCKL:
3490 case X86ISD::UNPCKH:
3491 return DAG.getNode(Opc, dl, VT, V1, V2);
3495 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3496 MachineFunction &MF = DAG.getMachineFunction();
3497 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3498 DAG.getSubtarget().getRegisterInfo());
3499 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3500 int ReturnAddrIndex = FuncInfo->getRAIndex();
3502 if (ReturnAddrIndex == 0) {
3503 // Set up a frame object for the return address.
3504 unsigned SlotSize = RegInfo->getSlotSize();
3505 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3508 FuncInfo->setRAIndex(ReturnAddrIndex);
3511 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3514 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3515 bool hasSymbolicDisplacement) {
3516 // Offset should fit into 32 bit immediate field.
3517 if (!isInt<32>(Offset))
3520 // If we don't have a symbolic displacement - we don't have any extra
3522 if (!hasSymbolicDisplacement)
3525 // FIXME: Some tweaks might be needed for medium code model.
3526 if (M != CodeModel::Small && M != CodeModel::Kernel)
3529 // For small code model we assume that latest object is 16MB before end of 31
3530 // bits boundary. We may also accept pretty large negative constants knowing
3531 // that all objects are in the positive half of address space.
3532 if (M == CodeModel::Small && Offset < 16*1024*1024)
3535 // For kernel code model we know that all object resist in the negative half
3536 // of 32bits address space. We may not accept negative offsets, since they may
3537 // be just off and we may accept pretty large positive ones.
3538 if (M == CodeModel::Kernel && Offset > 0)
3544 /// isCalleePop - Determines whether the callee is required to pop its
3545 /// own arguments. Callee pop is necessary to support tail calls.
3546 bool X86::isCalleePop(CallingConv::ID CallingConv,
3547 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3551 switch (CallingConv) {
3554 case CallingConv::X86_StdCall:
3556 case CallingConv::X86_FastCall:
3558 case CallingConv::X86_ThisCall:
3560 case CallingConv::Fast:
3562 case CallingConv::GHC:
3564 case CallingConv::HiPE:
3569 /// \brief Return true if the condition is an unsigned comparison operation.
3570 static bool isX86CCUnsigned(unsigned X86CC) {
3572 default: llvm_unreachable("Invalid integer condition!");
3573 case X86::COND_E: return true;
3574 case X86::COND_G: return false;
3575 case X86::COND_GE: return false;
3576 case X86::COND_L: return false;
3577 case X86::COND_LE: return false;
3578 case X86::COND_NE: return true;
3579 case X86::COND_B: return true;
3580 case X86::COND_A: return true;
3581 case X86::COND_BE: return true;
3582 case X86::COND_AE: return true;
3584 llvm_unreachable("covered switch fell through?!");
3587 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3588 /// specific condition code, returning the condition code and the LHS/RHS of the
3589 /// comparison to make.
3590 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3591 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3593 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3594 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3595 // X > -1 -> X == 0, jump !sign.
3596 RHS = DAG.getConstant(0, RHS.getValueType());
3597 return X86::COND_NS;
3599 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3600 // X < 0 -> X == 0, jump on sign.
3603 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3605 RHS = DAG.getConstant(0, RHS.getValueType());
3606 return X86::COND_LE;
3610 switch (SetCCOpcode) {
3611 default: llvm_unreachable("Invalid integer condition!");
3612 case ISD::SETEQ: return X86::COND_E;
3613 case ISD::SETGT: return X86::COND_G;
3614 case ISD::SETGE: return X86::COND_GE;
3615 case ISD::SETLT: return X86::COND_L;
3616 case ISD::SETLE: return X86::COND_LE;
3617 case ISD::SETNE: return X86::COND_NE;
3618 case ISD::SETULT: return X86::COND_B;
3619 case ISD::SETUGT: return X86::COND_A;
3620 case ISD::SETULE: return X86::COND_BE;
3621 case ISD::SETUGE: return X86::COND_AE;
3625 // First determine if it is required or is profitable to flip the operands.
3627 // If LHS is a foldable load, but RHS is not, flip the condition.
3628 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3629 !ISD::isNON_EXTLoad(RHS.getNode())) {
3630 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3631 std::swap(LHS, RHS);
3634 switch (SetCCOpcode) {
3640 std::swap(LHS, RHS);
3644 // On a floating point condition, the flags are set as follows:
3646 // 0 | 0 | 0 | X > Y
3647 // 0 | 0 | 1 | X < Y
3648 // 1 | 0 | 0 | X == Y
3649 // 1 | 1 | 1 | unordered
3650 switch (SetCCOpcode) {
3651 default: llvm_unreachable("Condcode should be pre-legalized away");
3653 case ISD::SETEQ: return X86::COND_E;
3654 case ISD::SETOLT: // flipped
3656 case ISD::SETGT: return X86::COND_A;
3657 case ISD::SETOLE: // flipped
3659 case ISD::SETGE: return X86::COND_AE;
3660 case ISD::SETUGT: // flipped
3662 case ISD::SETLT: return X86::COND_B;
3663 case ISD::SETUGE: // flipped
3665 case ISD::SETLE: return X86::COND_BE;
3667 case ISD::SETNE: return X86::COND_NE;
3668 case ISD::SETUO: return X86::COND_P;
3669 case ISD::SETO: return X86::COND_NP;
3671 case ISD::SETUNE: return X86::COND_INVALID;
3675 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3676 /// code. Current x86 isa includes the following FP cmov instructions:
3677 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3678 static bool hasFPCMov(unsigned X86CC) {
3694 /// isFPImmLegal - Returns true if the target can instruction select the
3695 /// specified FP immediate natively. If false, the legalizer will
3696 /// materialize the FP immediate as a load from a constant pool.
3697 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3698 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3699 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3705 /// \brief Returns true if it is beneficial to convert a load of a constant
3706 /// to just the constant itself.
3707 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3709 assert(Ty->isIntegerTy());
3711 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3712 if (BitSize == 0 || BitSize > 64)
3717 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3718 /// the specified range (L, H].
3719 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3720 return (Val < 0) || (Val >= Low && Val < Hi);
3723 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3724 /// specified value.
3725 static bool isUndefOrEqual(int Val, int CmpVal) {
3726 return (Val < 0 || Val == CmpVal);
3729 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3730 /// from position Pos and ending in Pos+Size, falls within the specified
3731 /// sequential range (L, L+Pos]. or is undef.
3732 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3733 unsigned Pos, unsigned Size, int Low) {
3734 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3735 if (!isUndefOrEqual(Mask[i], Low))
3740 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3741 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3742 /// the second operand.
3743 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3744 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3745 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3746 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3747 return (Mask[0] < 2 && Mask[1] < 2);
3751 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3752 /// is suitable for input to PSHUFHW.
3753 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3754 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3757 // Lower quadword copied in order or undef.
3758 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3761 // Upper quadword shuffled.
3762 for (unsigned i = 4; i != 8; ++i)
3763 if (!isUndefOrInRange(Mask[i], 4, 8))
3766 if (VT == MVT::v16i16) {
3767 // Lower quadword copied in order or undef.
3768 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3771 // Upper quadword shuffled.
3772 for (unsigned i = 12; i != 16; ++i)
3773 if (!isUndefOrInRange(Mask[i], 12, 16))
3780 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3781 /// is suitable for input to PSHUFLW.
3782 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3783 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3786 // Upper quadword copied in order.
3787 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3790 // Lower quadword shuffled.
3791 for (unsigned i = 0; i != 4; ++i)
3792 if (!isUndefOrInRange(Mask[i], 0, 4))
3795 if (VT == MVT::v16i16) {
3796 // Upper quadword copied in order.
3797 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3800 // Lower quadword shuffled.
3801 for (unsigned i = 8; i != 12; ++i)
3802 if (!isUndefOrInRange(Mask[i], 8, 12))
3809 /// \brief Return true if the mask specifies a shuffle of elements that is
3810 /// suitable for input to intralane (palignr) or interlane (valign) vector
3812 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3813 unsigned NumElts = VT.getVectorNumElements();
3814 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3815 unsigned NumLaneElts = NumElts/NumLanes;
3817 // Do not handle 64-bit element shuffles with palignr.
3818 if (NumLaneElts == 2)
3821 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3823 for (i = 0; i != NumLaneElts; ++i) {
3828 // Lane is all undef, go to next lane
3829 if (i == NumLaneElts)
3832 int Start = Mask[i+l];
3834 // Make sure its in this lane in one of the sources
3835 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3836 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3839 // If not lane 0, then we must match lane 0
3840 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3843 // Correct second source to be contiguous with first source
3844 if (Start >= (int)NumElts)
3845 Start -= NumElts - NumLaneElts;
3847 // Make sure we're shifting in the right direction.
3848 if (Start <= (int)(i+l))
3853 // Check the rest of the elements to see if they are consecutive.
3854 for (++i; i != NumLaneElts; ++i) {
3855 int Idx = Mask[i+l];
3857 // Make sure its in this lane
3858 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3859 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3862 // If not lane 0, then we must match lane 0
3863 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3866 if (Idx >= (int)NumElts)
3867 Idx -= NumElts - NumLaneElts;
3869 if (!isUndefOrEqual(Idx, Start+i))
3878 /// \brief Return true if the node specifies a shuffle of elements that is
3879 /// suitable for input to PALIGNR.
3880 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3881 const X86Subtarget *Subtarget) {
3882 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3883 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
3884 VT.is512BitVector())
3885 // FIXME: Add AVX512BW.
3888 return isAlignrMask(Mask, VT, false);
3891 /// \brief Return true if the node specifies a shuffle of elements that is
3892 /// suitable for input to VALIGN.
3893 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
3894 const X86Subtarget *Subtarget) {
3895 // FIXME: Add AVX512VL.
3896 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
3898 return isAlignrMask(Mask, VT, true);
3901 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3902 /// the two vector operands have swapped position.
3903 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3904 unsigned NumElems) {
3905 for (unsigned i = 0; i != NumElems; ++i) {
3909 else if (idx < (int)NumElems)
3910 Mask[i] = idx + NumElems;
3912 Mask[i] = idx - NumElems;
3916 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3917 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3918 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3919 /// reverse of what x86 shuffles want.
3920 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3922 unsigned NumElems = VT.getVectorNumElements();
3923 unsigned NumLanes = VT.getSizeInBits()/128;
3924 unsigned NumLaneElems = NumElems/NumLanes;
3926 if (NumLaneElems != 2 && NumLaneElems != 4)
3929 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3930 bool symetricMaskRequired =
3931 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3933 // VSHUFPSY divides the resulting vector into 4 chunks.
3934 // The sources are also splitted into 4 chunks, and each destination
3935 // chunk must come from a different source chunk.
3937 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3938 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3940 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3941 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3943 // VSHUFPDY divides the resulting vector into 4 chunks.
3944 // The sources are also splitted into 4 chunks, and each destination
3945 // chunk must come from a different source chunk.
3947 // SRC1 => X3 X2 X1 X0
3948 // SRC2 => Y3 Y2 Y1 Y0
3950 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3952 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3953 unsigned HalfLaneElems = NumLaneElems/2;
3954 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3955 for (unsigned i = 0; i != NumLaneElems; ++i) {
3956 int Idx = Mask[i+l];
3957 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3958 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3960 // For VSHUFPSY, the mask of the second half must be the same as the
3961 // first but with the appropriate offsets. This works in the same way as
3962 // VPERMILPS works with masks.
3963 if (!symetricMaskRequired || Idx < 0)
3965 if (MaskVal[i] < 0) {
3966 MaskVal[i] = Idx - l;
3969 if ((signed)(Idx - l) != MaskVal[i])
3977 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3978 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3979 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3980 if (!VT.is128BitVector())
3983 unsigned NumElems = VT.getVectorNumElements();
3988 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3989 return isUndefOrEqual(Mask[0], 6) &&
3990 isUndefOrEqual(Mask[1], 7) &&
3991 isUndefOrEqual(Mask[2], 2) &&
3992 isUndefOrEqual(Mask[3], 3);
3995 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3996 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3998 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3999 if (!VT.is128BitVector())
4002 unsigned NumElems = VT.getVectorNumElements();
4007 return isUndefOrEqual(Mask[0], 2) &&
4008 isUndefOrEqual(Mask[1], 3) &&
4009 isUndefOrEqual(Mask[2], 2) &&
4010 isUndefOrEqual(Mask[3], 3);
4013 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4014 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4015 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4016 if (!VT.is128BitVector())
4019 unsigned NumElems = VT.getVectorNumElements();
4021 if (NumElems != 2 && NumElems != 4)
4024 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4025 if (!isUndefOrEqual(Mask[i], i + NumElems))
4028 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4029 if (!isUndefOrEqual(Mask[i], i))
4035 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4036 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4037 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4038 if (!VT.is128BitVector())
4041 unsigned NumElems = VT.getVectorNumElements();
4043 if (NumElems != 2 && NumElems != 4)
4046 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4047 if (!isUndefOrEqual(Mask[i], i))
4050 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4051 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4057 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4058 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4059 /// i. e: If all but one element come from the same vector.
4060 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4061 // TODO: Deal with AVX's VINSERTPS
4062 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4065 unsigned CorrectPosV1 = 0;
4066 unsigned CorrectPosV2 = 0;
4067 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4068 if (Mask[i] == -1) {
4076 else if (Mask[i] == i + 4)
4080 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4081 // We have 3 elements (undefs count as elements from any vector) from one
4082 // vector, and one from another.
4089 // Some special combinations that can be optimized.
4092 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4093 SelectionDAG &DAG) {
4094 MVT VT = SVOp->getSimpleValueType(0);
4097 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4100 ArrayRef<int> Mask = SVOp->getMask();
4102 // These are the special masks that may be optimized.
4103 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4104 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4105 bool MatchEvenMask = true;
4106 bool MatchOddMask = true;
4107 for (int i=0; i<8; ++i) {
4108 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4109 MatchEvenMask = false;
4110 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4111 MatchOddMask = false;
4114 if (!MatchEvenMask && !MatchOddMask)
4117 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4119 SDValue Op0 = SVOp->getOperand(0);
4120 SDValue Op1 = SVOp->getOperand(1);
4122 if (MatchEvenMask) {
4123 // Shift the second operand right to 32 bits.
4124 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4125 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4127 // Shift the first operand left to 32 bits.
4128 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4129 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4131 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4132 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4135 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4136 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4137 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4138 bool HasInt256, bool V2IsSplat = false) {
4140 assert(VT.getSizeInBits() >= 128 &&
4141 "Unsupported vector type for unpckl");
4143 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4145 unsigned NumOf256BitLanes;
4146 unsigned NumElts = VT.getVectorNumElements();
4147 if (VT.is256BitVector()) {
4148 if (NumElts != 4 && NumElts != 8 &&
4149 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4152 NumOf256BitLanes = 1;
4153 } else if (VT.is512BitVector()) {
4154 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4155 "Unsupported vector type for unpckh");
4157 NumOf256BitLanes = 2;
4160 NumOf256BitLanes = 1;
4163 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4164 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4166 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4167 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4168 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4169 int BitI = Mask[l256*NumEltsInStride+l+i];
4170 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4171 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4173 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4175 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4183 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4184 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4185 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4186 bool HasInt256, bool V2IsSplat = false) {
4187 assert(VT.getSizeInBits() >= 128 &&
4188 "Unsupported vector type for unpckh");
4190 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4192 unsigned NumOf256BitLanes;
4193 unsigned NumElts = VT.getVectorNumElements();
4194 if (VT.is256BitVector()) {
4195 if (NumElts != 4 && NumElts != 8 &&
4196 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4199 NumOf256BitLanes = 1;
4200 } else if (VT.is512BitVector()) {
4201 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4202 "Unsupported vector type for unpckh");
4204 NumOf256BitLanes = 2;
4207 NumOf256BitLanes = 1;
4210 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4211 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4213 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4214 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4215 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4216 int BitI = Mask[l256*NumEltsInStride+l+i];
4217 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4218 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4220 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4222 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4230 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4231 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4233 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4234 unsigned NumElts = VT.getVectorNumElements();
4235 bool Is256BitVec = VT.is256BitVector();
4237 if (VT.is512BitVector())
4239 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4240 "Unsupported vector type for unpckh");
4242 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4243 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4246 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4247 // FIXME: Need a better way to get rid of this, there's no latency difference
4248 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4249 // the former later. We should also remove the "_undef" special mask.
4250 if (NumElts == 4 && Is256BitVec)
4253 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4254 // independently on 128-bit lanes.
4255 unsigned NumLanes = VT.getSizeInBits()/128;
4256 unsigned NumLaneElts = NumElts/NumLanes;
4258 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4259 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4260 int BitI = Mask[l+i];
4261 int BitI1 = Mask[l+i+1];
4263 if (!isUndefOrEqual(BitI, j))
4265 if (!isUndefOrEqual(BitI1, j))
4273 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4274 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4276 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4277 unsigned NumElts = VT.getVectorNumElements();
4279 if (VT.is512BitVector())
4282 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4283 "Unsupported vector type for unpckh");
4285 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4286 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4289 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4290 // independently on 128-bit lanes.
4291 unsigned NumLanes = VT.getSizeInBits()/128;
4292 unsigned NumLaneElts = NumElts/NumLanes;
4294 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4295 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4296 int BitI = Mask[l+i];
4297 int BitI1 = Mask[l+i+1];
4298 if (!isUndefOrEqual(BitI, j))
4300 if (!isUndefOrEqual(BitI1, j))
4307 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4308 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4309 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4310 if (!VT.is512BitVector())
4313 unsigned NumElts = VT.getVectorNumElements();
4314 unsigned HalfSize = NumElts/2;
4315 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4316 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4321 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4322 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4330 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4331 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4332 /// MOVSD, and MOVD, i.e. setting the lowest element.
4333 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4334 if (VT.getVectorElementType().getSizeInBits() < 32)
4336 if (!VT.is128BitVector())
4339 unsigned NumElts = VT.getVectorNumElements();
4341 if (!isUndefOrEqual(Mask[0], NumElts))
4344 for (unsigned i = 1; i != NumElts; ++i)
4345 if (!isUndefOrEqual(Mask[i], i))
4351 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4352 /// as permutations between 128-bit chunks or halves. As an example: this
4354 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4355 /// The first half comes from the second half of V1 and the second half from the
4356 /// the second half of V2.
4357 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4358 if (!HasFp256 || !VT.is256BitVector())
4361 // The shuffle result is divided into half A and half B. In total the two
4362 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4363 // B must come from C, D, E or F.
4364 unsigned HalfSize = VT.getVectorNumElements()/2;
4365 bool MatchA = false, MatchB = false;
4367 // Check if A comes from one of C, D, E, F.
4368 for (unsigned Half = 0; Half != 4; ++Half) {
4369 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4375 // Check if B comes from one of C, D, E, F.
4376 for (unsigned Half = 0; Half != 4; ++Half) {
4377 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4383 return MatchA && MatchB;
4386 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4387 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4388 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4389 MVT VT = SVOp->getSimpleValueType(0);
4391 unsigned HalfSize = VT.getVectorNumElements()/2;
4393 unsigned FstHalf = 0, SndHalf = 0;
4394 for (unsigned i = 0; i < HalfSize; ++i) {
4395 if (SVOp->getMaskElt(i) > 0) {
4396 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4400 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4401 if (SVOp->getMaskElt(i) > 0) {
4402 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4407 return (FstHalf | (SndHalf << 4));
4410 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4411 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4412 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4416 unsigned NumElts = VT.getVectorNumElements();
4418 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4419 for (unsigned i = 0; i != NumElts; ++i) {
4422 Imm8 |= Mask[i] << (i*2);
4427 unsigned LaneSize = 4;
4428 SmallVector<int, 4> MaskVal(LaneSize, -1);
4430 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4431 for (unsigned i = 0; i != LaneSize; ++i) {
4432 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4436 if (MaskVal[i] < 0) {
4437 MaskVal[i] = Mask[i+l] - l;
4438 Imm8 |= MaskVal[i] << (i*2);
4441 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4448 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4449 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4450 /// Note that VPERMIL mask matching is different depending whether theunderlying
4451 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4452 /// to the same elements of the low, but to the higher half of the source.
4453 /// In VPERMILPD the two lanes could be shuffled independently of each other
4454 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4455 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4456 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4457 if (VT.getSizeInBits() < 256 || EltSize < 32)
4459 bool symetricMaskRequired = (EltSize == 32);
4460 unsigned NumElts = VT.getVectorNumElements();
4462 unsigned NumLanes = VT.getSizeInBits()/128;
4463 unsigned LaneSize = NumElts/NumLanes;
4464 // 2 or 4 elements in one lane
4466 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4467 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4468 for (unsigned i = 0; i != LaneSize; ++i) {
4469 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4471 if (symetricMaskRequired) {
4472 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4473 ExpectedMaskVal[i] = Mask[i+l] - l;
4476 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4484 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4485 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4486 /// element of vector 2 and the other elements to come from vector 1 in order.
4487 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4488 bool V2IsSplat = false, bool V2IsUndef = false) {
4489 if (!VT.is128BitVector())
4492 unsigned NumOps = VT.getVectorNumElements();
4493 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4496 if (!isUndefOrEqual(Mask[0], 0))
4499 for (unsigned i = 1; i != NumOps; ++i)
4500 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4501 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4502 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4508 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4509 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4510 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4511 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4512 const X86Subtarget *Subtarget) {
4513 if (!Subtarget->hasSSE3())
4516 unsigned NumElems = VT.getVectorNumElements();
4518 if ((VT.is128BitVector() && NumElems != 4) ||
4519 (VT.is256BitVector() && NumElems != 8) ||
4520 (VT.is512BitVector() && NumElems != 16))
4523 // "i+1" is the value the indexed mask element must have
4524 for (unsigned i = 0; i != NumElems; i += 2)
4525 if (!isUndefOrEqual(Mask[i], i+1) ||
4526 !isUndefOrEqual(Mask[i+1], i+1))
4532 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4533 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4534 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4535 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4536 const X86Subtarget *Subtarget) {
4537 if (!Subtarget->hasSSE3())
4540 unsigned NumElems = VT.getVectorNumElements();
4542 if ((VT.is128BitVector() && NumElems != 4) ||
4543 (VT.is256BitVector() && NumElems != 8) ||
4544 (VT.is512BitVector() && NumElems != 16))
4547 // "i" is the value the indexed mask element must have
4548 for (unsigned i = 0; i != NumElems; i += 2)
4549 if (!isUndefOrEqual(Mask[i], i) ||
4550 !isUndefOrEqual(Mask[i+1], i))
4556 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4557 /// specifies a shuffle of elements that is suitable for input to 256-bit
4558 /// version of MOVDDUP.
4559 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4560 if (!HasFp256 || !VT.is256BitVector())
4563 unsigned NumElts = VT.getVectorNumElements();
4567 for (unsigned i = 0; i != NumElts/2; ++i)
4568 if (!isUndefOrEqual(Mask[i], 0))
4570 for (unsigned i = NumElts/2; i != NumElts; ++i)
4571 if (!isUndefOrEqual(Mask[i], NumElts/2))
4576 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4577 /// specifies a shuffle of elements that is suitable for input to 128-bit
4578 /// version of MOVDDUP.
4579 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4580 if (!VT.is128BitVector())
4583 unsigned e = VT.getVectorNumElements() / 2;
4584 for (unsigned i = 0; i != e; ++i)
4585 if (!isUndefOrEqual(Mask[i], i))
4587 for (unsigned i = 0; i != e; ++i)
4588 if (!isUndefOrEqual(Mask[e+i], i))
4593 /// isVEXTRACTIndex - Return true if the specified
4594 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4595 /// suitable for instruction that extract 128 or 256 bit vectors
4596 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4597 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4598 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4601 // The index should be aligned on a vecWidth-bit boundary.
4603 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4605 MVT VT = N->getSimpleValueType(0);
4606 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4607 bool Result = (Index * ElSize) % vecWidth == 0;
4612 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4613 /// operand specifies a subvector insert that is suitable for input to
4614 /// insertion of 128 or 256-bit subvectors
4615 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4616 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4617 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4619 // The index should be aligned on a vecWidth-bit boundary.
4621 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4623 MVT VT = N->getSimpleValueType(0);
4624 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4625 bool Result = (Index * ElSize) % vecWidth == 0;
4630 bool X86::isVINSERT128Index(SDNode *N) {
4631 return isVINSERTIndex(N, 128);
4634 bool X86::isVINSERT256Index(SDNode *N) {
4635 return isVINSERTIndex(N, 256);
4638 bool X86::isVEXTRACT128Index(SDNode *N) {
4639 return isVEXTRACTIndex(N, 128);
4642 bool X86::isVEXTRACT256Index(SDNode *N) {
4643 return isVEXTRACTIndex(N, 256);
4646 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4647 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4648 /// Handles 128-bit and 256-bit.
4649 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4650 MVT VT = N->getSimpleValueType(0);
4652 assert((VT.getSizeInBits() >= 128) &&
4653 "Unsupported vector type for PSHUF/SHUFP");
4655 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4656 // independently on 128-bit lanes.
4657 unsigned NumElts = VT.getVectorNumElements();
4658 unsigned NumLanes = VT.getSizeInBits()/128;
4659 unsigned NumLaneElts = NumElts/NumLanes;
4661 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4662 "Only supports 2, 4 or 8 elements per lane");
4664 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4666 for (unsigned i = 0; i != NumElts; ++i) {
4667 int Elt = N->getMaskElt(i);
4668 if (Elt < 0) continue;
4669 Elt &= NumLaneElts - 1;
4670 unsigned ShAmt = (i << Shift) % 8;
4671 Mask |= Elt << ShAmt;
4677 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4678 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4679 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4680 MVT VT = N->getSimpleValueType(0);
4682 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4683 "Unsupported vector type for PSHUFHW");
4685 unsigned NumElts = VT.getVectorNumElements();
4688 for (unsigned l = 0; l != NumElts; l += 8) {
4689 // 8 nodes per lane, but we only care about the last 4.
4690 for (unsigned i = 0; i < 4; ++i) {
4691 int Elt = N->getMaskElt(l+i+4);
4692 if (Elt < 0) continue;
4693 Elt &= 0x3; // only 2-bits.
4694 Mask |= Elt << (i * 2);
4701 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4702 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4703 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4704 MVT VT = N->getSimpleValueType(0);
4706 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4707 "Unsupported vector type for PSHUFHW");
4709 unsigned NumElts = VT.getVectorNumElements();
4712 for (unsigned l = 0; l != NumElts; l += 8) {
4713 // 8 nodes per lane, but we only care about the first 4.
4714 for (unsigned i = 0; i < 4; ++i) {
4715 int Elt = N->getMaskElt(l+i);
4716 if (Elt < 0) continue;
4717 Elt &= 0x3; // only 2-bits
4718 Mask |= Elt << (i * 2);
4725 /// \brief Return the appropriate immediate to shuffle the specified
4726 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4727 /// VALIGN (if Interlane is true) instructions.
4728 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4730 MVT VT = SVOp->getSimpleValueType(0);
4731 unsigned EltSize = InterLane ? 1 :
4732 VT.getVectorElementType().getSizeInBits() >> 3;
4734 unsigned NumElts = VT.getVectorNumElements();
4735 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4736 unsigned NumLaneElts = NumElts/NumLanes;
4740 for (i = 0; i != NumElts; ++i) {
4741 Val = SVOp->getMaskElt(i);
4745 if (Val >= (int)NumElts)
4746 Val -= NumElts - NumLaneElts;
4748 assert(Val - i > 0 && "PALIGNR imm should be positive");
4749 return (Val - i) * EltSize;
4752 /// \brief Return the appropriate immediate to shuffle the specified
4753 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4754 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4755 return getShuffleAlignrImmediate(SVOp, false);
4758 /// \brief Return the appropriate immediate to shuffle the specified
4759 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4760 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4761 return getShuffleAlignrImmediate(SVOp, true);
4765 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4766 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4767 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4768 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4771 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4773 MVT VecVT = N->getOperand(0).getSimpleValueType();
4774 MVT ElVT = VecVT.getVectorElementType();
4776 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4777 return Index / NumElemsPerChunk;
4780 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4781 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4782 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4783 llvm_unreachable("Illegal insert subvector for VINSERT");
4786 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4788 MVT VecVT = N->getSimpleValueType(0);
4789 MVT ElVT = VecVT.getVectorElementType();
4791 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4792 return Index / NumElemsPerChunk;
4795 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4796 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4797 /// and VINSERTI128 instructions.
4798 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4799 return getExtractVEXTRACTImmediate(N, 128);
4802 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4803 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4804 /// and VINSERTI64x4 instructions.
4805 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4806 return getExtractVEXTRACTImmediate(N, 256);
4809 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4810 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4811 /// and VINSERTI128 instructions.
4812 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4813 return getInsertVINSERTImmediate(N, 128);
4816 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4817 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4818 /// and VINSERTI64x4 instructions.
4819 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4820 return getInsertVINSERTImmediate(N, 256);
4823 /// isZero - Returns true if Elt is a constant integer zero
4824 static bool isZero(SDValue V) {
4825 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4826 return C && C->isNullValue();
4829 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4831 bool X86::isZeroNode(SDValue Elt) {
4834 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4835 return CFP->getValueAPF().isPosZero();
4839 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4840 /// match movhlps. The lower half elements should come from upper half of
4841 /// V1 (and in order), and the upper half elements should come from the upper
4842 /// half of V2 (and in order).
4843 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4844 if (!VT.is128BitVector())
4846 if (VT.getVectorNumElements() != 4)
4848 for (unsigned i = 0, e = 2; i != e; ++i)
4849 if (!isUndefOrEqual(Mask[i], i+2))
4851 for (unsigned i = 2; i != 4; ++i)
4852 if (!isUndefOrEqual(Mask[i], i+4))
4857 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4858 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4860 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4861 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4863 N = N->getOperand(0).getNode();
4864 if (!ISD::isNON_EXTLoad(N))
4867 *LD = cast<LoadSDNode>(N);
4871 // Test whether the given value is a vector value which will be legalized
4873 static bool WillBeConstantPoolLoad(SDNode *N) {
4874 if (N->getOpcode() != ISD::BUILD_VECTOR)
4877 // Check for any non-constant elements.
4878 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4879 switch (N->getOperand(i).getNode()->getOpcode()) {
4881 case ISD::ConstantFP:
4888 // Vectors of all-zeros and all-ones are materialized with special
4889 // instructions rather than being loaded.
4890 return !ISD::isBuildVectorAllZeros(N) &&
4891 !ISD::isBuildVectorAllOnes(N);
4894 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4895 /// match movlp{s|d}. The lower half elements should come from lower half of
4896 /// V1 (and in order), and the upper half elements should come from the upper
4897 /// half of V2 (and in order). And since V1 will become the source of the
4898 /// MOVLP, it must be either a vector load or a scalar load to vector.
4899 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4900 ArrayRef<int> Mask, MVT VT) {
4901 if (!VT.is128BitVector())
4904 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4906 // Is V2 is a vector load, don't do this transformation. We will try to use
4907 // load folding shufps op.
4908 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4911 unsigned NumElems = VT.getVectorNumElements();
4913 if (NumElems != 2 && NumElems != 4)
4915 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4916 if (!isUndefOrEqual(Mask[i], i))
4918 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4919 if (!isUndefOrEqual(Mask[i], i+NumElems))
4924 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4925 /// to an zero vector.
4926 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4927 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4928 SDValue V1 = N->getOperand(0);
4929 SDValue V2 = N->getOperand(1);
4930 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4931 for (unsigned i = 0; i != NumElems; ++i) {
4932 int Idx = N->getMaskElt(i);
4933 if (Idx >= (int)NumElems) {
4934 unsigned Opc = V2.getOpcode();
4935 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4937 if (Opc != ISD::BUILD_VECTOR ||
4938 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4940 } else if (Idx >= 0) {
4941 unsigned Opc = V1.getOpcode();
4942 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4944 if (Opc != ISD::BUILD_VECTOR ||
4945 !X86::isZeroNode(V1.getOperand(Idx)))
4952 /// getZeroVector - Returns a vector of specified type with all zero elements.
4954 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4955 SelectionDAG &DAG, SDLoc dl) {
4956 assert(VT.isVector() && "Expected a vector type");
4958 // Always build SSE zero vectors as <4 x i32> bitcasted
4959 // to their dest type. This ensures they get CSE'd.
4961 if (VT.is128BitVector()) { // SSE
4962 if (Subtarget->hasSSE2()) { // SSE2
4963 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4964 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4966 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4967 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4969 } else if (VT.is256BitVector()) { // AVX
4970 if (Subtarget->hasInt256()) { // AVX2
4971 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4972 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4973 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4975 // 256-bit logic and arithmetic instructions in AVX are all
4976 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4977 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4978 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4979 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4981 } else if (VT.is512BitVector()) { // AVX-512
4982 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4983 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4984 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4985 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4986 } else if (VT.getScalarType() == MVT::i1) {
4987 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4988 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4989 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4990 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4992 llvm_unreachable("Unexpected vector type");
4994 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4997 /// getOnesVector - Returns a vector of specified type with all bits set.
4998 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4999 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5000 /// Then bitcast to their original type, ensuring they get CSE'd.
5001 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5003 assert(VT.isVector() && "Expected a vector type");
5005 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5007 if (VT.is256BitVector()) {
5008 if (HasInt256) { // AVX2
5009 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5010 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5012 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5013 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5015 } else if (VT.is128BitVector()) {
5016 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5018 llvm_unreachable("Unexpected vector type");
5020 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5023 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5024 /// that point to V2 points to its first element.
5025 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5026 for (unsigned i = 0; i != NumElems; ++i) {
5027 if (Mask[i] > (int)NumElems) {
5033 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5034 /// operation of specified width.
5035 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5037 unsigned NumElems = VT.getVectorNumElements();
5038 SmallVector<int, 8> Mask;
5039 Mask.push_back(NumElems);
5040 for (unsigned i = 1; i != NumElems; ++i)
5042 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5045 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5046 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5048 unsigned NumElems = VT.getVectorNumElements();
5049 SmallVector<int, 8> Mask;
5050 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5052 Mask.push_back(i + NumElems);
5054 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5057 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5058 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5060 unsigned NumElems = VT.getVectorNumElements();
5061 SmallVector<int, 8> Mask;
5062 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5063 Mask.push_back(i + Half);
5064 Mask.push_back(i + NumElems + Half);
5066 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5069 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5070 // a generic shuffle instruction because the target has no such instructions.
5071 // Generate shuffles which repeat i16 and i8 several times until they can be
5072 // represented by v4f32 and then be manipulated by target suported shuffles.
5073 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5074 MVT VT = V.getSimpleValueType();
5075 int NumElems = VT.getVectorNumElements();
5078 while (NumElems > 4) {
5079 if (EltNo < NumElems/2) {
5080 V = getUnpackl(DAG, dl, VT, V, V);
5082 V = getUnpackh(DAG, dl, VT, V, V);
5083 EltNo -= NumElems/2;
5090 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5091 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5092 MVT VT = V.getSimpleValueType();
5095 if (VT.is128BitVector()) {
5096 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5097 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5098 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5100 } else if (VT.is256BitVector()) {
5101 // To use VPERMILPS to splat scalars, the second half of indicies must
5102 // refer to the higher part, which is a duplication of the lower one,
5103 // because VPERMILPS can only handle in-lane permutations.
5104 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5105 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5107 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5108 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5111 llvm_unreachable("Vector size not supported");
5113 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5116 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5117 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5118 MVT SrcVT = SV->getSimpleValueType(0);
5119 SDValue V1 = SV->getOperand(0);
5122 int EltNo = SV->getSplatIndex();
5123 int NumElems = SrcVT.getVectorNumElements();
5124 bool Is256BitVec = SrcVT.is256BitVector();
5126 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5127 "Unknown how to promote splat for type");
5129 // Extract the 128-bit part containing the splat element and update
5130 // the splat element index when it refers to the higher register.
5132 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5133 if (EltNo >= NumElems/2)
5134 EltNo -= NumElems/2;
5137 // All i16 and i8 vector types can't be used directly by a generic shuffle
5138 // instruction because the target has no such instruction. Generate shuffles
5139 // which repeat i16 and i8 several times until they fit in i32, and then can
5140 // be manipulated by target suported shuffles.
5141 MVT EltVT = SrcVT.getVectorElementType();
5142 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5143 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5145 // Recreate the 256-bit vector and place the same 128-bit vector
5146 // into the low and high part. This is necessary because we want
5147 // to use VPERM* to shuffle the vectors
5149 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5152 return getLegalSplat(DAG, V1, EltNo);
5155 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5156 /// vector of zero or undef vector. This produces a shuffle where the low
5157 /// element of V2 is swizzled into the zero/undef vector, landing at element
5158 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5159 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5161 const X86Subtarget *Subtarget,
5162 SelectionDAG &DAG) {
5163 MVT VT = V2.getSimpleValueType();
5165 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5166 unsigned NumElems = VT.getVectorNumElements();
5167 SmallVector<int, 16> MaskVec;
5168 for (unsigned i = 0; i != NumElems; ++i)
5169 // If this is the insertion idx, put the low elt of V2 here.
5170 MaskVec.push_back(i == Idx ? NumElems : i);
5171 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5174 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5175 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5176 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5177 /// shuffles which use a single input multiple times, and in those cases it will
5178 /// adjust the mask to only have indices within that single input.
5179 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5180 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5181 unsigned NumElems = VT.getVectorNumElements();
5185 bool IsFakeUnary = false;
5186 switch(N->getOpcode()) {
5188 ImmN = N->getOperand(N->getNumOperands()-1);
5189 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5190 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5192 case X86ISD::UNPCKH:
5193 DecodeUNPCKHMask(VT, Mask);
5194 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5196 case X86ISD::UNPCKL:
5197 DecodeUNPCKLMask(VT, Mask);
5198 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5200 case X86ISD::MOVHLPS:
5201 DecodeMOVHLPSMask(NumElems, Mask);
5202 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5204 case X86ISD::MOVLHPS:
5205 DecodeMOVLHPSMask(NumElems, Mask);
5206 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5208 case X86ISD::PALIGNR:
5209 ImmN = N->getOperand(N->getNumOperands()-1);
5210 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5212 case X86ISD::PSHUFD:
5213 case X86ISD::VPERMILP:
5214 ImmN = N->getOperand(N->getNumOperands()-1);
5215 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5218 case X86ISD::PSHUFHW:
5219 ImmN = N->getOperand(N->getNumOperands()-1);
5220 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5223 case X86ISD::PSHUFLW:
5224 ImmN = N->getOperand(N->getNumOperands()-1);
5225 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5228 case X86ISD::PSHUFB: {
5230 SDValue MaskNode = N->getOperand(1);
5231 while (MaskNode->getOpcode() == ISD::BITCAST)
5232 MaskNode = MaskNode->getOperand(0);
5234 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5235 // If we have a build-vector, then things are easy.
5236 EVT VT = MaskNode.getValueType();
5237 assert(VT.isVector() &&
5238 "Can't produce a non-vector with a build_vector!");
5239 if (!VT.isInteger())
5242 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5244 SmallVector<uint64_t, 32> RawMask;
5245 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5246 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5249 APInt MaskElement = CN->getAPIntValue();
5251 // We now have to decode the element which could be any integer size and
5252 // extract each byte of it.
5253 for (int j = 0; j < NumBytesPerElement; ++j) {
5254 // Note that this is x86 and so always little endian: the low byte is
5255 // the first byte of the mask.
5256 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5257 MaskElement = MaskElement.lshr(8);
5260 DecodePSHUFBMask(RawMask, Mask);
5264 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5268 SDValue Ptr = MaskLoad->getBasePtr();
5269 if (Ptr->getOpcode() == X86ISD::Wrapper)
5270 Ptr = Ptr->getOperand(0);
5272 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5273 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5276 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5277 // FIXME: Support AVX-512 here.
5278 if (!C->getType()->isVectorTy() ||
5279 (C->getNumElements() != 16 && C->getNumElements() != 32))
5282 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5283 DecodePSHUFBMask(C, Mask);
5289 case X86ISD::VPERMI:
5290 ImmN = N->getOperand(N->getNumOperands()-1);
5291 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5295 case X86ISD::MOVSD: {
5296 // The index 0 always comes from the first element of the second source,
5297 // this is why MOVSS and MOVSD are used in the first place. The other
5298 // elements come from the other positions of the first source vector
5299 Mask.push_back(NumElems);
5300 for (unsigned i = 1; i != NumElems; ++i) {
5305 case X86ISD::VPERM2X128:
5306 ImmN = N->getOperand(N->getNumOperands()-1);
5307 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5308 if (Mask.empty()) return false;
5310 case X86ISD::MOVDDUP:
5311 case X86ISD::MOVLHPD:
5312 case X86ISD::MOVLPD:
5313 case X86ISD::MOVLPS:
5314 case X86ISD::MOVSHDUP:
5315 case X86ISD::MOVSLDUP:
5316 // Not yet implemented
5318 default: llvm_unreachable("unknown target shuffle node");
5321 // If we have a fake unary shuffle, the shuffle mask is spread across two
5322 // inputs that are actually the same node. Re-map the mask to always point
5323 // into the first input.
5326 if (M >= (int)Mask.size())
5332 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5333 /// element of the result of the vector shuffle.
5334 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5337 return SDValue(); // Limit search depth.
5339 SDValue V = SDValue(N, 0);
5340 EVT VT = V.getValueType();
5341 unsigned Opcode = V.getOpcode();
5343 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5344 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5345 int Elt = SV->getMaskElt(Index);
5348 return DAG.getUNDEF(VT.getVectorElementType());
5350 unsigned NumElems = VT.getVectorNumElements();
5351 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5352 : SV->getOperand(1);
5353 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5356 // Recurse into target specific vector shuffles to find scalars.
5357 if (isTargetShuffle(Opcode)) {
5358 MVT ShufVT = V.getSimpleValueType();
5359 unsigned NumElems = ShufVT.getVectorNumElements();
5360 SmallVector<int, 16> ShuffleMask;
5363 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5366 int Elt = ShuffleMask[Index];
5368 return DAG.getUNDEF(ShufVT.getVectorElementType());
5370 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5372 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5376 // Actual nodes that may contain scalar elements
5377 if (Opcode == ISD::BITCAST) {
5378 V = V.getOperand(0);
5379 EVT SrcVT = V.getValueType();
5380 unsigned NumElems = VT.getVectorNumElements();
5382 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5386 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5387 return (Index == 0) ? V.getOperand(0)
5388 : DAG.getUNDEF(VT.getVectorElementType());
5390 if (V.getOpcode() == ISD::BUILD_VECTOR)
5391 return V.getOperand(Index);
5396 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5397 /// shuffle operation which come from a consecutively from a zero. The
5398 /// search can start in two different directions, from left or right.
5399 /// We count undefs as zeros until PreferredNum is reached.
5400 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5401 unsigned NumElems, bool ZerosFromLeft,
5403 unsigned PreferredNum = -1U) {
5404 unsigned NumZeros = 0;
5405 for (unsigned i = 0; i != NumElems; ++i) {
5406 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5407 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5411 if (X86::isZeroNode(Elt))
5413 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5414 NumZeros = std::min(NumZeros + 1, PreferredNum);
5422 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5423 /// correspond consecutively to elements from one of the vector operands,
5424 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5426 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5427 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5428 unsigned NumElems, unsigned &OpNum) {
5429 bool SeenV1 = false;
5430 bool SeenV2 = false;
5432 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5433 int Idx = SVOp->getMaskElt(i);
5434 // Ignore undef indicies
5438 if (Idx < (int)NumElems)
5443 // Only accept consecutive elements from the same vector
5444 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5448 OpNum = SeenV1 ? 0 : 1;
5452 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5453 /// logical left shift of a vector.
5454 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5455 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5457 SVOp->getSimpleValueType(0).getVectorNumElements();
5458 unsigned NumZeros = getNumOfConsecutiveZeros(
5459 SVOp, NumElems, false /* check zeros from right */, DAG,
5460 SVOp->getMaskElt(0));
5466 // Considering the elements in the mask that are not consecutive zeros,
5467 // check if they consecutively come from only one of the source vectors.
5469 // V1 = {X, A, B, C} 0
5471 // vector_shuffle V1, V2 <1, 2, 3, X>
5473 if (!isShuffleMaskConsecutive(SVOp,
5474 0, // Mask Start Index
5475 NumElems-NumZeros, // Mask End Index(exclusive)
5476 NumZeros, // Where to start looking in the src vector
5477 NumElems, // Number of elements in vector
5478 OpSrc)) // Which source operand ?
5483 ShVal = SVOp->getOperand(OpSrc);
5487 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5488 /// logical left shift of a vector.
5489 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5490 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5492 SVOp->getSimpleValueType(0).getVectorNumElements();
5493 unsigned NumZeros = getNumOfConsecutiveZeros(
5494 SVOp, NumElems, true /* check zeros from left */, DAG,
5495 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5501 // Considering the elements in the mask that are not consecutive zeros,
5502 // check if they consecutively come from only one of the source vectors.
5504 // 0 { A, B, X, X } = V2
5506 // vector_shuffle V1, V2 <X, X, 4, 5>
5508 if (!isShuffleMaskConsecutive(SVOp,
5509 NumZeros, // Mask Start Index
5510 NumElems, // Mask End Index(exclusive)
5511 0, // Where to start looking in the src vector
5512 NumElems, // Number of elements in vector
5513 OpSrc)) // Which source operand ?
5518 ShVal = SVOp->getOperand(OpSrc);
5522 /// isVectorShift - Returns true if the shuffle can be implemented as a
5523 /// logical left or right shift of a vector.
5524 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5525 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5526 // Although the logic below support any bitwidth size, there are no
5527 // shift instructions which handle more than 128-bit vectors.
5528 if (!SVOp->getSimpleValueType(0).is128BitVector())
5531 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5532 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5538 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5540 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5541 unsigned NumNonZero, unsigned NumZero,
5543 const X86Subtarget* Subtarget,
5544 const TargetLowering &TLI) {
5551 for (unsigned i = 0; i < 16; ++i) {
5552 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5553 if (ThisIsNonZero && First) {
5555 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5557 V = DAG.getUNDEF(MVT::v8i16);
5562 SDValue ThisElt, LastElt;
5563 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5564 if (LastIsNonZero) {
5565 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5566 MVT::i16, Op.getOperand(i-1));
5568 if (ThisIsNonZero) {
5569 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5570 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5571 ThisElt, DAG.getConstant(8, MVT::i8));
5573 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5577 if (ThisElt.getNode())
5578 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5579 DAG.getIntPtrConstant(i/2));
5583 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5586 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5588 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5589 unsigned NumNonZero, unsigned NumZero,
5591 const X86Subtarget* Subtarget,
5592 const TargetLowering &TLI) {
5599 for (unsigned i = 0; i < 8; ++i) {
5600 bool isNonZero = (NonZeros & (1 << i)) != 0;
5604 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5606 V = DAG.getUNDEF(MVT::v8i16);
5609 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5610 MVT::v8i16, V, Op.getOperand(i),
5611 DAG.getIntPtrConstant(i));
5618 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5619 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5620 unsigned NonZeros, unsigned NumNonZero,
5621 unsigned NumZero, SelectionDAG &DAG,
5622 const X86Subtarget *Subtarget,
5623 const TargetLowering &TLI) {
5624 // We know there's at least one non-zero element
5625 unsigned FirstNonZeroIdx = 0;
5626 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5627 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5628 X86::isZeroNode(FirstNonZero)) {
5630 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5633 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5634 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5637 SDValue V = FirstNonZero.getOperand(0);
5638 MVT VVT = V.getSimpleValueType();
5639 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5642 unsigned FirstNonZeroDst =
5643 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5644 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5645 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5646 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5648 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5649 SDValue Elem = Op.getOperand(Idx);
5650 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5653 // TODO: What else can be here? Deal with it.
5654 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5657 // TODO: Some optimizations are still possible here
5658 // ex: Getting one element from a vector, and the rest from another.
5659 if (Elem.getOperand(0) != V)
5662 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5665 else if (IncorrectIdx == -1U) {
5669 // There was already one element with an incorrect index.
5670 // We can't optimize this case to an insertps.
5674 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5676 EVT VT = Op.getSimpleValueType();
5677 unsigned ElementMoveMask = 0;
5678 if (IncorrectIdx == -1U)
5679 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5681 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5683 SDValue InsertpsMask =
5684 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5685 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5691 /// getVShift - Return a vector logical shift node.
5693 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5694 unsigned NumBits, SelectionDAG &DAG,
5695 const TargetLowering &TLI, SDLoc dl) {
5696 assert(VT.is128BitVector() && "Unknown type for VShift");
5697 EVT ShVT = MVT::v2i64;
5698 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5699 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5700 return DAG.getNode(ISD::BITCAST, dl, VT,
5701 DAG.getNode(Opc, dl, ShVT, SrcOp,
5702 DAG.getConstant(NumBits,
5703 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5707 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5709 // Check if the scalar load can be widened into a vector load. And if
5710 // the address is "base + cst" see if the cst can be "absorbed" into
5711 // the shuffle mask.
5712 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5713 SDValue Ptr = LD->getBasePtr();
5714 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5716 EVT PVT = LD->getValueType(0);
5717 if (PVT != MVT::i32 && PVT != MVT::f32)
5722 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5723 FI = FINode->getIndex();
5725 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5726 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5727 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5728 Offset = Ptr.getConstantOperandVal(1);
5729 Ptr = Ptr.getOperand(0);
5734 // FIXME: 256-bit vector instructions don't require a strict alignment,
5735 // improve this code to support it better.
5736 unsigned RequiredAlign = VT.getSizeInBits()/8;
5737 SDValue Chain = LD->getChain();
5738 // Make sure the stack object alignment is at least 16 or 32.
5739 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5740 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5741 if (MFI->isFixedObjectIndex(FI)) {
5742 // Can't change the alignment. FIXME: It's possible to compute
5743 // the exact stack offset and reference FI + adjust offset instead.
5744 // If someone *really* cares about this. That's the way to implement it.
5747 MFI->setObjectAlignment(FI, RequiredAlign);
5751 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5752 // Ptr + (Offset & ~15).
5755 if ((Offset % RequiredAlign) & 3)
5757 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5759 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5760 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5762 int EltNo = (Offset - StartOffset) >> 2;
5763 unsigned NumElems = VT.getVectorNumElements();
5765 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5766 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5767 LD->getPointerInfo().getWithOffset(StartOffset),
5768 false, false, false, 0);
5770 SmallVector<int, 8> Mask;
5771 for (unsigned i = 0; i != NumElems; ++i)
5772 Mask.push_back(EltNo);
5774 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5780 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5781 /// vector of type 'VT', see if the elements can be replaced by a single large
5782 /// load which has the same value as a build_vector whose operands are 'elts'.
5784 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5786 /// FIXME: we'd also like to handle the case where the last elements are zero
5787 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5788 /// There's even a handy isZeroNode for that purpose.
5789 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5790 SDLoc &DL, SelectionDAG &DAG,
5791 bool isAfterLegalize) {
5792 EVT EltVT = VT.getVectorElementType();
5793 unsigned NumElems = Elts.size();
5795 LoadSDNode *LDBase = nullptr;
5796 unsigned LastLoadedElt = -1U;
5798 // For each element in the initializer, see if we've found a load or an undef.
5799 // If we don't find an initial load element, or later load elements are
5800 // non-consecutive, bail out.
5801 for (unsigned i = 0; i < NumElems; ++i) {
5802 SDValue Elt = Elts[i];
5804 if (!Elt.getNode() ||
5805 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5808 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5810 LDBase = cast<LoadSDNode>(Elt.getNode());
5814 if (Elt.getOpcode() == ISD::UNDEF)
5817 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5818 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5823 // If we have found an entire vector of loads and undefs, then return a large
5824 // load of the entire vector width starting at the base pointer. If we found
5825 // consecutive loads for the low half, generate a vzext_load node.
5826 if (LastLoadedElt == NumElems - 1) {
5828 if (isAfterLegalize &&
5829 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5832 SDValue NewLd = SDValue();
5834 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5835 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5836 LDBase->getPointerInfo(),
5837 LDBase->isVolatile(), LDBase->isNonTemporal(),
5838 LDBase->isInvariant(), 0);
5839 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5840 LDBase->getPointerInfo(),
5841 LDBase->isVolatile(), LDBase->isNonTemporal(),
5842 LDBase->isInvariant(), LDBase->getAlignment());
5844 if (LDBase->hasAnyUseOfValue(1)) {
5845 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5847 SDValue(NewLd.getNode(), 1));
5848 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5849 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5850 SDValue(NewLd.getNode(), 1));
5855 if (NumElems == 4 && LastLoadedElt == 1 &&
5856 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5857 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5858 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5860 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5861 LDBase->getPointerInfo(),
5862 LDBase->getAlignment(),
5863 false/*isVolatile*/, true/*ReadMem*/,
5866 // Make sure the newly-created LOAD is in the same position as LDBase in
5867 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5868 // update uses of LDBase's output chain to use the TokenFactor.
5869 if (LDBase->hasAnyUseOfValue(1)) {
5870 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5871 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5872 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5873 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5874 SDValue(ResNode.getNode(), 1));
5877 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5882 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5883 /// to generate a splat value for the following cases:
5884 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5885 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5886 /// a scalar load, or a constant.
5887 /// The VBROADCAST node is returned when a pattern is found,
5888 /// or SDValue() otherwise.
5889 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5890 SelectionDAG &DAG) {
5891 if (!Subtarget->hasFp256())
5894 MVT VT = Op.getSimpleValueType();
5897 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5898 "Unsupported vector type for broadcast.");
5903 switch (Op.getOpcode()) {
5905 // Unknown pattern found.
5908 case ISD::BUILD_VECTOR: {
5909 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5910 BitVector UndefElements;
5911 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5913 // We need a splat of a single value to use broadcast, and it doesn't
5914 // make any sense if the value is only in one element of the vector.
5915 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5919 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5920 Ld.getOpcode() == ISD::ConstantFP);
5922 // Make sure that all of the users of a non-constant load are from the
5923 // BUILD_VECTOR node.
5924 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5929 case ISD::VECTOR_SHUFFLE: {
5930 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5932 // Shuffles must have a splat mask where the first element is
5934 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5937 SDValue Sc = Op.getOperand(0);
5938 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5939 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5941 if (!Subtarget->hasInt256())
5944 // Use the register form of the broadcast instruction available on AVX2.
5945 if (VT.getSizeInBits() >= 256)
5946 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5947 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5950 Ld = Sc.getOperand(0);
5951 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5952 Ld.getOpcode() == ISD::ConstantFP);
5954 // The scalar_to_vector node and the suspected
5955 // load node must have exactly one user.
5956 // Constants may have multiple users.
5958 // AVX-512 has register version of the broadcast
5959 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5960 Ld.getValueType().getSizeInBits() >= 32;
5961 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5968 bool IsGE256 = (VT.getSizeInBits() >= 256);
5970 // Handle the broadcasting a single constant scalar from the constant pool
5971 // into a vector. On Sandybridge it is still better to load a constant vector
5972 // from the constant pool and not to broadcast it from a scalar.
5973 if (ConstSplatVal && Subtarget->hasInt256()) {
5974 EVT CVT = Ld.getValueType();
5975 assert(!CVT.isVector() && "Must not broadcast a vector type");
5976 unsigned ScalarSize = CVT.getSizeInBits();
5978 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5979 const Constant *C = nullptr;
5980 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5981 C = CI->getConstantIntValue();
5982 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5983 C = CF->getConstantFPValue();
5985 assert(C && "Invalid constant type");
5987 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5988 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5989 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5990 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5991 MachinePointerInfo::getConstantPool(),
5992 false, false, false, Alignment);
5994 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5998 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5999 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6001 // Handle AVX2 in-register broadcasts.
6002 if (!IsLoad && Subtarget->hasInt256() &&
6003 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6004 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6006 // The scalar source must be a normal load.
6010 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6011 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6013 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6014 // double since there is no vbroadcastsd xmm
6015 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6016 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6017 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6020 // Unsupported broadcast.
6024 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6025 /// underlying vector and index.
6027 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6029 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6031 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6032 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6035 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6037 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6039 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6040 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6043 // In this case the vector is the extract_subvector expression and the index
6044 // is 2, as specified by the shuffle.
6045 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6046 SDValue ShuffleVec = SVOp->getOperand(0);
6047 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6048 assert(ShuffleVecVT.getVectorElementType() ==
6049 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6051 int ShuffleIdx = SVOp->getMaskElt(Idx);
6052 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6053 ExtractedFromVec = ShuffleVec;
6059 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6060 MVT VT = Op.getSimpleValueType();
6062 // Skip if insert_vec_elt is not supported.
6063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6064 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6068 unsigned NumElems = Op.getNumOperands();
6072 SmallVector<unsigned, 4> InsertIndices;
6073 SmallVector<int, 8> Mask(NumElems, -1);
6075 for (unsigned i = 0; i != NumElems; ++i) {
6076 unsigned Opc = Op.getOperand(i).getOpcode();
6078 if (Opc == ISD::UNDEF)
6081 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6082 // Quit if more than 1 elements need inserting.
6083 if (InsertIndices.size() > 1)
6086 InsertIndices.push_back(i);
6090 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6091 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6092 // Quit if non-constant index.
6093 if (!isa<ConstantSDNode>(ExtIdx))
6095 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6097 // Quit if extracted from vector of different type.
6098 if (ExtractedFromVec.getValueType() != VT)
6101 if (!VecIn1.getNode())
6102 VecIn1 = ExtractedFromVec;
6103 else if (VecIn1 != ExtractedFromVec) {
6104 if (!VecIn2.getNode())
6105 VecIn2 = ExtractedFromVec;
6106 else if (VecIn2 != ExtractedFromVec)
6107 // Quit if more than 2 vectors to shuffle
6111 if (ExtractedFromVec == VecIn1)
6113 else if (ExtractedFromVec == VecIn2)
6114 Mask[i] = Idx + NumElems;
6117 if (!VecIn1.getNode())
6120 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6121 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6122 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6123 unsigned Idx = InsertIndices[i];
6124 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6125 DAG.getIntPtrConstant(Idx));
6131 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6133 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6135 MVT VT = Op.getSimpleValueType();
6136 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6137 "Unexpected type in LowerBUILD_VECTORvXi1!");
6140 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6141 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6142 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6143 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6146 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6147 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6148 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6149 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6152 bool AllContants = true;
6153 uint64_t Immediate = 0;
6154 int NonConstIdx = -1;
6155 bool IsSplat = true;
6156 unsigned NumNonConsts = 0;
6157 unsigned NumConsts = 0;
6158 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6159 SDValue In = Op.getOperand(idx);
6160 if (In.getOpcode() == ISD::UNDEF)
6162 if (!isa<ConstantSDNode>(In)) {
6163 AllContants = false;
6169 if (cast<ConstantSDNode>(In)->getZExtValue())
6170 Immediate |= (1ULL << idx);
6172 if (In != Op.getOperand(0))
6177 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6178 DAG.getConstant(Immediate, MVT::i16));
6179 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6180 DAG.getIntPtrConstant(0));
6183 if (NumNonConsts == 1 && NonConstIdx != 0) {
6186 SDValue VecAsImm = DAG.getConstant(Immediate,
6187 MVT::getIntegerVT(VT.getSizeInBits()));
6188 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6191 DstVec = DAG.getUNDEF(VT);
6192 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6193 Op.getOperand(NonConstIdx),
6194 DAG.getIntPtrConstant(NonConstIdx));
6196 if (!IsSplat && (NonConstIdx != 0))
6197 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6198 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6201 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6202 DAG.getConstant(-1, SelectVT),
6203 DAG.getConstant(0, SelectVT));
6205 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6206 DAG.getConstant((Immediate | 1), SelectVT),
6207 DAG.getConstant(Immediate, SelectVT));
6208 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6211 /// \brief Return true if \p N implements a horizontal binop and return the
6212 /// operands for the horizontal binop into V0 and V1.
6214 /// This is a helper function of PerformBUILD_VECTORCombine.
6215 /// This function checks that the build_vector \p N in input implements a
6216 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6217 /// operation to match.
6218 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6219 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6220 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6223 /// This function only analyzes elements of \p N whose indices are
6224 /// in range [BaseIdx, LastIdx).
6225 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6227 unsigned BaseIdx, unsigned LastIdx,
6228 SDValue &V0, SDValue &V1) {
6229 EVT VT = N->getValueType(0);
6231 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6232 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6233 "Invalid Vector in input!");
6235 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6236 bool CanFold = true;
6237 unsigned ExpectedVExtractIdx = BaseIdx;
6238 unsigned NumElts = LastIdx - BaseIdx;
6239 V0 = DAG.getUNDEF(VT);
6240 V1 = DAG.getUNDEF(VT);
6242 // Check if N implements a horizontal binop.
6243 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6244 SDValue Op = N->getOperand(i + BaseIdx);
6247 if (Op->getOpcode() == ISD::UNDEF) {
6248 // Update the expected vector extract index.
6249 if (i * 2 == NumElts)
6250 ExpectedVExtractIdx = BaseIdx;
6251 ExpectedVExtractIdx += 2;
6255 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6260 SDValue Op0 = Op.getOperand(0);
6261 SDValue Op1 = Op.getOperand(1);
6263 // Try to match the following pattern:
6264 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6265 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6266 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6267 Op0.getOperand(0) == Op1.getOperand(0) &&
6268 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6269 isa<ConstantSDNode>(Op1.getOperand(1)));
6273 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6274 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6276 if (i * 2 < NumElts) {
6277 if (V0.getOpcode() == ISD::UNDEF)
6278 V0 = Op0.getOperand(0);
6280 if (V1.getOpcode() == ISD::UNDEF)
6281 V1 = Op0.getOperand(0);
6282 if (i * 2 == NumElts)
6283 ExpectedVExtractIdx = BaseIdx;
6286 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6287 if (I0 == ExpectedVExtractIdx)
6288 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6289 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6290 // Try to match the following dag sequence:
6291 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6292 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6296 ExpectedVExtractIdx += 2;
6302 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6303 /// a concat_vector.
6305 /// This is a helper function of PerformBUILD_VECTORCombine.
6306 /// This function expects two 256-bit vectors called V0 and V1.
6307 /// At first, each vector is split into two separate 128-bit vectors.
6308 /// Then, the resulting 128-bit vectors are used to implement two
6309 /// horizontal binary operations.
6311 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6313 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6314 /// the two new horizontal binop.
6315 /// When Mode is set, the first horizontal binop dag node would take as input
6316 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6317 /// horizontal binop dag node would take as input the lower 128-bit of V1
6318 /// and the upper 128-bit of V1.
6320 /// HADD V0_LO, V0_HI
6321 /// HADD V1_LO, V1_HI
6323 /// Otherwise, the first horizontal binop dag node takes as input the lower
6324 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6325 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6327 /// HADD V0_LO, V1_LO
6328 /// HADD V0_HI, V1_HI
6330 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6331 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6332 /// the upper 128-bits of the result.
6333 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6334 SDLoc DL, SelectionDAG &DAG,
6335 unsigned X86Opcode, bool Mode,
6336 bool isUndefLO, bool isUndefHI) {
6337 EVT VT = V0.getValueType();
6338 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6339 "Invalid nodes in input!");
6341 unsigned NumElts = VT.getVectorNumElements();
6342 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6343 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6344 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6345 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6346 EVT NewVT = V0_LO.getValueType();
6348 SDValue LO = DAG.getUNDEF(NewVT);
6349 SDValue HI = DAG.getUNDEF(NewVT);
6352 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6353 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6354 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6355 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6356 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6358 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6359 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6360 V1_LO->getOpcode() != ISD::UNDEF))
6361 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6363 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6364 V1_HI->getOpcode() != ISD::UNDEF))
6365 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6368 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6371 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6372 /// sequence of 'vadd + vsub + blendi'.
6373 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6374 const X86Subtarget *Subtarget) {
6376 EVT VT = BV->getValueType(0);
6377 unsigned NumElts = VT.getVectorNumElements();
6378 SDValue InVec0 = DAG.getUNDEF(VT);
6379 SDValue InVec1 = DAG.getUNDEF(VT);
6381 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6382 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6384 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6385 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6386 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6389 // Odd-numbered elements in the input build vector are obtained from
6390 // adding two integer/float elements.
6391 // Even-numbered elements in the input build vector are obtained from
6392 // subtracting two integer/float elements.
6393 unsigned ExpectedOpcode = ISD::FSUB;
6394 unsigned NextExpectedOpcode = ISD::FADD;
6395 bool AddFound = false;
6396 bool SubFound = false;
6398 for (unsigned i = 0, e = NumElts; i != e; i++) {
6399 SDValue Op = BV->getOperand(i);
6401 // Skip 'undef' values.
6402 unsigned Opcode = Op.getOpcode();
6403 if (Opcode == ISD::UNDEF) {
6404 std::swap(ExpectedOpcode, NextExpectedOpcode);
6408 // Early exit if we found an unexpected opcode.
6409 if (Opcode != ExpectedOpcode)
6412 SDValue Op0 = Op.getOperand(0);
6413 SDValue Op1 = Op.getOperand(1);
6415 // Try to match the following pattern:
6416 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6417 // Early exit if we cannot match that sequence.
6418 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6419 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6420 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6421 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6422 Op0.getOperand(1) != Op1.getOperand(1))
6425 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6429 // We found a valid add/sub node. Update the information accordingly.
6435 // Update InVec0 and InVec1.
6436 if (InVec0.getOpcode() == ISD::UNDEF)
6437 InVec0 = Op0.getOperand(0);
6438 if (InVec1.getOpcode() == ISD::UNDEF)
6439 InVec1 = Op1.getOperand(0);
6441 // Make sure that operands in input to each add/sub node always
6442 // come from a same pair of vectors.
6443 if (InVec0 != Op0.getOperand(0)) {
6444 if (ExpectedOpcode == ISD::FSUB)
6447 // FADD is commutable. Try to commute the operands
6448 // and then test again.
6449 std::swap(Op0, Op1);
6450 if (InVec0 != Op0.getOperand(0))
6454 if (InVec1 != Op1.getOperand(0))
6457 // Update the pair of expected opcodes.
6458 std::swap(ExpectedOpcode, NextExpectedOpcode);
6461 // Don't try to fold this build_vector into a VSELECT if it has
6462 // too many UNDEF operands.
6463 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6464 InVec1.getOpcode() != ISD::UNDEF) {
6465 // Emit a sequence of vector add and sub followed by a VSELECT.
6466 // The new VSELECT will be lowered into a BLENDI.
6467 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6468 // and emit a single ADDSUB instruction.
6469 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6470 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6472 // Construct the VSELECT mask.
6473 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6474 EVT SVT = MaskVT.getVectorElementType();
6475 unsigned SVTBits = SVT.getSizeInBits();
6476 SmallVector<SDValue, 8> Ops;
6478 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6479 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6480 APInt::getAllOnesValue(SVTBits);
6481 SDValue Constant = DAG.getConstant(Value, SVT);
6482 Ops.push_back(Constant);
6485 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6486 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6492 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6493 const X86Subtarget *Subtarget) {
6495 EVT VT = N->getValueType(0);
6496 unsigned NumElts = VT.getVectorNumElements();
6497 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6498 SDValue InVec0, InVec1;
6500 // Try to match an ADDSUB.
6501 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6502 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6503 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6504 if (Value.getNode())
6508 // Try to match horizontal ADD/SUB.
6509 unsigned NumUndefsLO = 0;
6510 unsigned NumUndefsHI = 0;
6511 unsigned Half = NumElts/2;
6513 // Count the number of UNDEF operands in the build_vector in input.
6514 for (unsigned i = 0, e = Half; i != e; ++i)
6515 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6518 for (unsigned i = Half, e = NumElts; i != e; ++i)
6519 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6522 // Early exit if this is either a build_vector of all UNDEFs or all the
6523 // operands but one are UNDEF.
6524 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6527 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6528 // Try to match an SSE3 float HADD/HSUB.
6529 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6530 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6532 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6533 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6534 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6535 // Try to match an SSSE3 integer HADD/HSUB.
6536 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6537 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6539 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6540 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6543 if (!Subtarget->hasAVX())
6546 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6547 // Try to match an AVX horizontal add/sub of packed single/double
6548 // precision floating point values from 256-bit vectors.
6549 SDValue InVec2, InVec3;
6550 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6551 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6552 ((InVec0.getOpcode() == ISD::UNDEF ||
6553 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6554 ((InVec1.getOpcode() == ISD::UNDEF ||
6555 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6556 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6558 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6559 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6560 ((InVec0.getOpcode() == ISD::UNDEF ||
6561 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6562 ((InVec1.getOpcode() == ISD::UNDEF ||
6563 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6564 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6565 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6566 // Try to match an AVX2 horizontal add/sub of signed integers.
6567 SDValue InVec2, InVec3;
6569 bool CanFold = true;
6571 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6572 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6573 ((InVec0.getOpcode() == ISD::UNDEF ||
6574 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6575 ((InVec1.getOpcode() == ISD::UNDEF ||
6576 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6577 X86Opcode = X86ISD::HADD;
6578 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6579 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6580 ((InVec0.getOpcode() == ISD::UNDEF ||
6581 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6582 ((InVec1.getOpcode() == ISD::UNDEF ||
6583 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6584 X86Opcode = X86ISD::HSUB;
6589 // Fold this build_vector into a single horizontal add/sub.
6590 // Do this only if the target has AVX2.
6591 if (Subtarget->hasAVX2())
6592 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6594 // Do not try to expand this build_vector into a pair of horizontal
6595 // add/sub if we can emit a pair of scalar add/sub.
6596 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6599 // Convert this build_vector into a pair of horizontal binop followed by
6601 bool isUndefLO = NumUndefsLO == Half;
6602 bool isUndefHI = NumUndefsHI == Half;
6603 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6604 isUndefLO, isUndefHI);
6608 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6609 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6611 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6612 X86Opcode = X86ISD::HADD;
6613 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6614 X86Opcode = X86ISD::HSUB;
6615 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6616 X86Opcode = X86ISD::FHADD;
6617 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6618 X86Opcode = X86ISD::FHSUB;
6622 // Don't try to expand this build_vector into a pair of horizontal add/sub
6623 // if we can simply emit a pair of scalar add/sub.
6624 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6627 // Convert this build_vector into two horizontal add/sub followed by
6629 bool isUndefLO = NumUndefsLO == Half;
6630 bool isUndefHI = NumUndefsHI == Half;
6631 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6632 isUndefLO, isUndefHI);
6639 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6642 MVT VT = Op.getSimpleValueType();
6643 MVT ExtVT = VT.getVectorElementType();
6644 unsigned NumElems = Op.getNumOperands();
6646 // Generate vectors for predicate vectors.
6647 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6648 return LowerBUILD_VECTORvXi1(Op, DAG);
6650 // Vectors containing all zeros can be matched by pxor and xorps later
6651 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6652 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6653 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6654 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6657 return getZeroVector(VT, Subtarget, DAG, dl);
6660 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6661 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6662 // vpcmpeqd on 256-bit vectors.
6663 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6664 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6667 if (!VT.is512BitVector())
6668 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6671 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6672 if (Broadcast.getNode())
6675 unsigned EVTBits = ExtVT.getSizeInBits();
6677 unsigned NumZero = 0;
6678 unsigned NumNonZero = 0;
6679 unsigned NonZeros = 0;
6680 bool IsAllConstants = true;
6681 SmallSet<SDValue, 8> Values;
6682 for (unsigned i = 0; i < NumElems; ++i) {
6683 SDValue Elt = Op.getOperand(i);
6684 if (Elt.getOpcode() == ISD::UNDEF)
6687 if (Elt.getOpcode() != ISD::Constant &&
6688 Elt.getOpcode() != ISD::ConstantFP)
6689 IsAllConstants = false;
6690 if (X86::isZeroNode(Elt))
6693 NonZeros |= (1 << i);
6698 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6699 if (NumNonZero == 0)
6700 return DAG.getUNDEF(VT);
6702 // Special case for single non-zero, non-undef, element.
6703 if (NumNonZero == 1) {
6704 unsigned Idx = countTrailingZeros(NonZeros);
6705 SDValue Item = Op.getOperand(Idx);
6707 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6708 // the value are obviously zero, truncate the value to i32 and do the
6709 // insertion that way. Only do this if the value is non-constant or if the
6710 // value is a constant being inserted into element 0. It is cheaper to do
6711 // a constant pool load than it is to do a movd + shuffle.
6712 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6713 (!IsAllConstants || Idx == 0)) {
6714 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6716 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6717 EVT VecVT = MVT::v4i32;
6718 unsigned VecElts = 4;
6720 // Truncate the value (which may itself be a constant) to i32, and
6721 // convert it to a vector with movd (S2V+shuffle to zero extend).
6722 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6723 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6724 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6726 // Now we have our 32-bit value zero extended in the low element of
6727 // a vector. If Idx != 0, swizzle it into place.
6729 SmallVector<int, 4> Mask;
6730 Mask.push_back(Idx);
6731 for (unsigned i = 1; i != VecElts; ++i)
6733 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6736 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6740 // If we have a constant or non-constant insertion into the low element of
6741 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6742 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6743 // depending on what the source datatype is.
6746 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6748 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6749 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6750 if (VT.is256BitVector() || VT.is512BitVector()) {
6751 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6752 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6753 Item, DAG.getIntPtrConstant(0));
6755 assert(VT.is128BitVector() && "Expected an SSE value type!");
6756 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6757 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6758 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6761 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6762 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6763 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6764 if (VT.is256BitVector()) {
6765 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6766 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6768 assert(VT.is128BitVector() && "Expected an SSE value type!");
6769 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6771 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6775 // Is it a vector logical left shift?
6776 if (NumElems == 2 && Idx == 1 &&
6777 X86::isZeroNode(Op.getOperand(0)) &&
6778 !X86::isZeroNode(Op.getOperand(1))) {
6779 unsigned NumBits = VT.getSizeInBits();
6780 return getVShift(true, VT,
6781 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6782 VT, Op.getOperand(1)),
6783 NumBits/2, DAG, *this, dl);
6786 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6789 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6790 // is a non-constant being inserted into an element other than the low one,
6791 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6792 // movd/movss) to move this into the low element, then shuffle it into
6794 if (EVTBits == 32) {
6795 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6797 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6798 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6799 SmallVector<int, 8> MaskVec;
6800 for (unsigned i = 0; i != NumElems; ++i)
6801 MaskVec.push_back(i == Idx ? 0 : 1);
6802 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6806 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6807 if (Values.size() == 1) {
6808 if (EVTBits == 32) {
6809 // Instead of a shuffle like this:
6810 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6811 // Check if it's possible to issue this instead.
6812 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6815 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6816 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6821 // A vector full of immediates; various special cases are already
6822 // handled, so this is best done with a single constant-pool load.
6826 // For AVX-length vectors, build the individual 128-bit pieces and use
6827 // shuffles to put them in place.
6828 if (VT.is256BitVector() || VT.is512BitVector()) {
6829 SmallVector<SDValue, 64> V;
6830 for (unsigned i = 0; i != NumElems; ++i)
6831 V.push_back(Op.getOperand(i));
6833 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6835 // Build both the lower and upper subvector.
6836 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6837 makeArrayRef(&V[0], NumElems/2));
6838 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6839 makeArrayRef(&V[NumElems / 2], NumElems/2));
6841 // Recreate the wider vector with the lower and upper part.
6842 if (VT.is256BitVector())
6843 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6844 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6847 // Let legalizer expand 2-wide build_vectors.
6848 if (EVTBits == 64) {
6849 if (NumNonZero == 1) {
6850 // One half is zero or undef.
6851 unsigned Idx = countTrailingZeros(NonZeros);
6852 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6853 Op.getOperand(Idx));
6854 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6859 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6860 if (EVTBits == 8 && NumElems == 16) {
6861 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6863 if (V.getNode()) return V;
6866 if (EVTBits == 16 && NumElems == 8) {
6867 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6869 if (V.getNode()) return V;
6872 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6873 if (EVTBits == 32 && NumElems == 4) {
6874 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6875 NumZero, DAG, Subtarget, *this);
6880 // If element VT is == 32 bits, turn it into a number of shuffles.
6881 SmallVector<SDValue, 8> V(NumElems);
6882 if (NumElems == 4 && NumZero > 0) {
6883 for (unsigned i = 0; i < 4; ++i) {
6884 bool isZero = !(NonZeros & (1 << i));
6886 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6888 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6891 for (unsigned i = 0; i < 2; ++i) {
6892 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6895 V[i] = V[i*2]; // Must be a zero vector.
6898 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6901 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6904 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6909 bool Reverse1 = (NonZeros & 0x3) == 2;
6910 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6914 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6915 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6917 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6920 if (Values.size() > 1 && VT.is128BitVector()) {
6921 // Check for a build vector of consecutive loads.
6922 for (unsigned i = 0; i < NumElems; ++i)
6923 V[i] = Op.getOperand(i);
6925 // Check for elements which are consecutive loads.
6926 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6930 // Check for a build vector from mostly shuffle plus few inserting.
6931 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6935 // For SSE 4.1, use insertps to put the high elements into the low element.
6936 if (getSubtarget()->hasSSE41()) {
6938 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6939 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6941 Result = DAG.getUNDEF(VT);
6943 for (unsigned i = 1; i < NumElems; ++i) {
6944 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6945 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6946 Op.getOperand(i), DAG.getIntPtrConstant(i));
6951 // Otherwise, expand into a number of unpckl*, start by extending each of
6952 // our (non-undef) elements to the full vector width with the element in the
6953 // bottom slot of the vector (which generates no code for SSE).
6954 for (unsigned i = 0; i < NumElems; ++i) {
6955 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6956 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6958 V[i] = DAG.getUNDEF(VT);
6961 // Next, we iteratively mix elements, e.g. for v4f32:
6962 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6963 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6964 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6965 unsigned EltStride = NumElems >> 1;
6966 while (EltStride != 0) {
6967 for (unsigned i = 0; i < EltStride; ++i) {
6968 // If V[i+EltStride] is undef and this is the first round of mixing,
6969 // then it is safe to just drop this shuffle: V[i] is already in the
6970 // right place, the one element (since it's the first round) being
6971 // inserted as undef can be dropped. This isn't safe for successive
6972 // rounds because they will permute elements within both vectors.
6973 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6974 EltStride == NumElems/2)
6977 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6986 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6987 // to create 256-bit vectors from two other 128-bit ones.
6988 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6990 MVT ResVT = Op.getSimpleValueType();
6992 assert((ResVT.is256BitVector() ||
6993 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6995 SDValue V1 = Op.getOperand(0);
6996 SDValue V2 = Op.getOperand(1);
6997 unsigned NumElems = ResVT.getVectorNumElements();
6998 if(ResVT.is256BitVector())
6999 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7001 if (Op.getNumOperands() == 4) {
7002 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7003 ResVT.getVectorNumElements()/2);
7004 SDValue V3 = Op.getOperand(2);
7005 SDValue V4 = Op.getOperand(3);
7006 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7007 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7009 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7012 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7013 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7014 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7015 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7016 Op.getNumOperands() == 4)));
7018 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7019 // from two other 128-bit ones.
7021 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7022 return LowerAVXCONCAT_VECTORS(Op, DAG);
7026 //===----------------------------------------------------------------------===//
7027 // Vector shuffle lowering
7029 // This is an experimental code path for lowering vector shuffles on x86. It is
7030 // designed to handle arbitrary vector shuffles and blends, gracefully
7031 // degrading performance as necessary. It works hard to recognize idiomatic
7032 // shuffles and lower them to optimal instruction patterns without leaving
7033 // a framework that allows reasonably efficient handling of all vector shuffle
7035 //===----------------------------------------------------------------------===//
7037 /// \brief Tiny helper function to identify a no-op mask.
7039 /// This is a somewhat boring predicate function. It checks whether the mask
7040 /// array input, which is assumed to be a single-input shuffle mask of the kind
7041 /// used by the X86 shuffle instructions (not a fully general
7042 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7043 /// in-place shuffle are 'no-op's.
7044 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7045 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7046 if (Mask[i] != -1 && Mask[i] != i)
7051 /// \brief Helper function to classify a mask as a single-input mask.
7053 /// This isn't a generic single-input test because in the vector shuffle
7054 /// lowering we canonicalize single inputs to be the first input operand. This
7055 /// means we can more quickly test for a single input by only checking whether
7056 /// an input from the second operand exists. We also assume that the size of
7057 /// mask corresponds to the size of the input vectors which isn't true in the
7058 /// fully general case.
7059 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7061 if (M >= (int)Mask.size())
7066 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7067 // 2013 will allow us to use it as a non-type template parameter.
7070 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7072 /// See its documentation for details.
7073 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7074 if (Mask.size() != Args.size())
7076 for (int i = 0, e = Mask.size(); i < e; ++i) {
7077 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7078 assert(*Args[i] < (int)Args.size() * 2 &&
7079 "Argument outside the range of possible shuffle inputs!");
7080 if (Mask[i] != -1 && Mask[i] != *Args[i])
7088 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7091 /// This is a fast way to test a shuffle mask against a fixed pattern:
7093 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7095 /// It returns true if the mask is exactly as wide as the argument list, and
7096 /// each element of the mask is either -1 (signifying undef) or the value given
7097 /// in the argument.
7098 static const VariadicFunction1<
7099 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7101 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7103 /// This helper function produces an 8-bit shuffle immediate corresponding to
7104 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7105 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7108 /// NB: We rely heavily on "undef" masks preserving the input lane.
7109 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7110 SelectionDAG &DAG) {
7111 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7112 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7113 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7114 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7115 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7118 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7119 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7120 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7121 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7122 return DAG.getConstant(Imm, MVT::i8);
7125 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7127 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7128 /// support for floating point shuffles but not integer shuffles. These
7129 /// instructions will incur a domain crossing penalty on some chips though so
7130 /// it is better to avoid lowering through this for integer vectors where
7132 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7133 const X86Subtarget *Subtarget,
7134 SelectionDAG &DAG) {
7136 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7137 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7138 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7139 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7140 ArrayRef<int> Mask = SVOp->getMask();
7141 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7143 if (isSingleInputShuffleMask(Mask)) {
7144 // Straight shuffle of a single input vector. Simulate this by using the
7145 // single input as both of the "inputs" to this instruction..
7146 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7147 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7148 DAG.getConstant(SHUFPDMask, MVT::i8));
7150 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7151 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7153 // Use dedicated unpack instructions for masks that match their pattern.
7154 if (isShuffleEquivalent(Mask, 0, 2))
7155 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7156 if (isShuffleEquivalent(Mask, 1, 3))
7157 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7159 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7160 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7161 DAG.getConstant(SHUFPDMask, MVT::i8));
7164 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7166 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7167 /// the integer unit to minimize domain crossing penalties. However, for blends
7168 /// it falls back to the floating point shuffle operation with appropriate bit
7170 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7171 const X86Subtarget *Subtarget,
7172 SelectionDAG &DAG) {
7174 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7175 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7176 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7177 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7178 ArrayRef<int> Mask = SVOp->getMask();
7179 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7181 if (isSingleInputShuffleMask(Mask)) {
7182 // Straight shuffle of a single input vector. For everything from SSE2
7183 // onward this has a single fast instruction with no scary immediates.
7184 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7185 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7186 int WidenedMask[4] = {
7187 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7188 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7190 ISD::BITCAST, DL, MVT::v2i64,
7191 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7192 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7195 // Use dedicated unpack instructions for masks that match their pattern.
7196 if (isShuffleEquivalent(Mask, 0, 2))
7197 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7198 if (isShuffleEquivalent(Mask, 1, 3))
7199 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7201 // We implement this with SHUFPD which is pretty lame because it will likely
7202 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7203 // However, all the alternatives are still more cycles and newer chips don't
7204 // have this problem. It would be really nice if x86 had better shuffles here.
7205 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7206 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7207 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7208 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7211 /// \brief Lower 4-lane 32-bit floating point shuffles.
7213 /// Uses instructions exclusively from the floating point unit to minimize
7214 /// domain crossing penalties, as these are sufficient to implement all v4f32
7216 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7217 const X86Subtarget *Subtarget,
7218 SelectionDAG &DAG) {
7220 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7221 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7222 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7223 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7224 ArrayRef<int> Mask = SVOp->getMask();
7225 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7227 SDValue LowV = V1, HighV = V2;
7228 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7231 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7233 if (NumV2Elements == 0)
7234 // Straight shuffle of a single input vector. We pass the input vector to
7235 // both operands to simulate this with a SHUFPS.
7236 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7237 getV4X86ShuffleImm8ForMask(Mask, DAG));
7239 // Use dedicated unpack instructions for masks that match their pattern.
7240 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7241 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7242 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7243 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7245 if (NumV2Elements == 1) {
7247 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7249 // Compute the index adjacent to V2Index and in the same half by toggling
7251 int V2AdjIndex = V2Index ^ 1;
7253 if (Mask[V2AdjIndex] == -1) {
7254 // Handles all the cases where we have a single V2 element and an undef.
7255 // This will only ever happen in the high lanes because we commute the
7256 // vector otherwise.
7258 std::swap(LowV, HighV);
7259 NewMask[V2Index] -= 4;
7261 // Handle the case where the V2 element ends up adjacent to a V1 element.
7262 // To make this work, blend them together as the first step.
7263 int V1Index = V2AdjIndex;
7264 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7265 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7266 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7268 // Now proceed to reconstruct the final blend as we have the necessary
7269 // high or low half formed.
7276 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7277 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7279 } else if (NumV2Elements == 2) {
7280 if (Mask[0] < 4 && Mask[1] < 4) {
7281 // Handle the easy case where we have V1 in the low lanes and V2 in the
7282 // high lanes. We never see this reversed because we sort the shuffle.
7286 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7287 // trying to place elements directly, just blend them and set up the final
7288 // shuffle to place them.
7290 // The first two blend mask elements are for V1, the second two are for
7292 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7293 Mask[2] < 4 ? Mask[2] : Mask[3],
7294 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7295 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7296 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7297 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7299 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7302 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7303 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7304 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7305 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7308 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7309 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7312 /// \brief Lower 4-lane i32 vector shuffles.
7314 /// We try to handle these with integer-domain shuffles where we can, but for
7315 /// blends we use the floating point domain blend instructions.
7316 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7317 const X86Subtarget *Subtarget,
7318 SelectionDAG &DAG) {
7320 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7321 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7322 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7323 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7324 ArrayRef<int> Mask = SVOp->getMask();
7325 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7327 if (isSingleInputShuffleMask(Mask))
7328 // Straight shuffle of a single input vector. For everything from SSE2
7329 // onward this has a single fast instruction with no scary immediates.
7330 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7331 getV4X86ShuffleImm8ForMask(Mask, DAG));
7333 // Use dedicated unpack instructions for masks that match their pattern.
7334 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7335 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7336 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7337 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7339 // We implement this with SHUFPS because it can blend from two vectors.
7340 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7341 // up the inputs, bypassing domain shift penalties that we would encur if we
7342 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7344 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7345 DAG.getVectorShuffle(
7347 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7348 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7351 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7352 /// shuffle lowering, and the most complex part.
7354 /// The lowering strategy is to try to form pairs of input lanes which are
7355 /// targeted at the same half of the final vector, and then use a dword shuffle
7356 /// to place them onto the right half, and finally unpack the paired lanes into
7357 /// their final position.
7359 /// The exact breakdown of how to form these dword pairs and align them on the
7360 /// correct sides is really tricky. See the comments within the function for
7361 /// more of the details.
7362 static SDValue lowerV8I16SingleInputVectorShuffle(
7363 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7364 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7365 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7366 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7367 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7369 SmallVector<int, 4> LoInputs;
7370 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7371 [](int M) { return M >= 0; });
7372 std::sort(LoInputs.begin(), LoInputs.end());
7373 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7374 SmallVector<int, 4> HiInputs;
7375 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7376 [](int M) { return M >= 0; });
7377 std::sort(HiInputs.begin(), HiInputs.end());
7378 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7380 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7381 int NumHToL = LoInputs.size() - NumLToL;
7383 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7384 int NumHToH = HiInputs.size() - NumLToH;
7385 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7386 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7387 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7388 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7390 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7391 // such inputs we can swap two of the dwords across the half mark and end up
7392 // with <=2 inputs to each half in each half. Once there, we can fall through
7393 // to the generic code below. For example:
7395 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7396 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7398 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7399 // and an existing 2-into-2 on the other half. In this case we may have to
7400 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7401 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7402 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7403 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7404 // half than the one we target for fixing) will be fixed when we re-enter this
7405 // path. We will also combine away any sequence of PSHUFD instructions that
7406 // result into a single instruction. Here is an example of the tricky case:
7408 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7409 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7411 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7413 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7414 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7416 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7417 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7419 // The result is fine to be handled by the generic logic.
7420 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7421 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7422 int AOffset, int BOffset) {
7423 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7424 "Must call this with A having 3 or 1 inputs from the A half.");
7425 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7426 "Must call this with B having 1 or 3 inputs from the B half.");
7427 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7428 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7430 // Compute the index of dword with only one word among the three inputs in
7431 // a half by taking the sum of the half with three inputs and subtracting
7432 // the sum of the actual three inputs. The difference is the remaining
7435 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7436 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7437 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7438 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7439 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7440 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7441 int TripleNonInputIdx =
7442 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7443 TripleDWord = TripleNonInputIdx / 2;
7445 // We use xor with one to compute the adjacent DWord to whichever one the
7447 OneInputDWord = (OneInput / 2) ^ 1;
7449 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7450 // and BToA inputs. If there is also such a problem with the BToB and AToB
7451 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7452 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7453 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7454 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7455 // Compute how many inputs will be flipped by swapping these DWords. We
7457 // to balance this to ensure we don't form a 3-1 shuffle in the other
7459 int NumFlippedAToBInputs =
7460 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7461 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7462 int NumFlippedBToBInputs =
7463 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7464 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7465 if ((NumFlippedAToBInputs == 1 &&
7466 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7467 (NumFlippedBToBInputs == 1 &&
7468 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7469 // We choose whether to fix the A half or B half based on whether that
7470 // half has zero flipped inputs. At zero, we may not be able to fix it
7471 // with that half. We also bias towards fixing the B half because that
7472 // will more commonly be the high half, and we have to bias one way.
7473 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7474 ArrayRef<int> Inputs) {
7475 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7476 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7477 PinnedIdx ^ 1) != Inputs.end();
7478 // Determine whether the free index is in the flipped dword or the
7479 // unflipped dword based on where the pinned index is. We use this bit
7480 // in an xor to conditionally select the adjacent dword.
7481 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7482 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7483 FixFreeIdx) != Inputs.end();
7484 if (IsFixIdxInput == IsFixFreeIdxInput)
7486 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7487 FixFreeIdx) != Inputs.end();
7488 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7489 "We need to be changing the number of flipped inputs!");
7490 int PSHUFHalfMask[] = {0, 1, 2, 3};
7491 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7492 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7494 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7497 if (M != -1 && M == FixIdx)
7499 else if (M != -1 && M == FixFreeIdx)
7502 if (NumFlippedBToBInputs != 0) {
7504 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7505 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7507 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7509 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7510 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7515 int PSHUFDMask[] = {0, 1, 2, 3};
7516 PSHUFDMask[ADWord] = BDWord;
7517 PSHUFDMask[BDWord] = ADWord;
7518 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7519 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7520 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7521 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7523 // Adjust the mask to match the new locations of A and B.
7525 if (M != -1 && M/2 == ADWord)
7526 M = 2 * BDWord + M % 2;
7527 else if (M != -1 && M/2 == BDWord)
7528 M = 2 * ADWord + M % 2;
7530 // Recurse back into this routine to re-compute state now that this isn't
7531 // a 3 and 1 problem.
7532 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7535 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
7536 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
7537 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
7538 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
7540 // At this point there are at most two inputs to the low and high halves from
7541 // each half. That means the inputs can always be grouped into dwords and
7542 // those dwords can then be moved to the correct half with a dword shuffle.
7543 // We use at most one low and one high word shuffle to collect these paired
7544 // inputs into dwords, and finally a dword shuffle to place them.
7545 int PSHUFLMask[4] = {-1, -1, -1, -1};
7546 int PSHUFHMask[4] = {-1, -1, -1, -1};
7547 int PSHUFDMask[4] = {-1, -1, -1, -1};
7549 // First fix the masks for all the inputs that are staying in their
7550 // original halves. This will then dictate the targets of the cross-half
7552 auto fixInPlaceInputs =
7553 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7554 MutableArrayRef<int> SourceHalfMask,
7555 MutableArrayRef<int> HalfMask, int HalfOffset) {
7556 if (InPlaceInputs.empty())
7558 if (InPlaceInputs.size() == 1) {
7559 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7560 InPlaceInputs[0] - HalfOffset;
7561 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7564 if (IncomingInputs.empty()) {
7565 // Just fix all of the in place inputs.
7566 for (int Input : InPlaceInputs) {
7567 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7568 PSHUFDMask[Input / 2] = Input / 2;
7573 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7574 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7575 InPlaceInputs[0] - HalfOffset;
7576 // Put the second input next to the first so that they are packed into
7577 // a dword. We find the adjacent index by toggling the low bit.
7578 int AdjIndex = InPlaceInputs[0] ^ 1;
7579 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7580 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7581 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7583 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7584 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7586 // Now gather the cross-half inputs and place them into a free dword of
7587 // their target half.
7588 // FIXME: This operation could almost certainly be simplified dramatically to
7589 // look more like the 3-1 fixing operation.
7590 auto moveInputsToRightHalf = [&PSHUFDMask](
7591 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7592 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7593 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7595 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7596 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7598 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7600 int LowWord = Word & ~1;
7601 int HighWord = Word | 1;
7602 return isWordClobbered(SourceHalfMask, LowWord) ||
7603 isWordClobbered(SourceHalfMask, HighWord);
7606 if (IncomingInputs.empty())
7609 if (ExistingInputs.empty()) {
7610 // Map any dwords with inputs from them into the right half.
7611 for (int Input : IncomingInputs) {
7612 // If the source half mask maps over the inputs, turn those into
7613 // swaps and use the swapped lane.
7614 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7615 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7616 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7617 Input - SourceOffset;
7618 // We have to swap the uses in our half mask in one sweep.
7619 for (int &M : HalfMask)
7620 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
7622 else if (M == Input)
7623 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7625 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7626 Input - SourceOffset &&
7627 "Previous placement doesn't match!");
7629 // Note that this correctly re-maps both when we do a swap and when
7630 // we observe the other side of the swap above. We rely on that to
7631 // avoid swapping the members of the input list directly.
7632 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7635 // Map the input's dword into the correct half.
7636 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7637 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7639 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7641 "Previous placement doesn't match!");
7644 // And just directly shift any other-half mask elements to be same-half
7645 // as we will have mirrored the dword containing the element into the
7646 // same position within that half.
7647 for (int &M : HalfMask)
7648 if (M >= SourceOffset && M < SourceOffset + 4) {
7649 M = M - SourceOffset + DestOffset;
7650 assert(M >= 0 && "This should never wrap below zero!");
7655 // Ensure we have the input in a viable dword of its current half. This
7656 // is particularly tricky because the original position may be clobbered
7657 // by inputs being moved and *staying* in that half.
7658 if (IncomingInputs.size() == 1) {
7659 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7660 int InputFixed = std::find(std::begin(SourceHalfMask),
7661 std::end(SourceHalfMask), -1) -
7662 std::begin(SourceHalfMask) + SourceOffset;
7663 SourceHalfMask[InputFixed - SourceOffset] =
7664 IncomingInputs[0] - SourceOffset;
7665 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7667 IncomingInputs[0] = InputFixed;
7669 } else if (IncomingInputs.size() == 2) {
7670 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7671 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7672 // We have two non-adjacent or clobbered inputs we need to extract from
7673 // the source half. To do this, we need to map them into some adjacent
7674 // dword slot in the source mask.
7675 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
7676 IncomingInputs[1] - SourceOffset};
7678 // If there is a free slot in the source half mask adjacent to one of
7679 // the inputs, place the other input in it. We use (Index XOR 1) to
7680 // compute an adjacent index.
7681 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
7682 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
7683 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
7684 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7685 InputsFixed[1] = InputsFixed[0] ^ 1;
7686 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
7687 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
7688 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
7689 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
7690 InputsFixed[0] = InputsFixed[1] ^ 1;
7691 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
7692 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
7693 // The two inputs are in the same DWord but it is clobbered and the
7694 // adjacent DWord isn't used at all. Move both inputs to the free
7696 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
7697 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
7698 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
7699 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
7701 // The only way we hit this point is if there is no clobbering
7702 // (because there are no off-half inputs to this half) and there is no
7703 // free slot adjacent to one of the inputs. In this case, we have to
7704 // swap an input with a non-input.
7705 for (int i = 0; i < 4; ++i)
7706 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
7707 "We can't handle any clobbers here!");
7708 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
7709 "Cannot have adjacent inputs here!");
7711 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7712 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
7714 // We also have to update the final source mask in this case because
7715 // it may need to undo the above swap.
7716 for (int &M : FinalSourceHalfMask)
7717 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
7718 M = InputsFixed[1] + SourceOffset;
7719 else if (M == InputsFixed[1] + SourceOffset)
7720 M = (InputsFixed[0] ^ 1) + SourceOffset;
7722 InputsFixed[1] = InputsFixed[0] ^ 1;
7725 // Point everything at the fixed inputs.
7726 for (int &M : HalfMask)
7727 if (M == IncomingInputs[0])
7728 M = InputsFixed[0] + SourceOffset;
7729 else if (M == IncomingInputs[1])
7730 M = InputsFixed[1] + SourceOffset;
7732 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
7733 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
7736 llvm_unreachable("Unhandled input size!");
7739 // Now hoist the DWord down to the right half.
7740 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7741 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7742 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7743 for (int &M : HalfMask)
7744 for (int Input : IncomingInputs)
7746 M = FreeDWord * 2 + Input % 2;
7748 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
7749 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7750 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
7751 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7753 // Now enact all the shuffles we've computed to move the inputs into their
7755 if (!isNoopShuffleMask(PSHUFLMask))
7756 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7757 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7758 if (!isNoopShuffleMask(PSHUFHMask))
7759 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7760 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7761 if (!isNoopShuffleMask(PSHUFDMask))
7762 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7763 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7764 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7765 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7767 // At this point, each half should contain all its inputs, and we can then
7768 // just shuffle them into their final position.
7769 assert(std::count_if(LoMask.begin(), LoMask.end(),
7770 [](int M) { return M >= 4; }) == 0 &&
7771 "Failed to lift all the high half inputs to the low mask!");
7772 assert(std::count_if(HiMask.begin(), HiMask.end(),
7773 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7774 "Failed to lift all the low half inputs to the high mask!");
7776 // Do a half shuffle for the low mask.
7777 if (!isNoopShuffleMask(LoMask))
7778 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7779 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7781 // Do a half shuffle with the high mask after shifting its values down.
7782 for (int &M : HiMask)
7785 if (!isNoopShuffleMask(HiMask))
7786 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7787 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7792 /// \brief Detect whether the mask pattern should be lowered through
7795 /// This essentially tests whether viewing the mask as an interleaving of two
7796 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7797 /// lowering it through interleaving is a significantly better strategy.
7798 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7799 int NumEvenInputs[2] = {0, 0};
7800 int NumOddInputs[2] = {0, 0};
7801 int NumLoInputs[2] = {0, 0};
7802 int NumHiInputs[2] = {0, 0};
7803 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7807 int InputIdx = Mask[i] >= Size;
7810 ++NumLoInputs[InputIdx];
7812 ++NumHiInputs[InputIdx];
7815 ++NumEvenInputs[InputIdx];
7817 ++NumOddInputs[InputIdx];
7820 // The minimum number of cross-input results for both the interleaved and
7821 // split cases. If interleaving results in fewer cross-input results, return
7823 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7824 NumEvenInputs[0] + NumOddInputs[1]);
7825 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7826 NumLoInputs[0] + NumHiInputs[1]);
7827 return InterleavedCrosses < SplitCrosses;
7830 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7832 /// This strategy only works when the inputs from each vector fit into a single
7833 /// half of that vector, and generally there are not so many inputs as to leave
7834 /// the in-place shuffles required highly constrained (and thus expensive). It
7835 /// shifts all the inputs into a single side of both input vectors and then
7836 /// uses an unpack to interleave these inputs in a single vector. At that
7837 /// point, we will fall back on the generic single input shuffle lowering.
7838 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7840 MutableArrayRef<int> Mask,
7841 const X86Subtarget *Subtarget,
7842 SelectionDAG &DAG) {
7843 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7844 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7845 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7846 for (int i = 0; i < 8; ++i)
7847 if (Mask[i] >= 0 && Mask[i] < 4)
7848 LoV1Inputs.push_back(i);
7849 else if (Mask[i] >= 4 && Mask[i] < 8)
7850 HiV1Inputs.push_back(i);
7851 else if (Mask[i] >= 8 && Mask[i] < 12)
7852 LoV2Inputs.push_back(i);
7853 else if (Mask[i] >= 12)
7854 HiV2Inputs.push_back(i);
7856 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7857 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7860 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7861 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7862 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7864 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7865 HiV1Inputs.size() + HiV2Inputs.size();
7867 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7868 ArrayRef<int> HiInputs, bool MoveToLo,
7870 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7871 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7872 if (BadInputs.empty())
7875 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7876 int MoveOffset = MoveToLo ? 0 : 4;
7878 if (GoodInputs.empty()) {
7879 for (int BadInput : BadInputs) {
7880 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7881 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7884 if (GoodInputs.size() == 2) {
7885 // If the low inputs are spread across two dwords, pack them into
7887 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
7888 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
7889 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
7890 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
7892 // Otherwise pin the good inputs.
7893 for (int GoodInput : GoodInputs)
7894 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7897 if (BadInputs.size() == 2) {
7898 // If we have two bad inputs then there may be either one or two good
7899 // inputs fixed in place. Find a fixed input, and then find the *other*
7900 // two adjacent indices by using modular arithmetic.
7902 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
7903 [](int M) { return M >= 0; }) -
7904 std::begin(MoveMask);
7906 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
7907 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7908 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7909 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7910 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
7911 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7912 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
7914 assert(BadInputs.size() == 1 && "All sizes handled");
7915 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
7916 std::end(MoveMask), -1) -
7917 std::begin(MoveMask);
7918 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7919 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7923 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7926 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7928 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7931 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7932 // cross-half traffic in the final shuffle.
7934 // Munge the mask to be a single-input mask after the unpack merges the
7938 M = 2 * (M % 4) + (M / 8);
7940 return DAG.getVectorShuffle(
7941 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7942 DL, MVT::v8i16, V1, V2),
7943 DAG.getUNDEF(MVT::v8i16), Mask);
7946 /// \brief Generic lowering of 8-lane i16 shuffles.
7948 /// This handles both single-input shuffles and combined shuffle/blends with
7949 /// two inputs. The single input shuffles are immediately delegated to
7950 /// a dedicated lowering routine.
7952 /// The blends are lowered in one of three fundamental ways. If there are few
7953 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7954 /// of the input is significantly cheaper when lowered as an interleaving of
7955 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7956 /// halves of the inputs separately (making them have relatively few inputs)
7957 /// and then concatenate them.
7958 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7959 const X86Subtarget *Subtarget,
7960 SelectionDAG &DAG) {
7962 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7963 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7964 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7965 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7966 ArrayRef<int> OrigMask = SVOp->getMask();
7967 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7968 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7969 MutableArrayRef<int> Mask(MaskStorage);
7971 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7973 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7974 auto isV2 = [](int M) { return M >= 8; };
7976 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7977 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7979 if (NumV2Inputs == 0)
7980 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7982 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7983 "to be V1-input shuffles.");
7985 if (NumV1Inputs + NumV2Inputs <= 4)
7986 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7988 // Check whether an interleaving lowering is likely to be more efficient.
7989 // This isn't perfect but it is a strong heuristic that tends to work well on
7990 // the kinds of shuffles that show up in practice.
7992 // FIXME: Handle 1x, 2x, and 4x interleaving.
7993 if (shouldLowerAsInterleaving(Mask)) {
7994 // FIXME: Figure out whether we should pack these into the low or high
7997 int EMask[8], OMask[8];
7998 for (int i = 0; i < 4; ++i) {
7999 EMask[i] = Mask[2*i];
8000 OMask[i] = Mask[2*i + 1];
8005 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8006 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8008 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8011 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8012 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8014 for (int i = 0; i < 4; ++i) {
8015 LoBlendMask[i] = Mask[i];
8016 HiBlendMask[i] = Mask[i + 4];
8019 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8020 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8021 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8022 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8024 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8025 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8028 /// \brief Check whether a compaction lowering can be done by dropping even
8029 /// elements and compute how many times even elements must be dropped.
8031 /// This handles shuffles which take every Nth element where N is a power of
8032 /// two. Example shuffle masks:
8034 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8035 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8036 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8037 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8038 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8039 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8041 /// Any of these lanes can of course be undef.
8043 /// This routine only supports N <= 3.
8044 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8047 /// \returns N above, or the number of times even elements must be dropped if
8048 /// there is such a number. Otherwise returns zero.
8049 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8050 // Figure out whether we're looping over two inputs or just one.
8051 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8053 // The modulus for the shuffle vector entries is based on whether this is
8054 // a single input or not.
8055 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8056 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8057 "We should only be called with masks with a power-of-2 size!");
8059 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8061 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8062 // and 2^3 simultaneously. This is because we may have ambiguity with
8063 // partially undef inputs.
8064 bool ViableForN[3] = {true, true, true};
8066 for (int i = 0, e = Mask.size(); i < e; ++i) {
8067 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8072 bool IsAnyViable = false;
8073 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8074 if (ViableForN[j]) {
8077 // The shuffle mask must be equal to (i * 2^N) % M.
8078 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8081 ViableForN[j] = false;
8083 // Early exit if we exhaust the possible powers of two.
8088 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8092 // Return 0 as there is no viable power of two.
8096 /// \brief Generic lowering of v16i8 shuffles.
8098 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8099 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8100 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8101 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8103 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8104 const X86Subtarget *Subtarget,
8105 SelectionDAG &DAG) {
8107 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8108 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8109 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8110 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8111 ArrayRef<int> OrigMask = SVOp->getMask();
8112 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8113 int MaskStorage[16] = {
8114 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8115 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8116 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8117 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8118 MutableArrayRef<int> Mask(MaskStorage);
8119 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8120 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8122 // For single-input shuffles, there are some nicer lowering tricks we can use.
8123 if (isSingleInputShuffleMask(Mask)) {
8124 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8125 // Notably, this handles splat and partial-splat shuffles more efficiently.
8126 // However, it only makes sense if the pre-duplication shuffle simplifies
8127 // things significantly. Currently, this means we need to be able to
8128 // express the pre-duplication shuffle as an i16 shuffle.
8130 // FIXME: We should check for other patterns which can be widened into an
8131 // i16 shuffle as well.
8132 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8133 for (int i = 0; i < 16; i += 2) {
8134 if (Mask[i] != Mask[i + 1])
8139 auto tryToWidenViaDuplication = [&]() -> SDValue {
8140 if (!canWidenViaDuplication(Mask))
8142 SmallVector<int, 4> LoInputs;
8143 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8144 [](int M) { return M >= 0 && M < 8; });
8145 std::sort(LoInputs.begin(), LoInputs.end());
8146 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8148 SmallVector<int, 4> HiInputs;
8149 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8150 [](int M) { return M >= 8; });
8151 std::sort(HiInputs.begin(), HiInputs.end());
8152 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8155 bool TargetLo = LoInputs.size() >= HiInputs.size();
8156 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8157 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8159 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8160 SmallDenseMap<int, int, 8> LaneMap;
8161 for (int I : InPlaceInputs) {
8162 PreDupI16Shuffle[I/2] = I/2;
8165 int j = TargetLo ? 0 : 4, je = j + 4;
8166 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8167 // Check if j is already a shuffle of this input. This happens when
8168 // there are two adjacent bytes after we move the low one.
8169 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8170 // If we haven't yet mapped the input, search for a slot into which
8172 while (j < je && PreDupI16Shuffle[j] != -1)
8176 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8179 // Map this input with the i16 shuffle.
8180 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8183 // Update the lane map based on the mapping we ended up with.
8184 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8187 ISD::BITCAST, DL, MVT::v16i8,
8188 DAG.getVectorShuffle(MVT::v8i16, DL,
8189 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8190 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8192 // Unpack the bytes to form the i16s that will be shuffled into place.
8193 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8194 MVT::v16i8, V1, V1);
8196 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8197 for (int i = 0; i < 16; i += 2) {
8199 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8200 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8203 ISD::BITCAST, DL, MVT::v16i8,
8204 DAG.getVectorShuffle(MVT::v8i16, DL,
8205 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8206 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8208 if (SDValue V = tryToWidenViaDuplication())
8212 // Check whether an interleaving lowering is likely to be more efficient.
8213 // This isn't perfect but it is a strong heuristic that tends to work well on
8214 // the kinds of shuffles that show up in practice.
8216 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8217 if (shouldLowerAsInterleaving(Mask)) {
8218 // FIXME: Figure out whether we should pack these into the low or high
8221 int EMask[16], OMask[16];
8222 for (int i = 0; i < 8; ++i) {
8223 EMask[i] = Mask[2*i];
8224 OMask[i] = Mask[2*i + 1];
8229 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8230 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8232 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8235 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8236 // with PSHUFB. It is important to do this before we attempt to generate any
8237 // blends but after all of the single-input lowerings. If the single input
8238 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8239 // want to preserve that and we can DAG combine any longer sequences into
8240 // a PSHUFB in the end. But once we start blending from multiple inputs,
8241 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8242 // and there are *very* few patterns that would actually be faster than the
8243 // PSHUFB approach because of its ability to zero lanes.
8245 // FIXME: The only exceptions to the above are blends which are exact
8246 // interleavings with direct instructions supporting them. We currently don't
8247 // handle those well here.
8248 if (Subtarget->hasSSSE3()) {
8251 for (int i = 0; i < 16; ++i)
8252 if (Mask[i] == -1) {
8253 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8255 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8257 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8259 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8260 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8261 if (isSingleInputShuffleMask(Mask))
8262 return V1; // Single inputs are easy.
8264 // Otherwise, blend the two.
8265 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8266 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8267 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8270 // Check whether a compaction lowering can be done. This handles shuffles
8271 // which take every Nth element for some even N. See the helper function for
8274 // We special case these as they can be particularly efficiently handled with
8275 // the PACKUSB instruction on x86 and they show up in common patterns of
8276 // rearranging bytes to truncate wide elements.
8277 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8278 // NumEvenDrops is the power of two stride of the elements. Another way of
8279 // thinking about it is that we need to drop the even elements this many
8280 // times to get the original input.
8281 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8283 // First we need to zero all the dropped bytes.
8284 assert(NumEvenDrops <= 3 &&
8285 "No support for dropping even elements more than 3 times.");
8286 // We use the mask type to pick which bytes are preserved based on how many
8287 // elements are dropped.
8288 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8289 SDValue ByteClearMask =
8290 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8291 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8292 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8294 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8296 // Now pack things back together.
8297 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8298 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8299 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8300 for (int i = 1; i < NumEvenDrops; ++i) {
8301 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8302 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8308 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8309 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8310 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8311 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8313 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8314 MutableArrayRef<int> V1HalfBlendMask,
8315 MutableArrayRef<int> V2HalfBlendMask) {
8316 for (int i = 0; i < 8; ++i)
8317 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8318 V1HalfBlendMask[i] = HalfMask[i];
8320 } else if (HalfMask[i] >= 16) {
8321 V2HalfBlendMask[i] = HalfMask[i] - 16;
8322 HalfMask[i] = i + 8;
8325 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8326 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8328 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8330 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8331 MutableArrayRef<int> HiBlendMask) {
8333 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8334 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8336 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8337 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8338 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8339 [](int M) { return M >= 0 && M % 2 == 1; })) {
8340 // Use a mask to drop the high bytes.
8341 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8342 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8343 DAG.getConstant(0x00FF, MVT::v8i16));
8345 // This will be a single vector shuffle instead of a blend so nuke V2.
8346 V2 = DAG.getUNDEF(MVT::v8i16);
8348 // Squash the masks to point directly into V1.
8349 for (int &M : LoBlendMask)
8352 for (int &M : HiBlendMask)
8356 // Otherwise just unpack the low half of V into V1 and the high half into
8357 // V2 so that we can blend them as i16s.
8358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8359 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8361 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8364 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8365 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8366 return std::make_pair(BlendedLo, BlendedHi);
8368 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8369 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8370 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8372 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8373 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8375 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8378 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8380 /// This routine breaks down the specific type of 128-bit shuffle and
8381 /// dispatches to the lowering routines accordingly.
8382 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8383 MVT VT, const X86Subtarget *Subtarget,
8384 SelectionDAG &DAG) {
8385 switch (VT.SimpleTy) {
8387 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8389 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8391 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8393 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8395 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8397 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8400 llvm_unreachable("Unimplemented!");
8404 static bool isHalfCrossingShuffleMask(ArrayRef<int> Mask) {
8405 int Size = Mask.size();
8406 for (int M : Mask.slice(0, Size / 2))
8407 if (M >= 0 && (M % Size) >= Size / 2)
8409 for (int M : Mask.slice(Size / 2, Size / 2))
8410 if (M >= 0 && (M % Size) < Size / 2)
8415 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
8418 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
8419 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
8420 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
8421 /// we encode the logic here for specific shuffle lowering routines to bail to
8422 /// when they exhaust the features avaible to more directly handle the shuffle.
8423 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
8425 const X86Subtarget *Subtarget,
8426 SelectionDAG &DAG) {
8428 MVT VT = Op.getSimpleValueType();
8429 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
8430 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8431 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8432 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8433 ArrayRef<int> Mask = SVOp->getMask();
8435 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
8436 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
8438 int NumElements = VT.getVectorNumElements();
8439 int SplitNumElements = NumElements / 2;
8440 MVT ScalarVT = VT.getScalarType();
8441 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8443 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8444 DAG.getIntPtrConstant(0));
8445 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8446 DAG.getIntPtrConstant(SplitNumElements));
8447 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8448 DAG.getIntPtrConstant(0));
8449 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8450 DAG.getIntPtrConstant(SplitNumElements));
8452 // Now create two 4-way blends of these half-width vectors.
8453 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8454 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
8455 for (int i = 0; i < SplitNumElements; ++i) {
8456 int M = HalfMask[i];
8457 if (M >= NumElements) {
8458 V2BlendMask.push_back(M - NumElements);
8459 V1BlendMask.push_back(-1);
8460 BlendMask.push_back(SplitNumElements + i);
8461 } else if (M >= 0) {
8462 V2BlendMask.push_back(-1);
8463 V1BlendMask.push_back(M);
8464 BlendMask.push_back(i);
8466 V2BlendMask.push_back(-1);
8467 V1BlendMask.push_back(-1);
8468 BlendMask.push_back(-1);
8471 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8472 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8473 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
8475 SDValue Lo = HalfBlend(LoMask);
8476 SDValue Hi = HalfBlend(HiMask);
8477 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
8480 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
8482 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
8483 /// isn't available.
8484 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8485 const X86Subtarget *Subtarget,
8486 SelectionDAG &DAG) {
8488 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8489 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8490 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8491 ArrayRef<int> Mask = SVOp->getMask();
8492 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8494 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8495 // shuffles aren't a problem and FP and int have the same patterns.
8497 // FIXME: We can handle these more cleverly than splitting for v4f64.
8498 if (isHalfCrossingShuffleMask(Mask))
8499 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8501 if (isSingleInputShuffleMask(Mask)) {
8502 // Non-half-crossing single input shuffles can be lowerid with an
8503 // interleaved permutation.
8504 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
8505 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
8506 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
8507 DAG.getConstant(VPERMILPMask, MVT::i8));
8510 // X86 has dedicated unpack instructions that can handle specific blend
8511 // operations: UNPCKH and UNPCKL.
8512 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
8513 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
8514 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
8515 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
8516 // FIXME: It would be nice to find a way to get canonicalization to commute
8518 if (isShuffleEquivalent(Mask, 4, 0, 6, 2))
8519 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
8520 if (isShuffleEquivalent(Mask, 5, 1, 7, 3))
8521 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
8523 // Check if the blend happens to exactly fit that of SHUFPD.
8524 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
8525 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
8526 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
8527 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
8528 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
8529 DAG.getConstant(SHUFPDMask, MVT::i8));
8531 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
8532 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
8533 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
8534 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
8535 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
8536 DAG.getConstant(SHUFPDMask, MVT::i8));
8539 // Shuffle the input elements into the desired positions in V1 and V2 and
8540 // blend them together.
8541 int V1Mask[] = {-1, -1, -1, -1};
8542 int V2Mask[] = {-1, -1, -1, -1};
8543 for (int i = 0; i < 4; ++i)
8544 if (Mask[i] >= 0 && Mask[i] < 4)
8545 V1Mask[i] = Mask[i];
8546 else if (Mask[i] >= 4)
8547 V2Mask[i] = Mask[i] - 4;
8549 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
8550 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
8552 unsigned BlendMask = 0;
8553 for (int i = 0; i < 4; ++i)
8555 BlendMask |= 1 << i;
8557 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
8558 DAG.getConstant(BlendMask, MVT::i8));
8561 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
8563 /// Largely delegates to common code when we have AVX2 and to the floating-point
8564 /// code when we only have AVX.
8565 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8566 const X86Subtarget *Subtarget,
8567 SelectionDAG &DAG) {
8569 assert(Op.getSimpleValueType() == MVT::v4i64 && "Bad shuffle type!");
8570 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8571 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8573 ArrayRef<int> Mask = SVOp->getMask();
8574 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8576 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8577 // shuffles aren't a problem and FP and int have the same patterns.
8579 if (isHalfCrossingShuffleMask(Mask))
8580 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8582 // AVX1 doesn't provide any facilities for v4i64 shuffles, bitcast and
8583 // delegate to floating point code.
8584 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
8585 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
8586 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
8587 lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG));
8590 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
8592 /// This routine either breaks down the specific type of a 256-bit x86 vector
8593 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
8594 /// together based on the available instructions.
8595 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8596 MVT VT, const X86Subtarget *Subtarget,
8597 SelectionDAG &DAG) {
8598 switch (VT.SimpleTy) {
8600 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8602 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8607 // Fall back to the basic pattern of extracting the high half and forming
8609 // FIXME: Add targeted lowering for each type that can document rationale
8610 // for delegating to this when necessary.
8611 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8614 llvm_unreachable("Not a valid 256-bit x86 vector type!");
8618 /// \brief Tiny helper function to test whether a shuffle mask could be
8619 /// simplified by widening the elements being shuffled.
8620 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
8621 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8622 if (Mask[i] % 2 != 0 || Mask[i] + 1 != Mask[i+1])
8628 /// \brief Top-level lowering for x86 vector shuffles.
8630 /// This handles decomposition, canonicalization, and lowering of all x86
8631 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8632 /// above in helper routines. The canonicalization attempts to widen shuffles
8633 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8634 /// s.t. only one of the two inputs needs to be tested, etc.
8635 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8636 SelectionDAG &DAG) {
8637 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8638 ArrayRef<int> Mask = SVOp->getMask();
8639 SDValue V1 = Op.getOperand(0);
8640 SDValue V2 = Op.getOperand(1);
8641 MVT VT = Op.getSimpleValueType();
8642 int NumElements = VT.getVectorNumElements();
8645 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8647 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8648 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8649 if (V1IsUndef && V2IsUndef)
8650 return DAG.getUNDEF(VT);
8652 // When we create a shuffle node we put the UNDEF node to second operand,
8653 // but in some cases the first operand may be transformed to UNDEF.
8654 // In this case we should just commute the node.
8656 return DAG.getCommutedVectorShuffle(*SVOp);
8658 // Check for non-undef masks pointing at an undef vector and make the masks
8659 // undef as well. This makes it easier to match the shuffle based solely on
8663 if (M >= NumElements) {
8664 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8665 for (int &M : NewMask)
8666 if (M >= NumElements)
8668 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8671 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8672 // lanes but wider integers. We cap this to not form integers larger than i64
8673 // but it might be interesting to form i128 integers to handle flipping the
8674 // low and high halves of AVX 256-bit vectors.
8675 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8676 canWidenShuffleElements(Mask)) {
8677 SmallVector<int, 8> NewMask;
8678 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8679 NewMask.push_back(Mask[i] / 2);
8681 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8682 VT.getVectorNumElements() / 2);
8683 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8684 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8685 return DAG.getNode(ISD::BITCAST, dl, VT,
8686 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8689 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8690 for (int M : SVOp->getMask())
8693 else if (M < NumElements)
8698 // Commute the shuffle as needed such that more elements come from V1 than
8699 // V2. This allows us to match the shuffle pattern strictly on how many
8700 // elements come from V1 without handling the symmetric cases.
8701 if (NumV2Elements > NumV1Elements)
8702 return DAG.getCommutedVectorShuffle(*SVOp);
8704 // When the number of V1 and V2 elements are the same, try to minimize the
8705 // number of uses of V2 in the low half of the vector.
8706 if (NumV1Elements == NumV2Elements) {
8707 int LowV1Elements = 0, LowV2Elements = 0;
8708 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8709 if (M >= NumElements)
8713 if (LowV2Elements > LowV1Elements)
8714 return DAG.getCommutedVectorShuffle(*SVOp);
8717 // For each vector width, delegate to a specialized lowering routine.
8718 if (VT.getSizeInBits() == 128)
8719 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8721 if (VT.getSizeInBits() == 256)
8722 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8724 llvm_unreachable("Unimplemented!");
8728 //===----------------------------------------------------------------------===//
8729 // Legacy vector shuffle lowering
8731 // This code is the legacy code handling vector shuffles until the above
8732 // replaces its functionality and performance.
8733 //===----------------------------------------------------------------------===//
8735 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8736 bool hasInt256, unsigned *MaskOut = nullptr) {
8737 MVT EltVT = VT.getVectorElementType();
8739 // There is no blend with immediate in AVX-512.
8740 if (VT.is512BitVector())
8743 if (!hasSSE41 || EltVT == MVT::i8)
8745 if (!hasInt256 && VT == MVT::v16i16)
8748 unsigned MaskValue = 0;
8749 unsigned NumElems = VT.getVectorNumElements();
8750 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8751 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8752 unsigned NumElemsInLane = NumElems / NumLanes;
8754 // Blend for v16i16 should be symetric for the both lanes.
8755 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8757 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8758 int EltIdx = MaskVals[i];
8760 if ((EltIdx < 0 || EltIdx == (int)i) &&
8761 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8764 if (((unsigned)EltIdx == (i + NumElems)) &&
8765 (SndLaneEltIdx < 0 ||
8766 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8767 MaskValue |= (1 << i);
8773 *MaskOut = MaskValue;
8777 // Try to lower a shuffle node into a simple blend instruction.
8778 // This function assumes isBlendMask returns true for this
8779 // SuffleVectorSDNode
8780 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8782 const X86Subtarget *Subtarget,
8783 SelectionDAG &DAG) {
8784 MVT VT = SVOp->getSimpleValueType(0);
8785 MVT EltVT = VT.getVectorElementType();
8786 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8787 Subtarget->hasInt256() && "Trying to lower a "
8788 "VECTOR_SHUFFLE to a Blend but "
8789 "with the wrong mask"));
8790 SDValue V1 = SVOp->getOperand(0);
8791 SDValue V2 = SVOp->getOperand(1);
8793 unsigned NumElems = VT.getVectorNumElements();
8795 // Convert i32 vectors to floating point if it is not AVX2.
8796 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8798 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8799 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8801 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8802 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8805 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8806 DAG.getConstant(MaskValue, MVT::i32));
8807 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8810 /// In vector type \p VT, return true if the element at index \p InputIdx
8811 /// falls on a different 128-bit lane than \p OutputIdx.
8812 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8813 unsigned OutputIdx) {
8814 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8815 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8818 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8819 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8820 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8821 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8823 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8824 SelectionDAG &DAG) {
8825 MVT VT = V1.getSimpleValueType();
8826 assert(VT.is128BitVector() || VT.is256BitVector());
8828 MVT EltVT = VT.getVectorElementType();
8829 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8830 unsigned NumElts = VT.getVectorNumElements();
8832 SmallVector<SDValue, 32> PshufbMask;
8833 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8834 int InputIdx = MaskVals[OutputIdx];
8835 unsigned InputByteIdx;
8837 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8838 InputByteIdx = 0x80;
8840 // Cross lane is not allowed.
8841 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8843 InputByteIdx = InputIdx * EltSizeInBytes;
8844 // Index is an byte offset within the 128-bit lane.
8845 InputByteIdx &= 0xf;
8848 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8849 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8850 if (InputByteIdx != 0x80)
8855 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8857 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8858 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8859 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8862 // v8i16 shuffles - Prefer shuffles in the following order:
8863 // 1. [all] pshuflw, pshufhw, optional move
8864 // 2. [ssse3] 1 x pshufb
8865 // 3. [ssse3] 2 x pshufb + 1 x por
8866 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8868 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8869 SelectionDAG &DAG) {
8870 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8871 SDValue V1 = SVOp->getOperand(0);
8872 SDValue V2 = SVOp->getOperand(1);
8874 SmallVector<int, 8> MaskVals;
8876 // Determine if more than 1 of the words in each of the low and high quadwords
8877 // of the result come from the same quadword of one of the two inputs. Undef
8878 // mask values count as coming from any quadword, for better codegen.
8880 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8881 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8882 unsigned LoQuad[] = { 0, 0, 0, 0 };
8883 unsigned HiQuad[] = { 0, 0, 0, 0 };
8884 // Indices of quads used.
8885 std::bitset<4> InputQuads;
8886 for (unsigned i = 0; i < 8; ++i) {
8887 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8888 int EltIdx = SVOp->getMaskElt(i);
8889 MaskVals.push_back(EltIdx);
8898 InputQuads.set(EltIdx / 4);
8901 int BestLoQuad = -1;
8902 unsigned MaxQuad = 1;
8903 for (unsigned i = 0; i < 4; ++i) {
8904 if (LoQuad[i] > MaxQuad) {
8906 MaxQuad = LoQuad[i];
8910 int BestHiQuad = -1;
8912 for (unsigned i = 0; i < 4; ++i) {
8913 if (HiQuad[i] > MaxQuad) {
8915 MaxQuad = HiQuad[i];
8919 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8920 // of the two input vectors, shuffle them into one input vector so only a
8921 // single pshufb instruction is necessary. If there are more than 2 input
8922 // quads, disable the next transformation since it does not help SSSE3.
8923 bool V1Used = InputQuads[0] || InputQuads[1];
8924 bool V2Used = InputQuads[2] || InputQuads[3];
8925 if (Subtarget->hasSSSE3()) {
8926 if (InputQuads.count() == 2 && V1Used && V2Used) {
8927 BestLoQuad = InputQuads[0] ? 0 : 1;
8928 BestHiQuad = InputQuads[2] ? 2 : 3;
8930 if (InputQuads.count() > 2) {
8936 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8937 // the shuffle mask. If a quad is scored as -1, that means that it contains
8938 // words from all 4 input quadwords.
8940 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8942 BestLoQuad < 0 ? 0 : BestLoQuad,
8943 BestHiQuad < 0 ? 1 : BestHiQuad
8945 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8946 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8947 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8948 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8950 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8951 // source words for the shuffle, to aid later transformations.
8952 bool AllWordsInNewV = true;
8953 bool InOrder[2] = { true, true };
8954 for (unsigned i = 0; i != 8; ++i) {
8955 int idx = MaskVals[i];
8957 InOrder[i/4] = false;
8958 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8960 AllWordsInNewV = false;
8964 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8965 if (AllWordsInNewV) {
8966 for (int i = 0; i != 8; ++i) {
8967 int idx = MaskVals[i];
8970 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8971 if ((idx != i) && idx < 4)
8973 if ((idx != i) && idx > 3)
8982 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8983 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8984 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8985 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8986 unsigned TargetMask = 0;
8987 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8988 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8989 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8990 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8991 getShufflePSHUFLWImmediate(SVOp);
8992 V1 = NewV.getOperand(0);
8993 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8997 // Promote splats to a larger type which usually leads to more efficient code.
8998 // FIXME: Is this true if pshufb is available?
8999 if (SVOp->isSplat())
9000 return PromoteSplat(SVOp, DAG);
9002 // If we have SSSE3, and all words of the result are from 1 input vector,
9003 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9004 // is present, fall back to case 4.
9005 if (Subtarget->hasSSSE3()) {
9006 SmallVector<SDValue,16> pshufbMask;
9008 // If we have elements from both input vectors, set the high bit of the
9009 // shuffle mask element to zero out elements that come from V2 in the V1
9010 // mask, and elements that come from V1 in the V2 mask, so that the two
9011 // results can be OR'd together.
9012 bool TwoInputs = V1Used && V2Used;
9013 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9015 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9017 // Calculate the shuffle mask for the second input, shuffle it, and
9018 // OR it with the first shuffled input.
9019 CommuteVectorShuffleMask(MaskVals, 8);
9020 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9021 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9022 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9025 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9026 // and update MaskVals with new element order.
9027 std::bitset<8> InOrder;
9028 if (BestLoQuad >= 0) {
9029 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9030 for (int i = 0; i != 4; ++i) {
9031 int idx = MaskVals[i];
9034 } else if ((idx / 4) == BestLoQuad) {
9039 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9042 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9044 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9046 getShufflePSHUFLWImmediate(SVOp), DAG);
9050 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9051 // and update MaskVals with the new element order.
9052 if (BestHiQuad >= 0) {
9053 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9054 for (unsigned i = 4; i != 8; ++i) {
9055 int idx = MaskVals[i];
9058 } else if ((idx / 4) == BestHiQuad) {
9059 MaskV[i] = (idx & 3) + 4;
9063 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9066 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9067 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9068 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
9070 getShufflePSHUFHWImmediate(SVOp), DAG);
9074 // In case BestHi & BestLo were both -1, which means each quadword has a word
9075 // from each of the four input quadwords, calculate the InOrder bitvector now
9076 // before falling through to the insert/extract cleanup.
9077 if (BestLoQuad == -1 && BestHiQuad == -1) {
9079 for (int i = 0; i != 8; ++i)
9080 if (MaskVals[i] < 0 || MaskVals[i] == i)
9084 // The other elements are put in the right place using pextrw and pinsrw.
9085 for (unsigned i = 0; i != 8; ++i) {
9088 int EltIdx = MaskVals[i];
9091 SDValue ExtOp = (EltIdx < 8) ?
9092 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
9093 DAG.getIntPtrConstant(EltIdx)) :
9094 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
9095 DAG.getIntPtrConstant(EltIdx - 8));
9096 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
9097 DAG.getIntPtrConstant(i));
9102 /// \brief v16i16 shuffles
9104 /// FIXME: We only support generation of a single pshufb currently. We can
9105 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
9106 /// well (e.g 2 x pshufb + 1 x por).
9108 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
9109 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9110 SDValue V1 = SVOp->getOperand(0);
9111 SDValue V2 = SVOp->getOperand(1);
9114 if (V2.getOpcode() != ISD::UNDEF)
9117 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9118 return getPSHUFB(MaskVals, V1, dl, DAG);
9121 // v16i8 shuffles - Prefer shuffles in the following order:
9122 // 1. [ssse3] 1 x pshufb
9123 // 2. [ssse3] 2 x pshufb + 1 x por
9124 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
9125 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
9126 const X86Subtarget* Subtarget,
9127 SelectionDAG &DAG) {
9128 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9129 SDValue V1 = SVOp->getOperand(0);
9130 SDValue V2 = SVOp->getOperand(1);
9132 ArrayRef<int> MaskVals = SVOp->getMask();
9134 // Promote splats to a larger type which usually leads to more efficient code.
9135 // FIXME: Is this true if pshufb is available?
9136 if (SVOp->isSplat())
9137 return PromoteSplat(SVOp, DAG);
9139 // If we have SSSE3, case 1 is generated when all result bytes come from
9140 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
9141 // present, fall back to case 3.
9143 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
9144 if (Subtarget->hasSSSE3()) {
9145 SmallVector<SDValue,16> pshufbMask;
9147 // If all result elements are from one input vector, then only translate
9148 // undef mask values to 0x80 (zero out result) in the pshufb mask.
9150 // Otherwise, we have elements from both input vectors, and must zero out
9151 // elements that come from V2 in the first mask, and V1 in the second mask
9152 // so that we can OR them together.
9153 for (unsigned i = 0; i != 16; ++i) {
9154 int EltIdx = MaskVals[i];
9155 if (EltIdx < 0 || EltIdx >= 16)
9157 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9159 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
9160 DAG.getNode(ISD::BUILD_VECTOR, dl,
9161 MVT::v16i8, pshufbMask));
9163 // As PSHUFB will zero elements with negative indices, it's safe to ignore
9164 // the 2nd operand if it's undefined or zero.
9165 if (V2.getOpcode() == ISD::UNDEF ||
9166 ISD::isBuildVectorAllZeros(V2.getNode()))
9169 // Calculate the shuffle mask for the second input, shuffle it, and
9170 // OR it with the first shuffled input.
9172 for (unsigned i = 0; i != 16; ++i) {
9173 int EltIdx = MaskVals[i];
9174 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
9175 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9177 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
9178 DAG.getNode(ISD::BUILD_VECTOR, dl,
9179 MVT::v16i8, pshufbMask));
9180 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9183 // No SSSE3 - Calculate in place words and then fix all out of place words
9184 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
9185 // the 16 different words that comprise the two doublequadword input vectors.
9186 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9187 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
9189 for (int i = 0; i != 8; ++i) {
9190 int Elt0 = MaskVals[i*2];
9191 int Elt1 = MaskVals[i*2+1];
9193 // This word of the result is all undef, skip it.
9194 if (Elt0 < 0 && Elt1 < 0)
9197 // This word of the result is already in the correct place, skip it.
9198 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9201 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9202 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9205 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9206 // using a single extract together, load it and store it.
9207 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9208 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9209 DAG.getIntPtrConstant(Elt1 / 2));
9210 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9211 DAG.getIntPtrConstant(i));
9215 // If Elt1 is defined, extract it from the appropriate source. If the
9216 // source byte is not also odd, shift the extracted word left 8 bits
9217 // otherwise clear the bottom 8 bits if we need to do an or.
9219 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9220 DAG.getIntPtrConstant(Elt1 / 2));
9221 if ((Elt1 & 1) == 0)
9222 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9224 TLI.getShiftAmountTy(InsElt.getValueType())));
9226 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9227 DAG.getConstant(0xFF00, MVT::i16));
9229 // If Elt0 is defined, extract it from the appropriate source. If the
9230 // source byte is not also even, shift the extracted word right 8 bits. If
9231 // Elt1 was also defined, OR the extracted values together before
9232 // inserting them in the result.
9234 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9235 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9236 if ((Elt0 & 1) != 0)
9237 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9239 TLI.getShiftAmountTy(InsElt0.getValueType())));
9241 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9242 DAG.getConstant(0x00FF, MVT::i16));
9243 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
9246 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9247 DAG.getIntPtrConstant(i));
9249 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
9252 // v32i8 shuffles - Translate to VPSHUFB if possible.
9254 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
9255 const X86Subtarget *Subtarget,
9256 SelectionDAG &DAG) {
9257 MVT VT = SVOp->getSimpleValueType(0);
9258 SDValue V1 = SVOp->getOperand(0);
9259 SDValue V2 = SVOp->getOperand(1);
9261 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9263 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9264 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
9265 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
9267 // VPSHUFB may be generated if
9268 // (1) one of input vector is undefined or zeroinitializer.
9269 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
9270 // And (2) the mask indexes don't cross the 128-bit lane.
9271 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
9272 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
9275 if (V1IsAllZero && !V2IsAllZero) {
9276 CommuteVectorShuffleMask(MaskVals, 32);
9279 return getPSHUFB(MaskVals, V1, dl, DAG);
9282 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
9283 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
9284 /// done when every pair / quad of shuffle mask elements point to elements in
9285 /// the right sequence. e.g.
9286 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
9288 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
9289 SelectionDAG &DAG) {
9290 MVT VT = SVOp->getSimpleValueType(0);
9292 unsigned NumElems = VT.getVectorNumElements();
9295 switch (VT.SimpleTy) {
9296 default: llvm_unreachable("Unexpected!");
9299 return SDValue(SVOp, 0);
9300 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
9301 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
9302 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
9303 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
9304 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
9305 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
9308 SmallVector<int, 8> MaskVec;
9309 for (unsigned i = 0; i != NumElems; i += Scale) {
9311 for (unsigned j = 0; j != Scale; ++j) {
9312 int EltIdx = SVOp->getMaskElt(i+j);
9316 StartIdx = (EltIdx / Scale);
9317 if (EltIdx != (int)(StartIdx*Scale + j))
9320 MaskVec.push_back(StartIdx);
9323 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
9324 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
9325 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
9328 /// getVZextMovL - Return a zero-extending vector move low node.
9330 static SDValue getVZextMovL(MVT VT, MVT OpVT,
9331 SDValue SrcOp, SelectionDAG &DAG,
9332 const X86Subtarget *Subtarget, SDLoc dl) {
9333 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
9334 LoadSDNode *LD = nullptr;
9335 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
9336 LD = dyn_cast<LoadSDNode>(SrcOp);
9338 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
9340 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
9341 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
9342 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
9343 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
9344 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
9346 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
9347 return DAG.getNode(ISD::BITCAST, dl, VT,
9348 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9349 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9357 return DAG.getNode(ISD::BITCAST, dl, VT,
9358 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9359 DAG.getNode(ISD::BITCAST, dl,
9363 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
9364 /// which could not be matched by any known target speficic shuffle
9366 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9368 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
9369 if (NewOp.getNode())
9372 MVT VT = SVOp->getSimpleValueType(0);
9374 unsigned NumElems = VT.getVectorNumElements();
9375 unsigned NumLaneElems = NumElems / 2;
9378 MVT EltVT = VT.getVectorElementType();
9379 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
9382 SmallVector<int, 16> Mask;
9383 for (unsigned l = 0; l < 2; ++l) {
9384 // Build a shuffle mask for the output, discovering on the fly which
9385 // input vectors to use as shuffle operands (recorded in InputUsed).
9386 // If building a suitable shuffle vector proves too hard, then bail
9387 // out with UseBuildVector set.
9388 bool UseBuildVector = false;
9389 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
9390 unsigned LaneStart = l * NumLaneElems;
9391 for (unsigned i = 0; i != NumLaneElems; ++i) {
9392 // The mask element. This indexes into the input.
9393 int Idx = SVOp->getMaskElt(i+LaneStart);
9395 // the mask element does not index into any input vector.
9400 // The input vector this mask element indexes into.
9401 int Input = Idx / NumLaneElems;
9403 // Turn the index into an offset from the start of the input vector.
9404 Idx -= Input * NumLaneElems;
9406 // Find or create a shuffle vector operand to hold this input.
9408 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
9409 if (InputUsed[OpNo] == Input)
9410 // This input vector is already an operand.
9412 if (InputUsed[OpNo] < 0) {
9413 // Create a new operand for this input vector.
9414 InputUsed[OpNo] = Input;
9419 if (OpNo >= array_lengthof(InputUsed)) {
9420 // More than two input vectors used! Give up on trying to create a
9421 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
9422 UseBuildVector = true;
9426 // Add the mask index for the new shuffle vector.
9427 Mask.push_back(Idx + OpNo * NumLaneElems);
9430 if (UseBuildVector) {
9431 SmallVector<SDValue, 16> SVOps;
9432 for (unsigned i = 0; i != NumLaneElems; ++i) {
9433 // The mask element. This indexes into the input.
9434 int Idx = SVOp->getMaskElt(i+LaneStart);
9436 SVOps.push_back(DAG.getUNDEF(EltVT));
9440 // The input vector this mask element indexes into.
9441 int Input = Idx / NumElems;
9443 // Turn the index into an offset from the start of the input vector.
9444 Idx -= Input * NumElems;
9446 // Extract the vector element by hand.
9447 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
9448 SVOp->getOperand(Input),
9449 DAG.getIntPtrConstant(Idx)));
9452 // Construct the output using a BUILD_VECTOR.
9453 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
9454 } else if (InputUsed[0] < 0) {
9455 // No input vectors were used! The result is undefined.
9456 Output[l] = DAG.getUNDEF(NVT);
9458 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
9459 (InputUsed[0] % 2) * NumLaneElems,
9461 // If only one input was used, use an undefined vector for the other.
9462 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
9463 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
9464 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
9465 // At least one input vector was used. Create a new shuffle vector.
9466 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9472 // Concatenate the result back
9473 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
9476 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9477 /// 4 elements, and match them with several different shuffle types.
9479 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9480 SDValue V1 = SVOp->getOperand(0);
9481 SDValue V2 = SVOp->getOperand(1);
9483 MVT VT = SVOp->getSimpleValueType(0);
9485 assert(VT.is128BitVector() && "Unsupported vector size");
9487 std::pair<int, int> Locs[4];
9488 int Mask1[] = { -1, -1, -1, -1 };
9489 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9493 for (unsigned i = 0; i != 4; ++i) {
9494 int Idx = PermMask[i];
9496 Locs[i] = std::make_pair(-1, -1);
9498 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9500 Locs[i] = std::make_pair(0, NumLo);
9504 Locs[i] = std::make_pair(1, NumHi);
9506 Mask1[2+NumHi] = Idx;
9512 if (NumLo <= 2 && NumHi <= 2) {
9513 // If no more than two elements come from either vector. This can be
9514 // implemented with two shuffles. First shuffle gather the elements.
9515 // The second shuffle, which takes the first shuffle as both of its
9516 // vector operands, put the elements into the right order.
9517 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9519 int Mask2[] = { -1, -1, -1, -1 };
9521 for (unsigned i = 0; i != 4; ++i)
9522 if (Locs[i].first != -1) {
9523 unsigned Idx = (i < 2) ? 0 : 4;
9524 Idx += Locs[i].first * 2 + Locs[i].second;
9528 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9531 if (NumLo == 3 || NumHi == 3) {
9532 // Otherwise, we must have three elements from one vector, call it X, and
9533 // one element from the other, call it Y. First, use a shufps to build an
9534 // intermediate vector with the one element from Y and the element from X
9535 // that will be in the same half in the final destination (the indexes don't
9536 // matter). Then, use a shufps to build the final vector, taking the half
9537 // containing the element from Y from the intermediate, and the other half
9540 // Normalize it so the 3 elements come from V1.
9541 CommuteVectorShuffleMask(PermMask, 4);
9545 // Find the element from V2.
9547 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9548 int Val = PermMask[HiIndex];
9555 Mask1[0] = PermMask[HiIndex];
9557 Mask1[2] = PermMask[HiIndex^1];
9559 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9562 Mask1[0] = PermMask[0];
9563 Mask1[1] = PermMask[1];
9564 Mask1[2] = HiIndex & 1 ? 6 : 4;
9565 Mask1[3] = HiIndex & 1 ? 4 : 6;
9566 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9569 Mask1[0] = HiIndex & 1 ? 2 : 0;
9570 Mask1[1] = HiIndex & 1 ? 0 : 2;
9571 Mask1[2] = PermMask[2];
9572 Mask1[3] = PermMask[3];
9577 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9580 // Break it into (shuffle shuffle_hi, shuffle_lo).
9581 int LoMask[] = { -1, -1, -1, -1 };
9582 int HiMask[] = { -1, -1, -1, -1 };
9584 int *MaskPtr = LoMask;
9585 unsigned MaskIdx = 0;
9588 for (unsigned i = 0; i != 4; ++i) {
9595 int Idx = PermMask[i];
9597 Locs[i] = std::make_pair(-1, -1);
9598 } else if (Idx < 4) {
9599 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9600 MaskPtr[LoIdx] = Idx;
9603 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9604 MaskPtr[HiIdx] = Idx;
9609 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9610 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9611 int MaskOps[] = { -1, -1, -1, -1 };
9612 for (unsigned i = 0; i != 4; ++i)
9613 if (Locs[i].first != -1)
9614 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9615 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9618 static bool MayFoldVectorLoad(SDValue V) {
9619 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9620 V = V.getOperand(0);
9622 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9623 V = V.getOperand(0);
9624 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9625 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9626 // BUILD_VECTOR (load), undef
9627 V = V.getOperand(0);
9629 return MayFoldLoad(V);
9633 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9634 MVT VT = Op.getSimpleValueType();
9636 // Canonizalize to v2f64.
9637 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9638 return DAG.getNode(ISD::BITCAST, dl, VT,
9639 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9644 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9646 SDValue V1 = Op.getOperand(0);
9647 SDValue V2 = Op.getOperand(1);
9648 MVT VT = Op.getSimpleValueType();
9650 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9652 if (HasSSE2 && VT == MVT::v2f64)
9653 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9655 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9656 return DAG.getNode(ISD::BITCAST, dl, VT,
9657 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9658 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9659 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9663 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9664 SDValue V1 = Op.getOperand(0);
9665 SDValue V2 = Op.getOperand(1);
9666 MVT VT = Op.getSimpleValueType();
9668 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9669 "unsupported shuffle type");
9671 if (V2.getOpcode() == ISD::UNDEF)
9675 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9679 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9680 SDValue V1 = Op.getOperand(0);
9681 SDValue V2 = Op.getOperand(1);
9682 MVT VT = Op.getSimpleValueType();
9683 unsigned NumElems = VT.getVectorNumElements();
9685 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9686 // operand of these instructions is only memory, so check if there's a
9687 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9689 bool CanFoldLoad = false;
9691 // Trivial case, when V2 comes from a load.
9692 if (MayFoldVectorLoad(V2))
9695 // When V1 is a load, it can be folded later into a store in isel, example:
9696 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9698 // (MOVLPSmr addr:$src1, VR128:$src2)
9699 // So, recognize this potential and also use MOVLPS or MOVLPD
9700 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9705 if (HasSSE2 && NumElems == 2)
9706 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9709 // If we don't care about the second element, proceed to use movss.
9710 if (SVOp->getMaskElt(1) != -1)
9711 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9714 // movl and movlp will both match v2i64, but v2i64 is never matched by
9715 // movl earlier because we make it strict to avoid messing with the movlp load
9716 // folding logic (see the code above getMOVLP call). Match it here then,
9717 // this is horrible, but will stay like this until we move all shuffle
9718 // matching to x86 specific nodes. Note that for the 1st condition all
9719 // types are matched with movsd.
9721 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9722 // as to remove this logic from here, as much as possible
9723 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9724 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9725 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9728 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9730 // Invert the operand order and use SHUFPS to match it.
9731 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9732 getShuffleSHUFImmediate(SVOp), DAG);
9735 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9736 SelectionDAG &DAG) {
9738 MVT VT = Load->getSimpleValueType(0);
9739 MVT EVT = VT.getVectorElementType();
9740 SDValue Addr = Load->getOperand(1);
9741 SDValue NewAddr = DAG.getNode(
9742 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9743 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9746 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9747 DAG.getMachineFunction().getMachineMemOperand(
9748 Load->getMemOperand(), 0, EVT.getStoreSize()));
9752 // It is only safe to call this function if isINSERTPSMask is true for
9753 // this shufflevector mask.
9754 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9755 SelectionDAG &DAG) {
9756 // Generate an insertps instruction when inserting an f32 from memory onto a
9757 // v4f32 or when copying a member from one v4f32 to another.
9758 // We also use it for transferring i32 from one register to another,
9759 // since it simply copies the same bits.
9760 // If we're transferring an i32 from memory to a specific element in a
9761 // register, we output a generic DAG that will match the PINSRD
9763 MVT VT = SVOp->getSimpleValueType(0);
9764 MVT EVT = VT.getVectorElementType();
9765 SDValue V1 = SVOp->getOperand(0);
9766 SDValue V2 = SVOp->getOperand(1);
9767 auto Mask = SVOp->getMask();
9768 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9769 "unsupported vector type for insertps/pinsrd");
9771 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9772 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9773 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9781 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9784 // If we have 1 element from each vector, we have to check if we're
9785 // changing V1's element's place. If so, we're done. Otherwise, we
9786 // should assume we're changing V2's element's place and behave
9788 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9789 assert(DestIndex <= INT32_MAX && "truncated destination index");
9790 if (FromV1 == FromV2 &&
9791 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
9795 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9798 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9799 "More than one element from V1 and from V2, or no elements from one "
9800 "of the vectors. This case should not have returned true from "
9805 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9808 // Get an index into the source vector in the range [0,4) (the mask is
9809 // in the range [0,8) because it can address V1 and V2)
9810 unsigned SrcIndex = Mask[DestIndex] % 4;
9811 if (MayFoldLoad(From)) {
9812 // Trivial case, when From comes from a load and is only used by the
9813 // shuffle. Make it use insertps from the vector that we need from that
9816 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9817 if (!NewLoad.getNode())
9820 if (EVT == MVT::f32) {
9821 // Create this as a scalar to vector to match the instruction pattern.
9822 SDValue LoadScalarToVector =
9823 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9824 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9825 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9827 } else { // EVT == MVT::i32
9828 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9829 // instruction, to match the PINSRD instruction, which loads an i32 to a
9830 // certain vector element.
9831 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9832 DAG.getConstant(DestIndex, MVT::i32));
9836 // Vector-element-to-vector
9837 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9838 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9841 // Reduce a vector shuffle to zext.
9842 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9843 SelectionDAG &DAG) {
9844 // PMOVZX is only available from SSE41.
9845 if (!Subtarget->hasSSE41())
9848 MVT VT = Op.getSimpleValueType();
9850 // Only AVX2 support 256-bit vector integer extending.
9851 if (!Subtarget->hasInt256() && VT.is256BitVector())
9854 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9856 SDValue V1 = Op.getOperand(0);
9857 SDValue V2 = Op.getOperand(1);
9858 unsigned NumElems = VT.getVectorNumElements();
9860 // Extending is an unary operation and the element type of the source vector
9861 // won't be equal to or larger than i64.
9862 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9863 VT.getVectorElementType() == MVT::i64)
9866 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9867 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9868 while ((1U << Shift) < NumElems) {
9869 if (SVOp->getMaskElt(1U << Shift) == 1)
9872 // The maximal ratio is 8, i.e. from i8 to i64.
9877 // Check the shuffle mask.
9878 unsigned Mask = (1U << Shift) - 1;
9879 for (unsigned i = 0; i != NumElems; ++i) {
9880 int EltIdx = SVOp->getMaskElt(i);
9881 if ((i & Mask) != 0 && EltIdx != -1)
9883 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9887 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9888 MVT NeVT = MVT::getIntegerVT(NBits);
9889 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9891 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9894 // Simplify the operand as it's prepared to be fed into shuffle.
9895 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9896 if (V1.getOpcode() == ISD::BITCAST &&
9897 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9898 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9899 V1.getOperand(0).getOperand(0)
9900 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9901 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9902 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9903 ConstantSDNode *CIdx =
9904 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9905 // If it's foldable, i.e. normal load with single use, we will let code
9906 // selection to fold it. Otherwise, we will short the conversion sequence.
9907 if (CIdx && CIdx->getZExtValue() == 0 &&
9908 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9909 MVT FullVT = V.getSimpleValueType();
9910 MVT V1VT = V1.getSimpleValueType();
9911 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9912 // The "ext_vec_elt" node is wider than the result node.
9913 // In this case we should extract subvector from V.
9914 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9915 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9916 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9917 FullVT.getVectorNumElements()/Ratio);
9918 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9919 DAG.getIntPtrConstant(0));
9921 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9925 return DAG.getNode(ISD::BITCAST, DL, VT,
9926 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9929 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9930 SelectionDAG &DAG) {
9931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9932 MVT VT = Op.getSimpleValueType();
9934 SDValue V1 = Op.getOperand(0);
9935 SDValue V2 = Op.getOperand(1);
9937 if (isZeroShuffle(SVOp))
9938 return getZeroVector(VT, Subtarget, DAG, dl);
9940 // Handle splat operations
9941 if (SVOp->isSplat()) {
9942 // Use vbroadcast whenever the splat comes from a foldable load
9943 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9944 if (Broadcast.getNode())
9948 // Check integer expanding shuffles.
9949 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9950 if (NewOp.getNode())
9953 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9955 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9957 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9958 if (NewOp.getNode())
9959 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9960 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9961 // FIXME: Figure out a cleaner way to do this.
9962 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9963 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9964 if (NewOp.getNode()) {
9965 MVT NewVT = NewOp.getSimpleValueType();
9966 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9967 NewVT, true, false))
9968 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9971 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9972 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9973 if (NewOp.getNode()) {
9974 MVT NewVT = NewOp.getSimpleValueType();
9975 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9976 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9985 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9986 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9987 SDValue V1 = Op.getOperand(0);
9988 SDValue V2 = Op.getOperand(1);
9989 MVT VT = Op.getSimpleValueType();
9991 unsigned NumElems = VT.getVectorNumElements();
9992 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9993 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9994 bool V1IsSplat = false;
9995 bool V2IsSplat = false;
9996 bool HasSSE2 = Subtarget->hasSSE2();
9997 bool HasFp256 = Subtarget->hasFp256();
9998 bool HasInt256 = Subtarget->hasInt256();
9999 MachineFunction &MF = DAG.getMachineFunction();
10000 bool OptForSize = MF.getFunction()->getAttributes().
10001 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10003 // Check if we should use the experimental vector shuffle lowering. If so,
10004 // delegate completely to that code path.
10005 if (ExperimentalVectorShuffleLowering)
10006 return lowerVectorShuffle(Op, Subtarget, DAG);
10008 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10010 if (V1IsUndef && V2IsUndef)
10011 return DAG.getUNDEF(VT);
10013 // When we create a shuffle node we put the UNDEF node to second operand,
10014 // but in some cases the first operand may be transformed to UNDEF.
10015 // In this case we should just commute the node.
10017 return DAG.getCommutedVectorShuffle(*SVOp);
10019 // Vector shuffle lowering takes 3 steps:
10021 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10022 // narrowing and commutation of operands should be handled.
10023 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10025 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10026 // so the shuffle can be broken into other shuffles and the legalizer can
10027 // try the lowering again.
10029 // The general idea is that no vector_shuffle operation should be left to
10030 // be matched during isel, all of them must be converted to a target specific
10033 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10034 // narrowing and commutation of operands should be handled. The actual code
10035 // doesn't include all of those, work in progress...
10036 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10037 if (NewOp.getNode())
10040 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10042 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10043 // unpckh_undef). Only use pshufd if speed is more important than size.
10044 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10045 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10046 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10047 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10049 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10050 V2IsUndef && MayFoldVectorLoad(V1))
10051 return getMOVDDup(Op, dl, V1, DAG);
10053 if (isMOVHLPS_v_undef_Mask(M, VT))
10054 return getMOVHighToLow(Op, dl, DAG);
10056 // Use to match splats
10057 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
10058 (VT == MVT::v2f64 || VT == MVT::v2i64))
10059 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10061 if (isPSHUFDMask(M, VT)) {
10062 // The actual implementation will match the mask in the if above and then
10063 // during isel it can match several different instructions, not only pshufd
10064 // as its name says, sad but true, emulate the behavior for now...
10065 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
10066 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
10068 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
10070 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
10071 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
10073 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
10074 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
10077 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
10081 if (isPALIGNRMask(M, VT, Subtarget))
10082 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
10083 getShufflePALIGNRImmediate(SVOp),
10086 if (isVALIGNMask(M, VT, Subtarget))
10087 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
10088 getShuffleVALIGNImmediate(SVOp),
10091 // Check if this can be converted into a logical shift.
10092 bool isLeft = false;
10093 unsigned ShAmt = 0;
10095 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
10096 if (isShift && ShVal.hasOneUse()) {
10097 // If the shifted value has multiple uses, it may be cheaper to use
10098 // v_set0 + movlhps or movhlps, etc.
10099 MVT EltVT = VT.getVectorElementType();
10100 ShAmt *= EltVT.getSizeInBits();
10101 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10104 if (isMOVLMask(M, VT)) {
10105 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10106 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
10107 if (!isMOVLPMask(M, VT)) {
10108 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
10109 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10111 if (VT == MVT::v4i32 || VT == MVT::v4f32)
10112 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10116 // FIXME: fold these into legal mask.
10117 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
10118 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
10120 if (isMOVHLPSMask(M, VT))
10121 return getMOVHighToLow(Op, dl, DAG);
10123 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
10124 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
10126 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
10127 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
10129 if (isMOVLPMask(M, VT))
10130 return getMOVLP(Op, dl, DAG, HasSSE2);
10132 if (ShouldXformToMOVHLPS(M, VT) ||
10133 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
10134 return DAG.getCommutedVectorShuffle(*SVOp);
10137 // No better options. Use a vshldq / vsrldq.
10138 MVT EltVT = VT.getVectorElementType();
10139 ShAmt *= EltVT.getSizeInBits();
10140 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10143 bool Commuted = false;
10144 // FIXME: This should also accept a bitcast of a splat? Be careful, not
10145 // 1,1,1,1 -> v8i16 though.
10146 BitVector UndefElements;
10147 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
10148 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10150 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
10151 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10154 // Canonicalize the splat or undef, if present, to be on the RHS.
10155 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
10156 CommuteVectorShuffleMask(M, NumElems);
10158 std::swap(V1IsSplat, V2IsSplat);
10162 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
10163 // Shuffling low element of v1 into undef, just return v1.
10166 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
10167 // the instruction selector will not match, so get a canonical MOVL with
10168 // swapped operands to undo the commute.
10169 return getMOVL(DAG, dl, VT, V2, V1);
10172 if (isUNPCKLMask(M, VT, HasInt256))
10173 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10175 if (isUNPCKHMask(M, VT, HasInt256))
10176 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10179 // Normalize mask so all entries that point to V2 points to its first
10180 // element then try to match unpck{h|l} again. If match, return a
10181 // new vector_shuffle with the corrected mask.p
10182 SmallVector<int, 8> NewMask(M.begin(), M.end());
10183 NormalizeMask(NewMask, NumElems);
10184 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
10185 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10186 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
10187 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10191 // Commute is back and try unpck* again.
10192 // FIXME: this seems wrong.
10193 CommuteVectorShuffleMask(M, NumElems);
10195 std::swap(V1IsSplat, V2IsSplat);
10197 if (isUNPCKLMask(M, VT, HasInt256))
10198 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10200 if (isUNPCKHMask(M, VT, HasInt256))
10201 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10204 // Normalize the node to match x86 shuffle ops if needed
10205 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10206 return DAG.getCommutedVectorShuffle(*SVOp);
10208 // The checks below are all present in isShuffleMaskLegal, but they are
10209 // inlined here right now to enable us to directly emit target specific
10210 // nodes, and remove one by one until they don't return Op anymore.
10212 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10213 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10214 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10215 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10218 if (isPSHUFHWMask(M, VT, HasInt256))
10219 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10220 getShufflePSHUFHWImmediate(SVOp),
10223 if (isPSHUFLWMask(M, VT, HasInt256))
10224 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10225 getShufflePSHUFLWImmediate(SVOp),
10228 unsigned MaskValue;
10229 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10231 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10233 if (isSHUFPMask(M, VT))
10234 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10235 getShuffleSHUFImmediate(SVOp), DAG);
10237 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10238 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10239 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10240 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10242 //===--------------------------------------------------------------------===//
10243 // Generate target specific nodes for 128 or 256-bit shuffles only
10244 // supported in the AVX instruction set.
10247 // Handle VMOVDDUPY permutations
10248 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
10249 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
10251 // Handle VPERMILPS/D* permutations
10252 if (isVPERMILPMask(M, VT)) {
10253 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
10254 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
10255 getShuffleSHUFImmediate(SVOp), DAG);
10256 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
10257 getShuffleSHUFImmediate(SVOp), DAG);
10261 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
10262 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
10263 Idx*(NumElems/2), DAG, dl);
10265 // Handle VPERM2F128/VPERM2I128 permutations
10266 if (isVPERM2X128Mask(M, VT, HasFp256))
10267 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
10268 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
10270 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
10271 return getINSERTPS(SVOp, dl, DAG);
10274 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
10275 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
10277 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
10278 VT.is512BitVector()) {
10279 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
10280 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
10281 SmallVector<SDValue, 16> permclMask;
10282 for (unsigned i = 0; i != NumElems; ++i) {
10283 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
10286 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
10288 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
10289 return DAG.getNode(X86ISD::VPERMV, dl, VT,
10290 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
10291 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
10292 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
10295 //===--------------------------------------------------------------------===//
10296 // Since no target specific shuffle was selected for this generic one,
10297 // lower it into other known shuffles. FIXME: this isn't true yet, but
10298 // this is the plan.
10301 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
10302 if (VT == MVT::v8i16) {
10303 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
10304 if (NewOp.getNode())
10308 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
10309 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
10310 if (NewOp.getNode())
10314 if (VT == MVT::v16i8) {
10315 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
10316 if (NewOp.getNode())
10320 if (VT == MVT::v32i8) {
10321 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
10322 if (NewOp.getNode())
10326 // Handle all 128-bit wide vectors with 4 elements, and match them with
10327 // several different shuffle types.
10328 if (NumElems == 4 && VT.is128BitVector())
10329 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
10331 // Handle general 256-bit shuffles
10332 if (VT.is256BitVector())
10333 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
10338 // This function assumes its argument is a BUILD_VECTOR of constants or
10339 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10341 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10342 unsigned &MaskValue) {
10344 unsigned NumElems = BuildVector->getNumOperands();
10345 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10346 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10347 unsigned NumElemsInLane = NumElems / NumLanes;
10349 // Blend for v16i16 should be symetric for the both lanes.
10350 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10351 SDValue EltCond = BuildVector->getOperand(i);
10352 SDValue SndLaneEltCond =
10353 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10355 int Lane1Cond = -1, Lane2Cond = -1;
10356 if (isa<ConstantSDNode>(EltCond))
10357 Lane1Cond = !isZero(EltCond);
10358 if (isa<ConstantSDNode>(SndLaneEltCond))
10359 Lane2Cond = !isZero(SndLaneEltCond);
10361 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10362 // Lane1Cond != 0, means we want the first argument.
10363 // Lane1Cond == 0, means we want the second argument.
10364 // The encoding of this argument is 0 for the first argument, 1
10365 // for the second. Therefore, invert the condition.
10366 MaskValue |= !Lane1Cond << i;
10367 else if (Lane1Cond < 0)
10368 MaskValue |= !Lane2Cond << i;
10375 // Try to lower a vselect node into a simple blend instruction.
10376 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
10377 SelectionDAG &DAG) {
10378 SDValue Cond = Op.getOperand(0);
10379 SDValue LHS = Op.getOperand(1);
10380 SDValue RHS = Op.getOperand(2);
10382 MVT VT = Op.getSimpleValueType();
10383 MVT EltVT = VT.getVectorElementType();
10384 unsigned NumElems = VT.getVectorNumElements();
10386 // There is no blend with immediate in AVX-512.
10387 if (VT.is512BitVector())
10390 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
10392 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
10395 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10398 // Check the mask for BLEND and build the value.
10399 unsigned MaskValue = 0;
10400 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
10403 // Convert i32 vectors to floating point if it is not AVX2.
10404 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10406 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10407 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10409 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
10410 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
10413 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
10414 DAG.getConstant(MaskValue, MVT::i32));
10415 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10418 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10419 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
10420 if (BlendOp.getNode())
10423 // Some types for vselect were previously set to Expand, not Legal or
10424 // Custom. Return an empty SDValue so we fall-through to Expand, after
10425 // the Custom lowering phase.
10426 MVT VT = Op.getSimpleValueType();
10427 switch (VT.SimpleTy) {
10435 // We couldn't create a "Blend with immediate" node.
10436 // This node should still be legal, but we'll have to emit a blendv*
10441 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10442 MVT VT = Op.getSimpleValueType();
10445 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10448 if (VT.getSizeInBits() == 8) {
10449 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10450 Op.getOperand(0), Op.getOperand(1));
10451 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10452 DAG.getValueType(VT));
10453 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10456 if (VT.getSizeInBits() == 16) {
10457 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10458 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10460 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10461 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10462 DAG.getNode(ISD::BITCAST, dl,
10465 Op.getOperand(1)));
10466 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10467 Op.getOperand(0), Op.getOperand(1));
10468 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10469 DAG.getValueType(VT));
10470 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10473 if (VT == MVT::f32) {
10474 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10475 // the result back to FR32 register. It's only worth matching if the
10476 // result has a single use which is a store or a bitcast to i32. And in
10477 // the case of a store, it's not worth it if the index is a constant 0,
10478 // because a MOVSSmr can be used instead, which is smaller and faster.
10479 if (!Op.hasOneUse())
10481 SDNode *User = *Op.getNode()->use_begin();
10482 if ((User->getOpcode() != ISD::STORE ||
10483 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10484 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10485 (User->getOpcode() != ISD::BITCAST ||
10486 User->getValueType(0) != MVT::i32))
10488 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10489 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10492 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10495 if (VT == MVT::i32 || VT == MVT::i64) {
10496 // ExtractPS/pextrq works with constant index.
10497 if (isa<ConstantSDNode>(Op.getOperand(1)))
10503 /// Extract one bit from mask vector, like v16i1 or v8i1.
10504 /// AVX-512 feature.
10506 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10507 SDValue Vec = Op.getOperand(0);
10509 MVT VecVT = Vec.getSimpleValueType();
10510 SDValue Idx = Op.getOperand(1);
10511 MVT EltVT = Op.getSimpleValueType();
10513 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10515 // variable index can't be handled in mask registers,
10516 // extend vector to VR512
10517 if (!isa<ConstantSDNode>(Idx)) {
10518 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10519 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10520 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10521 ExtVT.getVectorElementType(), Ext, Idx);
10522 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10525 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10526 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10527 unsigned MaxSift = rc->getSize()*8 - 1;
10528 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10529 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10530 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10531 DAG.getConstant(MaxSift, MVT::i8));
10532 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10533 DAG.getIntPtrConstant(0));
10537 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10538 SelectionDAG &DAG) const {
10540 SDValue Vec = Op.getOperand(0);
10541 MVT VecVT = Vec.getSimpleValueType();
10542 SDValue Idx = Op.getOperand(1);
10544 if (Op.getSimpleValueType() == MVT::i1)
10545 return ExtractBitFromMaskVector(Op, DAG);
10547 if (!isa<ConstantSDNode>(Idx)) {
10548 if (VecVT.is512BitVector() ||
10549 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10550 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10553 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10554 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10555 MaskEltVT.getSizeInBits());
10557 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10558 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10559 getZeroVector(MaskVT, Subtarget, DAG, dl),
10560 Idx, DAG.getConstant(0, getPointerTy()));
10561 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10562 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10563 Perm, DAG.getConstant(0, getPointerTy()));
10568 // If this is a 256-bit vector result, first extract the 128-bit vector and
10569 // then extract the element from the 128-bit vector.
10570 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10572 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10573 // Get the 128-bit vector.
10574 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10575 MVT EltVT = VecVT.getVectorElementType();
10577 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10579 //if (IdxVal >= NumElems/2)
10580 // IdxVal -= NumElems/2;
10581 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10582 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10583 DAG.getConstant(IdxVal, MVT::i32));
10586 assert(VecVT.is128BitVector() && "Unexpected vector length");
10588 if (Subtarget->hasSSE41()) {
10589 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10594 MVT VT = Op.getSimpleValueType();
10595 // TODO: handle v16i8.
10596 if (VT.getSizeInBits() == 16) {
10597 SDValue Vec = Op.getOperand(0);
10598 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10600 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10601 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10602 DAG.getNode(ISD::BITCAST, dl,
10604 Op.getOperand(1)));
10605 // Transform it so it match pextrw which produces a 32-bit result.
10606 MVT EltVT = MVT::i32;
10607 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10608 Op.getOperand(0), Op.getOperand(1));
10609 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10610 DAG.getValueType(VT));
10611 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10614 if (VT.getSizeInBits() == 32) {
10615 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10619 // SHUFPS the element to the lowest double word, then movss.
10620 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10621 MVT VVT = Op.getOperand(0).getSimpleValueType();
10622 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10623 DAG.getUNDEF(VVT), Mask);
10624 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10625 DAG.getIntPtrConstant(0));
10628 if (VT.getSizeInBits() == 64) {
10629 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10630 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10631 // to match extract_elt for f64.
10632 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10636 // UNPCKHPD the element to the lowest double word, then movsd.
10637 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10638 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10639 int Mask[2] = { 1, -1 };
10640 MVT VVT = Op.getOperand(0).getSimpleValueType();
10641 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10642 DAG.getUNDEF(VVT), Mask);
10643 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10644 DAG.getIntPtrConstant(0));
10650 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10651 MVT VT = Op.getSimpleValueType();
10652 MVT EltVT = VT.getVectorElementType();
10655 SDValue N0 = Op.getOperand(0);
10656 SDValue N1 = Op.getOperand(1);
10657 SDValue N2 = Op.getOperand(2);
10659 if (!VT.is128BitVector())
10662 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
10663 isa<ConstantSDNode>(N2)) {
10665 if (VT == MVT::v8i16)
10666 Opc = X86ISD::PINSRW;
10667 else if (VT == MVT::v16i8)
10668 Opc = X86ISD::PINSRB;
10670 Opc = X86ISD::PINSRB;
10672 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10674 if (N1.getValueType() != MVT::i32)
10675 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10676 if (N2.getValueType() != MVT::i32)
10677 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10678 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10681 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
10682 // Bits [7:6] of the constant are the source select. This will always be
10683 // zero here. The DAG Combiner may combine an extract_elt index into these
10684 // bits. For example (insert (extract, 3), 2) could be matched by putting
10685 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10686 // Bits [5:4] of the constant are the destination select. This is the
10687 // value of the incoming immediate.
10688 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10689 // combine either bitwise AND or insert of float 0.0 to set these bits.
10690 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
10691 // Create this as a scalar to vector..
10692 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10693 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10696 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
10697 // PINSR* works with constant index.
10703 /// Insert one bit to mask vector, like v16i1 or v8i1.
10704 /// AVX-512 feature.
10706 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10708 SDValue Vec = Op.getOperand(0);
10709 SDValue Elt = Op.getOperand(1);
10710 SDValue Idx = Op.getOperand(2);
10711 MVT VecVT = Vec.getSimpleValueType();
10713 if (!isa<ConstantSDNode>(Idx)) {
10714 // Non constant index. Extend source and destination,
10715 // insert element and then truncate the result.
10716 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10717 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10718 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10719 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10720 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10721 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10724 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10725 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10726 if (Vec.getOpcode() == ISD::UNDEF)
10727 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10728 DAG.getConstant(IdxVal, MVT::i8));
10729 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10730 unsigned MaxSift = rc->getSize()*8 - 1;
10731 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10732 DAG.getConstant(MaxSift, MVT::i8));
10733 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10734 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10735 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10738 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
10739 MVT VT = Op.getSimpleValueType();
10740 MVT EltVT = VT.getVectorElementType();
10742 if (EltVT == MVT::i1)
10743 return InsertBitToMaskVector(Op, DAG);
10746 SDValue N0 = Op.getOperand(0);
10747 SDValue N1 = Op.getOperand(1);
10748 SDValue N2 = Op.getOperand(2);
10750 // If this is a 256-bit vector result, first extract the 128-bit vector,
10751 // insert the element into the extracted half and then place it back.
10752 if (VT.is256BitVector() || VT.is512BitVector()) {
10753 if (!isa<ConstantSDNode>(N2))
10756 // Get the desired 128-bit vector half.
10757 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10758 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10760 // Insert the element into the desired half.
10761 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10762 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10764 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10765 DAG.getConstant(IdxIn128, MVT::i32));
10767 // Insert the changed part back to the 256-bit vector
10768 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10771 if (Subtarget->hasSSE41())
10772 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10774 if (EltVT == MVT::i8)
10777 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10778 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10779 // as its second argument.
10780 if (N1.getValueType() != MVT::i32)
10781 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10782 if (N2.getValueType() != MVT::i32)
10783 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10784 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10789 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10791 MVT OpVT = Op.getSimpleValueType();
10793 // If this is a 256-bit vector result, first insert into a 128-bit
10794 // vector and then insert into the 256-bit vector.
10795 if (!OpVT.is128BitVector()) {
10796 // Insert into a 128-bit vector.
10797 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10798 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10799 OpVT.getVectorNumElements() / SizeFactor);
10801 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10803 // Insert the 128-bit vector.
10804 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10807 if (OpVT == MVT::v1i64 &&
10808 Op.getOperand(0).getValueType() == MVT::i64)
10809 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10811 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10812 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10813 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10814 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10817 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10818 // a simple subregister reference or explicit instructions to grab
10819 // upper bits of a vector.
10820 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10821 SelectionDAG &DAG) {
10823 SDValue In = Op.getOperand(0);
10824 SDValue Idx = Op.getOperand(1);
10825 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10826 MVT ResVT = Op.getSimpleValueType();
10827 MVT InVT = In.getSimpleValueType();
10829 if (Subtarget->hasFp256()) {
10830 if (ResVT.is128BitVector() &&
10831 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10832 isa<ConstantSDNode>(Idx)) {
10833 return Extract128BitVector(In, IdxVal, DAG, dl);
10835 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10836 isa<ConstantSDNode>(Idx)) {
10837 return Extract256BitVector(In, IdxVal, DAG, dl);
10843 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10844 // simple superregister reference or explicit instructions to insert
10845 // the upper bits of a vector.
10846 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10847 SelectionDAG &DAG) {
10848 if (Subtarget->hasFp256()) {
10849 SDLoc dl(Op.getNode());
10850 SDValue Vec = Op.getNode()->getOperand(0);
10851 SDValue SubVec = Op.getNode()->getOperand(1);
10852 SDValue Idx = Op.getNode()->getOperand(2);
10854 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10855 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10856 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10857 isa<ConstantSDNode>(Idx)) {
10858 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10859 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10862 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10863 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10864 isa<ConstantSDNode>(Idx)) {
10865 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10866 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10872 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10873 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10874 // one of the above mentioned nodes. It has to be wrapped because otherwise
10875 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10876 // be used to form addressing mode. These wrapped nodes will be selected
10879 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10880 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10882 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10883 // global base reg.
10884 unsigned char OpFlag = 0;
10885 unsigned WrapperKind = X86ISD::Wrapper;
10886 CodeModel::Model M = DAG.getTarget().getCodeModel();
10888 if (Subtarget->isPICStyleRIPRel() &&
10889 (M == CodeModel::Small || M == CodeModel::Kernel))
10890 WrapperKind = X86ISD::WrapperRIP;
10891 else if (Subtarget->isPICStyleGOT())
10892 OpFlag = X86II::MO_GOTOFF;
10893 else if (Subtarget->isPICStyleStubPIC())
10894 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10896 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10897 CP->getAlignment(),
10898 CP->getOffset(), OpFlag);
10900 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10901 // With PIC, the address is actually $g + Offset.
10903 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10904 DAG.getNode(X86ISD::GlobalBaseReg,
10905 SDLoc(), getPointerTy()),
10912 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10913 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10915 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10916 // global base reg.
10917 unsigned char OpFlag = 0;
10918 unsigned WrapperKind = X86ISD::Wrapper;
10919 CodeModel::Model M = DAG.getTarget().getCodeModel();
10921 if (Subtarget->isPICStyleRIPRel() &&
10922 (M == CodeModel::Small || M == CodeModel::Kernel))
10923 WrapperKind = X86ISD::WrapperRIP;
10924 else if (Subtarget->isPICStyleGOT())
10925 OpFlag = X86II::MO_GOTOFF;
10926 else if (Subtarget->isPICStyleStubPIC())
10927 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10929 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10932 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10934 // With PIC, the address is actually $g + Offset.
10936 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10937 DAG.getNode(X86ISD::GlobalBaseReg,
10938 SDLoc(), getPointerTy()),
10945 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10946 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10948 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10949 // global base reg.
10950 unsigned char OpFlag = 0;
10951 unsigned WrapperKind = X86ISD::Wrapper;
10952 CodeModel::Model M = DAG.getTarget().getCodeModel();
10954 if (Subtarget->isPICStyleRIPRel() &&
10955 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10956 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10957 OpFlag = X86II::MO_GOTPCREL;
10958 WrapperKind = X86ISD::WrapperRIP;
10959 } else if (Subtarget->isPICStyleGOT()) {
10960 OpFlag = X86II::MO_GOT;
10961 } else if (Subtarget->isPICStyleStubPIC()) {
10962 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10963 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10964 OpFlag = X86II::MO_DARWIN_NONLAZY;
10967 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10970 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10972 // With PIC, the address is actually $g + Offset.
10973 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10974 !Subtarget->is64Bit()) {
10975 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10976 DAG.getNode(X86ISD::GlobalBaseReg,
10977 SDLoc(), getPointerTy()),
10981 // For symbols that require a load from a stub to get the address, emit the
10983 if (isGlobalStubReference(OpFlag))
10984 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10985 MachinePointerInfo::getGOT(), false, false, false, 0);
10991 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10992 // Create the TargetBlockAddressAddress node.
10993 unsigned char OpFlags =
10994 Subtarget->ClassifyBlockAddressReference();
10995 CodeModel::Model M = DAG.getTarget().getCodeModel();
10996 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10997 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10999 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11002 if (Subtarget->isPICStyleRIPRel() &&
11003 (M == CodeModel::Small || M == CodeModel::Kernel))
11004 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11006 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11008 // With PIC, the address is actually $g + Offset.
11009 if (isGlobalRelativeToPICBase(OpFlags)) {
11010 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11011 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11019 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11020 int64_t Offset, SelectionDAG &DAG) const {
11021 // Create the TargetGlobalAddress node, folding in the constant
11022 // offset if it is legal.
11023 unsigned char OpFlags =
11024 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11025 CodeModel::Model M = DAG.getTarget().getCodeModel();
11027 if (OpFlags == X86II::MO_NO_FLAG &&
11028 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11029 // A direct static reference to a global.
11030 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11033 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11036 if (Subtarget->isPICStyleRIPRel() &&
11037 (M == CodeModel::Small || M == CodeModel::Kernel))
11038 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11040 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11042 // With PIC, the address is actually $g + Offset.
11043 if (isGlobalRelativeToPICBase(OpFlags)) {
11044 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11045 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11049 // For globals that require a load from a stub to get the address, emit the
11051 if (isGlobalStubReference(OpFlags))
11052 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11053 MachinePointerInfo::getGOT(), false, false, false, 0);
11055 // If there was a non-zero offset that we didn't fold, create an explicit
11056 // addition for it.
11058 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11059 DAG.getConstant(Offset, getPointerTy()));
11065 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11066 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11067 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11068 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11072 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11073 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11074 unsigned char OperandFlags, bool LocalDynamic = false) {
11075 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11076 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11078 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11079 GA->getValueType(0),
11083 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11087 SDValue Ops[] = { Chain, TGA, *InFlag };
11088 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11090 SDValue Ops[] = { Chain, TGA };
11091 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11094 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11095 MFI->setAdjustsStack(true);
11097 SDValue Flag = Chain.getValue(1);
11098 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11101 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11103 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11106 SDLoc dl(GA); // ? function entry point might be better
11107 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11108 DAG.getNode(X86ISD::GlobalBaseReg,
11109 SDLoc(), PtrVT), InFlag);
11110 InFlag = Chain.getValue(1);
11112 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11115 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11117 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11119 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11120 X86::RAX, X86II::MO_TLSGD);
11123 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11129 // Get the start address of the TLS block for this module.
11130 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11131 .getInfo<X86MachineFunctionInfo>();
11132 MFI->incNumLocalDynamicTLSAccesses();
11136 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11137 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11140 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11141 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11142 InFlag = Chain.getValue(1);
11143 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11144 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11147 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11151 unsigned char OperandFlags = X86II::MO_DTPOFF;
11152 unsigned WrapperKind = X86ISD::Wrapper;
11153 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11154 GA->getValueType(0),
11155 GA->getOffset(), OperandFlags);
11156 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11158 // Add x@dtpoff with the base.
11159 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11162 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11163 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11164 const EVT PtrVT, TLSModel::Model model,
11165 bool is64Bit, bool isPIC) {
11168 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11169 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11170 is64Bit ? 257 : 256));
11172 SDValue ThreadPointer =
11173 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11174 MachinePointerInfo(Ptr), false, false, false, 0);
11176 unsigned char OperandFlags = 0;
11177 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11179 unsigned WrapperKind = X86ISD::Wrapper;
11180 if (model == TLSModel::LocalExec) {
11181 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11182 } else if (model == TLSModel::InitialExec) {
11184 OperandFlags = X86II::MO_GOTTPOFF;
11185 WrapperKind = X86ISD::WrapperRIP;
11187 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11190 llvm_unreachable("Unexpected model");
11193 // emit "addl x@ntpoff,%eax" (local exec)
11194 // or "addl x@indntpoff,%eax" (initial exec)
11195 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11197 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11198 GA->getOffset(), OperandFlags);
11199 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11201 if (model == TLSModel::InitialExec) {
11202 if (isPIC && !is64Bit) {
11203 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11204 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11208 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11209 MachinePointerInfo::getGOT(), false, false, false, 0);
11212 // The address of the thread local variable is the add of the thread
11213 // pointer with the offset of the variable.
11214 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11218 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11220 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11221 const GlobalValue *GV = GA->getGlobal();
11223 if (Subtarget->isTargetELF()) {
11224 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11227 case TLSModel::GeneralDynamic:
11228 if (Subtarget->is64Bit())
11229 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11230 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11231 case TLSModel::LocalDynamic:
11232 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11233 Subtarget->is64Bit());
11234 case TLSModel::InitialExec:
11235 case TLSModel::LocalExec:
11236 return LowerToTLSExecModel(
11237 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11238 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11240 llvm_unreachable("Unknown TLS model.");
11243 if (Subtarget->isTargetDarwin()) {
11244 // Darwin only has one model of TLS. Lower to that.
11245 unsigned char OpFlag = 0;
11246 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11247 X86ISD::WrapperRIP : X86ISD::Wrapper;
11249 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11250 // global base reg.
11251 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11252 !Subtarget->is64Bit();
11254 OpFlag = X86II::MO_TLVP_PIC_BASE;
11256 OpFlag = X86II::MO_TLVP;
11258 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11259 GA->getValueType(0),
11260 GA->getOffset(), OpFlag);
11261 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11263 // With PIC32, the address is actually $g + Offset.
11265 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11266 DAG.getNode(X86ISD::GlobalBaseReg,
11267 SDLoc(), getPointerTy()),
11270 // Lowering the machine isd will make sure everything is in the right
11272 SDValue Chain = DAG.getEntryNode();
11273 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11274 SDValue Args[] = { Chain, Offset };
11275 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11277 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11278 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11279 MFI->setAdjustsStack(true);
11281 // And our return value (tls address) is in the standard call return value
11283 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11284 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11285 Chain.getValue(1));
11288 if (Subtarget->isTargetKnownWindowsMSVC() ||
11289 Subtarget->isTargetWindowsGNU()) {
11290 // Just use the implicit TLS architecture
11291 // Need to generate someting similar to:
11292 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11294 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11295 // mov rcx, qword [rdx+rcx*8]
11296 // mov eax, .tls$:tlsvar
11297 // [rax+rcx] contains the address
11298 // Windows 64bit: gs:0x58
11299 // Windows 32bit: fs:__tls_array
11302 SDValue Chain = DAG.getEntryNode();
11304 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11305 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11306 // use its literal value of 0x2C.
11307 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11308 ? Type::getInt8PtrTy(*DAG.getContext(),
11310 : Type::getInt32PtrTy(*DAG.getContext(),
11314 Subtarget->is64Bit()
11315 ? DAG.getIntPtrConstant(0x58)
11316 : (Subtarget->isTargetWindowsGNU()
11317 ? DAG.getIntPtrConstant(0x2C)
11318 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11320 SDValue ThreadPointer =
11321 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11322 MachinePointerInfo(Ptr), false, false, false, 0);
11324 // Load the _tls_index variable
11325 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11326 if (Subtarget->is64Bit())
11327 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11328 IDX, MachinePointerInfo(), MVT::i32,
11329 false, false, false, 0);
11331 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11332 false, false, false, 0);
11334 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11336 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11338 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11339 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11340 false, false, false, 0);
11342 // Get the offset of start of .tls section
11343 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11344 GA->getValueType(0),
11345 GA->getOffset(), X86II::MO_SECREL);
11346 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11348 // The address of the thread local variable is the add of the thread
11349 // pointer with the offset of the variable.
11350 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11353 llvm_unreachable("TLS not implemented for this target.");
11356 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11357 /// and take a 2 x i32 value to shift plus a shift amount.
11358 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11359 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11360 MVT VT = Op.getSimpleValueType();
11361 unsigned VTBits = VT.getSizeInBits();
11363 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11364 SDValue ShOpLo = Op.getOperand(0);
11365 SDValue ShOpHi = Op.getOperand(1);
11366 SDValue ShAmt = Op.getOperand(2);
11367 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11368 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11370 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11371 DAG.getConstant(VTBits - 1, MVT::i8));
11372 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11373 DAG.getConstant(VTBits - 1, MVT::i8))
11374 : DAG.getConstant(0, VT);
11376 SDValue Tmp2, Tmp3;
11377 if (Op.getOpcode() == ISD::SHL_PARTS) {
11378 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11379 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11381 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11382 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11385 // If the shift amount is larger or equal than the width of a part we can't
11386 // rely on the results of shld/shrd. Insert a test and select the appropriate
11387 // values for large shift amounts.
11388 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11389 DAG.getConstant(VTBits, MVT::i8));
11390 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11391 AndNode, DAG.getConstant(0, MVT::i8));
11394 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11395 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11396 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11398 if (Op.getOpcode() == ISD::SHL_PARTS) {
11399 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11400 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11402 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11403 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11406 SDValue Ops[2] = { Lo, Hi };
11407 return DAG.getMergeValues(Ops, dl);
11410 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11411 SelectionDAG &DAG) const {
11412 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11414 if (SrcVT.isVector())
11417 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11418 "Unknown SINT_TO_FP to lower!");
11420 // These are really Legal; return the operand so the caller accepts it as
11422 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11424 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11425 Subtarget->is64Bit()) {
11430 unsigned Size = SrcVT.getSizeInBits()/8;
11431 MachineFunction &MF = DAG.getMachineFunction();
11432 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11433 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11434 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11436 MachinePointerInfo::getFixedStack(SSFI),
11438 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11441 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11443 SelectionDAG &DAG) const {
11447 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11449 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11451 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11453 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11455 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11456 MachineMemOperand *MMO;
11458 int SSFI = FI->getIndex();
11460 DAG.getMachineFunction()
11461 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11462 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11464 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11465 StackSlot = StackSlot.getOperand(1);
11467 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11468 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11470 Tys, Ops, SrcVT, MMO);
11473 Chain = Result.getValue(1);
11474 SDValue InFlag = Result.getValue(2);
11476 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11477 // shouldn't be necessary except that RFP cannot be live across
11478 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11479 MachineFunction &MF = DAG.getMachineFunction();
11480 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11481 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11482 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11483 Tys = DAG.getVTList(MVT::Other);
11485 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11487 MachineMemOperand *MMO =
11488 DAG.getMachineFunction()
11489 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11490 MachineMemOperand::MOStore, SSFISize, SSFISize);
11492 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11493 Ops, Op.getValueType(), MMO);
11494 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11495 MachinePointerInfo::getFixedStack(SSFI),
11496 false, false, false, 0);
11502 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11503 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11504 SelectionDAG &DAG) const {
11505 // This algorithm is not obvious. Here it is what we're trying to output:
11508 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11509 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11511 haddpd %xmm0, %xmm0
11513 pshufd $0x4e, %xmm0, %xmm1
11519 LLVMContext *Context = DAG.getContext();
11521 // Build some magic constants.
11522 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11523 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11524 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11526 SmallVector<Constant*,2> CV1;
11528 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11529 APInt(64, 0x4330000000000000ULL))));
11531 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11532 APInt(64, 0x4530000000000000ULL))));
11533 Constant *C1 = ConstantVector::get(CV1);
11534 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11536 // Load the 64-bit value into an XMM register.
11537 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11539 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11540 MachinePointerInfo::getConstantPool(),
11541 false, false, false, 16);
11542 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11543 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11546 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11547 MachinePointerInfo::getConstantPool(),
11548 false, false, false, 16);
11549 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11550 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11553 if (Subtarget->hasSSE3()) {
11554 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11555 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11557 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11558 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11560 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11561 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11565 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11566 DAG.getIntPtrConstant(0));
11569 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11570 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11571 SelectionDAG &DAG) const {
11573 // FP constant to bias correct the final result.
11574 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11577 // Load the 32-bit value into an XMM register.
11578 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11581 // Zero out the upper parts of the register.
11582 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11584 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11585 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11586 DAG.getIntPtrConstant(0));
11588 // Or the load with the bias.
11589 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11590 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11591 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11592 MVT::v2f64, Load)),
11593 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11594 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11595 MVT::v2f64, Bias)));
11596 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11597 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11598 DAG.getIntPtrConstant(0));
11600 // Subtract the bias.
11601 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11603 // Handle final rounding.
11604 EVT DestVT = Op.getValueType();
11606 if (DestVT.bitsLT(MVT::f64))
11607 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11608 DAG.getIntPtrConstant(0));
11609 if (DestVT.bitsGT(MVT::f64))
11610 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11612 // Handle final rounding.
11616 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11617 SelectionDAG &DAG) const {
11618 SDValue N0 = Op.getOperand(0);
11619 MVT SVT = N0.getSimpleValueType();
11622 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11623 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11624 "Custom UINT_TO_FP is not supported!");
11626 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11627 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11628 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11631 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11632 SelectionDAG &DAG) const {
11633 SDValue N0 = Op.getOperand(0);
11636 if (Op.getValueType().isVector())
11637 return lowerUINT_TO_FP_vec(Op, DAG);
11639 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11640 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11641 // the optimization here.
11642 if (DAG.SignBitIsZero(N0))
11643 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11645 MVT SrcVT = N0.getSimpleValueType();
11646 MVT DstVT = Op.getSimpleValueType();
11647 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11648 return LowerUINT_TO_FP_i64(Op, DAG);
11649 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11650 return LowerUINT_TO_FP_i32(Op, DAG);
11651 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11654 // Make a 64-bit buffer, and use it to build an FILD.
11655 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11656 if (SrcVT == MVT::i32) {
11657 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11658 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11659 getPointerTy(), StackSlot, WordOff);
11660 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11661 StackSlot, MachinePointerInfo(),
11663 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11664 OffsetSlot, MachinePointerInfo(),
11666 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11670 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11671 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11672 StackSlot, MachinePointerInfo(),
11674 // For i64 source, we need to add the appropriate power of 2 if the input
11675 // was negative. This is the same as the optimization in
11676 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11677 // we must be careful to do the computation in x87 extended precision, not
11678 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11679 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11680 MachineMemOperand *MMO =
11681 DAG.getMachineFunction()
11682 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11683 MachineMemOperand::MOLoad, 8, 8);
11685 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11686 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11687 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11690 APInt FF(32, 0x5F800000ULL);
11692 // Check whether the sign bit is set.
11693 SDValue SignSet = DAG.getSetCC(dl,
11694 getSetCCResultType(*DAG.getContext(), MVT::i64),
11695 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11698 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11699 SDValue FudgePtr = DAG.getConstantPool(
11700 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11703 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11704 SDValue Zero = DAG.getIntPtrConstant(0);
11705 SDValue Four = DAG.getIntPtrConstant(4);
11706 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11708 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11710 // Load the value out, extending it from f32 to f80.
11711 // FIXME: Avoid the extend by constructing the right constant pool?
11712 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11713 FudgePtr, MachinePointerInfo::getConstantPool(),
11714 MVT::f32, false, false, false, 4);
11715 // Extend everything to 80 bits to force it to be done on x87.
11716 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11717 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11720 std::pair<SDValue,SDValue>
11721 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11722 bool IsSigned, bool IsReplace) const {
11725 EVT DstTy = Op.getValueType();
11727 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11728 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11732 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11733 DstTy.getSimpleVT() >= MVT::i16 &&
11734 "Unknown FP_TO_INT to lower!");
11736 // These are really Legal.
11737 if (DstTy == MVT::i32 &&
11738 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11739 return std::make_pair(SDValue(), SDValue());
11740 if (Subtarget->is64Bit() &&
11741 DstTy == MVT::i64 &&
11742 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11743 return std::make_pair(SDValue(), SDValue());
11745 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11746 // stack slot, or into the FTOL runtime function.
11747 MachineFunction &MF = DAG.getMachineFunction();
11748 unsigned MemSize = DstTy.getSizeInBits()/8;
11749 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11750 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11753 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11754 Opc = X86ISD::WIN_FTOL;
11756 switch (DstTy.getSimpleVT().SimpleTy) {
11757 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11758 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11759 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11760 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11763 SDValue Chain = DAG.getEntryNode();
11764 SDValue Value = Op.getOperand(0);
11765 EVT TheVT = Op.getOperand(0).getValueType();
11766 // FIXME This causes a redundant load/store if the SSE-class value is already
11767 // in memory, such as if it is on the callstack.
11768 if (isScalarFPTypeInSSEReg(TheVT)) {
11769 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11770 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11771 MachinePointerInfo::getFixedStack(SSFI),
11773 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11775 Chain, StackSlot, DAG.getValueType(TheVT)
11778 MachineMemOperand *MMO =
11779 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11780 MachineMemOperand::MOLoad, MemSize, MemSize);
11781 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11782 Chain = Value.getValue(1);
11783 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11784 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11787 MachineMemOperand *MMO =
11788 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11789 MachineMemOperand::MOStore, MemSize, MemSize);
11791 if (Opc != X86ISD::WIN_FTOL) {
11792 // Build the FP_TO_INT*_IN_MEM
11793 SDValue Ops[] = { Chain, Value, StackSlot };
11794 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11796 return std::make_pair(FIST, StackSlot);
11798 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11799 DAG.getVTList(MVT::Other, MVT::Glue),
11801 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11802 MVT::i32, ftol.getValue(1));
11803 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11804 MVT::i32, eax.getValue(2));
11805 SDValue Ops[] = { eax, edx };
11806 SDValue pair = IsReplace
11807 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11808 : DAG.getMergeValues(Ops, DL);
11809 return std::make_pair(pair, SDValue());
11813 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11814 const X86Subtarget *Subtarget) {
11815 MVT VT = Op->getSimpleValueType(0);
11816 SDValue In = Op->getOperand(0);
11817 MVT InVT = In.getSimpleValueType();
11820 // Optimize vectors in AVX mode:
11823 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11824 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11825 // Concat upper and lower parts.
11828 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11829 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11830 // Concat upper and lower parts.
11833 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11834 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11835 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11838 if (Subtarget->hasInt256())
11839 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11841 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11842 SDValue Undef = DAG.getUNDEF(InVT);
11843 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11844 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11845 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11847 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11848 VT.getVectorNumElements()/2);
11850 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11851 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11853 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11856 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11857 SelectionDAG &DAG) {
11858 MVT VT = Op->getSimpleValueType(0);
11859 SDValue In = Op->getOperand(0);
11860 MVT InVT = In.getSimpleValueType();
11862 unsigned int NumElts = VT.getVectorNumElements();
11863 if (NumElts != 8 && NumElts != 16)
11866 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11867 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11869 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11871 // Now we have only mask extension
11872 assert(InVT.getVectorElementType() == MVT::i1);
11873 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11874 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11875 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11876 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11877 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11878 MachinePointerInfo::getConstantPool(),
11879 false, false, false, Alignment);
11881 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11882 if (VT.is512BitVector())
11884 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11887 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11888 SelectionDAG &DAG) {
11889 if (Subtarget->hasFp256()) {
11890 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11898 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11899 SelectionDAG &DAG) {
11901 MVT VT = Op.getSimpleValueType();
11902 SDValue In = Op.getOperand(0);
11903 MVT SVT = In.getSimpleValueType();
11905 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11906 return LowerZERO_EXTEND_AVX512(Op, DAG);
11908 if (Subtarget->hasFp256()) {
11909 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11914 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11915 VT.getVectorNumElements() != SVT.getVectorNumElements());
11919 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11921 MVT VT = Op.getSimpleValueType();
11922 SDValue In = Op.getOperand(0);
11923 MVT InVT = In.getSimpleValueType();
11925 if (VT == MVT::i1) {
11926 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11927 "Invalid scalar TRUNCATE operation");
11928 if (InVT.getSizeInBits() >= 32)
11930 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11931 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11933 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11934 "Invalid TRUNCATE operation");
11936 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11937 if (VT.getVectorElementType().getSizeInBits() >=8)
11938 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11940 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11941 unsigned NumElts = InVT.getVectorNumElements();
11942 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11943 if (InVT.getSizeInBits() < 512) {
11944 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11945 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11949 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11950 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11951 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11952 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11953 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11954 MachinePointerInfo::getConstantPool(),
11955 false, false, false, Alignment);
11956 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11957 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11958 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11961 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11962 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11963 if (Subtarget->hasInt256()) {
11964 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11965 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11966 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11968 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11969 DAG.getIntPtrConstant(0));
11972 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11973 DAG.getIntPtrConstant(0));
11974 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11975 DAG.getIntPtrConstant(2));
11976 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11977 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11978 static const int ShufMask[] = {0, 2, 4, 6};
11979 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11982 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11983 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11984 if (Subtarget->hasInt256()) {
11985 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11987 SmallVector<SDValue,32> pshufbMask;
11988 for (unsigned i = 0; i < 2; ++i) {
11989 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11990 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11991 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11992 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11993 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11994 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11995 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11996 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11997 for (unsigned j = 0; j < 8; ++j)
11998 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12000 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12001 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12002 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12004 static const int ShufMask[] = {0, 2, -1, -1};
12005 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12007 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12008 DAG.getIntPtrConstant(0));
12009 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12012 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12013 DAG.getIntPtrConstant(0));
12015 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12016 DAG.getIntPtrConstant(4));
12018 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12019 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12021 // The PSHUFB mask:
12022 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12023 -1, -1, -1, -1, -1, -1, -1, -1};
12025 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12026 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12027 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12029 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12030 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12032 // The MOVLHPS Mask:
12033 static const int ShufMask2[] = {0, 1, 4, 5};
12034 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12035 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12038 // Handle truncation of V256 to V128 using shuffles.
12039 if (!VT.is128BitVector() || !InVT.is256BitVector())
12042 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12044 unsigned NumElems = VT.getVectorNumElements();
12045 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12047 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12048 // Prepare truncation shuffle mask
12049 for (unsigned i = 0; i != NumElems; ++i)
12050 MaskVec[i] = i * 2;
12051 SDValue V = DAG.getVectorShuffle(NVT, DL,
12052 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12053 DAG.getUNDEF(NVT), &MaskVec[0]);
12054 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12055 DAG.getIntPtrConstant(0));
12058 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12059 SelectionDAG &DAG) const {
12060 assert(!Op.getSimpleValueType().isVector());
12062 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12063 /*IsSigned=*/ true, /*IsReplace=*/ false);
12064 SDValue FIST = Vals.first, StackSlot = Vals.second;
12065 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12066 if (!FIST.getNode()) return Op;
12068 if (StackSlot.getNode())
12069 // Load the result.
12070 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12071 FIST, StackSlot, MachinePointerInfo(),
12072 false, false, false, 0);
12074 // The node is the result.
12078 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12079 SelectionDAG &DAG) const {
12080 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12081 /*IsSigned=*/ false, /*IsReplace=*/ false);
12082 SDValue FIST = Vals.first, StackSlot = Vals.second;
12083 assert(FIST.getNode() && "Unexpected failure");
12085 if (StackSlot.getNode())
12086 // Load the result.
12087 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12088 FIST, StackSlot, MachinePointerInfo(),
12089 false, false, false, 0);
12091 // The node is the result.
12095 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12097 MVT VT = Op.getSimpleValueType();
12098 SDValue In = Op.getOperand(0);
12099 MVT SVT = In.getSimpleValueType();
12101 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12103 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12104 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12105 In, DAG.getUNDEF(SVT)));
12108 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
12109 LLVMContext *Context = DAG.getContext();
12111 MVT VT = Op.getSimpleValueType();
12113 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12114 if (VT.isVector()) {
12115 EltVT = VT.getVectorElementType();
12116 NumElts = VT.getVectorNumElements();
12119 if (EltVT == MVT::f64)
12120 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12121 APInt(64, ~(1ULL << 63))));
12123 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
12124 APInt(32, ~(1U << 31))));
12125 C = ConstantVector::getSplat(NumElts, C);
12126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12127 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12128 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12129 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12130 MachinePointerInfo::getConstantPool(),
12131 false, false, false, Alignment);
12132 if (VT.isVector()) {
12133 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12134 return DAG.getNode(ISD::BITCAST, dl, VT,
12135 DAG.getNode(ISD::AND, dl, ANDVT,
12136 DAG.getNode(ISD::BITCAST, dl, ANDVT,
12138 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
12140 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
12143 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
12144 LLVMContext *Context = DAG.getContext();
12146 MVT VT = Op.getSimpleValueType();
12148 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12149 if (VT.isVector()) {
12150 EltVT = VT.getVectorElementType();
12151 NumElts = VT.getVectorNumElements();
12154 if (EltVT == MVT::f64)
12155 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12156 APInt(64, 1ULL << 63)));
12158 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
12159 APInt(32, 1U << 31)));
12160 C = ConstantVector::getSplat(NumElts, C);
12161 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12162 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12163 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12164 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12165 MachinePointerInfo::getConstantPool(),
12166 false, false, false, Alignment);
12167 if (VT.isVector()) {
12168 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
12169 return DAG.getNode(ISD::BITCAST, dl, VT,
12170 DAG.getNode(ISD::XOR, dl, XORVT,
12171 DAG.getNode(ISD::BITCAST, dl, XORVT,
12173 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
12176 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
12179 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12180 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12181 LLVMContext *Context = DAG.getContext();
12182 SDValue Op0 = Op.getOperand(0);
12183 SDValue Op1 = Op.getOperand(1);
12185 MVT VT = Op.getSimpleValueType();
12186 MVT SrcVT = Op1.getSimpleValueType();
12188 // If second operand is smaller, extend it first.
12189 if (SrcVT.bitsLT(VT)) {
12190 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12193 // And if it is bigger, shrink it first.
12194 if (SrcVT.bitsGT(VT)) {
12195 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12199 // At this point the operands and the result should have the same
12200 // type, and that won't be f80 since that is not custom lowered.
12202 // First get the sign bit of second operand.
12203 SmallVector<Constant*,4> CV;
12204 if (SrcVT == MVT::f64) {
12205 const fltSemantics &Sem = APFloat::IEEEdouble;
12206 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12207 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12209 const fltSemantics &Sem = APFloat::IEEEsingle;
12210 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12211 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12212 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12213 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12215 Constant *C = ConstantVector::get(CV);
12216 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12217 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12218 MachinePointerInfo::getConstantPool(),
12219 false, false, false, 16);
12220 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12222 // Shift sign bit right or left if the two operands have different types.
12223 if (SrcVT.bitsGT(VT)) {
12224 // Op0 is MVT::f32, Op1 is MVT::f64.
12225 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12226 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12227 DAG.getConstant(32, MVT::i32));
12228 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12229 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12230 DAG.getIntPtrConstant(0));
12233 // Clear first operand sign bit.
12235 if (VT == MVT::f64) {
12236 const fltSemantics &Sem = APFloat::IEEEdouble;
12237 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12238 APInt(64, ~(1ULL << 63)))));
12239 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12241 const fltSemantics &Sem = APFloat::IEEEsingle;
12242 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12243 APInt(32, ~(1U << 31)))));
12244 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12245 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12246 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12248 C = ConstantVector::get(CV);
12249 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12250 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12251 MachinePointerInfo::getConstantPool(),
12252 false, false, false, 16);
12253 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12255 // Or the value with the sign bit.
12256 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12259 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12260 SDValue N0 = Op.getOperand(0);
12262 MVT VT = Op.getSimpleValueType();
12264 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12265 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12266 DAG.getConstant(1, VT));
12267 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12270 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
12272 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12273 SelectionDAG &DAG) {
12274 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12276 if (!Subtarget->hasSSE41())
12279 if (!Op->hasOneUse())
12282 SDNode *N = Op.getNode();
12285 SmallVector<SDValue, 8> Opnds;
12286 DenseMap<SDValue, unsigned> VecInMap;
12287 SmallVector<SDValue, 8> VecIns;
12288 EVT VT = MVT::Other;
12290 // Recognize a special case where a vector is casted into wide integer to
12292 Opnds.push_back(N->getOperand(0));
12293 Opnds.push_back(N->getOperand(1));
12295 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12296 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12297 // BFS traverse all OR'd operands.
12298 if (I->getOpcode() == ISD::OR) {
12299 Opnds.push_back(I->getOperand(0));
12300 Opnds.push_back(I->getOperand(1));
12301 // Re-evaluate the number of nodes to be traversed.
12302 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12306 // Quit if a non-EXTRACT_VECTOR_ELT
12307 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12310 // Quit if without a constant index.
12311 SDValue Idx = I->getOperand(1);
12312 if (!isa<ConstantSDNode>(Idx))
12315 SDValue ExtractedFromVec = I->getOperand(0);
12316 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12317 if (M == VecInMap.end()) {
12318 VT = ExtractedFromVec.getValueType();
12319 // Quit if not 128/256-bit vector.
12320 if (!VT.is128BitVector() && !VT.is256BitVector())
12322 // Quit if not the same type.
12323 if (VecInMap.begin() != VecInMap.end() &&
12324 VT != VecInMap.begin()->first.getValueType())
12326 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12327 VecIns.push_back(ExtractedFromVec);
12329 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12332 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12333 "Not extracted from 128-/256-bit vector.");
12335 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12337 for (DenseMap<SDValue, unsigned>::const_iterator
12338 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12339 // Quit if not all elements are used.
12340 if (I->second != FullMask)
12344 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12346 // Cast all vectors into TestVT for PTEST.
12347 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12348 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12350 // If more than one full vectors are evaluated, OR them first before PTEST.
12351 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12352 // Each iteration will OR 2 nodes and append the result until there is only
12353 // 1 node left, i.e. the final OR'd value of all vectors.
12354 SDValue LHS = VecIns[Slot];
12355 SDValue RHS = VecIns[Slot + 1];
12356 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12359 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12360 VecIns.back(), VecIns.back());
12363 /// \brief return true if \c Op has a use that doesn't just read flags.
12364 static bool hasNonFlagsUse(SDValue Op) {
12365 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12367 SDNode *User = *UI;
12368 unsigned UOpNo = UI.getOperandNo();
12369 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12370 // Look pass truncate.
12371 UOpNo = User->use_begin().getOperandNo();
12372 User = *User->use_begin();
12375 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12376 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12382 /// Emit nodes that will be selected as "test Op0,Op0", or something
12384 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12385 SelectionDAG &DAG) const {
12386 if (Op.getValueType() == MVT::i1)
12387 // KORTEST instruction should be selected
12388 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12389 DAG.getConstant(0, Op.getValueType()));
12391 // CF and OF aren't always set the way we want. Determine which
12392 // of these we need.
12393 bool NeedCF = false;
12394 bool NeedOF = false;
12397 case X86::COND_A: case X86::COND_AE:
12398 case X86::COND_B: case X86::COND_BE:
12401 case X86::COND_G: case X86::COND_GE:
12402 case X86::COND_L: case X86::COND_LE:
12403 case X86::COND_O: case X86::COND_NO: {
12404 // Check if we really need to set the
12405 // Overflow flag. If NoSignedWrap is present
12406 // that is not actually needed.
12407 switch (Op->getOpcode()) {
12412 const BinaryWithFlagsSDNode *BinNode =
12413 cast<BinaryWithFlagsSDNode>(Op.getNode());
12414 if (BinNode->hasNoSignedWrap())
12424 // See if we can use the EFLAGS value from the operand instead of
12425 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12426 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12427 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12428 // Emit a CMP with 0, which is the TEST pattern.
12429 //if (Op.getValueType() == MVT::i1)
12430 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12431 // DAG.getConstant(0, MVT::i1));
12432 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12433 DAG.getConstant(0, Op.getValueType()));
12435 unsigned Opcode = 0;
12436 unsigned NumOperands = 0;
12438 // Truncate operations may prevent the merge of the SETCC instruction
12439 // and the arithmetic instruction before it. Attempt to truncate the operands
12440 // of the arithmetic instruction and use a reduced bit-width instruction.
12441 bool NeedTruncation = false;
12442 SDValue ArithOp = Op;
12443 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12444 SDValue Arith = Op->getOperand(0);
12445 // Both the trunc and the arithmetic op need to have one user each.
12446 if (Arith->hasOneUse())
12447 switch (Arith.getOpcode()) {
12454 NeedTruncation = true;
12460 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12461 // which may be the result of a CAST. We use the variable 'Op', which is the
12462 // non-casted variable when we check for possible users.
12463 switch (ArithOp.getOpcode()) {
12465 // Due to an isel shortcoming, be conservative if this add is likely to be
12466 // selected as part of a load-modify-store instruction. When the root node
12467 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12468 // uses of other nodes in the match, such as the ADD in this case. This
12469 // leads to the ADD being left around and reselected, with the result being
12470 // two adds in the output. Alas, even if none our users are stores, that
12471 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12472 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12473 // climbing the DAG back to the root, and it doesn't seem to be worth the
12475 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12476 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12477 if (UI->getOpcode() != ISD::CopyToReg &&
12478 UI->getOpcode() != ISD::SETCC &&
12479 UI->getOpcode() != ISD::STORE)
12482 if (ConstantSDNode *C =
12483 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12484 // An add of one will be selected as an INC.
12485 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12486 Opcode = X86ISD::INC;
12491 // An add of negative one (subtract of one) will be selected as a DEC.
12492 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12493 Opcode = X86ISD::DEC;
12499 // Otherwise use a regular EFLAGS-setting add.
12500 Opcode = X86ISD::ADD;
12505 // If we have a constant logical shift that's only used in a comparison
12506 // against zero turn it into an equivalent AND. This allows turning it into
12507 // a TEST instruction later.
12508 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12509 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12510 EVT VT = Op.getValueType();
12511 unsigned BitWidth = VT.getSizeInBits();
12512 unsigned ShAmt = Op->getConstantOperandVal(1);
12513 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12515 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12516 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12517 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12518 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12520 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12521 DAG.getConstant(Mask, VT));
12522 DAG.ReplaceAllUsesWith(Op, New);
12528 // If the primary and result isn't used, don't bother using X86ISD::AND,
12529 // because a TEST instruction will be better.
12530 if (!hasNonFlagsUse(Op))
12536 // Due to the ISEL shortcoming noted above, be conservative if this op is
12537 // likely to be selected as part of a load-modify-store instruction.
12538 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12539 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12540 if (UI->getOpcode() == ISD::STORE)
12543 // Otherwise use a regular EFLAGS-setting instruction.
12544 switch (ArithOp.getOpcode()) {
12545 default: llvm_unreachable("unexpected operator!");
12546 case ISD::SUB: Opcode = X86ISD::SUB; break;
12547 case ISD::XOR: Opcode = X86ISD::XOR; break;
12548 case ISD::AND: Opcode = X86ISD::AND; break;
12550 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12551 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12552 if (EFLAGS.getNode())
12555 Opcode = X86ISD::OR;
12569 return SDValue(Op.getNode(), 1);
12575 // If we found that truncation is beneficial, perform the truncation and
12577 if (NeedTruncation) {
12578 EVT VT = Op.getValueType();
12579 SDValue WideVal = Op->getOperand(0);
12580 EVT WideVT = WideVal.getValueType();
12581 unsigned ConvertedOp = 0;
12582 // Use a target machine opcode to prevent further DAGCombine
12583 // optimizations that may separate the arithmetic operations
12584 // from the setcc node.
12585 switch (WideVal.getOpcode()) {
12587 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12588 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12589 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12590 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12591 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12595 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12596 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12597 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12598 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12599 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12605 // Emit a CMP with 0, which is the TEST pattern.
12606 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12607 DAG.getConstant(0, Op.getValueType()));
12609 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12610 SmallVector<SDValue, 4> Ops;
12611 for (unsigned i = 0; i != NumOperands; ++i)
12612 Ops.push_back(Op.getOperand(i));
12614 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12615 DAG.ReplaceAllUsesWith(Op, New);
12616 return SDValue(New.getNode(), 1);
12619 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12621 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12622 SDLoc dl, SelectionDAG &DAG) const {
12623 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12624 if (C->getAPIntValue() == 0)
12625 return EmitTest(Op0, X86CC, dl, DAG);
12627 if (Op0.getValueType() == MVT::i1)
12628 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12631 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12632 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12633 // Do the comparison at i32 if it's smaller, besides the Atom case.
12634 // This avoids subregister aliasing issues. Keep the smaller reference
12635 // if we're optimizing for size, however, as that'll allow better folding
12636 // of memory operations.
12637 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12638 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12639 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12640 !Subtarget->isAtom()) {
12641 unsigned ExtendOp =
12642 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12643 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12644 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12646 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12647 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12648 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12650 return SDValue(Sub.getNode(), 1);
12652 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12655 /// Convert a comparison if required by the subtarget.
12656 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12657 SelectionDAG &DAG) const {
12658 // If the subtarget does not support the FUCOMI instruction, floating-point
12659 // comparisons have to be converted.
12660 if (Subtarget->hasCMov() ||
12661 Cmp.getOpcode() != X86ISD::CMP ||
12662 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12663 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12666 // The instruction selector will select an FUCOM instruction instead of
12667 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12668 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12669 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12671 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12672 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12673 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12674 DAG.getConstant(8, MVT::i8));
12675 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12676 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12679 static bool isAllOnes(SDValue V) {
12680 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12681 return C && C->isAllOnesValue();
12684 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12685 /// if it's possible.
12686 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12687 SDLoc dl, SelectionDAG &DAG) const {
12688 SDValue Op0 = And.getOperand(0);
12689 SDValue Op1 = And.getOperand(1);
12690 if (Op0.getOpcode() == ISD::TRUNCATE)
12691 Op0 = Op0.getOperand(0);
12692 if (Op1.getOpcode() == ISD::TRUNCATE)
12693 Op1 = Op1.getOperand(0);
12696 if (Op1.getOpcode() == ISD::SHL)
12697 std::swap(Op0, Op1);
12698 if (Op0.getOpcode() == ISD::SHL) {
12699 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12700 if (And00C->getZExtValue() == 1) {
12701 // If we looked past a truncate, check that it's only truncating away
12703 unsigned BitWidth = Op0.getValueSizeInBits();
12704 unsigned AndBitWidth = And.getValueSizeInBits();
12705 if (BitWidth > AndBitWidth) {
12707 DAG.computeKnownBits(Op0, Zeros, Ones);
12708 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12712 RHS = Op0.getOperand(1);
12714 } else if (Op1.getOpcode() == ISD::Constant) {
12715 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12716 uint64_t AndRHSVal = AndRHS->getZExtValue();
12717 SDValue AndLHS = Op0;
12719 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12720 LHS = AndLHS.getOperand(0);
12721 RHS = AndLHS.getOperand(1);
12724 // Use BT if the immediate can't be encoded in a TEST instruction.
12725 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12727 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12731 if (LHS.getNode()) {
12732 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12733 // instruction. Since the shift amount is in-range-or-undefined, we know
12734 // that doing a bittest on the i32 value is ok. We extend to i32 because
12735 // the encoding for the i16 version is larger than the i32 version.
12736 // Also promote i16 to i32 for performance / code size reason.
12737 if (LHS.getValueType() == MVT::i8 ||
12738 LHS.getValueType() == MVT::i16)
12739 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12741 // If the operand types disagree, extend the shift amount to match. Since
12742 // BT ignores high bits (like shifts) we can use anyextend.
12743 if (LHS.getValueType() != RHS.getValueType())
12744 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12746 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12747 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12748 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12749 DAG.getConstant(Cond, MVT::i8), BT);
12755 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12757 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12762 // SSE Condition code mapping:
12771 switch (SetCCOpcode) {
12772 default: llvm_unreachable("Unexpected SETCC condition");
12774 case ISD::SETEQ: SSECC = 0; break;
12776 case ISD::SETGT: Swap = true; // Fallthrough
12778 case ISD::SETOLT: SSECC = 1; break;
12780 case ISD::SETGE: Swap = true; // Fallthrough
12782 case ISD::SETOLE: SSECC = 2; break;
12783 case ISD::SETUO: SSECC = 3; break;
12785 case ISD::SETNE: SSECC = 4; break;
12786 case ISD::SETULE: Swap = true; // Fallthrough
12787 case ISD::SETUGE: SSECC = 5; break;
12788 case ISD::SETULT: Swap = true; // Fallthrough
12789 case ISD::SETUGT: SSECC = 6; break;
12790 case ISD::SETO: SSECC = 7; break;
12792 case ISD::SETONE: SSECC = 8; break;
12795 std::swap(Op0, Op1);
12800 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12801 // ones, and then concatenate the result back.
12802 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12803 MVT VT = Op.getSimpleValueType();
12805 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12806 "Unsupported value type for operation");
12808 unsigned NumElems = VT.getVectorNumElements();
12810 SDValue CC = Op.getOperand(2);
12812 // Extract the LHS vectors
12813 SDValue LHS = Op.getOperand(0);
12814 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12815 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12817 // Extract the RHS vectors
12818 SDValue RHS = Op.getOperand(1);
12819 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12820 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12822 // Issue the operation on the smaller types and concatenate the result back
12823 MVT EltVT = VT.getVectorElementType();
12824 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12825 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12826 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12827 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12830 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12831 const X86Subtarget *Subtarget) {
12832 SDValue Op0 = Op.getOperand(0);
12833 SDValue Op1 = Op.getOperand(1);
12834 SDValue CC = Op.getOperand(2);
12835 MVT VT = Op.getSimpleValueType();
12838 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12839 Op.getValueType().getScalarType() == MVT::i1 &&
12840 "Cannot set masked compare for this operation");
12842 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12844 bool Unsigned = false;
12847 switch (SetCCOpcode) {
12848 default: llvm_unreachable("Unexpected SETCC condition");
12849 case ISD::SETNE: SSECC = 4; break;
12850 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12851 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12852 case ISD::SETLT: Swap = true; //fall-through
12853 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12854 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12855 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12856 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12857 case ISD::SETULE: Unsigned = true; //fall-through
12858 case ISD::SETLE: SSECC = 2; break;
12862 std::swap(Op0, Op1);
12864 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12865 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12866 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12867 DAG.getConstant(SSECC, MVT::i8));
12870 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12871 /// operand \p Op1. If non-trivial (for example because it's not constant)
12872 /// return an empty value.
12873 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12875 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12879 MVT VT = Op1.getSimpleValueType();
12880 MVT EVT = VT.getVectorElementType();
12881 unsigned n = VT.getVectorNumElements();
12882 SmallVector<SDValue, 8> ULTOp1;
12884 for (unsigned i = 0; i < n; ++i) {
12885 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12886 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12889 // Avoid underflow.
12890 APInt Val = Elt->getAPIntValue();
12894 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12897 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12900 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12901 SelectionDAG &DAG) {
12902 SDValue Op0 = Op.getOperand(0);
12903 SDValue Op1 = Op.getOperand(1);
12904 SDValue CC = Op.getOperand(2);
12905 MVT VT = Op.getSimpleValueType();
12906 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12907 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12912 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12913 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12916 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12917 unsigned Opc = X86ISD::CMPP;
12918 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12919 assert(VT.getVectorNumElements() <= 16);
12920 Opc = X86ISD::CMPM;
12922 // In the two special cases we can't handle, emit two comparisons.
12925 unsigned CombineOpc;
12926 if (SetCCOpcode == ISD::SETUEQ) {
12927 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12929 assert(SetCCOpcode == ISD::SETONE);
12930 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12933 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12934 DAG.getConstant(CC0, MVT::i8));
12935 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12936 DAG.getConstant(CC1, MVT::i8));
12937 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12939 // Handle all other FP comparisons here.
12940 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12941 DAG.getConstant(SSECC, MVT::i8));
12944 // Break 256-bit integer vector compare into smaller ones.
12945 if (VT.is256BitVector() && !Subtarget->hasInt256())
12946 return Lower256IntVSETCC(Op, DAG);
12948 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12949 EVT OpVT = Op1.getValueType();
12950 if (Subtarget->hasAVX512()) {
12951 if (Op1.getValueType().is512BitVector() ||
12952 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12953 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12955 // In AVX-512 architecture setcc returns mask with i1 elements,
12956 // But there is no compare instruction for i8 and i16 elements.
12957 // We are not talking about 512-bit operands in this case, these
12958 // types are illegal.
12960 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12961 OpVT.getVectorElementType().getSizeInBits() >= 8))
12962 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12963 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12966 // We are handling one of the integer comparisons here. Since SSE only has
12967 // GT and EQ comparisons for integer, swapping operands and multiple
12968 // operations may be required for some comparisons.
12970 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12971 bool Subus = false;
12973 switch (SetCCOpcode) {
12974 default: llvm_unreachable("Unexpected SETCC condition");
12975 case ISD::SETNE: Invert = true;
12976 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12977 case ISD::SETLT: Swap = true;
12978 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12979 case ISD::SETGE: Swap = true;
12980 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12981 Invert = true; break;
12982 case ISD::SETULT: Swap = true;
12983 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12984 FlipSigns = true; break;
12985 case ISD::SETUGE: Swap = true;
12986 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12987 FlipSigns = true; Invert = true; break;
12990 // Special case: Use min/max operations for SETULE/SETUGE
12991 MVT VET = VT.getVectorElementType();
12993 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12994 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12997 switch (SetCCOpcode) {
12999 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13000 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13003 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13006 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13007 if (!MinMax && hasSubus) {
13008 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13010 // t = psubus Op0, Op1
13011 // pcmpeq t, <0..0>
13012 switch (SetCCOpcode) {
13014 case ISD::SETULT: {
13015 // If the comparison is against a constant we can turn this into a
13016 // setule. With psubus, setule does not require a swap. This is
13017 // beneficial because the constant in the register is no longer
13018 // destructed as the destination so it can be hoisted out of a loop.
13019 // Only do this pre-AVX since vpcmp* is no longer destructive.
13020 if (Subtarget->hasAVX())
13022 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13023 if (ULEOp1.getNode()) {
13025 Subus = true; Invert = false; Swap = false;
13029 // Psubus is better than flip-sign because it requires no inversion.
13030 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13031 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13035 Opc = X86ISD::SUBUS;
13041 std::swap(Op0, Op1);
13043 // Check that the operation in question is available (most are plain SSE2,
13044 // but PCMPGTQ and PCMPEQQ have different requirements).
13045 if (VT == MVT::v2i64) {
13046 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13047 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13049 // First cast everything to the right type.
13050 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13051 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13053 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13054 // bits of the inputs before performing those operations. The lower
13055 // compare is always unsigned.
13058 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13060 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13061 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13062 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13063 Sign, Zero, Sign, Zero);
13065 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13066 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13068 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13069 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13070 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13072 // Create masks for only the low parts/high parts of the 64 bit integers.
13073 static const int MaskHi[] = { 1, 1, 3, 3 };
13074 static const int MaskLo[] = { 0, 0, 2, 2 };
13075 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13076 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13077 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13079 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13080 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13083 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13085 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13088 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13089 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13090 // pcmpeqd + pshufd + pand.
13091 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13093 // First cast everything to the right type.
13094 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13095 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13098 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13100 // Make sure the lower and upper halves are both all-ones.
13101 static const int Mask[] = { 1, 0, 3, 2 };
13102 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13103 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13106 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13108 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13112 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13113 // bits of the inputs before performing those operations.
13115 EVT EltVT = VT.getVectorElementType();
13116 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13117 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13118 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13121 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13123 // If the logical-not of the result is required, perform that now.
13125 Result = DAG.getNOT(dl, Result, VT);
13128 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13131 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13132 getZeroVector(VT, Subtarget, DAG, dl));
13137 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13139 MVT VT = Op.getSimpleValueType();
13141 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13143 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13144 && "SetCC type must be 8-bit or 1-bit integer");
13145 SDValue Op0 = Op.getOperand(0);
13146 SDValue Op1 = Op.getOperand(1);
13148 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13150 // Optimize to BT if possible.
13151 // Lower (X & (1 << N)) == 0 to BT(X, N).
13152 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13153 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13154 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13155 Op1.getOpcode() == ISD::Constant &&
13156 cast<ConstantSDNode>(Op1)->isNullValue() &&
13157 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13158 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13159 if (NewSetCC.getNode())
13163 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13165 if (Op1.getOpcode() == ISD::Constant &&
13166 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13167 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13168 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13170 // If the input is a setcc, then reuse the input setcc or use a new one with
13171 // the inverted condition.
13172 if (Op0.getOpcode() == X86ISD::SETCC) {
13173 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13174 bool Invert = (CC == ISD::SETNE) ^
13175 cast<ConstantSDNode>(Op1)->isNullValue();
13179 CCode = X86::GetOppositeBranchCondition(CCode);
13180 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13181 DAG.getConstant(CCode, MVT::i8),
13182 Op0.getOperand(1));
13184 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13188 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13189 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13190 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13192 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13193 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13196 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13197 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13198 if (X86CC == X86::COND_INVALID)
13201 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13202 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13203 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13204 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13206 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13210 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13211 static bool isX86LogicalCmp(SDValue Op) {
13212 unsigned Opc = Op.getNode()->getOpcode();
13213 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13214 Opc == X86ISD::SAHF)
13216 if (Op.getResNo() == 1 &&
13217 (Opc == X86ISD::ADD ||
13218 Opc == X86ISD::SUB ||
13219 Opc == X86ISD::ADC ||
13220 Opc == X86ISD::SBB ||
13221 Opc == X86ISD::SMUL ||
13222 Opc == X86ISD::UMUL ||
13223 Opc == X86ISD::INC ||
13224 Opc == X86ISD::DEC ||
13225 Opc == X86ISD::OR ||
13226 Opc == X86ISD::XOR ||
13227 Opc == X86ISD::AND))
13230 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13236 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13237 if (V.getOpcode() != ISD::TRUNCATE)
13240 SDValue VOp0 = V.getOperand(0);
13241 unsigned InBits = VOp0.getValueSizeInBits();
13242 unsigned Bits = V.getValueSizeInBits();
13243 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13246 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13247 bool addTest = true;
13248 SDValue Cond = Op.getOperand(0);
13249 SDValue Op1 = Op.getOperand(1);
13250 SDValue Op2 = Op.getOperand(2);
13252 EVT VT = Op1.getValueType();
13255 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13256 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13257 // sequence later on.
13258 if (Cond.getOpcode() == ISD::SETCC &&
13259 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13260 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13261 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13262 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13263 int SSECC = translateX86FSETCC(
13264 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13267 if (Subtarget->hasAVX512()) {
13268 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13269 DAG.getConstant(SSECC, MVT::i8));
13270 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13272 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13273 DAG.getConstant(SSECC, MVT::i8));
13274 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13275 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13276 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13280 if (Cond.getOpcode() == ISD::SETCC) {
13281 SDValue NewCond = LowerSETCC(Cond, DAG);
13282 if (NewCond.getNode())
13286 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13287 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13288 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13289 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13290 if (Cond.getOpcode() == X86ISD::SETCC &&
13291 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13292 isZero(Cond.getOperand(1).getOperand(1))) {
13293 SDValue Cmp = Cond.getOperand(1);
13295 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13297 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13298 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13299 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13301 SDValue CmpOp0 = Cmp.getOperand(0);
13302 // Apply further optimizations for special cases
13303 // (select (x != 0), -1, 0) -> neg & sbb
13304 // (select (x == 0), 0, -1) -> neg & sbb
13305 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13306 if (YC->isNullValue() &&
13307 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13308 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13309 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13310 DAG.getConstant(0, CmpOp0.getValueType()),
13312 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13313 DAG.getConstant(X86::COND_B, MVT::i8),
13314 SDValue(Neg.getNode(), 1));
13318 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13319 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13320 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13322 SDValue Res = // Res = 0 or -1.
13323 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13324 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13326 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13327 Res = DAG.getNOT(DL, Res, Res.getValueType());
13329 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13330 if (!N2C || !N2C->isNullValue())
13331 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13336 // Look past (and (setcc_carry (cmp ...)), 1).
13337 if (Cond.getOpcode() == ISD::AND &&
13338 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13339 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13340 if (C && C->getAPIntValue() == 1)
13341 Cond = Cond.getOperand(0);
13344 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13345 // setting operand in place of the X86ISD::SETCC.
13346 unsigned CondOpcode = Cond.getOpcode();
13347 if (CondOpcode == X86ISD::SETCC ||
13348 CondOpcode == X86ISD::SETCC_CARRY) {
13349 CC = Cond.getOperand(0);
13351 SDValue Cmp = Cond.getOperand(1);
13352 unsigned Opc = Cmp.getOpcode();
13353 MVT VT = Op.getSimpleValueType();
13355 bool IllegalFPCMov = false;
13356 if (VT.isFloatingPoint() && !VT.isVector() &&
13357 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13358 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13360 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13361 Opc == X86ISD::BT) { // FIXME
13365 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13366 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13367 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13368 Cond.getOperand(0).getValueType() != MVT::i8)) {
13369 SDValue LHS = Cond.getOperand(0);
13370 SDValue RHS = Cond.getOperand(1);
13371 unsigned X86Opcode;
13374 switch (CondOpcode) {
13375 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13376 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13377 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13378 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13379 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13380 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13381 default: llvm_unreachable("unexpected overflowing operator");
13383 if (CondOpcode == ISD::UMULO)
13384 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13387 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13389 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13391 if (CondOpcode == ISD::UMULO)
13392 Cond = X86Op.getValue(2);
13394 Cond = X86Op.getValue(1);
13396 CC = DAG.getConstant(X86Cond, MVT::i8);
13401 // Look pass the truncate if the high bits are known zero.
13402 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13403 Cond = Cond.getOperand(0);
13405 // We know the result of AND is compared against zero. Try to match
13407 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13408 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13409 if (NewSetCC.getNode()) {
13410 CC = NewSetCC.getOperand(0);
13411 Cond = NewSetCC.getOperand(1);
13418 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13419 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13422 // a < b ? -1 : 0 -> RES = ~setcc_carry
13423 // a < b ? 0 : -1 -> RES = setcc_carry
13424 // a >= b ? -1 : 0 -> RES = setcc_carry
13425 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13426 if (Cond.getOpcode() == X86ISD::SUB) {
13427 Cond = ConvertCmpIfNecessary(Cond, DAG);
13428 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13430 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13431 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13432 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13433 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13434 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13435 return DAG.getNOT(DL, Res, Res.getValueType());
13440 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13441 // widen the cmov and push the truncate through. This avoids introducing a new
13442 // branch during isel and doesn't add any extensions.
13443 if (Op.getValueType() == MVT::i8 &&
13444 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13445 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13446 if (T1.getValueType() == T2.getValueType() &&
13447 // Blacklist CopyFromReg to avoid partial register stalls.
13448 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13449 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13450 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13451 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13455 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13456 // condition is true.
13457 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13458 SDValue Ops[] = { Op2, Op1, CC, Cond };
13459 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13462 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
13463 MVT VT = Op->getSimpleValueType(0);
13464 SDValue In = Op->getOperand(0);
13465 MVT InVT = In.getSimpleValueType();
13468 unsigned int NumElts = VT.getVectorNumElements();
13469 if (NumElts != 8 && NumElts != 16)
13472 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13473 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13476 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13478 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13479 Constant *C = ConstantInt::get(*DAG.getContext(),
13480 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13482 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13483 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13484 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13485 MachinePointerInfo::getConstantPool(),
13486 false, false, false, Alignment);
13487 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13488 if (VT.is512BitVector())
13490 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13493 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13494 SelectionDAG &DAG) {
13495 MVT VT = Op->getSimpleValueType(0);
13496 SDValue In = Op->getOperand(0);
13497 MVT InVT = In.getSimpleValueType();
13500 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13501 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13503 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13504 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13505 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13508 if (Subtarget->hasInt256())
13509 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13511 // Optimize vectors in AVX mode
13512 // Sign extend v8i16 to v8i32 and
13515 // Divide input vector into two parts
13516 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13517 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13518 // concat the vectors to original VT
13520 unsigned NumElems = InVT.getVectorNumElements();
13521 SDValue Undef = DAG.getUNDEF(InVT);
13523 SmallVector<int,8> ShufMask1(NumElems, -1);
13524 for (unsigned i = 0; i != NumElems/2; ++i)
13527 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13529 SmallVector<int,8> ShufMask2(NumElems, -1);
13530 for (unsigned i = 0; i != NumElems/2; ++i)
13531 ShufMask2[i] = i + NumElems/2;
13533 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13535 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13536 VT.getVectorNumElements()/2);
13538 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13539 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13541 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13544 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13545 // may emit an illegal shuffle but the expansion is still better than scalar
13546 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13547 // we'll emit a shuffle and a arithmetic shift.
13548 // TODO: It is possible to support ZExt by zeroing the undef values during
13549 // the shuffle phase or after the shuffle.
13550 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13551 SelectionDAG &DAG) {
13552 MVT RegVT = Op.getSimpleValueType();
13553 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13554 assert(RegVT.isInteger() &&
13555 "We only custom lower integer vector sext loads.");
13557 // Nothing useful we can do without SSE2 shuffles.
13558 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13560 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13562 EVT MemVT = Ld->getMemoryVT();
13563 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13564 unsigned RegSz = RegVT.getSizeInBits();
13566 ISD::LoadExtType Ext = Ld->getExtensionType();
13568 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13569 && "Only anyext and sext are currently implemented.");
13570 assert(MemVT != RegVT && "Cannot extend to the same type");
13571 assert(MemVT.isVector() && "Must load a vector from memory");
13573 unsigned NumElems = RegVT.getVectorNumElements();
13574 unsigned MemSz = MemVT.getSizeInBits();
13575 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13577 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13578 // The only way in which we have a legal 256-bit vector result but not the
13579 // integer 256-bit operations needed to directly lower a sextload is if we
13580 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13581 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13582 // correctly legalized. We do this late to allow the canonical form of
13583 // sextload to persist throughout the rest of the DAG combiner -- it wants
13584 // to fold together any extensions it can, and so will fuse a sign_extend
13585 // of an sextload into a sextload targeting a wider value.
13587 if (MemSz == 128) {
13588 // Just switch this to a normal load.
13589 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13590 "it must be a legal 128-bit vector "
13592 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13593 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13594 Ld->isInvariant(), Ld->getAlignment());
13596 assert(MemSz < 128 &&
13597 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13598 // Do an sext load to a 128-bit vector type. We want to use the same
13599 // number of elements, but elements half as wide. This will end up being
13600 // recursively lowered by this routine, but will succeed as we definitely
13601 // have all the necessary features if we're using AVX1.
13603 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13604 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13606 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13607 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13608 Ld->isNonTemporal(), Ld->isInvariant(),
13609 Ld->getAlignment());
13612 // Replace chain users with the new chain.
13613 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13614 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13616 // Finally, do a normal sign-extend to the desired register.
13617 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13620 // All sizes must be a power of two.
13621 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13622 "Non-power-of-two elements are not custom lowered!");
13624 // Attempt to load the original value using scalar loads.
13625 // Find the largest scalar type that divides the total loaded size.
13626 MVT SclrLoadTy = MVT::i8;
13627 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13628 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13629 MVT Tp = (MVT::SimpleValueType)tp;
13630 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13635 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13636 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13638 SclrLoadTy = MVT::f64;
13640 // Calculate the number of scalar loads that we need to perform
13641 // in order to load our vector from memory.
13642 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13644 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13645 "Can only lower sext loads with a single scalar load!");
13647 unsigned loadRegZize = RegSz;
13648 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13651 // Represent our vector as a sequence of elements which are the
13652 // largest scalar that we can load.
13653 EVT LoadUnitVecVT = EVT::getVectorVT(
13654 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13656 // Represent the data using the same element type that is stored in
13657 // memory. In practice, we ''widen'' MemVT.
13659 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13660 loadRegZize / MemVT.getScalarType().getSizeInBits());
13662 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13663 "Invalid vector type");
13665 // We can't shuffle using an illegal type.
13666 assert(TLI.isTypeLegal(WideVecVT) &&
13667 "We only lower types that form legal widened vector types");
13669 SmallVector<SDValue, 8> Chains;
13670 SDValue Ptr = Ld->getBasePtr();
13671 SDValue Increment =
13672 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13673 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13675 for (unsigned i = 0; i < NumLoads; ++i) {
13676 // Perform a single load.
13677 SDValue ScalarLoad =
13678 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13679 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13680 Ld->getAlignment());
13681 Chains.push_back(ScalarLoad.getValue(1));
13682 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13683 // another round of DAGCombining.
13685 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13687 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13688 ScalarLoad, DAG.getIntPtrConstant(i));
13690 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13693 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13695 // Bitcast the loaded value to a vector of the original element type, in
13696 // the size of the target vector type.
13697 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13698 unsigned SizeRatio = RegSz / MemSz;
13700 if (Ext == ISD::SEXTLOAD) {
13701 // If we have SSE4.1, we can directly emit a VSEXT node.
13702 if (Subtarget->hasSSE41()) {
13703 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13704 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13708 // Otherwise we'll shuffle the small elements in the high bits of the
13709 // larger type and perform an arithmetic shift. If the shift is not legal
13710 // it's better to scalarize.
13711 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13712 "We can't implement a sext load without an arithmetic right shift!");
13714 // Redistribute the loaded elements into the different locations.
13715 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13716 for (unsigned i = 0; i != NumElems; ++i)
13717 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13719 SDValue Shuff = DAG.getVectorShuffle(
13720 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13722 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13724 // Build the arithmetic shift.
13725 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13726 MemVT.getVectorElementType().getSizeInBits();
13728 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13730 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13734 // Redistribute the loaded elements into the different locations.
13735 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13736 for (unsigned i = 0; i != NumElems; ++i)
13737 ShuffleVec[i * SizeRatio] = i;
13739 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13740 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13742 // Bitcast to the requested type.
13743 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13744 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13748 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13749 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13750 // from the AND / OR.
13751 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13752 Opc = Op.getOpcode();
13753 if (Opc != ISD::OR && Opc != ISD::AND)
13755 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13756 Op.getOperand(0).hasOneUse() &&
13757 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13758 Op.getOperand(1).hasOneUse());
13761 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13762 // 1 and that the SETCC node has a single use.
13763 static bool isXor1OfSetCC(SDValue Op) {
13764 if (Op.getOpcode() != ISD::XOR)
13766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13767 if (N1C && N1C->getAPIntValue() == 1) {
13768 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13769 Op.getOperand(0).hasOneUse();
13774 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13775 bool addTest = true;
13776 SDValue Chain = Op.getOperand(0);
13777 SDValue Cond = Op.getOperand(1);
13778 SDValue Dest = Op.getOperand(2);
13781 bool Inverted = false;
13783 if (Cond.getOpcode() == ISD::SETCC) {
13784 // Check for setcc([su]{add,sub,mul}o == 0).
13785 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13786 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13787 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13788 Cond.getOperand(0).getResNo() == 1 &&
13789 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13790 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13791 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13792 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13793 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13794 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13796 Cond = Cond.getOperand(0);
13798 SDValue NewCond = LowerSETCC(Cond, DAG);
13799 if (NewCond.getNode())
13804 // FIXME: LowerXALUO doesn't handle these!!
13805 else if (Cond.getOpcode() == X86ISD::ADD ||
13806 Cond.getOpcode() == X86ISD::SUB ||
13807 Cond.getOpcode() == X86ISD::SMUL ||
13808 Cond.getOpcode() == X86ISD::UMUL)
13809 Cond = LowerXALUO(Cond, DAG);
13812 // Look pass (and (setcc_carry (cmp ...)), 1).
13813 if (Cond.getOpcode() == ISD::AND &&
13814 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13815 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13816 if (C && C->getAPIntValue() == 1)
13817 Cond = Cond.getOperand(0);
13820 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13821 // setting operand in place of the X86ISD::SETCC.
13822 unsigned CondOpcode = Cond.getOpcode();
13823 if (CondOpcode == X86ISD::SETCC ||
13824 CondOpcode == X86ISD::SETCC_CARRY) {
13825 CC = Cond.getOperand(0);
13827 SDValue Cmp = Cond.getOperand(1);
13828 unsigned Opc = Cmp.getOpcode();
13829 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13830 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13834 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13838 // These can only come from an arithmetic instruction with overflow,
13839 // e.g. SADDO, UADDO.
13840 Cond = Cond.getNode()->getOperand(1);
13846 CondOpcode = Cond.getOpcode();
13847 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13848 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13849 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13850 Cond.getOperand(0).getValueType() != MVT::i8)) {
13851 SDValue LHS = Cond.getOperand(0);
13852 SDValue RHS = Cond.getOperand(1);
13853 unsigned X86Opcode;
13856 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13857 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13859 switch (CondOpcode) {
13860 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13862 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13864 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13867 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13868 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13870 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13872 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13875 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13876 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13877 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13878 default: llvm_unreachable("unexpected overflowing operator");
13881 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13882 if (CondOpcode == ISD::UMULO)
13883 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13886 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13888 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13890 if (CondOpcode == ISD::UMULO)
13891 Cond = X86Op.getValue(2);
13893 Cond = X86Op.getValue(1);
13895 CC = DAG.getConstant(X86Cond, MVT::i8);
13899 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13900 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13901 if (CondOpc == ISD::OR) {
13902 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13903 // two branches instead of an explicit OR instruction with a
13905 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13906 isX86LogicalCmp(Cmp)) {
13907 CC = Cond.getOperand(0).getOperand(0);
13908 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13909 Chain, Dest, CC, Cmp);
13910 CC = Cond.getOperand(1).getOperand(0);
13914 } else { // ISD::AND
13915 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13916 // two branches instead of an explicit AND instruction with a
13917 // separate test. However, we only do this if this block doesn't
13918 // have a fall-through edge, because this requires an explicit
13919 // jmp when the condition is false.
13920 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13921 isX86LogicalCmp(Cmp) &&
13922 Op.getNode()->hasOneUse()) {
13923 X86::CondCode CCode =
13924 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13925 CCode = X86::GetOppositeBranchCondition(CCode);
13926 CC = DAG.getConstant(CCode, MVT::i8);
13927 SDNode *User = *Op.getNode()->use_begin();
13928 // Look for an unconditional branch following this conditional branch.
13929 // We need this because we need to reverse the successors in order
13930 // to implement FCMP_OEQ.
13931 if (User->getOpcode() == ISD::BR) {
13932 SDValue FalseBB = User->getOperand(1);
13934 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13935 assert(NewBR == User);
13939 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13940 Chain, Dest, CC, Cmp);
13941 X86::CondCode CCode =
13942 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13943 CCode = X86::GetOppositeBranchCondition(CCode);
13944 CC = DAG.getConstant(CCode, MVT::i8);
13950 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13951 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13952 // It should be transformed during dag combiner except when the condition
13953 // is set by a arithmetics with overflow node.
13954 X86::CondCode CCode =
13955 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13956 CCode = X86::GetOppositeBranchCondition(CCode);
13957 CC = DAG.getConstant(CCode, MVT::i8);
13958 Cond = Cond.getOperand(0).getOperand(1);
13960 } else if (Cond.getOpcode() == ISD::SETCC &&
13961 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13962 // For FCMP_OEQ, we can emit
13963 // two branches instead of an explicit AND instruction with a
13964 // separate test. However, we only do this if this block doesn't
13965 // have a fall-through edge, because this requires an explicit
13966 // jmp when the condition is false.
13967 if (Op.getNode()->hasOneUse()) {
13968 SDNode *User = *Op.getNode()->use_begin();
13969 // Look for an unconditional branch following this conditional branch.
13970 // We need this because we need to reverse the successors in order
13971 // to implement FCMP_OEQ.
13972 if (User->getOpcode() == ISD::BR) {
13973 SDValue FalseBB = User->getOperand(1);
13975 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13976 assert(NewBR == User);
13980 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13981 Cond.getOperand(0), Cond.getOperand(1));
13982 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13983 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13984 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13985 Chain, Dest, CC, Cmp);
13986 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13991 } else if (Cond.getOpcode() == ISD::SETCC &&
13992 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13993 // For FCMP_UNE, we can emit
13994 // two branches instead of an explicit AND instruction with a
13995 // separate test. However, we only do this if this block doesn't
13996 // have a fall-through edge, because this requires an explicit
13997 // jmp when the condition is false.
13998 if (Op.getNode()->hasOneUse()) {
13999 SDNode *User = *Op.getNode()->use_begin();
14000 // Look for an unconditional branch following this conditional branch.
14001 // We need this because we need to reverse the successors in order
14002 // to implement FCMP_UNE.
14003 if (User->getOpcode() == ISD::BR) {
14004 SDValue FalseBB = User->getOperand(1);
14006 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14007 assert(NewBR == User);
14010 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14011 Cond.getOperand(0), Cond.getOperand(1));
14012 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14013 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14014 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14015 Chain, Dest, CC, Cmp);
14016 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14026 // Look pass the truncate if the high bits are known zero.
14027 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14028 Cond = Cond.getOperand(0);
14030 // We know the result of AND is compared against zero. Try to match
14032 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14033 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14034 if (NewSetCC.getNode()) {
14035 CC = NewSetCC.getOperand(0);
14036 Cond = NewSetCC.getOperand(1);
14043 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14044 CC = DAG.getConstant(X86Cond, MVT::i8);
14045 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14047 Cond = ConvertCmpIfNecessary(Cond, DAG);
14048 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14049 Chain, Dest, CC, Cond);
14052 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14053 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14054 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14055 // that the guard pages used by the OS virtual memory manager are allocated in
14056 // correct sequence.
14058 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14059 SelectionDAG &DAG) const {
14060 MachineFunction &MF = DAG.getMachineFunction();
14061 bool SplitStack = MF.shouldSplitStack();
14062 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14068 SDNode* Node = Op.getNode();
14070 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14071 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14072 " not tell us which reg is the stack pointer!");
14073 EVT VT = Node->getValueType(0);
14074 SDValue Tmp1 = SDValue(Node, 0);
14075 SDValue Tmp2 = SDValue(Node, 1);
14076 SDValue Tmp3 = Node->getOperand(2);
14077 SDValue Chain = Tmp1.getOperand(0);
14079 // Chain the dynamic stack allocation so that it doesn't modify the stack
14080 // pointer when other instructions are using the stack.
14081 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14084 SDValue Size = Tmp2.getOperand(1);
14085 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14086 Chain = SP.getValue(1);
14087 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14088 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
14089 unsigned StackAlign = TFI.getStackAlignment();
14090 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14091 if (Align > StackAlign)
14092 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14093 DAG.getConstant(-(uint64_t)Align, VT));
14094 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14096 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14097 DAG.getIntPtrConstant(0, true), SDValue(),
14100 SDValue Ops[2] = { Tmp1, Tmp2 };
14101 return DAG.getMergeValues(Ops, dl);
14105 SDValue Chain = Op.getOperand(0);
14106 SDValue Size = Op.getOperand(1);
14107 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14108 EVT VT = Op.getNode()->getValueType(0);
14110 bool Is64Bit = Subtarget->is64Bit();
14111 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
14114 MachineRegisterInfo &MRI = MF.getRegInfo();
14117 // The 64 bit implementation of segmented stacks needs to clobber both r10
14118 // r11. This makes it impossible to use it along with nested parameters.
14119 const Function *F = MF.getFunction();
14121 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14123 if (I->hasNestAttr())
14124 report_fatal_error("Cannot use segmented stacks with functions that "
14125 "have nested arguments.");
14128 const TargetRegisterClass *AddrRegClass =
14129 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
14130 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14131 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14132 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14133 DAG.getRegister(Vreg, SPTy));
14134 SDValue Ops1[2] = { Value, Chain };
14135 return DAG.getMergeValues(Ops1, dl);
14138 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14140 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14141 Flag = Chain.getValue(1);
14142 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14144 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14146 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
14147 DAG.getSubtarget().getRegisterInfo());
14148 unsigned SPReg = RegInfo->getStackRegister();
14149 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14150 Chain = SP.getValue(1);
14153 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14154 DAG.getConstant(-(uint64_t)Align, VT));
14155 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14158 SDValue Ops1[2] = { SP, Chain };
14159 return DAG.getMergeValues(Ops1, dl);
14163 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14164 MachineFunction &MF = DAG.getMachineFunction();
14165 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14167 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14170 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14171 // vastart just stores the address of the VarArgsFrameIndex slot into the
14172 // memory location argument.
14173 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14175 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14176 MachinePointerInfo(SV), false, false, 0);
14180 // gp_offset (0 - 6 * 8)
14181 // fp_offset (48 - 48 + 8 * 16)
14182 // overflow_arg_area (point to parameters coming in memory).
14184 SmallVector<SDValue, 8> MemOps;
14185 SDValue FIN = Op.getOperand(1);
14187 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14188 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14190 FIN, MachinePointerInfo(SV), false, false, 0);
14191 MemOps.push_back(Store);
14194 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14195 FIN, DAG.getIntPtrConstant(4));
14196 Store = DAG.getStore(Op.getOperand(0), DL,
14197 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14199 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14200 MemOps.push_back(Store);
14202 // Store ptr to overflow_arg_area
14203 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14204 FIN, DAG.getIntPtrConstant(4));
14205 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14207 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14208 MachinePointerInfo(SV, 8),
14210 MemOps.push_back(Store);
14212 // Store ptr to reg_save_area.
14213 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14214 FIN, DAG.getIntPtrConstant(8));
14215 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14217 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14218 MachinePointerInfo(SV, 16), false, false, 0);
14219 MemOps.push_back(Store);
14220 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14223 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14224 assert(Subtarget->is64Bit() &&
14225 "LowerVAARG only handles 64-bit va_arg!");
14226 assert((Subtarget->isTargetLinux() ||
14227 Subtarget->isTargetDarwin()) &&
14228 "Unhandled target in LowerVAARG");
14229 assert(Op.getNode()->getNumOperands() == 4);
14230 SDValue Chain = Op.getOperand(0);
14231 SDValue SrcPtr = Op.getOperand(1);
14232 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14233 unsigned Align = Op.getConstantOperandVal(3);
14236 EVT ArgVT = Op.getNode()->getValueType(0);
14237 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14238 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14241 // Decide which area this value should be read from.
14242 // TODO: Implement the AMD64 ABI in its entirety. This simple
14243 // selection mechanism works only for the basic types.
14244 if (ArgVT == MVT::f80) {
14245 llvm_unreachable("va_arg for f80 not yet implemented");
14246 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14247 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14248 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14249 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14251 llvm_unreachable("Unhandled argument type in LowerVAARG");
14254 if (ArgMode == 2) {
14255 // Sanity Check: Make sure using fp_offset makes sense.
14256 assert(!DAG.getTarget().Options.UseSoftFloat &&
14257 !(DAG.getMachineFunction()
14258 .getFunction()->getAttributes()
14259 .hasAttribute(AttributeSet::FunctionIndex,
14260 Attribute::NoImplicitFloat)) &&
14261 Subtarget->hasSSE1());
14264 // Insert VAARG_64 node into the DAG
14265 // VAARG_64 returns two values: Variable Argument Address, Chain
14266 SmallVector<SDValue, 11> InstOps;
14267 InstOps.push_back(Chain);
14268 InstOps.push_back(SrcPtr);
14269 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
14270 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
14271 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
14272 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14273 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14274 VTs, InstOps, MVT::i64,
14275 MachinePointerInfo(SV),
14277 /*Volatile=*/false,
14279 /*WriteMem=*/true);
14280 Chain = VAARG.getValue(1);
14282 // Load the next argument and return it
14283 return DAG.getLoad(ArgVT, dl,
14286 MachinePointerInfo(),
14287 false, false, false, 0);
14290 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14291 SelectionDAG &DAG) {
14292 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14293 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14294 SDValue Chain = Op.getOperand(0);
14295 SDValue DstPtr = Op.getOperand(1);
14296 SDValue SrcPtr = Op.getOperand(2);
14297 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14298 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14301 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14302 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14304 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14307 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14308 // amount is a constant. Takes immediate version of shift as input.
14309 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14310 SDValue SrcOp, uint64_t ShiftAmt,
14311 SelectionDAG &DAG) {
14312 MVT ElementType = VT.getVectorElementType();
14314 // Fold this packed shift into its first operand if ShiftAmt is 0.
14318 // Check for ShiftAmt >= element width
14319 if (ShiftAmt >= ElementType.getSizeInBits()) {
14320 if (Opc == X86ISD::VSRAI)
14321 ShiftAmt = ElementType.getSizeInBits() - 1;
14323 return DAG.getConstant(0, VT);
14326 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14327 && "Unknown target vector shift-by-constant node");
14329 // Fold this packed vector shift into a build vector if SrcOp is a
14330 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14331 if (VT == SrcOp.getSimpleValueType() &&
14332 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14333 SmallVector<SDValue, 8> Elts;
14334 unsigned NumElts = SrcOp->getNumOperands();
14335 ConstantSDNode *ND;
14338 default: llvm_unreachable(nullptr);
14339 case X86ISD::VSHLI:
14340 for (unsigned i=0; i!=NumElts; ++i) {
14341 SDValue CurrentOp = SrcOp->getOperand(i);
14342 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14343 Elts.push_back(CurrentOp);
14346 ND = cast<ConstantSDNode>(CurrentOp);
14347 const APInt &C = ND->getAPIntValue();
14348 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14351 case X86ISD::VSRLI:
14352 for (unsigned i=0; i!=NumElts; ++i) {
14353 SDValue CurrentOp = SrcOp->getOperand(i);
14354 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14355 Elts.push_back(CurrentOp);
14358 ND = cast<ConstantSDNode>(CurrentOp);
14359 const APInt &C = ND->getAPIntValue();
14360 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14363 case X86ISD::VSRAI:
14364 for (unsigned i=0; i!=NumElts; ++i) {
14365 SDValue CurrentOp = SrcOp->getOperand(i);
14366 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14367 Elts.push_back(CurrentOp);
14370 ND = cast<ConstantSDNode>(CurrentOp);
14371 const APInt &C = ND->getAPIntValue();
14372 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14377 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14380 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14383 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14384 // may or may not be a constant. Takes immediate version of shift as input.
14385 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14386 SDValue SrcOp, SDValue ShAmt,
14387 SelectionDAG &DAG) {
14388 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
14390 // Catch shift-by-constant.
14391 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14392 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14393 CShAmt->getZExtValue(), DAG);
14395 // Change opcode to non-immediate version
14397 default: llvm_unreachable("Unknown target vector shift node");
14398 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14399 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14400 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14403 // Need to build a vector containing shift amount
14404 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
14407 ShOps[1] = DAG.getConstant(0, MVT::i32);
14408 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
14409 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
14411 // The return type has to be a 128-bit type with the same element
14412 // type as the input type.
14413 MVT EltVT = VT.getVectorElementType();
14414 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14416 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14417 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14420 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
14421 /// necessary casting for \p Mask when lowering masking intrinsics.
14422 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14423 SDValue PreservedSrc, SelectionDAG &DAG) {
14424 EVT VT = Op.getValueType();
14425 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14426 MVT::i1, VT.getVectorNumElements());
14429 assert(MaskVT.isSimple() && "invalid mask type");
14430 return DAG.getNode(ISD::VSELECT, dl, VT,
14431 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
14435 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
14437 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14438 case Intrinsic::x86_fma_vfmadd_ps:
14439 case Intrinsic::x86_fma_vfmadd_pd:
14440 case Intrinsic::x86_fma_vfmadd_ps_256:
14441 case Intrinsic::x86_fma_vfmadd_pd_256:
14442 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
14443 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
14444 return X86ISD::FMADD;
14445 case Intrinsic::x86_fma_vfmsub_ps:
14446 case Intrinsic::x86_fma_vfmsub_pd:
14447 case Intrinsic::x86_fma_vfmsub_ps_256:
14448 case Intrinsic::x86_fma_vfmsub_pd_256:
14449 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
14450 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
14451 return X86ISD::FMSUB;
14452 case Intrinsic::x86_fma_vfnmadd_ps:
14453 case Intrinsic::x86_fma_vfnmadd_pd:
14454 case Intrinsic::x86_fma_vfnmadd_ps_256:
14455 case Intrinsic::x86_fma_vfnmadd_pd_256:
14456 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
14457 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
14458 return X86ISD::FNMADD;
14459 case Intrinsic::x86_fma_vfnmsub_ps:
14460 case Intrinsic::x86_fma_vfnmsub_pd:
14461 case Intrinsic::x86_fma_vfnmsub_ps_256:
14462 case Intrinsic::x86_fma_vfnmsub_pd_256:
14463 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
14464 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
14465 return X86ISD::FNMSUB;
14466 case Intrinsic::x86_fma_vfmaddsub_ps:
14467 case Intrinsic::x86_fma_vfmaddsub_pd:
14468 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14469 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14470 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
14471 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
14472 return X86ISD::FMADDSUB;
14473 case Intrinsic::x86_fma_vfmsubadd_ps:
14474 case Intrinsic::x86_fma_vfmsubadd_pd:
14475 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14476 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14477 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
14478 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
14479 return X86ISD::FMSUBADD;
14483 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
14485 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14487 default: return SDValue(); // Don't custom lower most intrinsics.
14488 // Comparison intrinsics.
14489 case Intrinsic::x86_sse_comieq_ss:
14490 case Intrinsic::x86_sse_comilt_ss:
14491 case Intrinsic::x86_sse_comile_ss:
14492 case Intrinsic::x86_sse_comigt_ss:
14493 case Intrinsic::x86_sse_comige_ss:
14494 case Intrinsic::x86_sse_comineq_ss:
14495 case Intrinsic::x86_sse_ucomieq_ss:
14496 case Intrinsic::x86_sse_ucomilt_ss:
14497 case Intrinsic::x86_sse_ucomile_ss:
14498 case Intrinsic::x86_sse_ucomigt_ss:
14499 case Intrinsic::x86_sse_ucomige_ss:
14500 case Intrinsic::x86_sse_ucomineq_ss:
14501 case Intrinsic::x86_sse2_comieq_sd:
14502 case Intrinsic::x86_sse2_comilt_sd:
14503 case Intrinsic::x86_sse2_comile_sd:
14504 case Intrinsic::x86_sse2_comigt_sd:
14505 case Intrinsic::x86_sse2_comige_sd:
14506 case Intrinsic::x86_sse2_comineq_sd:
14507 case Intrinsic::x86_sse2_ucomieq_sd:
14508 case Intrinsic::x86_sse2_ucomilt_sd:
14509 case Intrinsic::x86_sse2_ucomile_sd:
14510 case Intrinsic::x86_sse2_ucomigt_sd:
14511 case Intrinsic::x86_sse2_ucomige_sd:
14512 case Intrinsic::x86_sse2_ucomineq_sd: {
14516 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14517 case Intrinsic::x86_sse_comieq_ss:
14518 case Intrinsic::x86_sse2_comieq_sd:
14519 Opc = X86ISD::COMI;
14522 case Intrinsic::x86_sse_comilt_ss:
14523 case Intrinsic::x86_sse2_comilt_sd:
14524 Opc = X86ISD::COMI;
14527 case Intrinsic::x86_sse_comile_ss:
14528 case Intrinsic::x86_sse2_comile_sd:
14529 Opc = X86ISD::COMI;
14532 case Intrinsic::x86_sse_comigt_ss:
14533 case Intrinsic::x86_sse2_comigt_sd:
14534 Opc = X86ISD::COMI;
14537 case Intrinsic::x86_sse_comige_ss:
14538 case Intrinsic::x86_sse2_comige_sd:
14539 Opc = X86ISD::COMI;
14542 case Intrinsic::x86_sse_comineq_ss:
14543 case Intrinsic::x86_sse2_comineq_sd:
14544 Opc = X86ISD::COMI;
14547 case Intrinsic::x86_sse_ucomieq_ss:
14548 case Intrinsic::x86_sse2_ucomieq_sd:
14549 Opc = X86ISD::UCOMI;
14552 case Intrinsic::x86_sse_ucomilt_ss:
14553 case Intrinsic::x86_sse2_ucomilt_sd:
14554 Opc = X86ISD::UCOMI;
14557 case Intrinsic::x86_sse_ucomile_ss:
14558 case Intrinsic::x86_sse2_ucomile_sd:
14559 Opc = X86ISD::UCOMI;
14562 case Intrinsic::x86_sse_ucomigt_ss:
14563 case Intrinsic::x86_sse2_ucomigt_sd:
14564 Opc = X86ISD::UCOMI;
14567 case Intrinsic::x86_sse_ucomige_ss:
14568 case Intrinsic::x86_sse2_ucomige_sd:
14569 Opc = X86ISD::UCOMI;
14572 case Intrinsic::x86_sse_ucomineq_ss:
14573 case Intrinsic::x86_sse2_ucomineq_sd:
14574 Opc = X86ISD::UCOMI;
14579 SDValue LHS = Op.getOperand(1);
14580 SDValue RHS = Op.getOperand(2);
14581 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14582 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14583 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
14584 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14585 DAG.getConstant(X86CC, MVT::i8), Cond);
14586 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14589 // Arithmetic intrinsics.
14590 case Intrinsic::x86_sse2_pmulu_dq:
14591 case Intrinsic::x86_avx2_pmulu_dq:
14592 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14593 Op.getOperand(1), Op.getOperand(2));
14595 case Intrinsic::x86_sse41_pmuldq:
14596 case Intrinsic::x86_avx2_pmul_dq:
14597 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14598 Op.getOperand(1), Op.getOperand(2));
14600 case Intrinsic::x86_sse2_pmulhu_w:
14601 case Intrinsic::x86_avx2_pmulhu_w:
14602 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14603 Op.getOperand(1), Op.getOperand(2));
14605 case Intrinsic::x86_sse2_pmulh_w:
14606 case Intrinsic::x86_avx2_pmulh_w:
14607 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14608 Op.getOperand(1), Op.getOperand(2));
14610 // SSE2/AVX2 sub with unsigned saturation intrinsics
14611 case Intrinsic::x86_sse2_psubus_b:
14612 case Intrinsic::x86_sse2_psubus_w:
14613 case Intrinsic::x86_avx2_psubus_b:
14614 case Intrinsic::x86_avx2_psubus_w:
14615 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
14616 Op.getOperand(1), Op.getOperand(2));
14618 // SSE3/AVX horizontal add/sub intrinsics
14619 case Intrinsic::x86_sse3_hadd_ps:
14620 case Intrinsic::x86_sse3_hadd_pd:
14621 case Intrinsic::x86_avx_hadd_ps_256:
14622 case Intrinsic::x86_avx_hadd_pd_256:
14623 case Intrinsic::x86_sse3_hsub_ps:
14624 case Intrinsic::x86_sse3_hsub_pd:
14625 case Intrinsic::x86_avx_hsub_ps_256:
14626 case Intrinsic::x86_avx_hsub_pd_256:
14627 case Intrinsic::x86_ssse3_phadd_w_128:
14628 case Intrinsic::x86_ssse3_phadd_d_128:
14629 case Intrinsic::x86_avx2_phadd_w:
14630 case Intrinsic::x86_avx2_phadd_d:
14631 case Intrinsic::x86_ssse3_phsub_w_128:
14632 case Intrinsic::x86_ssse3_phsub_d_128:
14633 case Intrinsic::x86_avx2_phsub_w:
14634 case Intrinsic::x86_avx2_phsub_d: {
14637 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14638 case Intrinsic::x86_sse3_hadd_ps:
14639 case Intrinsic::x86_sse3_hadd_pd:
14640 case Intrinsic::x86_avx_hadd_ps_256:
14641 case Intrinsic::x86_avx_hadd_pd_256:
14642 Opcode = X86ISD::FHADD;
14644 case Intrinsic::x86_sse3_hsub_ps:
14645 case Intrinsic::x86_sse3_hsub_pd:
14646 case Intrinsic::x86_avx_hsub_ps_256:
14647 case Intrinsic::x86_avx_hsub_pd_256:
14648 Opcode = X86ISD::FHSUB;
14650 case Intrinsic::x86_ssse3_phadd_w_128:
14651 case Intrinsic::x86_ssse3_phadd_d_128:
14652 case Intrinsic::x86_avx2_phadd_w:
14653 case Intrinsic::x86_avx2_phadd_d:
14654 Opcode = X86ISD::HADD;
14656 case Intrinsic::x86_ssse3_phsub_w_128:
14657 case Intrinsic::x86_ssse3_phsub_d_128:
14658 case Intrinsic::x86_avx2_phsub_w:
14659 case Intrinsic::x86_avx2_phsub_d:
14660 Opcode = X86ISD::HSUB;
14663 return DAG.getNode(Opcode, dl, Op.getValueType(),
14664 Op.getOperand(1), Op.getOperand(2));
14667 // SSE2/SSE41/AVX2 integer max/min intrinsics.
14668 case Intrinsic::x86_sse2_pmaxu_b:
14669 case Intrinsic::x86_sse41_pmaxuw:
14670 case Intrinsic::x86_sse41_pmaxud:
14671 case Intrinsic::x86_avx2_pmaxu_b:
14672 case Intrinsic::x86_avx2_pmaxu_w:
14673 case Intrinsic::x86_avx2_pmaxu_d:
14674 case Intrinsic::x86_sse2_pminu_b:
14675 case Intrinsic::x86_sse41_pminuw:
14676 case Intrinsic::x86_sse41_pminud:
14677 case Intrinsic::x86_avx2_pminu_b:
14678 case Intrinsic::x86_avx2_pminu_w:
14679 case Intrinsic::x86_avx2_pminu_d:
14680 case Intrinsic::x86_sse41_pmaxsb:
14681 case Intrinsic::x86_sse2_pmaxs_w:
14682 case Intrinsic::x86_sse41_pmaxsd:
14683 case Intrinsic::x86_avx2_pmaxs_b:
14684 case Intrinsic::x86_avx2_pmaxs_w:
14685 case Intrinsic::x86_avx2_pmaxs_d:
14686 case Intrinsic::x86_sse41_pminsb:
14687 case Intrinsic::x86_sse2_pmins_w:
14688 case Intrinsic::x86_sse41_pminsd:
14689 case Intrinsic::x86_avx2_pmins_b:
14690 case Intrinsic::x86_avx2_pmins_w:
14691 case Intrinsic::x86_avx2_pmins_d: {
14694 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14695 case Intrinsic::x86_sse2_pmaxu_b:
14696 case Intrinsic::x86_sse41_pmaxuw:
14697 case Intrinsic::x86_sse41_pmaxud:
14698 case Intrinsic::x86_avx2_pmaxu_b:
14699 case Intrinsic::x86_avx2_pmaxu_w:
14700 case Intrinsic::x86_avx2_pmaxu_d:
14701 Opcode = X86ISD::UMAX;
14703 case Intrinsic::x86_sse2_pminu_b:
14704 case Intrinsic::x86_sse41_pminuw:
14705 case Intrinsic::x86_sse41_pminud:
14706 case Intrinsic::x86_avx2_pminu_b:
14707 case Intrinsic::x86_avx2_pminu_w:
14708 case Intrinsic::x86_avx2_pminu_d:
14709 Opcode = X86ISD::UMIN;
14711 case Intrinsic::x86_sse41_pmaxsb:
14712 case Intrinsic::x86_sse2_pmaxs_w:
14713 case Intrinsic::x86_sse41_pmaxsd:
14714 case Intrinsic::x86_avx2_pmaxs_b:
14715 case Intrinsic::x86_avx2_pmaxs_w:
14716 case Intrinsic::x86_avx2_pmaxs_d:
14717 Opcode = X86ISD::SMAX;
14719 case Intrinsic::x86_sse41_pminsb:
14720 case Intrinsic::x86_sse2_pmins_w:
14721 case Intrinsic::x86_sse41_pminsd:
14722 case Intrinsic::x86_avx2_pmins_b:
14723 case Intrinsic::x86_avx2_pmins_w:
14724 case Intrinsic::x86_avx2_pmins_d:
14725 Opcode = X86ISD::SMIN;
14728 return DAG.getNode(Opcode, dl, Op.getValueType(),
14729 Op.getOperand(1), Op.getOperand(2));
14732 // SSE/SSE2/AVX floating point max/min intrinsics.
14733 case Intrinsic::x86_sse_max_ps:
14734 case Intrinsic::x86_sse2_max_pd:
14735 case Intrinsic::x86_avx_max_ps_256:
14736 case Intrinsic::x86_avx_max_pd_256:
14737 case Intrinsic::x86_sse_min_ps:
14738 case Intrinsic::x86_sse2_min_pd:
14739 case Intrinsic::x86_avx_min_ps_256:
14740 case Intrinsic::x86_avx_min_pd_256: {
14743 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14744 case Intrinsic::x86_sse_max_ps:
14745 case Intrinsic::x86_sse2_max_pd:
14746 case Intrinsic::x86_avx_max_ps_256:
14747 case Intrinsic::x86_avx_max_pd_256:
14748 Opcode = X86ISD::FMAX;
14750 case Intrinsic::x86_sse_min_ps:
14751 case Intrinsic::x86_sse2_min_pd:
14752 case Intrinsic::x86_avx_min_ps_256:
14753 case Intrinsic::x86_avx_min_pd_256:
14754 Opcode = X86ISD::FMIN;
14757 return DAG.getNode(Opcode, dl, Op.getValueType(),
14758 Op.getOperand(1), Op.getOperand(2));
14761 // AVX2 variable shift intrinsics
14762 case Intrinsic::x86_avx2_psllv_d:
14763 case Intrinsic::x86_avx2_psllv_q:
14764 case Intrinsic::x86_avx2_psllv_d_256:
14765 case Intrinsic::x86_avx2_psllv_q_256:
14766 case Intrinsic::x86_avx2_psrlv_d:
14767 case Intrinsic::x86_avx2_psrlv_q:
14768 case Intrinsic::x86_avx2_psrlv_d_256:
14769 case Intrinsic::x86_avx2_psrlv_q_256:
14770 case Intrinsic::x86_avx2_psrav_d:
14771 case Intrinsic::x86_avx2_psrav_d_256: {
14774 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14775 case Intrinsic::x86_avx2_psllv_d:
14776 case Intrinsic::x86_avx2_psllv_q:
14777 case Intrinsic::x86_avx2_psllv_d_256:
14778 case Intrinsic::x86_avx2_psllv_q_256:
14781 case Intrinsic::x86_avx2_psrlv_d:
14782 case Intrinsic::x86_avx2_psrlv_q:
14783 case Intrinsic::x86_avx2_psrlv_d_256:
14784 case Intrinsic::x86_avx2_psrlv_q_256:
14787 case Intrinsic::x86_avx2_psrav_d:
14788 case Intrinsic::x86_avx2_psrav_d_256:
14792 return DAG.getNode(Opcode, dl, Op.getValueType(),
14793 Op.getOperand(1), Op.getOperand(2));
14796 case Intrinsic::x86_sse2_packssdw_128:
14797 case Intrinsic::x86_sse2_packsswb_128:
14798 case Intrinsic::x86_avx2_packssdw:
14799 case Intrinsic::x86_avx2_packsswb:
14800 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14801 Op.getOperand(1), Op.getOperand(2));
14803 case Intrinsic::x86_sse2_packuswb_128:
14804 case Intrinsic::x86_sse41_packusdw:
14805 case Intrinsic::x86_avx2_packuswb:
14806 case Intrinsic::x86_avx2_packusdw:
14807 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14808 Op.getOperand(1), Op.getOperand(2));
14810 case Intrinsic::x86_ssse3_pshuf_b_128:
14811 case Intrinsic::x86_avx2_pshuf_b:
14812 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14813 Op.getOperand(1), Op.getOperand(2));
14815 case Intrinsic::x86_sse2_pshuf_d:
14816 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14817 Op.getOperand(1), Op.getOperand(2));
14819 case Intrinsic::x86_sse2_pshufl_w:
14820 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14821 Op.getOperand(1), Op.getOperand(2));
14823 case Intrinsic::x86_sse2_pshufh_w:
14824 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14825 Op.getOperand(1), Op.getOperand(2));
14827 case Intrinsic::x86_ssse3_psign_b_128:
14828 case Intrinsic::x86_ssse3_psign_w_128:
14829 case Intrinsic::x86_ssse3_psign_d_128:
14830 case Intrinsic::x86_avx2_psign_b:
14831 case Intrinsic::x86_avx2_psign_w:
14832 case Intrinsic::x86_avx2_psign_d:
14833 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14834 Op.getOperand(1), Op.getOperand(2));
14836 case Intrinsic::x86_sse41_insertps:
14837 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
14838 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14840 case Intrinsic::x86_avx_vperm2f128_ps_256:
14841 case Intrinsic::x86_avx_vperm2f128_pd_256:
14842 case Intrinsic::x86_avx_vperm2f128_si_256:
14843 case Intrinsic::x86_avx2_vperm2i128:
14844 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
14845 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14847 case Intrinsic::x86_avx2_permd:
14848 case Intrinsic::x86_avx2_permps:
14849 // Operands intentionally swapped. Mask is last operand to intrinsic,
14850 // but second operand for node/instruction.
14851 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14852 Op.getOperand(2), Op.getOperand(1));
14854 case Intrinsic::x86_sse_sqrt_ps:
14855 case Intrinsic::x86_sse2_sqrt_pd:
14856 case Intrinsic::x86_avx_sqrt_ps_256:
14857 case Intrinsic::x86_avx_sqrt_pd_256:
14858 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
14860 case Intrinsic::x86_avx512_mask_valign_q_512:
14861 case Intrinsic::x86_avx512_mask_valign_d_512:
14862 // Vector source operands are swapped.
14863 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14864 Op.getValueType(), Op.getOperand(2),
14867 Op.getOperand(5), Op.getOperand(4), DAG);
14869 // ptest and testp intrinsics. The intrinsic these come from are designed to
14870 // return an integer value, not just an instruction so lower it to the ptest
14871 // or testp pattern and a setcc for the result.
14872 case Intrinsic::x86_sse41_ptestz:
14873 case Intrinsic::x86_sse41_ptestc:
14874 case Intrinsic::x86_sse41_ptestnzc:
14875 case Intrinsic::x86_avx_ptestz_256:
14876 case Intrinsic::x86_avx_ptestc_256:
14877 case Intrinsic::x86_avx_ptestnzc_256:
14878 case Intrinsic::x86_avx_vtestz_ps:
14879 case Intrinsic::x86_avx_vtestc_ps:
14880 case Intrinsic::x86_avx_vtestnzc_ps:
14881 case Intrinsic::x86_avx_vtestz_pd:
14882 case Intrinsic::x86_avx_vtestc_pd:
14883 case Intrinsic::x86_avx_vtestnzc_pd:
14884 case Intrinsic::x86_avx_vtestz_ps_256:
14885 case Intrinsic::x86_avx_vtestc_ps_256:
14886 case Intrinsic::x86_avx_vtestnzc_ps_256:
14887 case Intrinsic::x86_avx_vtestz_pd_256:
14888 case Intrinsic::x86_avx_vtestc_pd_256:
14889 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14890 bool IsTestPacked = false;
14893 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14894 case Intrinsic::x86_avx_vtestz_ps:
14895 case Intrinsic::x86_avx_vtestz_pd:
14896 case Intrinsic::x86_avx_vtestz_ps_256:
14897 case Intrinsic::x86_avx_vtestz_pd_256:
14898 IsTestPacked = true; // Fallthrough
14899 case Intrinsic::x86_sse41_ptestz:
14900 case Intrinsic::x86_avx_ptestz_256:
14902 X86CC = X86::COND_E;
14904 case Intrinsic::x86_avx_vtestc_ps:
14905 case Intrinsic::x86_avx_vtestc_pd:
14906 case Intrinsic::x86_avx_vtestc_ps_256:
14907 case Intrinsic::x86_avx_vtestc_pd_256:
14908 IsTestPacked = true; // Fallthrough
14909 case Intrinsic::x86_sse41_ptestc:
14910 case Intrinsic::x86_avx_ptestc_256:
14912 X86CC = X86::COND_B;
14914 case Intrinsic::x86_avx_vtestnzc_ps:
14915 case Intrinsic::x86_avx_vtestnzc_pd:
14916 case Intrinsic::x86_avx_vtestnzc_ps_256:
14917 case Intrinsic::x86_avx_vtestnzc_pd_256:
14918 IsTestPacked = true; // Fallthrough
14919 case Intrinsic::x86_sse41_ptestnzc:
14920 case Intrinsic::x86_avx_ptestnzc_256:
14922 X86CC = X86::COND_A;
14926 SDValue LHS = Op.getOperand(1);
14927 SDValue RHS = Op.getOperand(2);
14928 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14929 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14930 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14931 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14932 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14934 case Intrinsic::x86_avx512_kortestz_w:
14935 case Intrinsic::x86_avx512_kortestc_w: {
14936 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14937 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14938 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14939 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14940 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14941 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14942 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14945 // SSE/AVX shift intrinsics
14946 case Intrinsic::x86_sse2_psll_w:
14947 case Intrinsic::x86_sse2_psll_d:
14948 case Intrinsic::x86_sse2_psll_q:
14949 case Intrinsic::x86_avx2_psll_w:
14950 case Intrinsic::x86_avx2_psll_d:
14951 case Intrinsic::x86_avx2_psll_q:
14952 case Intrinsic::x86_sse2_psrl_w:
14953 case Intrinsic::x86_sse2_psrl_d:
14954 case Intrinsic::x86_sse2_psrl_q:
14955 case Intrinsic::x86_avx2_psrl_w:
14956 case Intrinsic::x86_avx2_psrl_d:
14957 case Intrinsic::x86_avx2_psrl_q:
14958 case Intrinsic::x86_sse2_psra_w:
14959 case Intrinsic::x86_sse2_psra_d:
14960 case Intrinsic::x86_avx2_psra_w:
14961 case Intrinsic::x86_avx2_psra_d: {
14964 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14965 case Intrinsic::x86_sse2_psll_w:
14966 case Intrinsic::x86_sse2_psll_d:
14967 case Intrinsic::x86_sse2_psll_q:
14968 case Intrinsic::x86_avx2_psll_w:
14969 case Intrinsic::x86_avx2_psll_d:
14970 case Intrinsic::x86_avx2_psll_q:
14971 Opcode = X86ISD::VSHL;
14973 case Intrinsic::x86_sse2_psrl_w:
14974 case Intrinsic::x86_sse2_psrl_d:
14975 case Intrinsic::x86_sse2_psrl_q:
14976 case Intrinsic::x86_avx2_psrl_w:
14977 case Intrinsic::x86_avx2_psrl_d:
14978 case Intrinsic::x86_avx2_psrl_q:
14979 Opcode = X86ISD::VSRL;
14981 case Intrinsic::x86_sse2_psra_w:
14982 case Intrinsic::x86_sse2_psra_d:
14983 case Intrinsic::x86_avx2_psra_w:
14984 case Intrinsic::x86_avx2_psra_d:
14985 Opcode = X86ISD::VSRA;
14988 return DAG.getNode(Opcode, dl, Op.getValueType(),
14989 Op.getOperand(1), Op.getOperand(2));
14992 // SSE/AVX immediate shift intrinsics
14993 case Intrinsic::x86_sse2_pslli_w:
14994 case Intrinsic::x86_sse2_pslli_d:
14995 case Intrinsic::x86_sse2_pslli_q:
14996 case Intrinsic::x86_avx2_pslli_w:
14997 case Intrinsic::x86_avx2_pslli_d:
14998 case Intrinsic::x86_avx2_pslli_q:
14999 case Intrinsic::x86_sse2_psrli_w:
15000 case Intrinsic::x86_sse2_psrli_d:
15001 case Intrinsic::x86_sse2_psrli_q:
15002 case Intrinsic::x86_avx2_psrli_w:
15003 case Intrinsic::x86_avx2_psrli_d:
15004 case Intrinsic::x86_avx2_psrli_q:
15005 case Intrinsic::x86_sse2_psrai_w:
15006 case Intrinsic::x86_sse2_psrai_d:
15007 case Intrinsic::x86_avx2_psrai_w:
15008 case Intrinsic::x86_avx2_psrai_d: {
15011 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15012 case Intrinsic::x86_sse2_pslli_w:
15013 case Intrinsic::x86_sse2_pslli_d:
15014 case Intrinsic::x86_sse2_pslli_q:
15015 case Intrinsic::x86_avx2_pslli_w:
15016 case Intrinsic::x86_avx2_pslli_d:
15017 case Intrinsic::x86_avx2_pslli_q:
15018 Opcode = X86ISD::VSHLI;
15020 case Intrinsic::x86_sse2_psrli_w:
15021 case Intrinsic::x86_sse2_psrli_d:
15022 case Intrinsic::x86_sse2_psrli_q:
15023 case Intrinsic::x86_avx2_psrli_w:
15024 case Intrinsic::x86_avx2_psrli_d:
15025 case Intrinsic::x86_avx2_psrli_q:
15026 Opcode = X86ISD::VSRLI;
15028 case Intrinsic::x86_sse2_psrai_w:
15029 case Intrinsic::x86_sse2_psrai_d:
15030 case Intrinsic::x86_avx2_psrai_w:
15031 case Intrinsic::x86_avx2_psrai_d:
15032 Opcode = X86ISD::VSRAI;
15035 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
15036 Op.getOperand(1), Op.getOperand(2), DAG);
15039 case Intrinsic::x86_sse42_pcmpistria128:
15040 case Intrinsic::x86_sse42_pcmpestria128:
15041 case Intrinsic::x86_sse42_pcmpistric128:
15042 case Intrinsic::x86_sse42_pcmpestric128:
15043 case Intrinsic::x86_sse42_pcmpistrio128:
15044 case Intrinsic::x86_sse42_pcmpestrio128:
15045 case Intrinsic::x86_sse42_pcmpistris128:
15046 case Intrinsic::x86_sse42_pcmpestris128:
15047 case Intrinsic::x86_sse42_pcmpistriz128:
15048 case Intrinsic::x86_sse42_pcmpestriz128: {
15052 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15053 case Intrinsic::x86_sse42_pcmpistria128:
15054 Opcode = X86ISD::PCMPISTRI;
15055 X86CC = X86::COND_A;
15057 case Intrinsic::x86_sse42_pcmpestria128:
15058 Opcode = X86ISD::PCMPESTRI;
15059 X86CC = X86::COND_A;
15061 case Intrinsic::x86_sse42_pcmpistric128:
15062 Opcode = X86ISD::PCMPISTRI;
15063 X86CC = X86::COND_B;
15065 case Intrinsic::x86_sse42_pcmpestric128:
15066 Opcode = X86ISD::PCMPESTRI;
15067 X86CC = X86::COND_B;
15069 case Intrinsic::x86_sse42_pcmpistrio128:
15070 Opcode = X86ISD::PCMPISTRI;
15071 X86CC = X86::COND_O;
15073 case Intrinsic::x86_sse42_pcmpestrio128:
15074 Opcode = X86ISD::PCMPESTRI;
15075 X86CC = X86::COND_O;
15077 case Intrinsic::x86_sse42_pcmpistris128:
15078 Opcode = X86ISD::PCMPISTRI;
15079 X86CC = X86::COND_S;
15081 case Intrinsic::x86_sse42_pcmpestris128:
15082 Opcode = X86ISD::PCMPESTRI;
15083 X86CC = X86::COND_S;
15085 case Intrinsic::x86_sse42_pcmpistriz128:
15086 Opcode = X86ISD::PCMPISTRI;
15087 X86CC = X86::COND_E;
15089 case Intrinsic::x86_sse42_pcmpestriz128:
15090 Opcode = X86ISD::PCMPESTRI;
15091 X86CC = X86::COND_E;
15094 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15095 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15096 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15097 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15098 DAG.getConstant(X86CC, MVT::i8),
15099 SDValue(PCMP.getNode(), 1));
15100 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15103 case Intrinsic::x86_sse42_pcmpistri128:
15104 case Intrinsic::x86_sse42_pcmpestri128: {
15106 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15107 Opcode = X86ISD::PCMPISTRI;
15109 Opcode = X86ISD::PCMPESTRI;
15111 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15112 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15113 return DAG.getNode(Opcode, dl, VTs, NewOps);
15116 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15117 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15118 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15119 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15120 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15121 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15122 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15123 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15124 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15125 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15126 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15127 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15128 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15129 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15130 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15131 dl, Op.getValueType(),
15135 Op.getOperand(4), Op.getOperand(1), DAG);
15140 case Intrinsic::x86_fma_vfmadd_ps:
15141 case Intrinsic::x86_fma_vfmadd_pd:
15142 case Intrinsic::x86_fma_vfmsub_ps:
15143 case Intrinsic::x86_fma_vfmsub_pd:
15144 case Intrinsic::x86_fma_vfnmadd_ps:
15145 case Intrinsic::x86_fma_vfnmadd_pd:
15146 case Intrinsic::x86_fma_vfnmsub_ps:
15147 case Intrinsic::x86_fma_vfnmsub_pd:
15148 case Intrinsic::x86_fma_vfmaddsub_ps:
15149 case Intrinsic::x86_fma_vfmaddsub_pd:
15150 case Intrinsic::x86_fma_vfmsubadd_ps:
15151 case Intrinsic::x86_fma_vfmsubadd_pd:
15152 case Intrinsic::x86_fma_vfmadd_ps_256:
15153 case Intrinsic::x86_fma_vfmadd_pd_256:
15154 case Intrinsic::x86_fma_vfmsub_ps_256:
15155 case Intrinsic::x86_fma_vfmsub_pd_256:
15156 case Intrinsic::x86_fma_vfnmadd_ps_256:
15157 case Intrinsic::x86_fma_vfnmadd_pd_256:
15158 case Intrinsic::x86_fma_vfnmsub_ps_256:
15159 case Intrinsic::x86_fma_vfnmsub_pd_256:
15160 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15161 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15162 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15163 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15164 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15165 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15169 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15170 SDValue Src, SDValue Mask, SDValue Base,
15171 SDValue Index, SDValue ScaleOp, SDValue Chain,
15172 const X86Subtarget * Subtarget) {
15174 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15175 assert(C && "Invalid scale type");
15176 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15177 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15178 Index.getSimpleValueType().getVectorNumElements());
15180 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15182 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15184 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15185 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15186 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15187 SDValue Segment = DAG.getRegister(0, MVT::i32);
15188 if (Src.getOpcode() == ISD::UNDEF)
15189 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15190 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15191 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15192 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15193 return DAG.getMergeValues(RetOps, dl);
15196 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15197 SDValue Src, SDValue Mask, SDValue Base,
15198 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15200 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15201 assert(C && "Invalid scale type");
15202 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15203 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15204 SDValue Segment = DAG.getRegister(0, MVT::i32);
15205 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15206 Index.getSimpleValueType().getVectorNumElements());
15208 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15210 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15212 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15213 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15214 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15215 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15216 return SDValue(Res, 1);
15219 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15220 SDValue Mask, SDValue Base, SDValue Index,
15221 SDValue ScaleOp, SDValue Chain) {
15223 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15224 assert(C && "Invalid scale type");
15225 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15226 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15227 SDValue Segment = DAG.getRegister(0, MVT::i32);
15229 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15231 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15233 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15235 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15236 //SDVTList VTs = DAG.getVTList(MVT::Other);
15237 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15238 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15239 return SDValue(Res, 0);
15242 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15243 // read performance monitor counters (x86_rdpmc).
15244 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15245 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15246 SmallVectorImpl<SDValue> &Results) {
15247 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15248 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15251 // The ECX register is used to select the index of the performance counter
15253 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15255 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15257 // Reads the content of a 64-bit performance counter and returns it in the
15258 // registers EDX:EAX.
15259 if (Subtarget->is64Bit()) {
15260 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15261 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15264 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15265 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15268 Chain = HI.getValue(1);
15270 if (Subtarget->is64Bit()) {
15271 // The EAX register is loaded with the low-order 32 bits. The EDX register
15272 // is loaded with the supported high-order bits of the counter.
15273 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15274 DAG.getConstant(32, MVT::i8));
15275 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15276 Results.push_back(Chain);
15280 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15281 SDValue Ops[] = { LO, HI };
15282 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15283 Results.push_back(Pair);
15284 Results.push_back(Chain);
15287 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15288 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15289 // also used to custom lower READCYCLECOUNTER nodes.
15290 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15291 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15292 SmallVectorImpl<SDValue> &Results) {
15293 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15294 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15297 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15298 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15299 // and the EAX register is loaded with the low-order 32 bits.
15300 if (Subtarget->is64Bit()) {
15301 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15302 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15305 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15306 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15309 SDValue Chain = HI.getValue(1);
15311 if (Opcode == X86ISD::RDTSCP_DAG) {
15312 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15314 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15315 // the ECX register. Add 'ecx' explicitly to the chain.
15316 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15318 // Explicitly store the content of ECX at the location passed in input
15319 // to the 'rdtscp' intrinsic.
15320 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15321 MachinePointerInfo(), false, false, 0);
15324 if (Subtarget->is64Bit()) {
15325 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15326 // the EAX register is loaded with the low-order 32 bits.
15327 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15328 DAG.getConstant(32, MVT::i8));
15329 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15330 Results.push_back(Chain);
15334 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15335 SDValue Ops[] = { LO, HI };
15336 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15337 Results.push_back(Pair);
15338 Results.push_back(Chain);
15341 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15342 SelectionDAG &DAG) {
15343 SmallVector<SDValue, 2> Results;
15345 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15347 return DAG.getMergeValues(Results, DL);
15350 enum IntrinsicType {
15351 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
15354 struct IntrinsicData {
15355 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
15356 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
15357 IntrinsicType Type;
15362 std::map < unsigned, IntrinsicData> IntrMap;
15363 static void InitIntinsicsMap() {
15364 static bool Initialized = false;
15367 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
15368 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
15369 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
15370 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
15371 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
15372 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
15373 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
15374 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
15375 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
15376 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
15377 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
15378 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
15379 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
15380 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
15381 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
15382 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
15383 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
15384 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
15386 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
15387 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
15388 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
15389 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
15390 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
15391 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
15392 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
15393 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
15394 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
15395 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
15396 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
15397 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
15398 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
15399 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
15400 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
15401 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
15403 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
15404 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
15405 X86::VGATHERPF1QPSm)));
15406 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
15407 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
15408 X86::VGATHERPF1QPDm)));
15409 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
15410 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
15411 X86::VGATHERPF1DPDm)));
15412 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
15413 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
15414 X86::VGATHERPF1DPSm)));
15415 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
15416 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
15417 X86::VSCATTERPF1QPSm)));
15418 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
15419 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
15420 X86::VSCATTERPF1QPDm)));
15421 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
15422 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
15423 X86::VSCATTERPF1DPDm)));
15424 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
15425 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
15426 X86::VSCATTERPF1DPSm)));
15427 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
15428 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15429 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
15430 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15431 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
15432 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15433 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
15434 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15435 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
15436 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15437 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
15438 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15439 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
15440 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
15441 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
15442 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
15443 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
15444 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
15445 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
15446 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
15447 Initialized = true;
15450 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15451 SelectionDAG &DAG) {
15452 InitIntinsicsMap();
15453 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15454 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
15455 if (itr == IntrMap.end())
15459 IntrinsicData Intr = itr->second;
15460 switch(Intr.Type) {
15463 // Emit the node with the right value type.
15464 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15465 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
15467 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15468 // Otherwise return the value from Rand, which is always 0, casted to i32.
15469 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15470 DAG.getConstant(1, Op->getValueType(1)),
15471 DAG.getConstant(X86::COND_B, MVT::i32),
15472 SDValue(Result.getNode(), 1) };
15473 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15474 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15477 // Return { result, isValid, chain }.
15478 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15479 SDValue(Result.getNode(), 2));
15482 //gather(v1, mask, index, base, scale);
15483 SDValue Chain = Op.getOperand(0);
15484 SDValue Src = Op.getOperand(2);
15485 SDValue Base = Op.getOperand(3);
15486 SDValue Index = Op.getOperand(4);
15487 SDValue Mask = Op.getOperand(5);
15488 SDValue Scale = Op.getOperand(6);
15489 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15493 //scatter(base, mask, index, v1, scale);
15494 SDValue Chain = Op.getOperand(0);
15495 SDValue Base = Op.getOperand(2);
15496 SDValue Mask = Op.getOperand(3);
15497 SDValue Index = Op.getOperand(4);
15498 SDValue Src = Op.getOperand(5);
15499 SDValue Scale = Op.getOperand(6);
15500 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15503 SDValue Hint = Op.getOperand(6);
15505 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15506 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15507 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15508 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
15509 SDValue Chain = Op.getOperand(0);
15510 SDValue Mask = Op.getOperand(2);
15511 SDValue Index = Op.getOperand(3);
15512 SDValue Base = Op.getOperand(4);
15513 SDValue Scale = Op.getOperand(5);
15514 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15516 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15518 SmallVector<SDValue, 2> Results;
15519 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
15520 return DAG.getMergeValues(Results, dl);
15522 // Read Performance Monitoring Counters.
15524 SmallVector<SDValue, 2> Results;
15525 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15526 return DAG.getMergeValues(Results, dl);
15528 // XTEST intrinsics.
15530 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15531 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
15532 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15533 DAG.getConstant(X86::COND_NE, MVT::i8),
15535 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15536 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15537 Ret, SDValue(InTrans.getNode(), 1));
15540 llvm_unreachable("Unknown Intrinsic Type");
15543 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15544 SelectionDAG &DAG) const {
15545 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15546 MFI->setReturnAddressIsTaken(true);
15548 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15551 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15553 EVT PtrVT = getPointerTy();
15556 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15557 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15558 DAG.getSubtarget().getRegisterInfo());
15559 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15560 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15561 DAG.getNode(ISD::ADD, dl, PtrVT,
15562 FrameAddr, Offset),
15563 MachinePointerInfo(), false, false, false, 0);
15566 // Just load the return address.
15567 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15568 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15569 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15572 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15573 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15574 MFI->setFrameAddressIsTaken(true);
15576 EVT VT = Op.getValueType();
15577 SDLoc dl(Op); // FIXME probably not meaningful
15578 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15579 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15580 DAG.getSubtarget().getRegisterInfo());
15581 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15582 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15583 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15584 "Invalid Frame Register!");
15585 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15587 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15588 MachinePointerInfo(),
15589 false, false, false, 0);
15593 // FIXME? Maybe this could be a TableGen attribute on some registers and
15594 // this table could be generated automatically from RegInfo.
15595 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15597 unsigned Reg = StringSwitch<unsigned>(RegName)
15598 .Case("esp", X86::ESP)
15599 .Case("rsp", X86::RSP)
15603 report_fatal_error("Invalid register name global variable");
15606 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15607 SelectionDAG &DAG) const {
15608 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15609 DAG.getSubtarget().getRegisterInfo());
15610 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15613 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15614 SDValue Chain = Op.getOperand(0);
15615 SDValue Offset = Op.getOperand(1);
15616 SDValue Handler = Op.getOperand(2);
15619 EVT PtrVT = getPointerTy();
15620 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15621 DAG.getSubtarget().getRegisterInfo());
15622 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15623 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15624 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15625 "Invalid Frame Register!");
15626 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15627 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15629 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15630 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15631 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15632 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15634 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15636 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15637 DAG.getRegister(StoreAddrReg, PtrVT));
15640 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15641 SelectionDAG &DAG) const {
15643 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15644 DAG.getVTList(MVT::i32, MVT::Other),
15645 Op.getOperand(0), Op.getOperand(1));
15648 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15649 SelectionDAG &DAG) const {
15651 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15652 Op.getOperand(0), Op.getOperand(1));
15655 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15656 return Op.getOperand(0);
15659 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15660 SelectionDAG &DAG) const {
15661 SDValue Root = Op.getOperand(0);
15662 SDValue Trmp = Op.getOperand(1); // trampoline
15663 SDValue FPtr = Op.getOperand(2); // nested function
15664 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15667 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15668 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15670 if (Subtarget->is64Bit()) {
15671 SDValue OutChains[6];
15673 // Large code-model.
15674 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15675 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15677 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15678 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15680 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15682 // Load the pointer to the nested function into R11.
15683 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15684 SDValue Addr = Trmp;
15685 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15686 Addr, MachinePointerInfo(TrmpAddr),
15689 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15690 DAG.getConstant(2, MVT::i64));
15691 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15692 MachinePointerInfo(TrmpAddr, 2),
15695 // Load the 'nest' parameter value into R10.
15696 // R10 is specified in X86CallingConv.td
15697 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15698 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15699 DAG.getConstant(10, MVT::i64));
15700 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15701 Addr, MachinePointerInfo(TrmpAddr, 10),
15704 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15705 DAG.getConstant(12, MVT::i64));
15706 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15707 MachinePointerInfo(TrmpAddr, 12),
15710 // Jump to the nested function.
15711 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15712 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15713 DAG.getConstant(20, MVT::i64));
15714 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15715 Addr, MachinePointerInfo(TrmpAddr, 20),
15718 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15719 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15720 DAG.getConstant(22, MVT::i64));
15721 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15722 MachinePointerInfo(TrmpAddr, 22),
15725 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15727 const Function *Func =
15728 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15729 CallingConv::ID CC = Func->getCallingConv();
15734 llvm_unreachable("Unsupported calling convention");
15735 case CallingConv::C:
15736 case CallingConv::X86_StdCall: {
15737 // Pass 'nest' parameter in ECX.
15738 // Must be kept in sync with X86CallingConv.td
15739 NestReg = X86::ECX;
15741 // Check that ECX wasn't needed by an 'inreg' parameter.
15742 FunctionType *FTy = Func->getFunctionType();
15743 const AttributeSet &Attrs = Func->getAttributes();
15745 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15746 unsigned InRegCount = 0;
15749 for (FunctionType::param_iterator I = FTy->param_begin(),
15750 E = FTy->param_end(); I != E; ++I, ++Idx)
15751 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15752 // FIXME: should only count parameters that are lowered to integers.
15753 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15755 if (InRegCount > 2) {
15756 report_fatal_error("Nest register in use - reduce number of inreg"
15762 case CallingConv::X86_FastCall:
15763 case CallingConv::X86_ThisCall:
15764 case CallingConv::Fast:
15765 // Pass 'nest' parameter in EAX.
15766 // Must be kept in sync with X86CallingConv.td
15767 NestReg = X86::EAX;
15771 SDValue OutChains[4];
15772 SDValue Addr, Disp;
15774 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15775 DAG.getConstant(10, MVT::i32));
15776 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15778 // This is storing the opcode for MOV32ri.
15779 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15780 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15781 OutChains[0] = DAG.getStore(Root, dl,
15782 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15783 Trmp, MachinePointerInfo(TrmpAddr),
15786 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15787 DAG.getConstant(1, MVT::i32));
15788 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15789 MachinePointerInfo(TrmpAddr, 1),
15792 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15793 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15794 DAG.getConstant(5, MVT::i32));
15795 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15796 MachinePointerInfo(TrmpAddr, 5),
15799 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15800 DAG.getConstant(6, MVT::i32));
15801 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15802 MachinePointerInfo(TrmpAddr, 6),
15805 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15809 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15810 SelectionDAG &DAG) const {
15812 The rounding mode is in bits 11:10 of FPSR, and has the following
15814 00 Round to nearest
15819 FLT_ROUNDS, on the other hand, expects the following:
15826 To perform the conversion, we do:
15827 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15830 MachineFunction &MF = DAG.getMachineFunction();
15831 const TargetMachine &TM = MF.getTarget();
15832 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15833 unsigned StackAlignment = TFI.getStackAlignment();
15834 MVT VT = Op.getSimpleValueType();
15837 // Save FP Control Word to stack slot
15838 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15839 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15841 MachineMemOperand *MMO =
15842 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15843 MachineMemOperand::MOStore, 2, 2);
15845 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15846 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15847 DAG.getVTList(MVT::Other),
15848 Ops, MVT::i16, MMO);
15850 // Load FP Control Word from stack slot
15851 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15852 MachinePointerInfo(), false, false, false, 0);
15854 // Transform as necessary
15856 DAG.getNode(ISD::SRL, DL, MVT::i16,
15857 DAG.getNode(ISD::AND, DL, MVT::i16,
15858 CWD, DAG.getConstant(0x800, MVT::i16)),
15859 DAG.getConstant(11, MVT::i8));
15861 DAG.getNode(ISD::SRL, DL, MVT::i16,
15862 DAG.getNode(ISD::AND, DL, MVT::i16,
15863 CWD, DAG.getConstant(0x400, MVT::i16)),
15864 DAG.getConstant(9, MVT::i8));
15867 DAG.getNode(ISD::AND, DL, MVT::i16,
15868 DAG.getNode(ISD::ADD, DL, MVT::i16,
15869 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15870 DAG.getConstant(1, MVT::i16)),
15871 DAG.getConstant(3, MVT::i16));
15873 return DAG.getNode((VT.getSizeInBits() < 16 ?
15874 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15877 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15878 MVT VT = Op.getSimpleValueType();
15880 unsigned NumBits = VT.getSizeInBits();
15883 Op = Op.getOperand(0);
15884 if (VT == MVT::i8) {
15885 // Zero extend to i32 since there is not an i8 bsr.
15887 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15890 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15891 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15892 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15894 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15897 DAG.getConstant(NumBits+NumBits-1, OpVT),
15898 DAG.getConstant(X86::COND_E, MVT::i8),
15901 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15903 // Finally xor with NumBits-1.
15904 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15907 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15911 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15912 MVT VT = Op.getSimpleValueType();
15914 unsigned NumBits = VT.getSizeInBits();
15917 Op = Op.getOperand(0);
15918 if (VT == MVT::i8) {
15919 // Zero extend to i32 since there is not an i8 bsr.
15921 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15924 // Issue a bsr (scan bits in reverse).
15925 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15926 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15928 // And xor with NumBits-1.
15929 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15932 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15936 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15937 MVT VT = Op.getSimpleValueType();
15938 unsigned NumBits = VT.getSizeInBits();
15940 Op = Op.getOperand(0);
15942 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15943 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15944 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15946 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15949 DAG.getConstant(NumBits, VT),
15950 DAG.getConstant(X86::COND_E, MVT::i8),
15953 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15956 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15957 // ones, and then concatenate the result back.
15958 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15959 MVT VT = Op.getSimpleValueType();
15961 assert(VT.is256BitVector() && VT.isInteger() &&
15962 "Unsupported value type for operation");
15964 unsigned NumElems = VT.getVectorNumElements();
15967 // Extract the LHS vectors
15968 SDValue LHS = Op.getOperand(0);
15969 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15970 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15972 // Extract the RHS vectors
15973 SDValue RHS = Op.getOperand(1);
15974 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15975 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15977 MVT EltVT = VT.getVectorElementType();
15978 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15980 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15981 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15982 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15985 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15986 assert(Op.getSimpleValueType().is256BitVector() &&
15987 Op.getSimpleValueType().isInteger() &&
15988 "Only handle AVX 256-bit vector integer operation");
15989 return Lower256IntArith(Op, DAG);
15992 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15993 assert(Op.getSimpleValueType().is256BitVector() &&
15994 Op.getSimpleValueType().isInteger() &&
15995 "Only handle AVX 256-bit vector integer operation");
15996 return Lower256IntArith(Op, DAG);
15999 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16000 SelectionDAG &DAG) {
16002 MVT VT = Op.getSimpleValueType();
16004 // Decompose 256-bit ops into smaller 128-bit ops.
16005 if (VT.is256BitVector() && !Subtarget->hasInt256())
16006 return Lower256IntArith(Op, DAG);
16008 SDValue A = Op.getOperand(0);
16009 SDValue B = Op.getOperand(1);
16011 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16012 if (VT == MVT::v4i32) {
16013 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16014 "Should not custom lower when pmuldq is available!");
16016 // Extract the odd parts.
16017 static const int UnpackMask[] = { 1, -1, 3, -1 };
16018 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16019 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16021 // Multiply the even parts.
16022 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16023 // Now multiply odd parts.
16024 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16026 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16027 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16029 // Merge the two vectors back together with a shuffle. This expands into 2
16031 static const int ShufMask[] = { 0, 4, 2, 6 };
16032 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16035 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16036 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16038 // Ahi = psrlqi(a, 32);
16039 // Bhi = psrlqi(b, 32);
16041 // AloBlo = pmuludq(a, b);
16042 // AloBhi = pmuludq(a, Bhi);
16043 // AhiBlo = pmuludq(Ahi, b);
16045 // AloBhi = psllqi(AloBhi, 32);
16046 // AhiBlo = psllqi(AhiBlo, 32);
16047 // return AloBlo + AloBhi + AhiBlo;
16049 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16050 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16052 // Bit cast to 32-bit vectors for MULUDQ
16053 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16054 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16055 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16056 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16057 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16058 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16060 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16061 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16062 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16064 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16065 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16067 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16068 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16071 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16072 assert(Subtarget->isTargetWin64() && "Unexpected target");
16073 EVT VT = Op.getValueType();
16074 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16075 "Unexpected return type for lowering");
16079 switch (Op->getOpcode()) {
16080 default: llvm_unreachable("Unexpected request for libcall!");
16081 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16082 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16083 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16084 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16085 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16086 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16090 SDValue InChain = DAG.getEntryNode();
16092 TargetLowering::ArgListTy Args;
16093 TargetLowering::ArgListEntry Entry;
16094 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16095 EVT ArgVT = Op->getOperand(i).getValueType();
16096 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16097 "Unexpected argument type for lowering");
16098 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16099 Entry.Node = StackPtr;
16100 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16102 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16103 Entry.Ty = PointerType::get(ArgTy,0);
16104 Entry.isSExt = false;
16105 Entry.isZExt = false;
16106 Args.push_back(Entry);
16109 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16112 TargetLowering::CallLoweringInfo CLI(DAG);
16113 CLI.setDebugLoc(dl).setChain(InChain)
16114 .setCallee(getLibcallCallingConv(LC),
16115 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16116 Callee, std::move(Args), 0)
16117 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16119 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16120 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16123 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16124 SelectionDAG &DAG) {
16125 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16126 EVT VT = Op0.getValueType();
16129 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16130 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16132 // PMULxD operations multiply each even value (starting at 0) of LHS with
16133 // the related value of RHS and produce a widen result.
16134 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16135 // => <2 x i64> <ae|cg>
16137 // In other word, to have all the results, we need to perform two PMULxD:
16138 // 1. one with the even values.
16139 // 2. one with the odd values.
16140 // To achieve #2, with need to place the odd values at an even position.
16142 // Place the odd value at an even position (basically, shift all values 1
16143 // step to the left):
16144 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16145 // <a|b|c|d> => <b|undef|d|undef>
16146 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16147 // <e|f|g|h> => <f|undef|h|undef>
16148 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16150 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16152 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16153 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16155 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16156 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16157 // => <2 x i64> <ae|cg>
16158 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16159 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16160 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16161 // => <2 x i64> <bf|dh>
16162 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16163 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16165 // Shuffle it back into the right order.
16166 SDValue Highs, Lows;
16167 if (VT == MVT::v8i32) {
16168 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16169 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16170 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16171 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16173 const int HighMask[] = {1, 5, 3, 7};
16174 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16175 const int LowMask[] = {0, 4, 2, 6};
16176 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16179 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16180 // unsigned multiply.
16181 if (IsSigned && !Subtarget->hasSSE41()) {
16183 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16184 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16185 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16186 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16187 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16189 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16190 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16193 // The first result of MUL_LOHI is actually the low value, followed by the
16195 SDValue Ops[] = {Lows, Highs};
16196 return DAG.getMergeValues(Ops, dl);
16199 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16200 const X86Subtarget *Subtarget) {
16201 MVT VT = Op.getSimpleValueType();
16203 SDValue R = Op.getOperand(0);
16204 SDValue Amt = Op.getOperand(1);
16206 // Optimize shl/srl/sra with constant shift amount.
16207 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16208 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16209 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16211 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16212 (Subtarget->hasInt256() &&
16213 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16214 (Subtarget->hasAVX512() &&
16215 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16216 if (Op.getOpcode() == ISD::SHL)
16217 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16219 if (Op.getOpcode() == ISD::SRL)
16220 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16222 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16223 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16227 if (VT == MVT::v16i8) {
16228 if (Op.getOpcode() == ISD::SHL) {
16229 // Make a large shift.
16230 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16231 MVT::v8i16, R, ShiftAmt,
16233 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16234 // Zero out the rightmost bits.
16235 SmallVector<SDValue, 16> V(16,
16236 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16238 return DAG.getNode(ISD::AND, dl, VT, SHL,
16239 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16241 if (Op.getOpcode() == ISD::SRL) {
16242 // Make a large shift.
16243 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16244 MVT::v8i16, R, ShiftAmt,
16246 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16247 // Zero out the leftmost bits.
16248 SmallVector<SDValue, 16> V(16,
16249 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16251 return DAG.getNode(ISD::AND, dl, VT, SRL,
16252 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16254 if (Op.getOpcode() == ISD::SRA) {
16255 if (ShiftAmt == 7) {
16256 // R s>> 7 === R s< 0
16257 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16258 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16261 // R s>> a === ((R u>> a) ^ m) - m
16262 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16263 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16265 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16266 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16267 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16270 llvm_unreachable("Unknown shift opcode.");
16273 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16274 if (Op.getOpcode() == ISD::SHL) {
16275 // Make a large shift.
16276 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16277 MVT::v16i16, R, ShiftAmt,
16279 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16280 // Zero out the rightmost bits.
16281 SmallVector<SDValue, 32> V(32,
16282 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16284 return DAG.getNode(ISD::AND, dl, VT, SHL,
16285 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16287 if (Op.getOpcode() == ISD::SRL) {
16288 // Make a large shift.
16289 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16290 MVT::v16i16, R, ShiftAmt,
16292 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16293 // Zero out the leftmost bits.
16294 SmallVector<SDValue, 32> V(32,
16295 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16297 return DAG.getNode(ISD::AND, dl, VT, SRL,
16298 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16300 if (Op.getOpcode() == ISD::SRA) {
16301 if (ShiftAmt == 7) {
16302 // R s>> 7 === R s< 0
16303 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16304 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16307 // R s>> a === ((R u>> a) ^ m) - m
16308 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16309 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16311 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16312 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16313 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16316 llvm_unreachable("Unknown shift opcode.");
16321 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16322 if (!Subtarget->is64Bit() &&
16323 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16324 Amt.getOpcode() == ISD::BITCAST &&
16325 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16326 Amt = Amt.getOperand(0);
16327 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16328 VT.getVectorNumElements();
16329 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16330 uint64_t ShiftAmt = 0;
16331 for (unsigned i = 0; i != Ratio; ++i) {
16332 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16336 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16338 // Check remaining shift amounts.
16339 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16340 uint64_t ShAmt = 0;
16341 for (unsigned j = 0; j != Ratio; ++j) {
16342 ConstantSDNode *C =
16343 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16347 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16349 if (ShAmt != ShiftAmt)
16352 switch (Op.getOpcode()) {
16354 llvm_unreachable("Unknown shift opcode!");
16356 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16359 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16362 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16370 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16371 const X86Subtarget* Subtarget) {
16372 MVT VT = Op.getSimpleValueType();
16374 SDValue R = Op.getOperand(0);
16375 SDValue Amt = Op.getOperand(1);
16377 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16378 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16379 (Subtarget->hasInt256() &&
16380 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16381 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16382 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16384 EVT EltVT = VT.getVectorElementType();
16386 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16387 unsigned NumElts = VT.getVectorNumElements();
16389 for (i = 0; i != NumElts; ++i) {
16390 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16394 for (j = i; j != NumElts; ++j) {
16395 SDValue Arg = Amt.getOperand(j);
16396 if (Arg.getOpcode() == ISD::UNDEF) continue;
16397 if (Arg != Amt.getOperand(i))
16400 if (i != NumElts && j == NumElts)
16401 BaseShAmt = Amt.getOperand(i);
16403 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16404 Amt = Amt.getOperand(0);
16405 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16406 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16407 SDValue InVec = Amt.getOperand(0);
16408 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16409 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16411 for (; i != NumElts; ++i) {
16412 SDValue Arg = InVec.getOperand(i);
16413 if (Arg.getOpcode() == ISD::UNDEF) continue;
16417 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16418 if (ConstantSDNode *C =
16419 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16420 unsigned SplatIdx =
16421 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16422 if (C->getZExtValue() == SplatIdx)
16423 BaseShAmt = InVec.getOperand(1);
16426 if (!BaseShAmt.getNode())
16427 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16428 DAG.getIntPtrConstant(0));
16432 if (BaseShAmt.getNode()) {
16433 if (EltVT.bitsGT(MVT::i32))
16434 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16435 else if (EltVT.bitsLT(MVT::i32))
16436 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16438 switch (Op.getOpcode()) {
16440 llvm_unreachable("Unknown shift opcode!");
16442 switch (VT.SimpleTy) {
16443 default: return SDValue();
16452 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16455 switch (VT.SimpleTy) {
16456 default: return SDValue();
16463 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16466 switch (VT.SimpleTy) {
16467 default: return SDValue();
16476 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16482 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16483 if (!Subtarget->is64Bit() &&
16484 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16485 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16486 Amt.getOpcode() == ISD::BITCAST &&
16487 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16488 Amt = Amt.getOperand(0);
16489 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16490 VT.getVectorNumElements();
16491 std::vector<SDValue> Vals(Ratio);
16492 for (unsigned i = 0; i != Ratio; ++i)
16493 Vals[i] = Amt.getOperand(i);
16494 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16495 for (unsigned j = 0; j != Ratio; ++j)
16496 if (Vals[j] != Amt.getOperand(i + j))
16499 switch (Op.getOpcode()) {
16501 llvm_unreachable("Unknown shift opcode!");
16503 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16505 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16507 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16514 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16515 SelectionDAG &DAG) {
16516 MVT VT = Op.getSimpleValueType();
16518 SDValue R = Op.getOperand(0);
16519 SDValue Amt = Op.getOperand(1);
16522 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16523 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16525 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16529 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16533 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16535 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16536 if (Subtarget->hasInt256()) {
16537 if (Op.getOpcode() == ISD::SRL &&
16538 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16539 VT == MVT::v4i64 || VT == MVT::v8i32))
16541 if (Op.getOpcode() == ISD::SHL &&
16542 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16543 VT == MVT::v4i64 || VT == MVT::v8i32))
16545 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16549 // If possible, lower this packed shift into a vector multiply instead of
16550 // expanding it into a sequence of scalar shifts.
16551 // Do this only if the vector shift count is a constant build_vector.
16552 if (Op.getOpcode() == ISD::SHL &&
16553 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16554 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16555 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16556 SmallVector<SDValue, 8> Elts;
16557 EVT SVT = VT.getScalarType();
16558 unsigned SVTBits = SVT.getSizeInBits();
16559 const APInt &One = APInt(SVTBits, 1);
16560 unsigned NumElems = VT.getVectorNumElements();
16562 for (unsigned i=0; i !=NumElems; ++i) {
16563 SDValue Op = Amt->getOperand(i);
16564 if (Op->getOpcode() == ISD::UNDEF) {
16565 Elts.push_back(Op);
16569 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16570 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16571 uint64_t ShAmt = C.getZExtValue();
16572 if (ShAmt >= SVTBits) {
16573 Elts.push_back(DAG.getUNDEF(SVT));
16576 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16578 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16579 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16582 // Lower SHL with variable shift amount.
16583 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16584 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16586 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16587 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16588 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16589 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16592 // If possible, lower this shift as a sequence of two shifts by
16593 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16595 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16597 // Could be rewritten as:
16598 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16600 // The advantage is that the two shifts from the example would be
16601 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16602 // the vector shift into four scalar shifts plus four pairs of vector
16604 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16605 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16606 unsigned TargetOpcode = X86ISD::MOVSS;
16607 bool CanBeSimplified;
16608 // The splat value for the first packed shift (the 'X' from the example).
16609 SDValue Amt1 = Amt->getOperand(0);
16610 // The splat value for the second packed shift (the 'Y' from the example).
16611 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16612 Amt->getOperand(2);
16614 // See if it is possible to replace this node with a sequence of
16615 // two shifts followed by a MOVSS/MOVSD
16616 if (VT == MVT::v4i32) {
16617 // Check if it is legal to use a MOVSS.
16618 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16619 Amt2 == Amt->getOperand(3);
16620 if (!CanBeSimplified) {
16621 // Otherwise, check if we can still simplify this node using a MOVSD.
16622 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16623 Amt->getOperand(2) == Amt->getOperand(3);
16624 TargetOpcode = X86ISD::MOVSD;
16625 Amt2 = Amt->getOperand(2);
16628 // Do similar checks for the case where the machine value type
16630 CanBeSimplified = Amt1 == Amt->getOperand(1);
16631 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16632 CanBeSimplified = Amt2 == Amt->getOperand(i);
16634 if (!CanBeSimplified) {
16635 TargetOpcode = X86ISD::MOVSD;
16636 CanBeSimplified = true;
16637 Amt2 = Amt->getOperand(4);
16638 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16639 CanBeSimplified = Amt1 == Amt->getOperand(i);
16640 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16641 CanBeSimplified = Amt2 == Amt->getOperand(j);
16645 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16646 isa<ConstantSDNode>(Amt2)) {
16647 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16648 EVT CastVT = MVT::v4i32;
16650 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16651 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16653 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16654 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16655 if (TargetOpcode == X86ISD::MOVSD)
16656 CastVT = MVT::v2i64;
16657 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16658 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16659 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16661 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16665 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16666 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16669 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16670 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16672 // Turn 'a' into a mask suitable for VSELECT
16673 SDValue VSelM = DAG.getConstant(0x80, VT);
16674 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16675 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16677 SDValue CM1 = DAG.getConstant(0x0f, VT);
16678 SDValue CM2 = DAG.getConstant(0x3f, VT);
16680 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16681 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16682 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16683 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16684 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16687 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16688 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16689 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16691 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16692 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16693 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16694 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16695 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16698 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16699 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16700 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16702 // return VSELECT(r, r+r, a);
16703 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16704 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16708 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16709 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16710 // solution better.
16711 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16712 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16714 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16715 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16716 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16717 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16718 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16721 // Decompose 256-bit shifts into smaller 128-bit shifts.
16722 if (VT.is256BitVector()) {
16723 unsigned NumElems = VT.getVectorNumElements();
16724 MVT EltVT = VT.getVectorElementType();
16725 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16727 // Extract the two vectors
16728 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16729 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16731 // Recreate the shift amount vectors
16732 SDValue Amt1, Amt2;
16733 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16734 // Constant shift amount
16735 SmallVector<SDValue, 4> Amt1Csts;
16736 SmallVector<SDValue, 4> Amt2Csts;
16737 for (unsigned i = 0; i != NumElems/2; ++i)
16738 Amt1Csts.push_back(Amt->getOperand(i));
16739 for (unsigned i = NumElems/2; i != NumElems; ++i)
16740 Amt2Csts.push_back(Amt->getOperand(i));
16742 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16743 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16745 // Variable shift amount
16746 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16747 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16750 // Issue new vector shifts for the smaller types
16751 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16752 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16754 // Concatenate the result back
16755 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16761 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16762 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16763 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16764 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16765 // has only one use.
16766 SDNode *N = Op.getNode();
16767 SDValue LHS = N->getOperand(0);
16768 SDValue RHS = N->getOperand(1);
16769 unsigned BaseOp = 0;
16772 switch (Op.getOpcode()) {
16773 default: llvm_unreachable("Unknown ovf instruction!");
16775 // A subtract of one will be selected as a INC. Note that INC doesn't
16776 // set CF, so we can't do this for UADDO.
16777 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16779 BaseOp = X86ISD::INC;
16780 Cond = X86::COND_O;
16783 BaseOp = X86ISD::ADD;
16784 Cond = X86::COND_O;
16787 BaseOp = X86ISD::ADD;
16788 Cond = X86::COND_B;
16791 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16792 // set CF, so we can't do this for USUBO.
16793 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16795 BaseOp = X86ISD::DEC;
16796 Cond = X86::COND_O;
16799 BaseOp = X86ISD::SUB;
16800 Cond = X86::COND_O;
16803 BaseOp = X86ISD::SUB;
16804 Cond = X86::COND_B;
16807 BaseOp = X86ISD::SMUL;
16808 Cond = X86::COND_O;
16810 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16811 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16813 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16816 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16817 DAG.getConstant(X86::COND_O, MVT::i32),
16818 SDValue(Sum.getNode(), 2));
16820 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16824 // Also sets EFLAGS.
16825 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16826 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16829 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16830 DAG.getConstant(Cond, MVT::i32),
16831 SDValue(Sum.getNode(), 1));
16833 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16836 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16837 SelectionDAG &DAG) const {
16839 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16840 MVT VT = Op.getSimpleValueType();
16842 if (!Subtarget->hasSSE2() || !VT.isVector())
16845 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16846 ExtraVT.getScalarType().getSizeInBits();
16848 switch (VT.SimpleTy) {
16849 default: return SDValue();
16852 if (!Subtarget->hasFp256())
16854 if (!Subtarget->hasInt256()) {
16855 // needs to be split
16856 unsigned NumElems = VT.getVectorNumElements();
16858 // Extract the LHS vectors
16859 SDValue LHS = Op.getOperand(0);
16860 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16861 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16863 MVT EltVT = VT.getVectorElementType();
16864 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16866 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16867 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16868 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16870 SDValue Extra = DAG.getValueType(ExtraVT);
16872 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16873 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16875 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16880 SDValue Op0 = Op.getOperand(0);
16881 SDValue Op00 = Op0.getOperand(0);
16883 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
16884 if (Op0.getOpcode() == ISD::BITCAST &&
16885 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
16886 // (sext (vzext x)) -> (vsext x)
16887 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
16888 if (Tmp1.getNode()) {
16889 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16890 // This folding is only valid when the in-reg type is a vector of i8,
16892 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
16893 ExtraEltVT == MVT::i32) {
16894 SDValue Tmp1Op0 = Tmp1.getOperand(0);
16895 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
16896 "This optimization is invalid without a VZEXT.");
16897 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
16903 // If the above didn't work, then just use Shift-Left + Shift-Right.
16904 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
16906 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
16912 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16913 SelectionDAG &DAG) {
16915 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16916 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16917 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16918 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16920 // The only fence that needs an instruction is a sequentially-consistent
16921 // cross-thread fence.
16922 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16923 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16924 // no-sse2). There isn't any reason to disable it if the target processor
16926 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16927 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16929 SDValue Chain = Op.getOperand(0);
16930 SDValue Zero = DAG.getConstant(0, MVT::i32);
16932 DAG.getRegister(X86::ESP, MVT::i32), // Base
16933 DAG.getTargetConstant(1, MVT::i8), // Scale
16934 DAG.getRegister(0, MVT::i32), // Index
16935 DAG.getTargetConstant(0, MVT::i32), // Disp
16936 DAG.getRegister(0, MVT::i32), // Segment.
16940 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16941 return SDValue(Res, 0);
16944 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16945 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16948 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16949 SelectionDAG &DAG) {
16950 MVT T = Op.getSimpleValueType();
16954 switch(T.SimpleTy) {
16955 default: llvm_unreachable("Invalid value type!");
16956 case MVT::i8: Reg = X86::AL; size = 1; break;
16957 case MVT::i16: Reg = X86::AX; size = 2; break;
16958 case MVT::i32: Reg = X86::EAX; size = 4; break;
16960 assert(Subtarget->is64Bit() && "Node not type legal!");
16961 Reg = X86::RAX; size = 8;
16964 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16965 Op.getOperand(2), SDValue());
16966 SDValue Ops[] = { cpIn.getValue(0),
16969 DAG.getTargetConstant(size, MVT::i8),
16970 cpIn.getValue(1) };
16971 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16972 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16973 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16977 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16978 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16979 MVT::i32, cpOut.getValue(2));
16980 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16981 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16983 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16984 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16985 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16989 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16990 SelectionDAG &DAG) {
16991 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16992 MVT DstVT = Op.getSimpleValueType();
16994 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16995 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16996 if (DstVT != MVT::f64)
16997 // This conversion needs to be expanded.
17000 SDValue InVec = Op->getOperand(0);
17002 unsigned NumElts = SrcVT.getVectorNumElements();
17003 EVT SVT = SrcVT.getVectorElementType();
17005 // Widen the vector in input in the case of MVT::v2i32.
17006 // Example: from MVT::v2i32 to MVT::v4i32.
17007 SmallVector<SDValue, 16> Elts;
17008 for (unsigned i = 0, e = NumElts; i != e; ++i)
17009 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17010 DAG.getIntPtrConstant(i)));
17012 // Explicitly mark the extra elements as Undef.
17013 SDValue Undef = DAG.getUNDEF(SVT);
17014 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17015 Elts.push_back(Undef);
17017 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17018 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17019 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17020 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17021 DAG.getIntPtrConstant(0));
17024 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17025 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17026 assert((DstVT == MVT::i64 ||
17027 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17028 "Unexpected custom BITCAST");
17029 // i64 <=> MMX conversions are Legal.
17030 if (SrcVT==MVT::i64 && DstVT.isVector())
17032 if (DstVT==MVT::i64 && SrcVT.isVector())
17034 // MMX <=> MMX conversions are Legal.
17035 if (SrcVT.isVector() && DstVT.isVector())
17037 // All other conversions need to be expanded.
17041 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17042 SDNode *Node = Op.getNode();
17044 EVT T = Node->getValueType(0);
17045 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17046 DAG.getConstant(0, T), Node->getOperand(2));
17047 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17048 cast<AtomicSDNode>(Node)->getMemoryVT(),
17049 Node->getOperand(0),
17050 Node->getOperand(1), negOp,
17051 cast<AtomicSDNode>(Node)->getMemOperand(),
17052 cast<AtomicSDNode>(Node)->getOrdering(),
17053 cast<AtomicSDNode>(Node)->getSynchScope());
17056 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17057 SDNode *Node = Op.getNode();
17059 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17061 // Convert seq_cst store -> xchg
17062 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17063 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17064 // (The only way to get a 16-byte store is cmpxchg16b)
17065 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17066 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17067 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17068 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17069 cast<AtomicSDNode>(Node)->getMemoryVT(),
17070 Node->getOperand(0),
17071 Node->getOperand(1), Node->getOperand(2),
17072 cast<AtomicSDNode>(Node)->getMemOperand(),
17073 cast<AtomicSDNode>(Node)->getOrdering(),
17074 cast<AtomicSDNode>(Node)->getSynchScope());
17075 return Swap.getValue(1);
17077 // Other atomic stores have a simple pattern.
17081 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17082 EVT VT = Op.getNode()->getSimpleValueType(0);
17084 // Let legalize expand this if it isn't a legal type yet.
17085 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17088 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17091 bool ExtraOp = false;
17092 switch (Op.getOpcode()) {
17093 default: llvm_unreachable("Invalid code");
17094 case ISD::ADDC: Opc = X86ISD::ADD; break;
17095 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17096 case ISD::SUBC: Opc = X86ISD::SUB; break;
17097 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17101 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17103 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17104 Op.getOperand(1), Op.getOperand(2));
17107 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17108 SelectionDAG &DAG) {
17109 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17111 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17112 // which returns the values as { float, float } (in XMM0) or
17113 // { double, double } (which is returned in XMM0, XMM1).
17115 SDValue Arg = Op.getOperand(0);
17116 EVT ArgVT = Arg.getValueType();
17117 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17119 TargetLowering::ArgListTy Args;
17120 TargetLowering::ArgListEntry Entry;
17124 Entry.isSExt = false;
17125 Entry.isZExt = false;
17126 Args.push_back(Entry);
17128 bool isF64 = ArgVT == MVT::f64;
17129 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17130 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17131 // the results are returned via SRet in memory.
17132 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17134 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17136 Type *RetTy = isF64
17137 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17138 : (Type*)VectorType::get(ArgTy, 4);
17140 TargetLowering::CallLoweringInfo CLI(DAG);
17141 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17142 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17144 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17147 // Returned in xmm0 and xmm1.
17148 return CallResult.first;
17150 // Returned in bits 0:31 and 32:64 xmm0.
17151 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17152 CallResult.first, DAG.getIntPtrConstant(0));
17153 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17154 CallResult.first, DAG.getIntPtrConstant(1));
17155 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17156 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17159 /// LowerOperation - Provide custom lowering hooks for some operations.
17161 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17162 switch (Op.getOpcode()) {
17163 default: llvm_unreachable("Should not custom lower this!");
17164 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17165 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17166 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17167 return LowerCMP_SWAP(Op, Subtarget, DAG);
17168 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17169 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17170 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17171 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17172 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17173 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17174 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17175 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17176 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17177 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17178 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17179 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17180 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17181 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17182 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17183 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17184 case ISD::SHL_PARTS:
17185 case ISD::SRA_PARTS:
17186 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17187 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17188 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17189 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17190 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17191 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17192 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17193 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17194 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17195 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17196 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17197 case ISD::FABS: return LowerFABS(Op, DAG);
17198 case ISD::FNEG: return LowerFNEG(Op, DAG);
17199 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17200 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17201 case ISD::SETCC: return LowerSETCC(Op, DAG);
17202 case ISD::SELECT: return LowerSELECT(Op, DAG);
17203 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17204 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17205 case ISD::VASTART: return LowerVASTART(Op, DAG);
17206 case ISD::VAARG: return LowerVAARG(Op, DAG);
17207 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17208 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17209 case ISD::INTRINSIC_VOID:
17210 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17211 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17212 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17213 case ISD::FRAME_TO_ARGS_OFFSET:
17214 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17215 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17216 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17217 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17218 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17219 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17220 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17221 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17222 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17223 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17224 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17225 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17226 case ISD::UMUL_LOHI:
17227 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17230 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17236 case ISD::UMULO: return LowerXALUO(Op, DAG);
17237 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17238 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17242 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17243 case ISD::ADD: return LowerADD(Op, DAG);
17244 case ISD::SUB: return LowerSUB(Op, DAG);
17245 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17249 static void ReplaceATOMIC_LOAD(SDNode *Node,
17250 SmallVectorImpl<SDValue> &Results,
17251 SelectionDAG &DAG) {
17253 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17255 // Convert wide load -> cmpxchg8b/cmpxchg16b
17256 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17257 // (The only way to get a 16-byte load is cmpxchg16b)
17258 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17259 SDValue Zero = DAG.getConstant(0, VT);
17260 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17262 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17263 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17264 cast<AtomicSDNode>(Node)->getMemOperand(),
17265 cast<AtomicSDNode>(Node)->getOrdering(),
17266 cast<AtomicSDNode>(Node)->getOrdering(),
17267 cast<AtomicSDNode>(Node)->getSynchScope());
17268 Results.push_back(Swap.getValue(0));
17269 Results.push_back(Swap.getValue(2));
17272 /// ReplaceNodeResults - Replace a node with an illegal result type
17273 /// with a new node built out of custom code.
17274 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17275 SmallVectorImpl<SDValue>&Results,
17276 SelectionDAG &DAG) const {
17278 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17279 switch (N->getOpcode()) {
17281 llvm_unreachable("Do not know how to custom type legalize this operation!");
17282 case ISD::SIGN_EXTEND_INREG:
17287 // We don't want to expand or promote these.
17294 case ISD::UDIVREM: {
17295 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17296 Results.push_back(V);
17299 case ISD::FP_TO_SINT:
17300 case ISD::FP_TO_UINT: {
17301 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17303 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17306 std::pair<SDValue,SDValue> Vals =
17307 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17308 SDValue FIST = Vals.first, StackSlot = Vals.second;
17309 if (FIST.getNode()) {
17310 EVT VT = N->getValueType(0);
17311 // Return a load from the stack slot.
17312 if (StackSlot.getNode())
17313 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17314 MachinePointerInfo(),
17315 false, false, false, 0));
17317 Results.push_back(FIST);
17321 case ISD::UINT_TO_FP: {
17322 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17323 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17324 N->getValueType(0) != MVT::v2f32)
17326 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17328 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17330 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17331 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17332 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17333 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17334 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17335 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17338 case ISD::FP_ROUND: {
17339 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17341 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17342 Results.push_back(V);
17345 case ISD::INTRINSIC_W_CHAIN: {
17346 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17348 default : llvm_unreachable("Do not know how to custom type "
17349 "legalize this intrinsic operation!");
17350 case Intrinsic::x86_rdtsc:
17351 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17353 case Intrinsic::x86_rdtscp:
17354 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17356 case Intrinsic::x86_rdpmc:
17357 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17360 case ISD::READCYCLECOUNTER: {
17361 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17364 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17365 EVT T = N->getValueType(0);
17366 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17367 bool Regs64bit = T == MVT::i128;
17368 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17369 SDValue cpInL, cpInH;
17370 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17371 DAG.getConstant(0, HalfT));
17372 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17373 DAG.getConstant(1, HalfT));
17374 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17375 Regs64bit ? X86::RAX : X86::EAX,
17377 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17378 Regs64bit ? X86::RDX : X86::EDX,
17379 cpInH, cpInL.getValue(1));
17380 SDValue swapInL, swapInH;
17381 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17382 DAG.getConstant(0, HalfT));
17383 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17384 DAG.getConstant(1, HalfT));
17385 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17386 Regs64bit ? X86::RBX : X86::EBX,
17387 swapInL, cpInH.getValue(1));
17388 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17389 Regs64bit ? X86::RCX : X86::ECX,
17390 swapInH, swapInL.getValue(1));
17391 SDValue Ops[] = { swapInH.getValue(0),
17393 swapInH.getValue(1) };
17394 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17395 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17396 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17397 X86ISD::LCMPXCHG8_DAG;
17398 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17399 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17400 Regs64bit ? X86::RAX : X86::EAX,
17401 HalfT, Result.getValue(1));
17402 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17403 Regs64bit ? X86::RDX : X86::EDX,
17404 HalfT, cpOutL.getValue(2));
17405 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17407 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17408 MVT::i32, cpOutH.getValue(2));
17410 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17411 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17412 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17414 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17415 Results.push_back(Success);
17416 Results.push_back(EFLAGS.getValue(1));
17419 case ISD::ATOMIC_SWAP:
17420 case ISD::ATOMIC_LOAD_ADD:
17421 case ISD::ATOMIC_LOAD_SUB:
17422 case ISD::ATOMIC_LOAD_AND:
17423 case ISD::ATOMIC_LOAD_OR:
17424 case ISD::ATOMIC_LOAD_XOR:
17425 case ISD::ATOMIC_LOAD_NAND:
17426 case ISD::ATOMIC_LOAD_MIN:
17427 case ISD::ATOMIC_LOAD_MAX:
17428 case ISD::ATOMIC_LOAD_UMIN:
17429 case ISD::ATOMIC_LOAD_UMAX:
17430 // Delegate to generic TypeLegalization. Situations we can really handle
17431 // should have already been dealt with by X86AtomicExpandPass.cpp.
17433 case ISD::ATOMIC_LOAD: {
17434 ReplaceATOMIC_LOAD(N, Results, DAG);
17437 case ISD::BITCAST: {
17438 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17439 EVT DstVT = N->getValueType(0);
17440 EVT SrcVT = N->getOperand(0)->getValueType(0);
17442 if (SrcVT != MVT::f64 ||
17443 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17446 unsigned NumElts = DstVT.getVectorNumElements();
17447 EVT SVT = DstVT.getVectorElementType();
17448 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17449 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17450 MVT::v2f64, N->getOperand(0));
17451 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17453 if (ExperimentalVectorWideningLegalization) {
17454 // If we are legalizing vectors by widening, we already have the desired
17455 // legal vector type, just return it.
17456 Results.push_back(ToVecInt);
17460 SmallVector<SDValue, 8> Elts;
17461 for (unsigned i = 0, e = NumElts; i != e; ++i)
17462 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17463 ToVecInt, DAG.getIntPtrConstant(i)));
17465 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17470 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17472 default: return nullptr;
17473 case X86ISD::BSF: return "X86ISD::BSF";
17474 case X86ISD::BSR: return "X86ISD::BSR";
17475 case X86ISD::SHLD: return "X86ISD::SHLD";
17476 case X86ISD::SHRD: return "X86ISD::SHRD";
17477 case X86ISD::FAND: return "X86ISD::FAND";
17478 case X86ISD::FANDN: return "X86ISD::FANDN";
17479 case X86ISD::FOR: return "X86ISD::FOR";
17480 case X86ISD::FXOR: return "X86ISD::FXOR";
17481 case X86ISD::FSRL: return "X86ISD::FSRL";
17482 case X86ISD::FILD: return "X86ISD::FILD";
17483 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17484 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17485 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17486 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17487 case X86ISD::FLD: return "X86ISD::FLD";
17488 case X86ISD::FST: return "X86ISD::FST";
17489 case X86ISD::CALL: return "X86ISD::CALL";
17490 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17491 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17492 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17493 case X86ISD::BT: return "X86ISD::BT";
17494 case X86ISD::CMP: return "X86ISD::CMP";
17495 case X86ISD::COMI: return "X86ISD::COMI";
17496 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17497 case X86ISD::CMPM: return "X86ISD::CMPM";
17498 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17499 case X86ISD::SETCC: return "X86ISD::SETCC";
17500 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17501 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17502 case X86ISD::CMOV: return "X86ISD::CMOV";
17503 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17504 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17505 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17506 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17507 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17508 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17509 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17510 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17511 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17512 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17513 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17514 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17515 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17516 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17517 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17518 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17519 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17520 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17521 case X86ISD::HADD: return "X86ISD::HADD";
17522 case X86ISD::HSUB: return "X86ISD::HSUB";
17523 case X86ISD::FHADD: return "X86ISD::FHADD";
17524 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17525 case X86ISD::UMAX: return "X86ISD::UMAX";
17526 case X86ISD::UMIN: return "X86ISD::UMIN";
17527 case X86ISD::SMAX: return "X86ISD::SMAX";
17528 case X86ISD::SMIN: return "X86ISD::SMIN";
17529 case X86ISD::FMAX: return "X86ISD::FMAX";
17530 case X86ISD::FMIN: return "X86ISD::FMIN";
17531 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17532 case X86ISD::FMINC: return "X86ISD::FMINC";
17533 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17534 case X86ISD::FRCP: return "X86ISD::FRCP";
17535 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17536 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17537 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17538 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17539 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17540 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17541 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17542 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17543 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17544 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17545 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17546 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17547 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17548 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17549 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17550 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17551 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17552 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17553 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17554 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17555 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17556 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17557 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17558 case X86ISD::VSHL: return "X86ISD::VSHL";
17559 case X86ISD::VSRL: return "X86ISD::VSRL";
17560 case X86ISD::VSRA: return "X86ISD::VSRA";
17561 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17562 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17563 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17564 case X86ISD::CMPP: return "X86ISD::CMPP";
17565 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17566 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17567 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17568 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17569 case X86ISD::ADD: return "X86ISD::ADD";
17570 case X86ISD::SUB: return "X86ISD::SUB";
17571 case X86ISD::ADC: return "X86ISD::ADC";
17572 case X86ISD::SBB: return "X86ISD::SBB";
17573 case X86ISD::SMUL: return "X86ISD::SMUL";
17574 case X86ISD::UMUL: return "X86ISD::UMUL";
17575 case X86ISD::INC: return "X86ISD::INC";
17576 case X86ISD::DEC: return "X86ISD::DEC";
17577 case X86ISD::OR: return "X86ISD::OR";
17578 case X86ISD::XOR: return "X86ISD::XOR";
17579 case X86ISD::AND: return "X86ISD::AND";
17580 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17581 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17582 case X86ISD::PTEST: return "X86ISD::PTEST";
17583 case X86ISD::TESTP: return "X86ISD::TESTP";
17584 case X86ISD::TESTM: return "X86ISD::TESTM";
17585 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17586 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17587 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17588 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17589 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17590 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17591 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17592 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17593 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17594 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17595 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17596 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17597 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17598 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17599 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17600 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17601 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17602 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17603 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17604 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17605 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17606 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17607 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17608 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17609 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17610 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17611 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17612 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17613 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17614 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17615 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17616 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17617 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17618 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17619 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17620 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17621 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17622 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17623 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17624 case X86ISD::SAHF: return "X86ISD::SAHF";
17625 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17626 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17627 case X86ISD::FMADD: return "X86ISD::FMADD";
17628 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17629 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17630 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17631 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17632 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17633 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17634 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17635 case X86ISD::XTEST: return "X86ISD::XTEST";
17639 // isLegalAddressingMode - Return true if the addressing mode represented
17640 // by AM is legal for this target, for a load/store of the specified type.
17641 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17643 // X86 supports extremely general addressing modes.
17644 CodeModel::Model M = getTargetMachine().getCodeModel();
17645 Reloc::Model R = getTargetMachine().getRelocationModel();
17647 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17648 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17653 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17655 // If a reference to this global requires an extra load, we can't fold it.
17656 if (isGlobalStubReference(GVFlags))
17659 // If BaseGV requires a register for the PIC base, we cannot also have a
17660 // BaseReg specified.
17661 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17664 // If lower 4G is not available, then we must use rip-relative addressing.
17665 if ((M != CodeModel::Small || R != Reloc::Static) &&
17666 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17670 switch (AM.Scale) {
17676 // These scales always work.
17681 // These scales are formed with basereg+scalereg. Only accept if there is
17686 default: // Other stuff never works.
17693 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17694 unsigned Bits = Ty->getScalarSizeInBits();
17696 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17697 // particularly cheaper than those without.
17701 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17702 // variable shifts just as cheap as scalar ones.
17703 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17706 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17707 // fully general vector.
17711 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17712 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17714 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17715 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17716 return NumBits1 > NumBits2;
17719 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17720 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17723 if (!isTypeLegal(EVT::getEVT(Ty1)))
17726 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17728 // Assuming the caller doesn't have a zeroext or signext return parameter,
17729 // truncation all the way down to i1 is valid.
17733 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17734 return isInt<32>(Imm);
17737 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17738 // Can also use sub to handle negated immediates.
17739 return isInt<32>(Imm);
17742 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17743 if (!VT1.isInteger() || !VT2.isInteger())
17745 unsigned NumBits1 = VT1.getSizeInBits();
17746 unsigned NumBits2 = VT2.getSizeInBits();
17747 return NumBits1 > NumBits2;
17750 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17751 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17752 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17755 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17756 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17757 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17760 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17761 EVT VT1 = Val.getValueType();
17762 if (isZExtFree(VT1, VT2))
17765 if (Val.getOpcode() != ISD::LOAD)
17768 if (!VT1.isSimple() || !VT1.isInteger() ||
17769 !VT2.isSimple() || !VT2.isInteger())
17772 switch (VT1.getSimpleVT().SimpleTy) {
17777 // X86 has 8, 16, and 32-bit zero-extending loads.
17785 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17786 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17789 VT = VT.getScalarType();
17791 if (!VT.isSimple())
17794 switch (VT.getSimpleVT().SimpleTy) {
17805 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17806 // i16 instructions are longer (0x66 prefix) and potentially slower.
17807 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17810 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17811 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17812 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17813 /// are assumed to be legal.
17815 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17817 if (!VT.isSimple())
17820 MVT SVT = VT.getSimpleVT();
17822 // Very little shuffling can be done for 64-bit vectors right now.
17823 if (VT.getSizeInBits() == 64)
17826 // If this is a single-input shuffle with no 128 bit lane crossings we can
17827 // lower it into pshufb.
17828 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17829 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17830 bool isLegal = true;
17831 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17832 if (M[I] >= (int)SVT.getVectorNumElements() ||
17833 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17842 // FIXME: blends, shifts.
17843 return (SVT.getVectorNumElements() == 2 ||
17844 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17845 isMOVLMask(M, SVT) ||
17846 isMOVHLPSMask(M, SVT) ||
17847 isSHUFPMask(M, SVT) ||
17848 isPSHUFDMask(M, SVT) ||
17849 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17850 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17851 isPALIGNRMask(M, SVT, Subtarget) ||
17852 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17853 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17854 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17855 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17856 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17860 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17862 if (!VT.isSimple())
17865 MVT SVT = VT.getSimpleVT();
17866 unsigned NumElts = SVT.getVectorNumElements();
17867 // FIXME: This collection of masks seems suspect.
17870 if (NumElts == 4 && SVT.is128BitVector()) {
17871 return (isMOVLMask(Mask, SVT) ||
17872 isCommutedMOVLMask(Mask, SVT, true) ||
17873 isSHUFPMask(Mask, SVT) ||
17874 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17879 //===----------------------------------------------------------------------===//
17880 // X86 Scheduler Hooks
17881 //===----------------------------------------------------------------------===//
17883 /// Utility function to emit xbegin specifying the start of an RTM region.
17884 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17885 const TargetInstrInfo *TII) {
17886 DebugLoc DL = MI->getDebugLoc();
17888 const BasicBlock *BB = MBB->getBasicBlock();
17889 MachineFunction::iterator I = MBB;
17892 // For the v = xbegin(), we generate
17903 MachineBasicBlock *thisMBB = MBB;
17904 MachineFunction *MF = MBB->getParent();
17905 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17906 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17907 MF->insert(I, mainMBB);
17908 MF->insert(I, sinkMBB);
17910 // Transfer the remainder of BB and its successor edges to sinkMBB.
17911 sinkMBB->splice(sinkMBB->begin(), MBB,
17912 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17913 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17917 // # fallthrough to mainMBB
17918 // # abortion to sinkMBB
17919 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17920 thisMBB->addSuccessor(mainMBB);
17921 thisMBB->addSuccessor(sinkMBB);
17925 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17926 mainMBB->addSuccessor(sinkMBB);
17929 // EAX is live into the sinkMBB
17930 sinkMBB->addLiveIn(X86::EAX);
17931 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17932 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17935 MI->eraseFromParent();
17939 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17940 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17941 // in the .td file.
17942 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17943 const TargetInstrInfo *TII) {
17945 switch (MI->getOpcode()) {
17946 default: llvm_unreachable("illegal opcode!");
17947 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17948 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17949 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17950 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17951 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17952 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17953 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17954 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17957 DebugLoc dl = MI->getDebugLoc();
17958 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17960 unsigned NumArgs = MI->getNumOperands();
17961 for (unsigned i = 1; i < NumArgs; ++i) {
17962 MachineOperand &Op = MI->getOperand(i);
17963 if (!(Op.isReg() && Op.isImplicit()))
17964 MIB.addOperand(Op);
17966 if (MI->hasOneMemOperand())
17967 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17969 BuildMI(*BB, MI, dl,
17970 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17971 .addReg(X86::XMM0);
17973 MI->eraseFromParent();
17977 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17978 // defs in an instruction pattern
17979 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17980 const TargetInstrInfo *TII) {
17982 switch (MI->getOpcode()) {
17983 default: llvm_unreachable("illegal opcode!");
17984 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17985 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17986 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17987 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17988 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17989 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17990 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17991 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17994 DebugLoc dl = MI->getDebugLoc();
17995 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17997 unsigned NumArgs = MI->getNumOperands(); // remove the results
17998 for (unsigned i = 1; i < NumArgs; ++i) {
17999 MachineOperand &Op = MI->getOperand(i);
18000 if (!(Op.isReg() && Op.isImplicit()))
18001 MIB.addOperand(Op);
18003 if (MI->hasOneMemOperand())
18004 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18006 BuildMI(*BB, MI, dl,
18007 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18010 MI->eraseFromParent();
18014 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18015 const TargetInstrInfo *TII,
18016 const X86Subtarget* Subtarget) {
18017 DebugLoc dl = MI->getDebugLoc();
18019 // Address into RAX/EAX, other two args into ECX, EDX.
18020 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18021 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18022 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18023 for (int i = 0; i < X86::AddrNumOperands; ++i)
18024 MIB.addOperand(MI->getOperand(i));
18026 unsigned ValOps = X86::AddrNumOperands;
18027 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18028 .addReg(MI->getOperand(ValOps).getReg());
18029 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18030 .addReg(MI->getOperand(ValOps+1).getReg());
18032 // The instruction doesn't actually take any operands though.
18033 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18035 MI->eraseFromParent(); // The pseudo is gone now.
18039 MachineBasicBlock *
18040 X86TargetLowering::EmitVAARG64WithCustomInserter(
18042 MachineBasicBlock *MBB) const {
18043 // Emit va_arg instruction on X86-64.
18045 // Operands to this pseudo-instruction:
18046 // 0 ) Output : destination address (reg)
18047 // 1-5) Input : va_list address (addr, i64mem)
18048 // 6 ) ArgSize : Size (in bytes) of vararg type
18049 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18050 // 8 ) Align : Alignment of type
18051 // 9 ) EFLAGS (implicit-def)
18053 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18054 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18056 unsigned DestReg = MI->getOperand(0).getReg();
18057 MachineOperand &Base = MI->getOperand(1);
18058 MachineOperand &Scale = MI->getOperand(2);
18059 MachineOperand &Index = MI->getOperand(3);
18060 MachineOperand &Disp = MI->getOperand(4);
18061 MachineOperand &Segment = MI->getOperand(5);
18062 unsigned ArgSize = MI->getOperand(6).getImm();
18063 unsigned ArgMode = MI->getOperand(7).getImm();
18064 unsigned Align = MI->getOperand(8).getImm();
18066 // Memory Reference
18067 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18068 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18069 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18071 // Machine Information
18072 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18073 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18074 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18075 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18076 DebugLoc DL = MI->getDebugLoc();
18078 // struct va_list {
18081 // i64 overflow_area (address)
18082 // i64 reg_save_area (address)
18084 // sizeof(va_list) = 24
18085 // alignment(va_list) = 8
18087 unsigned TotalNumIntRegs = 6;
18088 unsigned TotalNumXMMRegs = 8;
18089 bool UseGPOffset = (ArgMode == 1);
18090 bool UseFPOffset = (ArgMode == 2);
18091 unsigned MaxOffset = TotalNumIntRegs * 8 +
18092 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18094 /* Align ArgSize to a multiple of 8 */
18095 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18096 bool NeedsAlign = (Align > 8);
18098 MachineBasicBlock *thisMBB = MBB;
18099 MachineBasicBlock *overflowMBB;
18100 MachineBasicBlock *offsetMBB;
18101 MachineBasicBlock *endMBB;
18103 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18104 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18105 unsigned OffsetReg = 0;
18107 if (!UseGPOffset && !UseFPOffset) {
18108 // If we only pull from the overflow region, we don't create a branch.
18109 // We don't need to alter control flow.
18110 OffsetDestReg = 0; // unused
18111 OverflowDestReg = DestReg;
18113 offsetMBB = nullptr;
18114 overflowMBB = thisMBB;
18117 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18118 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18119 // If not, pull from overflow_area. (branch to overflowMBB)
18124 // offsetMBB overflowMBB
18129 // Registers for the PHI in endMBB
18130 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18131 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18133 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18134 MachineFunction *MF = MBB->getParent();
18135 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18136 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18137 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18139 MachineFunction::iterator MBBIter = MBB;
18142 // Insert the new basic blocks
18143 MF->insert(MBBIter, offsetMBB);
18144 MF->insert(MBBIter, overflowMBB);
18145 MF->insert(MBBIter, endMBB);
18147 // Transfer the remainder of MBB and its successor edges to endMBB.
18148 endMBB->splice(endMBB->begin(), thisMBB,
18149 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18150 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18152 // Make offsetMBB and overflowMBB successors of thisMBB
18153 thisMBB->addSuccessor(offsetMBB);
18154 thisMBB->addSuccessor(overflowMBB);
18156 // endMBB is a successor of both offsetMBB and overflowMBB
18157 offsetMBB->addSuccessor(endMBB);
18158 overflowMBB->addSuccessor(endMBB);
18160 // Load the offset value into a register
18161 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18162 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18166 .addDisp(Disp, UseFPOffset ? 4 : 0)
18167 .addOperand(Segment)
18168 .setMemRefs(MMOBegin, MMOEnd);
18170 // Check if there is enough room left to pull this argument.
18171 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18173 .addImm(MaxOffset + 8 - ArgSizeA8);
18175 // Branch to "overflowMBB" if offset >= max
18176 // Fall through to "offsetMBB" otherwise
18177 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18178 .addMBB(overflowMBB);
18181 // In offsetMBB, emit code to use the reg_save_area.
18183 assert(OffsetReg != 0);
18185 // Read the reg_save_area address.
18186 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18187 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18192 .addOperand(Segment)
18193 .setMemRefs(MMOBegin, MMOEnd);
18195 // Zero-extend the offset
18196 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18197 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18200 .addImm(X86::sub_32bit);
18202 // Add the offset to the reg_save_area to get the final address.
18203 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18204 .addReg(OffsetReg64)
18205 .addReg(RegSaveReg);
18207 // Compute the offset for the next argument
18208 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18209 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18211 .addImm(UseFPOffset ? 16 : 8);
18213 // Store it back into the va_list.
18214 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18218 .addDisp(Disp, UseFPOffset ? 4 : 0)
18219 .addOperand(Segment)
18220 .addReg(NextOffsetReg)
18221 .setMemRefs(MMOBegin, MMOEnd);
18224 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18229 // Emit code to use overflow area
18232 // Load the overflow_area address into a register.
18233 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18234 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18239 .addOperand(Segment)
18240 .setMemRefs(MMOBegin, MMOEnd);
18242 // If we need to align it, do so. Otherwise, just copy the address
18243 // to OverflowDestReg.
18245 // Align the overflow address
18246 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18247 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18249 // aligned_addr = (addr + (align-1)) & ~(align-1)
18250 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18251 .addReg(OverflowAddrReg)
18254 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18256 .addImm(~(uint64_t)(Align-1));
18258 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18259 .addReg(OverflowAddrReg);
18262 // Compute the next overflow address after this argument.
18263 // (the overflow address should be kept 8-byte aligned)
18264 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18265 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18266 .addReg(OverflowDestReg)
18267 .addImm(ArgSizeA8);
18269 // Store the new overflow address.
18270 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18275 .addOperand(Segment)
18276 .addReg(NextAddrReg)
18277 .setMemRefs(MMOBegin, MMOEnd);
18279 // If we branched, emit the PHI to the front of endMBB.
18281 BuildMI(*endMBB, endMBB->begin(), DL,
18282 TII->get(X86::PHI), DestReg)
18283 .addReg(OffsetDestReg).addMBB(offsetMBB)
18284 .addReg(OverflowDestReg).addMBB(overflowMBB);
18287 // Erase the pseudo instruction
18288 MI->eraseFromParent();
18293 MachineBasicBlock *
18294 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18296 MachineBasicBlock *MBB) const {
18297 // Emit code to save XMM registers to the stack. The ABI says that the
18298 // number of registers to save is given in %al, so it's theoretically
18299 // possible to do an indirect jump trick to avoid saving all of them,
18300 // however this code takes a simpler approach and just executes all
18301 // of the stores if %al is non-zero. It's less code, and it's probably
18302 // easier on the hardware branch predictor, and stores aren't all that
18303 // expensive anyway.
18305 // Create the new basic blocks. One block contains all the XMM stores,
18306 // and one block is the final destination regardless of whether any
18307 // stores were performed.
18308 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18309 MachineFunction *F = MBB->getParent();
18310 MachineFunction::iterator MBBIter = MBB;
18312 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18313 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18314 F->insert(MBBIter, XMMSaveMBB);
18315 F->insert(MBBIter, EndMBB);
18317 // Transfer the remainder of MBB and its successor edges to EndMBB.
18318 EndMBB->splice(EndMBB->begin(), MBB,
18319 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18320 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18322 // The original block will now fall through to the XMM save block.
18323 MBB->addSuccessor(XMMSaveMBB);
18324 // The XMMSaveMBB will fall through to the end block.
18325 XMMSaveMBB->addSuccessor(EndMBB);
18327 // Now add the instructions.
18328 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18329 DebugLoc DL = MI->getDebugLoc();
18331 unsigned CountReg = MI->getOperand(0).getReg();
18332 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18333 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18335 if (!Subtarget->isTargetWin64()) {
18336 // If %al is 0, branch around the XMM save block.
18337 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18338 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18339 MBB->addSuccessor(EndMBB);
18342 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18343 // that was just emitted, but clearly shouldn't be "saved".
18344 assert((MI->getNumOperands() <= 3 ||
18345 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18346 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18347 && "Expected last argument to be EFLAGS");
18348 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18349 // In the XMM save block, save all the XMM argument registers.
18350 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18351 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18352 MachineMemOperand *MMO =
18353 F->getMachineMemOperand(
18354 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18355 MachineMemOperand::MOStore,
18356 /*Size=*/16, /*Align=*/16);
18357 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18358 .addFrameIndex(RegSaveFrameIndex)
18359 .addImm(/*Scale=*/1)
18360 .addReg(/*IndexReg=*/0)
18361 .addImm(/*Disp=*/Offset)
18362 .addReg(/*Segment=*/0)
18363 .addReg(MI->getOperand(i).getReg())
18364 .addMemOperand(MMO);
18367 MI->eraseFromParent(); // The pseudo instruction is gone now.
18372 // The EFLAGS operand of SelectItr might be missing a kill marker
18373 // because there were multiple uses of EFLAGS, and ISel didn't know
18374 // which to mark. Figure out whether SelectItr should have had a
18375 // kill marker, and set it if it should. Returns the correct kill
18377 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18378 MachineBasicBlock* BB,
18379 const TargetRegisterInfo* TRI) {
18380 // Scan forward through BB for a use/def of EFLAGS.
18381 MachineBasicBlock::iterator miI(std::next(SelectItr));
18382 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18383 const MachineInstr& mi = *miI;
18384 if (mi.readsRegister(X86::EFLAGS))
18386 if (mi.definesRegister(X86::EFLAGS))
18387 break; // Should have kill-flag - update below.
18390 // If we hit the end of the block, check whether EFLAGS is live into a
18392 if (miI == BB->end()) {
18393 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18394 sEnd = BB->succ_end();
18395 sItr != sEnd; ++sItr) {
18396 MachineBasicBlock* succ = *sItr;
18397 if (succ->isLiveIn(X86::EFLAGS))
18402 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18403 // out. SelectMI should have a kill flag on EFLAGS.
18404 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18408 MachineBasicBlock *
18409 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18410 MachineBasicBlock *BB) const {
18411 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18412 DebugLoc DL = MI->getDebugLoc();
18414 // To "insert" a SELECT_CC instruction, we actually have to insert the
18415 // diamond control-flow pattern. The incoming instruction knows the
18416 // destination vreg to set, the condition code register to branch on, the
18417 // true/false values to select between, and a branch opcode to use.
18418 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18419 MachineFunction::iterator It = BB;
18425 // cmpTY ccX, r1, r2
18427 // fallthrough --> copy0MBB
18428 MachineBasicBlock *thisMBB = BB;
18429 MachineFunction *F = BB->getParent();
18430 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18431 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18432 F->insert(It, copy0MBB);
18433 F->insert(It, sinkMBB);
18435 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18436 // live into the sink and copy blocks.
18437 const TargetRegisterInfo *TRI =
18438 BB->getParent()->getSubtarget().getRegisterInfo();
18439 if (!MI->killsRegister(X86::EFLAGS) &&
18440 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18441 copy0MBB->addLiveIn(X86::EFLAGS);
18442 sinkMBB->addLiveIn(X86::EFLAGS);
18445 // Transfer the remainder of BB and its successor edges to sinkMBB.
18446 sinkMBB->splice(sinkMBB->begin(), BB,
18447 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18448 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18450 // Add the true and fallthrough blocks as its successors.
18451 BB->addSuccessor(copy0MBB);
18452 BB->addSuccessor(sinkMBB);
18454 // Create the conditional branch instruction.
18456 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18457 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18460 // %FalseValue = ...
18461 // # fallthrough to sinkMBB
18462 copy0MBB->addSuccessor(sinkMBB);
18465 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18467 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18468 TII->get(X86::PHI), MI->getOperand(0).getReg())
18469 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18470 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18472 MI->eraseFromParent(); // The pseudo instruction is gone now.
18476 MachineBasicBlock *
18477 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18478 bool Is64Bit) const {
18479 MachineFunction *MF = BB->getParent();
18480 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18481 DebugLoc DL = MI->getDebugLoc();
18482 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18484 assert(MF->shouldSplitStack());
18486 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18487 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18490 // ... [Till the alloca]
18491 // If stacklet is not large enough, jump to mallocMBB
18494 // Allocate by subtracting from RSP
18495 // Jump to continueMBB
18498 // Allocate by call to runtime
18502 // [rest of original BB]
18505 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18506 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18507 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18509 MachineRegisterInfo &MRI = MF->getRegInfo();
18510 const TargetRegisterClass *AddrRegClass =
18511 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18513 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18514 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18515 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18516 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18517 sizeVReg = MI->getOperand(1).getReg(),
18518 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18520 MachineFunction::iterator MBBIter = BB;
18523 MF->insert(MBBIter, bumpMBB);
18524 MF->insert(MBBIter, mallocMBB);
18525 MF->insert(MBBIter, continueMBB);
18527 continueMBB->splice(continueMBB->begin(), BB,
18528 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18529 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18531 // Add code to the main basic block to check if the stack limit has been hit,
18532 // and if so, jump to mallocMBB otherwise to bumpMBB.
18533 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18534 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18535 .addReg(tmpSPVReg).addReg(sizeVReg);
18536 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18537 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18538 .addReg(SPLimitVReg);
18539 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18541 // bumpMBB simply decreases the stack pointer, since we know the current
18542 // stacklet has enough space.
18543 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18544 .addReg(SPLimitVReg);
18545 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18546 .addReg(SPLimitVReg);
18547 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18549 // Calls into a routine in libgcc to allocate more space from the heap.
18550 const uint32_t *RegMask = MF->getTarget()
18551 .getSubtargetImpl()
18552 ->getRegisterInfo()
18553 ->getCallPreservedMask(CallingConv::C);
18555 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18557 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18558 .addExternalSymbol("__morestack_allocate_stack_space")
18559 .addRegMask(RegMask)
18560 .addReg(X86::RDI, RegState::Implicit)
18561 .addReg(X86::RAX, RegState::ImplicitDefine);
18563 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18565 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18566 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18567 .addExternalSymbol("__morestack_allocate_stack_space")
18568 .addRegMask(RegMask)
18569 .addReg(X86::EAX, RegState::ImplicitDefine);
18573 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18576 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18577 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18578 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18580 // Set up the CFG correctly.
18581 BB->addSuccessor(bumpMBB);
18582 BB->addSuccessor(mallocMBB);
18583 mallocMBB->addSuccessor(continueMBB);
18584 bumpMBB->addSuccessor(continueMBB);
18586 // Take care of the PHI nodes.
18587 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18588 MI->getOperand(0).getReg())
18589 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18590 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18592 // Delete the original pseudo instruction.
18593 MI->eraseFromParent();
18596 return continueMBB;
18599 MachineBasicBlock *
18600 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18601 MachineBasicBlock *BB) const {
18602 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18603 DebugLoc DL = MI->getDebugLoc();
18605 assert(!Subtarget->isTargetMacho());
18607 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18608 // non-trivial part is impdef of ESP.
18610 if (Subtarget->isTargetWin64()) {
18611 if (Subtarget->isTargetCygMing()) {
18612 // ___chkstk(Mingw64):
18613 // Clobbers R10, R11, RAX and EFLAGS.
18615 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18616 .addExternalSymbol("___chkstk")
18617 .addReg(X86::RAX, RegState::Implicit)
18618 .addReg(X86::RSP, RegState::Implicit)
18619 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18620 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18621 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18623 // __chkstk(MSVCRT): does not update stack pointer.
18624 // Clobbers R10, R11 and EFLAGS.
18625 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18626 .addExternalSymbol("__chkstk")
18627 .addReg(X86::RAX, RegState::Implicit)
18628 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18629 // RAX has the offset to be subtracted from RSP.
18630 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18635 const char *StackProbeSymbol =
18636 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18638 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18639 .addExternalSymbol(StackProbeSymbol)
18640 .addReg(X86::EAX, RegState::Implicit)
18641 .addReg(X86::ESP, RegState::Implicit)
18642 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18643 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18644 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18647 MI->eraseFromParent(); // The pseudo instruction is gone now.
18651 MachineBasicBlock *
18652 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18653 MachineBasicBlock *BB) const {
18654 // This is pretty easy. We're taking the value that we received from
18655 // our load from the relocation, sticking it in either RDI (x86-64)
18656 // or EAX and doing an indirect call. The return value will then
18657 // be in the normal return register.
18658 MachineFunction *F = BB->getParent();
18659 const X86InstrInfo *TII =
18660 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18661 DebugLoc DL = MI->getDebugLoc();
18663 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18664 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18666 // Get a register mask for the lowered call.
18667 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18668 // proper register mask.
18669 const uint32_t *RegMask = F->getTarget()
18670 .getSubtargetImpl()
18671 ->getRegisterInfo()
18672 ->getCallPreservedMask(CallingConv::C);
18673 if (Subtarget->is64Bit()) {
18674 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18675 TII->get(X86::MOV64rm), X86::RDI)
18677 .addImm(0).addReg(0)
18678 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18679 MI->getOperand(3).getTargetFlags())
18681 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18682 addDirectMem(MIB, X86::RDI);
18683 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18684 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18685 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18686 TII->get(X86::MOV32rm), X86::EAX)
18688 .addImm(0).addReg(0)
18689 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18690 MI->getOperand(3).getTargetFlags())
18692 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18693 addDirectMem(MIB, X86::EAX);
18694 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18696 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18697 TII->get(X86::MOV32rm), X86::EAX)
18698 .addReg(TII->getGlobalBaseReg(F))
18699 .addImm(0).addReg(0)
18700 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18701 MI->getOperand(3).getTargetFlags())
18703 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18704 addDirectMem(MIB, X86::EAX);
18705 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18708 MI->eraseFromParent(); // The pseudo instruction is gone now.
18712 MachineBasicBlock *
18713 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18714 MachineBasicBlock *MBB) const {
18715 DebugLoc DL = MI->getDebugLoc();
18716 MachineFunction *MF = MBB->getParent();
18717 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18718 MachineRegisterInfo &MRI = MF->getRegInfo();
18720 const BasicBlock *BB = MBB->getBasicBlock();
18721 MachineFunction::iterator I = MBB;
18724 // Memory Reference
18725 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18726 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18729 unsigned MemOpndSlot = 0;
18731 unsigned CurOp = 0;
18733 DstReg = MI->getOperand(CurOp++).getReg();
18734 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18735 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18736 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18737 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18739 MemOpndSlot = CurOp;
18741 MVT PVT = getPointerTy();
18742 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18743 "Invalid Pointer Size!");
18745 // For v = setjmp(buf), we generate
18748 // buf[LabelOffset] = restoreMBB
18749 // SjLjSetup restoreMBB
18755 // v = phi(main, restore)
18760 MachineBasicBlock *thisMBB = MBB;
18761 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18762 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18763 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18764 MF->insert(I, mainMBB);
18765 MF->insert(I, sinkMBB);
18766 MF->push_back(restoreMBB);
18768 MachineInstrBuilder MIB;
18770 // Transfer the remainder of BB and its successor edges to sinkMBB.
18771 sinkMBB->splice(sinkMBB->begin(), MBB,
18772 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18773 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18776 unsigned PtrStoreOpc = 0;
18777 unsigned LabelReg = 0;
18778 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18779 Reloc::Model RM = MF->getTarget().getRelocationModel();
18780 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18781 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18783 // Prepare IP either in reg or imm.
18784 if (!UseImmLabel) {
18785 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18786 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18787 LabelReg = MRI.createVirtualRegister(PtrRC);
18788 if (Subtarget->is64Bit()) {
18789 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18793 .addMBB(restoreMBB)
18796 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18797 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18798 .addReg(XII->getGlobalBaseReg(MF))
18801 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18805 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18807 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18808 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18809 if (i == X86::AddrDisp)
18810 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18812 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18815 MIB.addReg(LabelReg);
18817 MIB.addMBB(restoreMBB);
18818 MIB.setMemRefs(MMOBegin, MMOEnd);
18820 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18821 .addMBB(restoreMBB);
18823 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18824 MF->getSubtarget().getRegisterInfo());
18825 MIB.addRegMask(RegInfo->getNoPreservedMask());
18826 thisMBB->addSuccessor(mainMBB);
18827 thisMBB->addSuccessor(restoreMBB);
18831 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18832 mainMBB->addSuccessor(sinkMBB);
18835 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18836 TII->get(X86::PHI), DstReg)
18837 .addReg(mainDstReg).addMBB(mainMBB)
18838 .addReg(restoreDstReg).addMBB(restoreMBB);
18841 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18842 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18843 restoreMBB->addSuccessor(sinkMBB);
18845 MI->eraseFromParent();
18849 MachineBasicBlock *
18850 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18851 MachineBasicBlock *MBB) const {
18852 DebugLoc DL = MI->getDebugLoc();
18853 MachineFunction *MF = MBB->getParent();
18854 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18855 MachineRegisterInfo &MRI = MF->getRegInfo();
18857 // Memory Reference
18858 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18859 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18861 MVT PVT = getPointerTy();
18862 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18863 "Invalid Pointer Size!");
18865 const TargetRegisterClass *RC =
18866 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18867 unsigned Tmp = MRI.createVirtualRegister(RC);
18868 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18869 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18870 MF->getSubtarget().getRegisterInfo());
18871 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18872 unsigned SP = RegInfo->getStackRegister();
18874 MachineInstrBuilder MIB;
18876 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18877 const int64_t SPOffset = 2 * PVT.getStoreSize();
18879 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18880 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18883 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18884 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18885 MIB.addOperand(MI->getOperand(i));
18886 MIB.setMemRefs(MMOBegin, MMOEnd);
18888 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18889 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18890 if (i == X86::AddrDisp)
18891 MIB.addDisp(MI->getOperand(i), LabelOffset);
18893 MIB.addOperand(MI->getOperand(i));
18895 MIB.setMemRefs(MMOBegin, MMOEnd);
18897 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18898 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18899 if (i == X86::AddrDisp)
18900 MIB.addDisp(MI->getOperand(i), SPOffset);
18902 MIB.addOperand(MI->getOperand(i));
18904 MIB.setMemRefs(MMOBegin, MMOEnd);
18906 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18908 MI->eraseFromParent();
18912 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18913 // accumulator loops. Writing back to the accumulator allows the coalescer
18914 // to remove extra copies in the loop.
18915 MachineBasicBlock *
18916 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18917 MachineBasicBlock *MBB) const {
18918 MachineOperand &AddendOp = MI->getOperand(3);
18920 // Bail out early if the addend isn't a register - we can't switch these.
18921 if (!AddendOp.isReg())
18924 MachineFunction &MF = *MBB->getParent();
18925 MachineRegisterInfo &MRI = MF.getRegInfo();
18927 // Check whether the addend is defined by a PHI:
18928 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18929 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18930 if (!AddendDef.isPHI())
18933 // Look for the following pattern:
18935 // %addend = phi [%entry, 0], [%loop, %result]
18937 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18941 // %addend = phi [%entry, 0], [%loop, %result]
18943 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18945 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18946 assert(AddendDef.getOperand(i).isReg());
18947 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18948 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18949 if (&PHISrcInst == MI) {
18950 // Found a matching instruction.
18951 unsigned NewFMAOpc = 0;
18952 switch (MI->getOpcode()) {
18953 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18954 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18955 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18956 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18957 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18958 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18959 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18960 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18961 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18962 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18963 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18964 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18965 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18966 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18967 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18968 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18969 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18970 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18971 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18972 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18973 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18974 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18975 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18976 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18977 default: llvm_unreachable("Unrecognized FMA variant.");
18980 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18981 MachineInstrBuilder MIB =
18982 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18983 .addOperand(MI->getOperand(0))
18984 .addOperand(MI->getOperand(3))
18985 .addOperand(MI->getOperand(2))
18986 .addOperand(MI->getOperand(1));
18987 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18988 MI->eraseFromParent();
18995 MachineBasicBlock *
18996 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18997 MachineBasicBlock *BB) const {
18998 switch (MI->getOpcode()) {
18999 default: llvm_unreachable("Unexpected instr type to insert");
19000 case X86::TAILJMPd64:
19001 case X86::TAILJMPr64:
19002 case X86::TAILJMPm64:
19003 llvm_unreachable("TAILJMP64 would not be touched here.");
19004 case X86::TCRETURNdi64:
19005 case X86::TCRETURNri64:
19006 case X86::TCRETURNmi64:
19008 case X86::WIN_ALLOCA:
19009 return EmitLoweredWinAlloca(MI, BB);
19010 case X86::SEG_ALLOCA_32:
19011 return EmitLoweredSegAlloca(MI, BB, false);
19012 case X86::SEG_ALLOCA_64:
19013 return EmitLoweredSegAlloca(MI, BB, true);
19014 case X86::TLSCall_32:
19015 case X86::TLSCall_64:
19016 return EmitLoweredTLSCall(MI, BB);
19017 case X86::CMOV_GR8:
19018 case X86::CMOV_FR32:
19019 case X86::CMOV_FR64:
19020 case X86::CMOV_V4F32:
19021 case X86::CMOV_V2F64:
19022 case X86::CMOV_V2I64:
19023 case X86::CMOV_V8F32:
19024 case X86::CMOV_V4F64:
19025 case X86::CMOV_V4I64:
19026 case X86::CMOV_V16F32:
19027 case X86::CMOV_V8F64:
19028 case X86::CMOV_V8I64:
19029 case X86::CMOV_GR16:
19030 case X86::CMOV_GR32:
19031 case X86::CMOV_RFP32:
19032 case X86::CMOV_RFP64:
19033 case X86::CMOV_RFP80:
19034 return EmitLoweredSelect(MI, BB);
19036 case X86::FP32_TO_INT16_IN_MEM:
19037 case X86::FP32_TO_INT32_IN_MEM:
19038 case X86::FP32_TO_INT64_IN_MEM:
19039 case X86::FP64_TO_INT16_IN_MEM:
19040 case X86::FP64_TO_INT32_IN_MEM:
19041 case X86::FP64_TO_INT64_IN_MEM:
19042 case X86::FP80_TO_INT16_IN_MEM:
19043 case X86::FP80_TO_INT32_IN_MEM:
19044 case X86::FP80_TO_INT64_IN_MEM: {
19045 MachineFunction *F = BB->getParent();
19046 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19047 DebugLoc DL = MI->getDebugLoc();
19049 // Change the floating point control register to use "round towards zero"
19050 // mode when truncating to an integer value.
19051 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19052 addFrameReference(BuildMI(*BB, MI, DL,
19053 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19055 // Load the old value of the high byte of the control word...
19057 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19058 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19061 // Set the high part to be round to zero...
19062 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19065 // Reload the modified control word now...
19066 addFrameReference(BuildMI(*BB, MI, DL,
19067 TII->get(X86::FLDCW16m)), CWFrameIdx);
19069 // Restore the memory image of control word to original value
19070 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19073 // Get the X86 opcode to use.
19075 switch (MI->getOpcode()) {
19076 default: llvm_unreachable("illegal opcode!");
19077 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19078 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19079 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19080 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19081 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19082 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19083 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19084 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19085 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19089 MachineOperand &Op = MI->getOperand(0);
19091 AM.BaseType = X86AddressMode::RegBase;
19092 AM.Base.Reg = Op.getReg();
19094 AM.BaseType = X86AddressMode::FrameIndexBase;
19095 AM.Base.FrameIndex = Op.getIndex();
19097 Op = MI->getOperand(1);
19099 AM.Scale = Op.getImm();
19100 Op = MI->getOperand(2);
19102 AM.IndexReg = Op.getImm();
19103 Op = MI->getOperand(3);
19104 if (Op.isGlobal()) {
19105 AM.GV = Op.getGlobal();
19107 AM.Disp = Op.getImm();
19109 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19110 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19112 // Reload the original control word now.
19113 addFrameReference(BuildMI(*BB, MI, DL,
19114 TII->get(X86::FLDCW16m)), CWFrameIdx);
19116 MI->eraseFromParent(); // The pseudo instruction is gone now.
19119 // String/text processing lowering.
19120 case X86::PCMPISTRM128REG:
19121 case X86::VPCMPISTRM128REG:
19122 case X86::PCMPISTRM128MEM:
19123 case X86::VPCMPISTRM128MEM:
19124 case X86::PCMPESTRM128REG:
19125 case X86::VPCMPESTRM128REG:
19126 case X86::PCMPESTRM128MEM:
19127 case X86::VPCMPESTRM128MEM:
19128 assert(Subtarget->hasSSE42() &&
19129 "Target must have SSE4.2 or AVX features enabled");
19130 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19132 // String/text processing lowering.
19133 case X86::PCMPISTRIREG:
19134 case X86::VPCMPISTRIREG:
19135 case X86::PCMPISTRIMEM:
19136 case X86::VPCMPISTRIMEM:
19137 case X86::PCMPESTRIREG:
19138 case X86::VPCMPESTRIREG:
19139 case X86::PCMPESTRIMEM:
19140 case X86::VPCMPESTRIMEM:
19141 assert(Subtarget->hasSSE42() &&
19142 "Target must have SSE4.2 or AVX features enabled");
19143 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19145 // Thread synchronization.
19147 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19152 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19154 case X86::VASTART_SAVE_XMM_REGS:
19155 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19157 case X86::VAARG_64:
19158 return EmitVAARG64WithCustomInserter(MI, BB);
19160 case X86::EH_SjLj_SetJmp32:
19161 case X86::EH_SjLj_SetJmp64:
19162 return emitEHSjLjSetJmp(MI, BB);
19164 case X86::EH_SjLj_LongJmp32:
19165 case X86::EH_SjLj_LongJmp64:
19166 return emitEHSjLjLongJmp(MI, BB);
19168 case TargetOpcode::STACKMAP:
19169 case TargetOpcode::PATCHPOINT:
19170 return emitPatchPoint(MI, BB);
19172 case X86::VFMADDPDr213r:
19173 case X86::VFMADDPSr213r:
19174 case X86::VFMADDSDr213r:
19175 case X86::VFMADDSSr213r:
19176 case X86::VFMSUBPDr213r:
19177 case X86::VFMSUBPSr213r:
19178 case X86::VFMSUBSDr213r:
19179 case X86::VFMSUBSSr213r:
19180 case X86::VFNMADDPDr213r:
19181 case X86::VFNMADDPSr213r:
19182 case X86::VFNMADDSDr213r:
19183 case X86::VFNMADDSSr213r:
19184 case X86::VFNMSUBPDr213r:
19185 case X86::VFNMSUBPSr213r:
19186 case X86::VFNMSUBSDr213r:
19187 case X86::VFNMSUBSSr213r:
19188 case X86::VFMADDPDr213rY:
19189 case X86::VFMADDPSr213rY:
19190 case X86::VFMSUBPDr213rY:
19191 case X86::VFMSUBPSr213rY:
19192 case X86::VFNMADDPDr213rY:
19193 case X86::VFNMADDPSr213rY:
19194 case X86::VFNMSUBPDr213rY:
19195 case X86::VFNMSUBPSr213rY:
19196 return emitFMA3Instr(MI, BB);
19200 //===----------------------------------------------------------------------===//
19201 // X86 Optimization Hooks
19202 //===----------------------------------------------------------------------===//
19204 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19207 const SelectionDAG &DAG,
19208 unsigned Depth) const {
19209 unsigned BitWidth = KnownZero.getBitWidth();
19210 unsigned Opc = Op.getOpcode();
19211 assert((Opc >= ISD::BUILTIN_OP_END ||
19212 Opc == ISD::INTRINSIC_WO_CHAIN ||
19213 Opc == ISD::INTRINSIC_W_CHAIN ||
19214 Opc == ISD::INTRINSIC_VOID) &&
19215 "Should use MaskedValueIsZero if you don't know whether Op"
19216 " is a target node!");
19218 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19232 // These nodes' second result is a boolean.
19233 if (Op.getResNo() == 0)
19236 case X86ISD::SETCC:
19237 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19239 case ISD::INTRINSIC_WO_CHAIN: {
19240 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19241 unsigned NumLoBits = 0;
19244 case Intrinsic::x86_sse_movmsk_ps:
19245 case Intrinsic::x86_avx_movmsk_ps_256:
19246 case Intrinsic::x86_sse2_movmsk_pd:
19247 case Intrinsic::x86_avx_movmsk_pd_256:
19248 case Intrinsic::x86_mmx_pmovmskb:
19249 case Intrinsic::x86_sse2_pmovmskb_128:
19250 case Intrinsic::x86_avx2_pmovmskb: {
19251 // High bits of movmskp{s|d}, pmovmskb are known zero.
19253 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19254 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19255 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19256 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19257 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19258 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19259 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19260 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19262 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19271 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19273 const SelectionDAG &,
19274 unsigned Depth) const {
19275 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19276 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19277 return Op.getValueType().getScalarType().getSizeInBits();
19283 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19284 /// node is a GlobalAddress + offset.
19285 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19286 const GlobalValue* &GA,
19287 int64_t &Offset) const {
19288 if (N->getOpcode() == X86ISD::Wrapper) {
19289 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19290 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19291 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19295 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19298 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19299 /// same as extracting the high 128-bit part of 256-bit vector and then
19300 /// inserting the result into the low part of a new 256-bit vector
19301 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19302 EVT VT = SVOp->getValueType(0);
19303 unsigned NumElems = VT.getVectorNumElements();
19305 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19306 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19307 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19308 SVOp->getMaskElt(j) >= 0)
19314 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19315 /// same as extracting the low 128-bit part of 256-bit vector and then
19316 /// inserting the result into the high part of a new 256-bit vector
19317 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19318 EVT VT = SVOp->getValueType(0);
19319 unsigned NumElems = VT.getVectorNumElements();
19321 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19322 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19323 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19324 SVOp->getMaskElt(j) >= 0)
19330 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19331 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19332 TargetLowering::DAGCombinerInfo &DCI,
19333 const X86Subtarget* Subtarget) {
19335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19336 SDValue V1 = SVOp->getOperand(0);
19337 SDValue V2 = SVOp->getOperand(1);
19338 EVT VT = SVOp->getValueType(0);
19339 unsigned NumElems = VT.getVectorNumElements();
19341 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19342 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19346 // V UNDEF BUILD_VECTOR UNDEF
19348 // CONCAT_VECTOR CONCAT_VECTOR
19351 // RESULT: V + zero extended
19353 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19354 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19355 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19358 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19361 // To match the shuffle mask, the first half of the mask should
19362 // be exactly the first vector, and all the rest a splat with the
19363 // first element of the second one.
19364 for (unsigned i = 0; i != NumElems/2; ++i)
19365 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19366 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19369 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19370 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19371 if (Ld->hasNUsesOfValue(1, 0)) {
19372 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19373 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19375 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19377 Ld->getPointerInfo(),
19378 Ld->getAlignment(),
19379 false/*isVolatile*/, true/*ReadMem*/,
19380 false/*WriteMem*/);
19382 // Make sure the newly-created LOAD is in the same position as Ld in
19383 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19384 // and update uses of Ld's output chain to use the TokenFactor.
19385 if (Ld->hasAnyUseOfValue(1)) {
19386 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19387 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19388 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19389 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19390 SDValue(ResNode.getNode(), 1));
19393 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19397 // Emit a zeroed vector and insert the desired subvector on its
19399 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19400 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19401 return DCI.CombineTo(N, InsV);
19404 //===--------------------------------------------------------------------===//
19405 // Combine some shuffles into subvector extracts and inserts:
19408 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19409 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19410 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19411 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19412 return DCI.CombineTo(N, InsV);
19415 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19416 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19417 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19418 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19419 return DCI.CombineTo(N, InsV);
19425 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19428 /// This is the leaf of the recursive combinine below. When we have found some
19429 /// chain of single-use x86 shuffle instructions and accumulated the combined
19430 /// shuffle mask represented by them, this will try to pattern match that mask
19431 /// into either a single instruction if there is a special purpose instruction
19432 /// for this operation, or into a PSHUFB instruction which is a fully general
19433 /// instruction but should only be used to replace chains over a certain depth.
19434 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19435 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19436 TargetLowering::DAGCombinerInfo &DCI,
19437 const X86Subtarget *Subtarget) {
19438 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19440 // Find the operand that enters the chain. Note that multiple uses are OK
19441 // here, we're not going to remove the operand we find.
19442 SDValue Input = Op.getOperand(0);
19443 while (Input.getOpcode() == ISD::BITCAST)
19444 Input = Input.getOperand(0);
19446 MVT VT = Input.getSimpleValueType();
19447 MVT RootVT = Root.getSimpleValueType();
19450 // Just remove no-op shuffle masks.
19451 if (Mask.size() == 1) {
19452 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19457 // Use the float domain if the operand type is a floating point type.
19458 bool FloatDomain = VT.isFloatingPoint();
19460 // If we don't have access to VEX encodings, the generic PSHUF instructions
19461 // are preferable to some of the specialized forms despite requiring one more
19462 // byte to encode because they can implicitly copy.
19464 // IF we *do* have VEX encodings, than we can use shorter, more specific
19465 // shuffle instructions freely as they can copy due to the extra register
19467 if (Subtarget->hasAVX()) {
19468 // We have both floating point and integer variants of shuffles that dup
19469 // either the low or high half of the vector.
19470 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19471 bool Lo = Mask.equals(0, 0);
19472 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
19473 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
19474 if (Depth == 1 && Root->getOpcode() == Shuffle)
19475 return false; // Nothing to do!
19476 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
19477 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19478 DCI.AddToWorklist(Op.getNode());
19479 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19480 DCI.AddToWorklist(Op.getNode());
19481 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19486 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
19488 // For the integer domain we have specialized instructions for duplicating
19489 // any element size from the low or high half.
19490 if (!FloatDomain &&
19491 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
19492 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19493 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19494 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19495 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19497 bool Lo = Mask[0] == 0;
19498 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19499 if (Depth == 1 && Root->getOpcode() == Shuffle)
19500 return false; // Nothing to do!
19502 switch (Mask.size()) {
19503 case 4: ShuffleVT = MVT::v4i32; break;
19504 case 8: ShuffleVT = MVT::v8i16; break;
19505 case 16: ShuffleVT = MVT::v16i8; break;
19507 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19508 DCI.AddToWorklist(Op.getNode());
19509 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19510 DCI.AddToWorklist(Op.getNode());
19511 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19517 // Don't try to re-form single instruction chains under any circumstances now
19518 // that we've done encoding canonicalization for them.
19522 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19523 // can replace them with a single PSHUFB instruction profitably. Intel's
19524 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19525 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19526 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19527 SmallVector<SDValue, 16> PSHUFBMask;
19528 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19529 int Ratio = 16 / Mask.size();
19530 for (unsigned i = 0; i < 16; ++i) {
19531 int M = Mask[i / Ratio] != SM_SentinelZero
19532 ? Ratio * Mask[i / Ratio] + i % Ratio
19534 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19536 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19537 DCI.AddToWorklist(Op.getNode());
19538 SDValue PSHUFBMaskOp =
19539 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19540 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19541 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19542 DCI.AddToWorklist(Op.getNode());
19543 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19548 // Failed to find any combines.
19552 /// \brief Fully generic combining of x86 shuffle instructions.
19554 /// This should be the last combine run over the x86 shuffle instructions. Once
19555 /// they have been fully optimized, this will recursively consider all chains
19556 /// of single-use shuffle instructions, build a generic model of the cumulative
19557 /// shuffle operation, and check for simpler instructions which implement this
19558 /// operation. We use this primarily for two purposes:
19560 /// 1) Collapse generic shuffles to specialized single instructions when
19561 /// equivalent. In most cases, this is just an encoding size win, but
19562 /// sometimes we will collapse multiple generic shuffles into a single
19563 /// special-purpose shuffle.
19564 /// 2) Look for sequences of shuffle instructions with 3 or more total
19565 /// instructions, and replace them with the slightly more expensive SSSE3
19566 /// PSHUFB instruction if available. We do this as the last combining step
19567 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19568 /// a suitable short sequence of other instructions. The PHUFB will either
19569 /// use a register or have to read from memory and so is slightly (but only
19570 /// slightly) more expensive than the other shuffle instructions.
19572 /// Because this is inherently a quadratic operation (for each shuffle in
19573 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19574 /// This should never be an issue in practice as the shuffle lowering doesn't
19575 /// produce sequences of more than 8 instructions.
19577 /// FIXME: We will currently miss some cases where the redundant shuffling
19578 /// would simplify under the threshold for PSHUFB formation because of
19579 /// combine-ordering. To fix this, we should do the redundant instruction
19580 /// combining in this recursive walk.
19581 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19582 ArrayRef<int> RootMask,
19583 int Depth, bool HasPSHUFB,
19585 TargetLowering::DAGCombinerInfo &DCI,
19586 const X86Subtarget *Subtarget) {
19587 // Bound the depth of our recursive combine because this is ultimately
19588 // quadratic in nature.
19592 // Directly rip through bitcasts to find the underlying operand.
19593 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19594 Op = Op.getOperand(0);
19596 MVT VT = Op.getSimpleValueType();
19597 if (!VT.isVector())
19598 return false; // Bail if we hit a non-vector.
19599 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19600 // version should be added.
19601 if (VT.getSizeInBits() != 128)
19604 assert(Root.getSimpleValueType().isVector() &&
19605 "Shuffles operate on vector types!");
19606 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19607 "Can only combine shuffles of the same vector register size.");
19609 if (!isTargetShuffle(Op.getOpcode()))
19611 SmallVector<int, 16> OpMask;
19613 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19614 // We only can combine unary shuffles which we can decode the mask for.
19615 if (!HaveMask || !IsUnary)
19618 assert(VT.getVectorNumElements() == OpMask.size() &&
19619 "Different mask size from vector size!");
19620 assert(((RootMask.size() > OpMask.size() &&
19621 RootMask.size() % OpMask.size() == 0) ||
19622 (OpMask.size() > RootMask.size() &&
19623 OpMask.size() % RootMask.size() == 0) ||
19624 OpMask.size() == RootMask.size()) &&
19625 "The smaller number of elements must divide the larger.");
19626 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19627 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19628 assert(((RootRatio == 1 && OpRatio == 1) ||
19629 (RootRatio == 1) != (OpRatio == 1)) &&
19630 "Must not have a ratio for both incoming and op masks!");
19632 SmallVector<int, 16> Mask;
19633 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19635 // Merge this shuffle operation's mask into our accumulated mask. Note that
19636 // this shuffle's mask will be the first applied to the input, followed by the
19637 // root mask to get us all the way to the root value arrangement. The reason
19638 // for this order is that we are recursing up the operation chain.
19639 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19640 int RootIdx = i / RootRatio;
19641 if (RootMask[RootIdx] == SM_SentinelZero) {
19642 // This is a zero-ed lane, we're done.
19643 Mask.push_back(SM_SentinelZero);
19647 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19648 int OpIdx = RootMaskedIdx / OpRatio;
19649 if (OpMask[OpIdx] == SM_SentinelZero) {
19650 // The incoming lanes are zero, it doesn't matter which ones we are using.
19651 Mask.push_back(SM_SentinelZero);
19655 // Ok, we have non-zero lanes, map them through.
19656 Mask.push_back(OpMask[OpIdx] * OpRatio +
19657 RootMaskedIdx % OpRatio);
19660 // See if we can recurse into the operand to combine more things.
19661 switch (Op.getOpcode()) {
19662 case X86ISD::PSHUFB:
19664 case X86ISD::PSHUFD:
19665 case X86ISD::PSHUFHW:
19666 case X86ISD::PSHUFLW:
19667 if (Op.getOperand(0).hasOneUse() &&
19668 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19669 HasPSHUFB, DAG, DCI, Subtarget))
19673 case X86ISD::UNPCKL:
19674 case X86ISD::UNPCKH:
19675 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19676 // We can't check for single use, we have to check that this shuffle is the only user.
19677 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19678 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19679 HasPSHUFB, DAG, DCI, Subtarget))
19684 // Minor canonicalization of the accumulated shuffle mask to make it easier
19685 // to match below. All this does is detect masks with squential pairs of
19686 // elements, and shrink them to the half-width mask. It does this in a loop
19687 // so it will reduce the size of the mask to the minimal width mask which
19688 // performs an equivalent shuffle.
19689 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
19690 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
19691 Mask[i] = Mask[2 * i] / 2;
19692 Mask.resize(Mask.size() / 2);
19695 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19699 /// \brief Get the PSHUF-style mask from PSHUF node.
19701 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19702 /// PSHUF-style masks that can be reused with such instructions.
19703 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19704 SmallVector<int, 4> Mask;
19706 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19710 switch (N.getOpcode()) {
19711 case X86ISD::PSHUFD:
19713 case X86ISD::PSHUFLW:
19716 case X86ISD::PSHUFHW:
19717 Mask.erase(Mask.begin(), Mask.begin() + 4);
19718 for (int &M : Mask)
19722 llvm_unreachable("No valid shuffle instruction found!");
19726 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19728 /// We walk up the chain and look for a combinable shuffle, skipping over
19729 /// shuffles that we could hoist this shuffle's transformation past without
19730 /// altering anything.
19731 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19733 TargetLowering::DAGCombinerInfo &DCI) {
19734 assert(N.getOpcode() == X86ISD::PSHUFD &&
19735 "Called with something other than an x86 128-bit half shuffle!");
19738 // Walk up a single-use chain looking for a combinable shuffle.
19739 SDValue V = N.getOperand(0);
19740 for (; V.hasOneUse(); V = V.getOperand(0)) {
19741 switch (V.getOpcode()) {
19743 return false; // Nothing combined!
19746 // Skip bitcasts as we always know the type for the target specific
19750 case X86ISD::PSHUFD:
19751 // Found another dword shuffle.
19754 case X86ISD::PSHUFLW:
19755 // Check that the low words (being shuffled) are the identity in the
19756 // dword shuffle, and the high words are self-contained.
19757 if (Mask[0] != 0 || Mask[1] != 1 ||
19758 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19763 case X86ISD::PSHUFHW:
19764 // Check that the high words (being shuffled) are the identity in the
19765 // dword shuffle, and the low words are self-contained.
19766 if (Mask[2] != 2 || Mask[3] != 3 ||
19767 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19772 case X86ISD::UNPCKL:
19773 case X86ISD::UNPCKH:
19774 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19775 // shuffle into a preceding word shuffle.
19776 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19779 // Search for a half-shuffle which we can combine with.
19780 unsigned CombineOp =
19781 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19782 if (V.getOperand(0) != V.getOperand(1) ||
19783 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19785 V = V.getOperand(0);
19787 switch (V.getOpcode()) {
19789 return false; // Nothing to combine.
19791 case X86ISD::PSHUFLW:
19792 case X86ISD::PSHUFHW:
19793 if (V.getOpcode() == CombineOp)
19798 V = V.getOperand(0);
19802 } while (V.hasOneUse());
19805 // Break out of the loop if we break out of the switch.
19809 if (!V.hasOneUse())
19810 // We fell out of the loop without finding a viable combining instruction.
19813 // Record the old value to use in RAUW-ing.
19816 // Merge this node's mask and our incoming mask.
19817 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19818 for (int &M : Mask)
19820 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19821 getV4X86ShuffleImm8ForMask(Mask, DAG));
19823 // It is possible that one of the combinable shuffles was completely absorbed
19824 // by the other, just replace it and revisit all users in that case.
19825 if (Old.getNode() == V.getNode()) {
19826 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
19830 // Replace N with its operand as we're going to combine that shuffle away.
19831 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
19833 // Replace the combinable shuffle with the combined one, updating all users
19834 // so that we re-evaluate the chain here.
19835 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19839 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19841 /// We walk up the chain, skipping shuffles of the other half and looking
19842 /// through shuffles which switch halves trying to find a shuffle of the same
19843 /// pair of dwords.
19844 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19846 TargetLowering::DAGCombinerInfo &DCI) {
19848 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19849 "Called with something other than an x86 128-bit half shuffle!");
19851 unsigned CombineOpcode = N.getOpcode();
19853 // Walk up a single-use chain looking for a combinable shuffle.
19854 SDValue V = N.getOperand(0);
19855 for (; V.hasOneUse(); V = V.getOperand(0)) {
19856 switch (V.getOpcode()) {
19858 return false; // Nothing combined!
19861 // Skip bitcasts as we always know the type for the target specific
19865 case X86ISD::PSHUFLW:
19866 case X86ISD::PSHUFHW:
19867 if (V.getOpcode() == CombineOpcode)
19870 // Other-half shuffles are no-ops.
19873 // Break out of the loop if we break out of the switch.
19877 if (!V.hasOneUse())
19878 // We fell out of the loop without finding a viable combining instruction.
19881 // Combine away the bottom node as its shuffle will be accumulated into
19882 // a preceding shuffle.
19883 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19885 // Record the old value.
19888 // Merge this node's mask and our incoming mask (adjusted to account for all
19889 // the pshufd instructions encountered).
19890 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19891 for (int &M : Mask)
19893 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19894 getV4X86ShuffleImm8ForMask(Mask, DAG));
19896 // Check that the shuffles didn't cancel each other out. If not, we need to
19897 // combine to the new one.
19899 // Replace the combinable shuffle with the combined one, updating all users
19900 // so that we re-evaluate the chain here.
19901 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19906 /// \brief Try to combine x86 target specific shuffles.
19907 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19908 TargetLowering::DAGCombinerInfo &DCI,
19909 const X86Subtarget *Subtarget) {
19911 MVT VT = N.getSimpleValueType();
19912 SmallVector<int, 4> Mask;
19914 switch (N.getOpcode()) {
19915 case X86ISD::PSHUFD:
19916 case X86ISD::PSHUFLW:
19917 case X86ISD::PSHUFHW:
19918 Mask = getPSHUFShuffleMask(N);
19919 assert(Mask.size() == 4);
19925 // Nuke no-op shuffles that show up after combining.
19926 if (isNoopShuffleMask(Mask))
19927 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19929 // Look for simplifications involving one or two shuffle instructions.
19930 SDValue V = N.getOperand(0);
19931 switch (N.getOpcode()) {
19934 case X86ISD::PSHUFLW:
19935 case X86ISD::PSHUFHW:
19936 assert(VT == MVT::v8i16);
19939 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19940 return SDValue(); // We combined away this shuffle, so we're done.
19942 // See if this reduces to a PSHUFD which is no more expensive and can
19943 // combine with more operations.
19944 if (canWidenShuffleElements(Mask)) {
19945 int DMask[] = {-1, -1, -1, -1};
19946 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19947 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19948 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19949 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19950 DCI.AddToWorklist(V.getNode());
19951 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19952 getV4X86ShuffleImm8ForMask(DMask, DAG));
19953 DCI.AddToWorklist(V.getNode());
19954 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19957 // Look for shuffle patterns which can be implemented as a single unpack.
19958 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19959 // only works when we have a PSHUFD followed by two half-shuffles.
19960 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19961 (V.getOpcode() == X86ISD::PSHUFLW ||
19962 V.getOpcode() == X86ISD::PSHUFHW) &&
19963 V.getOpcode() != N.getOpcode() &&
19965 SDValue D = V.getOperand(0);
19966 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19967 D = D.getOperand(0);
19968 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19969 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19970 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19971 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19972 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19974 for (int i = 0; i < 4; ++i) {
19975 WordMask[i + NOffset] = Mask[i] + NOffset;
19976 WordMask[i + VOffset] = VMask[i] + VOffset;
19978 // Map the word mask through the DWord mask.
19980 for (int i = 0; i < 8; ++i)
19981 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19982 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19983 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19984 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19985 std::begin(UnpackLoMask)) ||
19986 std::equal(std::begin(MappedMask), std::end(MappedMask),
19987 std::begin(UnpackHiMask))) {
19988 // We can replace all three shuffles with an unpack.
19989 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19990 DCI.AddToWorklist(V.getNode());
19991 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19993 DL, MVT::v8i16, V, V);
20000 case X86ISD::PSHUFD:
20001 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20002 return SDValue(); // We combined away this shuffle.
20010 /// PerformShuffleCombine - Performs several different shuffle combines.
20011 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20012 TargetLowering::DAGCombinerInfo &DCI,
20013 const X86Subtarget *Subtarget) {
20015 SDValue N0 = N->getOperand(0);
20016 SDValue N1 = N->getOperand(1);
20017 EVT VT = N->getValueType(0);
20019 // Don't create instructions with illegal types after legalize types has run.
20020 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20021 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20024 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20025 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20026 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20027 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20029 // During Type Legalization, when promoting illegal vector types,
20030 // the backend might introduce new shuffle dag nodes and bitcasts.
20032 // This code performs the following transformation:
20033 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20034 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20036 // We do this only if both the bitcast and the BINOP dag nodes have
20037 // one use. Also, perform this transformation only if the new binary
20038 // operation is legal. This is to avoid introducing dag nodes that
20039 // potentially need to be further expanded (or custom lowered) into a
20040 // less optimal sequence of dag nodes.
20041 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20042 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20043 N0.getOpcode() == ISD::BITCAST) {
20044 SDValue BC0 = N0.getOperand(0);
20045 EVT SVT = BC0.getValueType();
20046 unsigned Opcode = BC0.getOpcode();
20047 unsigned NumElts = VT.getVectorNumElements();
20049 if (BC0.hasOneUse() && SVT.isVector() &&
20050 SVT.getVectorNumElements() * 2 == NumElts &&
20051 TLI.isOperationLegal(Opcode, VT)) {
20052 bool CanFold = false;
20064 unsigned SVTNumElts = SVT.getVectorNumElements();
20065 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20066 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20067 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20068 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20069 CanFold = SVOp->getMaskElt(i) < 0;
20072 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20073 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20074 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20075 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20080 // Only handle 128 wide vector from here on.
20081 if (!VT.is128BitVector())
20084 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20085 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20086 // consecutive, non-overlapping, and in the right order.
20087 SmallVector<SDValue, 16> Elts;
20088 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20089 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20091 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20095 if (isTargetShuffle(N->getOpcode())) {
20097 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20098 if (Shuffle.getNode())
20101 // Try recursively combining arbitrary sequences of x86 shuffle
20102 // instructions into higher-order shuffles. We do this after combining
20103 // specific PSHUF instruction sequences into their minimal form so that we
20104 // can evaluate how many specialized shuffle instructions are involved in
20105 // a particular chain.
20106 SmallVector<int, 1> NonceMask; // Just a placeholder.
20107 NonceMask.push_back(0);
20108 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20109 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20111 return SDValue(); // This routine will use CombineTo to replace N.
20117 /// PerformTruncateCombine - Converts truncate operation to
20118 /// a sequence of vector shuffle operations.
20119 /// It is possible when we truncate 256-bit vector to 128-bit vector
20120 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20121 TargetLowering::DAGCombinerInfo &DCI,
20122 const X86Subtarget *Subtarget) {
20126 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20127 /// specific shuffle of a load can be folded into a single element load.
20128 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20129 /// shuffles have been customed lowered so we need to handle those here.
20130 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20131 TargetLowering::DAGCombinerInfo &DCI) {
20132 if (DCI.isBeforeLegalizeOps())
20135 SDValue InVec = N->getOperand(0);
20136 SDValue EltNo = N->getOperand(1);
20138 if (!isa<ConstantSDNode>(EltNo))
20141 EVT VT = InVec.getValueType();
20143 bool HasShuffleIntoBitcast = false;
20144 if (InVec.getOpcode() == ISD::BITCAST) {
20145 // Don't duplicate a load with other uses.
20146 if (!InVec.hasOneUse())
20148 EVT BCVT = InVec.getOperand(0).getValueType();
20149 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20151 InVec = InVec.getOperand(0);
20152 HasShuffleIntoBitcast = true;
20155 if (!isTargetShuffle(InVec.getOpcode()))
20158 // Don't duplicate a load with other uses.
20159 if (!InVec.hasOneUse())
20162 SmallVector<int, 16> ShuffleMask;
20164 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20168 // Select the input vector, guarding against out of range extract vector.
20169 unsigned NumElems = VT.getVectorNumElements();
20170 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20171 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20172 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20173 : InVec.getOperand(1);
20175 // If inputs to shuffle are the same for both ops, then allow 2 uses
20176 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20178 if (LdNode.getOpcode() == ISD::BITCAST) {
20179 // Don't duplicate a load with other uses.
20180 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20183 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20184 LdNode = LdNode.getOperand(0);
20187 if (!ISD::isNormalLoad(LdNode.getNode()))
20190 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20192 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20195 if (HasShuffleIntoBitcast) {
20196 // If there's a bitcast before the shuffle, check if the load type and
20197 // alignment is valid.
20198 unsigned Align = LN0->getAlignment();
20199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20200 unsigned NewAlign = TLI.getDataLayout()->
20201 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
20203 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
20207 // All checks match so transform back to vector_shuffle so that DAG combiner
20208 // can finish the job
20211 // Create shuffle node taking into account the case that its a unary shuffle
20212 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20213 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20214 InVec.getOperand(0), Shuffle,
20216 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20217 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20221 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20222 /// generation and convert it from being a bunch of shuffles and extracts
20223 /// to a simple store and scalar loads to extract the elements.
20224 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20225 TargetLowering::DAGCombinerInfo &DCI) {
20226 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20227 if (NewOp.getNode())
20230 SDValue InputVector = N->getOperand(0);
20232 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20233 // from mmx to v2i32 has a single usage.
20234 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20235 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20236 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20237 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20238 N->getValueType(0),
20239 InputVector.getNode()->getOperand(0));
20241 // Only operate on vectors of 4 elements, where the alternative shuffling
20242 // gets to be more expensive.
20243 if (InputVector.getValueType() != MVT::v4i32)
20246 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20247 // single use which is a sign-extend or zero-extend, and all elements are
20249 SmallVector<SDNode *, 4> Uses;
20250 unsigned ExtractedElements = 0;
20251 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20252 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20253 if (UI.getUse().getResNo() != InputVector.getResNo())
20256 SDNode *Extract = *UI;
20257 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20260 if (Extract->getValueType(0) != MVT::i32)
20262 if (!Extract->hasOneUse())
20264 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20265 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20267 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20270 // Record which element was extracted.
20271 ExtractedElements |=
20272 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20274 Uses.push_back(Extract);
20277 // If not all the elements were used, this may not be worthwhile.
20278 if (ExtractedElements != 15)
20281 // Ok, we've now decided to do the transformation.
20282 SDLoc dl(InputVector);
20284 // Store the value to a temporary stack slot.
20285 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20286 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20287 MachinePointerInfo(), false, false, 0);
20289 // Replace each use (extract) with a load of the appropriate element.
20290 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20291 UE = Uses.end(); UI != UE; ++UI) {
20292 SDNode *Extract = *UI;
20294 // cOMpute the element's address.
20295 SDValue Idx = Extract->getOperand(1);
20297 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20298 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20299 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20300 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20302 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20303 StackPtr, OffsetVal);
20305 // Load the scalar.
20306 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20307 ScalarAddr, MachinePointerInfo(),
20308 false, false, false, 0);
20310 // Replace the exact with the load.
20311 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20314 // The replacement was made in place; don't return anything.
20318 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20319 static std::pair<unsigned, bool>
20320 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20321 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20322 if (!VT.isVector())
20323 return std::make_pair(0, false);
20325 bool NeedSplit = false;
20326 switch (VT.getSimpleVT().SimpleTy) {
20327 default: return std::make_pair(0, false);
20331 if (!Subtarget->hasAVX2())
20333 if (!Subtarget->hasAVX())
20334 return std::make_pair(0, false);
20339 if (!Subtarget->hasSSE2())
20340 return std::make_pair(0, false);
20343 // SSE2 has only a small subset of the operations.
20344 bool hasUnsigned = Subtarget->hasSSE41() ||
20345 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20346 bool hasSigned = Subtarget->hasSSE41() ||
20347 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20349 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20352 // Check for x CC y ? x : y.
20353 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20354 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20359 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20362 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20365 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20368 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20370 // Check for x CC y ? y : x -- a min/max with reversed arms.
20371 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20372 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20377 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20380 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20383 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20386 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20390 return std::make_pair(Opc, NeedSplit);
20394 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20395 const X86Subtarget *Subtarget) {
20397 SDValue Cond = N->getOperand(0);
20398 SDValue LHS = N->getOperand(1);
20399 SDValue RHS = N->getOperand(2);
20401 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20402 SDValue CondSrc = Cond->getOperand(0);
20403 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20404 Cond = CondSrc->getOperand(0);
20407 MVT VT = N->getSimpleValueType(0);
20408 MVT EltVT = VT.getVectorElementType();
20409 unsigned NumElems = VT.getVectorNumElements();
20410 // There is no blend with immediate in AVX-512.
20411 if (VT.is512BitVector())
20414 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20416 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20419 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20422 unsigned MaskValue = 0;
20423 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20426 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20427 for (unsigned i = 0; i < NumElems; ++i) {
20428 // Be sure we emit undef where we can.
20429 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20430 ShuffleMask[i] = -1;
20432 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20435 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20438 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20440 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20441 TargetLowering::DAGCombinerInfo &DCI,
20442 const X86Subtarget *Subtarget) {
20444 SDValue Cond = N->getOperand(0);
20445 // Get the LHS/RHS of the select.
20446 SDValue LHS = N->getOperand(1);
20447 SDValue RHS = N->getOperand(2);
20448 EVT VT = LHS.getValueType();
20449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20451 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20452 // instructions match the semantics of the common C idiom x<y?x:y but not
20453 // x<=y?x:y, because of how they handle negative zero (which can be
20454 // ignored in unsafe-math mode).
20455 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20456 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20457 (Subtarget->hasSSE2() ||
20458 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20459 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20461 unsigned Opcode = 0;
20462 // Check for x CC y ? x : y.
20463 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20464 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20468 // Converting this to a min would handle NaNs incorrectly, and swapping
20469 // the operands would cause it to handle comparisons between positive
20470 // and negative zero incorrectly.
20471 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20472 if (!DAG.getTarget().Options.UnsafeFPMath &&
20473 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20475 std::swap(LHS, RHS);
20477 Opcode = X86ISD::FMIN;
20480 // Converting this to a min would handle comparisons between positive
20481 // and negative zero incorrectly.
20482 if (!DAG.getTarget().Options.UnsafeFPMath &&
20483 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20485 Opcode = X86ISD::FMIN;
20488 // Converting this to a min would handle both negative zeros and NaNs
20489 // incorrectly, but we can swap the operands to fix both.
20490 std::swap(LHS, RHS);
20494 Opcode = X86ISD::FMIN;
20498 // Converting this to a max would handle comparisons between positive
20499 // and negative zero incorrectly.
20500 if (!DAG.getTarget().Options.UnsafeFPMath &&
20501 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20503 Opcode = X86ISD::FMAX;
20506 // Converting this to a max would handle NaNs incorrectly, and swapping
20507 // the operands would cause it to handle comparisons between positive
20508 // and negative zero incorrectly.
20509 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20510 if (!DAG.getTarget().Options.UnsafeFPMath &&
20511 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20513 std::swap(LHS, RHS);
20515 Opcode = X86ISD::FMAX;
20518 // Converting this to a max would handle both negative zeros and NaNs
20519 // incorrectly, but we can swap the operands to fix both.
20520 std::swap(LHS, RHS);
20524 Opcode = X86ISD::FMAX;
20527 // Check for x CC y ? y : x -- a min/max with reversed arms.
20528 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20529 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20533 // Converting this to a min would handle comparisons between positive
20534 // and negative zero incorrectly, and swapping the operands would
20535 // cause it to handle NaNs incorrectly.
20536 if (!DAG.getTarget().Options.UnsafeFPMath &&
20537 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20538 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20540 std::swap(LHS, RHS);
20542 Opcode = X86ISD::FMIN;
20545 // Converting this to a min would handle NaNs incorrectly.
20546 if (!DAG.getTarget().Options.UnsafeFPMath &&
20547 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20549 Opcode = X86ISD::FMIN;
20552 // Converting this to a min would handle both negative zeros and NaNs
20553 // incorrectly, but we can swap the operands to fix both.
20554 std::swap(LHS, RHS);
20558 Opcode = X86ISD::FMIN;
20562 // Converting this to a max would handle NaNs incorrectly.
20563 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20565 Opcode = X86ISD::FMAX;
20568 // Converting this to a max would handle comparisons between positive
20569 // and negative zero incorrectly, and swapping the operands would
20570 // cause it to handle NaNs incorrectly.
20571 if (!DAG.getTarget().Options.UnsafeFPMath &&
20572 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20573 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20575 std::swap(LHS, RHS);
20577 Opcode = X86ISD::FMAX;
20580 // Converting this to a max would handle both negative zeros and NaNs
20581 // incorrectly, but we can swap the operands to fix both.
20582 std::swap(LHS, RHS);
20586 Opcode = X86ISD::FMAX;
20592 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20595 EVT CondVT = Cond.getValueType();
20596 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20597 CondVT.getVectorElementType() == MVT::i1) {
20598 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20599 // lowering on AVX-512. In this case we convert it to
20600 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20601 // The same situation for all 128 and 256-bit vectors of i8 and i16
20602 EVT OpVT = LHS.getValueType();
20603 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20604 (OpVT.getVectorElementType() == MVT::i8 ||
20605 OpVT.getVectorElementType() == MVT::i16)) {
20606 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20607 DCI.AddToWorklist(Cond.getNode());
20608 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20611 // If this is a select between two integer constants, try to do some
20613 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20614 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20615 // Don't do this for crazy integer types.
20616 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20617 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20618 // so that TrueC (the true value) is larger than FalseC.
20619 bool NeedsCondInvert = false;
20621 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20622 // Efficiently invertible.
20623 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20624 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20625 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20626 NeedsCondInvert = true;
20627 std::swap(TrueC, FalseC);
20630 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20631 if (FalseC->getAPIntValue() == 0 &&
20632 TrueC->getAPIntValue().isPowerOf2()) {
20633 if (NeedsCondInvert) // Invert the condition if needed.
20634 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20635 DAG.getConstant(1, Cond.getValueType()));
20637 // Zero extend the condition if needed.
20638 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20640 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20641 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20642 DAG.getConstant(ShAmt, MVT::i8));
20645 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20646 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20647 if (NeedsCondInvert) // Invert the condition if needed.
20648 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20649 DAG.getConstant(1, Cond.getValueType()));
20651 // Zero extend the condition if needed.
20652 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20653 FalseC->getValueType(0), Cond);
20654 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20655 SDValue(FalseC, 0));
20658 // Optimize cases that will turn into an LEA instruction. This requires
20659 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20660 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20661 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20662 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20664 bool isFastMultiplier = false;
20666 switch ((unsigned char)Diff) {
20668 case 1: // result = add base, cond
20669 case 2: // result = lea base( , cond*2)
20670 case 3: // result = lea base(cond, cond*2)
20671 case 4: // result = lea base( , cond*4)
20672 case 5: // result = lea base(cond, cond*4)
20673 case 8: // result = lea base( , cond*8)
20674 case 9: // result = lea base(cond, cond*8)
20675 isFastMultiplier = true;
20680 if (isFastMultiplier) {
20681 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20682 if (NeedsCondInvert) // Invert the condition if needed.
20683 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20684 DAG.getConstant(1, Cond.getValueType()));
20686 // Zero extend the condition if needed.
20687 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20689 // Scale the condition by the difference.
20691 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20692 DAG.getConstant(Diff, Cond.getValueType()));
20694 // Add the base if non-zero.
20695 if (FalseC->getAPIntValue() != 0)
20696 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20697 SDValue(FalseC, 0));
20704 // Canonicalize max and min:
20705 // (x > y) ? x : y -> (x >= y) ? x : y
20706 // (x < y) ? x : y -> (x <= y) ? x : y
20707 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20708 // the need for an extra compare
20709 // against zero. e.g.
20710 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20712 // testl %edi, %edi
20714 // cmovgl %edi, %eax
20718 // cmovsl %eax, %edi
20719 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20720 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20721 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20722 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20727 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20728 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20729 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20730 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20735 // Early exit check
20736 if (!TLI.isTypeLegal(VT))
20739 // Match VSELECTs into subs with unsigned saturation.
20740 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20741 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20742 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20743 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20744 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20746 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20747 // left side invert the predicate to simplify logic below.
20749 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20751 CC = ISD::getSetCCInverse(CC, true);
20752 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20756 if (Other.getNode() && Other->getNumOperands() == 2 &&
20757 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20758 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20759 SDValue CondRHS = Cond->getOperand(1);
20761 // Look for a general sub with unsigned saturation first.
20762 // x >= y ? x-y : 0 --> subus x, y
20763 // x > y ? x-y : 0 --> subus x, y
20764 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20765 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20766 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20768 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20769 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20770 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20771 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20772 // If the RHS is a constant we have to reverse the const
20773 // canonicalization.
20774 // x > C-1 ? x+-C : 0 --> subus x, C
20775 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20776 CondRHSConst->getAPIntValue() ==
20777 (-OpRHSConst->getAPIntValue() - 1))
20778 return DAG.getNode(
20779 X86ISD::SUBUS, DL, VT, OpLHS,
20780 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20782 // Another special case: If C was a sign bit, the sub has been
20783 // canonicalized into a xor.
20784 // FIXME: Would it be better to use computeKnownBits to determine
20785 // whether it's safe to decanonicalize the xor?
20786 // x s< 0 ? x^C : 0 --> subus x, C
20787 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20788 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20789 OpRHSConst->getAPIntValue().isSignBit())
20790 // Note that we have to rebuild the RHS constant here to ensure we
20791 // don't rely on particular values of undef lanes.
20792 return DAG.getNode(
20793 X86ISD::SUBUS, DL, VT, OpLHS,
20794 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20799 // Try to match a min/max vector operation.
20800 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20801 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20802 unsigned Opc = ret.first;
20803 bool NeedSplit = ret.second;
20805 if (Opc && NeedSplit) {
20806 unsigned NumElems = VT.getVectorNumElements();
20807 // Extract the LHS vectors
20808 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20809 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20811 // Extract the RHS vectors
20812 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20813 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20815 // Create min/max for each subvector
20816 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20817 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20819 // Merge the result
20820 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20822 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20825 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20826 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20827 // Check if SETCC has already been promoted
20828 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20829 // Check that condition value type matches vselect operand type
20832 assert(Cond.getValueType().isVector() &&
20833 "vector select expects a vector selector!");
20835 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20836 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20838 if (!TValIsAllOnes && !FValIsAllZeros) {
20839 // Try invert the condition if true value is not all 1s and false value
20841 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20842 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20844 if (TValIsAllZeros || FValIsAllOnes) {
20845 SDValue CC = Cond.getOperand(2);
20846 ISD::CondCode NewCC =
20847 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20848 Cond.getOperand(0).getValueType().isInteger());
20849 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20850 std::swap(LHS, RHS);
20851 TValIsAllOnes = FValIsAllOnes;
20852 FValIsAllZeros = TValIsAllZeros;
20856 if (TValIsAllOnes || FValIsAllZeros) {
20859 if (TValIsAllOnes && FValIsAllZeros)
20861 else if (TValIsAllOnes)
20862 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20863 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20864 else if (FValIsAllZeros)
20865 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20866 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20868 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20872 // Try to fold this VSELECT into a MOVSS/MOVSD
20873 if (N->getOpcode() == ISD::VSELECT &&
20874 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20875 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20876 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20877 bool CanFold = false;
20878 unsigned NumElems = Cond.getNumOperands();
20882 if (isZero(Cond.getOperand(0))) {
20885 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20886 // fold (vselect <0,-1> -> (movsd A, B)
20887 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20888 CanFold = isAllOnes(Cond.getOperand(i));
20889 } else if (isAllOnes(Cond.getOperand(0))) {
20893 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20894 // fold (vselect <-1,0> -> (movsd B, A)
20895 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20896 CanFold = isZero(Cond.getOperand(i));
20900 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20901 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20902 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20905 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20906 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20907 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20908 // (v2i64 (bitcast B)))))
20910 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20911 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20912 // (v2f64 (bitcast B)))))
20914 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20915 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20916 // (v2i64 (bitcast A)))))
20918 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20919 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20920 // (v2f64 (bitcast A)))))
20922 CanFold = (isZero(Cond.getOperand(0)) &&
20923 isZero(Cond.getOperand(1)) &&
20924 isAllOnes(Cond.getOperand(2)) &&
20925 isAllOnes(Cond.getOperand(3)));
20927 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20928 isAllOnes(Cond.getOperand(1)) &&
20929 isZero(Cond.getOperand(2)) &&
20930 isZero(Cond.getOperand(3))) {
20932 std::swap(LHS, RHS);
20936 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20937 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20938 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20939 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20941 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20947 // If we know that this node is legal then we know that it is going to be
20948 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20949 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20950 // to simplify previous instructions.
20951 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20952 !DCI.isBeforeLegalize() &&
20953 // We explicitly check against v8i16 and v16i16 because, although
20954 // they're marked as Custom, they might only be legal when Cond is a
20955 // build_vector of constants. This will be taken care in a later
20957 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20958 VT != MVT::v8i16)) {
20959 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20961 // Don't optimize vector selects that map to mask-registers.
20965 // Check all uses of that condition operand to check whether it will be
20966 // consumed by non-BLEND instructions, which may depend on all bits are set
20968 for (SDNode::use_iterator I = Cond->use_begin(),
20969 E = Cond->use_end(); I != E; ++I)
20970 if (I->getOpcode() != ISD::VSELECT)
20971 // TODO: Add other opcodes eventually lowered into BLEND.
20974 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20975 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20977 APInt KnownZero, KnownOne;
20978 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20979 DCI.isBeforeLegalizeOps());
20980 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20981 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20982 DCI.CommitTargetLoweringOpt(TLO);
20985 // We should generate an X86ISD::BLENDI from a vselect if its argument
20986 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20987 // constants. This specific pattern gets generated when we split a
20988 // selector for a 512 bit vector in a machine without AVX512 (but with
20989 // 256-bit vectors), during legalization:
20991 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20993 // Iff we find this pattern and the build_vectors are built from
20994 // constants, we translate the vselect into a shuffle_vector that we
20995 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20996 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20997 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20998 if (Shuffle.getNode())
21005 // Check whether a boolean test is testing a boolean value generated by
21006 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21009 // Simplify the following patterns:
21010 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21011 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21012 // to (Op EFLAGS Cond)
21014 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21015 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21016 // to (Op EFLAGS !Cond)
21018 // where Op could be BRCOND or CMOV.
21020 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21021 // Quit if not CMP and SUB with its value result used.
21022 if (Cmp.getOpcode() != X86ISD::CMP &&
21023 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21026 // Quit if not used as a boolean value.
21027 if (CC != X86::COND_E && CC != X86::COND_NE)
21030 // Check CMP operands. One of them should be 0 or 1 and the other should be
21031 // an SetCC or extended from it.
21032 SDValue Op1 = Cmp.getOperand(0);
21033 SDValue Op2 = Cmp.getOperand(1);
21036 const ConstantSDNode* C = nullptr;
21037 bool needOppositeCond = (CC == X86::COND_E);
21038 bool checkAgainstTrue = false; // Is it a comparison against 1?
21040 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21042 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21044 else // Quit if all operands are not constants.
21047 if (C->getZExtValue() == 1) {
21048 needOppositeCond = !needOppositeCond;
21049 checkAgainstTrue = true;
21050 } else if (C->getZExtValue() != 0)
21051 // Quit if the constant is neither 0 or 1.
21054 bool truncatedToBoolWithAnd = false;
21055 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21056 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21057 SetCC.getOpcode() == ISD::TRUNCATE ||
21058 SetCC.getOpcode() == ISD::AND) {
21059 if (SetCC.getOpcode() == ISD::AND) {
21061 ConstantSDNode *CS;
21062 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21063 CS->getZExtValue() == 1)
21065 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21066 CS->getZExtValue() == 1)
21070 SetCC = SetCC.getOperand(OpIdx);
21071 truncatedToBoolWithAnd = true;
21073 SetCC = SetCC.getOperand(0);
21076 switch (SetCC.getOpcode()) {
21077 case X86ISD::SETCC_CARRY:
21078 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21079 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21080 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21081 // truncated to i1 using 'and'.
21082 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21084 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21085 "Invalid use of SETCC_CARRY!");
21087 case X86ISD::SETCC:
21088 // Set the condition code or opposite one if necessary.
21089 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21090 if (needOppositeCond)
21091 CC = X86::GetOppositeBranchCondition(CC);
21092 return SetCC.getOperand(1);
21093 case X86ISD::CMOV: {
21094 // Check whether false/true value has canonical one, i.e. 0 or 1.
21095 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21096 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21097 // Quit if true value is not a constant.
21100 // Quit if false value is not a constant.
21102 SDValue Op = SetCC.getOperand(0);
21103 // Skip 'zext' or 'trunc' node.
21104 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21105 Op.getOpcode() == ISD::TRUNCATE)
21106 Op = Op.getOperand(0);
21107 // A special case for rdrand/rdseed, where 0 is set if false cond is
21109 if ((Op.getOpcode() != X86ISD::RDRAND &&
21110 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21113 // Quit if false value is not the constant 0 or 1.
21114 bool FValIsFalse = true;
21115 if (FVal && FVal->getZExtValue() != 0) {
21116 if (FVal->getZExtValue() != 1)
21118 // If FVal is 1, opposite cond is needed.
21119 needOppositeCond = !needOppositeCond;
21120 FValIsFalse = false;
21122 // Quit if TVal is not the constant opposite of FVal.
21123 if (FValIsFalse && TVal->getZExtValue() != 1)
21125 if (!FValIsFalse && TVal->getZExtValue() != 0)
21127 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21128 if (needOppositeCond)
21129 CC = X86::GetOppositeBranchCondition(CC);
21130 return SetCC.getOperand(3);
21137 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21138 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21139 TargetLowering::DAGCombinerInfo &DCI,
21140 const X86Subtarget *Subtarget) {
21143 // If the flag operand isn't dead, don't touch this CMOV.
21144 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21147 SDValue FalseOp = N->getOperand(0);
21148 SDValue TrueOp = N->getOperand(1);
21149 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21150 SDValue Cond = N->getOperand(3);
21152 if (CC == X86::COND_E || CC == X86::COND_NE) {
21153 switch (Cond.getOpcode()) {
21157 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21158 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21159 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21165 Flags = checkBoolTestSetCCCombine(Cond, CC);
21166 if (Flags.getNode() &&
21167 // Extra check as FCMOV only supports a subset of X86 cond.
21168 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21169 SDValue Ops[] = { FalseOp, TrueOp,
21170 DAG.getConstant(CC, MVT::i8), Flags };
21171 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21174 // If this is a select between two integer constants, try to do some
21175 // optimizations. Note that the operands are ordered the opposite of SELECT
21177 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21178 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21179 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21180 // larger than FalseC (the false value).
21181 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21182 CC = X86::GetOppositeBranchCondition(CC);
21183 std::swap(TrueC, FalseC);
21184 std::swap(TrueOp, FalseOp);
21187 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21188 // This is efficient for any integer data type (including i8/i16) and
21190 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21191 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21192 DAG.getConstant(CC, MVT::i8), Cond);
21194 // Zero extend the condition if needed.
21195 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21197 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21198 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21199 DAG.getConstant(ShAmt, MVT::i8));
21200 if (N->getNumValues() == 2) // Dead flag value?
21201 return DCI.CombineTo(N, Cond, SDValue());
21205 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21206 // for any integer data type, including i8/i16.
21207 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21208 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21209 DAG.getConstant(CC, MVT::i8), Cond);
21211 // Zero extend the condition if needed.
21212 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21213 FalseC->getValueType(0), Cond);
21214 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21215 SDValue(FalseC, 0));
21217 if (N->getNumValues() == 2) // Dead flag value?
21218 return DCI.CombineTo(N, Cond, SDValue());
21222 // Optimize cases that will turn into an LEA instruction. This requires
21223 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21224 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21225 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21226 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21228 bool isFastMultiplier = false;
21230 switch ((unsigned char)Diff) {
21232 case 1: // result = add base, cond
21233 case 2: // result = lea base( , cond*2)
21234 case 3: // result = lea base(cond, cond*2)
21235 case 4: // result = lea base( , cond*4)
21236 case 5: // result = lea base(cond, cond*4)
21237 case 8: // result = lea base( , cond*8)
21238 case 9: // result = lea base(cond, cond*8)
21239 isFastMultiplier = true;
21244 if (isFastMultiplier) {
21245 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21246 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21247 DAG.getConstant(CC, MVT::i8), Cond);
21248 // Zero extend the condition if needed.
21249 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21251 // Scale the condition by the difference.
21253 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21254 DAG.getConstant(Diff, Cond.getValueType()));
21256 // Add the base if non-zero.
21257 if (FalseC->getAPIntValue() != 0)
21258 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21259 SDValue(FalseC, 0));
21260 if (N->getNumValues() == 2) // Dead flag value?
21261 return DCI.CombineTo(N, Cond, SDValue());
21268 // Handle these cases:
21269 // (select (x != c), e, c) -> select (x != c), e, x),
21270 // (select (x == c), c, e) -> select (x == c), x, e)
21271 // where the c is an integer constant, and the "select" is the combination
21272 // of CMOV and CMP.
21274 // The rationale for this change is that the conditional-move from a constant
21275 // needs two instructions, however, conditional-move from a register needs
21276 // only one instruction.
21278 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21279 // some instruction-combining opportunities. This opt needs to be
21280 // postponed as late as possible.
21282 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21283 // the DCI.xxxx conditions are provided to postpone the optimization as
21284 // late as possible.
21286 ConstantSDNode *CmpAgainst = nullptr;
21287 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21288 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21289 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21291 if (CC == X86::COND_NE &&
21292 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21293 CC = X86::GetOppositeBranchCondition(CC);
21294 std::swap(TrueOp, FalseOp);
21297 if (CC == X86::COND_E &&
21298 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21299 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21300 DAG.getConstant(CC, MVT::i8), Cond };
21301 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21309 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21310 const X86Subtarget *Subtarget) {
21311 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21313 default: return SDValue();
21314 // SSE/AVX/AVX2 blend intrinsics.
21315 case Intrinsic::x86_avx2_pblendvb:
21316 case Intrinsic::x86_avx2_pblendw:
21317 case Intrinsic::x86_avx2_pblendd_128:
21318 case Intrinsic::x86_avx2_pblendd_256:
21319 // Don't try to simplify this intrinsic if we don't have AVX2.
21320 if (!Subtarget->hasAVX2())
21323 case Intrinsic::x86_avx_blend_pd_256:
21324 case Intrinsic::x86_avx_blend_ps_256:
21325 case Intrinsic::x86_avx_blendv_pd_256:
21326 case Intrinsic::x86_avx_blendv_ps_256:
21327 // Don't try to simplify this intrinsic if we don't have AVX.
21328 if (!Subtarget->hasAVX())
21331 case Intrinsic::x86_sse41_pblendw:
21332 case Intrinsic::x86_sse41_blendpd:
21333 case Intrinsic::x86_sse41_blendps:
21334 case Intrinsic::x86_sse41_blendvps:
21335 case Intrinsic::x86_sse41_blendvpd:
21336 case Intrinsic::x86_sse41_pblendvb: {
21337 SDValue Op0 = N->getOperand(1);
21338 SDValue Op1 = N->getOperand(2);
21339 SDValue Mask = N->getOperand(3);
21341 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21342 if (!Subtarget->hasSSE41())
21345 // fold (blend A, A, Mask) -> A
21348 // fold (blend A, B, allZeros) -> A
21349 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21351 // fold (blend A, B, allOnes) -> B
21352 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21355 // Simplify the case where the mask is a constant i32 value.
21356 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21357 if (C->isNullValue())
21359 if (C->isAllOnesValue())
21366 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21367 case Intrinsic::x86_sse2_psrai_w:
21368 case Intrinsic::x86_sse2_psrai_d:
21369 case Intrinsic::x86_avx2_psrai_w:
21370 case Intrinsic::x86_avx2_psrai_d:
21371 case Intrinsic::x86_sse2_psra_w:
21372 case Intrinsic::x86_sse2_psra_d:
21373 case Intrinsic::x86_avx2_psra_w:
21374 case Intrinsic::x86_avx2_psra_d: {
21375 SDValue Op0 = N->getOperand(1);
21376 SDValue Op1 = N->getOperand(2);
21377 EVT VT = Op0.getValueType();
21378 assert(VT.isVector() && "Expected a vector type!");
21380 if (isa<BuildVectorSDNode>(Op1))
21381 Op1 = Op1.getOperand(0);
21383 if (!isa<ConstantSDNode>(Op1))
21386 EVT SVT = VT.getVectorElementType();
21387 unsigned SVTBits = SVT.getSizeInBits();
21389 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21390 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21391 uint64_t ShAmt = C.getZExtValue();
21393 // Don't try to convert this shift into a ISD::SRA if the shift
21394 // count is bigger than or equal to the element size.
21395 if (ShAmt >= SVTBits)
21398 // Trivial case: if the shift count is zero, then fold this
21399 // into the first operand.
21403 // Replace this packed shift intrinsic with a target independent
21405 SDValue Splat = DAG.getConstant(C, VT);
21406 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21411 /// PerformMulCombine - Optimize a single multiply with constant into two
21412 /// in order to implement it with two cheaper instructions, e.g.
21413 /// LEA + SHL, LEA + LEA.
21414 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21415 TargetLowering::DAGCombinerInfo &DCI) {
21416 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21419 EVT VT = N->getValueType(0);
21420 if (VT != MVT::i64)
21423 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21426 uint64_t MulAmt = C->getZExtValue();
21427 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21430 uint64_t MulAmt1 = 0;
21431 uint64_t MulAmt2 = 0;
21432 if ((MulAmt % 9) == 0) {
21434 MulAmt2 = MulAmt / 9;
21435 } else if ((MulAmt % 5) == 0) {
21437 MulAmt2 = MulAmt / 5;
21438 } else if ((MulAmt % 3) == 0) {
21440 MulAmt2 = MulAmt / 3;
21443 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21446 if (isPowerOf2_64(MulAmt2) &&
21447 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21448 // If second multiplifer is pow2, issue it first. We want the multiply by
21449 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21451 std::swap(MulAmt1, MulAmt2);
21454 if (isPowerOf2_64(MulAmt1))
21455 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21456 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21458 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21459 DAG.getConstant(MulAmt1, VT));
21461 if (isPowerOf2_64(MulAmt2))
21462 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21463 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21465 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21466 DAG.getConstant(MulAmt2, VT));
21468 // Do not add new nodes to DAG combiner worklist.
21469 DCI.CombineTo(N, NewMul, false);
21474 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21475 SDValue N0 = N->getOperand(0);
21476 SDValue N1 = N->getOperand(1);
21477 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21478 EVT VT = N0.getValueType();
21480 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21481 // since the result of setcc_c is all zero's or all ones.
21482 if (VT.isInteger() && !VT.isVector() &&
21483 N1C && N0.getOpcode() == ISD::AND &&
21484 N0.getOperand(1).getOpcode() == ISD::Constant) {
21485 SDValue N00 = N0.getOperand(0);
21486 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21487 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21488 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21489 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21490 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21491 APInt ShAmt = N1C->getAPIntValue();
21492 Mask = Mask.shl(ShAmt);
21494 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21495 N00, DAG.getConstant(Mask, VT));
21499 // Hardware support for vector shifts is sparse which makes us scalarize the
21500 // vector operations in many cases. Also, on sandybridge ADD is faster than
21502 // (shl V, 1) -> add V,V
21503 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21504 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21505 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21506 // We shift all of the values by one. In many cases we do not have
21507 // hardware support for this operation. This is better expressed as an ADD
21509 if (N1SplatC->getZExtValue() == 1)
21510 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21516 /// \brief Returns a vector of 0s if the node in input is a vector logical
21517 /// shift by a constant amount which is known to be bigger than or equal
21518 /// to the vector element size in bits.
21519 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21520 const X86Subtarget *Subtarget) {
21521 EVT VT = N->getValueType(0);
21523 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21524 (!Subtarget->hasInt256() ||
21525 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21528 SDValue Amt = N->getOperand(1);
21530 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21531 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21532 APInt ShiftAmt = AmtSplat->getAPIntValue();
21533 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21535 // SSE2/AVX2 logical shifts always return a vector of 0s
21536 // if the shift amount is bigger than or equal to
21537 // the element size. The constant shift amount will be
21538 // encoded as a 8-bit immediate.
21539 if (ShiftAmt.trunc(8).uge(MaxAmount))
21540 return getZeroVector(VT, Subtarget, DAG, DL);
21546 /// PerformShiftCombine - Combine shifts.
21547 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21548 TargetLowering::DAGCombinerInfo &DCI,
21549 const X86Subtarget *Subtarget) {
21550 if (N->getOpcode() == ISD::SHL) {
21551 SDValue V = PerformSHLCombine(N, DAG);
21552 if (V.getNode()) return V;
21555 if (N->getOpcode() != ISD::SRA) {
21556 // Try to fold this logical shift into a zero vector.
21557 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21558 if (V.getNode()) return V;
21564 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21565 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21566 // and friends. Likewise for OR -> CMPNEQSS.
21567 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21568 TargetLowering::DAGCombinerInfo &DCI,
21569 const X86Subtarget *Subtarget) {
21572 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21573 // we're requiring SSE2 for both.
21574 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21575 SDValue N0 = N->getOperand(0);
21576 SDValue N1 = N->getOperand(1);
21577 SDValue CMP0 = N0->getOperand(1);
21578 SDValue CMP1 = N1->getOperand(1);
21581 // The SETCCs should both refer to the same CMP.
21582 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21585 SDValue CMP00 = CMP0->getOperand(0);
21586 SDValue CMP01 = CMP0->getOperand(1);
21587 EVT VT = CMP00.getValueType();
21589 if (VT == MVT::f32 || VT == MVT::f64) {
21590 bool ExpectingFlags = false;
21591 // Check for any users that want flags:
21592 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21593 !ExpectingFlags && UI != UE; ++UI)
21594 switch (UI->getOpcode()) {
21599 ExpectingFlags = true;
21601 case ISD::CopyToReg:
21602 case ISD::SIGN_EXTEND:
21603 case ISD::ZERO_EXTEND:
21604 case ISD::ANY_EXTEND:
21608 if (!ExpectingFlags) {
21609 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21610 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21612 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21613 X86::CondCode tmp = cc0;
21618 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21619 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21620 // FIXME: need symbolic constants for these magic numbers.
21621 // See X86ATTInstPrinter.cpp:printSSECC().
21622 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21623 if (Subtarget->hasAVX512()) {
21624 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21625 CMP01, DAG.getConstant(x86cc, MVT::i8));
21626 if (N->getValueType(0) != MVT::i1)
21627 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21631 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21632 CMP00.getValueType(), CMP00, CMP01,
21633 DAG.getConstant(x86cc, MVT::i8));
21635 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21636 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21638 if (is64BitFP && !Subtarget->is64Bit()) {
21639 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21640 // 64-bit integer, since that's not a legal type. Since
21641 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21642 // bits, but can do this little dance to extract the lowest 32 bits
21643 // and work with those going forward.
21644 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21646 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21648 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21649 Vector32, DAG.getIntPtrConstant(0));
21653 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21654 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21655 DAG.getConstant(1, IntVT));
21656 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21657 return OneBitOfTruth;
21665 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21666 /// so it can be folded inside ANDNP.
21667 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21668 EVT VT = N->getValueType(0);
21670 // Match direct AllOnes for 128 and 256-bit vectors
21671 if (ISD::isBuildVectorAllOnes(N))
21674 // Look through a bit convert.
21675 if (N->getOpcode() == ISD::BITCAST)
21676 N = N->getOperand(0).getNode();
21678 // Sometimes the operand may come from a insert_subvector building a 256-bit
21680 if (VT.is256BitVector() &&
21681 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21682 SDValue V1 = N->getOperand(0);
21683 SDValue V2 = N->getOperand(1);
21685 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21686 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21687 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21688 ISD::isBuildVectorAllOnes(V2.getNode()))
21695 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21696 // register. In most cases we actually compare or select YMM-sized registers
21697 // and mixing the two types creates horrible code. This method optimizes
21698 // some of the transition sequences.
21699 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21700 TargetLowering::DAGCombinerInfo &DCI,
21701 const X86Subtarget *Subtarget) {
21702 EVT VT = N->getValueType(0);
21703 if (!VT.is256BitVector())
21706 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21707 N->getOpcode() == ISD::ZERO_EXTEND ||
21708 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21710 SDValue Narrow = N->getOperand(0);
21711 EVT NarrowVT = Narrow->getValueType(0);
21712 if (!NarrowVT.is128BitVector())
21715 if (Narrow->getOpcode() != ISD::XOR &&
21716 Narrow->getOpcode() != ISD::AND &&
21717 Narrow->getOpcode() != ISD::OR)
21720 SDValue N0 = Narrow->getOperand(0);
21721 SDValue N1 = Narrow->getOperand(1);
21724 // The Left side has to be a trunc.
21725 if (N0.getOpcode() != ISD::TRUNCATE)
21728 // The type of the truncated inputs.
21729 EVT WideVT = N0->getOperand(0)->getValueType(0);
21733 // The right side has to be a 'trunc' or a constant vector.
21734 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21735 ConstantSDNode *RHSConstSplat = nullptr;
21736 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21737 RHSConstSplat = RHSBV->getConstantSplatNode();
21738 if (!RHSTrunc && !RHSConstSplat)
21741 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21743 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21746 // Set N0 and N1 to hold the inputs to the new wide operation.
21747 N0 = N0->getOperand(0);
21748 if (RHSConstSplat) {
21749 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21750 SDValue(RHSConstSplat, 0));
21751 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21752 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21753 } else if (RHSTrunc) {
21754 N1 = N1->getOperand(0);
21757 // Generate the wide operation.
21758 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21759 unsigned Opcode = N->getOpcode();
21761 case ISD::ANY_EXTEND:
21763 case ISD::ZERO_EXTEND: {
21764 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21765 APInt Mask = APInt::getAllOnesValue(InBits);
21766 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21767 return DAG.getNode(ISD::AND, DL, VT,
21768 Op, DAG.getConstant(Mask, VT));
21770 case ISD::SIGN_EXTEND:
21771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21772 Op, DAG.getValueType(NarrowVT));
21774 llvm_unreachable("Unexpected opcode");
21778 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21779 TargetLowering::DAGCombinerInfo &DCI,
21780 const X86Subtarget *Subtarget) {
21781 EVT VT = N->getValueType(0);
21782 if (DCI.isBeforeLegalizeOps())
21785 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21789 // Create BEXTR instructions
21790 // BEXTR is ((X >> imm) & (2**size-1))
21791 if (VT == MVT::i32 || VT == MVT::i64) {
21792 SDValue N0 = N->getOperand(0);
21793 SDValue N1 = N->getOperand(1);
21796 // Check for BEXTR.
21797 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21798 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21799 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21800 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21801 if (MaskNode && ShiftNode) {
21802 uint64_t Mask = MaskNode->getZExtValue();
21803 uint64_t Shift = ShiftNode->getZExtValue();
21804 if (isMask_64(Mask)) {
21805 uint64_t MaskSize = CountPopulation_64(Mask);
21806 if (Shift + MaskSize <= VT.getSizeInBits())
21807 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21808 DAG.getConstant(Shift | (MaskSize << 8), VT));
21816 // Want to form ANDNP nodes:
21817 // 1) In the hopes of then easily combining them with OR and AND nodes
21818 // to form PBLEND/PSIGN.
21819 // 2) To match ANDN packed intrinsics
21820 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21823 SDValue N0 = N->getOperand(0);
21824 SDValue N1 = N->getOperand(1);
21827 // Check LHS for vnot
21828 if (N0.getOpcode() == ISD::XOR &&
21829 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21830 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21831 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21833 // Check RHS for vnot
21834 if (N1.getOpcode() == ISD::XOR &&
21835 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21836 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21837 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21842 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21843 TargetLowering::DAGCombinerInfo &DCI,
21844 const X86Subtarget *Subtarget) {
21845 if (DCI.isBeforeLegalizeOps())
21848 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21852 SDValue N0 = N->getOperand(0);
21853 SDValue N1 = N->getOperand(1);
21854 EVT VT = N->getValueType(0);
21856 // look for psign/blend
21857 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21858 if (!Subtarget->hasSSSE3() ||
21859 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21862 // Canonicalize pandn to RHS
21863 if (N0.getOpcode() == X86ISD::ANDNP)
21865 // or (and (m, y), (pandn m, x))
21866 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21867 SDValue Mask = N1.getOperand(0);
21868 SDValue X = N1.getOperand(1);
21870 if (N0.getOperand(0) == Mask)
21871 Y = N0.getOperand(1);
21872 if (N0.getOperand(1) == Mask)
21873 Y = N0.getOperand(0);
21875 // Check to see if the mask appeared in both the AND and ANDNP and
21879 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21880 // Look through mask bitcast.
21881 if (Mask.getOpcode() == ISD::BITCAST)
21882 Mask = Mask.getOperand(0);
21883 if (X.getOpcode() == ISD::BITCAST)
21884 X = X.getOperand(0);
21885 if (Y.getOpcode() == ISD::BITCAST)
21886 Y = Y.getOperand(0);
21888 EVT MaskVT = Mask.getValueType();
21890 // Validate that the Mask operand is a vector sra node.
21891 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21892 // there is no psrai.b
21893 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21894 unsigned SraAmt = ~0;
21895 if (Mask.getOpcode() == ISD::SRA) {
21896 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21897 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21898 SraAmt = AmtConst->getZExtValue();
21899 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21900 SDValue SraC = Mask.getOperand(1);
21901 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21903 if ((SraAmt + 1) != EltBits)
21908 // Now we know we at least have a plendvb with the mask val. See if
21909 // we can form a psignb/w/d.
21910 // psign = x.type == y.type == mask.type && y = sub(0, x);
21911 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21912 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21913 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21914 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21915 "Unsupported VT for PSIGN");
21916 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21917 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21919 // PBLENDVB only available on SSE 4.1
21920 if (!Subtarget->hasSSE41())
21923 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21925 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21926 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21927 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21928 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21929 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21933 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21936 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21937 MachineFunction &MF = DAG.getMachineFunction();
21938 bool OptForSize = MF.getFunction()->getAttributes().
21939 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21941 // SHLD/SHRD instructions have lower register pressure, but on some
21942 // platforms they have higher latency than the equivalent
21943 // series of shifts/or that would otherwise be generated.
21944 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21945 // have higher latencies and we are not optimizing for size.
21946 if (!OptForSize && Subtarget->isSHLDSlow())
21949 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21951 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21953 if (!N0.hasOneUse() || !N1.hasOneUse())
21956 SDValue ShAmt0 = N0.getOperand(1);
21957 if (ShAmt0.getValueType() != MVT::i8)
21959 SDValue ShAmt1 = N1.getOperand(1);
21960 if (ShAmt1.getValueType() != MVT::i8)
21962 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21963 ShAmt0 = ShAmt0.getOperand(0);
21964 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21965 ShAmt1 = ShAmt1.getOperand(0);
21968 unsigned Opc = X86ISD::SHLD;
21969 SDValue Op0 = N0.getOperand(0);
21970 SDValue Op1 = N1.getOperand(0);
21971 if (ShAmt0.getOpcode() == ISD::SUB) {
21972 Opc = X86ISD::SHRD;
21973 std::swap(Op0, Op1);
21974 std::swap(ShAmt0, ShAmt1);
21977 unsigned Bits = VT.getSizeInBits();
21978 if (ShAmt1.getOpcode() == ISD::SUB) {
21979 SDValue Sum = ShAmt1.getOperand(0);
21980 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21981 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21982 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21983 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21984 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21985 return DAG.getNode(Opc, DL, VT,
21987 DAG.getNode(ISD::TRUNCATE, DL,
21990 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21991 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21993 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21994 return DAG.getNode(Opc, DL, VT,
21995 N0.getOperand(0), N1.getOperand(0),
21996 DAG.getNode(ISD::TRUNCATE, DL,
22003 // Generate NEG and CMOV for integer abs.
22004 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22005 EVT VT = N->getValueType(0);
22007 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22008 // 8-bit integer abs to NEG and CMOV.
22009 if (VT.isInteger() && VT.getSizeInBits() == 8)
22012 SDValue N0 = N->getOperand(0);
22013 SDValue N1 = N->getOperand(1);
22016 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22017 // and change it to SUB and CMOV.
22018 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22019 N0.getOpcode() == ISD::ADD &&
22020 N0.getOperand(1) == N1 &&
22021 N1.getOpcode() == ISD::SRA &&
22022 N1.getOperand(0) == N0.getOperand(0))
22023 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22024 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22025 // Generate SUB & CMOV.
22026 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22027 DAG.getConstant(0, VT), N0.getOperand(0));
22029 SDValue Ops[] = { N0.getOperand(0), Neg,
22030 DAG.getConstant(X86::COND_GE, MVT::i8),
22031 SDValue(Neg.getNode(), 1) };
22032 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22037 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22038 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22039 TargetLowering::DAGCombinerInfo &DCI,
22040 const X86Subtarget *Subtarget) {
22041 if (DCI.isBeforeLegalizeOps())
22044 if (Subtarget->hasCMov()) {
22045 SDValue RV = performIntegerAbsCombine(N, DAG);
22053 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22054 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22055 TargetLowering::DAGCombinerInfo &DCI,
22056 const X86Subtarget *Subtarget) {
22057 LoadSDNode *Ld = cast<LoadSDNode>(N);
22058 EVT RegVT = Ld->getValueType(0);
22059 EVT MemVT = Ld->getMemoryVT();
22061 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22063 // On Sandybridge unaligned 256bit loads are inefficient.
22064 ISD::LoadExtType Ext = Ld->getExtensionType();
22065 unsigned Alignment = Ld->getAlignment();
22066 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22067 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22068 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22069 unsigned NumElems = RegVT.getVectorNumElements();
22073 SDValue Ptr = Ld->getBasePtr();
22074 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22076 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22078 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22079 Ld->getPointerInfo(), Ld->isVolatile(),
22080 Ld->isNonTemporal(), Ld->isInvariant(),
22082 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22083 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22084 Ld->getPointerInfo(), Ld->isVolatile(),
22085 Ld->isNonTemporal(), Ld->isInvariant(),
22086 std::min(16U, Alignment));
22087 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22089 Load2.getValue(1));
22091 SDValue NewVec = DAG.getUNDEF(RegVT);
22092 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22093 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22094 return DCI.CombineTo(N, NewVec, TF, true);
22100 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22101 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22102 const X86Subtarget *Subtarget) {
22103 StoreSDNode *St = cast<StoreSDNode>(N);
22104 EVT VT = St->getValue().getValueType();
22105 EVT StVT = St->getMemoryVT();
22107 SDValue StoredVal = St->getOperand(1);
22108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22110 // If we are saving a concatenation of two XMM registers, perform two stores.
22111 // On Sandy Bridge, 256-bit memory operations are executed by two
22112 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22113 // memory operation.
22114 unsigned Alignment = St->getAlignment();
22115 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22116 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22117 StVT == VT && !IsAligned) {
22118 unsigned NumElems = VT.getVectorNumElements();
22122 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22123 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22125 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22126 SDValue Ptr0 = St->getBasePtr();
22127 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22129 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22130 St->getPointerInfo(), St->isVolatile(),
22131 St->isNonTemporal(), Alignment);
22132 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22133 St->getPointerInfo(), St->isVolatile(),
22134 St->isNonTemporal(),
22135 std::min(16U, Alignment));
22136 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22139 // Optimize trunc store (of multiple scalars) to shuffle and store.
22140 // First, pack all of the elements in one place. Next, store to memory
22141 // in fewer chunks.
22142 if (St->isTruncatingStore() && VT.isVector()) {
22143 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22144 unsigned NumElems = VT.getVectorNumElements();
22145 assert(StVT != VT && "Cannot truncate to the same type");
22146 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22147 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22149 // From, To sizes and ElemCount must be pow of two
22150 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22151 // We are going to use the original vector elt for storing.
22152 // Accumulated smaller vector elements must be a multiple of the store size.
22153 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22155 unsigned SizeRatio = FromSz / ToSz;
22157 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22159 // Create a type on which we perform the shuffle
22160 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22161 StVT.getScalarType(), NumElems*SizeRatio);
22163 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22165 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22166 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22167 for (unsigned i = 0; i != NumElems; ++i)
22168 ShuffleVec[i] = i * SizeRatio;
22170 // Can't shuffle using an illegal type.
22171 if (!TLI.isTypeLegal(WideVecVT))
22174 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22175 DAG.getUNDEF(WideVecVT),
22177 // At this point all of the data is stored at the bottom of the
22178 // register. We now need to save it to mem.
22180 // Find the largest store unit
22181 MVT StoreType = MVT::i8;
22182 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22183 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22184 MVT Tp = (MVT::SimpleValueType)tp;
22185 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22189 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22190 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22191 (64 <= NumElems * ToSz))
22192 StoreType = MVT::f64;
22194 // Bitcast the original vector into a vector of store-size units
22195 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22196 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22197 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22198 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22199 SmallVector<SDValue, 8> Chains;
22200 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22201 TLI.getPointerTy());
22202 SDValue Ptr = St->getBasePtr();
22204 // Perform one or more big stores into memory.
22205 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22206 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22207 StoreType, ShuffWide,
22208 DAG.getIntPtrConstant(i));
22209 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22210 St->getPointerInfo(), St->isVolatile(),
22211 St->isNonTemporal(), St->getAlignment());
22212 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22213 Chains.push_back(Ch);
22216 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22219 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22220 // the FP state in cases where an emms may be missing.
22221 // A preferable solution to the general problem is to figure out the right
22222 // places to insert EMMS. This qualifies as a quick hack.
22224 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22225 if (VT.getSizeInBits() != 64)
22228 const Function *F = DAG.getMachineFunction().getFunction();
22229 bool NoImplicitFloatOps = F->getAttributes().
22230 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22231 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22232 && Subtarget->hasSSE2();
22233 if ((VT.isVector() ||
22234 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22235 isa<LoadSDNode>(St->getValue()) &&
22236 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22237 St->getChain().hasOneUse() && !St->isVolatile()) {
22238 SDNode* LdVal = St->getValue().getNode();
22239 LoadSDNode *Ld = nullptr;
22240 int TokenFactorIndex = -1;
22241 SmallVector<SDValue, 8> Ops;
22242 SDNode* ChainVal = St->getChain().getNode();
22243 // Must be a store of a load. We currently handle two cases: the load
22244 // is a direct child, and it's under an intervening TokenFactor. It is
22245 // possible to dig deeper under nested TokenFactors.
22246 if (ChainVal == LdVal)
22247 Ld = cast<LoadSDNode>(St->getChain());
22248 else if (St->getValue().hasOneUse() &&
22249 ChainVal->getOpcode() == ISD::TokenFactor) {
22250 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22251 if (ChainVal->getOperand(i).getNode() == LdVal) {
22252 TokenFactorIndex = i;
22253 Ld = cast<LoadSDNode>(St->getValue());
22255 Ops.push_back(ChainVal->getOperand(i));
22259 if (!Ld || !ISD::isNormalLoad(Ld))
22262 // If this is not the MMX case, i.e. we are just turning i64 load/store
22263 // into f64 load/store, avoid the transformation if there are multiple
22264 // uses of the loaded value.
22265 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22270 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22271 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22273 if (Subtarget->is64Bit() || F64IsLegal) {
22274 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22275 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22276 Ld->getPointerInfo(), Ld->isVolatile(),
22277 Ld->isNonTemporal(), Ld->isInvariant(),
22278 Ld->getAlignment());
22279 SDValue NewChain = NewLd.getValue(1);
22280 if (TokenFactorIndex != -1) {
22281 Ops.push_back(NewChain);
22282 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22284 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22285 St->getPointerInfo(),
22286 St->isVolatile(), St->isNonTemporal(),
22287 St->getAlignment());
22290 // Otherwise, lower to two pairs of 32-bit loads / stores.
22291 SDValue LoAddr = Ld->getBasePtr();
22292 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22293 DAG.getConstant(4, MVT::i32));
22295 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22296 Ld->getPointerInfo(),
22297 Ld->isVolatile(), Ld->isNonTemporal(),
22298 Ld->isInvariant(), Ld->getAlignment());
22299 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22300 Ld->getPointerInfo().getWithOffset(4),
22301 Ld->isVolatile(), Ld->isNonTemporal(),
22303 MinAlign(Ld->getAlignment(), 4));
22305 SDValue NewChain = LoLd.getValue(1);
22306 if (TokenFactorIndex != -1) {
22307 Ops.push_back(LoLd);
22308 Ops.push_back(HiLd);
22309 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22312 LoAddr = St->getBasePtr();
22313 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22314 DAG.getConstant(4, MVT::i32));
22316 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22317 St->getPointerInfo(),
22318 St->isVolatile(), St->isNonTemporal(),
22319 St->getAlignment());
22320 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22321 St->getPointerInfo().getWithOffset(4),
22323 St->isNonTemporal(),
22324 MinAlign(St->getAlignment(), 4));
22325 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22330 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22331 /// and return the operands for the horizontal operation in LHS and RHS. A
22332 /// horizontal operation performs the binary operation on successive elements
22333 /// of its first operand, then on successive elements of its second operand,
22334 /// returning the resulting values in a vector. For example, if
22335 /// A = < float a0, float a1, float a2, float a3 >
22337 /// B = < float b0, float b1, float b2, float b3 >
22338 /// then the result of doing a horizontal operation on A and B is
22339 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22340 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22341 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22342 /// set to A, RHS to B, and the routine returns 'true'.
22343 /// Note that the binary operation should have the property that if one of the
22344 /// operands is UNDEF then the result is UNDEF.
22345 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22346 // Look for the following pattern: if
22347 // A = < float a0, float a1, float a2, float a3 >
22348 // B = < float b0, float b1, float b2, float b3 >
22350 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22351 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22352 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22353 // which is A horizontal-op B.
22355 // At least one of the operands should be a vector shuffle.
22356 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22357 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22360 MVT VT = LHS.getSimpleValueType();
22362 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22363 "Unsupported vector type for horizontal add/sub");
22365 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22366 // operate independently on 128-bit lanes.
22367 unsigned NumElts = VT.getVectorNumElements();
22368 unsigned NumLanes = VT.getSizeInBits()/128;
22369 unsigned NumLaneElts = NumElts / NumLanes;
22370 assert((NumLaneElts % 2 == 0) &&
22371 "Vector type should have an even number of elements in each lane");
22372 unsigned HalfLaneElts = NumLaneElts/2;
22374 // View LHS in the form
22375 // LHS = VECTOR_SHUFFLE A, B, LMask
22376 // If LHS is not a shuffle then pretend it is the shuffle
22377 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22378 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22381 SmallVector<int, 16> LMask(NumElts);
22382 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22383 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22384 A = LHS.getOperand(0);
22385 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22386 B = LHS.getOperand(1);
22387 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22388 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22390 if (LHS.getOpcode() != ISD::UNDEF)
22392 for (unsigned i = 0; i != NumElts; ++i)
22396 // Likewise, view RHS in the form
22397 // RHS = VECTOR_SHUFFLE C, D, RMask
22399 SmallVector<int, 16> RMask(NumElts);
22400 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22401 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22402 C = RHS.getOperand(0);
22403 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22404 D = RHS.getOperand(1);
22405 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22406 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22408 if (RHS.getOpcode() != ISD::UNDEF)
22410 for (unsigned i = 0; i != NumElts; ++i)
22414 // Check that the shuffles are both shuffling the same vectors.
22415 if (!(A == C && B == D) && !(A == D && B == C))
22418 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22419 if (!A.getNode() && !B.getNode())
22422 // If A and B occur in reverse order in RHS, then "swap" them (which means
22423 // rewriting the mask).
22425 CommuteVectorShuffleMask(RMask, NumElts);
22427 // At this point LHS and RHS are equivalent to
22428 // LHS = VECTOR_SHUFFLE A, B, LMask
22429 // RHS = VECTOR_SHUFFLE A, B, RMask
22430 // Check that the masks correspond to performing a horizontal operation.
22431 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22432 for (unsigned i = 0; i != NumLaneElts; ++i) {
22433 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22435 // Ignore any UNDEF components.
22436 if (LIdx < 0 || RIdx < 0 ||
22437 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22438 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22441 // Check that successive elements are being operated on. If not, this is
22442 // not a horizontal operation.
22443 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22444 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22445 if (!(LIdx == Index && RIdx == Index + 1) &&
22446 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22451 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22452 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22456 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22457 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22458 const X86Subtarget *Subtarget) {
22459 EVT VT = N->getValueType(0);
22460 SDValue LHS = N->getOperand(0);
22461 SDValue RHS = N->getOperand(1);
22463 // Try to synthesize horizontal adds from adds of shuffles.
22464 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22465 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22466 isHorizontalBinOp(LHS, RHS, true))
22467 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22471 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22472 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22473 const X86Subtarget *Subtarget) {
22474 EVT VT = N->getValueType(0);
22475 SDValue LHS = N->getOperand(0);
22476 SDValue RHS = N->getOperand(1);
22478 // Try to synthesize horizontal subs from subs of shuffles.
22479 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22480 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22481 isHorizontalBinOp(LHS, RHS, false))
22482 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22486 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22487 /// X86ISD::FXOR nodes.
22488 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22489 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22490 // F[X]OR(0.0, x) -> x
22491 // F[X]OR(x, 0.0) -> x
22492 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22493 if (C->getValueAPF().isPosZero())
22494 return N->getOperand(1);
22495 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22496 if (C->getValueAPF().isPosZero())
22497 return N->getOperand(0);
22501 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22502 /// X86ISD::FMAX nodes.
22503 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22504 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22506 // Only perform optimizations if UnsafeMath is used.
22507 if (!DAG.getTarget().Options.UnsafeFPMath)
22510 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22511 // into FMINC and FMAXC, which are Commutative operations.
22512 unsigned NewOp = 0;
22513 switch (N->getOpcode()) {
22514 default: llvm_unreachable("unknown opcode");
22515 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22516 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22519 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22520 N->getOperand(0), N->getOperand(1));
22523 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22524 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22525 // FAND(0.0, x) -> 0.0
22526 // FAND(x, 0.0) -> 0.0
22527 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22528 if (C->getValueAPF().isPosZero())
22529 return N->getOperand(0);
22530 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22531 if (C->getValueAPF().isPosZero())
22532 return N->getOperand(1);
22536 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22537 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22538 // FANDN(x, 0.0) -> 0.0
22539 // FANDN(0.0, x) -> x
22540 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22541 if (C->getValueAPF().isPosZero())
22542 return N->getOperand(1);
22543 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22544 if (C->getValueAPF().isPosZero())
22545 return N->getOperand(1);
22549 static SDValue PerformBTCombine(SDNode *N,
22551 TargetLowering::DAGCombinerInfo &DCI) {
22552 // BT ignores high bits in the bit index operand.
22553 SDValue Op1 = N->getOperand(1);
22554 if (Op1.hasOneUse()) {
22555 unsigned BitWidth = Op1.getValueSizeInBits();
22556 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22557 APInt KnownZero, KnownOne;
22558 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22559 !DCI.isBeforeLegalizeOps());
22560 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22561 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22562 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22563 DCI.CommitTargetLoweringOpt(TLO);
22568 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22569 SDValue Op = N->getOperand(0);
22570 if (Op.getOpcode() == ISD::BITCAST)
22571 Op = Op.getOperand(0);
22572 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22573 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22574 VT.getVectorElementType().getSizeInBits() ==
22575 OpVT.getVectorElementType().getSizeInBits()) {
22576 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22581 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22582 const X86Subtarget *Subtarget) {
22583 EVT VT = N->getValueType(0);
22584 if (!VT.isVector())
22587 SDValue N0 = N->getOperand(0);
22588 SDValue N1 = N->getOperand(1);
22589 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22592 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22593 // both SSE and AVX2 since there is no sign-extended shift right
22594 // operation on a vector with 64-bit elements.
22595 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22596 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22597 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22598 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22599 SDValue N00 = N0.getOperand(0);
22601 // EXTLOAD has a better solution on AVX2,
22602 // it may be replaced with X86ISD::VSEXT node.
22603 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22604 if (!ISD::isNormalLoad(N00.getNode()))
22607 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22608 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22610 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22616 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22617 TargetLowering::DAGCombinerInfo &DCI,
22618 const X86Subtarget *Subtarget) {
22619 if (!DCI.isBeforeLegalizeOps())
22622 if (!Subtarget->hasFp256())
22625 EVT VT = N->getValueType(0);
22626 if (VT.isVector() && VT.getSizeInBits() == 256) {
22627 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22635 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22636 const X86Subtarget* Subtarget) {
22638 EVT VT = N->getValueType(0);
22640 // Let legalize expand this if it isn't a legal type yet.
22641 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22644 EVT ScalarVT = VT.getScalarType();
22645 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22646 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22649 SDValue A = N->getOperand(0);
22650 SDValue B = N->getOperand(1);
22651 SDValue C = N->getOperand(2);
22653 bool NegA = (A.getOpcode() == ISD::FNEG);
22654 bool NegB = (B.getOpcode() == ISD::FNEG);
22655 bool NegC = (C.getOpcode() == ISD::FNEG);
22657 // Negative multiplication when NegA xor NegB
22658 bool NegMul = (NegA != NegB);
22660 A = A.getOperand(0);
22662 B = B.getOperand(0);
22664 C = C.getOperand(0);
22668 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22670 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22672 return DAG.getNode(Opcode, dl, VT, A, B, C);
22675 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22676 TargetLowering::DAGCombinerInfo &DCI,
22677 const X86Subtarget *Subtarget) {
22678 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22679 // (and (i32 x86isd::setcc_carry), 1)
22680 // This eliminates the zext. This transformation is necessary because
22681 // ISD::SETCC is always legalized to i8.
22683 SDValue N0 = N->getOperand(0);
22684 EVT VT = N->getValueType(0);
22686 if (N0.getOpcode() == ISD::AND &&
22688 N0.getOperand(0).hasOneUse()) {
22689 SDValue N00 = N0.getOperand(0);
22690 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22691 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22692 if (!C || C->getZExtValue() != 1)
22694 return DAG.getNode(ISD::AND, dl, VT,
22695 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22696 N00.getOperand(0), N00.getOperand(1)),
22697 DAG.getConstant(1, VT));
22701 if (N0.getOpcode() == ISD::TRUNCATE &&
22703 N0.getOperand(0).hasOneUse()) {
22704 SDValue N00 = N0.getOperand(0);
22705 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22706 return DAG.getNode(ISD::AND, dl, VT,
22707 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22708 N00.getOperand(0), N00.getOperand(1)),
22709 DAG.getConstant(1, VT));
22712 if (VT.is256BitVector()) {
22713 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22721 // Optimize x == -y --> x+y == 0
22722 // x != -y --> x+y != 0
22723 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22724 const X86Subtarget* Subtarget) {
22725 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22726 SDValue LHS = N->getOperand(0);
22727 SDValue RHS = N->getOperand(1);
22728 EVT VT = N->getValueType(0);
22731 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22732 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22733 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22734 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22735 LHS.getValueType(), RHS, LHS.getOperand(1));
22736 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22737 addV, DAG.getConstant(0, addV.getValueType()), CC);
22739 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22741 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22742 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22743 RHS.getValueType(), LHS, RHS.getOperand(1));
22744 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22745 addV, DAG.getConstant(0, addV.getValueType()), CC);
22748 if (VT.getScalarType() == MVT::i1) {
22749 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22750 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22751 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22752 if (!IsSEXT0 && !IsVZero0)
22754 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22755 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22756 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22758 if (!IsSEXT1 && !IsVZero1)
22761 if (IsSEXT0 && IsVZero1) {
22762 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22763 if (CC == ISD::SETEQ)
22764 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22765 return LHS.getOperand(0);
22767 if (IsSEXT1 && IsVZero0) {
22768 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22769 if (CC == ISD::SETEQ)
22770 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22771 return RHS.getOperand(0);
22778 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22779 const X86Subtarget *Subtarget) {
22781 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22782 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22783 "X86insertps is only defined for v4x32");
22785 SDValue Ld = N->getOperand(1);
22786 if (MayFoldLoad(Ld)) {
22787 // Extract the countS bits from the immediate so we can get the proper
22788 // address when narrowing the vector load to a specific element.
22789 // When the second source op is a memory address, interps doesn't use
22790 // countS and just gets an f32 from that address.
22791 unsigned DestIndex =
22792 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22793 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22797 // Create this as a scalar to vector to match the instruction pattern.
22798 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22799 // countS bits are ignored when loading from memory on insertps, which
22800 // means we don't need to explicitly set them to 0.
22801 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22802 LoadScalarToVector, N->getOperand(2));
22805 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22806 // as "sbb reg,reg", since it can be extended without zext and produces
22807 // an all-ones bit which is more useful than 0/1 in some cases.
22808 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22811 return DAG.getNode(ISD::AND, DL, VT,
22812 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22813 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22814 DAG.getConstant(1, VT));
22815 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22816 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22817 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22818 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22821 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22822 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22823 TargetLowering::DAGCombinerInfo &DCI,
22824 const X86Subtarget *Subtarget) {
22826 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22827 SDValue EFLAGS = N->getOperand(1);
22829 if (CC == X86::COND_A) {
22830 // Try to convert COND_A into COND_B in an attempt to facilitate
22831 // materializing "setb reg".
22833 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22834 // cannot take an immediate as its first operand.
22836 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22837 EFLAGS.getValueType().isInteger() &&
22838 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22839 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22840 EFLAGS.getNode()->getVTList(),
22841 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22842 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22843 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22847 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22848 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22850 if (CC == X86::COND_B)
22851 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22855 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22856 if (Flags.getNode()) {
22857 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22858 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22864 // Optimize branch condition evaluation.
22866 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22867 TargetLowering::DAGCombinerInfo &DCI,
22868 const X86Subtarget *Subtarget) {
22870 SDValue Chain = N->getOperand(0);
22871 SDValue Dest = N->getOperand(1);
22872 SDValue EFLAGS = N->getOperand(3);
22873 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22877 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22878 if (Flags.getNode()) {
22879 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22880 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22887 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22888 SelectionDAG &DAG) {
22889 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22890 // optimize away operation when it's from a constant.
22892 // The general transformation is:
22893 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22894 // AND(VECTOR_CMP(x,y), constant2)
22895 // constant2 = UNARYOP(constant)
22897 // Early exit if this isn't a vector operation, the operand of the
22898 // unary operation isn't a bitwise AND, or if the sizes of the operations
22899 // aren't the same.
22900 EVT VT = N->getValueType(0);
22901 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22902 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22903 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22906 // Now check that the other operand of the AND is a constant. We could
22907 // make the transformation for non-constant splats as well, but it's unclear
22908 // that would be a benefit as it would not eliminate any operations, just
22909 // perform one more step in scalar code before moving to the vector unit.
22910 if (BuildVectorSDNode *BV =
22911 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22912 // Bail out if the vector isn't a constant.
22913 if (!BV->isConstant())
22916 // Everything checks out. Build up the new and improved node.
22918 EVT IntVT = BV->getValueType(0);
22919 // Create a new constant of the appropriate type for the transformed
22921 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22922 // The AND node needs bitcasts to/from an integer vector type around it.
22923 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22924 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22925 N->getOperand(0)->getOperand(0), MaskConst);
22926 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22933 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22934 const X86TargetLowering *XTLI) {
22935 // First try to optimize away the conversion entirely when it's
22936 // conditionally from a constant. Vectors only.
22937 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22938 if (Res != SDValue())
22941 // Now move on to more general possibilities.
22942 SDValue Op0 = N->getOperand(0);
22943 EVT InVT = Op0->getValueType(0);
22945 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22946 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22948 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22949 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22950 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22953 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22954 // a 32-bit target where SSE doesn't support i64->FP operations.
22955 if (Op0.getOpcode() == ISD::LOAD) {
22956 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22957 EVT VT = Ld->getValueType(0);
22958 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22959 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22960 !XTLI->getSubtarget()->is64Bit() &&
22962 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22963 Ld->getChain(), Op0, DAG);
22964 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22971 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22972 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22973 X86TargetLowering::DAGCombinerInfo &DCI) {
22974 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22975 // the result is either zero or one (depending on the input carry bit).
22976 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22977 if (X86::isZeroNode(N->getOperand(0)) &&
22978 X86::isZeroNode(N->getOperand(1)) &&
22979 // We don't have a good way to replace an EFLAGS use, so only do this when
22981 SDValue(N, 1).use_empty()) {
22983 EVT VT = N->getValueType(0);
22984 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22985 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22986 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22987 DAG.getConstant(X86::COND_B,MVT::i8),
22989 DAG.getConstant(1, VT));
22990 return DCI.CombineTo(N, Res1, CarryOut);
22996 // fold (add Y, (sete X, 0)) -> adc 0, Y
22997 // (add Y, (setne X, 0)) -> sbb -1, Y
22998 // (sub (sete X, 0), Y) -> sbb 0, Y
22999 // (sub (setne X, 0), Y) -> adc -1, Y
23000 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23003 // Look through ZExts.
23004 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23005 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23008 SDValue SetCC = Ext.getOperand(0);
23009 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23012 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23013 if (CC != X86::COND_E && CC != X86::COND_NE)
23016 SDValue Cmp = SetCC.getOperand(1);
23017 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23018 !X86::isZeroNode(Cmp.getOperand(1)) ||
23019 !Cmp.getOperand(0).getValueType().isInteger())
23022 SDValue CmpOp0 = Cmp.getOperand(0);
23023 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23024 DAG.getConstant(1, CmpOp0.getValueType()));
23026 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23027 if (CC == X86::COND_NE)
23028 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23029 DL, OtherVal.getValueType(), OtherVal,
23030 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23031 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23032 DL, OtherVal.getValueType(), OtherVal,
23033 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23036 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23037 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23038 const X86Subtarget *Subtarget) {
23039 EVT VT = N->getValueType(0);
23040 SDValue Op0 = N->getOperand(0);
23041 SDValue Op1 = N->getOperand(1);
23043 // Try to synthesize horizontal adds from adds of shuffles.
23044 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23045 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23046 isHorizontalBinOp(Op0, Op1, true))
23047 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23049 return OptimizeConditionalInDecrement(N, DAG);
23052 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23053 const X86Subtarget *Subtarget) {
23054 SDValue Op0 = N->getOperand(0);
23055 SDValue Op1 = N->getOperand(1);
23057 // X86 can't encode an immediate LHS of a sub. See if we can push the
23058 // negation into a preceding instruction.
23059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23060 // If the RHS of the sub is a XOR with one use and a constant, invert the
23061 // immediate. Then add one to the LHS of the sub so we can turn
23062 // X-Y -> X+~Y+1, saving one register.
23063 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23064 isa<ConstantSDNode>(Op1.getOperand(1))) {
23065 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23066 EVT VT = Op0.getValueType();
23067 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23069 DAG.getConstant(~XorC, VT));
23070 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23071 DAG.getConstant(C->getAPIntValue()+1, VT));
23075 // Try to synthesize horizontal adds from adds of shuffles.
23076 EVT VT = N->getValueType(0);
23077 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23078 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23079 isHorizontalBinOp(Op0, Op1, true))
23080 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23082 return OptimizeConditionalInDecrement(N, DAG);
23085 /// performVZEXTCombine - Performs build vector combines
23086 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23087 TargetLowering::DAGCombinerInfo &DCI,
23088 const X86Subtarget *Subtarget) {
23089 // (vzext (bitcast (vzext (x)) -> (vzext x)
23090 SDValue In = N->getOperand(0);
23091 while (In.getOpcode() == ISD::BITCAST)
23092 In = In.getOperand(0);
23094 if (In.getOpcode() != X86ISD::VZEXT)
23097 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23101 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23102 DAGCombinerInfo &DCI) const {
23103 SelectionDAG &DAG = DCI.DAG;
23104 switch (N->getOpcode()) {
23106 case ISD::EXTRACT_VECTOR_ELT:
23107 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23109 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23110 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23111 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23112 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23113 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23114 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23117 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23118 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23119 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23120 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23121 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23122 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23123 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23124 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23125 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23127 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23129 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23130 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23131 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23132 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23133 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23134 case ISD::ANY_EXTEND:
23135 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23136 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23137 case ISD::SIGN_EXTEND_INREG:
23138 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23139 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23140 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23141 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23142 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23143 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23144 case X86ISD::SHUFP: // Handle all target specific shuffles
23145 case X86ISD::PALIGNR:
23146 case X86ISD::UNPCKH:
23147 case X86ISD::UNPCKL:
23148 case X86ISD::MOVHLPS:
23149 case X86ISD::MOVLHPS:
23150 case X86ISD::PSHUFB:
23151 case X86ISD::PSHUFD:
23152 case X86ISD::PSHUFHW:
23153 case X86ISD::PSHUFLW:
23154 case X86ISD::MOVSS:
23155 case X86ISD::MOVSD:
23156 case X86ISD::VPERMILP:
23157 case X86ISD::VPERM2X128:
23158 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23159 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23160 case ISD::INTRINSIC_WO_CHAIN:
23161 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23162 case X86ISD::INSERTPS:
23163 return PerformINSERTPSCombine(N, DAG, Subtarget);
23164 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23170 /// isTypeDesirableForOp - Return true if the target has native support for
23171 /// the specified value type and it is 'desirable' to use the type for the
23172 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23173 /// instruction encodings are longer and some i16 instructions are slow.
23174 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23175 if (!isTypeLegal(VT))
23177 if (VT != MVT::i16)
23184 case ISD::SIGN_EXTEND:
23185 case ISD::ZERO_EXTEND:
23186 case ISD::ANY_EXTEND:
23199 /// IsDesirableToPromoteOp - This method query the target whether it is
23200 /// beneficial for dag combiner to promote the specified node. If true, it
23201 /// should return the desired promotion type by reference.
23202 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23203 EVT VT = Op.getValueType();
23204 if (VT != MVT::i16)
23207 bool Promote = false;
23208 bool Commute = false;
23209 switch (Op.getOpcode()) {
23212 LoadSDNode *LD = cast<LoadSDNode>(Op);
23213 // If the non-extending load has a single use and it's not live out, then it
23214 // might be folded.
23215 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23216 Op.hasOneUse()*/) {
23217 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23218 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23219 // The only case where we'd want to promote LOAD (rather then it being
23220 // promoted as an operand is when it's only use is liveout.
23221 if (UI->getOpcode() != ISD::CopyToReg)
23228 case ISD::SIGN_EXTEND:
23229 case ISD::ZERO_EXTEND:
23230 case ISD::ANY_EXTEND:
23235 SDValue N0 = Op.getOperand(0);
23236 // Look out for (store (shl (load), x)).
23237 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23250 SDValue N0 = Op.getOperand(0);
23251 SDValue N1 = Op.getOperand(1);
23252 if (!Commute && MayFoldLoad(N1))
23254 // Avoid disabling potential load folding opportunities.
23255 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23257 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23267 //===----------------------------------------------------------------------===//
23268 // X86 Inline Assembly Support
23269 //===----------------------------------------------------------------------===//
23272 // Helper to match a string separated by whitespace.
23273 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23274 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23276 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23277 StringRef piece(*args[i]);
23278 if (!s.startswith(piece)) // Check if the piece matches.
23281 s = s.substr(piece.size());
23282 StringRef::size_type pos = s.find_first_not_of(" \t");
23283 if (pos == 0) // We matched a prefix.
23291 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23294 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23296 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23297 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23298 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23299 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23301 if (AsmPieces.size() == 3)
23303 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23310 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23311 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23313 std::string AsmStr = IA->getAsmString();
23315 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23316 if (!Ty || Ty->getBitWidth() % 16 != 0)
23319 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23320 SmallVector<StringRef, 4> AsmPieces;
23321 SplitString(AsmStr, AsmPieces, ";\n");
23323 switch (AsmPieces.size()) {
23324 default: return false;
23326 // FIXME: this should verify that we are targeting a 486 or better. If not,
23327 // we will turn this bswap into something that will be lowered to logical
23328 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23329 // lower so don't worry about this.
23331 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23332 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23333 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23334 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23335 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23336 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23337 // No need to check constraints, nothing other than the equivalent of
23338 // "=r,0" would be valid here.
23339 return IntrinsicLowering::LowerToByteSwap(CI);
23342 // rorw $$8, ${0:w} --> llvm.bswap.i16
23343 if (CI->getType()->isIntegerTy(16) &&
23344 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23345 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23346 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23348 const std::string &ConstraintsStr = IA->getConstraintString();
23349 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23350 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23351 if (clobbersFlagRegisters(AsmPieces))
23352 return IntrinsicLowering::LowerToByteSwap(CI);
23356 if (CI->getType()->isIntegerTy(32) &&
23357 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23358 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23359 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23360 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23362 const std::string &ConstraintsStr = IA->getConstraintString();
23363 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23364 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23365 if (clobbersFlagRegisters(AsmPieces))
23366 return IntrinsicLowering::LowerToByteSwap(CI);
23369 if (CI->getType()->isIntegerTy(64)) {
23370 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23371 if (Constraints.size() >= 2 &&
23372 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23373 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23374 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23375 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23376 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23377 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23378 return IntrinsicLowering::LowerToByteSwap(CI);
23386 /// getConstraintType - Given a constraint letter, return the type of
23387 /// constraint it is for this target.
23388 X86TargetLowering::ConstraintType
23389 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23390 if (Constraint.size() == 1) {
23391 switch (Constraint[0]) {
23402 return C_RegisterClass;
23426 return TargetLowering::getConstraintType(Constraint);
23429 /// Examine constraint type and operand type and determine a weight value.
23430 /// This object must already have been set up with the operand type
23431 /// and the current alternative constraint selected.
23432 TargetLowering::ConstraintWeight
23433 X86TargetLowering::getSingleConstraintMatchWeight(
23434 AsmOperandInfo &info, const char *constraint) const {
23435 ConstraintWeight weight = CW_Invalid;
23436 Value *CallOperandVal = info.CallOperandVal;
23437 // If we don't have a value, we can't do a match,
23438 // but allow it at the lowest weight.
23439 if (!CallOperandVal)
23441 Type *type = CallOperandVal->getType();
23442 // Look at the constraint type.
23443 switch (*constraint) {
23445 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23456 if (CallOperandVal->getType()->isIntegerTy())
23457 weight = CW_SpecificReg;
23462 if (type->isFloatingPointTy())
23463 weight = CW_SpecificReg;
23466 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23467 weight = CW_SpecificReg;
23471 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23472 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23473 weight = CW_Register;
23476 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23477 if (C->getZExtValue() <= 31)
23478 weight = CW_Constant;
23482 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23483 if (C->getZExtValue() <= 63)
23484 weight = CW_Constant;
23488 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23489 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23490 weight = CW_Constant;
23494 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23495 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23496 weight = CW_Constant;
23500 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23501 if (C->getZExtValue() <= 3)
23502 weight = CW_Constant;
23506 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23507 if (C->getZExtValue() <= 0xff)
23508 weight = CW_Constant;
23513 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23514 weight = CW_Constant;
23518 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23519 if ((C->getSExtValue() >= -0x80000000LL) &&
23520 (C->getSExtValue() <= 0x7fffffffLL))
23521 weight = CW_Constant;
23525 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23526 if (C->getZExtValue() <= 0xffffffff)
23527 weight = CW_Constant;
23534 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23535 /// with another that has more specific requirements based on the type of the
23536 /// corresponding operand.
23537 const char *X86TargetLowering::
23538 LowerXConstraint(EVT ConstraintVT) const {
23539 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23540 // 'f' like normal targets.
23541 if (ConstraintVT.isFloatingPoint()) {
23542 if (Subtarget->hasSSE2())
23544 if (Subtarget->hasSSE1())
23548 return TargetLowering::LowerXConstraint(ConstraintVT);
23551 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23552 /// vector. If it is invalid, don't add anything to Ops.
23553 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23554 std::string &Constraint,
23555 std::vector<SDValue>&Ops,
23556 SelectionDAG &DAG) const {
23559 // Only support length 1 constraints for now.
23560 if (Constraint.length() > 1) return;
23562 char ConstraintLetter = Constraint[0];
23563 switch (ConstraintLetter) {
23566 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23567 if (C->getZExtValue() <= 31) {
23568 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23574 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23575 if (C->getZExtValue() <= 63) {
23576 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23582 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23583 if (isInt<8>(C->getSExtValue())) {
23584 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23590 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23591 if (C->getZExtValue() <= 255) {
23592 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23598 // 32-bit signed value
23599 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23600 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23601 C->getSExtValue())) {
23602 // Widen to 64 bits here to get it sign extended.
23603 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23606 // FIXME gcc accepts some relocatable values here too, but only in certain
23607 // memory models; it's complicated.
23612 // 32-bit unsigned value
23613 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23614 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23615 C->getZExtValue())) {
23616 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23620 // FIXME gcc accepts some relocatable values here too, but only in certain
23621 // memory models; it's complicated.
23625 // Literal immediates are always ok.
23626 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23627 // Widen to 64 bits here to get it sign extended.
23628 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23632 // In any sort of PIC mode addresses need to be computed at runtime by
23633 // adding in a register or some sort of table lookup. These can't
23634 // be used as immediates.
23635 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23638 // If we are in non-pic codegen mode, we allow the address of a global (with
23639 // an optional displacement) to be used with 'i'.
23640 GlobalAddressSDNode *GA = nullptr;
23641 int64_t Offset = 0;
23643 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23645 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23646 Offset += GA->getOffset();
23648 } else if (Op.getOpcode() == ISD::ADD) {
23649 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23650 Offset += C->getZExtValue();
23651 Op = Op.getOperand(0);
23654 } else if (Op.getOpcode() == ISD::SUB) {
23655 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23656 Offset += -C->getZExtValue();
23657 Op = Op.getOperand(0);
23662 // Otherwise, this isn't something we can handle, reject it.
23666 const GlobalValue *GV = GA->getGlobal();
23667 // If we require an extra load to get this address, as in PIC mode, we
23668 // can't accept it.
23669 if (isGlobalStubReference(
23670 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23673 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23674 GA->getValueType(0), Offset);
23679 if (Result.getNode()) {
23680 Ops.push_back(Result);
23683 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23686 std::pair<unsigned, const TargetRegisterClass*>
23687 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23689 // First, see if this is a constraint that directly corresponds to an LLVM
23691 if (Constraint.size() == 1) {
23692 // GCC Constraint Letters
23693 switch (Constraint[0]) {
23695 // TODO: Slight differences here in allocation order and leaving
23696 // RIP in the class. Do they matter any more here than they do
23697 // in the normal allocation?
23698 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23699 if (Subtarget->is64Bit()) {
23700 if (VT == MVT::i32 || VT == MVT::f32)
23701 return std::make_pair(0U, &X86::GR32RegClass);
23702 if (VT == MVT::i16)
23703 return std::make_pair(0U, &X86::GR16RegClass);
23704 if (VT == MVT::i8 || VT == MVT::i1)
23705 return std::make_pair(0U, &X86::GR8RegClass);
23706 if (VT == MVT::i64 || VT == MVT::f64)
23707 return std::make_pair(0U, &X86::GR64RegClass);
23710 // 32-bit fallthrough
23711 case 'Q': // Q_REGS
23712 if (VT == MVT::i32 || VT == MVT::f32)
23713 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23714 if (VT == MVT::i16)
23715 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23716 if (VT == MVT::i8 || VT == MVT::i1)
23717 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23718 if (VT == MVT::i64)
23719 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23721 case 'r': // GENERAL_REGS
23722 case 'l': // INDEX_REGS
23723 if (VT == MVT::i8 || VT == MVT::i1)
23724 return std::make_pair(0U, &X86::GR8RegClass);
23725 if (VT == MVT::i16)
23726 return std::make_pair(0U, &X86::GR16RegClass);
23727 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23728 return std::make_pair(0U, &X86::GR32RegClass);
23729 return std::make_pair(0U, &X86::GR64RegClass);
23730 case 'R': // LEGACY_REGS
23731 if (VT == MVT::i8 || VT == MVT::i1)
23732 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23733 if (VT == MVT::i16)
23734 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23735 if (VT == MVT::i32 || !Subtarget->is64Bit())
23736 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23737 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23738 case 'f': // FP Stack registers.
23739 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23740 // value to the correct fpstack register class.
23741 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23742 return std::make_pair(0U, &X86::RFP32RegClass);
23743 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23744 return std::make_pair(0U, &X86::RFP64RegClass);
23745 return std::make_pair(0U, &X86::RFP80RegClass);
23746 case 'y': // MMX_REGS if MMX allowed.
23747 if (!Subtarget->hasMMX()) break;
23748 return std::make_pair(0U, &X86::VR64RegClass);
23749 case 'Y': // SSE_REGS if SSE2 allowed
23750 if (!Subtarget->hasSSE2()) break;
23752 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23753 if (!Subtarget->hasSSE1()) break;
23755 switch (VT.SimpleTy) {
23757 // Scalar SSE types.
23760 return std::make_pair(0U, &X86::FR32RegClass);
23763 return std::make_pair(0U, &X86::FR64RegClass);
23771 return std::make_pair(0U, &X86::VR128RegClass);
23779 return std::make_pair(0U, &X86::VR256RegClass);
23784 return std::make_pair(0U, &X86::VR512RegClass);
23790 // Use the default implementation in TargetLowering to convert the register
23791 // constraint into a member of a register class.
23792 std::pair<unsigned, const TargetRegisterClass*> Res;
23793 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23795 // Not found as a standard register?
23797 // Map st(0) -> st(7) -> ST0
23798 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23799 tolower(Constraint[1]) == 's' &&
23800 tolower(Constraint[2]) == 't' &&
23801 Constraint[3] == '(' &&
23802 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23803 Constraint[5] == ')' &&
23804 Constraint[6] == '}') {
23806 Res.first = X86::FP0+Constraint[4]-'0';
23807 Res.second = &X86::RFP80RegClass;
23811 // GCC allows "st(0)" to be called just plain "st".
23812 if (StringRef("{st}").equals_lower(Constraint)) {
23813 Res.first = X86::FP0;
23814 Res.second = &X86::RFP80RegClass;
23819 if (StringRef("{flags}").equals_lower(Constraint)) {
23820 Res.first = X86::EFLAGS;
23821 Res.second = &X86::CCRRegClass;
23825 // 'A' means EAX + EDX.
23826 if (Constraint == "A") {
23827 Res.first = X86::EAX;
23828 Res.second = &X86::GR32_ADRegClass;
23834 // Otherwise, check to see if this is a register class of the wrong value
23835 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23836 // turn into {ax},{dx}.
23837 if (Res.second->hasType(VT))
23838 return Res; // Correct type already, nothing to do.
23840 // All of the single-register GCC register classes map their values onto
23841 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23842 // really want an 8-bit or 32-bit register, map to the appropriate register
23843 // class and return the appropriate register.
23844 if (Res.second == &X86::GR16RegClass) {
23845 if (VT == MVT::i8 || VT == MVT::i1) {
23846 unsigned DestReg = 0;
23847 switch (Res.first) {
23849 case X86::AX: DestReg = X86::AL; break;
23850 case X86::DX: DestReg = X86::DL; break;
23851 case X86::CX: DestReg = X86::CL; break;
23852 case X86::BX: DestReg = X86::BL; break;
23855 Res.first = DestReg;
23856 Res.second = &X86::GR8RegClass;
23858 } else if (VT == MVT::i32 || VT == MVT::f32) {
23859 unsigned DestReg = 0;
23860 switch (Res.first) {
23862 case X86::AX: DestReg = X86::EAX; break;
23863 case X86::DX: DestReg = X86::EDX; break;
23864 case X86::CX: DestReg = X86::ECX; break;
23865 case X86::BX: DestReg = X86::EBX; break;
23866 case X86::SI: DestReg = X86::ESI; break;
23867 case X86::DI: DestReg = X86::EDI; break;
23868 case X86::BP: DestReg = X86::EBP; break;
23869 case X86::SP: DestReg = X86::ESP; break;
23872 Res.first = DestReg;
23873 Res.second = &X86::GR32RegClass;
23875 } else if (VT == MVT::i64 || VT == MVT::f64) {
23876 unsigned DestReg = 0;
23877 switch (Res.first) {
23879 case X86::AX: DestReg = X86::RAX; break;
23880 case X86::DX: DestReg = X86::RDX; break;
23881 case X86::CX: DestReg = X86::RCX; break;
23882 case X86::BX: DestReg = X86::RBX; break;
23883 case X86::SI: DestReg = X86::RSI; break;
23884 case X86::DI: DestReg = X86::RDI; break;
23885 case X86::BP: DestReg = X86::RBP; break;
23886 case X86::SP: DestReg = X86::RSP; break;
23889 Res.first = DestReg;
23890 Res.second = &X86::GR64RegClass;
23893 } else if (Res.second == &X86::FR32RegClass ||
23894 Res.second == &X86::FR64RegClass ||
23895 Res.second == &X86::VR128RegClass ||
23896 Res.second == &X86::VR256RegClass ||
23897 Res.second == &X86::FR32XRegClass ||
23898 Res.second == &X86::FR64XRegClass ||
23899 Res.second == &X86::VR128XRegClass ||
23900 Res.second == &X86::VR256XRegClass ||
23901 Res.second == &X86::VR512RegClass) {
23902 // Handle references to XMM physical registers that got mapped into the
23903 // wrong class. This can happen with constraints like {xmm0} where the
23904 // target independent register mapper will just pick the first match it can
23905 // find, ignoring the required type.
23907 if (VT == MVT::f32 || VT == MVT::i32)
23908 Res.second = &X86::FR32RegClass;
23909 else if (VT == MVT::f64 || VT == MVT::i64)
23910 Res.second = &X86::FR64RegClass;
23911 else if (X86::VR128RegClass.hasType(VT))
23912 Res.second = &X86::VR128RegClass;
23913 else if (X86::VR256RegClass.hasType(VT))
23914 Res.second = &X86::VR256RegClass;
23915 else if (X86::VR512RegClass.hasType(VT))
23916 Res.second = &X86::VR512RegClass;
23922 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23924 // Scaling factors are not free at all.
23925 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23926 // will take 2 allocations in the out of order engine instead of 1
23927 // for plain addressing mode, i.e. inst (reg1).
23929 // vaddps (%rsi,%drx), %ymm0, %ymm1
23930 // Requires two allocations (one for the load, one for the computation)
23932 // vaddps (%rsi), %ymm0, %ymm1
23933 // Requires just 1 allocation, i.e., freeing allocations for other operations
23934 // and having less micro operations to execute.
23936 // For some X86 architectures, this is even worse because for instance for
23937 // stores, the complex addressing mode forces the instruction to use the
23938 // "load" ports instead of the dedicated "store" port.
23939 // E.g., on Haswell:
23940 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23941 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23942 if (isLegalAddressingMode(AM, Ty))
23943 // Scale represents reg2 * scale, thus account for 1
23944 // as soon as we use a second register.
23945 return AM.Scale != 0;
23949 bool X86TargetLowering::isTargetFTOL() const {
23950 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();