1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
253 addBypassSlowDiv(32, 8);
254 if (Subtarget->is64Bit())
255 addBypassSlowDiv(64, 16);
258 if (Subtarget->isTargetKnownWindowsMSVC()) {
259 // Setup Windows compiler runtime calls.
260 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
261 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
262 setLibcallName(RTLIB::SREM_I64, "_allrem");
263 setLibcallName(RTLIB::UREM_I64, "_aullrem");
264 setLibcallName(RTLIB::MUL_I64, "_allmul");
265 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
271 // The _ftol2 runtime function has an unusual calling conv, which
272 // is modeled by a special pseudo-instruction.
273 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
279 if (Subtarget->isTargetDarwin()) {
280 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
281 setUseUnderscoreSetJmp(false);
282 setUseUnderscoreLongJmp(false);
283 } else if (Subtarget->isTargetWindowsGNU()) {
284 // MS runtime is weird: it exports _setjmp, but longjmp!
285 setUseUnderscoreSetJmp(true);
286 setUseUnderscoreLongJmp(false);
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(true);
292 // Set up the register classes.
293 addRegisterClass(MVT::i8, &X86::GR8RegClass);
294 addRegisterClass(MVT::i16, &X86::GR16RegClass);
295 addRegisterClass(MVT::i32, &X86::GR32RegClass);
296 if (Subtarget->is64Bit())
297 addRegisterClass(MVT::i64, &X86::GR64RegClass);
299 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
301 // We don't accept any truncstore of integer registers.
302 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
305 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
306 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
307 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
309 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
311 // SETOEQ and SETUNE require checking two conditions.
312 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
319 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
321 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
325 if (Subtarget->is64Bit()) {
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 } else if (!TM.Options.UseSoftFloat) {
329 // We have an algorithm for SSE2->double, and we turn this into a
330 // 64-bit FILD followed by conditional FADD for other targets.
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 // We have an algorithm for SSE2, and we turn this into a 64-bit
333 // FILD for other targets.
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
337 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
339 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
342 if (!TM.Options.UseSoftFloat) {
343 // SSE has no i16 to fp conversion, only i32
344 if (X86ScalarSSEf32) {
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 // f32 and f64 cases are Legal, f80 case is not
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
357 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
358 // are Legal, f80 is custom lowered.
359 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
360 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
362 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
364 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
367 if (X86ScalarSSEf32) {
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
369 // f32 and f64 cases are Legal, f80 case is not
370 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 // Handle FP_TO_UINT by promoting the destination to a larger signed
378 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
382 if (Subtarget->is64Bit()) {
383 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
385 } else if (!TM.Options.UseSoftFloat) {
386 // Since AVX is a superset of SSE3, only check for SSE here.
387 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
388 // Expand FP_TO_UINT into a select.
389 // FIXME: We would like to use a Custom expander here eventually to do
390 // the optimal thing for SSE vs. the default expansion in the legalizer.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
393 // With SSE3 we can use fisttpll to convert to a signed i64; without
394 // SSE, we're stuck with a fistpll.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
398 if (isTargetFTOL()) {
399 // Use the _ftol2 runtime function, which has a pseudo-instruction
400 // to handle its weird calling convention.
401 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
404 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
405 if (!X86ScalarSSEf64) {
406 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
407 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
408 if (Subtarget->is64Bit()) {
409 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
410 // Without SSE, i64->f64 goes through memory.
411 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
415 // Scalar integer divide and remainder are lowered to use operations that
416 // produce two results, to match the available instructions. This exposes
417 // the two-result form to trivial CSE, which is able to combine x/y and x%y
418 // into a single instruction.
420 // Scalar integer multiply-high is also lowered to use two-result
421 // operations, to match the available instructions. However, plain multiply
422 // (low) operations are left as Legal, as there are single-result
423 // instructions for this in x86. Using the two-result multiply instructions
424 // when both high and low results are needed must be arranged by dagcombine.
425 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
427 setOperationAction(ISD::MULHS, VT, Expand);
428 setOperationAction(ISD::MULHU, VT, Expand);
429 setOperationAction(ISD::SDIV, VT, Expand);
430 setOperationAction(ISD::UDIV, VT, Expand);
431 setOperationAction(ISD::SREM, VT, Expand);
432 setOperationAction(ISD::UREM, VT, Expand);
434 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
435 setOperationAction(ISD::ADDC, VT, Custom);
436 setOperationAction(ISD::ADDE, VT, Custom);
437 setOperationAction(ISD::SUBC, VT, Custom);
438 setOperationAction(ISD::SUBE, VT, Custom);
441 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
442 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
443 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
457 if (Subtarget->is64Bit())
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
462 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f64 , Expand);
465 setOperationAction(ISD::FREM , MVT::f80 , Expand);
466 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
468 // Promote the i8 variants and force them on up to i32 which has a shorter
470 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
471 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
473 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
474 if (Subtarget->hasBMI()) {
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
477 if (Subtarget->is64Bit())
478 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
480 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
481 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
486 if (Subtarget->hasLZCNT()) {
487 // When promoting the i8 variants, force them to i32 for a shorter
489 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
490 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
492 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
495 if (Subtarget->is64Bit())
496 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
498 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
504 if (Subtarget->is64Bit()) {
505 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
510 // Special handling for half-precision floating point conversions.
511 // If we don't have F16C support, then lower half float conversions
512 // into library calls.
513 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
514 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
515 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
518 // There's never any support for operations beyond MVT::f32.
519 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
520 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
524 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
529 if (Subtarget->hasPOPCNT()) {
530 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
532 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
535 if (Subtarget->is64Bit())
536 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
539 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
541 if (!Subtarget->hasMOVBE())
542 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
544 // These should be promoted to a larger select which is supported.
545 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
546 // X86 wants to expand cmov itself.
547 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
563 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
564 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
565 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
566 // support continuation, user-level threading, and etc.. As a result, no
567 // other SjLj exception interfaces are implemented and please don't build
568 // your own exception handling based on them.
569 // LLVM/Clang supports zero-cost DWARF exception handling.
570 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
571 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
574 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
575 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
578 if (Subtarget->is64Bit())
579 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
580 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
581 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
582 if (Subtarget->is64Bit()) {
583 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
584 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
585 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
586 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
589 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
590 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
593 if (Subtarget->is64Bit()) {
594 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
599 if (Subtarget->hasSSE1())
600 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
602 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
604 // Expand certain atomics
605 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
607 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
608 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
609 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
612 if (Subtarget->hasCmpxchg16b()) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
616 // FIXME - use subtarget debug flags
617 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
618 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
619 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
622 if (Subtarget->is64Bit()) {
623 setExceptionPointerRegister(X86::RAX);
624 setExceptionSelectorRegister(X86::RDX);
626 setExceptionPointerRegister(X86::EAX);
627 setExceptionSelectorRegister(X86::EDX);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
632 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
633 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
635 setOperationAction(ISD::TRAP, MVT::Other, Legal);
636 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
638 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
639 setOperationAction(ISD::VASTART , MVT::Other, Custom);
640 setOperationAction(ISD::VAEND , MVT::Other, Expand);
641 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
642 // TargetInfo::X86_64ABIBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Custom);
644 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
646 // TargetInfo::CharPtrBuiltinVaList
647 setOperationAction(ISD::VAARG , MVT::Other, Expand);
648 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
651 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
652 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
654 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
656 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
657 // f32 and f64 use SSE.
658 // Set up the FP register classes.
659 addRegisterClass(MVT::f32, &X86::FR32RegClass);
660 addRegisterClass(MVT::f64, &X86::FR64RegClass);
662 // Use ANDPD to simulate FABS.
663 setOperationAction(ISD::FABS , MVT::f64, Custom);
664 setOperationAction(ISD::FABS , MVT::f32, Custom);
666 // Use XORP to simulate FNEG.
667 setOperationAction(ISD::FNEG , MVT::f64, Custom);
668 setOperationAction(ISD::FNEG , MVT::f32, Custom);
670 // Use ANDPD and ORPD to simulate FCOPYSIGN.
671 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
672 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
674 // Lower this to FGETSIGNx86 plus an AND.
675 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
676 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
678 // We don't support sin/cos/fmod
679 setOperationAction(ISD::FSIN , MVT::f64, Expand);
680 setOperationAction(ISD::FCOS , MVT::f64, Expand);
681 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
682 setOperationAction(ISD::FSIN , MVT::f32, Expand);
683 setOperationAction(ISD::FCOS , MVT::f32, Expand);
684 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
686 // Expand FP immediates into loads from the stack, except for the special
688 addLegalFPImmediate(APFloat(+0.0)); // xorpd
689 addLegalFPImmediate(APFloat(+0.0f)); // xorps
690 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
691 // Use SSE for f32, x87 for f64.
692 // Set up the FP register classes.
693 addRegisterClass(MVT::f32, &X86::FR32RegClass);
694 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
696 // Use ANDPS to simulate FABS.
697 setOperationAction(ISD::FABS , MVT::f32, Custom);
699 // Use XORP to simulate FNEG.
700 setOperationAction(ISD::FNEG , MVT::f32, Custom);
702 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
704 // Use ANDPS and ORPS to simulate FCOPYSIGN.
705 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
706 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
708 // We don't support sin/cos/fmod
709 setOperationAction(ISD::FSIN , MVT::f32, Expand);
710 setOperationAction(ISD::FCOS , MVT::f32, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
713 // Special cases we handle for FP constants.
714 addLegalFPImmediate(APFloat(+0.0f)); // xorps
715 addLegalFPImmediate(APFloat(+0.0)); // FLD0
716 addLegalFPImmediate(APFloat(+1.0)); // FLD1
717 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
718 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
720 if (!TM.Options.UnsafeFPMath) {
721 setOperationAction(ISD::FSIN , MVT::f64, Expand);
722 setOperationAction(ISD::FCOS , MVT::f64, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
725 } else if (!TM.Options.UseSoftFloat) {
726 // f32 and f64 in x87.
727 // Set up the FP register classes.
728 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
729 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
731 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
732 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
736 if (!TM.Options.UnsafeFPMath) {
737 setOperationAction(ISD::FSIN , MVT::f64, Expand);
738 setOperationAction(ISD::FSIN , MVT::f32, Expand);
739 setOperationAction(ISD::FCOS , MVT::f64, Expand);
740 setOperationAction(ISD::FCOS , MVT::f32, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
744 addLegalFPImmediate(APFloat(+0.0)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
748 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
749 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
750 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
751 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
754 // We don't support FMA.
755 setOperationAction(ISD::FMA, MVT::f64, Expand);
756 setOperationAction(ISD::FMA, MVT::f32, Expand);
758 // Long double always uses X87.
759 if (!TM.Options.UseSoftFloat) {
760 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
761 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
762 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
764 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
765 addLegalFPImmediate(TmpFlt); // FLD0
767 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
770 APFloat TmpFlt2(+1.0);
771 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
773 addLegalFPImmediate(TmpFlt2); // FLD1
774 TmpFlt2.changeSign();
775 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
778 if (!TM.Options.UnsafeFPMath) {
779 setOperationAction(ISD::FSIN , MVT::f80, Expand);
780 setOperationAction(ISD::FCOS , MVT::f80, Expand);
781 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
784 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
785 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
786 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
787 setOperationAction(ISD::FRINT, MVT::f80, Expand);
788 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
789 setOperationAction(ISD::FMA, MVT::f80, Expand);
792 // Always use a library call for pow.
793 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
797 setOperationAction(ISD::FLOG, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
802 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
803 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
805 // First set operation action for all vector types to either promote
806 // (for widening) or expand (for scalarization). Then we will selectively
807 // turn on ones that can be effectively codegen'd.
808 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
809 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
810 MVT VT = (MVT::SimpleValueType)i;
811 setOperationAction(ISD::ADD , VT, Expand);
812 setOperationAction(ISD::SUB , VT, Expand);
813 setOperationAction(ISD::FADD, VT, Expand);
814 setOperationAction(ISD::FNEG, VT, Expand);
815 setOperationAction(ISD::FSUB, VT, Expand);
816 setOperationAction(ISD::MUL , VT, Expand);
817 setOperationAction(ISD::FMUL, VT, Expand);
818 setOperationAction(ISD::SDIV, VT, Expand);
819 setOperationAction(ISD::UDIV, VT, Expand);
820 setOperationAction(ISD::FDIV, VT, Expand);
821 setOperationAction(ISD::SREM, VT, Expand);
822 setOperationAction(ISD::UREM, VT, Expand);
823 setOperationAction(ISD::LOAD, VT, Expand);
824 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
827 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::FABS, VT, Expand);
830 setOperationAction(ISD::FSIN, VT, Expand);
831 setOperationAction(ISD::FSINCOS, VT, Expand);
832 setOperationAction(ISD::FCOS, VT, Expand);
833 setOperationAction(ISD::FSINCOS, VT, Expand);
834 setOperationAction(ISD::FREM, VT, Expand);
835 setOperationAction(ISD::FMA, VT, Expand);
836 setOperationAction(ISD::FPOWI, VT, Expand);
837 setOperationAction(ISD::FSQRT, VT, Expand);
838 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
839 setOperationAction(ISD::FFLOOR, VT, Expand);
840 setOperationAction(ISD::FCEIL, VT, Expand);
841 setOperationAction(ISD::FTRUNC, VT, Expand);
842 setOperationAction(ISD::FRINT, VT, Expand);
843 setOperationAction(ISD::FNEARBYINT, VT, Expand);
844 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
845 setOperationAction(ISD::MULHS, VT, Expand);
846 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
847 setOperationAction(ISD::MULHU, VT, Expand);
848 setOperationAction(ISD::SDIVREM, VT, Expand);
849 setOperationAction(ISD::UDIVREM, VT, Expand);
850 setOperationAction(ISD::FPOW, VT, Expand);
851 setOperationAction(ISD::CTPOP, VT, Expand);
852 setOperationAction(ISD::CTTZ, VT, Expand);
853 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
854 setOperationAction(ISD::CTLZ, VT, Expand);
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
856 setOperationAction(ISD::SHL, VT, Expand);
857 setOperationAction(ISD::SRA, VT, Expand);
858 setOperationAction(ISD::SRL, VT, Expand);
859 setOperationAction(ISD::ROTL, VT, Expand);
860 setOperationAction(ISD::ROTR, VT, Expand);
861 setOperationAction(ISD::BSWAP, VT, Expand);
862 setOperationAction(ISD::SETCC, VT, Expand);
863 setOperationAction(ISD::FLOG, VT, Expand);
864 setOperationAction(ISD::FLOG2, VT, Expand);
865 setOperationAction(ISD::FLOG10, VT, Expand);
866 setOperationAction(ISD::FEXP, VT, Expand);
867 setOperationAction(ISD::FEXP2, VT, Expand);
868 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
869 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
870 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
873 setOperationAction(ISD::TRUNCATE, VT, Expand);
874 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
875 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
876 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
877 setOperationAction(ISD::VSELECT, VT, Expand);
878 setOperationAction(ISD::SELECT_CC, VT, Expand);
879 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
880 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
881 setTruncStoreAction(VT,
882 (MVT::SimpleValueType)InnerVT, Expand);
883 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
884 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
886 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
887 // we have to deal with them whether we ask for Expansion or not. Setting
888 // Expand causes its own optimisation problems though, so leave them legal.
889 if (VT.getVectorElementType() == MVT::i1)
890 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
893 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
894 // with -msoft-float, disable use of MMX as well.
895 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
896 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
897 // No operations on x86mmx supported, everything uses intrinsics.
900 // MMX-sized vectors (other than x86mmx) are expected to be expanded
901 // into smaller operations.
902 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
903 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
904 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
905 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
906 setOperationAction(ISD::AND, MVT::v8i8, Expand);
907 setOperationAction(ISD::AND, MVT::v4i16, Expand);
908 setOperationAction(ISD::AND, MVT::v2i32, Expand);
909 setOperationAction(ISD::AND, MVT::v1i64, Expand);
910 setOperationAction(ISD::OR, MVT::v8i8, Expand);
911 setOperationAction(ISD::OR, MVT::v4i16, Expand);
912 setOperationAction(ISD::OR, MVT::v2i32, Expand);
913 setOperationAction(ISD::OR, MVT::v1i64, Expand);
914 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
923 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
924 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
925 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
926 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
932 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
933 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
935 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
936 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
937 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
938 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
939 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
940 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
941 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
942 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
943 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
944 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
946 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
947 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
950 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
951 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
953 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
954 // registers cannot be used even for integer operations.
955 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
956 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
957 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
958 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
960 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
961 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
962 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
963 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
964 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
965 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
966 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
969 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
970 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
971 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
972 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
973 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
974 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
975 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
976 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
977 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
978 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
979 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
980 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
981 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
985 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
986 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
994 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to custom lower non-power-of-2 vectors
998 if (!isPowerOf2_32(VT.getVectorNumElements()))
1000 // Do not attempt to custom lower non-128-bit vectors
1001 if (!VT.is128BitVector())
1003 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1004 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1008 // We support custom legalizing of sext and anyext loads for specific
1009 // memory vector types which we can load as a scalar (or sequence of
1010 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1011 // loads these must work with a single scalar load.
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1029 if (Subtarget->is64Bit()) {
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1034 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1035 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1036 MVT VT = (MVT::SimpleValueType)i;
1038 // Do not attempt to promote non-128-bit vectors
1039 if (!VT.is128BitVector())
1042 setOperationAction(ISD::AND, VT, Promote);
1043 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1044 setOperationAction(ISD::OR, VT, Promote);
1045 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1046 setOperationAction(ISD::XOR, VT, Promote);
1047 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1048 setOperationAction(ISD::LOAD, VT, Promote);
1049 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1050 setOperationAction(ISD::SELECT, VT, Promote);
1051 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1054 // Custom lower v2i64 and v2f64 selects.
1055 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1056 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1057 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1058 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1060 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1061 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1065 // As there is no 64-bit GPR available, we need build a special custom
1066 // sequence to convert from v2i32 to v2f32.
1067 if (!Subtarget->is64Bit())
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1073 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1075 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1080 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1081 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1084 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1087 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1088 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1089 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1090 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1092 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1103 // FIXME: Do we need to handle scalar-to-vector here?
1104 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1106 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1111 // There is no BLENDI for byte vectors. We don't need to custom lower
1112 // some vselects for now.
1113 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1115 // SSE41 brings specific instructions for doing vector sign extend even in
1116 // cases where we don't have SRA.
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1121 // i8 and i16 vectors are custom because the source register and source
1122 // source memory operand types are not the same width. f32 vectors are
1123 // custom since the immediate controlling the insert encodes additional
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1135 // FIXME: these should be Legal, but that's only for the case where
1136 // the index is constant. For now custom expand to deal with that.
1137 if (Subtarget->is64Bit()) {
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1143 if (Subtarget->hasSSE2()) {
1144 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1145 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1147 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1148 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1150 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1151 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1153 // In the customized shift lowering, the legal cases in AVX2 will be
1155 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1156 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1158 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1159 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1161 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1164 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1165 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1172 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1176 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1187 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1189 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1200 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1202 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1203 // even though v8i16 is a legal type.
1204 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1210 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1215 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1217 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1218 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1220 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1253 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1254 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1257 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1258 setOperationAction(ISD::FMA, MVT::f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::f64, Legal);
1262 if (Subtarget->hasInt256()) {
1263 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1264 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1265 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1266 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1268 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1269 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1270 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1271 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1273 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1274 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1275 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1276 // Don't lower v32i8 because there is no 128-bit byte mul
1278 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1281 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1283 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1284 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1286 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1287 // when we have a 256bit-wide blend with immediate.
1288 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1290 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1291 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1292 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1293 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1295 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1296 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1297 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1298 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1300 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1301 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1302 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1303 // Don't lower v32i8 because there is no 128-bit byte mul
1306 // In the customized shift lowering, the legal cases in AVX2 will be
1308 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1309 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1312 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1314 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1316 // Custom lower several nodes for 256-bit types.
1317 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1318 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1319 MVT VT = (MVT::SimpleValueType)i;
1321 // Extract subvector is special because the value type
1322 // (result) is 128-bit but the source is 256-bit wide.
1323 if (VT.is128BitVector())
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1335 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1336 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1339 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1340 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1341 MVT VT = (MVT::SimpleValueType)i;
1343 // Do not attempt to promote non-256-bit vectors
1344 if (!VT.is256BitVector())
1347 setOperationAction(ISD::AND, VT, Promote);
1348 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1349 setOperationAction(ISD::OR, VT, Promote);
1350 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1351 setOperationAction(ISD::XOR, VT, Promote);
1352 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1353 setOperationAction(ISD::LOAD, VT, Promote);
1354 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1355 setOperationAction(ISD::SELECT, VT, Promote);
1356 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1360 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1361 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1362 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1366 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1367 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1368 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1370 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1371 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1372 setOperationAction(ISD::XOR, MVT::i1, Legal);
1373 setOperationAction(ISD::OR, MVT::i1, Legal);
1374 setOperationAction(ISD::AND, MVT::i1, Legal);
1375 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1376 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1382 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1389 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1395 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1399 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1400 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1402 if (Subtarget->is64Bit()) {
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1421 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1444 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1445 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1447 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1459 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1460 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1462 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1463 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1465 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1467 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1470 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1483 if (Subtarget->hasCDI()) {
1484 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1485 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1488 // Custom lower several nodes.
1489 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1490 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1491 MVT VT = (MVT::SimpleValueType)i;
1493 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1494 // Extract subvector is special because the value type
1495 // (result) is 256/128-bit but the source is 512-bit wide.
1496 if (VT.is128BitVector() || VT.is256BitVector())
1497 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1499 if (VT.getVectorElementType() == MVT::i1)
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1502 // Do not attempt to custom lower other non-512-bit vectors
1503 if (!VT.is512BitVector())
1506 if ( EltSize >= 32) {
1507 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1508 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1513 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1516 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1517 MVT VT = (MVT::SimpleValueType)i;
1519 // Do not attempt to promote non-256-bit vectors
1520 if (!VT.is512BitVector())
1523 setOperationAction(ISD::SELECT, VT, Promote);
1524 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1528 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1529 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1530 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1533 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1536 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1537 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1538 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1540 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1541 const MVT VT = (MVT::SimpleValueType)i;
1543 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1545 // Do not attempt to promote non-256-bit vectors
1546 if (!VT.is512BitVector())
1549 if ( EltSize < 32) {
1550 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1551 setOperationAction(ISD::VSELECT, VT, Legal);
1556 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1557 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1558 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1560 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1562 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1598 if (!Subtarget->is64Bit()) {
1599 // These libcalls are not available in 32-bit.
1600 setLibcallName(RTLIB::SHL_I128, nullptr);
1601 setLibcallName(RTLIB::SRL_I128, nullptr);
1602 setLibcallName(RTLIB::SRA_I128, nullptr);
1605 // Combine sin / cos into one node or libcall if possible.
1606 if (Subtarget->hasSinCos()) {
1607 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1608 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1609 if (Subtarget->isTargetDarwin()) {
1610 // For MacOSX, we don't want to the normal expansion of a libcall to
1611 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1613 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1614 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1618 if (Subtarget->isTargetWin64()) {
1619 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1620 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1621 setOperationAction(ISD::SREM, MVT::i128, Custom);
1622 setOperationAction(ISD::UREM, MVT::i128, Custom);
1623 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1627 // We have target-specific dag combine patterns for the following nodes:
1628 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1629 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1630 setTargetDAGCombine(ISD::VSELECT);
1631 setTargetDAGCombine(ISD::SELECT);
1632 setTargetDAGCombine(ISD::SHL);
1633 setTargetDAGCombine(ISD::SRA);
1634 setTargetDAGCombine(ISD::SRL);
1635 setTargetDAGCombine(ISD::OR);
1636 setTargetDAGCombine(ISD::AND);
1637 setTargetDAGCombine(ISD::ADD);
1638 setTargetDAGCombine(ISD::FADD);
1639 setTargetDAGCombine(ISD::FSUB);
1640 setTargetDAGCombine(ISD::FMA);
1641 setTargetDAGCombine(ISD::SUB);
1642 setTargetDAGCombine(ISD::LOAD);
1643 setTargetDAGCombine(ISD::STORE);
1644 setTargetDAGCombine(ISD::ZERO_EXTEND);
1645 setTargetDAGCombine(ISD::ANY_EXTEND);
1646 setTargetDAGCombine(ISD::SIGN_EXTEND);
1647 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1648 setTargetDAGCombine(ISD::TRUNCATE);
1649 setTargetDAGCombine(ISD::SINT_TO_FP);
1650 setTargetDAGCombine(ISD::SETCC);
1651 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1652 setTargetDAGCombine(ISD::BUILD_VECTOR);
1653 if (Subtarget->is64Bit())
1654 setTargetDAGCombine(ISD::MUL);
1655 setTargetDAGCombine(ISD::XOR);
1657 computeRegisterProperties();
1659 // On Darwin, -Os means optimize for size without hurting performance,
1660 // do not reduce the limit.
1661 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1662 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1663 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1664 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1665 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1666 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1667 setPrefLoopAlignment(4); // 2^4 bytes.
1669 // Predictable cmov don't hurt on atom because it's in-order.
1670 PredictableSelectIsExpensive = !Subtarget->isAtom();
1672 setPrefFunctionAlignment(4); // 2^4 bytes.
1674 verifyIntrinsicTables();
1677 // This has so far only been implemented for 64-bit MachO.
1678 bool X86TargetLowering::useLoadStackGuardNode() const {
1679 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1680 Subtarget->is64Bit();
1683 TargetLoweringBase::LegalizeTypeAction
1684 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1685 if (ExperimentalVectorWideningLegalization &&
1686 VT.getVectorNumElements() != 1 &&
1687 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1688 return TypeWidenVector;
1690 return TargetLoweringBase::getPreferredVectorAction(VT);
1693 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1695 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1697 const unsigned NumElts = VT.getVectorNumElements();
1698 const EVT EltVT = VT.getVectorElementType();
1699 if (VT.is512BitVector()) {
1700 if (Subtarget->hasAVX512())
1701 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1702 EltVT == MVT::f32 || EltVT == MVT::f64)
1704 case 8: return MVT::v8i1;
1705 case 16: return MVT::v16i1;
1707 if (Subtarget->hasBWI())
1708 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1710 case 32: return MVT::v32i1;
1711 case 64: return MVT::v64i1;
1715 if (VT.is256BitVector() || VT.is128BitVector()) {
1716 if (Subtarget->hasVLX())
1717 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1718 EltVT == MVT::f32 || EltVT == MVT::f64)
1720 case 2: return MVT::v2i1;
1721 case 4: return MVT::v4i1;
1722 case 8: return MVT::v8i1;
1724 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1725 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1727 case 8: return MVT::v8i1;
1728 case 16: return MVT::v16i1;
1729 case 32: return MVT::v32i1;
1733 return VT.changeVectorElementTypeToInteger();
1736 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1737 /// the desired ByVal argument alignment.
1738 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1741 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1742 if (VTy->getBitWidth() == 128)
1744 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1745 unsigned EltAlign = 0;
1746 getMaxByValAlign(ATy->getElementType(), EltAlign);
1747 if (EltAlign > MaxAlign)
1748 MaxAlign = EltAlign;
1749 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1750 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1751 unsigned EltAlign = 0;
1752 getMaxByValAlign(STy->getElementType(i), EltAlign);
1753 if (EltAlign > MaxAlign)
1754 MaxAlign = EltAlign;
1761 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1762 /// function arguments in the caller parameter area. For X86, aggregates
1763 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1764 /// are at 4-byte boundaries.
1765 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1766 if (Subtarget->is64Bit()) {
1767 // Max of 8 and alignment of type.
1768 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1775 if (Subtarget->hasSSE1())
1776 getMaxByValAlign(Ty, Align);
1780 /// getOptimalMemOpType - Returns the target specific optimal type for load
1781 /// and store operations as a result of memset, memcpy, and memmove
1782 /// lowering. If DstAlign is zero that means it's safe to destination
1783 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1784 /// means there isn't a need to check it against alignment requirement,
1785 /// probably because the source does not need to be loaded. If 'IsMemset' is
1786 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1787 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1788 /// source is constant so it does not need to be loaded.
1789 /// It returns EVT::Other if the type should be determined using generic
1790 /// target-independent logic.
1792 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1793 unsigned DstAlign, unsigned SrcAlign,
1794 bool IsMemset, bool ZeroMemset,
1796 MachineFunction &MF) const {
1797 const Function *F = MF.getFunction();
1798 if ((!IsMemset || ZeroMemset) &&
1799 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1800 Attribute::NoImplicitFloat)) {
1802 (Subtarget->isUnalignedMemAccessFast() ||
1803 ((DstAlign == 0 || DstAlign >= 16) &&
1804 (SrcAlign == 0 || SrcAlign >= 16)))) {
1806 if (Subtarget->hasInt256())
1808 if (Subtarget->hasFp256())
1811 if (Subtarget->hasSSE2())
1813 if (Subtarget->hasSSE1())
1815 } else if (!MemcpyStrSrc && Size >= 8 &&
1816 !Subtarget->is64Bit() &&
1817 Subtarget->hasSSE2()) {
1818 // Do not use f64 to lower memcpy if source is string constant. It's
1819 // better to use i32 to avoid the loads.
1823 if (Subtarget->is64Bit() && Size >= 8)
1828 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1830 return X86ScalarSSEf32;
1831 else if (VT == MVT::f64)
1832 return X86ScalarSSEf64;
1837 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1842 *Fast = Subtarget->isUnalignedMemAccessFast();
1846 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1847 /// current function. The returned value is a member of the
1848 /// MachineJumpTableInfo::JTEntryKind enum.
1849 unsigned X86TargetLowering::getJumpTableEncoding() const {
1850 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1852 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1853 Subtarget->isPICStyleGOT())
1854 return MachineJumpTableInfo::EK_Custom32;
1856 // Otherwise, use the normal jump table encoding heuristics.
1857 return TargetLowering::getJumpTableEncoding();
1861 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1862 const MachineBasicBlock *MBB,
1863 unsigned uid,MCContext &Ctx) const{
1864 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1865 Subtarget->isPICStyleGOT());
1866 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1868 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1869 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1872 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1874 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1875 SelectionDAG &DAG) const {
1876 if (!Subtarget->is64Bit())
1877 // This doesn't have SDLoc associated with it, but is not really the
1878 // same as a Register.
1879 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1883 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1884 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1886 const MCExpr *X86TargetLowering::
1887 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1888 MCContext &Ctx) const {
1889 // X86-64 uses RIP relative addressing based on the jump table label.
1890 if (Subtarget->isPICStyleRIPRel())
1891 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1893 // Otherwise, the reference is relative to the PIC base.
1894 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1897 // FIXME: Why this routine is here? Move to RegInfo!
1898 std::pair<const TargetRegisterClass*, uint8_t>
1899 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1900 const TargetRegisterClass *RRC = nullptr;
1902 switch (VT.SimpleTy) {
1904 return TargetLowering::findRepresentativeClass(VT);
1905 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1906 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1909 RRC = &X86::VR64RegClass;
1911 case MVT::f32: case MVT::f64:
1912 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1913 case MVT::v4f32: case MVT::v2f64:
1914 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1916 RRC = &X86::VR128RegClass;
1919 return std::make_pair(RRC, Cost);
1922 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1923 unsigned &Offset) const {
1924 if (!Subtarget->isTargetLinux())
1927 if (Subtarget->is64Bit()) {
1928 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1930 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1942 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1943 unsigned DestAS) const {
1944 assert(SrcAS != DestAS && "Expected different address spaces!");
1946 return SrcAS < 256 && DestAS < 256;
1949 //===----------------------------------------------------------------------===//
1950 // Return Value Calling Convention Implementation
1951 //===----------------------------------------------------------------------===//
1953 #include "X86GenCallingConv.inc"
1956 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1957 MachineFunction &MF, bool isVarArg,
1958 const SmallVectorImpl<ISD::OutputArg> &Outs,
1959 LLVMContext &Context) const {
1960 SmallVector<CCValAssign, 16> RVLocs;
1961 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1962 return CCInfo.CheckReturn(Outs, RetCC_X86);
1965 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1966 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1971 X86TargetLowering::LowerReturn(SDValue Chain,
1972 CallingConv::ID CallConv, bool isVarArg,
1973 const SmallVectorImpl<ISD::OutputArg> &Outs,
1974 const SmallVectorImpl<SDValue> &OutVals,
1975 SDLoc dl, SelectionDAG &DAG) const {
1976 MachineFunction &MF = DAG.getMachineFunction();
1977 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1979 SmallVector<CCValAssign, 16> RVLocs;
1980 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1981 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1984 SmallVector<SDValue, 6> RetOps;
1985 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1986 // Operand #1 = Bytes To Pop
1987 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1990 // Copy the result values into the output registers.
1991 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1992 CCValAssign &VA = RVLocs[i];
1993 assert(VA.isRegLoc() && "Can only return in registers!");
1994 SDValue ValToCopy = OutVals[i];
1995 EVT ValVT = ValToCopy.getValueType();
1997 // Promote values to the appropriate types
1998 if (VA.getLocInfo() == CCValAssign::SExt)
1999 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2000 else if (VA.getLocInfo() == CCValAssign::ZExt)
2001 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::AExt)
2003 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::BCvt)
2005 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2007 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2008 "Unexpected FP-extend for return value.");
2010 // If this is x86-64, and we disabled SSE, we can't return FP values,
2011 // or SSE or MMX vectors.
2012 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2013 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2014 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2015 report_fatal_error("SSE register return with SSE disabled");
2017 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2018 // llvm-gcc has never done it right and no one has noticed, so this
2019 // should be OK for now.
2020 if (ValVT == MVT::f64 &&
2021 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2022 report_fatal_error("SSE2 register return with SSE2 disabled");
2024 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2025 // the RET instruction and handled by the FP Stackifier.
2026 if (VA.getLocReg() == X86::FP0 ||
2027 VA.getLocReg() == X86::FP1) {
2028 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2029 // change the value to the FP stack register class.
2030 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2031 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2032 RetOps.push_back(ValToCopy);
2033 // Don't emit a copytoreg.
2037 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2038 // which is returned in RAX / RDX.
2039 if (Subtarget->is64Bit()) {
2040 if (ValVT == MVT::x86mmx) {
2041 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2042 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2043 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2045 // If we don't have SSE2 available, convert to v4f32 so the generated
2046 // register is legal.
2047 if (!Subtarget->hasSSE2())
2048 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2053 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2054 Flag = Chain.getValue(1);
2055 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2058 // The x86-64 ABIs require that for returning structs by value we copy
2059 // the sret argument into %rax/%eax (depending on ABI) for the return.
2060 // Win32 requires us to put the sret argument to %eax as well.
2061 // We saved the argument into a virtual register in the entry block,
2062 // so now we copy the value out and into %rax/%eax.
2063 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2064 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2065 MachineFunction &MF = DAG.getMachineFunction();
2066 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2067 unsigned Reg = FuncInfo->getSRetReturnReg();
2069 "SRetReturnReg should have been set in LowerFormalArguments().");
2070 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2073 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2074 X86::RAX : X86::EAX;
2075 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2076 Flag = Chain.getValue(1);
2078 // RAX/EAX now acts like a return value.
2079 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2082 RetOps[0] = Chain; // Update chain.
2084 // Add the flag if we have it.
2086 RetOps.push_back(Flag);
2088 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2091 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2092 if (N->getNumValues() != 1)
2094 if (!N->hasNUsesOfValue(1, 0))
2097 SDValue TCChain = Chain;
2098 SDNode *Copy = *N->use_begin();
2099 if (Copy->getOpcode() == ISD::CopyToReg) {
2100 // If the copy has a glue operand, we conservatively assume it isn't safe to
2101 // perform a tail call.
2102 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2104 TCChain = Copy->getOperand(0);
2105 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2108 bool HasRet = false;
2109 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2111 if (UI->getOpcode() != X86ISD::RET_FLAG)
2113 // If we are returning more than one value, we can definitely
2114 // not make a tail call see PR19530
2115 if (UI->getNumOperands() > 4)
2117 if (UI->getNumOperands() == 4 &&
2118 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2131 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2132 ISD::NodeType ExtendKind) const {
2134 // TODO: Is this also valid on 32-bit?
2135 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2136 ReturnMVT = MVT::i8;
2138 ReturnMVT = MVT::i32;
2140 EVT MinVT = getRegisterType(Context, ReturnMVT);
2141 return VT.bitsLT(MinVT) ? MinVT : VT;
2144 /// LowerCallResult - Lower the result values of a call into the
2145 /// appropriate copies out of appropriate physical registers.
2148 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2149 CallingConv::ID CallConv, bool isVarArg,
2150 const SmallVectorImpl<ISD::InputArg> &Ins,
2151 SDLoc dl, SelectionDAG &DAG,
2152 SmallVectorImpl<SDValue> &InVals) const {
2154 // Assign locations to each value returned by this call.
2155 SmallVector<CCValAssign, 16> RVLocs;
2156 bool Is64Bit = Subtarget->is64Bit();
2157 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2159 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2161 // Copy all of the result registers out of their specified physreg.
2162 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2163 CCValAssign &VA = RVLocs[i];
2164 EVT CopyVT = VA.getValVT();
2166 // If this is x86-64, and we disabled SSE, we can't return FP values
2167 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2168 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2169 report_fatal_error("SSE register return with SSE disabled");
2172 // If we prefer to use the value in xmm registers, copy it out as f80 and
2173 // use a truncate to move it from fp stack reg to xmm reg.
2174 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2175 isScalarFPTypeInSSEReg(VA.getValVT()))
2178 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2179 CopyVT, InFlag).getValue(1);
2180 SDValue Val = Chain.getValue(0);
2182 if (CopyVT != VA.getValVT())
2183 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2184 // This truncation won't change the value.
2185 DAG.getIntPtrConstant(1));
2187 InFlag = Chain.getValue(2);
2188 InVals.push_back(Val);
2194 //===----------------------------------------------------------------------===//
2195 // C & StdCall & Fast Calling Convention implementation
2196 //===----------------------------------------------------------------------===//
2197 // StdCall calling convention seems to be standard for many Windows' API
2198 // routines and around. It differs from C calling convention just a little:
2199 // callee should clean up the stack, not caller. Symbols should be also
2200 // decorated in some fancy way :) It doesn't support any vector arguments.
2201 // For info on fast calling convention see Fast Calling Convention (tail call)
2202 // implementation LowerX86_32FastCCCallTo.
2204 /// CallIsStructReturn - Determines whether a call uses struct return
2206 enum StructReturnType {
2211 static StructReturnType
2212 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2214 return NotStructReturn;
2216 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2217 if (!Flags.isSRet())
2218 return NotStructReturn;
2219 if (Flags.isInReg())
2220 return RegStructReturn;
2221 return StackStructReturn;
2224 /// ArgsAreStructReturn - Determines whether a function uses struct
2225 /// return semantics.
2226 static StructReturnType
2227 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2229 return NotStructReturn;
2231 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2232 if (!Flags.isSRet())
2233 return NotStructReturn;
2234 if (Flags.isInReg())
2235 return RegStructReturn;
2236 return StackStructReturn;
2239 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2240 /// by "Src" to address "Dst" with size and alignment information specified by
2241 /// the specific parameter attribute. The copy will be passed as a byval
2242 /// function parameter.
2244 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2245 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2247 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2249 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2250 /*isVolatile*/false, /*AlwaysInline=*/true,
2251 MachinePointerInfo(), MachinePointerInfo());
2254 /// IsTailCallConvention - Return true if the calling convention is one that
2255 /// supports tail call optimization.
2256 static bool IsTailCallConvention(CallingConv::ID CC) {
2257 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2258 CC == CallingConv::HiPE);
2261 /// \brief Return true if the calling convention is a C calling convention.
2262 static bool IsCCallConvention(CallingConv::ID CC) {
2263 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2264 CC == CallingConv::X86_64_SysV);
2267 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2268 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2272 CallingConv::ID CalleeCC = CS.getCallingConv();
2273 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2279 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2280 /// a tailcall target by changing its ABI.
2281 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2282 bool GuaranteedTailCallOpt) {
2283 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2287 X86TargetLowering::LowerMemArgument(SDValue Chain,
2288 CallingConv::ID CallConv,
2289 const SmallVectorImpl<ISD::InputArg> &Ins,
2290 SDLoc dl, SelectionDAG &DAG,
2291 const CCValAssign &VA,
2292 MachineFrameInfo *MFI,
2294 // Create the nodes corresponding to a load from this parameter slot.
2295 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2296 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2297 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2298 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2301 // If value is passed by pointer we have address passed instead of the value
2303 if (VA.getLocInfo() == CCValAssign::Indirect)
2304 ValVT = VA.getLocVT();
2306 ValVT = VA.getValVT();
2308 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2309 // changed with more analysis.
2310 // In case of tail call optimization mark all arguments mutable. Since they
2311 // could be overwritten by lowering of arguments in case of a tail call.
2312 if (Flags.isByVal()) {
2313 unsigned Bytes = Flags.getByValSize();
2314 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2315 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2316 return DAG.getFrameIndex(FI, getPointerTy());
2318 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2319 VA.getLocMemOffset(), isImmutable);
2320 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2321 return DAG.getLoad(ValVT, dl, Chain, FIN,
2322 MachinePointerInfo::getFixedStack(FI),
2323 false, false, false, 0);
2327 // FIXME: Get this from tablegen.
2328 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2329 const X86Subtarget *Subtarget) {
2330 assert(Subtarget->is64Bit());
2332 if (Subtarget->isCallingConvWin64(CallConv)) {
2333 static const MCPhysReg GPR64ArgRegsWin64[] = {
2334 X86::RCX, X86::RDX, X86::R8, X86::R9
2336 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2339 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2340 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2342 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2345 // FIXME: Get this from tablegen.
2346 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2347 CallingConv::ID CallConv,
2348 const X86Subtarget *Subtarget) {
2349 assert(Subtarget->is64Bit());
2350 if (Subtarget->isCallingConvWin64(CallConv)) {
2351 // The XMM registers which might contain var arg parameters are shadowed
2352 // in their paired GPR. So we only need to save the GPR to their home
2354 // TODO: __vectorcall will change this.
2358 const Function *Fn = MF.getFunction();
2359 bool NoImplicitFloatOps = Fn->getAttributes().
2360 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2361 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2362 "SSE register cannot be used when SSE is disabled!");
2363 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2364 !Subtarget->hasSSE1())
2365 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2369 static const MCPhysReg XMMArgRegs64Bit[] = {
2370 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2371 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2373 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2377 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2378 CallingConv::ID CallConv,
2380 const SmallVectorImpl<ISD::InputArg> &Ins,
2383 SmallVectorImpl<SDValue> &InVals)
2385 MachineFunction &MF = DAG.getMachineFunction();
2386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2388 const Function* Fn = MF.getFunction();
2389 if (Fn->hasExternalLinkage() &&
2390 Subtarget->isTargetCygMing() &&
2391 Fn->getName() == "main")
2392 FuncInfo->setForceFramePointer(true);
2394 MachineFrameInfo *MFI = MF.getFrameInfo();
2395 bool Is64Bit = Subtarget->is64Bit();
2396 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2398 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2399 "Var args not supported with calling convention fastcc, ghc or hipe");
2401 // Assign locations to all of the incoming arguments.
2402 SmallVector<CCValAssign, 16> ArgLocs;
2403 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2405 // Allocate shadow area for Win64
2407 CCInfo.AllocateStack(32, 8);
2409 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2411 unsigned LastVal = ~0U;
2413 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2414 CCValAssign &VA = ArgLocs[i];
2415 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2417 assert(VA.getValNo() != LastVal &&
2418 "Don't support value assigned to multiple locs yet");
2420 LastVal = VA.getValNo();
2422 if (VA.isRegLoc()) {
2423 EVT RegVT = VA.getLocVT();
2424 const TargetRegisterClass *RC;
2425 if (RegVT == MVT::i32)
2426 RC = &X86::GR32RegClass;
2427 else if (Is64Bit && RegVT == MVT::i64)
2428 RC = &X86::GR64RegClass;
2429 else if (RegVT == MVT::f32)
2430 RC = &X86::FR32RegClass;
2431 else if (RegVT == MVT::f64)
2432 RC = &X86::FR64RegClass;
2433 else if (RegVT.is512BitVector())
2434 RC = &X86::VR512RegClass;
2435 else if (RegVT.is256BitVector())
2436 RC = &X86::VR256RegClass;
2437 else if (RegVT.is128BitVector())
2438 RC = &X86::VR128RegClass;
2439 else if (RegVT == MVT::x86mmx)
2440 RC = &X86::VR64RegClass;
2441 else if (RegVT == MVT::i1)
2442 RC = &X86::VK1RegClass;
2443 else if (RegVT == MVT::v8i1)
2444 RC = &X86::VK8RegClass;
2445 else if (RegVT == MVT::v16i1)
2446 RC = &X86::VK16RegClass;
2447 else if (RegVT == MVT::v32i1)
2448 RC = &X86::VK32RegClass;
2449 else if (RegVT == MVT::v64i1)
2450 RC = &X86::VK64RegClass;
2452 llvm_unreachable("Unknown argument type!");
2454 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2455 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2457 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2458 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2460 if (VA.getLocInfo() == CCValAssign::SExt)
2461 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2462 DAG.getValueType(VA.getValVT()));
2463 else if (VA.getLocInfo() == CCValAssign::ZExt)
2464 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::BCvt)
2467 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2469 if (VA.isExtInLoc()) {
2470 // Handle MMX values passed in XMM regs.
2471 if (RegVT.isVector())
2472 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2474 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2477 assert(VA.isMemLoc());
2478 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2481 // If value is passed via pointer - do a load.
2482 if (VA.getLocInfo() == CCValAssign::Indirect)
2483 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2484 MachinePointerInfo(), false, false, false, 0);
2486 InVals.push_back(ArgValue);
2489 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2490 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2491 // The x86-64 ABIs require that for returning structs by value we copy
2492 // the sret argument into %rax/%eax (depending on ABI) for the return.
2493 // Win32 requires us to put the sret argument to %eax as well.
2494 // Save the argument into a virtual register so that we can access it
2495 // from the return points.
2496 if (Ins[i].Flags.isSRet()) {
2497 unsigned Reg = FuncInfo->getSRetReturnReg();
2499 MVT PtrTy = getPointerTy();
2500 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2501 FuncInfo->setSRetReturnReg(Reg);
2503 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2504 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2510 unsigned StackSize = CCInfo.getNextStackOffset();
2511 // Align stack specially for tail calls.
2512 if (FuncIsMadeTailCallSafe(CallConv,
2513 MF.getTarget().Options.GuaranteedTailCallOpt))
2514 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2516 // If the function takes variable number of arguments, make a frame index for
2517 // the start of the first vararg value... for expansion of llvm.va_start. We
2518 // can skip this if there are no va_start calls.
2519 if (MFI->hasVAStart() &&
2520 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2521 CallConv != CallingConv::X86_ThisCall))) {
2522 FuncInfo->setVarArgsFrameIndex(
2523 MFI->CreateFixedObject(1, StackSize, true));
2526 // 64-bit calling conventions support varargs and register parameters, so we
2527 // have to do extra work to spill them in the prologue or forward them to
2529 if (Is64Bit && isVarArg &&
2530 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2531 // Find the first unallocated argument registers.
2532 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2533 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2534 unsigned NumIntRegs =
2535 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2536 unsigned NumXMMRegs =
2537 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2538 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2539 "SSE register cannot be used when SSE is disabled!");
2541 // Gather all the live in physical registers.
2542 SmallVector<SDValue, 6> LiveGPRs;
2543 SmallVector<SDValue, 8> LiveXMMRegs;
2545 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2546 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2548 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2550 if (!ArgXMMs.empty()) {
2551 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2552 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2553 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2554 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2555 LiveXMMRegs.push_back(
2556 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2560 // Store them to the va_list returned by va_start.
2561 if (MFI->hasVAStart()) {
2563 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2564 // Get to the caller-allocated home save location. Add 8 to account
2565 // for the return address.
2566 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2567 FuncInfo->setRegSaveFrameIndex(
2568 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2569 // Fixup to set vararg frame on shadow area (4 x i64).
2571 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2573 // For X86-64, if there are vararg parameters that are passed via
2574 // registers, then we must store them to their spots on the stack so
2575 // they may be loaded by deferencing the result of va_next.
2576 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2577 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2578 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2579 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2582 // Store the integer parameter registers.
2583 SmallVector<SDValue, 8> MemOps;
2584 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2586 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2587 for (SDValue Val : LiveGPRs) {
2588 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2589 DAG.getIntPtrConstant(Offset));
2591 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2592 MachinePointerInfo::getFixedStack(
2593 FuncInfo->getRegSaveFrameIndex(), Offset),
2595 MemOps.push_back(Store);
2599 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2600 // Now store the XMM (fp + vector) parameter registers.
2601 SmallVector<SDValue, 12> SaveXMMOps;
2602 SaveXMMOps.push_back(Chain);
2603 SaveXMMOps.push_back(ALVal);
2604 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2605 FuncInfo->getRegSaveFrameIndex()));
2606 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2607 FuncInfo->getVarArgsFPOffset()));
2608 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2610 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2611 MVT::Other, SaveXMMOps));
2614 if (!MemOps.empty())
2615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2617 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2618 // to the liveout set on a musttail call.
2619 assert(MFI->hasMustTailInVarArgFunc());
2620 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2621 typedef X86MachineFunctionInfo::Forward Forward;
2623 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2625 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2626 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2627 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2630 if (!ArgXMMs.empty()) {
2632 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2633 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2634 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2636 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2638 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2639 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2641 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2647 // Some CCs need callee pop.
2648 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2649 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2650 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2652 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2653 // If this is an sret function, the return should pop the hidden pointer.
2654 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2655 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2656 argsAreStructReturn(Ins) == StackStructReturn)
2657 FuncInfo->setBytesToPopOnReturn(4);
2661 // RegSaveFrameIndex is X86-64 only.
2662 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2663 if (CallConv == CallingConv::X86_FastCall ||
2664 CallConv == CallingConv::X86_ThisCall)
2665 // fastcc functions can't have varargs.
2666 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2669 FuncInfo->setArgumentStackSize(StackSize);
2675 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2676 SDValue StackPtr, SDValue Arg,
2677 SDLoc dl, SelectionDAG &DAG,
2678 const CCValAssign &VA,
2679 ISD::ArgFlagsTy Flags) const {
2680 unsigned LocMemOffset = VA.getLocMemOffset();
2681 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2682 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2683 if (Flags.isByVal())
2684 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2686 return DAG.getStore(Chain, dl, Arg, PtrOff,
2687 MachinePointerInfo::getStack(LocMemOffset),
2691 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2692 /// optimization is performed and it is required.
2694 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2695 SDValue &OutRetAddr, SDValue Chain,
2696 bool IsTailCall, bool Is64Bit,
2697 int FPDiff, SDLoc dl) const {
2698 // Adjust the Return address stack slot.
2699 EVT VT = getPointerTy();
2700 OutRetAddr = getReturnAddressFrameIndex(DAG);
2702 // Load the "old" Return address.
2703 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2704 false, false, false, 0);
2705 return SDValue(OutRetAddr.getNode(), 1);
2708 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2709 /// optimization is performed and it is required (FPDiff!=0).
2710 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2711 SDValue Chain, SDValue RetAddrFrIdx,
2712 EVT PtrVT, unsigned SlotSize,
2713 int FPDiff, SDLoc dl) {
2714 // Store the return address to the appropriate stack slot.
2715 if (!FPDiff) return Chain;
2716 // Calculate the new stack slot for the return address.
2717 int NewReturnAddrFI =
2718 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2720 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2721 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2722 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2728 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2729 SmallVectorImpl<SDValue> &InVals) const {
2730 SelectionDAG &DAG = CLI.DAG;
2732 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2733 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2734 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2735 SDValue Chain = CLI.Chain;
2736 SDValue Callee = CLI.Callee;
2737 CallingConv::ID CallConv = CLI.CallConv;
2738 bool &isTailCall = CLI.IsTailCall;
2739 bool isVarArg = CLI.IsVarArg;
2741 MachineFunction &MF = DAG.getMachineFunction();
2742 bool Is64Bit = Subtarget->is64Bit();
2743 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2744 StructReturnType SR = callIsStructReturn(Outs);
2745 bool IsSibcall = false;
2746 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2748 if (MF.getTarget().Options.DisableTailCalls)
2751 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2753 // Force this to be a tail call. The verifier rules are enough to ensure
2754 // that we can lower this successfully without moving the return address
2757 } else if (isTailCall) {
2758 // Check if it's really possible to do a tail call.
2759 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2760 isVarArg, SR != NotStructReturn,
2761 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2762 Outs, OutVals, Ins, DAG);
2764 // Sibcalls are automatically detected tailcalls which do not require
2766 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2773 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2774 "Var args not supported with calling convention fastcc, ghc or hipe");
2776 // Analyze operands of the call, assigning locations to each operand.
2777 SmallVector<CCValAssign, 16> ArgLocs;
2778 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2780 // Allocate shadow area for Win64
2782 CCInfo.AllocateStack(32, 8);
2784 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2786 // Get a count of how many bytes are to be pushed on the stack.
2787 unsigned NumBytes = CCInfo.getNextStackOffset();
2789 // This is a sibcall. The memory operands are available in caller's
2790 // own caller's stack.
2792 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2793 IsTailCallConvention(CallConv))
2794 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2797 if (isTailCall && !IsSibcall && !IsMustTail) {
2798 // Lower arguments at fp - stackoffset + fpdiff.
2799 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2801 FPDiff = NumBytesCallerPushed - NumBytes;
2803 // Set the delta of movement of the returnaddr stackslot.
2804 // But only set if delta is greater than previous delta.
2805 if (FPDiff < X86Info->getTCReturnAddrDelta())
2806 X86Info->setTCReturnAddrDelta(FPDiff);
2809 unsigned NumBytesToPush = NumBytes;
2810 unsigned NumBytesToPop = NumBytes;
2812 // If we have an inalloca argument, all stack space has already been allocated
2813 // for us and be right at the top of the stack. We don't support multiple
2814 // arguments passed in memory when using inalloca.
2815 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2817 if (!ArgLocs.back().isMemLoc())
2818 report_fatal_error("cannot use inalloca attribute on a register "
2820 if (ArgLocs.back().getLocMemOffset() != 0)
2821 report_fatal_error("any parameter with the inalloca attribute must be "
2822 "the only memory argument");
2826 Chain = DAG.getCALLSEQ_START(
2827 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2829 SDValue RetAddrFrIdx;
2830 // Load return address for tail calls.
2831 if (isTailCall && FPDiff)
2832 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2833 Is64Bit, FPDiff, dl);
2835 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2836 SmallVector<SDValue, 8> MemOpChains;
2839 // Walk the register/memloc assignments, inserting copies/loads. In the case
2840 // of tail call optimization arguments are handle later.
2841 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2842 DAG.getSubtarget().getRegisterInfo());
2843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2844 // Skip inalloca arguments, they have already been written.
2845 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2846 if (Flags.isInAlloca())
2849 CCValAssign &VA = ArgLocs[i];
2850 EVT RegVT = VA.getLocVT();
2851 SDValue Arg = OutVals[i];
2852 bool isByVal = Flags.isByVal();
2854 // Promote the value if needed.
2855 switch (VA.getLocInfo()) {
2856 default: llvm_unreachable("Unknown loc info!");
2857 case CCValAssign::Full: break;
2858 case CCValAssign::SExt:
2859 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2861 case CCValAssign::ZExt:
2862 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::AExt:
2865 if (RegVT.is128BitVector()) {
2866 // Special case: passing MMX values in XMM registers.
2867 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2868 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2869 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2871 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2873 case CCValAssign::BCvt:
2874 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2876 case CCValAssign::Indirect: {
2877 // Store the argument.
2878 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2879 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2880 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2881 MachinePointerInfo::getFixedStack(FI),
2888 if (VA.isRegLoc()) {
2889 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2890 if (isVarArg && IsWin64) {
2891 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2892 // shadow reg if callee is a varargs function.
2893 unsigned ShadowReg = 0;
2894 switch (VA.getLocReg()) {
2895 case X86::XMM0: ShadowReg = X86::RCX; break;
2896 case X86::XMM1: ShadowReg = X86::RDX; break;
2897 case X86::XMM2: ShadowReg = X86::R8; break;
2898 case X86::XMM3: ShadowReg = X86::R9; break;
2901 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2903 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2904 assert(VA.isMemLoc());
2905 if (!StackPtr.getNode())
2906 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2908 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2909 dl, DAG, VA, Flags));
2913 if (!MemOpChains.empty())
2914 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2916 if (Subtarget->isPICStyleGOT()) {
2917 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2920 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2921 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2923 // If we are tail calling and generating PIC/GOT style code load the
2924 // address of the callee into ECX. The value in ecx is used as target of
2925 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2926 // for tail calls on PIC/GOT architectures. Normally we would just put the
2927 // address of GOT into ebx and then call target@PLT. But for tail calls
2928 // ebx would be restored (since ebx is callee saved) before jumping to the
2931 // Note: The actual moving to ECX is done further down.
2932 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2933 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2934 !G->getGlobal()->hasProtectedVisibility())
2935 Callee = LowerGlobalAddress(Callee, DAG);
2936 else if (isa<ExternalSymbolSDNode>(Callee))
2937 Callee = LowerExternalSymbol(Callee, DAG);
2941 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2942 // From AMD64 ABI document:
2943 // For calls that may call functions that use varargs or stdargs
2944 // (prototype-less calls or calls to functions containing ellipsis (...) in
2945 // the declaration) %al is used as hidden argument to specify the number
2946 // of SSE registers used. The contents of %al do not need to match exactly
2947 // the number of registers, but must be an ubound on the number of SSE
2948 // registers used and is in the range 0 - 8 inclusive.
2950 // Count the number of XMM registers allocated.
2951 static const MCPhysReg XMMArgRegs[] = {
2952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2956 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2957 && "SSE registers cannot be used when SSE is disabled");
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2960 DAG.getConstant(NumXMMRegs, MVT::i8)));
2963 if (Is64Bit && isVarArg && IsMustTail) {
2964 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2965 for (const auto &F : Forwards) {
2966 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2967 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2971 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2972 // don't need this because the eligibility check rejects calls that require
2973 // shuffling arguments passed in memory.
2974 if (!IsSibcall && isTailCall) {
2975 // Force all the incoming stack arguments to be loaded from the stack
2976 // before any new outgoing arguments are stored to the stack, because the
2977 // outgoing stack slots may alias the incoming argument stack slots, and
2978 // the alias isn't otherwise explicit. This is slightly more conservative
2979 // than necessary, because it means that each store effectively depends
2980 // on every argument instead of just those arguments it would clobber.
2981 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2983 SmallVector<SDValue, 8> MemOpChains2;
2986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2987 CCValAssign &VA = ArgLocs[i];
2990 assert(VA.isMemLoc());
2991 SDValue Arg = OutVals[i];
2992 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2993 // Skip inalloca arguments. They don't require any work.
2994 if (Flags.isInAlloca())
2996 // Create frame index.
2997 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2998 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2999 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3000 FIN = DAG.getFrameIndex(FI, getPointerTy());
3002 if (Flags.isByVal()) {
3003 // Copy relative to framepointer.
3004 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3005 if (!StackPtr.getNode())
3006 StackPtr = DAG.getCopyFromReg(Chain, dl,
3007 RegInfo->getStackRegister(),
3009 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3011 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3015 // Store relative to framepointer.
3016 MemOpChains2.push_back(
3017 DAG.getStore(ArgChain, dl, Arg, FIN,
3018 MachinePointerInfo::getFixedStack(FI),
3023 if (!MemOpChains2.empty())
3024 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3026 // Store the return address to the appropriate stack slot.
3027 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3028 getPointerTy(), RegInfo->getSlotSize(),
3032 // Build a sequence of copy-to-reg nodes chained together with token chain
3033 // and flag operands which copy the outgoing args into registers.
3035 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3036 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3037 RegsToPass[i].second, InFlag);
3038 InFlag = Chain.getValue(1);
3041 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3042 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3043 // In the 64-bit large code model, we have to make all calls
3044 // through a register, since the call instruction's 32-bit
3045 // pc-relative offset may not be large enough to hold the whole
3047 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3048 // If the callee is a GlobalAddress node (quite common, every direct call
3049 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3052 // We should use extra load for direct calls to dllimported functions in
3054 const GlobalValue *GV = G->getGlobal();
3055 if (!GV->hasDLLImportStorageClass()) {
3056 unsigned char OpFlags = 0;
3057 bool ExtraLoad = false;
3058 unsigned WrapperKind = ISD::DELETED_NODE;
3060 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3061 // external symbols most go through the PLT in PIC mode. If the symbol
3062 // has hidden or protected visibility, or if it is static or local, then
3063 // we don't need to use the PLT - we can directly call it.
3064 if (Subtarget->isTargetELF() &&
3065 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3066 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3067 OpFlags = X86II::MO_PLT;
3068 } else if (Subtarget->isPICStyleStubAny() &&
3069 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3070 (!Subtarget->getTargetTriple().isMacOSX() ||
3071 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3072 // PC-relative references to external symbols should go through $stub,
3073 // unless we're building with the leopard linker or later, which
3074 // automatically synthesizes these stubs.
3075 OpFlags = X86II::MO_DARWIN_STUB;
3076 } else if (Subtarget->isPICStyleRIPRel() &&
3077 isa<Function>(GV) &&
3078 cast<Function>(GV)->getAttributes().
3079 hasAttribute(AttributeSet::FunctionIndex,
3080 Attribute::NonLazyBind)) {
3081 // If the function is marked as non-lazy, generate an indirect call
3082 // which loads from the GOT directly. This avoids runtime overhead
3083 // at the cost of eager binding (and one extra byte of encoding).
3084 OpFlags = X86II::MO_GOTPCREL;
3085 WrapperKind = X86ISD::WrapperRIP;
3089 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3090 G->getOffset(), OpFlags);
3092 // Add a wrapper if needed.
3093 if (WrapperKind != ISD::DELETED_NODE)
3094 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3095 // Add extra indirection if needed.
3097 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3098 MachinePointerInfo::getGOT(),
3099 false, false, false, 0);
3101 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3102 unsigned char OpFlags = 0;
3104 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3105 // external symbols should go through the PLT.
3106 if (Subtarget->isTargetELF() &&
3107 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3108 OpFlags = X86II::MO_PLT;
3109 } else if (Subtarget->isPICStyleStubAny() &&
3110 (!Subtarget->getTargetTriple().isMacOSX() ||
3111 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3112 // PC-relative references to external symbols should go through $stub,
3113 // unless we're building with the leopard linker or later, which
3114 // automatically synthesizes these stubs.
3115 OpFlags = X86II::MO_DARWIN_STUB;
3118 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3120 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3121 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3122 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3125 // Returns a chain & a flag for retval copy to use.
3126 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3127 SmallVector<SDValue, 8> Ops;
3129 if (!IsSibcall && isTailCall) {
3130 Chain = DAG.getCALLSEQ_END(Chain,
3131 DAG.getIntPtrConstant(NumBytesToPop, true),
3132 DAG.getIntPtrConstant(0, true), InFlag, dl);
3133 InFlag = Chain.getValue(1);
3136 Ops.push_back(Chain);
3137 Ops.push_back(Callee);
3140 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3142 // Add argument registers to the end of the list so that they are known live
3144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3145 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3146 RegsToPass[i].second.getValueType()));
3148 // Add a register mask operand representing the call-preserved registers.
3149 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3150 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3151 assert(Mask && "Missing call preserved mask for calling convention");
3152 Ops.push_back(DAG.getRegisterMask(Mask));
3154 if (InFlag.getNode())
3155 Ops.push_back(InFlag);
3159 //// If this is the first return lowered for this function, add the regs
3160 //// to the liveout set for the function.
3161 // This isn't right, although it's probably harmless on x86; liveouts
3162 // should be computed from returns not tail calls. Consider a void
3163 // function making a tail call to a function returning int.
3164 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3167 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3168 InFlag = Chain.getValue(1);
3170 // Create the CALLSEQ_END node.
3171 unsigned NumBytesForCalleeToPop;
3172 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3173 DAG.getTarget().Options.GuaranteedTailCallOpt))
3174 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3175 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3176 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3177 SR == StackStructReturn)
3178 // If this is a call to a struct-return function, the callee
3179 // pops the hidden struct pointer, so we have to push it back.
3180 // This is common for Darwin/X86, Linux & Mingw32 targets.
3181 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3182 NumBytesForCalleeToPop = 4;
3184 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3186 // Returns a flag for retval copy to use.
3188 Chain = DAG.getCALLSEQ_END(Chain,
3189 DAG.getIntPtrConstant(NumBytesToPop, true),
3190 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3193 InFlag = Chain.getValue(1);
3196 // Handle result values, copying them out of physregs into vregs that we
3198 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3199 Ins, dl, DAG, InVals);
3202 //===----------------------------------------------------------------------===//
3203 // Fast Calling Convention (tail call) implementation
3204 //===----------------------------------------------------------------------===//
3206 // Like std call, callee cleans arguments, convention except that ECX is
3207 // reserved for storing the tail called function address. Only 2 registers are
3208 // free for argument passing (inreg). Tail call optimization is performed
3210 // * tailcallopt is enabled
3211 // * caller/callee are fastcc
3212 // On X86_64 architecture with GOT-style position independent code only local
3213 // (within module) calls are supported at the moment.
3214 // To keep the stack aligned according to platform abi the function
3215 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3216 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3217 // If a tail called function callee has more arguments than the caller the
3218 // caller needs to make sure that there is room to move the RETADDR to. This is
3219 // achieved by reserving an area the size of the argument delta right after the
3220 // original RETADDR, but before the saved framepointer or the spilled registers
3221 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3233 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3234 /// for a 16 byte align requirement.
3236 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3237 SelectionDAG& DAG) const {
3238 MachineFunction &MF = DAG.getMachineFunction();
3239 const TargetMachine &TM = MF.getTarget();
3240 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3241 TM.getSubtargetImpl()->getRegisterInfo());
3242 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3243 unsigned StackAlignment = TFI.getStackAlignment();
3244 uint64_t AlignMask = StackAlignment - 1;
3245 int64_t Offset = StackSize;
3246 unsigned SlotSize = RegInfo->getSlotSize();
3247 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3248 // Number smaller than 12 so just add the difference.
3249 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3251 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3252 Offset = ((~AlignMask) & Offset) + StackAlignment +
3253 (StackAlignment-SlotSize);
3258 /// MatchingStackOffset - Return true if the given stack call argument is
3259 /// already available in the same position (relatively) of the caller's
3260 /// incoming argument stack.
3262 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3263 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3264 const X86InstrInfo *TII) {
3265 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3267 if (Arg.getOpcode() == ISD::CopyFromReg) {
3268 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3269 if (!TargetRegisterInfo::isVirtualRegister(VR))
3271 MachineInstr *Def = MRI->getVRegDef(VR);
3274 if (!Flags.isByVal()) {
3275 if (!TII->isLoadFromStackSlot(Def, FI))
3278 unsigned Opcode = Def->getOpcode();
3279 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3280 Def->getOperand(1).isFI()) {
3281 FI = Def->getOperand(1).getIndex();
3282 Bytes = Flags.getByValSize();
3286 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3287 if (Flags.isByVal())
3288 // ByVal argument is passed in as a pointer but it's now being
3289 // dereferenced. e.g.
3290 // define @foo(%struct.X* %A) {
3291 // tail call @bar(%struct.X* byval %A)
3294 SDValue Ptr = Ld->getBasePtr();
3295 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3298 FI = FINode->getIndex();
3299 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3300 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3301 FI = FINode->getIndex();
3302 Bytes = Flags.getByValSize();
3306 assert(FI != INT_MAX);
3307 if (!MFI->isFixedObjectIndex(FI))
3309 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3312 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3313 /// for tail call optimization. Targets which want to do tail call
3314 /// optimization should implement this function.
3316 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3317 CallingConv::ID CalleeCC,
3319 bool isCalleeStructRet,
3320 bool isCallerStructRet,
3322 const SmallVectorImpl<ISD::OutputArg> &Outs,
3323 const SmallVectorImpl<SDValue> &OutVals,
3324 const SmallVectorImpl<ISD::InputArg> &Ins,
3325 SelectionDAG &DAG) const {
3326 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3329 // If -tailcallopt is specified, make fastcc functions tail-callable.
3330 const MachineFunction &MF = DAG.getMachineFunction();
3331 const Function *CallerF = MF.getFunction();
3333 // If the function return type is x86_fp80 and the callee return type is not,
3334 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3335 // perform a tailcall optimization here.
3336 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3339 CallingConv::ID CallerCC = CallerF->getCallingConv();
3340 bool CCMatch = CallerCC == CalleeCC;
3341 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3342 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3344 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3345 if (IsTailCallConvention(CalleeCC) && CCMatch)
3350 // Look for obvious safe cases to perform tail call optimization that do not
3351 // require ABI changes. This is what gcc calls sibcall.
3353 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3354 // emit a special epilogue.
3355 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3356 DAG.getSubtarget().getRegisterInfo());
3357 if (RegInfo->needsStackRealignment(MF))
3360 // Also avoid sibcall optimization if either caller or callee uses struct
3361 // return semantics.
3362 if (isCalleeStructRet || isCallerStructRet)
3365 // An stdcall/thiscall caller is expected to clean up its arguments; the
3366 // callee isn't going to do that.
3367 // FIXME: this is more restrictive than needed. We could produce a tailcall
3368 // when the stack adjustment matches. For example, with a thiscall that takes
3369 // only one argument.
3370 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3371 CallerCC == CallingConv::X86_ThisCall))
3374 // Do not sibcall optimize vararg calls unless all arguments are passed via
3376 if (isVarArg && !Outs.empty()) {
3378 // Optimizing for varargs on Win64 is unlikely to be safe without
3379 // additional testing.
3380 if (IsCalleeWin64 || IsCallerWin64)
3383 SmallVector<CCValAssign, 16> ArgLocs;
3384 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3387 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3388 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3389 if (!ArgLocs[i].isRegLoc())
3393 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3394 // stack. Therefore, if it's not used by the call it is not safe to optimize
3395 // this into a sibcall.
3396 bool Unused = false;
3397 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3404 SmallVector<CCValAssign, 16> RVLocs;
3405 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3407 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3408 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3409 CCValAssign &VA = RVLocs[i];
3410 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3415 // If the calling conventions do not match, then we'd better make sure the
3416 // results are returned in the same way as what the caller expects.
3418 SmallVector<CCValAssign, 16> RVLocs1;
3419 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3421 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3423 SmallVector<CCValAssign, 16> RVLocs2;
3424 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3426 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3428 if (RVLocs1.size() != RVLocs2.size())
3430 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3431 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3433 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3435 if (RVLocs1[i].isRegLoc()) {
3436 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3439 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3445 // If the callee takes no arguments then go on to check the results of the
3447 if (!Outs.empty()) {
3448 // Check if stack adjustment is needed. For now, do not do this if any
3449 // argument is passed on the stack.
3450 SmallVector<CCValAssign, 16> ArgLocs;
3451 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3454 // Allocate shadow area for Win64
3456 CCInfo.AllocateStack(32, 8);
3458 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3459 if (CCInfo.getNextStackOffset()) {
3460 MachineFunction &MF = DAG.getMachineFunction();
3461 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3464 // Check if the arguments are already laid out in the right way as
3465 // the caller's fixed stack objects.
3466 MachineFrameInfo *MFI = MF.getFrameInfo();
3467 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3468 const X86InstrInfo *TII =
3469 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3471 CCValAssign &VA = ArgLocs[i];
3472 SDValue Arg = OutVals[i];
3473 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3474 if (VA.getLocInfo() == CCValAssign::Indirect)
3476 if (!VA.isRegLoc()) {
3477 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3484 // If the tailcall address may be in a register, then make sure it's
3485 // possible to register allocate for it. In 32-bit, the call address can
3486 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3487 // callee-saved registers are restored. These happen to be the same
3488 // registers used to pass 'inreg' arguments so watch out for those.
3489 if (!Subtarget->is64Bit() &&
3490 ((!isa<GlobalAddressSDNode>(Callee) &&
3491 !isa<ExternalSymbolSDNode>(Callee)) ||
3492 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3493 unsigned NumInRegs = 0;
3494 // In PIC we need an extra register to formulate the address computation
3496 unsigned MaxInRegs =
3497 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3499 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3500 CCValAssign &VA = ArgLocs[i];
3503 unsigned Reg = VA.getLocReg();
3506 case X86::EAX: case X86::EDX: case X86::ECX:
3507 if (++NumInRegs == MaxInRegs)
3519 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3520 const TargetLibraryInfo *libInfo) const {
3521 return X86::createFastISel(funcInfo, libInfo);
3524 //===----------------------------------------------------------------------===//
3525 // Other Lowering Hooks
3526 //===----------------------------------------------------------------------===//
3528 static bool MayFoldLoad(SDValue Op) {
3529 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3532 static bool MayFoldIntoStore(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3536 static bool isTargetShuffle(unsigned Opcode) {
3538 default: return false;
3539 case X86ISD::BLENDI:
3540 case X86ISD::PSHUFB:
3541 case X86ISD::PSHUFD:
3542 case X86ISD::PSHUFHW:
3543 case X86ISD::PSHUFLW:
3545 case X86ISD::PALIGNR:
3546 case X86ISD::MOVLHPS:
3547 case X86ISD::MOVLHPD:
3548 case X86ISD::MOVHLPS:
3549 case X86ISD::MOVLPS:
3550 case X86ISD::MOVLPD:
3551 case X86ISD::MOVSHDUP:
3552 case X86ISD::MOVSLDUP:
3553 case X86ISD::MOVDDUP:
3556 case X86ISD::UNPCKL:
3557 case X86ISD::UNPCKH:
3558 case X86ISD::VPERMILPI:
3559 case X86ISD::VPERM2X128:
3560 case X86ISD::VPERMI:
3565 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3566 SDValue V1, SelectionDAG &DAG) {
3568 default: llvm_unreachable("Unknown x86 shuffle node");
3569 case X86ISD::MOVSHDUP:
3570 case X86ISD::MOVSLDUP:
3571 case X86ISD::MOVDDUP:
3572 return DAG.getNode(Opc, dl, VT, V1);
3576 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3577 SDValue V1, unsigned TargetMask,
3578 SelectionDAG &DAG) {
3580 default: llvm_unreachable("Unknown x86 shuffle node");
3581 case X86ISD::PSHUFD:
3582 case X86ISD::PSHUFHW:
3583 case X86ISD::PSHUFLW:
3584 case X86ISD::VPERMILPI:
3585 case X86ISD::VPERMI:
3586 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3590 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3591 SDValue V1, SDValue V2, unsigned TargetMask,
3592 SelectionDAG &DAG) {
3594 default: llvm_unreachable("Unknown x86 shuffle node");
3595 case X86ISD::PALIGNR:
3596 case X86ISD::VALIGN:
3598 case X86ISD::VPERM2X128:
3599 return DAG.getNode(Opc, dl, VT, V1, V2,
3600 DAG.getConstant(TargetMask, MVT::i8));
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVLHPS:
3609 case X86ISD::MOVLHPD:
3610 case X86ISD::MOVHLPS:
3611 case X86ISD::MOVLPS:
3612 case X86ISD::MOVLPD:
3615 case X86ISD::UNPCKL:
3616 case X86ISD::UNPCKH:
3617 return DAG.getNode(Opc, dl, VT, V1, V2);
3621 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3622 MachineFunction &MF = DAG.getMachineFunction();
3623 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3624 DAG.getSubtarget().getRegisterInfo());
3625 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3626 int ReturnAddrIndex = FuncInfo->getRAIndex();
3628 if (ReturnAddrIndex == 0) {
3629 // Set up a frame object for the return address.
3630 unsigned SlotSize = RegInfo->getSlotSize();
3631 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3634 FuncInfo->setRAIndex(ReturnAddrIndex);
3637 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3640 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3641 bool hasSymbolicDisplacement) {
3642 // Offset should fit into 32 bit immediate field.
3643 if (!isInt<32>(Offset))
3646 // If we don't have a symbolic displacement - we don't have any extra
3648 if (!hasSymbolicDisplacement)
3651 // FIXME: Some tweaks might be needed for medium code model.
3652 if (M != CodeModel::Small && M != CodeModel::Kernel)
3655 // For small code model we assume that latest object is 16MB before end of 31
3656 // bits boundary. We may also accept pretty large negative constants knowing
3657 // that all objects are in the positive half of address space.
3658 if (M == CodeModel::Small && Offset < 16*1024*1024)
3661 // For kernel code model we know that all object resist in the negative half
3662 // of 32bits address space. We may not accept negative offsets, since they may
3663 // be just off and we may accept pretty large positive ones.
3664 if (M == CodeModel::Kernel && Offset > 0)
3670 /// isCalleePop - Determines whether the callee is required to pop its
3671 /// own arguments. Callee pop is necessary to support tail calls.
3672 bool X86::isCalleePop(CallingConv::ID CallingConv,
3673 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3674 switch (CallingConv) {
3677 case CallingConv::X86_StdCall:
3678 case CallingConv::X86_FastCall:
3679 case CallingConv::X86_ThisCall:
3681 case CallingConv::Fast:
3682 case CallingConv::GHC:
3683 case CallingConv::HiPE:
3690 /// \brief Return true if the condition is an unsigned comparison operation.
3691 static bool isX86CCUnsigned(unsigned X86CC) {
3693 default: llvm_unreachable("Invalid integer condition!");
3694 case X86::COND_E: return true;
3695 case X86::COND_G: return false;
3696 case X86::COND_GE: return false;
3697 case X86::COND_L: return false;
3698 case X86::COND_LE: return false;
3699 case X86::COND_NE: return true;
3700 case X86::COND_B: return true;
3701 case X86::COND_A: return true;
3702 case X86::COND_BE: return true;
3703 case X86::COND_AE: return true;
3705 llvm_unreachable("covered switch fell through?!");
3708 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3709 /// specific condition code, returning the condition code and the LHS/RHS of the
3710 /// comparison to make.
3711 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3712 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3714 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3715 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3716 // X > -1 -> X == 0, jump !sign.
3717 RHS = DAG.getConstant(0, RHS.getValueType());
3718 return X86::COND_NS;
3720 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3721 // X < 0 -> X == 0, jump on sign.
3724 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3726 RHS = DAG.getConstant(0, RHS.getValueType());
3727 return X86::COND_LE;
3731 switch (SetCCOpcode) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case ISD::SETEQ: return X86::COND_E;
3734 case ISD::SETGT: return X86::COND_G;
3735 case ISD::SETGE: return X86::COND_GE;
3736 case ISD::SETLT: return X86::COND_L;
3737 case ISD::SETLE: return X86::COND_LE;
3738 case ISD::SETNE: return X86::COND_NE;
3739 case ISD::SETULT: return X86::COND_B;
3740 case ISD::SETUGT: return X86::COND_A;
3741 case ISD::SETULE: return X86::COND_BE;
3742 case ISD::SETUGE: return X86::COND_AE;
3746 // First determine if it is required or is profitable to flip the operands.
3748 // If LHS is a foldable load, but RHS is not, flip the condition.
3749 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3750 !ISD::isNON_EXTLoad(RHS.getNode())) {
3751 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3752 std::swap(LHS, RHS);
3755 switch (SetCCOpcode) {
3761 std::swap(LHS, RHS);
3765 // On a floating point condition, the flags are set as follows:
3767 // 0 | 0 | 0 | X > Y
3768 // 0 | 0 | 1 | X < Y
3769 // 1 | 0 | 0 | X == Y
3770 // 1 | 1 | 1 | unordered
3771 switch (SetCCOpcode) {
3772 default: llvm_unreachable("Condcode should be pre-legalized away");
3774 case ISD::SETEQ: return X86::COND_E;
3775 case ISD::SETOLT: // flipped
3777 case ISD::SETGT: return X86::COND_A;
3778 case ISD::SETOLE: // flipped
3780 case ISD::SETGE: return X86::COND_AE;
3781 case ISD::SETUGT: // flipped
3783 case ISD::SETLT: return X86::COND_B;
3784 case ISD::SETUGE: // flipped
3786 case ISD::SETLE: return X86::COND_BE;
3788 case ISD::SETNE: return X86::COND_NE;
3789 case ISD::SETUO: return X86::COND_P;
3790 case ISD::SETO: return X86::COND_NP;
3792 case ISD::SETUNE: return X86::COND_INVALID;
3796 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3797 /// code. Current x86 isa includes the following FP cmov instructions:
3798 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3799 static bool hasFPCMov(unsigned X86CC) {
3815 /// isFPImmLegal - Returns true if the target can instruction select the
3816 /// specified FP immediate natively. If false, the legalizer will
3817 /// materialize the FP immediate as a load from a constant pool.
3818 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3819 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3820 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3826 /// \brief Returns true if it is beneficial to convert a load of a constant
3827 /// to just the constant itself.
3828 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3830 assert(Ty->isIntegerTy());
3832 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3833 if (BitSize == 0 || BitSize > 64)
3838 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3839 /// the specified range (L, H].
3840 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3841 return (Val < 0) || (Val >= Low && Val < Hi);
3844 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3845 /// specified value.
3846 static bool isUndefOrEqual(int Val, int CmpVal) {
3847 return (Val < 0 || Val == CmpVal);
3850 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3851 /// from position Pos and ending in Pos+Size, falls within the specified
3852 /// sequential range (L, L+Pos]. or is undef.
3853 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3854 unsigned Pos, unsigned Size, int Low) {
3855 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3856 if (!isUndefOrEqual(Mask[i], Low))
3861 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3862 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3863 /// operand - by default will match for first operand.
3864 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3865 bool TestSecondOperand = false) {
3866 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3867 VT != MVT::v2f64 && VT != MVT::v2i64)
3870 unsigned NumElems = VT.getVectorNumElements();
3871 unsigned Lo = TestSecondOperand ? NumElems : 0;
3872 unsigned Hi = Lo + NumElems;
3874 for (unsigned i = 0; i < NumElems; ++i)
3875 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3881 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3882 /// is suitable for input to PSHUFHW.
3883 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3884 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3887 // Lower quadword copied in order or undef.
3888 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3891 // Upper quadword shuffled.
3892 for (unsigned i = 4; i != 8; ++i)
3893 if (!isUndefOrInRange(Mask[i], 4, 8))
3896 if (VT == MVT::v16i16) {
3897 // Lower quadword copied in order or undef.
3898 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3901 // Upper quadword shuffled.
3902 for (unsigned i = 12; i != 16; ++i)
3903 if (!isUndefOrInRange(Mask[i], 12, 16))
3910 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3911 /// is suitable for input to PSHUFLW.
3912 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3913 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3916 // Upper quadword copied in order.
3917 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3920 // Lower quadword shuffled.
3921 for (unsigned i = 0; i != 4; ++i)
3922 if (!isUndefOrInRange(Mask[i], 0, 4))
3925 if (VT == MVT::v16i16) {
3926 // Upper quadword copied in order.
3927 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3930 // Lower quadword shuffled.
3931 for (unsigned i = 8; i != 12; ++i)
3932 if (!isUndefOrInRange(Mask[i], 8, 12))
3939 /// \brief Return true if the mask specifies a shuffle of elements that is
3940 /// suitable for input to intralane (palignr) or interlane (valign) vector
3942 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3943 unsigned NumElts = VT.getVectorNumElements();
3944 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3945 unsigned NumLaneElts = NumElts/NumLanes;
3947 // Do not handle 64-bit element shuffles with palignr.
3948 if (NumLaneElts == 2)
3951 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3953 for (i = 0; i != NumLaneElts; ++i) {
3958 // Lane is all undef, go to next lane
3959 if (i == NumLaneElts)
3962 int Start = Mask[i+l];
3964 // Make sure its in this lane in one of the sources
3965 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3966 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3969 // If not lane 0, then we must match lane 0
3970 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3973 // Correct second source to be contiguous with first source
3974 if (Start >= (int)NumElts)
3975 Start -= NumElts - NumLaneElts;
3977 // Make sure we're shifting in the right direction.
3978 if (Start <= (int)(i+l))
3983 // Check the rest of the elements to see if they are consecutive.
3984 for (++i; i != NumLaneElts; ++i) {
3985 int Idx = Mask[i+l];
3987 // Make sure its in this lane
3988 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3989 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3992 // If not lane 0, then we must match lane 0
3993 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3996 if (Idx >= (int)NumElts)
3997 Idx -= NumElts - NumLaneElts;
3999 if (!isUndefOrEqual(Idx, Start+i))
4008 /// \brief Return true if the node specifies a shuffle of elements that is
4009 /// suitable for input to PALIGNR.
4010 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4011 const X86Subtarget *Subtarget) {
4012 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4013 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4014 VT.is512BitVector())
4015 // FIXME: Add AVX512BW.
4018 return isAlignrMask(Mask, VT, false);
4021 /// \brief Return true if the node specifies a shuffle of elements that is
4022 /// suitable for input to VALIGN.
4023 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4024 const X86Subtarget *Subtarget) {
4025 // FIXME: Add AVX512VL.
4026 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4028 return isAlignrMask(Mask, VT, true);
4031 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4032 /// the two vector operands have swapped position.
4033 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4034 unsigned NumElems) {
4035 for (unsigned i = 0; i != NumElems; ++i) {
4039 else if (idx < (int)NumElems)
4040 Mask[i] = idx + NumElems;
4042 Mask[i] = idx - NumElems;
4046 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4047 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4048 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4049 /// reverse of what x86 shuffles want.
4050 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4052 unsigned NumElems = VT.getVectorNumElements();
4053 unsigned NumLanes = VT.getSizeInBits()/128;
4054 unsigned NumLaneElems = NumElems/NumLanes;
4056 if (NumLaneElems != 2 && NumLaneElems != 4)
4059 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4060 bool symetricMaskRequired =
4061 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4063 // VSHUFPSY divides the resulting vector into 4 chunks.
4064 // The sources are also splitted into 4 chunks, and each destination
4065 // chunk must come from a different source chunk.
4067 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4068 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4070 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4071 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4073 // VSHUFPDY divides the resulting vector into 4 chunks.
4074 // The sources are also splitted into 4 chunks, and each destination
4075 // chunk must come from a different source chunk.
4077 // SRC1 => X3 X2 X1 X0
4078 // SRC2 => Y3 Y2 Y1 Y0
4080 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4082 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4083 unsigned HalfLaneElems = NumLaneElems/2;
4084 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4085 for (unsigned i = 0; i != NumLaneElems; ++i) {
4086 int Idx = Mask[i+l];
4087 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4088 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4090 // For VSHUFPSY, the mask of the second half must be the same as the
4091 // first but with the appropriate offsets. This works in the same way as
4092 // VPERMILPS works with masks.
4093 if (!symetricMaskRequired || Idx < 0)
4095 if (MaskVal[i] < 0) {
4096 MaskVal[i] = Idx - l;
4099 if ((signed)(Idx - l) != MaskVal[i])
4107 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4108 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4109 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4110 if (!VT.is128BitVector())
4113 unsigned NumElems = VT.getVectorNumElements();
4118 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4119 return isUndefOrEqual(Mask[0], 6) &&
4120 isUndefOrEqual(Mask[1], 7) &&
4121 isUndefOrEqual(Mask[2], 2) &&
4122 isUndefOrEqual(Mask[3], 3);
4125 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4126 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4128 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4129 if (!VT.is128BitVector())
4132 unsigned NumElems = VT.getVectorNumElements();
4137 return isUndefOrEqual(Mask[0], 2) &&
4138 isUndefOrEqual(Mask[1], 3) &&
4139 isUndefOrEqual(Mask[2], 2) &&
4140 isUndefOrEqual(Mask[3], 3);
4143 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4144 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4145 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4146 if (!VT.is128BitVector())
4149 unsigned NumElems = VT.getVectorNumElements();
4151 if (NumElems != 2 && NumElems != 4)
4154 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4155 if (!isUndefOrEqual(Mask[i], i + NumElems))
4158 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4159 if (!isUndefOrEqual(Mask[i], i))
4165 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4166 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4167 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4168 if (!VT.is128BitVector())
4171 unsigned NumElems = VT.getVectorNumElements();
4173 if (NumElems != 2 && NumElems != 4)
4176 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4177 if (!isUndefOrEqual(Mask[i], i))
4180 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4181 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4187 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4188 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4189 /// i. e: If all but one element come from the same vector.
4190 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4191 // TODO: Deal with AVX's VINSERTPS
4192 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4195 unsigned CorrectPosV1 = 0;
4196 unsigned CorrectPosV2 = 0;
4197 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4198 if (Mask[i] == -1) {
4206 else if (Mask[i] == i + 4)
4210 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4211 // We have 3 elements (undefs count as elements from any vector) from one
4212 // vector, and one from another.
4219 // Some special combinations that can be optimized.
4222 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4223 SelectionDAG &DAG) {
4224 MVT VT = SVOp->getSimpleValueType(0);
4227 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4230 ArrayRef<int> Mask = SVOp->getMask();
4232 // These are the special masks that may be optimized.
4233 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4234 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4235 bool MatchEvenMask = true;
4236 bool MatchOddMask = true;
4237 for (int i=0; i<8; ++i) {
4238 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4239 MatchEvenMask = false;
4240 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4241 MatchOddMask = false;
4244 if (!MatchEvenMask && !MatchOddMask)
4247 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4249 SDValue Op0 = SVOp->getOperand(0);
4250 SDValue Op1 = SVOp->getOperand(1);
4252 if (MatchEvenMask) {
4253 // Shift the second operand right to 32 bits.
4254 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4255 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4257 // Shift the first operand left to 32 bits.
4258 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4259 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4261 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4262 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4265 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4266 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4267 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4268 bool HasInt256, bool V2IsSplat = false) {
4270 assert(VT.getSizeInBits() >= 128 &&
4271 "Unsupported vector type for unpckl");
4273 unsigned NumElts = VT.getVectorNumElements();
4274 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4275 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4278 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4279 "Unsupported vector type for unpckh");
4281 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4282 unsigned NumLanes = VT.getSizeInBits()/128;
4283 unsigned NumLaneElts = NumElts/NumLanes;
4285 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4286 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4287 int BitI = Mask[l+i];
4288 int BitI1 = Mask[l+i+1];
4289 if (!isUndefOrEqual(BitI, j))
4292 if (!isUndefOrEqual(BitI1, NumElts))
4295 if (!isUndefOrEqual(BitI1, j + NumElts))
4304 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4305 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4306 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4307 bool HasInt256, bool V2IsSplat = false) {
4308 assert(VT.getSizeInBits() >= 128 &&
4309 "Unsupported vector type for unpckh");
4311 unsigned NumElts = VT.getVectorNumElements();
4312 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4313 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4316 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4317 "Unsupported vector type for unpckh");
4319 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4320 unsigned NumLanes = VT.getSizeInBits()/128;
4321 unsigned NumLaneElts = NumElts/NumLanes;
4323 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4324 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4325 int BitI = Mask[l+i];
4326 int BitI1 = Mask[l+i+1];
4327 if (!isUndefOrEqual(BitI, j))
4330 if (isUndefOrEqual(BitI1, NumElts))
4333 if (!isUndefOrEqual(BitI1, j+NumElts))
4341 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4342 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4344 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4345 unsigned NumElts = VT.getVectorNumElements();
4346 bool Is256BitVec = VT.is256BitVector();
4348 if (VT.is512BitVector())
4350 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4351 "Unsupported vector type for unpckh");
4353 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4354 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4357 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4358 // FIXME: Need a better way to get rid of this, there's no latency difference
4359 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4360 // the former later. We should also remove the "_undef" special mask.
4361 if (NumElts == 4 && Is256BitVec)
4364 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4365 // independently on 128-bit lanes.
4366 unsigned NumLanes = VT.getSizeInBits()/128;
4367 unsigned NumLaneElts = NumElts/NumLanes;
4369 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4370 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4371 int BitI = Mask[l+i];
4372 int BitI1 = Mask[l+i+1];
4374 if (!isUndefOrEqual(BitI, j))
4376 if (!isUndefOrEqual(BitI1, j))
4384 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4385 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4387 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4388 unsigned NumElts = VT.getVectorNumElements();
4390 if (VT.is512BitVector())
4393 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4394 "Unsupported vector type for unpckh");
4396 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4397 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4400 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4401 // independently on 128-bit lanes.
4402 unsigned NumLanes = VT.getSizeInBits()/128;
4403 unsigned NumLaneElts = NumElts/NumLanes;
4405 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4406 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4407 int BitI = Mask[l+i];
4408 int BitI1 = Mask[l+i+1];
4409 if (!isUndefOrEqual(BitI, j))
4411 if (!isUndefOrEqual(BitI1, j))
4418 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4419 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4420 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4421 if (!VT.is512BitVector())
4424 unsigned NumElts = VT.getVectorNumElements();
4425 unsigned HalfSize = NumElts/2;
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4432 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4433 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4441 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4442 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4443 /// MOVSD, and MOVD, i.e. setting the lowest element.
4444 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4445 if (VT.getVectorElementType().getSizeInBits() < 32)
4447 if (!VT.is128BitVector())
4450 unsigned NumElts = VT.getVectorNumElements();
4452 if (!isUndefOrEqual(Mask[0], NumElts))
4455 for (unsigned i = 1; i != NumElts; ++i)
4456 if (!isUndefOrEqual(Mask[i], i))
4462 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4463 /// as permutations between 128-bit chunks or halves. As an example: this
4465 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4466 /// The first half comes from the second half of V1 and the second half from the
4467 /// the second half of V2.
4468 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4469 if (!HasFp256 || !VT.is256BitVector())
4472 // The shuffle result is divided into half A and half B. In total the two
4473 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4474 // B must come from C, D, E or F.
4475 unsigned HalfSize = VT.getVectorNumElements()/2;
4476 bool MatchA = false, MatchB = false;
4478 // Check if A comes from one of C, D, E, F.
4479 for (unsigned Half = 0; Half != 4; ++Half) {
4480 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4486 // Check if B comes from one of C, D, E, F.
4487 for (unsigned Half = 0; Half != 4; ++Half) {
4488 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4494 return MatchA && MatchB;
4497 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4498 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4499 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4500 MVT VT = SVOp->getSimpleValueType(0);
4502 unsigned HalfSize = VT.getVectorNumElements()/2;
4504 unsigned FstHalf = 0, SndHalf = 0;
4505 for (unsigned i = 0; i < HalfSize; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4511 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4512 if (SVOp->getMaskElt(i) > 0) {
4513 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4518 return (FstHalf | (SndHalf << 4));
4521 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4522 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4523 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4527 unsigned NumElts = VT.getVectorNumElements();
4529 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4530 for (unsigned i = 0; i != NumElts; ++i) {
4533 Imm8 |= Mask[i] << (i*2);
4538 unsigned LaneSize = 4;
4539 SmallVector<int, 4> MaskVal(LaneSize, -1);
4541 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4542 for (unsigned i = 0; i != LaneSize; ++i) {
4543 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4547 if (MaskVal[i] < 0) {
4548 MaskVal[i] = Mask[i+l] - l;
4549 Imm8 |= MaskVal[i] << (i*2);
4552 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4559 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4560 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4561 /// Note that VPERMIL mask matching is different depending whether theunderlying
4562 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4563 /// to the same elements of the low, but to the higher half of the source.
4564 /// In VPERMILPD the two lanes could be shuffled independently of each other
4565 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4566 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4567 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4568 if (VT.getSizeInBits() < 256 || EltSize < 32)
4570 bool symetricMaskRequired = (EltSize == 32);
4571 unsigned NumElts = VT.getVectorNumElements();
4573 unsigned NumLanes = VT.getSizeInBits()/128;
4574 unsigned LaneSize = NumElts/NumLanes;
4575 // 2 or 4 elements in one lane
4577 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4578 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4579 for (unsigned i = 0; i != LaneSize; ++i) {
4580 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4582 if (symetricMaskRequired) {
4583 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4584 ExpectedMaskVal[i] = Mask[i+l] - l;
4587 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4595 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4596 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4597 /// element of vector 2 and the other elements to come from vector 1 in order.
4598 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4599 bool V2IsSplat = false, bool V2IsUndef = false) {
4600 if (!VT.is128BitVector())
4603 unsigned NumOps = VT.getVectorNumElements();
4604 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4607 if (!isUndefOrEqual(Mask[0], 0))
4610 for (unsigned i = 1; i != NumOps; ++i)
4611 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4612 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4613 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4619 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4620 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4621 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4622 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4623 const X86Subtarget *Subtarget) {
4624 if (!Subtarget->hasSSE3())
4627 unsigned NumElems = VT.getVectorNumElements();
4629 if ((VT.is128BitVector() && NumElems != 4) ||
4630 (VT.is256BitVector() && NumElems != 8) ||
4631 (VT.is512BitVector() && NumElems != 16))
4634 // "i+1" is the value the indexed mask element must have
4635 for (unsigned i = 0; i != NumElems; i += 2)
4636 if (!isUndefOrEqual(Mask[i], i+1) ||
4637 !isUndefOrEqual(Mask[i+1], i+1))
4643 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4644 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4645 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4646 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4647 const X86Subtarget *Subtarget) {
4648 if (!Subtarget->hasSSE3())
4651 unsigned NumElems = VT.getVectorNumElements();
4653 if ((VT.is128BitVector() && NumElems != 4) ||
4654 (VT.is256BitVector() && NumElems != 8) ||
4655 (VT.is512BitVector() && NumElems != 16))
4658 // "i" is the value the indexed mask element must have
4659 for (unsigned i = 0; i != NumElems; i += 2)
4660 if (!isUndefOrEqual(Mask[i], i) ||
4661 !isUndefOrEqual(Mask[i+1], i))
4667 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4668 /// specifies a shuffle of elements that is suitable for input to 256-bit
4669 /// version of MOVDDUP.
4670 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4671 if (!HasFp256 || !VT.is256BitVector())
4674 unsigned NumElts = VT.getVectorNumElements();
4678 for (unsigned i = 0; i != NumElts/2; ++i)
4679 if (!isUndefOrEqual(Mask[i], 0))
4681 for (unsigned i = NumElts/2; i != NumElts; ++i)
4682 if (!isUndefOrEqual(Mask[i], NumElts/2))
4687 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4688 /// specifies a shuffle of elements that is suitable for input to 128-bit
4689 /// version of MOVDDUP.
4690 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4691 if (!VT.is128BitVector())
4694 unsigned e = VT.getVectorNumElements() / 2;
4695 for (unsigned i = 0; i != e; ++i)
4696 if (!isUndefOrEqual(Mask[i], i))
4698 for (unsigned i = 0; i != e; ++i)
4699 if (!isUndefOrEqual(Mask[e+i], i))
4704 /// isVEXTRACTIndex - Return true if the specified
4705 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4706 /// suitable for instruction that extract 128 or 256 bit vectors
4707 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4708 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4709 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4712 // The index should be aligned on a vecWidth-bit boundary.
4714 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4716 MVT VT = N->getSimpleValueType(0);
4717 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4718 bool Result = (Index * ElSize) % vecWidth == 0;
4723 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4724 /// operand specifies a subvector insert that is suitable for input to
4725 /// insertion of 128 or 256-bit subvectors
4726 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4727 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4728 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4730 // The index should be aligned on a vecWidth-bit boundary.
4732 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4734 MVT VT = N->getSimpleValueType(0);
4735 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4736 bool Result = (Index * ElSize) % vecWidth == 0;
4741 bool X86::isVINSERT128Index(SDNode *N) {
4742 return isVINSERTIndex(N, 128);
4745 bool X86::isVINSERT256Index(SDNode *N) {
4746 return isVINSERTIndex(N, 256);
4749 bool X86::isVEXTRACT128Index(SDNode *N) {
4750 return isVEXTRACTIndex(N, 128);
4753 bool X86::isVEXTRACT256Index(SDNode *N) {
4754 return isVEXTRACTIndex(N, 256);
4757 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4758 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4759 /// Handles 128-bit and 256-bit.
4760 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4761 MVT VT = N->getSimpleValueType(0);
4763 assert((VT.getSizeInBits() >= 128) &&
4764 "Unsupported vector type for PSHUF/SHUFP");
4766 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4767 // independently on 128-bit lanes.
4768 unsigned NumElts = VT.getVectorNumElements();
4769 unsigned NumLanes = VT.getSizeInBits()/128;
4770 unsigned NumLaneElts = NumElts/NumLanes;
4772 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4773 "Only supports 2, 4 or 8 elements per lane");
4775 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4777 for (unsigned i = 0; i != NumElts; ++i) {
4778 int Elt = N->getMaskElt(i);
4779 if (Elt < 0) continue;
4780 Elt &= NumLaneElts - 1;
4781 unsigned ShAmt = (i << Shift) % 8;
4782 Mask |= Elt << ShAmt;
4788 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4789 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4790 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4791 MVT VT = N->getSimpleValueType(0);
4793 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4794 "Unsupported vector type for PSHUFHW");
4796 unsigned NumElts = VT.getVectorNumElements();
4799 for (unsigned l = 0; l != NumElts; l += 8) {
4800 // 8 nodes per lane, but we only care about the last 4.
4801 for (unsigned i = 0; i < 4; ++i) {
4802 int Elt = N->getMaskElt(l+i+4);
4803 if (Elt < 0) continue;
4804 Elt &= 0x3; // only 2-bits.
4805 Mask |= Elt << (i * 2);
4812 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4813 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4814 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4815 MVT VT = N->getSimpleValueType(0);
4817 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4818 "Unsupported vector type for PSHUFHW");
4820 unsigned NumElts = VT.getVectorNumElements();
4823 for (unsigned l = 0; l != NumElts; l += 8) {
4824 // 8 nodes per lane, but we only care about the first 4.
4825 for (unsigned i = 0; i < 4; ++i) {
4826 int Elt = N->getMaskElt(l+i);
4827 if (Elt < 0) continue;
4828 Elt &= 0x3; // only 2-bits
4829 Mask |= Elt << (i * 2);
4836 /// \brief Return the appropriate immediate to shuffle the specified
4837 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4838 /// VALIGN (if Interlane is true) instructions.
4839 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4841 MVT VT = SVOp->getSimpleValueType(0);
4842 unsigned EltSize = InterLane ? 1 :
4843 VT.getVectorElementType().getSizeInBits() >> 3;
4845 unsigned NumElts = VT.getVectorNumElements();
4846 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4847 unsigned NumLaneElts = NumElts/NumLanes;
4851 for (i = 0; i != NumElts; ++i) {
4852 Val = SVOp->getMaskElt(i);
4856 if (Val >= (int)NumElts)
4857 Val -= NumElts - NumLaneElts;
4859 assert(Val - i > 0 && "PALIGNR imm should be positive");
4860 return (Val - i) * EltSize;
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4865 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, false);
4869 /// \brief Return the appropriate immediate to shuffle the specified
4870 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4871 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4872 return getShuffleAlignrImmediate(SVOp, true);
4876 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4877 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4878 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4879 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4882 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4884 MVT VecVT = N->getOperand(0).getSimpleValueType();
4885 MVT ElVT = VecVT.getVectorElementType();
4887 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4888 return Index / NumElemsPerChunk;
4891 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4892 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4893 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4894 llvm_unreachable("Illegal insert subvector for VINSERT");
4897 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4899 MVT VecVT = N->getSimpleValueType(0);
4900 MVT ElVT = VecVT.getVectorElementType();
4902 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4903 return Index / NumElemsPerChunk;
4906 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4908 /// and VINSERTI128 instructions.
4909 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 128);
4913 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4914 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4915 /// and VINSERTI64x4 instructions.
4916 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4917 return getExtractVEXTRACTImmediate(N, 256);
4920 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4922 /// and VINSERTI128 instructions.
4923 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 128);
4927 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4928 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4929 /// and VINSERTI64x4 instructions.
4930 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4931 return getInsertVINSERTImmediate(N, 256);
4934 /// isZero - Returns true if Elt is a constant integer zero
4935 static bool isZero(SDValue V) {
4936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4937 return C && C->isNullValue();
4940 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4942 bool X86::isZeroNode(SDValue Elt) {
4945 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4946 return CFP->getValueAPF().isPosZero();
4950 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4951 /// match movhlps. The lower half elements should come from upper half of
4952 /// V1 (and in order), and the upper half elements should come from the upper
4953 /// half of V2 (and in order).
4954 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4955 if (!VT.is128BitVector())
4957 if (VT.getVectorNumElements() != 4)
4959 for (unsigned i = 0, e = 2; i != e; ++i)
4960 if (!isUndefOrEqual(Mask[i], i+2))
4962 for (unsigned i = 2; i != 4; ++i)
4963 if (!isUndefOrEqual(Mask[i], i+4))
4968 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4969 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4971 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4972 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4974 N = N->getOperand(0).getNode();
4975 if (!ISD::isNON_EXTLoad(N))
4978 *LD = cast<LoadSDNode>(N);
4982 // Test whether the given value is a vector value which will be legalized
4984 static bool WillBeConstantPoolLoad(SDNode *N) {
4985 if (N->getOpcode() != ISD::BUILD_VECTOR)
4988 // Check for any non-constant elements.
4989 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4990 switch (N->getOperand(i).getNode()->getOpcode()) {
4992 case ISD::ConstantFP:
4999 // Vectors of all-zeros and all-ones are materialized with special
5000 // instructions rather than being loaded.
5001 return !ISD::isBuildVectorAllZeros(N) &&
5002 !ISD::isBuildVectorAllOnes(N);
5005 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5006 /// match movlp{s|d}. The lower half elements should come from lower half of
5007 /// V1 (and in order), and the upper half elements should come from the upper
5008 /// half of V2 (and in order). And since V1 will become the source of the
5009 /// MOVLP, it must be either a vector load or a scalar load to vector.
5010 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5011 ArrayRef<int> Mask, MVT VT) {
5012 if (!VT.is128BitVector())
5015 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5017 // Is V2 is a vector load, don't do this transformation. We will try to use
5018 // load folding shufps op.
5019 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5022 unsigned NumElems = VT.getVectorNumElements();
5024 if (NumElems != 2 && NumElems != 4)
5026 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5027 if (!isUndefOrEqual(Mask[i], i))
5029 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5030 if (!isUndefOrEqual(Mask[i], i+NumElems))
5035 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5036 /// to an zero vector.
5037 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5038 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5039 SDValue V1 = N->getOperand(0);
5040 SDValue V2 = N->getOperand(1);
5041 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5042 for (unsigned i = 0; i != NumElems; ++i) {
5043 int Idx = N->getMaskElt(i);
5044 if (Idx >= (int)NumElems) {
5045 unsigned Opc = V2.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5051 } else if (Idx >= 0) {
5052 unsigned Opc = V1.getOpcode();
5053 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5055 if (Opc != ISD::BUILD_VECTOR ||
5056 !X86::isZeroNode(V1.getOperand(Idx)))
5063 /// getZeroVector - Returns a vector of specified type with all zero elements.
5065 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5066 SelectionDAG &DAG, SDLoc dl) {
5067 assert(VT.isVector() && "Expected a vector type");
5069 // Always build SSE zero vectors as <4 x i32> bitcasted
5070 // to their dest type. This ensures they get CSE'd.
5072 if (VT.is128BitVector()) { // SSE
5073 if (Subtarget->hasSSE2()) { // SSE2
5074 SDValue Cst = DAG.getConstant(0, MVT::i32);
5075 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5077 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5080 } else if (VT.is256BitVector()) { // AVX
5081 if (Subtarget->hasInt256()) { // AVX2
5082 SDValue Cst = DAG.getConstant(0, MVT::i32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5086 // 256-bit logic and arithmetic instructions in AVX are all
5087 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5088 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5092 } else if (VT.is512BitVector()) { // AVX-512
5093 SDValue Cst = DAG.getConstant(0, MVT::i32);
5094 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5095 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5096 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5097 } else if (VT.getScalarType() == MVT::i1) {
5098 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5099 SDValue Cst = DAG.getConstant(0, MVT::i1);
5100 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5101 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5103 llvm_unreachable("Unexpected vector type");
5105 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5108 /// getOnesVector - Returns a vector of specified type with all bits set.
5109 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5110 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5111 /// Then bitcast to their original type, ensuring they get CSE'd.
5112 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5114 assert(VT.isVector() && "Expected a vector type");
5116 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5118 if (VT.is256BitVector()) {
5119 if (HasInt256) { // AVX2
5120 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5123 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5126 } else if (VT.is128BitVector()) {
5127 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5129 llvm_unreachable("Unexpected vector type");
5131 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5134 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5135 /// that point to V2 points to its first element.
5136 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5137 for (unsigned i = 0; i != NumElems; ++i) {
5138 if (Mask[i] > (int)NumElems) {
5144 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5145 /// operation of specified width.
5146 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5148 unsigned NumElems = VT.getVectorNumElements();
5149 SmallVector<int, 8> Mask;
5150 Mask.push_back(NumElems);
5151 for (unsigned i = 1; i != NumElems; ++i)
5153 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5156 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5157 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5159 unsigned NumElems = VT.getVectorNumElements();
5160 SmallVector<int, 8> Mask;
5161 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5163 Mask.push_back(i + NumElems);
5165 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5168 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5169 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5171 unsigned NumElems = VT.getVectorNumElements();
5172 SmallVector<int, 8> Mask;
5173 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5174 Mask.push_back(i + Half);
5175 Mask.push_back(i + NumElems + Half);
5177 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5180 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5181 // a generic shuffle instruction because the target has no such instructions.
5182 // Generate shuffles which repeat i16 and i8 several times until they can be
5183 // represented by v4f32 and then be manipulated by target suported shuffles.
5184 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5185 MVT VT = V.getSimpleValueType();
5186 int NumElems = VT.getVectorNumElements();
5189 while (NumElems > 4) {
5190 if (EltNo < NumElems/2) {
5191 V = getUnpackl(DAG, dl, VT, V, V);
5193 V = getUnpackh(DAG, dl, VT, V, V);
5194 EltNo -= NumElems/2;
5201 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5202 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5203 MVT VT = V.getSimpleValueType();
5206 if (VT.is128BitVector()) {
5207 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5208 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5209 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5211 } else if (VT.is256BitVector()) {
5212 // To use VPERMILPS to splat scalars, the second half of indicies must
5213 // refer to the higher part, which is a duplication of the lower one,
5214 // because VPERMILPS can only handle in-lane permutations.
5215 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5216 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5218 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5219 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5222 llvm_unreachable("Vector size not supported");
5224 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5227 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5228 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5229 MVT SrcVT = SV->getSimpleValueType(0);
5230 SDValue V1 = SV->getOperand(0);
5233 int EltNo = SV->getSplatIndex();
5234 int NumElems = SrcVT.getVectorNumElements();
5235 bool Is256BitVec = SrcVT.is256BitVector();
5237 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5238 "Unknown how to promote splat for type");
5240 // Extract the 128-bit part containing the splat element and update
5241 // the splat element index when it refers to the higher register.
5243 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5244 if (EltNo >= NumElems/2)
5245 EltNo -= NumElems/2;
5248 // All i16 and i8 vector types can't be used directly by a generic shuffle
5249 // instruction because the target has no such instruction. Generate shuffles
5250 // which repeat i16 and i8 several times until they fit in i32, and then can
5251 // be manipulated by target suported shuffles.
5252 MVT EltVT = SrcVT.getVectorElementType();
5253 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5254 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5256 // Recreate the 256-bit vector and place the same 128-bit vector
5257 // into the low and high part. This is necessary because we want
5258 // to use VPERM* to shuffle the vectors
5260 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5263 return getLegalSplat(DAG, V1, EltNo);
5266 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5267 /// vector of zero or undef vector. This produces a shuffle where the low
5268 /// element of V2 is swizzled into the zero/undef vector, landing at element
5269 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5270 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5272 const X86Subtarget *Subtarget,
5273 SelectionDAG &DAG) {
5274 MVT VT = V2.getSimpleValueType();
5276 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5277 unsigned NumElems = VT.getVectorNumElements();
5278 SmallVector<int, 16> MaskVec;
5279 for (unsigned i = 0; i != NumElems; ++i)
5280 // If this is the insertion idx, put the low elt of V2 here.
5281 MaskVec.push_back(i == Idx ? NumElems : i);
5282 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5285 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5286 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5287 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5288 /// shuffles which use a single input multiple times, and in those cases it will
5289 /// adjust the mask to only have indices within that single input.
5290 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5291 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5292 unsigned NumElems = VT.getVectorNumElements();
5296 bool IsFakeUnary = false;
5297 switch(N->getOpcode()) {
5298 case X86ISD::BLENDI:
5299 ImmN = N->getOperand(N->getNumOperands()-1);
5300 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5303 ImmN = N->getOperand(N->getNumOperands()-1);
5304 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5305 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5307 case X86ISD::UNPCKH:
5308 DecodeUNPCKHMask(VT, Mask);
5309 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5311 case X86ISD::UNPCKL:
5312 DecodeUNPCKLMask(VT, Mask);
5313 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5315 case X86ISD::MOVHLPS:
5316 DecodeMOVHLPSMask(NumElems, Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::MOVLHPS:
5320 DecodeMOVLHPSMask(NumElems, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::PALIGNR:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFD:
5328 case X86ISD::VPERMILPI:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFHW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFLW:
5339 ImmN = N->getOperand(N->getNumOperands()-1);
5340 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5343 case X86ISD::PSHUFB: {
5345 SDValue MaskNode = N->getOperand(1);
5346 while (MaskNode->getOpcode() == ISD::BITCAST)
5347 MaskNode = MaskNode->getOperand(0);
5349 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5350 // If we have a build-vector, then things are easy.
5351 EVT VT = MaskNode.getValueType();
5352 assert(VT.isVector() &&
5353 "Can't produce a non-vector with a build_vector!");
5354 if (!VT.isInteger())
5357 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5359 SmallVector<uint64_t, 32> RawMask;
5360 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5361 SDValue Op = MaskNode->getOperand(i);
5362 if (Op->getOpcode() == ISD::UNDEF) {
5363 RawMask.push_back((uint64_t)SM_SentinelUndef);
5366 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5369 APInt MaskElement = CN->getAPIntValue();
5371 // We now have to decode the element which could be any integer size and
5372 // extract each byte of it.
5373 for (int j = 0; j < NumBytesPerElement; ++j) {
5374 // Note that this is x86 and so always little endian: the low byte is
5375 // the first byte of the mask.
5376 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5377 MaskElement = MaskElement.lshr(8);
5380 DecodePSHUFBMask(RawMask, Mask);
5384 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5388 SDValue Ptr = MaskLoad->getBasePtr();
5389 if (Ptr->getOpcode() == X86ISD::Wrapper)
5390 Ptr = Ptr->getOperand(0);
5392 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5393 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5396 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5397 // FIXME: Support AVX-512 here.
5398 Type *Ty = C->getType();
5399 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5400 Ty->getVectorNumElements() != 32))
5403 DecodePSHUFBMask(C, Mask);
5409 case X86ISD::VPERMI:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5415 case X86ISD::MOVSD: {
5416 // The index 0 always comes from the first element of the second source,
5417 // this is why MOVSS and MOVSD are used in the first place. The other
5418 // elements come from the other positions of the first source vector
5419 Mask.push_back(NumElems);
5420 for (unsigned i = 1; i != NumElems; ++i) {
5425 case X86ISD::VPERM2X128:
5426 ImmN = N->getOperand(N->getNumOperands()-1);
5427 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5428 if (Mask.empty()) return false;
5430 case X86ISD::MOVSLDUP:
5431 DecodeMOVSLDUPMask(VT, Mask);
5433 case X86ISD::MOVSHDUP:
5434 DecodeMOVSHDUPMask(VT, Mask);
5436 case X86ISD::MOVDDUP:
5437 case X86ISD::MOVLHPD:
5438 case X86ISD::MOVLPD:
5439 case X86ISD::MOVLPS:
5440 // Not yet implemented
5442 default: llvm_unreachable("unknown target shuffle node");
5445 // If we have a fake unary shuffle, the shuffle mask is spread across two
5446 // inputs that are actually the same node. Re-map the mask to always point
5447 // into the first input.
5450 if (M >= (int)Mask.size())
5456 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5457 /// element of the result of the vector shuffle.
5458 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5461 return SDValue(); // Limit search depth.
5463 SDValue V = SDValue(N, 0);
5464 EVT VT = V.getValueType();
5465 unsigned Opcode = V.getOpcode();
5467 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5468 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5469 int Elt = SV->getMaskElt(Index);
5472 return DAG.getUNDEF(VT.getVectorElementType());
5474 unsigned NumElems = VT.getVectorNumElements();
5475 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5476 : SV->getOperand(1);
5477 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5480 // Recurse into target specific vector shuffles to find scalars.
5481 if (isTargetShuffle(Opcode)) {
5482 MVT ShufVT = V.getSimpleValueType();
5483 unsigned NumElems = ShufVT.getVectorNumElements();
5484 SmallVector<int, 16> ShuffleMask;
5487 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5490 int Elt = ShuffleMask[Index];
5492 return DAG.getUNDEF(ShufVT.getVectorElementType());
5494 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5496 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5500 // Actual nodes that may contain scalar elements
5501 if (Opcode == ISD::BITCAST) {
5502 V = V.getOperand(0);
5503 EVT SrcVT = V.getValueType();
5504 unsigned NumElems = VT.getVectorNumElements();
5506 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5510 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5511 return (Index == 0) ? V.getOperand(0)
5512 : DAG.getUNDEF(VT.getVectorElementType());
5514 if (V.getOpcode() == ISD::BUILD_VECTOR)
5515 return V.getOperand(Index);
5520 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5521 /// shuffle operation which come from a consecutively from a zero. The
5522 /// search can start in two different directions, from left or right.
5523 /// We count undefs as zeros until PreferredNum is reached.
5524 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5525 unsigned NumElems, bool ZerosFromLeft,
5527 unsigned PreferredNum = -1U) {
5528 unsigned NumZeros = 0;
5529 for (unsigned i = 0; i != NumElems; ++i) {
5530 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5531 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5535 if (X86::isZeroNode(Elt))
5537 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5538 NumZeros = std::min(NumZeros + 1, PreferredNum);
5546 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5547 /// correspond consecutively to elements from one of the vector operands,
5548 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5550 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5551 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5552 unsigned NumElems, unsigned &OpNum) {
5553 bool SeenV1 = false;
5554 bool SeenV2 = false;
5556 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5557 int Idx = SVOp->getMaskElt(i);
5558 // Ignore undef indicies
5562 if (Idx < (int)NumElems)
5567 // Only accept consecutive elements from the same vector
5568 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5572 OpNum = SeenV1 ? 0 : 1;
5576 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5577 /// logical left shift of a vector.
5578 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5579 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5581 SVOp->getSimpleValueType(0).getVectorNumElements();
5582 unsigned NumZeros = getNumOfConsecutiveZeros(
5583 SVOp, NumElems, false /* check zeros from right */, DAG,
5584 SVOp->getMaskElt(0));
5590 // Considering the elements in the mask that are not consecutive zeros,
5591 // check if they consecutively come from only one of the source vectors.
5593 // V1 = {X, A, B, C} 0
5595 // vector_shuffle V1, V2 <1, 2, 3, X>
5597 if (!isShuffleMaskConsecutive(SVOp,
5598 0, // Mask Start Index
5599 NumElems-NumZeros, // Mask End Index(exclusive)
5600 NumZeros, // Where to start looking in the src vector
5601 NumElems, // Number of elements in vector
5602 OpSrc)) // Which source operand ?
5607 ShVal = SVOp->getOperand(OpSrc);
5611 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5612 /// logical left shift of a vector.
5613 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5614 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5616 SVOp->getSimpleValueType(0).getVectorNumElements();
5617 unsigned NumZeros = getNumOfConsecutiveZeros(
5618 SVOp, NumElems, true /* check zeros from left */, DAG,
5619 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5625 // Considering the elements in the mask that are not consecutive zeros,
5626 // check if they consecutively come from only one of the source vectors.
5628 // 0 { A, B, X, X } = V2
5630 // vector_shuffle V1, V2 <X, X, 4, 5>
5632 if (!isShuffleMaskConsecutive(SVOp,
5633 NumZeros, // Mask Start Index
5634 NumElems, // Mask End Index(exclusive)
5635 0, // Where to start looking in the src vector
5636 NumElems, // Number of elements in vector
5637 OpSrc)) // Which source operand ?
5642 ShVal = SVOp->getOperand(OpSrc);
5646 /// isVectorShift - Returns true if the shuffle can be implemented as a
5647 /// logical left or right shift of a vector.
5648 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5649 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5650 // Although the logic below support any bitwidth size, there are no
5651 // shift instructions which handle more than 128-bit vectors.
5652 if (!SVOp->getSimpleValueType(0).is128BitVector())
5655 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5656 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5662 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5664 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5665 unsigned NumNonZero, unsigned NumZero,
5667 const X86Subtarget* Subtarget,
5668 const TargetLowering &TLI) {
5675 for (unsigned i = 0; i < 16; ++i) {
5676 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5677 if (ThisIsNonZero && First) {
5679 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5681 V = DAG.getUNDEF(MVT::v8i16);
5686 SDValue ThisElt, LastElt;
5687 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5688 if (LastIsNonZero) {
5689 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5690 MVT::i16, Op.getOperand(i-1));
5692 if (ThisIsNonZero) {
5693 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5694 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5695 ThisElt, DAG.getConstant(8, MVT::i8));
5697 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5701 if (ThisElt.getNode())
5702 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5703 DAG.getIntPtrConstant(i/2));
5707 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5710 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5712 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5713 unsigned NumNonZero, unsigned NumZero,
5715 const X86Subtarget* Subtarget,
5716 const TargetLowering &TLI) {
5723 for (unsigned i = 0; i < 8; ++i) {
5724 bool isNonZero = (NonZeros & (1 << i)) != 0;
5728 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5730 V = DAG.getUNDEF(MVT::v8i16);
5733 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5734 MVT::v8i16, V, Op.getOperand(i),
5735 DAG.getIntPtrConstant(i));
5742 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5743 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5744 const X86Subtarget *Subtarget,
5745 const TargetLowering &TLI) {
5746 // Find all zeroable elements.
5748 for (int i=0; i < 4; ++i) {
5749 SDValue Elt = Op->getOperand(i);
5750 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5752 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5753 [](bool M) { return !M; }) > 1 &&
5754 "We expect at least two non-zero elements!");
5756 // We only know how to deal with build_vector nodes where elements are either
5757 // zeroable or extract_vector_elt with constant index.
5758 SDValue FirstNonZero;
5759 for (int i=0; i < 4; ++i) {
5762 SDValue Elt = Op->getOperand(i);
5763 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5764 !isa<ConstantSDNode>(Elt.getOperand(1)))
5766 // Make sure that this node is extracting from a 128-bit vector.
5767 MVT VT = Elt.getOperand(0).getSimpleValueType();
5768 if (!VT.is128BitVector())
5770 if (!FirstNonZero.getNode())
5774 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5775 SDValue V1 = FirstNonZero.getOperand(0);
5776 MVT VT = V1.getSimpleValueType();
5778 // See if this build_vector can be lowered as a blend with zero.
5780 unsigned EltMaskIdx, EltIdx;
5782 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5783 if (Zeroable[EltIdx]) {
5784 // The zero vector will be on the right hand side.
5785 Mask[EltIdx] = EltIdx+4;
5789 Elt = Op->getOperand(EltIdx);
5790 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5791 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5792 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5794 Mask[EltIdx] = EltIdx;
5798 // Let the shuffle legalizer deal with blend operations.
5799 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5800 if (V1.getSimpleValueType() != VT)
5801 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5802 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5805 // See if we can lower this build_vector to a INSERTPS.
5806 if (!Subtarget->hasSSE41())
5809 SDValue V2 = Elt.getOperand(0);
5810 if (Elt == FirstNonZero)
5813 bool CanFold = true;
5814 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5818 SDValue Current = Op->getOperand(i);
5819 SDValue SrcVector = Current->getOperand(0);
5822 CanFold = SrcVector == V1 &&
5823 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5829 assert(V1.getNode() && "Expected at least two non-zero elements!");
5830 if (V1.getSimpleValueType() != MVT::v4f32)
5831 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5832 if (V2.getSimpleValueType() != MVT::v4f32)
5833 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5835 // Ok, we can emit an INSERTPS instruction.
5837 for (int i = 0; i < 4; ++i)
5841 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5842 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5843 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5844 DAG.getIntPtrConstant(InsertPSMask));
5845 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5848 /// getVShift - Return a vector logical shift node.
5850 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5851 unsigned NumBits, SelectionDAG &DAG,
5852 const TargetLowering &TLI, SDLoc dl) {
5853 assert(VT.is128BitVector() && "Unknown type for VShift");
5854 EVT ShVT = MVT::v2i64;
5855 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5856 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5857 return DAG.getNode(ISD::BITCAST, dl, VT,
5858 DAG.getNode(Opc, dl, ShVT, SrcOp,
5859 DAG.getConstant(NumBits,
5860 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5864 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5866 // Check if the scalar load can be widened into a vector load. And if
5867 // the address is "base + cst" see if the cst can be "absorbed" into
5868 // the shuffle mask.
5869 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5870 SDValue Ptr = LD->getBasePtr();
5871 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5873 EVT PVT = LD->getValueType(0);
5874 if (PVT != MVT::i32 && PVT != MVT::f32)
5879 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5880 FI = FINode->getIndex();
5882 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5883 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5884 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5885 Offset = Ptr.getConstantOperandVal(1);
5886 Ptr = Ptr.getOperand(0);
5891 // FIXME: 256-bit vector instructions don't require a strict alignment,
5892 // improve this code to support it better.
5893 unsigned RequiredAlign = VT.getSizeInBits()/8;
5894 SDValue Chain = LD->getChain();
5895 // Make sure the stack object alignment is at least 16 or 32.
5896 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5897 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5898 if (MFI->isFixedObjectIndex(FI)) {
5899 // Can't change the alignment. FIXME: It's possible to compute
5900 // the exact stack offset and reference FI + adjust offset instead.
5901 // If someone *really* cares about this. That's the way to implement it.
5904 MFI->setObjectAlignment(FI, RequiredAlign);
5908 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5909 // Ptr + (Offset & ~15).
5912 if ((Offset % RequiredAlign) & 3)
5914 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5916 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5917 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5919 int EltNo = (Offset - StartOffset) >> 2;
5920 unsigned NumElems = VT.getVectorNumElements();
5922 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5923 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5924 LD->getPointerInfo().getWithOffset(StartOffset),
5925 false, false, false, 0);
5927 SmallVector<int, 8> Mask;
5928 for (unsigned i = 0; i != NumElems; ++i)
5929 Mask.push_back(EltNo);
5931 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5937 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5938 /// vector of type 'VT', see if the elements can be replaced by a single large
5939 /// load which has the same value as a build_vector whose operands are 'elts'.
5941 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5943 /// FIXME: we'd also like to handle the case where the last elements are zero
5944 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5945 /// There's even a handy isZeroNode for that purpose.
5946 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5947 SDLoc &DL, SelectionDAG &DAG,
5948 bool isAfterLegalize) {
5949 EVT EltVT = VT.getVectorElementType();
5950 unsigned NumElems = Elts.size();
5952 LoadSDNode *LDBase = nullptr;
5953 unsigned LastLoadedElt = -1U;
5955 // For each element in the initializer, see if we've found a load or an undef.
5956 // If we don't find an initial load element, or later load elements are
5957 // non-consecutive, bail out.
5958 for (unsigned i = 0; i < NumElems; ++i) {
5959 SDValue Elt = Elts[i];
5961 if (!Elt.getNode() ||
5962 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5965 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5967 LDBase = cast<LoadSDNode>(Elt.getNode());
5971 if (Elt.getOpcode() == ISD::UNDEF)
5974 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5975 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5980 // If we have found an entire vector of loads and undefs, then return a large
5981 // load of the entire vector width starting at the base pointer. If we found
5982 // consecutive loads for the low half, generate a vzext_load node.
5983 if (LastLoadedElt == NumElems - 1) {
5985 if (isAfterLegalize &&
5986 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5989 SDValue NewLd = SDValue();
5991 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5992 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5993 LDBase->getPointerInfo(),
5994 LDBase->isVolatile(), LDBase->isNonTemporal(),
5995 LDBase->isInvariant(), 0);
5996 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5997 LDBase->getPointerInfo(),
5998 LDBase->isVolatile(), LDBase->isNonTemporal(),
5999 LDBase->isInvariant(), LDBase->getAlignment());
6001 if (LDBase->hasAnyUseOfValue(1)) {
6002 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6004 SDValue(NewLd.getNode(), 1));
6005 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6006 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6007 SDValue(NewLd.getNode(), 1));
6012 if (NumElems == 4 && LastLoadedElt == 1 &&
6013 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6014 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6015 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6017 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6018 LDBase->getPointerInfo(),
6019 LDBase->getAlignment(),
6020 false/*isVolatile*/, true/*ReadMem*/,
6023 // Make sure the newly-created LOAD is in the same position as LDBase in
6024 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6025 // update uses of LDBase's output chain to use the TokenFactor.
6026 if (LDBase->hasAnyUseOfValue(1)) {
6027 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6028 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6029 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6030 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6031 SDValue(ResNode.getNode(), 1));
6034 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6039 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6040 /// to generate a splat value for the following cases:
6041 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6042 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6043 /// a scalar load, or a constant.
6044 /// The VBROADCAST node is returned when a pattern is found,
6045 /// or SDValue() otherwise.
6046 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6047 SelectionDAG &DAG) {
6048 // VBROADCAST requires AVX.
6049 // TODO: Splats could be generated for non-AVX CPUs using SSE
6050 // instructions, but there's less potential gain for only 128-bit vectors.
6051 if (!Subtarget->hasAVX())
6054 MVT VT = Op.getSimpleValueType();
6057 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6058 "Unsupported vector type for broadcast.");
6063 switch (Op.getOpcode()) {
6065 // Unknown pattern found.
6068 case ISD::BUILD_VECTOR: {
6069 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6070 BitVector UndefElements;
6071 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6073 // We need a splat of a single value to use broadcast, and it doesn't
6074 // make any sense if the value is only in one element of the vector.
6075 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6079 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6080 Ld.getOpcode() == ISD::ConstantFP);
6082 // Make sure that all of the users of a non-constant load are from the
6083 // BUILD_VECTOR node.
6084 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6089 case ISD::VECTOR_SHUFFLE: {
6090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6092 // Shuffles must have a splat mask where the first element is
6094 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6097 SDValue Sc = Op.getOperand(0);
6098 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6099 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6101 if (!Subtarget->hasInt256())
6104 // Use the register form of the broadcast instruction available on AVX2.
6105 if (VT.getSizeInBits() >= 256)
6106 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6107 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6110 Ld = Sc.getOperand(0);
6111 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6112 Ld.getOpcode() == ISD::ConstantFP);
6114 // The scalar_to_vector node and the suspected
6115 // load node must have exactly one user.
6116 // Constants may have multiple users.
6118 // AVX-512 has register version of the broadcast
6119 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6120 Ld.getValueType().getSizeInBits() >= 32;
6121 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6128 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6129 bool IsGE256 = (VT.getSizeInBits() >= 256);
6131 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6132 // instruction to save 8 or more bytes of constant pool data.
6133 // TODO: If multiple splats are generated to load the same constant,
6134 // it may be detrimental to overall size. There needs to be a way to detect
6135 // that condition to know if this is truly a size win.
6136 const Function *F = DAG.getMachineFunction().getFunction();
6137 bool OptForSize = F->getAttributes().
6138 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6140 // Handle broadcasting a single constant scalar from the constant pool
6142 // On Sandybridge (no AVX2), it is still better to load a constant vector
6143 // from the constant pool and not to broadcast it from a scalar.
6144 // But override that restriction when optimizing for size.
6145 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6146 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6147 EVT CVT = Ld.getValueType();
6148 assert(!CVT.isVector() && "Must not broadcast a vector type");
6150 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6151 // For size optimization, also splat v2f64 and v2i64, and for size opt
6152 // with AVX2, also splat i8 and i16.
6153 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6154 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6155 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6156 const Constant *C = nullptr;
6157 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6158 C = CI->getConstantIntValue();
6159 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6160 C = CF->getConstantFPValue();
6162 assert(C && "Invalid constant type");
6164 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6165 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6166 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6167 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6168 MachinePointerInfo::getConstantPool(),
6169 false, false, false, Alignment);
6171 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6175 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6177 // Handle AVX2 in-register broadcasts.
6178 if (!IsLoad && Subtarget->hasInt256() &&
6179 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6180 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6182 // The scalar source must be a normal load.
6186 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6187 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6189 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6190 // double since there is no vbroadcastsd xmm
6191 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6192 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6193 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6196 // Unsupported broadcast.
6200 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6201 /// underlying vector and index.
6203 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6205 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6207 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6208 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6211 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6213 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6215 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6216 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6219 // In this case the vector is the extract_subvector expression and the index
6220 // is 2, as specified by the shuffle.
6221 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6222 SDValue ShuffleVec = SVOp->getOperand(0);
6223 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6224 assert(ShuffleVecVT.getVectorElementType() ==
6225 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6227 int ShuffleIdx = SVOp->getMaskElt(Idx);
6228 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6229 ExtractedFromVec = ShuffleVec;
6235 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6236 MVT VT = Op.getSimpleValueType();
6238 // Skip if insert_vec_elt is not supported.
6239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6240 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6244 unsigned NumElems = Op.getNumOperands();
6248 SmallVector<unsigned, 4> InsertIndices;
6249 SmallVector<int, 8> Mask(NumElems, -1);
6251 for (unsigned i = 0; i != NumElems; ++i) {
6252 unsigned Opc = Op.getOperand(i).getOpcode();
6254 if (Opc == ISD::UNDEF)
6257 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6258 // Quit if more than 1 elements need inserting.
6259 if (InsertIndices.size() > 1)
6262 InsertIndices.push_back(i);
6266 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6267 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6268 // Quit if non-constant index.
6269 if (!isa<ConstantSDNode>(ExtIdx))
6271 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6273 // Quit if extracted from vector of different type.
6274 if (ExtractedFromVec.getValueType() != VT)
6277 if (!VecIn1.getNode())
6278 VecIn1 = ExtractedFromVec;
6279 else if (VecIn1 != ExtractedFromVec) {
6280 if (!VecIn2.getNode())
6281 VecIn2 = ExtractedFromVec;
6282 else if (VecIn2 != ExtractedFromVec)
6283 // Quit if more than 2 vectors to shuffle
6287 if (ExtractedFromVec == VecIn1)
6289 else if (ExtractedFromVec == VecIn2)
6290 Mask[i] = Idx + NumElems;
6293 if (!VecIn1.getNode())
6296 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6297 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6298 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6299 unsigned Idx = InsertIndices[i];
6300 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6301 DAG.getIntPtrConstant(Idx));
6307 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6309 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6311 MVT VT = Op.getSimpleValueType();
6312 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6313 "Unexpected type in LowerBUILD_VECTORvXi1!");
6316 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6317 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6318 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6319 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6322 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6323 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6324 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6325 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6328 bool AllContants = true;
6329 uint64_t Immediate = 0;
6330 int NonConstIdx = -1;
6331 bool IsSplat = true;
6332 unsigned NumNonConsts = 0;
6333 unsigned NumConsts = 0;
6334 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6335 SDValue In = Op.getOperand(idx);
6336 if (In.getOpcode() == ISD::UNDEF)
6338 if (!isa<ConstantSDNode>(In)) {
6339 AllContants = false;
6345 if (cast<ConstantSDNode>(In)->getZExtValue())
6346 Immediate |= (1ULL << idx);
6348 if (In != Op.getOperand(0))
6353 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6354 DAG.getConstant(Immediate, MVT::i16));
6355 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6356 DAG.getIntPtrConstant(0));
6359 if (NumNonConsts == 1 && NonConstIdx != 0) {
6362 SDValue VecAsImm = DAG.getConstant(Immediate,
6363 MVT::getIntegerVT(VT.getSizeInBits()));
6364 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6367 DstVec = DAG.getUNDEF(VT);
6368 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6369 Op.getOperand(NonConstIdx),
6370 DAG.getIntPtrConstant(NonConstIdx));
6372 if (!IsSplat && (NonConstIdx != 0))
6373 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6374 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6377 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6378 DAG.getConstant(-1, SelectVT),
6379 DAG.getConstant(0, SelectVT));
6381 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6382 DAG.getConstant((Immediate | 1), SelectVT),
6383 DAG.getConstant(Immediate, SelectVT));
6384 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6387 /// \brief Return true if \p N implements a horizontal binop and return the
6388 /// operands for the horizontal binop into V0 and V1.
6390 /// This is a helper function of PerformBUILD_VECTORCombine.
6391 /// This function checks that the build_vector \p N in input implements a
6392 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6393 /// operation to match.
6394 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6395 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6396 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6399 /// This function only analyzes elements of \p N whose indices are
6400 /// in range [BaseIdx, LastIdx).
6401 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6403 unsigned BaseIdx, unsigned LastIdx,
6404 SDValue &V0, SDValue &V1) {
6405 EVT VT = N->getValueType(0);
6407 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6408 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6409 "Invalid Vector in input!");
6411 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6412 bool CanFold = true;
6413 unsigned ExpectedVExtractIdx = BaseIdx;
6414 unsigned NumElts = LastIdx - BaseIdx;
6415 V0 = DAG.getUNDEF(VT);
6416 V1 = DAG.getUNDEF(VT);
6418 // Check if N implements a horizontal binop.
6419 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6420 SDValue Op = N->getOperand(i + BaseIdx);
6423 if (Op->getOpcode() == ISD::UNDEF) {
6424 // Update the expected vector extract index.
6425 if (i * 2 == NumElts)
6426 ExpectedVExtractIdx = BaseIdx;
6427 ExpectedVExtractIdx += 2;
6431 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6436 SDValue Op0 = Op.getOperand(0);
6437 SDValue Op1 = Op.getOperand(1);
6439 // Try to match the following pattern:
6440 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6441 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6442 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6443 Op0.getOperand(0) == Op1.getOperand(0) &&
6444 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6445 isa<ConstantSDNode>(Op1.getOperand(1)));
6449 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6450 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6452 if (i * 2 < NumElts) {
6453 if (V0.getOpcode() == ISD::UNDEF)
6454 V0 = Op0.getOperand(0);
6456 if (V1.getOpcode() == ISD::UNDEF)
6457 V1 = Op0.getOperand(0);
6458 if (i * 2 == NumElts)
6459 ExpectedVExtractIdx = BaseIdx;
6462 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6463 if (I0 == ExpectedVExtractIdx)
6464 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6465 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6466 // Try to match the following dag sequence:
6467 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6468 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6472 ExpectedVExtractIdx += 2;
6478 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6479 /// a concat_vector.
6481 /// This is a helper function of PerformBUILD_VECTORCombine.
6482 /// This function expects two 256-bit vectors called V0 and V1.
6483 /// At first, each vector is split into two separate 128-bit vectors.
6484 /// Then, the resulting 128-bit vectors are used to implement two
6485 /// horizontal binary operations.
6487 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6489 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6490 /// the two new horizontal binop.
6491 /// When Mode is set, the first horizontal binop dag node would take as input
6492 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6493 /// horizontal binop dag node would take as input the lower 128-bit of V1
6494 /// and the upper 128-bit of V1.
6496 /// HADD V0_LO, V0_HI
6497 /// HADD V1_LO, V1_HI
6499 /// Otherwise, the first horizontal binop dag node takes as input the lower
6500 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6501 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6503 /// HADD V0_LO, V1_LO
6504 /// HADD V0_HI, V1_HI
6506 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6507 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6508 /// the upper 128-bits of the result.
6509 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6510 SDLoc DL, SelectionDAG &DAG,
6511 unsigned X86Opcode, bool Mode,
6512 bool isUndefLO, bool isUndefHI) {
6513 EVT VT = V0.getValueType();
6514 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6515 "Invalid nodes in input!");
6517 unsigned NumElts = VT.getVectorNumElements();
6518 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6519 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6520 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6521 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6522 EVT NewVT = V0_LO.getValueType();
6524 SDValue LO = DAG.getUNDEF(NewVT);
6525 SDValue HI = DAG.getUNDEF(NewVT);
6528 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6529 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6530 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6531 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6532 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6534 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6535 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6536 V1_LO->getOpcode() != ISD::UNDEF))
6537 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6539 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6540 V1_HI->getOpcode() != ISD::UNDEF))
6541 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6544 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6547 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6548 /// sequence of 'vadd + vsub + blendi'.
6549 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6550 const X86Subtarget *Subtarget) {
6552 EVT VT = BV->getValueType(0);
6553 unsigned NumElts = VT.getVectorNumElements();
6554 SDValue InVec0 = DAG.getUNDEF(VT);
6555 SDValue InVec1 = DAG.getUNDEF(VT);
6557 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6558 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6560 // Odd-numbered elements in the input build vector are obtained from
6561 // adding two integer/float elements.
6562 // Even-numbered elements in the input build vector are obtained from
6563 // subtracting two integer/float elements.
6564 unsigned ExpectedOpcode = ISD::FSUB;
6565 unsigned NextExpectedOpcode = ISD::FADD;
6566 bool AddFound = false;
6567 bool SubFound = false;
6569 for (unsigned i = 0, e = NumElts; i != e; i++) {
6570 SDValue Op = BV->getOperand(i);
6572 // Skip 'undef' values.
6573 unsigned Opcode = Op.getOpcode();
6574 if (Opcode == ISD::UNDEF) {
6575 std::swap(ExpectedOpcode, NextExpectedOpcode);
6579 // Early exit if we found an unexpected opcode.
6580 if (Opcode != ExpectedOpcode)
6583 SDValue Op0 = Op.getOperand(0);
6584 SDValue Op1 = Op.getOperand(1);
6586 // Try to match the following pattern:
6587 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6588 // Early exit if we cannot match that sequence.
6589 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6590 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6591 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6592 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6593 Op0.getOperand(1) != Op1.getOperand(1))
6596 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6600 // We found a valid add/sub node. Update the information accordingly.
6606 // Update InVec0 and InVec1.
6607 if (InVec0.getOpcode() == ISD::UNDEF)
6608 InVec0 = Op0.getOperand(0);
6609 if (InVec1.getOpcode() == ISD::UNDEF)
6610 InVec1 = Op1.getOperand(0);
6612 // Make sure that operands in input to each add/sub node always
6613 // come from a same pair of vectors.
6614 if (InVec0 != Op0.getOperand(0)) {
6615 if (ExpectedOpcode == ISD::FSUB)
6618 // FADD is commutable. Try to commute the operands
6619 // and then test again.
6620 std::swap(Op0, Op1);
6621 if (InVec0 != Op0.getOperand(0))
6625 if (InVec1 != Op1.getOperand(0))
6628 // Update the pair of expected opcodes.
6629 std::swap(ExpectedOpcode, NextExpectedOpcode);
6632 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6633 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6634 InVec1.getOpcode() != ISD::UNDEF)
6635 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6640 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6641 const X86Subtarget *Subtarget) {
6643 EVT VT = N->getValueType(0);
6644 unsigned NumElts = VT.getVectorNumElements();
6645 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6646 SDValue InVec0, InVec1;
6648 // Try to match an ADDSUB.
6649 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6650 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6651 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6652 if (Value.getNode())
6656 // Try to match horizontal ADD/SUB.
6657 unsigned NumUndefsLO = 0;
6658 unsigned NumUndefsHI = 0;
6659 unsigned Half = NumElts/2;
6661 // Count the number of UNDEF operands in the build_vector in input.
6662 for (unsigned i = 0, e = Half; i != e; ++i)
6663 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6666 for (unsigned i = Half, e = NumElts; i != e; ++i)
6667 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6670 // Early exit if this is either a build_vector of all UNDEFs or all the
6671 // operands but one are UNDEF.
6672 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6675 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6676 // Try to match an SSE3 float HADD/HSUB.
6677 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6678 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6680 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6681 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6682 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6683 // Try to match an SSSE3 integer HADD/HSUB.
6684 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6685 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6687 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6688 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6691 if (!Subtarget->hasAVX())
6694 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6695 // Try to match an AVX horizontal add/sub of packed single/double
6696 // precision floating point values from 256-bit vectors.
6697 SDValue InVec2, InVec3;
6698 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6699 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6700 ((InVec0.getOpcode() == ISD::UNDEF ||
6701 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6702 ((InVec1.getOpcode() == ISD::UNDEF ||
6703 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6704 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6706 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6707 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6708 ((InVec0.getOpcode() == ISD::UNDEF ||
6709 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6710 ((InVec1.getOpcode() == ISD::UNDEF ||
6711 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6712 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6713 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6714 // Try to match an AVX2 horizontal add/sub of signed integers.
6715 SDValue InVec2, InVec3;
6717 bool CanFold = true;
6719 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6720 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6721 ((InVec0.getOpcode() == ISD::UNDEF ||
6722 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6723 ((InVec1.getOpcode() == ISD::UNDEF ||
6724 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6725 X86Opcode = X86ISD::HADD;
6726 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6727 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6728 ((InVec0.getOpcode() == ISD::UNDEF ||
6729 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6730 ((InVec1.getOpcode() == ISD::UNDEF ||
6731 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6732 X86Opcode = X86ISD::HSUB;
6737 // Fold this build_vector into a single horizontal add/sub.
6738 // Do this only if the target has AVX2.
6739 if (Subtarget->hasAVX2())
6740 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6742 // Do not try to expand this build_vector into a pair of horizontal
6743 // add/sub if we can emit a pair of scalar add/sub.
6744 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6747 // Convert this build_vector into a pair of horizontal binop followed by
6749 bool isUndefLO = NumUndefsLO == Half;
6750 bool isUndefHI = NumUndefsHI == Half;
6751 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6752 isUndefLO, isUndefHI);
6756 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6757 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6759 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6760 X86Opcode = X86ISD::HADD;
6761 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6762 X86Opcode = X86ISD::HSUB;
6763 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6764 X86Opcode = X86ISD::FHADD;
6765 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6766 X86Opcode = X86ISD::FHSUB;
6770 // Don't try to expand this build_vector into a pair of horizontal add/sub
6771 // if we can simply emit a pair of scalar add/sub.
6772 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6775 // Convert this build_vector into two horizontal add/sub followed by
6777 bool isUndefLO = NumUndefsLO == Half;
6778 bool isUndefHI = NumUndefsHI == Half;
6779 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6780 isUndefLO, isUndefHI);
6787 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6790 MVT VT = Op.getSimpleValueType();
6791 MVT ExtVT = VT.getVectorElementType();
6792 unsigned NumElems = Op.getNumOperands();
6794 // Generate vectors for predicate vectors.
6795 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6796 return LowerBUILD_VECTORvXi1(Op, DAG);
6798 // Vectors containing all zeros can be matched by pxor and xorps later
6799 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6800 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6801 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6802 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6805 return getZeroVector(VT, Subtarget, DAG, dl);
6808 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6809 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6810 // vpcmpeqd on 256-bit vectors.
6811 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6812 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6815 if (!VT.is512BitVector())
6816 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6819 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6820 if (Broadcast.getNode())
6823 unsigned EVTBits = ExtVT.getSizeInBits();
6825 unsigned NumZero = 0;
6826 unsigned NumNonZero = 0;
6827 unsigned NonZeros = 0;
6828 bool IsAllConstants = true;
6829 SmallSet<SDValue, 8> Values;
6830 for (unsigned i = 0; i < NumElems; ++i) {
6831 SDValue Elt = Op.getOperand(i);
6832 if (Elt.getOpcode() == ISD::UNDEF)
6835 if (Elt.getOpcode() != ISD::Constant &&
6836 Elt.getOpcode() != ISD::ConstantFP)
6837 IsAllConstants = false;
6838 if (X86::isZeroNode(Elt))
6841 NonZeros |= (1 << i);
6846 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6847 if (NumNonZero == 0)
6848 return DAG.getUNDEF(VT);
6850 // Special case for single non-zero, non-undef, element.
6851 if (NumNonZero == 1) {
6852 unsigned Idx = countTrailingZeros(NonZeros);
6853 SDValue Item = Op.getOperand(Idx);
6855 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6856 // the value are obviously zero, truncate the value to i32 and do the
6857 // insertion that way. Only do this if the value is non-constant or if the
6858 // value is a constant being inserted into element 0. It is cheaper to do
6859 // a constant pool load than it is to do a movd + shuffle.
6860 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6861 (!IsAllConstants || Idx == 0)) {
6862 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6864 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6865 EVT VecVT = MVT::v4i32;
6866 unsigned VecElts = 4;
6868 // Truncate the value (which may itself be a constant) to i32, and
6869 // convert it to a vector with movd (S2V+shuffle to zero extend).
6870 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6871 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6873 // If using the new shuffle lowering, just directly insert this.
6874 if (ExperimentalVectorShuffleLowering)
6876 ISD::BITCAST, dl, VT,
6877 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6879 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6881 // Now we have our 32-bit value zero extended in the low element of
6882 // a vector. If Idx != 0, swizzle it into place.
6884 SmallVector<int, 4> Mask;
6885 Mask.push_back(Idx);
6886 for (unsigned i = 1; i != VecElts; ++i)
6888 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6891 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6895 // If we have a constant or non-constant insertion into the low element of
6896 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6897 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6898 // depending on what the source datatype is.
6901 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6903 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6904 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6905 if (VT.is256BitVector() || VT.is512BitVector()) {
6906 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6907 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6908 Item, DAG.getIntPtrConstant(0));
6910 assert(VT.is128BitVector() && "Expected an SSE value type!");
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6912 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6913 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6916 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6917 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6918 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6919 if (VT.is256BitVector()) {
6920 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6921 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6923 assert(VT.is128BitVector() && "Expected an SSE value type!");
6924 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6926 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6930 // Is it a vector logical left shift?
6931 if (NumElems == 2 && Idx == 1 &&
6932 X86::isZeroNode(Op.getOperand(0)) &&
6933 !X86::isZeroNode(Op.getOperand(1))) {
6934 unsigned NumBits = VT.getSizeInBits();
6935 return getVShift(true, VT,
6936 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6937 VT, Op.getOperand(1)),
6938 NumBits/2, DAG, *this, dl);
6941 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6944 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6945 // is a non-constant being inserted into an element other than the low one,
6946 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6947 // movd/movss) to move this into the low element, then shuffle it into
6949 if (EVTBits == 32) {
6950 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6952 // If using the new shuffle lowering, just directly insert this.
6953 if (ExperimentalVectorShuffleLowering)
6954 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6956 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6957 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6958 SmallVector<int, 8> MaskVec;
6959 for (unsigned i = 0; i != NumElems; ++i)
6960 MaskVec.push_back(i == Idx ? 0 : 1);
6961 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6965 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6966 if (Values.size() == 1) {
6967 if (EVTBits == 32) {
6968 // Instead of a shuffle like this:
6969 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6970 // Check if it's possible to issue this instead.
6971 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue Item = Op.getOperand(Idx);
6974 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6975 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6980 // A vector full of immediates; various special cases are already
6981 // handled, so this is best done with a single constant-pool load.
6985 // For AVX-length vectors, build the individual 128-bit pieces and use
6986 // shuffles to put them in place.
6987 if (VT.is256BitVector() || VT.is512BitVector()) {
6988 SmallVector<SDValue, 64> V;
6989 for (unsigned i = 0; i != NumElems; ++i)
6990 V.push_back(Op.getOperand(i));
6992 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6994 // Build both the lower and upper subvector.
6995 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6996 makeArrayRef(&V[0], NumElems/2));
6997 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6998 makeArrayRef(&V[NumElems / 2], NumElems/2));
7000 // Recreate the wider vector with the lower and upper part.
7001 if (VT.is256BitVector())
7002 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7003 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7006 // Let legalizer expand 2-wide build_vectors.
7007 if (EVTBits == 64) {
7008 if (NumNonZero == 1) {
7009 // One half is zero or undef.
7010 unsigned Idx = countTrailingZeros(NonZeros);
7011 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7012 Op.getOperand(Idx));
7013 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7018 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7019 if (EVTBits == 8 && NumElems == 16) {
7020 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7022 if (V.getNode()) return V;
7025 if (EVTBits == 16 && NumElems == 8) {
7026 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7028 if (V.getNode()) return V;
7031 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7032 if (EVTBits == 32 && NumElems == 4) {
7033 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7038 // If element VT is == 32 bits, turn it into a number of shuffles.
7039 SmallVector<SDValue, 8> V(NumElems);
7040 if (NumElems == 4 && NumZero > 0) {
7041 for (unsigned i = 0; i < 4; ++i) {
7042 bool isZero = !(NonZeros & (1 << i));
7044 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7046 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7049 for (unsigned i = 0; i < 2; ++i) {
7050 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7053 V[i] = V[i*2]; // Must be a zero vector.
7056 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7059 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7062 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7067 bool Reverse1 = (NonZeros & 0x3) == 2;
7068 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7072 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7073 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7075 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7078 if (Values.size() > 1 && VT.is128BitVector()) {
7079 // Check for a build vector of consecutive loads.
7080 for (unsigned i = 0; i < NumElems; ++i)
7081 V[i] = Op.getOperand(i);
7083 // Check for elements which are consecutive loads.
7084 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7088 // Check for a build vector from mostly shuffle plus few inserting.
7089 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7093 // For SSE 4.1, use insertps to put the high elements into the low element.
7094 if (getSubtarget()->hasSSE41()) {
7096 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7097 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7099 Result = DAG.getUNDEF(VT);
7101 for (unsigned i = 1; i < NumElems; ++i) {
7102 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7103 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7104 Op.getOperand(i), DAG.getIntPtrConstant(i));
7109 // Otherwise, expand into a number of unpckl*, start by extending each of
7110 // our (non-undef) elements to the full vector width with the element in the
7111 // bottom slot of the vector (which generates no code for SSE).
7112 for (unsigned i = 0; i < NumElems; ++i) {
7113 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7114 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7116 V[i] = DAG.getUNDEF(VT);
7119 // Next, we iteratively mix elements, e.g. for v4f32:
7120 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7121 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7122 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7123 unsigned EltStride = NumElems >> 1;
7124 while (EltStride != 0) {
7125 for (unsigned i = 0; i < EltStride; ++i) {
7126 // If V[i+EltStride] is undef and this is the first round of mixing,
7127 // then it is safe to just drop this shuffle: V[i] is already in the
7128 // right place, the one element (since it's the first round) being
7129 // inserted as undef can be dropped. This isn't safe for successive
7130 // rounds because they will permute elements within both vectors.
7131 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7132 EltStride == NumElems/2)
7135 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7144 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7145 // to create 256-bit vectors from two other 128-bit ones.
7146 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7148 MVT ResVT = Op.getSimpleValueType();
7150 assert((ResVT.is256BitVector() ||
7151 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7153 SDValue V1 = Op.getOperand(0);
7154 SDValue V2 = Op.getOperand(1);
7155 unsigned NumElems = ResVT.getVectorNumElements();
7156 if(ResVT.is256BitVector())
7157 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7159 if (Op.getNumOperands() == 4) {
7160 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7161 ResVT.getVectorNumElements()/2);
7162 SDValue V3 = Op.getOperand(2);
7163 SDValue V4 = Op.getOperand(3);
7164 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7165 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7167 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7170 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7171 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7172 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7173 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7174 Op.getNumOperands() == 4)));
7176 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7177 // from two other 128-bit ones.
7179 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7180 return LowerAVXCONCAT_VECTORS(Op, DAG);
7184 //===----------------------------------------------------------------------===//
7185 // Vector shuffle lowering
7187 // This is an experimental code path for lowering vector shuffles on x86. It is
7188 // designed to handle arbitrary vector shuffles and blends, gracefully
7189 // degrading performance as necessary. It works hard to recognize idiomatic
7190 // shuffles and lower them to optimal instruction patterns without leaving
7191 // a framework that allows reasonably efficient handling of all vector shuffle
7193 //===----------------------------------------------------------------------===//
7195 /// \brief Tiny helper function to identify a no-op mask.
7197 /// This is a somewhat boring predicate function. It checks whether the mask
7198 /// array input, which is assumed to be a single-input shuffle mask of the kind
7199 /// used by the X86 shuffle instructions (not a fully general
7200 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7201 /// in-place shuffle are 'no-op's.
7202 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7203 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7204 if (Mask[i] != -1 && Mask[i] != i)
7209 /// \brief Helper function to classify a mask as a single-input mask.
7211 /// This isn't a generic single-input test because in the vector shuffle
7212 /// lowering we canonicalize single inputs to be the first input operand. This
7213 /// means we can more quickly test for a single input by only checking whether
7214 /// an input from the second operand exists. We also assume that the size of
7215 /// mask corresponds to the size of the input vectors which isn't true in the
7216 /// fully general case.
7217 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7219 if (M >= (int)Mask.size())
7224 /// \brief Test whether there are elements crossing 128-bit lanes in this
7227 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7228 /// and we routinely test for these.
7229 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7230 int LaneSize = 128 / VT.getScalarSizeInBits();
7231 int Size = Mask.size();
7232 for (int i = 0; i < Size; ++i)
7233 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7238 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7240 /// This checks a shuffle mask to see if it is performing the same
7241 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7242 /// that it is also not lane-crossing. It may however involve a blend from the
7243 /// same lane of a second vector.
7245 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7246 /// non-trivial to compute in the face of undef lanes. The representation is
7247 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7248 /// entries from both V1 and V2 inputs to the wider mask.
7250 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7251 SmallVectorImpl<int> &RepeatedMask) {
7252 int LaneSize = 128 / VT.getScalarSizeInBits();
7253 RepeatedMask.resize(LaneSize, -1);
7254 int Size = Mask.size();
7255 for (int i = 0; i < Size; ++i) {
7258 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7259 // This entry crosses lanes, so there is no way to model this shuffle.
7262 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7263 if (RepeatedMask[i % LaneSize] == -1)
7264 // This is the first non-undef entry in this slot of a 128-bit lane.
7265 RepeatedMask[i % LaneSize] =
7266 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7267 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7268 // Found a mismatch with the repeated mask.
7274 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7275 // 2013 will allow us to use it as a non-type template parameter.
7278 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7280 /// See its documentation for details.
7281 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7282 if (Mask.size() != Args.size())
7284 for (int i = 0, e = Mask.size(); i < e; ++i) {
7285 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7286 if (Mask[i] != -1 && Mask[i] != *Args[i])
7294 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7297 /// This is a fast way to test a shuffle mask against a fixed pattern:
7299 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7301 /// It returns true if the mask is exactly as wide as the argument list, and
7302 /// each element of the mask is either -1 (signifying undef) or the value given
7303 /// in the argument.
7304 static const VariadicFunction1<
7305 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7307 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7309 /// This helper function produces an 8-bit shuffle immediate corresponding to
7310 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7311 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7314 /// NB: We rely heavily on "undef" masks preserving the input lane.
7315 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7316 SelectionDAG &DAG) {
7317 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7318 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7319 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7320 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7321 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7324 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7325 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7326 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7327 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7328 return DAG.getConstant(Imm, MVT::i8);
7331 /// \brief Try to emit a blend instruction for a shuffle.
7333 /// This doesn't do any checks for the availability of instructions for blending
7334 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7335 /// be matched in the backend with the type given. What it does check for is
7336 /// that the shuffle mask is in fact a blend.
7337 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7338 SDValue V2, ArrayRef<int> Mask,
7339 const X86Subtarget *Subtarget,
7340 SelectionDAG &DAG) {
7342 unsigned BlendMask = 0;
7343 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7344 if (Mask[i] >= Size) {
7345 if (Mask[i] != i + Size)
7346 return SDValue(); // Shuffled V2 input!
7347 BlendMask |= 1u << i;
7350 if (Mask[i] >= 0 && Mask[i] != i)
7351 return SDValue(); // Shuffled V1 input!
7353 switch (VT.SimpleTy) {
7358 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7359 DAG.getConstant(BlendMask, MVT::i8));
7363 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7368 // that instruction.
7369 if (Subtarget->hasAVX2()) {
7370 // Scale the blend by the number of 32-bit dwords per element.
7371 int Scale = VT.getScalarSizeInBits() / 32;
7373 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7374 if (Mask[i] >= Size)
7375 for (int j = 0; j < Scale; ++j)
7376 BlendMask |= 1u << (i * Scale + j);
7378 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7379 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7380 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7381 return DAG.getNode(ISD::BITCAST, DL, VT,
7382 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7383 DAG.getConstant(BlendMask, MVT::i8)));
7387 // For integer shuffles we need to expand the mask and cast the inputs to
7388 // v8i16s prior to blending.
7389 int Scale = 8 / VT.getVectorNumElements();
7391 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7392 if (Mask[i] >= Size)
7393 for (int j = 0; j < Scale; ++j)
7394 BlendMask |= 1u << (i * Scale + j);
7396 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7397 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7398 return DAG.getNode(ISD::BITCAST, DL, VT,
7399 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7400 DAG.getConstant(BlendMask, MVT::i8)));
7404 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7405 SmallVector<int, 8> RepeatedMask;
7406 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7407 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7408 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7410 for (int i = 0; i < 8; ++i)
7411 if (RepeatedMask[i] >= 16)
7412 BlendMask |= 1u << i;
7413 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7414 DAG.getConstant(BlendMask, MVT::i8));
7419 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7420 // Scale the blend by the number of bytes per element.
7421 int Scale = VT.getScalarSizeInBits() / 8;
7422 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7424 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7425 // mix of LLVM's code generator and the x86 backend. We tell the code
7426 // generator that boolean values in the elements of an x86 vector register
7427 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7428 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7429 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7430 // of the element (the remaining are ignored) and 0 in that high bit would
7431 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7432 // the LLVM model for boolean values in vector elements gets the relevant
7433 // bit set, it is set backwards and over constrained relative to x86's
7435 SDValue VSELECTMask[32];
7436 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7437 for (int j = 0; j < Scale; ++j)
7438 VSELECTMask[Scale * i + j] =
7439 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7440 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7442 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7443 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7445 ISD::BITCAST, DL, VT,
7446 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7447 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7452 llvm_unreachable("Not a supported integer vector type!");
7456 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7457 /// unblended shuffles followed by an unshuffled blend.
7459 /// This matches the extremely common pattern for handling combined
7460 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7462 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7466 SelectionDAG &DAG) {
7467 // Shuffle the input elements into the desired positions in V1 and V2 and
7468 // blend them together.
7469 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7470 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7471 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7472 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7473 if (Mask[i] >= 0 && Mask[i] < Size) {
7474 V1Mask[i] = Mask[i];
7476 } else if (Mask[i] >= Size) {
7477 V2Mask[i] = Mask[i] - Size;
7478 BlendMask[i] = i + Size;
7481 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7482 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7483 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7486 /// \brief Try to lower a vector shuffle as a byte rotation.
7488 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7489 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7490 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7491 /// try to generically lower a vector shuffle through such an pattern. It
7492 /// does not check for the profitability of lowering either as PALIGNR or
7493 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7494 /// This matches shuffle vectors that look like:
7496 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7498 /// Essentially it concatenates V1 and V2, shifts right by some number of
7499 /// elements, and takes the low elements as the result. Note that while this is
7500 /// specified as a *right shift* because x86 is little-endian, it is a *left
7501 /// rotate* of the vector lanes.
7503 /// Note that this only handles 128-bit vector widths currently.
7504 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7507 const X86Subtarget *Subtarget,
7508 SelectionDAG &DAG) {
7509 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7511 // We need to detect various ways of spelling a rotation:
7512 // [11, 12, 13, 14, 15, 0, 1, 2]
7513 // [-1, 12, 13, 14, -1, -1, 1, -1]
7514 // [-1, -1, -1, -1, -1, -1, 1, 2]
7515 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7516 // [-1, 4, 5, 6, -1, -1, 9, -1]
7517 // [-1, 4, 5, 6, -1, -1, -1, -1]
7520 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7523 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7525 // Based on the mod-Size value of this mask element determine where
7526 // a rotated vector would have started.
7527 int StartIdx = i - (Mask[i] % Size);
7529 // The identity rotation isn't interesting, stop.
7532 // If we found the tail of a vector the rotation must be the missing
7533 // front. If we found the head of a vector, it must be how much of the head.
7534 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7537 Rotation = CandidateRotation;
7538 else if (Rotation != CandidateRotation)
7539 // The rotations don't match, so we can't match this mask.
7542 // Compute which value this mask is pointing at.
7543 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7545 // Compute which of the two target values this index should be assigned to.
7546 // This reflects whether the high elements are remaining or the low elements
7548 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7550 // Either set up this value if we've not encountered it before, or check
7551 // that it remains consistent.
7554 else if (TargetV != MaskV)
7555 // This may be a rotation, but it pulls from the inputs in some
7556 // unsupported interleaving.
7560 // Check that we successfully analyzed the mask, and normalize the results.
7561 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7562 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7568 assert(VT.getSizeInBits() == 128 &&
7569 "Rotate-based lowering only supports 128-bit lowering!");
7570 assert(Mask.size() <= 16 &&
7571 "Can shuffle at most 16 bytes in a 128-bit vector!");
7573 // The actual rotate instruction rotates bytes, so we need to scale the
7574 // rotation based on how many bytes are in the vector.
7575 int Scale = 16 / Mask.size();
7577 // SSSE3 targets can use the palignr instruction
7578 if (Subtarget->hasSSSE3()) {
7579 // Cast the inputs to v16i8 to match PALIGNR.
7580 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7581 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7583 return DAG.getNode(ISD::BITCAST, DL, VT,
7584 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7585 DAG.getConstant(Rotation * Scale, MVT::i8)));
7588 // Default SSE2 implementation
7589 int LoByteShift = 16 - Rotation * Scale;
7590 int HiByteShift = Rotation * Scale;
7592 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7593 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7594 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7596 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7597 DAG.getConstant(8 * LoByteShift, MVT::i8));
7598 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7599 DAG.getConstant(8 * HiByteShift, MVT::i8));
7600 return DAG.getNode(ISD::BITCAST, DL, VT,
7601 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7604 /// \brief Compute whether each element of a shuffle is zeroable.
7606 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7607 /// Either it is an undef element in the shuffle mask, the element of the input
7608 /// referenced is undef, or the element of the input referenced is known to be
7609 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7610 /// as many lanes with this technique as possible to simplify the remaining
7612 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7613 SDValue V1, SDValue V2) {
7614 SmallBitVector Zeroable(Mask.size(), false);
7616 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7617 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7619 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7621 // Handle the easy cases.
7622 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7627 // If this is an index into a build_vector node, dig out the input value and
7629 SDValue V = M < Size ? V1 : V2;
7630 if (V.getOpcode() != ISD::BUILD_VECTOR)
7633 SDValue Input = V.getOperand(M % Size);
7634 // The UNDEF opcode check really should be dead code here, but not quite
7635 // worth asserting on (it isn't invalid, just unexpected).
7636 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7643 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7645 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7646 /// byte-shift instructions. The mask must consist of a shifted sequential
7647 /// shuffle from one of the input vectors and zeroable elements for the
7648 /// remaining 'shifted in' elements.
7650 /// Note that this only handles 128-bit vector widths currently.
7651 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7652 SDValue V2, ArrayRef<int> Mask,
7653 SelectionDAG &DAG) {
7654 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7656 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7658 int Size = Mask.size();
7659 int Scale = 16 / Size;
7661 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7662 ArrayRef<int> Mask) {
7663 for (int i = StartIndex; i < EndIndex; i++) {
7666 if (i + Base != Mask[i] - MaskOffset)
7672 for (int Shift = 1; Shift < Size; Shift++) {
7673 int ByteShift = Shift * Scale;
7675 // PSRLDQ : (little-endian) right byte shift
7676 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7677 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7678 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7679 bool ZeroableRight = true;
7680 for (int i = Size - Shift; i < Size; i++) {
7681 ZeroableRight &= Zeroable[i];
7684 if (ZeroableRight) {
7685 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7686 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7688 if (ValidShiftRight1 || ValidShiftRight2) {
7689 // Cast the inputs to v2i64 to match PSRLDQ.
7690 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7691 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7692 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7693 DAG.getConstant(ByteShift * 8, MVT::i8));
7694 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7698 // PSLLDQ : (little-endian) left byte shift
7699 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7700 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7701 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7702 bool ZeroableLeft = true;
7703 for (int i = 0; i < Shift; i++) {
7704 ZeroableLeft &= Zeroable[i];
7708 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7709 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7711 if (ValidShiftLeft1 || ValidShiftLeft2) {
7712 // Cast the inputs to v2i64 to match PSLLDQ.
7713 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7714 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7715 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7716 DAG.getConstant(ByteShift * 8, MVT::i8));
7717 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7725 /// \brief Lower a vector shuffle as a zero or any extension.
7727 /// Given a specific number of elements, element bit width, and extension
7728 /// stride, produce either a zero or any extension based on the available
7729 /// features of the subtarget.
7730 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7731 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7732 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7733 assert(Scale > 1 && "Need a scale to extend.");
7734 int EltBits = VT.getSizeInBits() / NumElements;
7735 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7736 "Only 8, 16, and 32 bit elements can be extended.");
7737 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7739 // Found a valid zext mask! Try various lowering strategies based on the
7740 // input type and available ISA extensions.
7741 if (Subtarget->hasSSE41()) {
7742 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7743 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7744 NumElements / Scale);
7745 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7746 return DAG.getNode(ISD::BITCAST, DL, VT,
7747 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7750 // For any extends we can cheat for larger element sizes and use shuffle
7751 // instructions that can fold with a load and/or copy.
7752 if (AnyExt && EltBits == 32) {
7753 int PSHUFDMask[4] = {0, -1, 1, -1};
7755 ISD::BITCAST, DL, VT,
7756 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7757 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7758 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7760 if (AnyExt && EltBits == 16 && Scale > 2) {
7761 int PSHUFDMask[4] = {0, -1, 0, -1};
7762 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7763 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7764 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7765 int PSHUFHWMask[4] = {1, -1, -1, -1};
7767 ISD::BITCAST, DL, VT,
7768 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7769 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7770 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7773 // If this would require more than 2 unpack instructions to expand, use
7774 // pshufb when available. We can only use more than 2 unpack instructions
7775 // when zero extending i8 elements which also makes it easier to use pshufb.
7776 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7777 assert(NumElements == 16 && "Unexpected byte vector width!");
7778 SDValue PSHUFBMask[16];
7779 for (int i = 0; i < 16; ++i)
7781 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7782 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7783 return DAG.getNode(ISD::BITCAST, DL, VT,
7784 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7785 DAG.getNode(ISD::BUILD_VECTOR, DL,
7786 MVT::v16i8, PSHUFBMask)));
7789 // Otherwise emit a sequence of unpacks.
7791 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7792 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7793 : getZeroVector(InputVT, Subtarget, DAG, DL);
7794 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7795 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7799 } while (Scale > 1);
7800 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7803 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7805 /// This routine will try to do everything in its power to cleverly lower
7806 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7807 /// check for the profitability of this lowering, it tries to aggressively
7808 /// match this pattern. It will use all of the micro-architectural details it
7809 /// can to emit an efficient lowering. It handles both blends with all-zero
7810 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7811 /// masking out later).
7813 /// The reason we have dedicated lowering for zext-style shuffles is that they
7814 /// are both incredibly common and often quite performance sensitive.
7815 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7816 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7817 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7818 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7820 int Bits = VT.getSizeInBits();
7821 int NumElements = Mask.size();
7823 // Define a helper function to check a particular ext-scale and lower to it if
7825 auto Lower = [&](int Scale) -> SDValue {
7828 for (int i = 0; i < NumElements; ++i) {
7830 continue; // Valid anywhere but doesn't tell us anything.
7831 if (i % Scale != 0) {
7832 // Each of the extend elements needs to be zeroable.
7836 // We no lorger are in the anyext case.
7841 // Each of the base elements needs to be consecutive indices into the
7842 // same input vector.
7843 SDValue V = Mask[i] < NumElements ? V1 : V2;
7846 else if (InputV != V)
7847 return SDValue(); // Flip-flopping inputs.
7849 if (Mask[i] % NumElements != i / Scale)
7850 return SDValue(); // Non-consecutive strided elemenst.
7853 // If we fail to find an input, we have a zero-shuffle which should always
7854 // have already been handled.
7855 // FIXME: Maybe handle this here in case during blending we end up with one?
7859 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7860 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7863 // The widest scale possible for extending is to a 64-bit integer.
7864 assert(Bits % 64 == 0 &&
7865 "The number of bits in a vector must be divisible by 64 on x86!");
7866 int NumExtElements = Bits / 64;
7868 // Each iteration, try extending the elements half as much, but into twice as
7870 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7871 assert(NumElements % NumExtElements == 0 &&
7872 "The input vector size must be divisble by the extended size.");
7873 if (SDValue V = Lower(NumElements / NumExtElements))
7877 // No viable ext lowering found.
7881 /// \brief Try to get a scalar value for a specific element of a vector.
7883 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7884 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7885 SelectionDAG &DAG) {
7886 MVT VT = V.getSimpleValueType();
7887 MVT EltVT = VT.getVectorElementType();
7888 while (V.getOpcode() == ISD::BITCAST)
7889 V = V.getOperand(0);
7890 // If the bitcasts shift the element size, we can't extract an equivalent
7892 MVT NewVT = V.getSimpleValueType();
7893 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7896 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7897 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7898 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7903 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7905 /// This is particularly important because the set of instructions varies
7906 /// significantly based on whether the operand is a load or not.
7907 static bool isShuffleFoldableLoad(SDValue V) {
7908 while (V.getOpcode() == ISD::BITCAST)
7909 V = V.getOperand(0);
7911 return ISD::isNON_EXTLoad(V.getNode());
7914 /// \brief Try to lower insertion of a single element into a zero vector.
7916 /// This is a common pattern that we have especially efficient patterns to lower
7917 /// across all subtarget feature sets.
7918 static SDValue lowerVectorShuffleAsElementInsertion(
7919 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7920 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7921 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7923 MVT EltVT = VT.getVectorElementType();
7925 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7926 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7928 bool IsV1Zeroable = true;
7929 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7930 if (i != V2Index && !Zeroable[i]) {
7931 IsV1Zeroable = false;
7935 // Check for a single input from a SCALAR_TO_VECTOR node.
7936 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7937 // all the smarts here sunk into that routine. However, the current
7938 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7939 // vector shuffle lowering is dead.
7940 if (SDValue V2S = getScalarValueForVectorElement(
7941 V2, Mask[V2Index] - Mask.size(), DAG)) {
7942 // We need to zext the scalar if it is smaller than an i32.
7943 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7944 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7945 // Using zext to expand a narrow element won't work for non-zero
7950 // Zero-extend directly to i32.
7952 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7954 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7955 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7956 EltVT == MVT::i16) {
7957 // Either not inserting from the low element of the input or the input
7958 // element size is too small to use VZEXT_MOVL to clear the high bits.
7962 if (!IsV1Zeroable) {
7963 // If V1 can't be treated as a zero vector we have fewer options to lower
7964 // this. We can't support integer vectors or non-zero targets cheaply, and
7965 // the V1 elements can't be permuted in any way.
7966 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7967 if (!VT.isFloatingPoint() || V2Index != 0)
7969 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7970 V1Mask[V2Index] = -1;
7971 if (!isNoopShuffleMask(V1Mask))
7973 // This is essentially a special case blend operation, but if we have
7974 // general purpose blend operations, they are always faster. Bail and let
7975 // the rest of the lowering handle these as blends.
7976 if (Subtarget->hasSSE41())
7979 // Otherwise, use MOVSD or MOVSS.
7980 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7981 "Only two types of floating point element types to handle!");
7982 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7986 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7988 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7991 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7992 // the desired position. Otherwise it is more efficient to do a vector
7993 // shift left. We know that we can do a vector shift left because all
7994 // the inputs are zero.
7995 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7996 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7997 V2Shuffle[V2Index] = 0;
7998 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8000 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8002 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8004 V2Index * EltVT.getSizeInBits(),
8005 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8006 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8012 /// \brief Try to lower broadcast of a single element.
8014 /// For convenience, this code also bundles all of the subtarget feature set
8015 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8016 /// a convenient way to factor it out.
8017 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8019 const X86Subtarget *Subtarget,
8020 SelectionDAG &DAG) {
8021 if (!Subtarget->hasAVX())
8023 if (VT.isInteger() && !Subtarget->hasAVX2())
8026 // Check that the mask is a broadcast.
8027 int BroadcastIdx = -1;
8029 if (M >= 0 && BroadcastIdx == -1)
8031 else if (M >= 0 && M != BroadcastIdx)
8034 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8035 "a sorted mask where the broadcast "
8038 // Go up the chain of (vector) values to try and find a scalar load that
8039 // we can combine with the broadcast.
8041 switch (V.getOpcode()) {
8042 case ISD::CONCAT_VECTORS: {
8043 int OperandSize = Mask.size() / V.getNumOperands();
8044 V = V.getOperand(BroadcastIdx / OperandSize);
8045 BroadcastIdx %= OperandSize;
8049 case ISD::INSERT_SUBVECTOR: {
8050 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8051 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8055 int BeginIdx = (int)ConstantIdx->getZExtValue();
8057 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8058 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8059 BroadcastIdx -= BeginIdx;
8070 // Check if this is a broadcast of a scalar. We special case lowering
8071 // for scalars so that we can more effectively fold with loads.
8072 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8073 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8074 V = V.getOperand(BroadcastIdx);
8076 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8078 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8080 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8081 // We can't broadcast from a vector register w/o AVX2, and we can only
8082 // broadcast from the zero-element of a vector register.
8086 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8089 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8091 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8092 /// support for floating point shuffles but not integer shuffles. These
8093 /// instructions will incur a domain crossing penalty on some chips though so
8094 /// it is better to avoid lowering through this for integer vectors where
8096 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8097 const X86Subtarget *Subtarget,
8098 SelectionDAG &DAG) {
8100 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8101 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8102 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8103 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8104 ArrayRef<int> Mask = SVOp->getMask();
8105 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8107 if (isSingleInputShuffleMask(Mask)) {
8108 // Straight shuffle of a single input vector. Simulate this by using the
8109 // single input as both of the "inputs" to this instruction..
8110 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8112 if (Subtarget->hasAVX()) {
8113 // If we have AVX, we can use VPERMILPS which will allow folding a load
8114 // into the shuffle.
8115 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8116 DAG.getConstant(SHUFPDMask, MVT::i8));
8119 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8120 DAG.getConstant(SHUFPDMask, MVT::i8));
8122 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8123 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8125 // Use dedicated unpack instructions for masks that match their pattern.
8126 if (isShuffleEquivalent(Mask, 0, 2))
8127 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8128 if (isShuffleEquivalent(Mask, 1, 3))
8129 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8131 // If we have a single input, insert that into V1 if we can do so cheaply.
8132 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8133 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8134 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8136 // Try inverting the insertion since for v2 masks it is easy to do and we
8137 // can't reliably sort the mask one way or the other.
8138 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8139 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8140 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8141 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8145 // Try to use one of the special instruction patterns to handle two common
8146 // blend patterns if a zero-blend above didn't work.
8147 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8148 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8149 // We can either use a special instruction to load over the low double or
8150 // to move just the low double.
8152 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8154 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8156 if (Subtarget->hasSSE41())
8157 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8161 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8162 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8163 DAG.getConstant(SHUFPDMask, MVT::i8));
8166 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8168 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8169 /// the integer unit to minimize domain crossing penalties. However, for blends
8170 /// it falls back to the floating point shuffle operation with appropriate bit
8172 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8173 const X86Subtarget *Subtarget,
8174 SelectionDAG &DAG) {
8176 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8177 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8178 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8179 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8180 ArrayRef<int> Mask = SVOp->getMask();
8181 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8183 if (isSingleInputShuffleMask(Mask)) {
8184 // Check for being able to broadcast a single element.
8185 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8186 Mask, Subtarget, DAG))
8189 // Straight shuffle of a single input vector. For everything from SSE2
8190 // onward this has a single fast instruction with no scary immediates.
8191 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8192 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8193 int WidenedMask[4] = {
8194 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8195 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8197 ISD::BITCAST, DL, MVT::v2i64,
8198 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8199 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8202 // If we have a single input from V2 insert that into V1 if we can do so
8204 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8205 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8206 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8208 // Try inverting the insertion since for v2 masks it is easy to do and we
8209 // can't reliably sort the mask one way or the other.
8210 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8211 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8212 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8213 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8217 // Use dedicated unpack instructions for masks that match their pattern.
8218 if (isShuffleEquivalent(Mask, 0, 2))
8219 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8220 if (isShuffleEquivalent(Mask, 1, 3))
8221 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8223 if (Subtarget->hasSSE41())
8224 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8228 // Try to use byte shift instructions.
8229 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8230 DL, MVT::v2i64, V1, V2, Mask, DAG))
8233 // Try to use byte rotation instructions.
8234 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8235 if (Subtarget->hasSSSE3())
8236 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8237 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8240 // We implement this with SHUFPD which is pretty lame because it will likely
8241 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8242 // However, all the alternatives are still more cycles and newer chips don't
8243 // have this problem. It would be really nice if x86 had better shuffles here.
8244 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8245 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8246 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8247 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8250 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8252 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8253 /// It makes no assumptions about whether this is the *best* lowering, it simply
8255 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8256 ArrayRef<int> Mask, SDValue V1,
8257 SDValue V2, SelectionDAG &DAG) {
8258 SDValue LowV = V1, HighV = V2;
8259 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8262 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8264 if (NumV2Elements == 1) {
8266 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8269 // Compute the index adjacent to V2Index and in the same half by toggling
8271 int V2AdjIndex = V2Index ^ 1;
8273 if (Mask[V2AdjIndex] == -1) {
8274 // Handles all the cases where we have a single V2 element and an undef.
8275 // This will only ever happen in the high lanes because we commute the
8276 // vector otherwise.
8278 std::swap(LowV, HighV);
8279 NewMask[V2Index] -= 4;
8281 // Handle the case where the V2 element ends up adjacent to a V1 element.
8282 // To make this work, blend them together as the first step.
8283 int V1Index = V2AdjIndex;
8284 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8285 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8286 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8288 // Now proceed to reconstruct the final blend as we have the necessary
8289 // high or low half formed.
8296 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8297 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8299 } else if (NumV2Elements == 2) {
8300 if (Mask[0] < 4 && Mask[1] < 4) {
8301 // Handle the easy case where we have V1 in the low lanes and V2 in the
8305 } else if (Mask[2] < 4 && Mask[3] < 4) {
8306 // We also handle the reversed case because this utility may get called
8307 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8308 // arrange things in the right direction.
8314 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8315 // trying to place elements directly, just blend them and set up the final
8316 // shuffle to place them.
8318 // The first two blend mask elements are for V1, the second two are for
8320 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8321 Mask[2] < 4 ? Mask[2] : Mask[3],
8322 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8323 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8324 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8325 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8327 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8330 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8331 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8332 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8333 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8336 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8337 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8340 /// \brief Lower 4-lane 32-bit floating point shuffles.
8342 /// Uses instructions exclusively from the floating point unit to minimize
8343 /// domain crossing penalties, as these are sufficient to implement all v4f32
8345 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8346 const X86Subtarget *Subtarget,
8347 SelectionDAG &DAG) {
8349 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8350 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8351 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8352 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8353 ArrayRef<int> Mask = SVOp->getMask();
8354 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8357 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8359 if (NumV2Elements == 0) {
8360 // Check for being able to broadcast a single element.
8361 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8362 Mask, Subtarget, DAG))
8365 if (Subtarget->hasAVX()) {
8366 // If we have AVX, we can use VPERMILPS which will allow folding a load
8367 // into the shuffle.
8368 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8369 getV4X86ShuffleImm8ForMask(Mask, DAG));
8372 // Otherwise, use a straight shuffle of a single input vector. We pass the
8373 // input vector to both operands to simulate this with a SHUFPS.
8374 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8375 getV4X86ShuffleImm8ForMask(Mask, DAG));
8378 // Use dedicated unpack instructions for masks that match their pattern.
8379 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8380 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8381 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8382 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8384 // There are special ways we can lower some single-element blends. However, we
8385 // have custom ways we can lower more complex single-element blends below that
8386 // we defer to if both this and BLENDPS fail to match, so restrict this to
8387 // when the V2 input is targeting element 0 of the mask -- that is the fast
8389 if (NumV2Elements == 1 && Mask[0] >= 4)
8390 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8391 Mask, Subtarget, DAG))
8394 if (Subtarget->hasSSE41())
8395 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8399 // Check for whether we can use INSERTPS to perform the blend. We only use
8400 // INSERTPS when the V1 elements are already in the correct locations
8401 // because otherwise we can just always use two SHUFPS instructions which
8402 // are much smaller to encode than a SHUFPS and an INSERTPS.
8403 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8405 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8408 // When using INSERTPS we can zero any lane of the destination. Collect
8409 // the zero inputs into a mask and drop them from the lanes of V1 which
8410 // actually need to be present as inputs to the INSERTPS.
8411 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8413 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8414 bool InsertNeedsShuffle = false;
8416 for (int i = 0; i < 4; ++i)
8420 } else if (Mask[i] != i) {
8421 InsertNeedsShuffle = true;
8426 // We don't want to use INSERTPS or other insertion techniques if it will
8427 // require shuffling anyways.
8428 if (!InsertNeedsShuffle) {
8429 // If all of V1 is zeroable, replace it with undef.
8430 if ((ZMask | 1 << V2Index) == 0xF)
8431 V1 = DAG.getUNDEF(MVT::v4f32);
8433 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8434 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8436 // Insert the V2 element into the desired position.
8437 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8438 DAG.getConstant(InsertPSMask, MVT::i8));
8442 // Otherwise fall back to a SHUFPS lowering strategy.
8443 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8446 /// \brief Lower 4-lane i32 vector shuffles.
8448 /// We try to handle these with integer-domain shuffles where we can, but for
8449 /// blends we use the floating point domain blend instructions.
8450 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8451 const X86Subtarget *Subtarget,
8452 SelectionDAG &DAG) {
8454 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8455 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8456 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8457 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8458 ArrayRef<int> Mask = SVOp->getMask();
8459 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8461 // Whenever we can lower this as a zext, that instruction is strictly faster
8462 // than any alternative. It also allows us to fold memory operands into the
8463 // shuffle in many cases.
8464 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8465 Mask, Subtarget, DAG))
8469 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8471 if (NumV2Elements == 0) {
8472 // Check for being able to broadcast a single element.
8473 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8474 Mask, Subtarget, DAG))
8477 // Straight shuffle of a single input vector. For everything from SSE2
8478 // onward this has a single fast instruction with no scary immediates.
8479 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8480 // but we aren't actually going to use the UNPCK instruction because doing
8481 // so prevents folding a load into this instruction or making a copy.
8482 const int UnpackLoMask[] = {0, 0, 1, 1};
8483 const int UnpackHiMask[] = {2, 2, 3, 3};
8484 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8485 Mask = UnpackLoMask;
8486 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8487 Mask = UnpackHiMask;
8489 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8490 getV4X86ShuffleImm8ForMask(Mask, DAG));
8493 // There are special ways we can lower some single-element blends.
8494 if (NumV2Elements == 1)
8495 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8496 Mask, Subtarget, DAG))
8499 // Use dedicated unpack instructions for masks that match their pattern.
8500 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8501 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8502 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8503 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8505 if (Subtarget->hasSSE41())
8506 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8510 // Try to use byte shift instructions.
8511 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8512 DL, MVT::v4i32, V1, V2, Mask, DAG))
8515 // Try to use byte rotation instructions.
8516 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8517 if (Subtarget->hasSSSE3())
8518 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8519 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8522 // We implement this with SHUFPS because it can blend from two vectors.
8523 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8524 // up the inputs, bypassing domain shift penalties that we would encur if we
8525 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8527 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8528 DAG.getVectorShuffle(
8530 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8531 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8534 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8535 /// shuffle lowering, and the most complex part.
8537 /// The lowering strategy is to try to form pairs of input lanes which are
8538 /// targeted at the same half of the final vector, and then use a dword shuffle
8539 /// to place them onto the right half, and finally unpack the paired lanes into
8540 /// their final position.
8542 /// The exact breakdown of how to form these dword pairs and align them on the
8543 /// correct sides is really tricky. See the comments within the function for
8544 /// more of the details.
8545 static SDValue lowerV8I16SingleInputVectorShuffle(
8546 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8547 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8548 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8549 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8550 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8552 SmallVector<int, 4> LoInputs;
8553 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8554 [](int M) { return M >= 0; });
8555 std::sort(LoInputs.begin(), LoInputs.end());
8556 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8557 SmallVector<int, 4> HiInputs;
8558 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8559 [](int M) { return M >= 0; });
8560 std::sort(HiInputs.begin(), HiInputs.end());
8561 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8563 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8564 int NumHToL = LoInputs.size() - NumLToL;
8566 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8567 int NumHToH = HiInputs.size() - NumLToH;
8568 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8569 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8570 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8571 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8573 // Check for being able to broadcast a single element.
8574 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8575 Mask, Subtarget, DAG))
8578 // Use dedicated unpack instructions for masks that match their pattern.
8579 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8580 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8581 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8582 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8584 // Try to use byte shift instructions.
8585 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8586 DL, MVT::v8i16, V, V, Mask, DAG))
8589 // Try to use byte rotation instructions.
8590 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8591 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8594 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8595 // such inputs we can swap two of the dwords across the half mark and end up
8596 // with <=2 inputs to each half in each half. Once there, we can fall through
8597 // to the generic code below. For example:
8599 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8600 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8602 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8603 // and an existing 2-into-2 on the other half. In this case we may have to
8604 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8605 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8606 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8607 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8608 // half than the one we target for fixing) will be fixed when we re-enter this
8609 // path. We will also combine away any sequence of PSHUFD instructions that
8610 // result into a single instruction. Here is an example of the tricky case:
8612 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8613 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8615 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8617 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8618 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8620 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8621 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8623 // The result is fine to be handled by the generic logic.
8624 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8625 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8626 int AOffset, int BOffset) {
8627 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8628 "Must call this with A having 3 or 1 inputs from the A half.");
8629 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8630 "Must call this with B having 1 or 3 inputs from the B half.");
8631 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8632 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8634 // Compute the index of dword with only one word among the three inputs in
8635 // a half by taking the sum of the half with three inputs and subtracting
8636 // the sum of the actual three inputs. The difference is the remaining
8639 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8640 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8641 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8642 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8643 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8644 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8645 int TripleNonInputIdx =
8646 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8647 TripleDWord = TripleNonInputIdx / 2;
8649 // We use xor with one to compute the adjacent DWord to whichever one the
8651 OneInputDWord = (OneInput / 2) ^ 1;
8653 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8654 // and BToA inputs. If there is also such a problem with the BToB and AToB
8655 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8656 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8657 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8658 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8659 // Compute how many inputs will be flipped by swapping these DWords. We
8661 // to balance this to ensure we don't form a 3-1 shuffle in the other
8663 int NumFlippedAToBInputs =
8664 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8665 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8666 int NumFlippedBToBInputs =
8667 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8668 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8669 if ((NumFlippedAToBInputs == 1 &&
8670 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8671 (NumFlippedBToBInputs == 1 &&
8672 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8673 // We choose whether to fix the A half or B half based on whether that
8674 // half has zero flipped inputs. At zero, we may not be able to fix it
8675 // with that half. We also bias towards fixing the B half because that
8676 // will more commonly be the high half, and we have to bias one way.
8677 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8678 ArrayRef<int> Inputs) {
8679 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8680 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8681 PinnedIdx ^ 1) != Inputs.end();
8682 // Determine whether the free index is in the flipped dword or the
8683 // unflipped dword based on where the pinned index is. We use this bit
8684 // in an xor to conditionally select the adjacent dword.
8685 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8686 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8687 FixFreeIdx) != Inputs.end();
8688 if (IsFixIdxInput == IsFixFreeIdxInput)
8690 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8691 FixFreeIdx) != Inputs.end();
8692 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8693 "We need to be changing the number of flipped inputs!");
8694 int PSHUFHalfMask[] = {0, 1, 2, 3};
8695 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8696 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8698 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8701 if (M != -1 && M == FixIdx)
8703 else if (M != -1 && M == FixFreeIdx)
8706 if (NumFlippedBToBInputs != 0) {
8708 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8709 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8711 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8713 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8714 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8719 int PSHUFDMask[] = {0, 1, 2, 3};
8720 PSHUFDMask[ADWord] = BDWord;
8721 PSHUFDMask[BDWord] = ADWord;
8722 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8723 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8724 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8725 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8727 // Adjust the mask to match the new locations of A and B.
8729 if (M != -1 && M/2 == ADWord)
8730 M = 2 * BDWord + M % 2;
8731 else if (M != -1 && M/2 == BDWord)
8732 M = 2 * ADWord + M % 2;
8734 // Recurse back into this routine to re-compute state now that this isn't
8735 // a 3 and 1 problem.
8736 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8739 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8740 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8741 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8742 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8744 // At this point there are at most two inputs to the low and high halves from
8745 // each half. That means the inputs can always be grouped into dwords and
8746 // those dwords can then be moved to the correct half with a dword shuffle.
8747 // We use at most one low and one high word shuffle to collect these paired
8748 // inputs into dwords, and finally a dword shuffle to place them.
8749 int PSHUFLMask[4] = {-1, -1, -1, -1};
8750 int PSHUFHMask[4] = {-1, -1, -1, -1};
8751 int PSHUFDMask[4] = {-1, -1, -1, -1};
8753 // First fix the masks for all the inputs that are staying in their
8754 // original halves. This will then dictate the targets of the cross-half
8756 auto fixInPlaceInputs =
8757 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8758 MutableArrayRef<int> SourceHalfMask,
8759 MutableArrayRef<int> HalfMask, int HalfOffset) {
8760 if (InPlaceInputs.empty())
8762 if (InPlaceInputs.size() == 1) {
8763 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8764 InPlaceInputs[0] - HalfOffset;
8765 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8768 if (IncomingInputs.empty()) {
8769 // Just fix all of the in place inputs.
8770 for (int Input : InPlaceInputs) {
8771 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8772 PSHUFDMask[Input / 2] = Input / 2;
8777 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8778 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8779 InPlaceInputs[0] - HalfOffset;
8780 // Put the second input next to the first so that they are packed into
8781 // a dword. We find the adjacent index by toggling the low bit.
8782 int AdjIndex = InPlaceInputs[0] ^ 1;
8783 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8784 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8785 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8787 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8788 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8790 // Now gather the cross-half inputs and place them into a free dword of
8791 // their target half.
8792 // FIXME: This operation could almost certainly be simplified dramatically to
8793 // look more like the 3-1 fixing operation.
8794 auto moveInputsToRightHalf = [&PSHUFDMask](
8795 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8796 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8797 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8799 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8800 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8802 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8804 int LowWord = Word & ~1;
8805 int HighWord = Word | 1;
8806 return isWordClobbered(SourceHalfMask, LowWord) ||
8807 isWordClobbered(SourceHalfMask, HighWord);
8810 if (IncomingInputs.empty())
8813 if (ExistingInputs.empty()) {
8814 // Map any dwords with inputs from them into the right half.
8815 for (int Input : IncomingInputs) {
8816 // If the source half mask maps over the inputs, turn those into
8817 // swaps and use the swapped lane.
8818 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8819 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8820 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8821 Input - SourceOffset;
8822 // We have to swap the uses in our half mask in one sweep.
8823 for (int &M : HalfMask)
8824 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8826 else if (M == Input)
8827 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8829 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8830 Input - SourceOffset &&
8831 "Previous placement doesn't match!");
8833 // Note that this correctly re-maps both when we do a swap and when
8834 // we observe the other side of the swap above. We rely on that to
8835 // avoid swapping the members of the input list directly.
8836 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8839 // Map the input's dword into the correct half.
8840 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8841 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8843 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8845 "Previous placement doesn't match!");
8848 // And just directly shift any other-half mask elements to be same-half
8849 // as we will have mirrored the dword containing the element into the
8850 // same position within that half.
8851 for (int &M : HalfMask)
8852 if (M >= SourceOffset && M < SourceOffset + 4) {
8853 M = M - SourceOffset + DestOffset;
8854 assert(M >= 0 && "This should never wrap below zero!");
8859 // Ensure we have the input in a viable dword of its current half. This
8860 // is particularly tricky because the original position may be clobbered
8861 // by inputs being moved and *staying* in that half.
8862 if (IncomingInputs.size() == 1) {
8863 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8864 int InputFixed = std::find(std::begin(SourceHalfMask),
8865 std::end(SourceHalfMask), -1) -
8866 std::begin(SourceHalfMask) + SourceOffset;
8867 SourceHalfMask[InputFixed - SourceOffset] =
8868 IncomingInputs[0] - SourceOffset;
8869 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8871 IncomingInputs[0] = InputFixed;
8873 } else if (IncomingInputs.size() == 2) {
8874 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8875 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8876 // We have two non-adjacent or clobbered inputs we need to extract from
8877 // the source half. To do this, we need to map them into some adjacent
8878 // dword slot in the source mask.
8879 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8880 IncomingInputs[1] - SourceOffset};
8882 // If there is a free slot in the source half mask adjacent to one of
8883 // the inputs, place the other input in it. We use (Index XOR 1) to
8884 // compute an adjacent index.
8885 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8886 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8887 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8888 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8889 InputsFixed[1] = InputsFixed[0] ^ 1;
8890 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8891 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8892 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8893 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8894 InputsFixed[0] = InputsFixed[1] ^ 1;
8895 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8896 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8897 // The two inputs are in the same DWord but it is clobbered and the
8898 // adjacent DWord isn't used at all. Move both inputs to the free
8900 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8901 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8902 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8903 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8905 // The only way we hit this point is if there is no clobbering
8906 // (because there are no off-half inputs to this half) and there is no
8907 // free slot adjacent to one of the inputs. In this case, we have to
8908 // swap an input with a non-input.
8909 for (int i = 0; i < 4; ++i)
8910 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8911 "We can't handle any clobbers here!");
8912 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8913 "Cannot have adjacent inputs here!");
8915 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8916 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8918 // We also have to update the final source mask in this case because
8919 // it may need to undo the above swap.
8920 for (int &M : FinalSourceHalfMask)
8921 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8922 M = InputsFixed[1] + SourceOffset;
8923 else if (M == InputsFixed[1] + SourceOffset)
8924 M = (InputsFixed[0] ^ 1) + SourceOffset;
8926 InputsFixed[1] = InputsFixed[0] ^ 1;
8929 // Point everything at the fixed inputs.
8930 for (int &M : HalfMask)
8931 if (M == IncomingInputs[0])
8932 M = InputsFixed[0] + SourceOffset;
8933 else if (M == IncomingInputs[1])
8934 M = InputsFixed[1] + SourceOffset;
8936 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8937 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8940 llvm_unreachable("Unhandled input size!");
8943 // Now hoist the DWord down to the right half.
8944 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8945 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8946 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8947 for (int &M : HalfMask)
8948 for (int Input : IncomingInputs)
8950 M = FreeDWord * 2 + Input % 2;
8952 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8953 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8954 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8955 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8957 // Now enact all the shuffles we've computed to move the inputs into their
8959 if (!isNoopShuffleMask(PSHUFLMask))
8960 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8961 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8962 if (!isNoopShuffleMask(PSHUFHMask))
8963 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8964 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8965 if (!isNoopShuffleMask(PSHUFDMask))
8966 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8967 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8968 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8969 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8971 // At this point, each half should contain all its inputs, and we can then
8972 // just shuffle them into their final position.
8973 assert(std::count_if(LoMask.begin(), LoMask.end(),
8974 [](int M) { return M >= 4; }) == 0 &&
8975 "Failed to lift all the high half inputs to the low mask!");
8976 assert(std::count_if(HiMask.begin(), HiMask.end(),
8977 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8978 "Failed to lift all the low half inputs to the high mask!");
8980 // Do a half shuffle for the low mask.
8981 if (!isNoopShuffleMask(LoMask))
8982 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8983 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8985 // Do a half shuffle with the high mask after shifting its values down.
8986 for (int &M : HiMask)
8989 if (!isNoopShuffleMask(HiMask))
8990 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8991 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8996 /// \brief Detect whether the mask pattern should be lowered through
8999 /// This essentially tests whether viewing the mask as an interleaving of two
9000 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9001 /// lowering it through interleaving is a significantly better strategy.
9002 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9003 int NumEvenInputs[2] = {0, 0};
9004 int NumOddInputs[2] = {0, 0};
9005 int NumLoInputs[2] = {0, 0};
9006 int NumHiInputs[2] = {0, 0};
9007 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9011 int InputIdx = Mask[i] >= Size;
9014 ++NumLoInputs[InputIdx];
9016 ++NumHiInputs[InputIdx];
9019 ++NumEvenInputs[InputIdx];
9021 ++NumOddInputs[InputIdx];
9024 // The minimum number of cross-input results for both the interleaved and
9025 // split cases. If interleaving results in fewer cross-input results, return
9027 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9028 NumEvenInputs[0] + NumOddInputs[1]);
9029 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9030 NumLoInputs[0] + NumHiInputs[1]);
9031 return InterleavedCrosses < SplitCrosses;
9034 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9036 /// This strategy only works when the inputs from each vector fit into a single
9037 /// half of that vector, and generally there are not so many inputs as to leave
9038 /// the in-place shuffles required highly constrained (and thus expensive). It
9039 /// shifts all the inputs into a single side of both input vectors and then
9040 /// uses an unpack to interleave these inputs in a single vector. At that
9041 /// point, we will fall back on the generic single input shuffle lowering.
9042 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9044 MutableArrayRef<int> Mask,
9045 const X86Subtarget *Subtarget,
9046 SelectionDAG &DAG) {
9047 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9048 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9049 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9050 for (int i = 0; i < 8; ++i)
9051 if (Mask[i] >= 0 && Mask[i] < 4)
9052 LoV1Inputs.push_back(i);
9053 else if (Mask[i] >= 4 && Mask[i] < 8)
9054 HiV1Inputs.push_back(i);
9055 else if (Mask[i] >= 8 && Mask[i] < 12)
9056 LoV2Inputs.push_back(i);
9057 else if (Mask[i] >= 12)
9058 HiV2Inputs.push_back(i);
9060 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9061 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9064 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9065 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9066 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9068 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9069 HiV1Inputs.size() + HiV2Inputs.size();
9071 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9072 ArrayRef<int> HiInputs, bool MoveToLo,
9074 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9075 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9076 if (BadInputs.empty())
9079 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9080 int MoveOffset = MoveToLo ? 0 : 4;
9082 if (GoodInputs.empty()) {
9083 for (int BadInput : BadInputs) {
9084 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9085 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9088 if (GoodInputs.size() == 2) {
9089 // If the low inputs are spread across two dwords, pack them into
9091 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9092 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9093 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9094 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9096 // Otherwise pin the good inputs.
9097 for (int GoodInput : GoodInputs)
9098 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9101 if (BadInputs.size() == 2) {
9102 // If we have two bad inputs then there may be either one or two good
9103 // inputs fixed in place. Find a fixed input, and then find the *other*
9104 // two adjacent indices by using modular arithmetic.
9106 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9107 [](int M) { return M >= 0; }) -
9108 std::begin(MoveMask);
9110 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9111 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9112 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9113 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9114 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9115 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9116 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9118 assert(BadInputs.size() == 1 && "All sizes handled");
9119 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9120 std::end(MoveMask), -1) -
9121 std::begin(MoveMask);
9122 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9123 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9127 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9130 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9132 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9135 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9136 // cross-half traffic in the final shuffle.
9138 // Munge the mask to be a single-input mask after the unpack merges the
9142 M = 2 * (M % 4) + (M / 8);
9144 return DAG.getVectorShuffle(
9145 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9146 DL, MVT::v8i16, V1, V2),
9147 DAG.getUNDEF(MVT::v8i16), Mask);
9150 /// \brief Generic lowering of 8-lane i16 shuffles.
9152 /// This handles both single-input shuffles and combined shuffle/blends with
9153 /// two inputs. The single input shuffles are immediately delegated to
9154 /// a dedicated lowering routine.
9156 /// The blends are lowered in one of three fundamental ways. If there are few
9157 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9158 /// of the input is significantly cheaper when lowered as an interleaving of
9159 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9160 /// halves of the inputs separately (making them have relatively few inputs)
9161 /// and then concatenate them.
9162 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9163 const X86Subtarget *Subtarget,
9164 SelectionDAG &DAG) {
9166 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9167 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9168 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9169 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9170 ArrayRef<int> OrigMask = SVOp->getMask();
9171 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9172 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9173 MutableArrayRef<int> Mask(MaskStorage);
9175 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9177 // Whenever we can lower this as a zext, that instruction is strictly faster
9178 // than any alternative.
9179 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9180 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9183 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9184 auto isV2 = [](int M) { return M >= 8; };
9186 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9187 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9189 if (NumV2Inputs == 0)
9190 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9192 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9193 "to be V1-input shuffles.");
9195 // There are special ways we can lower some single-element blends.
9196 if (NumV2Inputs == 1)
9197 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9198 Mask, Subtarget, DAG))
9201 // Use dedicated unpack instructions for masks that match their pattern.
9202 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9203 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9204 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9205 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9207 if (Subtarget->hasSSE41())
9208 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9212 // Try to use byte shift instructions.
9213 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9214 DL, MVT::v8i16, V1, V2, Mask, DAG))
9217 // Try to use byte rotation instructions.
9218 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9219 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9222 if (NumV1Inputs + NumV2Inputs <= 4)
9223 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9225 // Check whether an interleaving lowering is likely to be more efficient.
9226 // This isn't perfect but it is a strong heuristic that tends to work well on
9227 // the kinds of shuffles that show up in practice.
9229 // FIXME: Handle 1x, 2x, and 4x interleaving.
9230 if (shouldLowerAsInterleaving(Mask)) {
9231 // FIXME: Figure out whether we should pack these into the low or high
9234 int EMask[8], OMask[8];
9235 for (int i = 0; i < 4; ++i) {
9236 EMask[i] = Mask[2*i];
9237 OMask[i] = Mask[2*i + 1];
9242 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9243 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9245 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9248 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9249 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9251 for (int i = 0; i < 4; ++i) {
9252 LoBlendMask[i] = Mask[i];
9253 HiBlendMask[i] = Mask[i + 4];
9256 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9257 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9258 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9259 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9261 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9262 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9265 /// \brief Check whether a compaction lowering can be done by dropping even
9266 /// elements and compute how many times even elements must be dropped.
9268 /// This handles shuffles which take every Nth element where N is a power of
9269 /// two. Example shuffle masks:
9271 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9272 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9273 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9274 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9275 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9276 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9278 /// Any of these lanes can of course be undef.
9280 /// This routine only supports N <= 3.
9281 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9284 /// \returns N above, or the number of times even elements must be dropped if
9285 /// there is such a number. Otherwise returns zero.
9286 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9287 // Figure out whether we're looping over two inputs or just one.
9288 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9290 // The modulus for the shuffle vector entries is based on whether this is
9291 // a single input or not.
9292 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9293 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9294 "We should only be called with masks with a power-of-2 size!");
9296 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9298 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9299 // and 2^3 simultaneously. This is because we may have ambiguity with
9300 // partially undef inputs.
9301 bool ViableForN[3] = {true, true, true};
9303 for (int i = 0, e = Mask.size(); i < e; ++i) {
9304 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9309 bool IsAnyViable = false;
9310 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9311 if (ViableForN[j]) {
9314 // The shuffle mask must be equal to (i * 2^N) % M.
9315 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9318 ViableForN[j] = false;
9320 // Early exit if we exhaust the possible powers of two.
9325 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9329 // Return 0 as there is no viable power of two.
9333 /// \brief Generic lowering of v16i8 shuffles.
9335 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9336 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9337 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9338 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9340 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9341 const X86Subtarget *Subtarget,
9342 SelectionDAG &DAG) {
9344 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9345 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9346 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9348 ArrayRef<int> OrigMask = SVOp->getMask();
9349 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9351 // Try to use byte shift instructions.
9352 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9353 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9356 // Try to use byte rotation instructions.
9357 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9358 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9361 // Try to use a zext lowering.
9362 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9363 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9366 int MaskStorage[16] = {
9367 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9368 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9369 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9370 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9371 MutableArrayRef<int> Mask(MaskStorage);
9372 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9373 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9376 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9378 // For single-input shuffles, there are some nicer lowering tricks we can use.
9379 if (NumV2Elements == 0) {
9380 // Check for being able to broadcast a single element.
9381 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9382 Mask, Subtarget, DAG))
9385 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9386 // Notably, this handles splat and partial-splat shuffles more efficiently.
9387 // However, it only makes sense if the pre-duplication shuffle simplifies
9388 // things significantly. Currently, this means we need to be able to
9389 // express the pre-duplication shuffle as an i16 shuffle.
9391 // FIXME: We should check for other patterns which can be widened into an
9392 // i16 shuffle as well.
9393 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9394 for (int i = 0; i < 16; i += 2)
9395 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9400 auto tryToWidenViaDuplication = [&]() -> SDValue {
9401 if (!canWidenViaDuplication(Mask))
9403 SmallVector<int, 4> LoInputs;
9404 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9405 [](int M) { return M >= 0 && M < 8; });
9406 std::sort(LoInputs.begin(), LoInputs.end());
9407 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9409 SmallVector<int, 4> HiInputs;
9410 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9411 [](int M) { return M >= 8; });
9412 std::sort(HiInputs.begin(), HiInputs.end());
9413 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9416 bool TargetLo = LoInputs.size() >= HiInputs.size();
9417 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9418 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9420 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9421 SmallDenseMap<int, int, 8> LaneMap;
9422 for (int I : InPlaceInputs) {
9423 PreDupI16Shuffle[I/2] = I/2;
9426 int j = TargetLo ? 0 : 4, je = j + 4;
9427 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9428 // Check if j is already a shuffle of this input. This happens when
9429 // there are two adjacent bytes after we move the low one.
9430 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9431 // If we haven't yet mapped the input, search for a slot into which
9433 while (j < je && PreDupI16Shuffle[j] != -1)
9437 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9440 // Map this input with the i16 shuffle.
9441 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9444 // Update the lane map based on the mapping we ended up with.
9445 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9448 ISD::BITCAST, DL, MVT::v16i8,
9449 DAG.getVectorShuffle(MVT::v8i16, DL,
9450 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9451 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9453 // Unpack the bytes to form the i16s that will be shuffled into place.
9454 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9455 MVT::v16i8, V1, V1);
9457 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9458 for (int i = 0; i < 16; ++i)
9459 if (Mask[i] != -1) {
9460 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9461 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9462 if (PostDupI16Shuffle[i / 2] == -1)
9463 PostDupI16Shuffle[i / 2] = MappedMask;
9465 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9466 "Conflicting entrties in the original shuffle!");
9469 ISD::BITCAST, DL, MVT::v16i8,
9470 DAG.getVectorShuffle(MVT::v8i16, DL,
9471 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9472 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9474 if (SDValue V = tryToWidenViaDuplication())
9478 // Check whether an interleaving lowering is likely to be more efficient.
9479 // This isn't perfect but it is a strong heuristic that tends to work well on
9480 // the kinds of shuffles that show up in practice.
9482 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9483 if (shouldLowerAsInterleaving(Mask)) {
9484 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9485 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9487 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9488 return (M >= 8 && M < 16) || M >= 24;
9490 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9491 -1, -1, -1, -1, -1, -1, -1, -1};
9492 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9493 -1, -1, -1, -1, -1, -1, -1, -1};
9494 bool UnpackLo = NumLoHalf >= NumHiHalf;
9495 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9496 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9497 for (int i = 0; i < 8; ++i) {
9498 TargetEMask[i] = Mask[2 * i];
9499 TargetOMask[i] = Mask[2 * i + 1];
9502 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9503 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9505 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9506 MVT::v16i8, Evens, Odds);
9509 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9510 // with PSHUFB. It is important to do this before we attempt to generate any
9511 // blends but after all of the single-input lowerings. If the single input
9512 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9513 // want to preserve that and we can DAG combine any longer sequences into
9514 // a PSHUFB in the end. But once we start blending from multiple inputs,
9515 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9516 // and there are *very* few patterns that would actually be faster than the
9517 // PSHUFB approach because of its ability to zero lanes.
9519 // FIXME: The only exceptions to the above are blends which are exact
9520 // interleavings with direct instructions supporting them. We currently don't
9521 // handle those well here.
9522 if (Subtarget->hasSSSE3()) {
9525 for (int i = 0; i < 16; ++i)
9526 if (Mask[i] == -1) {
9527 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9529 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9531 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9533 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9534 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9535 if (isSingleInputShuffleMask(Mask))
9536 return V1; // Single inputs are easy.
9538 // Otherwise, blend the two.
9539 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9540 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9541 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9544 // There are special ways we can lower some single-element blends.
9545 if (NumV2Elements == 1)
9546 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9547 Mask, Subtarget, DAG))
9550 // Check whether a compaction lowering can be done. This handles shuffles
9551 // which take every Nth element for some even N. See the helper function for
9554 // We special case these as they can be particularly efficiently handled with
9555 // the PACKUSB instruction on x86 and they show up in common patterns of
9556 // rearranging bytes to truncate wide elements.
9557 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9558 // NumEvenDrops is the power of two stride of the elements. Another way of
9559 // thinking about it is that we need to drop the even elements this many
9560 // times to get the original input.
9561 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9563 // First we need to zero all the dropped bytes.
9564 assert(NumEvenDrops <= 3 &&
9565 "No support for dropping even elements more than 3 times.");
9566 // We use the mask type to pick which bytes are preserved based on how many
9567 // elements are dropped.
9568 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9569 SDValue ByteClearMask =
9570 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9571 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9572 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9574 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9576 // Now pack things back together.
9577 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9578 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9579 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9580 for (int i = 1; i < NumEvenDrops; ++i) {
9581 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9582 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9588 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9589 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9590 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9591 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9593 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9594 MutableArrayRef<int> V1HalfBlendMask,
9595 MutableArrayRef<int> V2HalfBlendMask) {
9596 for (int i = 0; i < 8; ++i)
9597 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9598 V1HalfBlendMask[i] = HalfMask[i];
9600 } else if (HalfMask[i] >= 16) {
9601 V2HalfBlendMask[i] = HalfMask[i] - 16;
9602 HalfMask[i] = i + 8;
9605 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9606 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9608 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9610 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9611 MutableArrayRef<int> HiBlendMask) {
9613 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9614 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9616 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9617 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9618 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9619 [](int M) { return M >= 0 && M % 2 == 1; })) {
9620 // Use a mask to drop the high bytes.
9621 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9622 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9623 DAG.getConstant(0x00FF, MVT::v8i16));
9625 // This will be a single vector shuffle instead of a blend so nuke V2.
9626 V2 = DAG.getUNDEF(MVT::v8i16);
9628 // Squash the masks to point directly into V1.
9629 for (int &M : LoBlendMask)
9632 for (int &M : HiBlendMask)
9636 // Otherwise just unpack the low half of V into V1 and the high half into
9637 // V2 so that we can blend them as i16s.
9638 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9639 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9640 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9641 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9644 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9645 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9646 return std::make_pair(BlendedLo, BlendedHi);
9648 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9649 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9650 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9652 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9653 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9655 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9658 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9660 /// This routine breaks down the specific type of 128-bit shuffle and
9661 /// dispatches to the lowering routines accordingly.
9662 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9663 MVT VT, const X86Subtarget *Subtarget,
9664 SelectionDAG &DAG) {
9665 switch (VT.SimpleTy) {
9667 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9669 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9671 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9673 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9675 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9677 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9680 llvm_unreachable("Unimplemented!");
9684 /// \brief Helper function to test whether a shuffle mask could be
9685 /// simplified by widening the elements being shuffled.
9687 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9688 /// leaves it in an unspecified state.
9690 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9691 /// shuffle masks. The latter have the special property of a '-2' representing
9692 /// a zero-ed lane of a vector.
9693 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9694 SmallVectorImpl<int> &WidenedMask) {
9695 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9696 // If both elements are undef, its trivial.
9697 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9698 WidenedMask.push_back(SM_SentinelUndef);
9702 // Check for an undef mask and a mask value properly aligned to fit with
9703 // a pair of values. If we find such a case, use the non-undef mask's value.
9704 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9705 WidenedMask.push_back(Mask[i + 1] / 2);
9708 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9709 WidenedMask.push_back(Mask[i] / 2);
9713 // When zeroing, we need to spread the zeroing across both lanes to widen.
9714 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9715 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9716 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9717 WidenedMask.push_back(SM_SentinelZero);
9723 // Finally check if the two mask values are adjacent and aligned with
9725 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9726 WidenedMask.push_back(Mask[i] / 2);
9730 // Otherwise we can't safely widen the elements used in this shuffle.
9733 assert(WidenedMask.size() == Mask.size() / 2 &&
9734 "Incorrect size of mask after widening the elements!");
9739 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9741 /// This routine just extracts two subvectors, shuffles them independently, and
9742 /// then concatenates them back together. This should work effectively with all
9743 /// AVX vector shuffle types.
9744 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9745 SDValue V2, ArrayRef<int> Mask,
9746 SelectionDAG &DAG) {
9747 assert(VT.getSizeInBits() >= 256 &&
9748 "Only for 256-bit or wider vector shuffles!");
9749 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9750 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9752 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9753 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9755 int NumElements = VT.getVectorNumElements();
9756 int SplitNumElements = NumElements / 2;
9757 MVT ScalarVT = VT.getScalarType();
9758 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9760 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9761 DAG.getIntPtrConstant(0));
9762 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9763 DAG.getIntPtrConstant(SplitNumElements));
9764 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9765 DAG.getIntPtrConstant(0));
9766 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9767 DAG.getIntPtrConstant(SplitNumElements));
9769 // Now create two 4-way blends of these half-width vectors.
9770 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9771 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9772 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9773 for (int i = 0; i < SplitNumElements; ++i) {
9774 int M = HalfMask[i];
9775 if (M >= NumElements) {
9776 if (M >= NumElements + SplitNumElements)
9780 V2BlendMask.push_back(M - NumElements);
9781 V1BlendMask.push_back(-1);
9782 BlendMask.push_back(SplitNumElements + i);
9783 } else if (M >= 0) {
9784 if (M >= SplitNumElements)
9788 V2BlendMask.push_back(-1);
9789 V1BlendMask.push_back(M);
9790 BlendMask.push_back(i);
9792 V2BlendMask.push_back(-1);
9793 V1BlendMask.push_back(-1);
9794 BlendMask.push_back(-1);
9798 // Because the lowering happens after all combining takes place, we need to
9799 // manually combine these blend masks as much as possible so that we create
9800 // a minimal number of high-level vector shuffle nodes.
9802 // First try just blending the halves of V1 or V2.
9803 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9804 return DAG.getUNDEF(SplitVT);
9805 if (!UseLoV2 && !UseHiV2)
9806 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9807 if (!UseLoV1 && !UseHiV1)
9808 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9810 SDValue V1Blend, V2Blend;
9811 if (UseLoV1 && UseHiV1) {
9813 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9815 // We only use half of V1 so map the usage down into the final blend mask.
9816 V1Blend = UseLoV1 ? LoV1 : HiV1;
9817 for (int i = 0; i < SplitNumElements; ++i)
9818 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9819 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9821 if (UseLoV2 && UseHiV2) {
9823 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9825 // We only use half of V2 so map the usage down into the final blend mask.
9826 V2Blend = UseLoV2 ? LoV2 : HiV2;
9827 for (int i = 0; i < SplitNumElements; ++i)
9828 if (BlendMask[i] >= SplitNumElements)
9829 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9831 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9833 SDValue Lo = HalfBlend(LoMask);
9834 SDValue Hi = HalfBlend(HiMask);
9835 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9838 /// \brief Either split a vector in halves or decompose the shuffles and the
9841 /// This is provided as a good fallback for many lowerings of non-single-input
9842 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9843 /// between splitting the shuffle into 128-bit components and stitching those
9844 /// back together vs. extracting the single-input shuffles and blending those
9846 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9847 SDValue V2, ArrayRef<int> Mask,
9848 SelectionDAG &DAG) {
9849 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9850 "lower single-input shuffles as it "
9851 "could then recurse on itself.");
9852 int Size = Mask.size();
9854 // If this can be modeled as a broadcast of two elements followed by a blend,
9855 // prefer that lowering. This is especially important because broadcasts can
9856 // often fold with memory operands.
9857 auto DoBothBroadcast = [&] {
9858 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9861 if (V2BroadcastIdx == -1)
9862 V2BroadcastIdx = M - Size;
9863 else if (M - Size != V2BroadcastIdx)
9865 } else if (M >= 0) {
9866 if (V1BroadcastIdx == -1)
9868 else if (M != V1BroadcastIdx)
9873 if (DoBothBroadcast())
9874 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9877 // If the inputs all stem from a single 128-bit lane of each input, then we
9878 // split them rather than blending because the split will decompose to
9879 // unusually few instructions.
9880 int LaneCount = VT.getSizeInBits() / 128;
9881 int LaneSize = Size / LaneCount;
9882 SmallBitVector LaneInputs[2];
9883 LaneInputs[0].resize(LaneCount, false);
9884 LaneInputs[1].resize(LaneCount, false);
9885 for (int i = 0; i < Size; ++i)
9887 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9888 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9889 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9891 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9892 // that the decomposed single-input shuffles don't end up here.
9893 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9896 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9897 /// a permutation and blend of those lanes.
9899 /// This essentially blends the out-of-lane inputs to each lane into the lane
9900 /// from a permuted copy of the vector. This lowering strategy results in four
9901 /// instructions in the worst case for a single-input cross lane shuffle which
9902 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9903 /// of. Special cases for each particular shuffle pattern should be handled
9904 /// prior to trying this lowering.
9905 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9906 SDValue V1, SDValue V2,
9908 SelectionDAG &DAG) {
9909 // FIXME: This should probably be generalized for 512-bit vectors as well.
9910 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9911 int LaneSize = Mask.size() / 2;
9913 // If there are only inputs from one 128-bit lane, splitting will in fact be
9914 // less expensive. The flags track wether the given lane contains an element
9915 // that crosses to another lane.
9916 bool LaneCrossing[2] = {false, false};
9917 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9918 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9919 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9920 if (!LaneCrossing[0] || !LaneCrossing[1])
9921 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9923 if (isSingleInputShuffleMask(Mask)) {
9924 SmallVector<int, 32> FlippedBlendMask;
9925 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9926 FlippedBlendMask.push_back(
9927 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9929 : Mask[i] % LaneSize +
9930 (i / LaneSize) * LaneSize + Size));
9932 // Flip the vector, and blend the results which should now be in-lane. The
9933 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9934 // 5 for the high source. The value 3 selects the high half of source 2 and
9935 // the value 2 selects the low half of source 2. We only use source 2 to
9936 // allow folding it into a memory operand.
9937 unsigned PERMMask = 3 | 2 << 4;
9938 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9939 V1, DAG.getConstant(PERMMask, MVT::i8));
9940 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9943 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9944 // will be handled by the above logic and a blend of the results, much like
9945 // other patterns in AVX.
9946 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9949 /// \brief Handle lowering 2-lane 128-bit shuffles.
9950 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9951 SDValue V2, ArrayRef<int> Mask,
9952 const X86Subtarget *Subtarget,
9953 SelectionDAG &DAG) {
9954 // Blends are faster and handle all the non-lane-crossing cases.
9955 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9959 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9960 VT.getVectorNumElements() / 2);
9961 // Check for patterns which can be matched with a single insert of a 128-bit
9963 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9964 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9965 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9966 DAG.getIntPtrConstant(0));
9967 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9968 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9969 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9971 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9972 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9973 DAG.getIntPtrConstant(0));
9974 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9975 DAG.getIntPtrConstant(2));
9976 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9979 // Otherwise form a 128-bit permutation.
9980 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9981 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9982 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9983 DAG.getConstant(PermMask, MVT::i8));
9986 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9988 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9989 /// isn't available.
9990 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9991 const X86Subtarget *Subtarget,
9992 SelectionDAG &DAG) {
9994 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9995 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9997 ArrayRef<int> Mask = SVOp->getMask();
9998 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10000 SmallVector<int, 4> WidenedMask;
10001 if (canWidenShuffleElements(Mask, WidenedMask))
10002 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10005 if (isSingleInputShuffleMask(Mask)) {
10006 // Check for being able to broadcast a single element.
10007 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10008 Mask, Subtarget, DAG))
10011 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10012 // Non-half-crossing single input shuffles can be lowerid with an
10013 // interleaved permutation.
10014 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10015 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10016 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10017 DAG.getConstant(VPERMILPMask, MVT::i8));
10020 // With AVX2 we have direct support for this permutation.
10021 if (Subtarget->hasAVX2())
10022 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10023 getV4X86ShuffleImm8ForMask(Mask, DAG));
10025 // Otherwise, fall back.
10026 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10030 // X86 has dedicated unpack instructions that can handle specific blend
10031 // operations: UNPCKH and UNPCKL.
10032 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10033 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10034 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10035 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10037 // If we have a single input to the zero element, insert that into V1 if we
10038 // can do so cheaply.
10039 int NumV2Elements =
10040 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10041 if (NumV2Elements == 1 && Mask[0] >= 4)
10042 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10043 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10046 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10050 // Check if the blend happens to exactly fit that of SHUFPD.
10051 if ((Mask[0] == -1 || Mask[0] < 2) &&
10052 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10053 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10054 (Mask[3] == -1 || Mask[3] >= 6)) {
10055 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10056 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10057 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10058 DAG.getConstant(SHUFPDMask, MVT::i8));
10060 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10061 (Mask[1] == -1 || Mask[1] < 2) &&
10062 (Mask[2] == -1 || Mask[2] >= 6) &&
10063 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10064 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10065 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10066 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10067 DAG.getConstant(SHUFPDMask, MVT::i8));
10070 // If we have AVX2 then we always want to lower with a blend because an v4 we
10071 // can fully permute the elements.
10072 if (Subtarget->hasAVX2())
10073 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10076 // Otherwise fall back on generic lowering.
10077 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10080 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10082 /// This routine is only called when we have AVX2 and thus a reasonable
10083 /// instruction set for v4i64 shuffling..
10084 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10085 const X86Subtarget *Subtarget,
10086 SelectionDAG &DAG) {
10088 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10089 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10091 ArrayRef<int> Mask = SVOp->getMask();
10092 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10093 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10095 SmallVector<int, 4> WidenedMask;
10096 if (canWidenShuffleElements(Mask, WidenedMask))
10097 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10100 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10104 // Check for being able to broadcast a single element.
10105 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10106 Mask, Subtarget, DAG))
10109 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10110 // use lower latency instructions that will operate on both 128-bit lanes.
10111 SmallVector<int, 2> RepeatedMask;
10112 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10113 if (isSingleInputShuffleMask(Mask)) {
10114 int PSHUFDMask[] = {-1, -1, -1, -1};
10115 for (int i = 0; i < 2; ++i)
10116 if (RepeatedMask[i] >= 0) {
10117 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10118 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10120 return DAG.getNode(
10121 ISD::BITCAST, DL, MVT::v4i64,
10122 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10123 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10124 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10127 // Use dedicated unpack instructions for masks that match their pattern.
10128 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10129 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10130 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10131 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10134 // AVX2 provides a direct instruction for permuting a single input across
10136 if (isSingleInputShuffleMask(Mask))
10137 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10138 getV4X86ShuffleImm8ForMask(Mask, DAG));
10140 // Otherwise fall back on generic blend lowering.
10141 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10145 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10147 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10148 /// isn't available.
10149 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10150 const X86Subtarget *Subtarget,
10151 SelectionDAG &DAG) {
10153 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10154 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10156 ArrayRef<int> Mask = SVOp->getMask();
10157 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10159 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10163 // Check for being able to broadcast a single element.
10164 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10165 Mask, Subtarget, DAG))
10168 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10169 // options to efficiently lower the shuffle.
10170 SmallVector<int, 4> RepeatedMask;
10171 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10172 assert(RepeatedMask.size() == 4 &&
10173 "Repeated masks must be half the mask width!");
10174 if (isSingleInputShuffleMask(Mask))
10175 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10176 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10178 // Use dedicated unpack instructions for masks that match their pattern.
10179 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10180 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10181 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10182 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10184 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10185 // have already handled any direct blends. We also need to squash the
10186 // repeated mask into a simulated v4f32 mask.
10187 for (int i = 0; i < 4; ++i)
10188 if (RepeatedMask[i] >= 8)
10189 RepeatedMask[i] -= 4;
10190 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10193 // If we have a single input shuffle with different shuffle patterns in the
10194 // two 128-bit lanes use the variable mask to VPERMILPS.
10195 if (isSingleInputShuffleMask(Mask)) {
10196 SDValue VPermMask[8];
10197 for (int i = 0; i < 8; ++i)
10198 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10199 : DAG.getConstant(Mask[i], MVT::i32);
10200 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10201 return DAG.getNode(
10202 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10203 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10205 if (Subtarget->hasAVX2())
10206 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10207 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10208 DAG.getNode(ISD::BUILD_VECTOR, DL,
10209 MVT::v8i32, VPermMask)),
10212 // Otherwise, fall back.
10213 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10217 // If we have AVX2 then we always want to lower with a blend because at v8 we
10218 // can fully permute the elements.
10219 if (Subtarget->hasAVX2())
10220 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10223 // Otherwise fall back on generic lowering.
10224 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10227 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10229 /// This routine is only called when we have AVX2 and thus a reasonable
10230 /// instruction set for v8i32 shuffling..
10231 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10232 const X86Subtarget *Subtarget,
10233 SelectionDAG &DAG) {
10235 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10236 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10237 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10238 ArrayRef<int> Mask = SVOp->getMask();
10239 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10240 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10242 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10246 // Check for being able to broadcast a single element.
10247 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10248 Mask, Subtarget, DAG))
10251 // If the shuffle mask is repeated in each 128-bit lane we can use more
10252 // efficient instructions that mirror the shuffles across the two 128-bit
10254 SmallVector<int, 4> RepeatedMask;
10255 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10256 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10257 if (isSingleInputShuffleMask(Mask))
10258 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10259 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10261 // Use dedicated unpack instructions for masks that match their pattern.
10262 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10263 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10264 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10265 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10268 // If the shuffle patterns aren't repeated but it is a single input, directly
10269 // generate a cross-lane VPERMD instruction.
10270 if (isSingleInputShuffleMask(Mask)) {
10271 SDValue VPermMask[8];
10272 for (int i = 0; i < 8; ++i)
10273 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10274 : DAG.getConstant(Mask[i], MVT::i32);
10275 return DAG.getNode(
10276 X86ISD::VPERMV, DL, MVT::v8i32,
10277 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10280 // Otherwise fall back on generic blend lowering.
10281 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10285 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10287 /// This routine is only called when we have AVX2 and thus a reasonable
10288 /// instruction set for v16i16 shuffling..
10289 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10290 const X86Subtarget *Subtarget,
10291 SelectionDAG &DAG) {
10293 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10294 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10296 ArrayRef<int> Mask = SVOp->getMask();
10297 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10298 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10300 // Check for being able to broadcast a single element.
10301 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10302 Mask, Subtarget, DAG))
10305 // There are no generalized cross-lane shuffle operations available on i16
10307 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10308 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10311 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10315 // Use dedicated unpack instructions for masks that match their pattern.
10316 if (isShuffleEquivalent(Mask,
10317 // First 128-bit lane:
10318 0, 16, 1, 17, 2, 18, 3, 19,
10319 // Second 128-bit lane:
10320 8, 24, 9, 25, 10, 26, 11, 27))
10321 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10322 if (isShuffleEquivalent(Mask,
10323 // First 128-bit lane:
10324 4, 20, 5, 21, 6, 22, 7, 23,
10325 // Second 128-bit lane:
10326 12, 28, 13, 29, 14, 30, 15, 31))
10327 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10329 if (isSingleInputShuffleMask(Mask)) {
10330 SDValue PSHUFBMask[32];
10331 for (int i = 0; i < 16; ++i) {
10332 if (Mask[i] == -1) {
10333 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10337 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10338 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10339 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10340 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10342 return DAG.getNode(
10343 ISD::BITCAST, DL, MVT::v16i16,
10345 X86ISD::PSHUFB, DL, MVT::v32i8,
10346 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10347 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10350 // Otherwise fall back on generic lowering.
10351 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10354 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10356 /// This routine is only called when we have AVX2 and thus a reasonable
10357 /// instruction set for v32i8 shuffling..
10358 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10359 const X86Subtarget *Subtarget,
10360 SelectionDAG &DAG) {
10362 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10363 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10365 ArrayRef<int> Mask = SVOp->getMask();
10366 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10367 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10369 // Check for being able to broadcast a single element.
10370 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10371 Mask, Subtarget, DAG))
10374 // There are no generalized cross-lane shuffle operations available on i8
10376 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10377 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10380 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10384 // Use dedicated unpack instructions for masks that match their pattern.
10385 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10387 if (isShuffleEquivalent(
10389 // First 128-bit lane:
10390 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10391 // Second 128-bit lane:
10392 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10393 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10394 if (isShuffleEquivalent(
10396 // First 128-bit lane:
10397 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10398 // Second 128-bit lane:
10399 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10400 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10402 if (isSingleInputShuffleMask(Mask)) {
10403 SDValue PSHUFBMask[32];
10404 for (int i = 0; i < 32; ++i)
10407 ? DAG.getUNDEF(MVT::i8)
10408 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10410 return DAG.getNode(
10411 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10412 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10415 // Otherwise fall back on generic lowering.
10416 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10419 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10421 /// This routine either breaks down the specific type of a 256-bit x86 vector
10422 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10423 /// together based on the available instructions.
10424 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10425 MVT VT, const X86Subtarget *Subtarget,
10426 SelectionDAG &DAG) {
10428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10429 ArrayRef<int> Mask = SVOp->getMask();
10431 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10432 // check for those subtargets here and avoid much of the subtarget querying in
10433 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10434 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10435 // floating point types there eventually, just immediately cast everything to
10436 // a float and operate entirely in that domain.
10437 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10438 int ElementBits = VT.getScalarSizeInBits();
10439 if (ElementBits < 32)
10440 // No floating point type available, decompose into 128-bit vectors.
10441 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10443 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10444 VT.getVectorNumElements());
10445 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10446 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10447 return DAG.getNode(ISD::BITCAST, DL, VT,
10448 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10451 switch (VT.SimpleTy) {
10453 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10455 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10457 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10459 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10461 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10463 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10466 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10470 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10471 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10472 const X86Subtarget *Subtarget,
10473 SelectionDAG &DAG) {
10475 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10476 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10478 ArrayRef<int> Mask = SVOp->getMask();
10479 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10481 // FIXME: Implement direct support for this type!
10482 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10485 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10486 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10487 const X86Subtarget *Subtarget,
10488 SelectionDAG &DAG) {
10490 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10491 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10493 ArrayRef<int> Mask = SVOp->getMask();
10494 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10496 // FIXME: Implement direct support for this type!
10497 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10500 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10501 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10502 const X86Subtarget *Subtarget,
10503 SelectionDAG &DAG) {
10505 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10506 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10507 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10508 ArrayRef<int> Mask = SVOp->getMask();
10509 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10511 // FIXME: Implement direct support for this type!
10512 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10515 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10516 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10517 const X86Subtarget *Subtarget,
10518 SelectionDAG &DAG) {
10520 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10521 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10522 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10523 ArrayRef<int> Mask = SVOp->getMask();
10524 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10526 // FIXME: Implement direct support for this type!
10527 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10530 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10531 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10532 const X86Subtarget *Subtarget,
10533 SelectionDAG &DAG) {
10535 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10536 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10537 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10538 ArrayRef<int> Mask = SVOp->getMask();
10539 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10540 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10542 // FIXME: Implement direct support for this type!
10543 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10546 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10547 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10548 const X86Subtarget *Subtarget,
10549 SelectionDAG &DAG) {
10551 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10552 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10553 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10554 ArrayRef<int> Mask = SVOp->getMask();
10555 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10556 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10558 // FIXME: Implement direct support for this type!
10559 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10562 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10564 /// This routine either breaks down the specific type of a 512-bit x86 vector
10565 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10566 /// together based on the available instructions.
10567 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10568 MVT VT, const X86Subtarget *Subtarget,
10569 SelectionDAG &DAG) {
10571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10572 ArrayRef<int> Mask = SVOp->getMask();
10573 assert(Subtarget->hasAVX512() &&
10574 "Cannot lower 512-bit vectors w/ basic ISA!");
10576 // Check for being able to broadcast a single element.
10577 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10578 Mask, Subtarget, DAG))
10581 // Dispatch to each element type for lowering. If we don't have supprot for
10582 // specific element type shuffles at 512 bits, immediately split them and
10583 // lower them. Each lowering routine of a given type is allowed to assume that
10584 // the requisite ISA extensions for that element type are available.
10585 switch (VT.SimpleTy) {
10587 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10589 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10591 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10593 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10595 if (Subtarget->hasBWI())
10596 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10599 if (Subtarget->hasBWI())
10600 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10604 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10607 // Otherwise fall back on splitting.
10608 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10611 /// \brief Top-level lowering for x86 vector shuffles.
10613 /// This handles decomposition, canonicalization, and lowering of all x86
10614 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10615 /// above in helper routines. The canonicalization attempts to widen shuffles
10616 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10617 /// s.t. only one of the two inputs needs to be tested, etc.
10618 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10619 SelectionDAG &DAG) {
10620 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10621 ArrayRef<int> Mask = SVOp->getMask();
10622 SDValue V1 = Op.getOperand(0);
10623 SDValue V2 = Op.getOperand(1);
10624 MVT VT = Op.getSimpleValueType();
10625 int NumElements = VT.getVectorNumElements();
10628 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10630 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10631 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10632 if (V1IsUndef && V2IsUndef)
10633 return DAG.getUNDEF(VT);
10635 // When we create a shuffle node we put the UNDEF node to second operand,
10636 // but in some cases the first operand may be transformed to UNDEF.
10637 // In this case we should just commute the node.
10639 return DAG.getCommutedVectorShuffle(*SVOp);
10641 // Check for non-undef masks pointing at an undef vector and make the masks
10642 // undef as well. This makes it easier to match the shuffle based solely on
10646 if (M >= NumElements) {
10647 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10648 for (int &M : NewMask)
10649 if (M >= NumElements)
10651 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10654 // Try to collapse shuffles into using a vector type with fewer elements but
10655 // wider element types. We cap this to not form integers or floating point
10656 // elements wider than 64 bits, but it might be interesting to form i128
10657 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10658 SmallVector<int, 16> WidenedMask;
10659 if (VT.getScalarSizeInBits() < 64 &&
10660 canWidenShuffleElements(Mask, WidenedMask)) {
10661 MVT NewEltVT = VT.isFloatingPoint()
10662 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10663 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10664 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10665 // Make sure that the new vector type is legal. For example, v2f64 isn't
10667 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10668 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10669 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10670 return DAG.getNode(ISD::BITCAST, dl, VT,
10671 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10675 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10676 for (int M : SVOp->getMask())
10678 ++NumUndefElements;
10679 else if (M < NumElements)
10684 // Commute the shuffle as needed such that more elements come from V1 than
10685 // V2. This allows us to match the shuffle pattern strictly on how many
10686 // elements come from V1 without handling the symmetric cases.
10687 if (NumV2Elements > NumV1Elements)
10688 return DAG.getCommutedVectorShuffle(*SVOp);
10690 // When the number of V1 and V2 elements are the same, try to minimize the
10691 // number of uses of V2 in the low half of the vector. When that is tied,
10692 // ensure that the sum of indices for V1 is equal to or lower than the sum
10694 if (NumV1Elements == NumV2Elements) {
10695 int LowV1Elements = 0, LowV2Elements = 0;
10696 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10697 if (M >= NumElements)
10701 if (LowV2Elements > LowV1Elements) {
10702 return DAG.getCommutedVectorShuffle(*SVOp);
10703 } else if (LowV2Elements == LowV1Elements) {
10704 int SumV1Indices = 0, SumV2Indices = 0;
10705 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10706 if (SVOp->getMask()[i] >= NumElements)
10708 else if (SVOp->getMask()[i] >= 0)
10710 if (SumV2Indices < SumV1Indices)
10711 return DAG.getCommutedVectorShuffle(*SVOp);
10715 // For each vector width, delegate to a specialized lowering routine.
10716 if (VT.getSizeInBits() == 128)
10717 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10719 if (VT.getSizeInBits() == 256)
10720 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10722 // Force AVX-512 vectors to be scalarized for now.
10723 // FIXME: Implement AVX-512 support!
10724 if (VT.getSizeInBits() == 512)
10725 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10727 llvm_unreachable("Unimplemented!");
10731 //===----------------------------------------------------------------------===//
10732 // Legacy vector shuffle lowering
10734 // This code is the legacy code handling vector shuffles until the above
10735 // replaces its functionality and performance.
10736 //===----------------------------------------------------------------------===//
10738 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10739 bool hasInt256, unsigned *MaskOut = nullptr) {
10740 MVT EltVT = VT.getVectorElementType();
10742 // There is no blend with immediate in AVX-512.
10743 if (VT.is512BitVector())
10746 if (!hasSSE41 || EltVT == MVT::i8)
10748 if (!hasInt256 && VT == MVT::v16i16)
10751 unsigned MaskValue = 0;
10752 unsigned NumElems = VT.getVectorNumElements();
10753 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10754 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10755 unsigned NumElemsInLane = NumElems / NumLanes;
10757 // Blend for v16i16 should be symetric for the both lanes.
10758 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10760 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10761 int EltIdx = MaskVals[i];
10763 if ((EltIdx < 0 || EltIdx == (int)i) &&
10764 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10767 if (((unsigned)EltIdx == (i + NumElems)) &&
10768 (SndLaneEltIdx < 0 ||
10769 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10770 MaskValue |= (1 << i);
10776 *MaskOut = MaskValue;
10780 // Try to lower a shuffle node into a simple blend instruction.
10781 // This function assumes isBlendMask returns true for this
10782 // SuffleVectorSDNode
10783 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10784 unsigned MaskValue,
10785 const X86Subtarget *Subtarget,
10786 SelectionDAG &DAG) {
10787 MVT VT = SVOp->getSimpleValueType(0);
10788 MVT EltVT = VT.getVectorElementType();
10789 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10790 Subtarget->hasInt256() && "Trying to lower a "
10791 "VECTOR_SHUFFLE to a Blend but "
10792 "with the wrong mask"));
10793 SDValue V1 = SVOp->getOperand(0);
10794 SDValue V2 = SVOp->getOperand(1);
10796 unsigned NumElems = VT.getVectorNumElements();
10798 // Convert i32 vectors to floating point if it is not AVX2.
10799 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10801 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10802 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10804 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10805 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10808 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10809 DAG.getConstant(MaskValue, MVT::i32));
10810 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10813 /// In vector type \p VT, return true if the element at index \p InputIdx
10814 /// falls on a different 128-bit lane than \p OutputIdx.
10815 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10816 unsigned OutputIdx) {
10817 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10818 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10821 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10822 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10823 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10824 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10826 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10827 SelectionDAG &DAG) {
10828 MVT VT = V1.getSimpleValueType();
10829 assert(VT.is128BitVector() || VT.is256BitVector());
10831 MVT EltVT = VT.getVectorElementType();
10832 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10833 unsigned NumElts = VT.getVectorNumElements();
10835 SmallVector<SDValue, 32> PshufbMask;
10836 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10837 int InputIdx = MaskVals[OutputIdx];
10838 unsigned InputByteIdx;
10840 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10841 InputByteIdx = 0x80;
10843 // Cross lane is not allowed.
10844 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10846 InputByteIdx = InputIdx * EltSizeInBytes;
10847 // Index is an byte offset within the 128-bit lane.
10848 InputByteIdx &= 0xf;
10851 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10852 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10853 if (InputByteIdx != 0x80)
10858 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10860 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10861 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10862 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10865 // v8i16 shuffles - Prefer shuffles in the following order:
10866 // 1. [all] pshuflw, pshufhw, optional move
10867 // 2. [ssse3] 1 x pshufb
10868 // 3. [ssse3] 2 x pshufb + 1 x por
10869 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10871 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10872 SelectionDAG &DAG) {
10873 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10874 SDValue V1 = SVOp->getOperand(0);
10875 SDValue V2 = SVOp->getOperand(1);
10877 SmallVector<int, 8> MaskVals;
10879 // Determine if more than 1 of the words in each of the low and high quadwords
10880 // of the result come from the same quadword of one of the two inputs. Undef
10881 // mask values count as coming from any quadword, for better codegen.
10883 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10884 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10885 unsigned LoQuad[] = { 0, 0, 0, 0 };
10886 unsigned HiQuad[] = { 0, 0, 0, 0 };
10887 // Indices of quads used.
10888 std::bitset<4> InputQuads;
10889 for (unsigned i = 0; i < 8; ++i) {
10890 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10891 int EltIdx = SVOp->getMaskElt(i);
10892 MaskVals.push_back(EltIdx);
10900 ++Quad[EltIdx / 4];
10901 InputQuads.set(EltIdx / 4);
10904 int BestLoQuad = -1;
10905 unsigned MaxQuad = 1;
10906 for (unsigned i = 0; i < 4; ++i) {
10907 if (LoQuad[i] > MaxQuad) {
10909 MaxQuad = LoQuad[i];
10913 int BestHiQuad = -1;
10915 for (unsigned i = 0; i < 4; ++i) {
10916 if (HiQuad[i] > MaxQuad) {
10918 MaxQuad = HiQuad[i];
10922 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10923 // of the two input vectors, shuffle them into one input vector so only a
10924 // single pshufb instruction is necessary. If there are more than 2 input
10925 // quads, disable the next transformation since it does not help SSSE3.
10926 bool V1Used = InputQuads[0] || InputQuads[1];
10927 bool V2Used = InputQuads[2] || InputQuads[3];
10928 if (Subtarget->hasSSSE3()) {
10929 if (InputQuads.count() == 2 && V1Used && V2Used) {
10930 BestLoQuad = InputQuads[0] ? 0 : 1;
10931 BestHiQuad = InputQuads[2] ? 2 : 3;
10933 if (InputQuads.count() > 2) {
10939 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10940 // the shuffle mask. If a quad is scored as -1, that means that it contains
10941 // words from all 4 input quadwords.
10943 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10945 BestLoQuad < 0 ? 0 : BestLoQuad,
10946 BestHiQuad < 0 ? 1 : BestHiQuad
10948 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10949 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10950 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10951 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10953 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10954 // source words for the shuffle, to aid later transformations.
10955 bool AllWordsInNewV = true;
10956 bool InOrder[2] = { true, true };
10957 for (unsigned i = 0; i != 8; ++i) {
10958 int idx = MaskVals[i];
10960 InOrder[i/4] = false;
10961 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10963 AllWordsInNewV = false;
10967 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10968 if (AllWordsInNewV) {
10969 for (int i = 0; i != 8; ++i) {
10970 int idx = MaskVals[i];
10973 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10974 if ((idx != i) && idx < 4)
10976 if ((idx != i) && idx > 3)
10985 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10986 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10987 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10988 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10989 unsigned TargetMask = 0;
10990 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10991 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10992 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10993 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10994 getShufflePSHUFLWImmediate(SVOp);
10995 V1 = NewV.getOperand(0);
10996 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11000 // Promote splats to a larger type which usually leads to more efficient code.
11001 // FIXME: Is this true if pshufb is available?
11002 if (SVOp->isSplat())
11003 return PromoteSplat(SVOp, DAG);
11005 // If we have SSSE3, and all words of the result are from 1 input vector,
11006 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11007 // is present, fall back to case 4.
11008 if (Subtarget->hasSSSE3()) {
11009 SmallVector<SDValue,16> pshufbMask;
11011 // If we have elements from both input vectors, set the high bit of the
11012 // shuffle mask element to zero out elements that come from V2 in the V1
11013 // mask, and elements that come from V1 in the V2 mask, so that the two
11014 // results can be OR'd together.
11015 bool TwoInputs = V1Used && V2Used;
11016 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11018 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11020 // Calculate the shuffle mask for the second input, shuffle it, and
11021 // OR it with the first shuffled input.
11022 CommuteVectorShuffleMask(MaskVals, 8);
11023 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11024 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11025 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11028 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11029 // and update MaskVals with new element order.
11030 std::bitset<8> InOrder;
11031 if (BestLoQuad >= 0) {
11032 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11033 for (int i = 0; i != 4; ++i) {
11034 int idx = MaskVals[i];
11037 } else if ((idx / 4) == BestLoQuad) {
11038 MaskV[i] = idx & 3;
11042 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11045 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11047 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11048 NewV.getOperand(0),
11049 getShufflePSHUFLWImmediate(SVOp), DAG);
11053 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11054 // and update MaskVals with the new element order.
11055 if (BestHiQuad >= 0) {
11056 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11057 for (unsigned i = 4; i != 8; ++i) {
11058 int idx = MaskVals[i];
11061 } else if ((idx / 4) == BestHiQuad) {
11062 MaskV[i] = (idx & 3) + 4;
11066 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11069 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11070 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11071 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11072 NewV.getOperand(0),
11073 getShufflePSHUFHWImmediate(SVOp), DAG);
11077 // In case BestHi & BestLo were both -1, which means each quadword has a word
11078 // from each of the four input quadwords, calculate the InOrder bitvector now
11079 // before falling through to the insert/extract cleanup.
11080 if (BestLoQuad == -1 && BestHiQuad == -1) {
11082 for (int i = 0; i != 8; ++i)
11083 if (MaskVals[i] < 0 || MaskVals[i] == i)
11087 // The other elements are put in the right place using pextrw and pinsrw.
11088 for (unsigned i = 0; i != 8; ++i) {
11091 int EltIdx = MaskVals[i];
11094 SDValue ExtOp = (EltIdx < 8) ?
11095 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11096 DAG.getIntPtrConstant(EltIdx)) :
11097 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11098 DAG.getIntPtrConstant(EltIdx - 8));
11099 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11100 DAG.getIntPtrConstant(i));
11105 /// \brief v16i16 shuffles
11107 /// FIXME: We only support generation of a single pshufb currently. We can
11108 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11109 /// well (e.g 2 x pshufb + 1 x por).
11111 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11113 SDValue V1 = SVOp->getOperand(0);
11114 SDValue V2 = SVOp->getOperand(1);
11117 if (V2.getOpcode() != ISD::UNDEF)
11120 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11121 return getPSHUFB(MaskVals, V1, dl, DAG);
11124 // v16i8 shuffles - Prefer shuffles in the following order:
11125 // 1. [ssse3] 1 x pshufb
11126 // 2. [ssse3] 2 x pshufb + 1 x por
11127 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11128 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11129 const X86Subtarget* Subtarget,
11130 SelectionDAG &DAG) {
11131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11132 SDValue V1 = SVOp->getOperand(0);
11133 SDValue V2 = SVOp->getOperand(1);
11135 ArrayRef<int> MaskVals = SVOp->getMask();
11137 // Promote splats to a larger type which usually leads to more efficient code.
11138 // FIXME: Is this true if pshufb is available?
11139 if (SVOp->isSplat())
11140 return PromoteSplat(SVOp, DAG);
11142 // If we have SSSE3, case 1 is generated when all result bytes come from
11143 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11144 // present, fall back to case 3.
11146 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11147 if (Subtarget->hasSSSE3()) {
11148 SmallVector<SDValue,16> pshufbMask;
11150 // If all result elements are from one input vector, then only translate
11151 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11153 // Otherwise, we have elements from both input vectors, and must zero out
11154 // elements that come from V2 in the first mask, and V1 in the second mask
11155 // so that we can OR them together.
11156 for (unsigned i = 0; i != 16; ++i) {
11157 int EltIdx = MaskVals[i];
11158 if (EltIdx < 0 || EltIdx >= 16)
11160 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11162 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11163 DAG.getNode(ISD::BUILD_VECTOR, dl,
11164 MVT::v16i8, pshufbMask));
11166 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11167 // the 2nd operand if it's undefined or zero.
11168 if (V2.getOpcode() == ISD::UNDEF ||
11169 ISD::isBuildVectorAllZeros(V2.getNode()))
11172 // Calculate the shuffle mask for the second input, shuffle it, and
11173 // OR it with the first shuffled input.
11174 pshufbMask.clear();
11175 for (unsigned i = 0; i != 16; ++i) {
11176 int EltIdx = MaskVals[i];
11177 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11178 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11180 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11181 DAG.getNode(ISD::BUILD_VECTOR, dl,
11182 MVT::v16i8, pshufbMask));
11183 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11186 // No SSSE3 - Calculate in place words and then fix all out of place words
11187 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11188 // the 16 different words that comprise the two doublequadword input vectors.
11189 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11190 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11192 for (int i = 0; i != 8; ++i) {
11193 int Elt0 = MaskVals[i*2];
11194 int Elt1 = MaskVals[i*2+1];
11196 // This word of the result is all undef, skip it.
11197 if (Elt0 < 0 && Elt1 < 0)
11200 // This word of the result is already in the correct place, skip it.
11201 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11204 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11205 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11208 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11209 // using a single extract together, load it and store it.
11210 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11211 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11212 DAG.getIntPtrConstant(Elt1 / 2));
11213 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11214 DAG.getIntPtrConstant(i));
11218 // If Elt1 is defined, extract it from the appropriate source. If the
11219 // source byte is not also odd, shift the extracted word left 8 bits
11220 // otherwise clear the bottom 8 bits if we need to do an or.
11222 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11223 DAG.getIntPtrConstant(Elt1 / 2));
11224 if ((Elt1 & 1) == 0)
11225 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11227 TLI.getShiftAmountTy(InsElt.getValueType())));
11228 else if (Elt0 >= 0)
11229 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11230 DAG.getConstant(0xFF00, MVT::i16));
11232 // If Elt0 is defined, extract it from the appropriate source. If the
11233 // source byte is not also even, shift the extracted word right 8 bits. If
11234 // Elt1 was also defined, OR the extracted values together before
11235 // inserting them in the result.
11237 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11238 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11239 if ((Elt0 & 1) != 0)
11240 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11242 TLI.getShiftAmountTy(InsElt0.getValueType())));
11243 else if (Elt1 >= 0)
11244 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11245 DAG.getConstant(0x00FF, MVT::i16));
11246 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11249 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11250 DAG.getIntPtrConstant(i));
11252 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11255 // v32i8 shuffles - Translate to VPSHUFB if possible.
11257 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11258 const X86Subtarget *Subtarget,
11259 SelectionDAG &DAG) {
11260 MVT VT = SVOp->getSimpleValueType(0);
11261 SDValue V1 = SVOp->getOperand(0);
11262 SDValue V2 = SVOp->getOperand(1);
11264 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11266 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11267 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11268 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11270 // VPSHUFB may be generated if
11271 // (1) one of input vector is undefined or zeroinitializer.
11272 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11273 // And (2) the mask indexes don't cross the 128-bit lane.
11274 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11275 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11278 if (V1IsAllZero && !V2IsAllZero) {
11279 CommuteVectorShuffleMask(MaskVals, 32);
11282 return getPSHUFB(MaskVals, V1, dl, DAG);
11285 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11286 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11287 /// done when every pair / quad of shuffle mask elements point to elements in
11288 /// the right sequence. e.g.
11289 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11291 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11292 SelectionDAG &DAG) {
11293 MVT VT = SVOp->getSimpleValueType(0);
11295 unsigned NumElems = VT.getVectorNumElements();
11298 switch (VT.SimpleTy) {
11299 default: llvm_unreachable("Unexpected!");
11302 return SDValue(SVOp, 0);
11303 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11304 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11305 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11306 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11307 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11308 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11311 SmallVector<int, 8> MaskVec;
11312 for (unsigned i = 0; i != NumElems; i += Scale) {
11314 for (unsigned j = 0; j != Scale; ++j) {
11315 int EltIdx = SVOp->getMaskElt(i+j);
11319 StartIdx = (EltIdx / Scale);
11320 if (EltIdx != (int)(StartIdx*Scale + j))
11323 MaskVec.push_back(StartIdx);
11326 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11327 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11328 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11331 /// getVZextMovL - Return a zero-extending vector move low node.
11333 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11334 SDValue SrcOp, SelectionDAG &DAG,
11335 const X86Subtarget *Subtarget, SDLoc dl) {
11336 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11337 LoadSDNode *LD = nullptr;
11338 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11339 LD = dyn_cast<LoadSDNode>(SrcOp);
11341 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11343 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11344 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11345 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11346 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11347 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11349 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11350 return DAG.getNode(ISD::BITCAST, dl, VT,
11351 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11352 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11354 SrcOp.getOperand(0)
11360 return DAG.getNode(ISD::BITCAST, dl, VT,
11361 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11362 DAG.getNode(ISD::BITCAST, dl,
11366 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11367 /// which could not be matched by any known target speficic shuffle
11369 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11371 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11372 if (NewOp.getNode())
11375 MVT VT = SVOp->getSimpleValueType(0);
11377 unsigned NumElems = VT.getVectorNumElements();
11378 unsigned NumLaneElems = NumElems / 2;
11381 MVT EltVT = VT.getVectorElementType();
11382 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11385 SmallVector<int, 16> Mask;
11386 for (unsigned l = 0; l < 2; ++l) {
11387 // Build a shuffle mask for the output, discovering on the fly which
11388 // input vectors to use as shuffle operands (recorded in InputUsed).
11389 // If building a suitable shuffle vector proves too hard, then bail
11390 // out with UseBuildVector set.
11391 bool UseBuildVector = false;
11392 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11393 unsigned LaneStart = l * NumLaneElems;
11394 for (unsigned i = 0; i != NumLaneElems; ++i) {
11395 // The mask element. This indexes into the input.
11396 int Idx = SVOp->getMaskElt(i+LaneStart);
11398 // the mask element does not index into any input vector.
11399 Mask.push_back(-1);
11403 // The input vector this mask element indexes into.
11404 int Input = Idx / NumLaneElems;
11406 // Turn the index into an offset from the start of the input vector.
11407 Idx -= Input * NumLaneElems;
11409 // Find or create a shuffle vector operand to hold this input.
11411 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11412 if (InputUsed[OpNo] == Input)
11413 // This input vector is already an operand.
11415 if (InputUsed[OpNo] < 0) {
11416 // Create a new operand for this input vector.
11417 InputUsed[OpNo] = Input;
11422 if (OpNo >= array_lengthof(InputUsed)) {
11423 // More than two input vectors used! Give up on trying to create a
11424 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11425 UseBuildVector = true;
11429 // Add the mask index for the new shuffle vector.
11430 Mask.push_back(Idx + OpNo * NumLaneElems);
11433 if (UseBuildVector) {
11434 SmallVector<SDValue, 16> SVOps;
11435 for (unsigned i = 0; i != NumLaneElems; ++i) {
11436 // The mask element. This indexes into the input.
11437 int Idx = SVOp->getMaskElt(i+LaneStart);
11439 SVOps.push_back(DAG.getUNDEF(EltVT));
11443 // The input vector this mask element indexes into.
11444 int Input = Idx / NumElems;
11446 // Turn the index into an offset from the start of the input vector.
11447 Idx -= Input * NumElems;
11449 // Extract the vector element by hand.
11450 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11451 SVOp->getOperand(Input),
11452 DAG.getIntPtrConstant(Idx)));
11455 // Construct the output using a BUILD_VECTOR.
11456 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11457 } else if (InputUsed[0] < 0) {
11458 // No input vectors were used! The result is undefined.
11459 Output[l] = DAG.getUNDEF(NVT);
11461 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11462 (InputUsed[0] % 2) * NumLaneElems,
11464 // If only one input was used, use an undefined vector for the other.
11465 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11466 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11467 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11468 // At least one input vector was used. Create a new shuffle vector.
11469 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11475 // Concatenate the result back
11476 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11479 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11480 /// 4 elements, and match them with several different shuffle types.
11482 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11483 SDValue V1 = SVOp->getOperand(0);
11484 SDValue V2 = SVOp->getOperand(1);
11486 MVT VT = SVOp->getSimpleValueType(0);
11488 assert(VT.is128BitVector() && "Unsupported vector size");
11490 std::pair<int, int> Locs[4];
11491 int Mask1[] = { -1, -1, -1, -1 };
11492 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11494 unsigned NumHi = 0;
11495 unsigned NumLo = 0;
11496 for (unsigned i = 0; i != 4; ++i) {
11497 int Idx = PermMask[i];
11499 Locs[i] = std::make_pair(-1, -1);
11501 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11503 Locs[i] = std::make_pair(0, NumLo);
11504 Mask1[NumLo] = Idx;
11507 Locs[i] = std::make_pair(1, NumHi);
11509 Mask1[2+NumHi] = Idx;
11515 if (NumLo <= 2 && NumHi <= 2) {
11516 // If no more than two elements come from either vector. This can be
11517 // implemented with two shuffles. First shuffle gather the elements.
11518 // The second shuffle, which takes the first shuffle as both of its
11519 // vector operands, put the elements into the right order.
11520 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11522 int Mask2[] = { -1, -1, -1, -1 };
11524 for (unsigned i = 0; i != 4; ++i)
11525 if (Locs[i].first != -1) {
11526 unsigned Idx = (i < 2) ? 0 : 4;
11527 Idx += Locs[i].first * 2 + Locs[i].second;
11531 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11534 if (NumLo == 3 || NumHi == 3) {
11535 // Otherwise, we must have three elements from one vector, call it X, and
11536 // one element from the other, call it Y. First, use a shufps to build an
11537 // intermediate vector with the one element from Y and the element from X
11538 // that will be in the same half in the final destination (the indexes don't
11539 // matter). Then, use a shufps to build the final vector, taking the half
11540 // containing the element from Y from the intermediate, and the other half
11543 // Normalize it so the 3 elements come from V1.
11544 CommuteVectorShuffleMask(PermMask, 4);
11548 // Find the element from V2.
11550 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11551 int Val = PermMask[HiIndex];
11558 Mask1[0] = PermMask[HiIndex];
11560 Mask1[2] = PermMask[HiIndex^1];
11562 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11564 if (HiIndex >= 2) {
11565 Mask1[0] = PermMask[0];
11566 Mask1[1] = PermMask[1];
11567 Mask1[2] = HiIndex & 1 ? 6 : 4;
11568 Mask1[3] = HiIndex & 1 ? 4 : 6;
11569 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11572 Mask1[0] = HiIndex & 1 ? 2 : 0;
11573 Mask1[1] = HiIndex & 1 ? 0 : 2;
11574 Mask1[2] = PermMask[2];
11575 Mask1[3] = PermMask[3];
11580 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11583 // Break it into (shuffle shuffle_hi, shuffle_lo).
11584 int LoMask[] = { -1, -1, -1, -1 };
11585 int HiMask[] = { -1, -1, -1, -1 };
11587 int *MaskPtr = LoMask;
11588 unsigned MaskIdx = 0;
11589 unsigned LoIdx = 0;
11590 unsigned HiIdx = 2;
11591 for (unsigned i = 0; i != 4; ++i) {
11598 int Idx = PermMask[i];
11600 Locs[i] = std::make_pair(-1, -1);
11601 } else if (Idx < 4) {
11602 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11603 MaskPtr[LoIdx] = Idx;
11606 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11607 MaskPtr[HiIdx] = Idx;
11612 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11613 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11614 int MaskOps[] = { -1, -1, -1, -1 };
11615 for (unsigned i = 0; i != 4; ++i)
11616 if (Locs[i].first != -1)
11617 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11618 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11621 static bool MayFoldVectorLoad(SDValue V) {
11622 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11623 V = V.getOperand(0);
11625 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11626 V = V.getOperand(0);
11627 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11628 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11629 // BUILD_VECTOR (load), undef
11630 V = V.getOperand(0);
11632 return MayFoldLoad(V);
11636 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11637 MVT VT = Op.getSimpleValueType();
11639 // Canonizalize to v2f64.
11640 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11641 return DAG.getNode(ISD::BITCAST, dl, VT,
11642 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11647 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11649 SDValue V1 = Op.getOperand(0);
11650 SDValue V2 = Op.getOperand(1);
11651 MVT VT = Op.getSimpleValueType();
11653 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11655 if (HasSSE2 && VT == MVT::v2f64)
11656 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11658 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11659 return DAG.getNode(ISD::BITCAST, dl, VT,
11660 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11661 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11662 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11666 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11667 SDValue V1 = Op.getOperand(0);
11668 SDValue V2 = Op.getOperand(1);
11669 MVT VT = Op.getSimpleValueType();
11671 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11672 "unsupported shuffle type");
11674 if (V2.getOpcode() == ISD::UNDEF)
11678 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11682 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11683 SDValue V1 = Op.getOperand(0);
11684 SDValue V2 = Op.getOperand(1);
11685 MVT VT = Op.getSimpleValueType();
11686 unsigned NumElems = VT.getVectorNumElements();
11688 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11689 // operand of these instructions is only memory, so check if there's a
11690 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11692 bool CanFoldLoad = false;
11694 // Trivial case, when V2 comes from a load.
11695 if (MayFoldVectorLoad(V2))
11696 CanFoldLoad = true;
11698 // When V1 is a load, it can be folded later into a store in isel, example:
11699 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11701 // (MOVLPSmr addr:$src1, VR128:$src2)
11702 // So, recognize this potential and also use MOVLPS or MOVLPD
11703 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11704 CanFoldLoad = true;
11706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11708 if (HasSSE2 && NumElems == 2)
11709 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11712 // If we don't care about the second element, proceed to use movss.
11713 if (SVOp->getMaskElt(1) != -1)
11714 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11717 // movl and movlp will both match v2i64, but v2i64 is never matched by
11718 // movl earlier because we make it strict to avoid messing with the movlp load
11719 // folding logic (see the code above getMOVLP call). Match it here then,
11720 // this is horrible, but will stay like this until we move all shuffle
11721 // matching to x86 specific nodes. Note that for the 1st condition all
11722 // types are matched with movsd.
11724 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11725 // as to remove this logic from here, as much as possible
11726 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11727 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11728 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11731 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11733 // Invert the operand order and use SHUFPS to match it.
11734 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11735 getShuffleSHUFImmediate(SVOp), DAG);
11738 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11739 SelectionDAG &DAG) {
11741 MVT VT = Load->getSimpleValueType(0);
11742 MVT EVT = VT.getVectorElementType();
11743 SDValue Addr = Load->getOperand(1);
11744 SDValue NewAddr = DAG.getNode(
11745 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11746 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11749 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11750 DAG.getMachineFunction().getMachineMemOperand(
11751 Load->getMemOperand(), 0, EVT.getStoreSize()));
11755 // It is only safe to call this function if isINSERTPSMask is true for
11756 // this shufflevector mask.
11757 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11758 SelectionDAG &DAG) {
11759 // Generate an insertps instruction when inserting an f32 from memory onto a
11760 // v4f32 or when copying a member from one v4f32 to another.
11761 // We also use it for transferring i32 from one register to another,
11762 // since it simply copies the same bits.
11763 // If we're transferring an i32 from memory to a specific element in a
11764 // register, we output a generic DAG that will match the PINSRD
11766 MVT VT = SVOp->getSimpleValueType(0);
11767 MVT EVT = VT.getVectorElementType();
11768 SDValue V1 = SVOp->getOperand(0);
11769 SDValue V2 = SVOp->getOperand(1);
11770 auto Mask = SVOp->getMask();
11771 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11772 "unsupported vector type for insertps/pinsrd");
11774 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11775 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11776 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11780 unsigned DestIndex;
11784 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11787 // If we have 1 element from each vector, we have to check if we're
11788 // changing V1's element's place. If so, we're done. Otherwise, we
11789 // should assume we're changing V2's element's place and behave
11791 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11792 assert(DestIndex <= INT32_MAX && "truncated destination index");
11793 if (FromV1 == FromV2 &&
11794 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11798 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11801 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11802 "More than one element from V1 and from V2, or no elements from one "
11803 "of the vectors. This case should not have returned true from "
11808 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11811 // Get an index into the source vector in the range [0,4) (the mask is
11812 // in the range [0,8) because it can address V1 and V2)
11813 unsigned SrcIndex = Mask[DestIndex] % 4;
11814 if (MayFoldLoad(From)) {
11815 // Trivial case, when From comes from a load and is only used by the
11816 // shuffle. Make it use insertps from the vector that we need from that
11819 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11820 if (!NewLoad.getNode())
11823 if (EVT == MVT::f32) {
11824 // Create this as a scalar to vector to match the instruction pattern.
11825 SDValue LoadScalarToVector =
11826 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11827 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11828 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11830 } else { // EVT == MVT::i32
11831 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11832 // instruction, to match the PINSRD instruction, which loads an i32 to a
11833 // certain vector element.
11834 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11835 DAG.getConstant(DestIndex, MVT::i32));
11839 // Vector-element-to-vector
11840 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11841 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11844 // Reduce a vector shuffle to zext.
11845 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11846 SelectionDAG &DAG) {
11847 // PMOVZX is only available from SSE41.
11848 if (!Subtarget->hasSSE41())
11851 MVT VT = Op.getSimpleValueType();
11853 // Only AVX2 support 256-bit vector integer extending.
11854 if (!Subtarget->hasInt256() && VT.is256BitVector())
11857 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11859 SDValue V1 = Op.getOperand(0);
11860 SDValue V2 = Op.getOperand(1);
11861 unsigned NumElems = VT.getVectorNumElements();
11863 // Extending is an unary operation and the element type of the source vector
11864 // won't be equal to or larger than i64.
11865 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11866 VT.getVectorElementType() == MVT::i64)
11869 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11870 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11871 while ((1U << Shift) < NumElems) {
11872 if (SVOp->getMaskElt(1U << Shift) == 1)
11875 // The maximal ratio is 8, i.e. from i8 to i64.
11880 // Check the shuffle mask.
11881 unsigned Mask = (1U << Shift) - 1;
11882 for (unsigned i = 0; i != NumElems; ++i) {
11883 int EltIdx = SVOp->getMaskElt(i);
11884 if ((i & Mask) != 0 && EltIdx != -1)
11886 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11890 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11891 MVT NeVT = MVT::getIntegerVT(NBits);
11892 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11894 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11897 return DAG.getNode(ISD::BITCAST, DL, VT,
11898 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11901 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11902 SelectionDAG &DAG) {
11903 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11904 MVT VT = Op.getSimpleValueType();
11906 SDValue V1 = Op.getOperand(0);
11907 SDValue V2 = Op.getOperand(1);
11909 if (isZeroShuffle(SVOp))
11910 return getZeroVector(VT, Subtarget, DAG, dl);
11912 // Handle splat operations
11913 if (SVOp->isSplat()) {
11914 // Use vbroadcast whenever the splat comes from a foldable load
11915 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11916 if (Broadcast.getNode())
11920 // Check integer expanding shuffles.
11921 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11922 if (NewOp.getNode())
11925 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11927 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11928 VT == MVT::v32i8) {
11929 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11930 if (NewOp.getNode())
11931 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11932 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11933 // FIXME: Figure out a cleaner way to do this.
11934 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11935 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11936 if (NewOp.getNode()) {
11937 MVT NewVT = NewOp.getSimpleValueType();
11938 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11939 NewVT, true, false))
11940 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11943 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11944 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11945 if (NewOp.getNode()) {
11946 MVT NewVT = NewOp.getSimpleValueType();
11947 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11948 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11957 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11958 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11959 SDValue V1 = Op.getOperand(0);
11960 SDValue V2 = Op.getOperand(1);
11961 MVT VT = Op.getSimpleValueType();
11963 unsigned NumElems = VT.getVectorNumElements();
11964 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11965 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11966 bool V1IsSplat = false;
11967 bool V2IsSplat = false;
11968 bool HasSSE2 = Subtarget->hasSSE2();
11969 bool HasFp256 = Subtarget->hasFp256();
11970 bool HasInt256 = Subtarget->hasInt256();
11971 MachineFunction &MF = DAG.getMachineFunction();
11972 bool OptForSize = MF.getFunction()->getAttributes().
11973 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11975 // Check if we should use the experimental vector shuffle lowering. If so,
11976 // delegate completely to that code path.
11977 if (ExperimentalVectorShuffleLowering)
11978 return lowerVectorShuffle(Op, Subtarget, DAG);
11980 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11982 if (V1IsUndef && V2IsUndef)
11983 return DAG.getUNDEF(VT);
11985 // When we create a shuffle node we put the UNDEF node to second operand,
11986 // but in some cases the first operand may be transformed to UNDEF.
11987 // In this case we should just commute the node.
11989 return DAG.getCommutedVectorShuffle(*SVOp);
11991 // Vector shuffle lowering takes 3 steps:
11993 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11994 // narrowing and commutation of operands should be handled.
11995 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11997 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11998 // so the shuffle can be broken into other shuffles and the legalizer can
11999 // try the lowering again.
12001 // The general idea is that no vector_shuffle operation should be left to
12002 // be matched during isel, all of them must be converted to a target specific
12005 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12006 // narrowing and commutation of operands should be handled. The actual code
12007 // doesn't include all of those, work in progress...
12008 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12009 if (NewOp.getNode())
12012 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12014 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12015 // unpckh_undef). Only use pshufd if speed is more important than size.
12016 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12017 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12018 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12019 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12021 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12022 V2IsUndef && MayFoldVectorLoad(V1))
12023 return getMOVDDup(Op, dl, V1, DAG);
12025 if (isMOVHLPS_v_undef_Mask(M, VT))
12026 return getMOVHighToLow(Op, dl, DAG);
12028 // Use to match splats
12029 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12030 (VT == MVT::v2f64 || VT == MVT::v2i64))
12031 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12033 if (isPSHUFDMask(M, VT)) {
12034 // The actual implementation will match the mask in the if above and then
12035 // during isel it can match several different instructions, not only pshufd
12036 // as its name says, sad but true, emulate the behavior for now...
12037 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12038 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12040 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12042 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12043 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12045 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12046 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12049 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12053 if (isPALIGNRMask(M, VT, Subtarget))
12054 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12055 getShufflePALIGNRImmediate(SVOp),
12058 if (isVALIGNMask(M, VT, Subtarget))
12059 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12060 getShuffleVALIGNImmediate(SVOp),
12063 // Check if this can be converted into a logical shift.
12064 bool isLeft = false;
12065 unsigned ShAmt = 0;
12067 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12068 if (isShift && ShVal.hasOneUse()) {
12069 // If the shifted value has multiple uses, it may be cheaper to use
12070 // v_set0 + movlhps or movhlps, etc.
12071 MVT EltVT = VT.getVectorElementType();
12072 ShAmt *= EltVT.getSizeInBits();
12073 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12076 if (isMOVLMask(M, VT)) {
12077 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12078 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12079 if (!isMOVLPMask(M, VT)) {
12080 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12081 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12083 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12084 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12088 // FIXME: fold these into legal mask.
12089 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12090 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12092 if (isMOVHLPSMask(M, VT))
12093 return getMOVHighToLow(Op, dl, DAG);
12095 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12096 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12098 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12099 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12101 if (isMOVLPMask(M, VT))
12102 return getMOVLP(Op, dl, DAG, HasSSE2);
12104 if (ShouldXformToMOVHLPS(M, VT) ||
12105 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12106 return DAG.getCommutedVectorShuffle(*SVOp);
12109 // No better options. Use a vshldq / vsrldq.
12110 MVT EltVT = VT.getVectorElementType();
12111 ShAmt *= EltVT.getSizeInBits();
12112 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12115 bool Commuted = false;
12116 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12117 // 1,1,1,1 -> v8i16 though.
12118 BitVector UndefElements;
12119 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12120 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12122 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12123 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12126 // Canonicalize the splat or undef, if present, to be on the RHS.
12127 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12128 CommuteVectorShuffleMask(M, NumElems);
12130 std::swap(V1IsSplat, V2IsSplat);
12134 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12135 // Shuffling low element of v1 into undef, just return v1.
12138 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12139 // the instruction selector will not match, so get a canonical MOVL with
12140 // swapped operands to undo the commute.
12141 return getMOVL(DAG, dl, VT, V2, V1);
12144 if (isUNPCKLMask(M, VT, HasInt256))
12145 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12147 if (isUNPCKHMask(M, VT, HasInt256))
12148 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12151 // Normalize mask so all entries that point to V2 points to its first
12152 // element then try to match unpck{h|l} again. If match, return a
12153 // new vector_shuffle with the corrected mask.p
12154 SmallVector<int, 8> NewMask(M.begin(), M.end());
12155 NormalizeMask(NewMask, NumElems);
12156 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12157 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12158 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12159 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12163 // Commute is back and try unpck* again.
12164 // FIXME: this seems wrong.
12165 CommuteVectorShuffleMask(M, NumElems);
12167 std::swap(V1IsSplat, V2IsSplat);
12169 if (isUNPCKLMask(M, VT, HasInt256))
12170 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12172 if (isUNPCKHMask(M, VT, HasInt256))
12173 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12176 // Normalize the node to match x86 shuffle ops if needed
12177 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12178 return DAG.getCommutedVectorShuffle(*SVOp);
12180 // The checks below are all present in isShuffleMaskLegal, but they are
12181 // inlined here right now to enable us to directly emit target specific
12182 // nodes, and remove one by one until they don't return Op anymore.
12184 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12185 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12186 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12187 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12190 if (isPSHUFHWMask(M, VT, HasInt256))
12191 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12192 getShufflePSHUFHWImmediate(SVOp),
12195 if (isPSHUFLWMask(M, VT, HasInt256))
12196 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12197 getShufflePSHUFLWImmediate(SVOp),
12200 unsigned MaskValue;
12201 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12203 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12205 if (isSHUFPMask(M, VT))
12206 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12207 getShuffleSHUFImmediate(SVOp), DAG);
12209 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12210 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12211 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12212 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12214 //===--------------------------------------------------------------------===//
12215 // Generate target specific nodes for 128 or 256-bit shuffles only
12216 // supported in the AVX instruction set.
12219 // Handle VMOVDDUPY permutations
12220 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12221 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12223 // Handle VPERMILPS/D* permutations
12224 if (isVPERMILPMask(M, VT)) {
12225 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12226 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12227 getShuffleSHUFImmediate(SVOp), DAG);
12228 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12229 getShuffleSHUFImmediate(SVOp), DAG);
12233 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12234 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12235 Idx*(NumElems/2), DAG, dl);
12237 // Handle VPERM2F128/VPERM2I128 permutations
12238 if (isVPERM2X128Mask(M, VT, HasFp256))
12239 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12240 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12242 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12243 return getINSERTPS(SVOp, dl, DAG);
12246 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12247 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12249 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12250 VT.is512BitVector()) {
12251 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12252 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12253 SmallVector<SDValue, 16> permclMask;
12254 for (unsigned i = 0; i != NumElems; ++i) {
12255 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12258 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12260 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12261 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12262 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12263 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12264 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12267 //===--------------------------------------------------------------------===//
12268 // Since no target specific shuffle was selected for this generic one,
12269 // lower it into other known shuffles. FIXME: this isn't true yet, but
12270 // this is the plan.
12273 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12274 if (VT == MVT::v8i16) {
12275 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12276 if (NewOp.getNode())
12280 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12281 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12282 if (NewOp.getNode())
12286 if (VT == MVT::v16i8) {
12287 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12288 if (NewOp.getNode())
12292 if (VT == MVT::v32i8) {
12293 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12294 if (NewOp.getNode())
12298 // Handle all 128-bit wide vectors with 4 elements, and match them with
12299 // several different shuffle types.
12300 if (NumElems == 4 && VT.is128BitVector())
12301 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12303 // Handle general 256-bit shuffles
12304 if (VT.is256BitVector())
12305 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12310 // This function assumes its argument is a BUILD_VECTOR of constants or
12311 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12313 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12314 unsigned &MaskValue) {
12316 unsigned NumElems = BuildVector->getNumOperands();
12317 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12318 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12319 unsigned NumElemsInLane = NumElems / NumLanes;
12321 // Blend for v16i16 should be symetric for the both lanes.
12322 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12323 SDValue EltCond = BuildVector->getOperand(i);
12324 SDValue SndLaneEltCond =
12325 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12327 int Lane1Cond = -1, Lane2Cond = -1;
12328 if (isa<ConstantSDNode>(EltCond))
12329 Lane1Cond = !isZero(EltCond);
12330 if (isa<ConstantSDNode>(SndLaneEltCond))
12331 Lane2Cond = !isZero(SndLaneEltCond);
12333 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12334 // Lane1Cond != 0, means we want the first argument.
12335 // Lane1Cond == 0, means we want the second argument.
12336 // The encoding of this argument is 0 for the first argument, 1
12337 // for the second. Therefore, invert the condition.
12338 MaskValue |= !Lane1Cond << i;
12339 else if (Lane1Cond < 0)
12340 MaskValue |= !Lane2Cond << i;
12347 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12349 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12350 SelectionDAG &DAG) {
12351 SDValue Cond = Op.getOperand(0);
12352 SDValue LHS = Op.getOperand(1);
12353 SDValue RHS = Op.getOperand(2);
12355 MVT VT = Op.getSimpleValueType();
12356 MVT EltVT = VT.getVectorElementType();
12357 unsigned NumElems = VT.getVectorNumElements();
12359 // There is no blend with immediate in AVX-512.
12360 if (VT.is512BitVector())
12363 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12365 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12368 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12371 // Check the mask for BLEND and build the value.
12372 unsigned MaskValue = 0;
12373 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12376 // Convert i32 vectors to floating point if it is not AVX2.
12377 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12379 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12380 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12382 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12383 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12386 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12387 DAG.getConstant(MaskValue, MVT::i32));
12388 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12391 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12392 // A vselect where all conditions and data are constants can be optimized into
12393 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12394 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12395 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12396 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12399 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12400 if (BlendOp.getNode())
12403 // Some types for vselect were previously set to Expand, not Legal or
12404 // Custom. Return an empty SDValue so we fall-through to Expand, after
12405 // the Custom lowering phase.
12406 MVT VT = Op.getSimpleValueType();
12407 switch (VT.SimpleTy) {
12412 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12417 // We couldn't create a "Blend with immediate" node.
12418 // This node should still be legal, but we'll have to emit a blendv*
12423 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12424 MVT VT = Op.getSimpleValueType();
12427 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12430 if (VT.getSizeInBits() == 8) {
12431 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12432 Op.getOperand(0), Op.getOperand(1));
12433 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12434 DAG.getValueType(VT));
12435 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12438 if (VT.getSizeInBits() == 16) {
12439 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12440 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12442 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12443 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12444 DAG.getNode(ISD::BITCAST, dl,
12447 Op.getOperand(1)));
12448 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12449 Op.getOperand(0), Op.getOperand(1));
12450 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12451 DAG.getValueType(VT));
12452 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12455 if (VT == MVT::f32) {
12456 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12457 // the result back to FR32 register. It's only worth matching if the
12458 // result has a single use which is a store or a bitcast to i32. And in
12459 // the case of a store, it's not worth it if the index is a constant 0,
12460 // because a MOVSSmr can be used instead, which is smaller and faster.
12461 if (!Op.hasOneUse())
12463 SDNode *User = *Op.getNode()->use_begin();
12464 if ((User->getOpcode() != ISD::STORE ||
12465 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12466 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12467 (User->getOpcode() != ISD::BITCAST ||
12468 User->getValueType(0) != MVT::i32))
12470 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12471 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12474 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12477 if (VT == MVT::i32 || VT == MVT::i64) {
12478 // ExtractPS/pextrq works with constant index.
12479 if (isa<ConstantSDNode>(Op.getOperand(1)))
12485 /// Extract one bit from mask vector, like v16i1 or v8i1.
12486 /// AVX-512 feature.
12488 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12489 SDValue Vec = Op.getOperand(0);
12491 MVT VecVT = Vec.getSimpleValueType();
12492 SDValue Idx = Op.getOperand(1);
12493 MVT EltVT = Op.getSimpleValueType();
12495 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12497 // variable index can't be handled in mask registers,
12498 // extend vector to VR512
12499 if (!isa<ConstantSDNode>(Idx)) {
12500 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12501 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12502 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12503 ExtVT.getVectorElementType(), Ext, Idx);
12504 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12507 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12508 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12509 unsigned MaxSift = rc->getSize()*8 - 1;
12510 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12511 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12512 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12513 DAG.getConstant(MaxSift, MVT::i8));
12514 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12515 DAG.getIntPtrConstant(0));
12519 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12520 SelectionDAG &DAG) const {
12522 SDValue Vec = Op.getOperand(0);
12523 MVT VecVT = Vec.getSimpleValueType();
12524 SDValue Idx = Op.getOperand(1);
12526 if (Op.getSimpleValueType() == MVT::i1)
12527 return ExtractBitFromMaskVector(Op, DAG);
12529 if (!isa<ConstantSDNode>(Idx)) {
12530 if (VecVT.is512BitVector() ||
12531 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12532 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12535 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12536 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12537 MaskEltVT.getSizeInBits());
12539 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12540 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12541 getZeroVector(MaskVT, Subtarget, DAG, dl),
12542 Idx, DAG.getConstant(0, getPointerTy()));
12543 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12544 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12545 Perm, DAG.getConstant(0, getPointerTy()));
12550 // If this is a 256-bit vector result, first extract the 128-bit vector and
12551 // then extract the element from the 128-bit vector.
12552 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12554 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12555 // Get the 128-bit vector.
12556 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12557 MVT EltVT = VecVT.getVectorElementType();
12559 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12561 //if (IdxVal >= NumElems/2)
12562 // IdxVal -= NumElems/2;
12563 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12564 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12565 DAG.getConstant(IdxVal, MVT::i32));
12568 assert(VecVT.is128BitVector() && "Unexpected vector length");
12570 if (Subtarget->hasSSE41()) {
12571 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12576 MVT VT = Op.getSimpleValueType();
12577 // TODO: handle v16i8.
12578 if (VT.getSizeInBits() == 16) {
12579 SDValue Vec = Op.getOperand(0);
12580 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12582 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12584 DAG.getNode(ISD::BITCAST, dl,
12586 Op.getOperand(1)));
12587 // Transform it so it match pextrw which produces a 32-bit result.
12588 MVT EltVT = MVT::i32;
12589 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12590 Op.getOperand(0), Op.getOperand(1));
12591 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12592 DAG.getValueType(VT));
12593 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12596 if (VT.getSizeInBits() == 32) {
12597 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12601 // SHUFPS the element to the lowest double word, then movss.
12602 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12603 MVT VVT = Op.getOperand(0).getSimpleValueType();
12604 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12605 DAG.getUNDEF(VVT), Mask);
12606 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12607 DAG.getIntPtrConstant(0));
12610 if (VT.getSizeInBits() == 64) {
12611 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12612 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12613 // to match extract_elt for f64.
12614 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12618 // UNPCKHPD the element to the lowest double word, then movsd.
12619 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12620 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12621 int Mask[2] = { 1, -1 };
12622 MVT VVT = Op.getOperand(0).getSimpleValueType();
12623 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12624 DAG.getUNDEF(VVT), Mask);
12625 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12626 DAG.getIntPtrConstant(0));
12632 /// Insert one bit to mask vector, like v16i1 or v8i1.
12633 /// AVX-512 feature.
12635 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12637 SDValue Vec = Op.getOperand(0);
12638 SDValue Elt = Op.getOperand(1);
12639 SDValue Idx = Op.getOperand(2);
12640 MVT VecVT = Vec.getSimpleValueType();
12642 if (!isa<ConstantSDNode>(Idx)) {
12643 // Non constant index. Extend source and destination,
12644 // insert element and then truncate the result.
12645 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12646 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12647 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12648 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12649 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12650 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12653 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12654 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12655 if (Vec.getOpcode() == ISD::UNDEF)
12656 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12657 DAG.getConstant(IdxVal, MVT::i8));
12658 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12659 unsigned MaxSift = rc->getSize()*8 - 1;
12660 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12661 DAG.getConstant(MaxSift, MVT::i8));
12662 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12663 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12664 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12667 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12668 SelectionDAG &DAG) const {
12669 MVT VT = Op.getSimpleValueType();
12670 MVT EltVT = VT.getVectorElementType();
12672 if (EltVT == MVT::i1)
12673 return InsertBitToMaskVector(Op, DAG);
12676 SDValue N0 = Op.getOperand(0);
12677 SDValue N1 = Op.getOperand(1);
12678 SDValue N2 = Op.getOperand(2);
12679 if (!isa<ConstantSDNode>(N2))
12681 auto *N2C = cast<ConstantSDNode>(N2);
12682 unsigned IdxVal = N2C->getZExtValue();
12684 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12685 // into that, and then insert the subvector back into the result.
12686 if (VT.is256BitVector() || VT.is512BitVector()) {
12687 // Get the desired 128-bit vector half.
12688 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12690 // Insert the element into the desired half.
12691 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12692 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12694 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12695 DAG.getConstant(IdxIn128, MVT::i32));
12697 // Insert the changed part back to the 256-bit vector
12698 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12700 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12702 if (Subtarget->hasSSE41()) {
12703 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12705 if (VT == MVT::v8i16) {
12706 Opc = X86ISD::PINSRW;
12708 assert(VT == MVT::v16i8);
12709 Opc = X86ISD::PINSRB;
12712 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12714 if (N1.getValueType() != MVT::i32)
12715 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12716 if (N2.getValueType() != MVT::i32)
12717 N2 = DAG.getIntPtrConstant(IdxVal);
12718 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12721 if (EltVT == MVT::f32) {
12722 // Bits [7:6] of the constant are the source select. This will always be
12723 // zero here. The DAG Combiner may combine an extract_elt index into
12725 // bits. For example (insert (extract, 3), 2) could be matched by
12727 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12728 // Bits [5:4] of the constant are the destination select. This is the
12729 // value of the incoming immediate.
12730 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12731 // combine either bitwise AND or insert of float 0.0 to set these bits.
12732 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12733 // Create this as a scalar to vector..
12734 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12735 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12738 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12739 // PINSR* works with constant index.
12744 if (EltVT == MVT::i8)
12747 if (EltVT.getSizeInBits() == 16) {
12748 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12749 // as its second argument.
12750 if (N1.getValueType() != MVT::i32)
12751 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12752 if (N2.getValueType() != MVT::i32)
12753 N2 = DAG.getIntPtrConstant(IdxVal);
12754 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12759 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12761 MVT OpVT = Op.getSimpleValueType();
12763 // If this is a 256-bit vector result, first insert into a 128-bit
12764 // vector and then insert into the 256-bit vector.
12765 if (!OpVT.is128BitVector()) {
12766 // Insert into a 128-bit vector.
12767 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12768 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12769 OpVT.getVectorNumElements() / SizeFactor);
12771 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12773 // Insert the 128-bit vector.
12774 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12777 if (OpVT == MVT::v1i64 &&
12778 Op.getOperand(0).getValueType() == MVT::i64)
12779 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12781 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12782 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12783 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12784 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12787 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12788 // a simple subregister reference or explicit instructions to grab
12789 // upper bits of a vector.
12790 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12791 SelectionDAG &DAG) {
12793 SDValue In = Op.getOperand(0);
12794 SDValue Idx = Op.getOperand(1);
12795 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12796 MVT ResVT = Op.getSimpleValueType();
12797 MVT InVT = In.getSimpleValueType();
12799 if (Subtarget->hasFp256()) {
12800 if (ResVT.is128BitVector() &&
12801 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12802 isa<ConstantSDNode>(Idx)) {
12803 return Extract128BitVector(In, IdxVal, DAG, dl);
12805 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12806 isa<ConstantSDNode>(Idx)) {
12807 return Extract256BitVector(In, IdxVal, DAG, dl);
12813 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12814 // simple superregister reference or explicit instructions to insert
12815 // the upper bits of a vector.
12816 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12817 SelectionDAG &DAG) {
12818 if (Subtarget->hasFp256()) {
12819 SDLoc dl(Op.getNode());
12820 SDValue Vec = Op.getNode()->getOperand(0);
12821 SDValue SubVec = Op.getNode()->getOperand(1);
12822 SDValue Idx = Op.getNode()->getOperand(2);
12824 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12825 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12826 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12827 isa<ConstantSDNode>(Idx)) {
12828 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12829 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12832 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12833 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12834 isa<ConstantSDNode>(Idx)) {
12835 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12836 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12842 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12843 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12844 // one of the above mentioned nodes. It has to be wrapped because otherwise
12845 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12846 // be used to form addressing mode. These wrapped nodes will be selected
12849 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12850 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12852 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12853 // global base reg.
12854 unsigned char OpFlag = 0;
12855 unsigned WrapperKind = X86ISD::Wrapper;
12856 CodeModel::Model M = DAG.getTarget().getCodeModel();
12858 if (Subtarget->isPICStyleRIPRel() &&
12859 (M == CodeModel::Small || M == CodeModel::Kernel))
12860 WrapperKind = X86ISD::WrapperRIP;
12861 else if (Subtarget->isPICStyleGOT())
12862 OpFlag = X86II::MO_GOTOFF;
12863 else if (Subtarget->isPICStyleStubPIC())
12864 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12866 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12867 CP->getAlignment(),
12868 CP->getOffset(), OpFlag);
12870 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12871 // With PIC, the address is actually $g + Offset.
12873 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12874 DAG.getNode(X86ISD::GlobalBaseReg,
12875 SDLoc(), getPointerTy()),
12882 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12883 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12885 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12886 // global base reg.
12887 unsigned char OpFlag = 0;
12888 unsigned WrapperKind = X86ISD::Wrapper;
12889 CodeModel::Model M = DAG.getTarget().getCodeModel();
12891 if (Subtarget->isPICStyleRIPRel() &&
12892 (M == CodeModel::Small || M == CodeModel::Kernel))
12893 WrapperKind = X86ISD::WrapperRIP;
12894 else if (Subtarget->isPICStyleGOT())
12895 OpFlag = X86II::MO_GOTOFF;
12896 else if (Subtarget->isPICStyleStubPIC())
12897 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12899 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12902 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12904 // With PIC, the address is actually $g + Offset.
12906 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12907 DAG.getNode(X86ISD::GlobalBaseReg,
12908 SDLoc(), getPointerTy()),
12915 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12916 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12918 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12919 // global base reg.
12920 unsigned char OpFlag = 0;
12921 unsigned WrapperKind = X86ISD::Wrapper;
12922 CodeModel::Model M = DAG.getTarget().getCodeModel();
12924 if (Subtarget->isPICStyleRIPRel() &&
12925 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12926 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12927 OpFlag = X86II::MO_GOTPCREL;
12928 WrapperKind = X86ISD::WrapperRIP;
12929 } else if (Subtarget->isPICStyleGOT()) {
12930 OpFlag = X86II::MO_GOT;
12931 } else if (Subtarget->isPICStyleStubPIC()) {
12932 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12933 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12934 OpFlag = X86II::MO_DARWIN_NONLAZY;
12937 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12940 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12942 // With PIC, the address is actually $g + Offset.
12943 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12944 !Subtarget->is64Bit()) {
12945 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12946 DAG.getNode(X86ISD::GlobalBaseReg,
12947 SDLoc(), getPointerTy()),
12951 // For symbols that require a load from a stub to get the address, emit the
12953 if (isGlobalStubReference(OpFlag))
12954 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12955 MachinePointerInfo::getGOT(), false, false, false, 0);
12961 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12962 // Create the TargetBlockAddressAddress node.
12963 unsigned char OpFlags =
12964 Subtarget->ClassifyBlockAddressReference();
12965 CodeModel::Model M = DAG.getTarget().getCodeModel();
12966 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12967 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12969 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12972 if (Subtarget->isPICStyleRIPRel() &&
12973 (M == CodeModel::Small || M == CodeModel::Kernel))
12974 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12976 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12978 // With PIC, the address is actually $g + Offset.
12979 if (isGlobalRelativeToPICBase(OpFlags)) {
12980 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12981 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12989 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12990 int64_t Offset, SelectionDAG &DAG) const {
12991 // Create the TargetGlobalAddress node, folding in the constant
12992 // offset if it is legal.
12993 unsigned char OpFlags =
12994 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12995 CodeModel::Model M = DAG.getTarget().getCodeModel();
12997 if (OpFlags == X86II::MO_NO_FLAG &&
12998 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12999 // A direct static reference to a global.
13000 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13003 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13006 if (Subtarget->isPICStyleRIPRel() &&
13007 (M == CodeModel::Small || M == CodeModel::Kernel))
13008 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13010 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13012 // With PIC, the address is actually $g + Offset.
13013 if (isGlobalRelativeToPICBase(OpFlags)) {
13014 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13015 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13019 // For globals that require a load from a stub to get the address, emit the
13021 if (isGlobalStubReference(OpFlags))
13022 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13023 MachinePointerInfo::getGOT(), false, false, false, 0);
13025 // If there was a non-zero offset that we didn't fold, create an explicit
13026 // addition for it.
13028 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13029 DAG.getConstant(Offset, getPointerTy()));
13035 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13036 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13037 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13038 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13042 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13043 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13044 unsigned char OperandFlags, bool LocalDynamic = false) {
13045 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13046 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13048 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13049 GA->getValueType(0),
13053 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13057 SDValue Ops[] = { Chain, TGA, *InFlag };
13058 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13060 SDValue Ops[] = { Chain, TGA };
13061 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13064 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13065 MFI->setAdjustsStack(true);
13066 MFI->setHasCalls(true);
13068 SDValue Flag = Chain.getValue(1);
13069 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13072 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13074 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13077 SDLoc dl(GA); // ? function entry point might be better
13078 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13079 DAG.getNode(X86ISD::GlobalBaseReg,
13080 SDLoc(), PtrVT), InFlag);
13081 InFlag = Chain.getValue(1);
13083 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13086 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13088 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13090 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13091 X86::RAX, X86II::MO_TLSGD);
13094 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13100 // Get the start address of the TLS block for this module.
13101 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13102 .getInfo<X86MachineFunctionInfo>();
13103 MFI->incNumLocalDynamicTLSAccesses();
13107 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13108 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13111 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13112 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13113 InFlag = Chain.getValue(1);
13114 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13115 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13118 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13122 unsigned char OperandFlags = X86II::MO_DTPOFF;
13123 unsigned WrapperKind = X86ISD::Wrapper;
13124 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13125 GA->getValueType(0),
13126 GA->getOffset(), OperandFlags);
13127 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13129 // Add x@dtpoff with the base.
13130 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13133 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13134 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13135 const EVT PtrVT, TLSModel::Model model,
13136 bool is64Bit, bool isPIC) {
13139 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13140 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13141 is64Bit ? 257 : 256));
13143 SDValue ThreadPointer =
13144 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13145 MachinePointerInfo(Ptr), false, false, false, 0);
13147 unsigned char OperandFlags = 0;
13148 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13150 unsigned WrapperKind = X86ISD::Wrapper;
13151 if (model == TLSModel::LocalExec) {
13152 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13153 } else if (model == TLSModel::InitialExec) {
13155 OperandFlags = X86II::MO_GOTTPOFF;
13156 WrapperKind = X86ISD::WrapperRIP;
13158 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13161 llvm_unreachable("Unexpected model");
13164 // emit "addl x@ntpoff,%eax" (local exec)
13165 // or "addl x@indntpoff,%eax" (initial exec)
13166 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13168 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13169 GA->getOffset(), OperandFlags);
13170 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13172 if (model == TLSModel::InitialExec) {
13173 if (isPIC && !is64Bit) {
13174 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13175 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13179 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13180 MachinePointerInfo::getGOT(), false, false, false, 0);
13183 // The address of the thread local variable is the add of the thread
13184 // pointer with the offset of the variable.
13185 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13189 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13191 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13192 const GlobalValue *GV = GA->getGlobal();
13194 if (Subtarget->isTargetELF()) {
13195 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13198 case TLSModel::GeneralDynamic:
13199 if (Subtarget->is64Bit())
13200 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13201 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13202 case TLSModel::LocalDynamic:
13203 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13204 Subtarget->is64Bit());
13205 case TLSModel::InitialExec:
13206 case TLSModel::LocalExec:
13207 return LowerToTLSExecModel(
13208 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13209 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13211 llvm_unreachable("Unknown TLS model.");
13214 if (Subtarget->isTargetDarwin()) {
13215 // Darwin only has one model of TLS. Lower to that.
13216 unsigned char OpFlag = 0;
13217 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13218 X86ISD::WrapperRIP : X86ISD::Wrapper;
13220 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13221 // global base reg.
13222 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13223 !Subtarget->is64Bit();
13225 OpFlag = X86II::MO_TLVP_PIC_BASE;
13227 OpFlag = X86II::MO_TLVP;
13229 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13230 GA->getValueType(0),
13231 GA->getOffset(), OpFlag);
13232 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13234 // With PIC32, the address is actually $g + Offset.
13236 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13237 DAG.getNode(X86ISD::GlobalBaseReg,
13238 SDLoc(), getPointerTy()),
13241 // Lowering the machine isd will make sure everything is in the right
13243 SDValue Chain = DAG.getEntryNode();
13244 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13245 SDValue Args[] = { Chain, Offset };
13246 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13248 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13249 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13250 MFI->setAdjustsStack(true);
13252 // And our return value (tls address) is in the standard call return value
13254 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13255 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13256 Chain.getValue(1));
13259 if (Subtarget->isTargetKnownWindowsMSVC() ||
13260 Subtarget->isTargetWindowsGNU()) {
13261 // Just use the implicit TLS architecture
13262 // Need to generate someting similar to:
13263 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13265 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13266 // mov rcx, qword [rdx+rcx*8]
13267 // mov eax, .tls$:tlsvar
13268 // [rax+rcx] contains the address
13269 // Windows 64bit: gs:0x58
13270 // Windows 32bit: fs:__tls_array
13273 SDValue Chain = DAG.getEntryNode();
13275 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13276 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13277 // use its literal value of 0x2C.
13278 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13279 ? Type::getInt8PtrTy(*DAG.getContext(),
13281 : Type::getInt32PtrTy(*DAG.getContext(),
13285 Subtarget->is64Bit()
13286 ? DAG.getIntPtrConstant(0x58)
13287 : (Subtarget->isTargetWindowsGNU()
13288 ? DAG.getIntPtrConstant(0x2C)
13289 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13291 SDValue ThreadPointer =
13292 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13293 MachinePointerInfo(Ptr), false, false, false, 0);
13295 // Load the _tls_index variable
13296 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13297 if (Subtarget->is64Bit())
13298 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13299 IDX, MachinePointerInfo(), MVT::i32,
13300 false, false, false, 0);
13302 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13303 false, false, false, 0);
13305 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13307 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13309 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13310 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13311 false, false, false, 0);
13313 // Get the offset of start of .tls section
13314 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13315 GA->getValueType(0),
13316 GA->getOffset(), X86II::MO_SECREL);
13317 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13319 // The address of the thread local variable is the add of the thread
13320 // pointer with the offset of the variable.
13321 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13324 llvm_unreachable("TLS not implemented for this target.");
13327 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13328 /// and take a 2 x i32 value to shift plus a shift amount.
13329 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13330 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13331 MVT VT = Op.getSimpleValueType();
13332 unsigned VTBits = VT.getSizeInBits();
13334 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13335 SDValue ShOpLo = Op.getOperand(0);
13336 SDValue ShOpHi = Op.getOperand(1);
13337 SDValue ShAmt = Op.getOperand(2);
13338 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13339 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13341 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13342 DAG.getConstant(VTBits - 1, MVT::i8));
13343 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13344 DAG.getConstant(VTBits - 1, MVT::i8))
13345 : DAG.getConstant(0, VT);
13347 SDValue Tmp2, Tmp3;
13348 if (Op.getOpcode() == ISD::SHL_PARTS) {
13349 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13350 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13352 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13353 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13356 // If the shift amount is larger or equal than the width of a part we can't
13357 // rely on the results of shld/shrd. Insert a test and select the appropriate
13358 // values for large shift amounts.
13359 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13360 DAG.getConstant(VTBits, MVT::i8));
13361 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13362 AndNode, DAG.getConstant(0, MVT::i8));
13365 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13366 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13367 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13369 if (Op.getOpcode() == ISD::SHL_PARTS) {
13370 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13371 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13373 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13374 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13377 SDValue Ops[2] = { Lo, Hi };
13378 return DAG.getMergeValues(Ops, dl);
13381 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13382 SelectionDAG &DAG) const {
13383 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13386 if (SrcVT.isVector()) {
13387 if (SrcVT.getVectorElementType() == MVT::i1) {
13388 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13389 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13390 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13391 Op.getOperand(0)));
13396 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13397 "Unknown SINT_TO_FP to lower!");
13399 // These are really Legal; return the operand so the caller accepts it as
13401 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13403 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13404 Subtarget->is64Bit()) {
13408 unsigned Size = SrcVT.getSizeInBits()/8;
13409 MachineFunction &MF = DAG.getMachineFunction();
13410 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13411 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13412 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13414 MachinePointerInfo::getFixedStack(SSFI),
13416 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13419 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13421 SelectionDAG &DAG) const {
13425 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13427 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13429 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13431 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13433 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13434 MachineMemOperand *MMO;
13436 int SSFI = FI->getIndex();
13438 DAG.getMachineFunction()
13439 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13440 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13442 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13443 StackSlot = StackSlot.getOperand(1);
13445 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13446 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13448 Tys, Ops, SrcVT, MMO);
13451 Chain = Result.getValue(1);
13452 SDValue InFlag = Result.getValue(2);
13454 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13455 // shouldn't be necessary except that RFP cannot be live across
13456 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13457 MachineFunction &MF = DAG.getMachineFunction();
13458 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13459 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13460 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13461 Tys = DAG.getVTList(MVT::Other);
13463 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13465 MachineMemOperand *MMO =
13466 DAG.getMachineFunction()
13467 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13468 MachineMemOperand::MOStore, SSFISize, SSFISize);
13470 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13471 Ops, Op.getValueType(), MMO);
13472 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13473 MachinePointerInfo::getFixedStack(SSFI),
13474 false, false, false, 0);
13480 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13481 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13482 SelectionDAG &DAG) const {
13483 // This algorithm is not obvious. Here it is what we're trying to output:
13486 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13487 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13489 haddpd %xmm0, %xmm0
13491 pshufd $0x4e, %xmm0, %xmm1
13497 LLVMContext *Context = DAG.getContext();
13499 // Build some magic constants.
13500 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13501 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13502 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13504 SmallVector<Constant*,2> CV1;
13506 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13507 APInt(64, 0x4330000000000000ULL))));
13509 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13510 APInt(64, 0x4530000000000000ULL))));
13511 Constant *C1 = ConstantVector::get(CV1);
13512 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13514 // Load the 64-bit value into an XMM register.
13515 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13517 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13518 MachinePointerInfo::getConstantPool(),
13519 false, false, false, 16);
13520 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13521 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13524 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13525 MachinePointerInfo::getConstantPool(),
13526 false, false, false, 16);
13527 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13528 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13531 if (Subtarget->hasSSE3()) {
13532 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13533 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13535 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13536 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13538 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13539 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13543 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13544 DAG.getIntPtrConstant(0));
13547 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13548 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13549 SelectionDAG &DAG) const {
13551 // FP constant to bias correct the final result.
13552 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13555 // Load the 32-bit value into an XMM register.
13556 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13559 // Zero out the upper parts of the register.
13560 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13562 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13563 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13564 DAG.getIntPtrConstant(0));
13566 // Or the load with the bias.
13567 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13568 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13569 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13570 MVT::v2f64, Load)),
13571 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13572 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13573 MVT::v2f64, Bias)));
13574 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13575 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13576 DAG.getIntPtrConstant(0));
13578 // Subtract the bias.
13579 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13581 // Handle final rounding.
13582 EVT DestVT = Op.getValueType();
13584 if (DestVT.bitsLT(MVT::f64))
13585 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13586 DAG.getIntPtrConstant(0));
13587 if (DestVT.bitsGT(MVT::f64))
13588 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13590 // Handle final rounding.
13594 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13595 const X86Subtarget &Subtarget) {
13596 // The algorithm is the following:
13597 // #ifdef __SSE4_1__
13598 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13599 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13600 // (uint4) 0x53000000, 0xaa);
13602 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13603 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13605 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13606 // return (float4) lo + fhi;
13609 SDValue V = Op->getOperand(0);
13610 EVT VecIntVT = V.getValueType();
13611 bool Is128 = VecIntVT == MVT::v4i32;
13612 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13613 unsigned NumElts = VecIntVT.getVectorNumElements();
13614 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13615 "Unsupported custom type");
13616 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13618 // In the #idef/#else code, we have in common:
13619 // - The vector of constants:
13625 // Create the splat vector for 0x4b000000.
13626 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13627 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13628 CstLow, CstLow, CstLow, CstLow};
13629 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13630 makeArrayRef(&CstLowArray[0], NumElts));
13631 // Create the splat vector for 0x53000000.
13632 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13633 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13634 CstHigh, CstHigh, CstHigh, CstHigh};
13635 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13636 makeArrayRef(&CstHighArray[0], NumElts));
13638 // Create the right shift.
13639 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13640 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13641 CstShift, CstShift, CstShift, CstShift};
13642 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13643 makeArrayRef(&CstShiftArray[0], NumElts));
13644 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13647 if (Subtarget.hasSSE41()) {
13648 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13649 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13650 SDValue VecCstLowBitcast =
13651 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13652 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13653 // Low will be bitcasted right away, so do not bother bitcasting back to its
13655 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13656 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13657 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13658 // (uint4) 0x53000000, 0xaa);
13659 SDValue VecCstHighBitcast =
13660 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13661 SDValue VecShiftBitcast =
13662 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13663 // High will be bitcasted right away, so do not bother bitcasting back to
13664 // its original type.
13665 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13666 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13668 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13669 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13670 CstMask, CstMask, CstMask);
13671 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13672 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13673 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13675 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13676 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13679 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13680 SDValue CstFAdd = DAG.getConstantFP(
13681 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13682 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13683 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13684 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13685 makeArrayRef(&CstFAddArray[0], NumElts));
13687 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13688 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13690 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13691 // return (float4) lo + fhi;
13692 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13693 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13696 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13697 SelectionDAG &DAG) const {
13698 SDValue N0 = Op.getOperand(0);
13699 MVT SVT = N0.getSimpleValueType();
13702 switch (SVT.SimpleTy) {
13704 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13709 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13710 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13711 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13715 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13717 llvm_unreachable(nullptr);
13720 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13721 SelectionDAG &DAG) const {
13722 SDValue N0 = Op.getOperand(0);
13725 if (Op.getValueType().isVector())
13726 return lowerUINT_TO_FP_vec(Op, DAG);
13728 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13729 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13730 // the optimization here.
13731 if (DAG.SignBitIsZero(N0))
13732 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13734 MVT SrcVT = N0.getSimpleValueType();
13735 MVT DstVT = Op.getSimpleValueType();
13736 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13737 return LowerUINT_TO_FP_i64(Op, DAG);
13738 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13739 return LowerUINT_TO_FP_i32(Op, DAG);
13740 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13743 // Make a 64-bit buffer, and use it to build an FILD.
13744 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13745 if (SrcVT == MVT::i32) {
13746 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13747 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13748 getPointerTy(), StackSlot, WordOff);
13749 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13750 StackSlot, MachinePointerInfo(),
13752 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13753 OffsetSlot, MachinePointerInfo(),
13755 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13759 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13760 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13761 StackSlot, MachinePointerInfo(),
13763 // For i64 source, we need to add the appropriate power of 2 if the input
13764 // was negative. This is the same as the optimization in
13765 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13766 // we must be careful to do the computation in x87 extended precision, not
13767 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13768 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13769 MachineMemOperand *MMO =
13770 DAG.getMachineFunction()
13771 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13772 MachineMemOperand::MOLoad, 8, 8);
13774 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13775 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13776 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13779 APInt FF(32, 0x5F800000ULL);
13781 // Check whether the sign bit is set.
13782 SDValue SignSet = DAG.getSetCC(dl,
13783 getSetCCResultType(*DAG.getContext(), MVT::i64),
13784 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13787 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13788 SDValue FudgePtr = DAG.getConstantPool(
13789 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13792 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13793 SDValue Zero = DAG.getIntPtrConstant(0);
13794 SDValue Four = DAG.getIntPtrConstant(4);
13795 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13797 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13799 // Load the value out, extending it from f32 to f80.
13800 // FIXME: Avoid the extend by constructing the right constant pool?
13801 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13802 FudgePtr, MachinePointerInfo::getConstantPool(),
13803 MVT::f32, false, false, false, 4);
13804 // Extend everything to 80 bits to force it to be done on x87.
13805 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13806 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13809 std::pair<SDValue,SDValue>
13810 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13811 bool IsSigned, bool IsReplace) const {
13814 EVT DstTy = Op.getValueType();
13816 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13817 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13821 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13822 DstTy.getSimpleVT() >= MVT::i16 &&
13823 "Unknown FP_TO_INT to lower!");
13825 // These are really Legal.
13826 if (DstTy == MVT::i32 &&
13827 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13828 return std::make_pair(SDValue(), SDValue());
13829 if (Subtarget->is64Bit() &&
13830 DstTy == MVT::i64 &&
13831 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13832 return std::make_pair(SDValue(), SDValue());
13834 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13835 // stack slot, or into the FTOL runtime function.
13836 MachineFunction &MF = DAG.getMachineFunction();
13837 unsigned MemSize = DstTy.getSizeInBits()/8;
13838 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13839 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13842 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13843 Opc = X86ISD::WIN_FTOL;
13845 switch (DstTy.getSimpleVT().SimpleTy) {
13846 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13847 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13848 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13849 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13852 SDValue Chain = DAG.getEntryNode();
13853 SDValue Value = Op.getOperand(0);
13854 EVT TheVT = Op.getOperand(0).getValueType();
13855 // FIXME This causes a redundant load/store if the SSE-class value is already
13856 // in memory, such as if it is on the callstack.
13857 if (isScalarFPTypeInSSEReg(TheVT)) {
13858 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13859 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13860 MachinePointerInfo::getFixedStack(SSFI),
13862 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13864 Chain, StackSlot, DAG.getValueType(TheVT)
13867 MachineMemOperand *MMO =
13868 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13869 MachineMemOperand::MOLoad, MemSize, MemSize);
13870 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13871 Chain = Value.getValue(1);
13872 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13873 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13876 MachineMemOperand *MMO =
13877 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13878 MachineMemOperand::MOStore, MemSize, MemSize);
13880 if (Opc != X86ISD::WIN_FTOL) {
13881 // Build the FP_TO_INT*_IN_MEM
13882 SDValue Ops[] = { Chain, Value, StackSlot };
13883 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13885 return std::make_pair(FIST, StackSlot);
13887 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13888 DAG.getVTList(MVT::Other, MVT::Glue),
13890 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13891 MVT::i32, ftol.getValue(1));
13892 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13893 MVT::i32, eax.getValue(2));
13894 SDValue Ops[] = { eax, edx };
13895 SDValue pair = IsReplace
13896 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13897 : DAG.getMergeValues(Ops, DL);
13898 return std::make_pair(pair, SDValue());
13902 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13903 const X86Subtarget *Subtarget) {
13904 MVT VT = Op->getSimpleValueType(0);
13905 SDValue In = Op->getOperand(0);
13906 MVT InVT = In.getSimpleValueType();
13909 // Optimize vectors in AVX mode:
13912 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13913 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13914 // Concat upper and lower parts.
13917 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13918 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13919 // Concat upper and lower parts.
13922 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13923 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13924 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13927 if (Subtarget->hasInt256())
13928 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13930 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13931 SDValue Undef = DAG.getUNDEF(InVT);
13932 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13933 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13934 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13936 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13937 VT.getVectorNumElements()/2);
13939 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13940 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13942 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13945 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13946 SelectionDAG &DAG) {
13947 MVT VT = Op->getSimpleValueType(0);
13948 SDValue In = Op->getOperand(0);
13949 MVT InVT = In.getSimpleValueType();
13951 unsigned int NumElts = VT.getVectorNumElements();
13952 if (NumElts != 8 && NumElts != 16)
13955 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13956 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13958 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13959 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13960 // Now we have only mask extension
13961 assert(InVT.getVectorElementType() == MVT::i1);
13962 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13963 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13964 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13965 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13966 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13967 MachinePointerInfo::getConstantPool(),
13968 false, false, false, Alignment);
13970 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13971 if (VT.is512BitVector())
13973 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13976 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13977 SelectionDAG &DAG) {
13978 if (Subtarget->hasFp256()) {
13979 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13987 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13988 SelectionDAG &DAG) {
13990 MVT VT = Op.getSimpleValueType();
13991 SDValue In = Op.getOperand(0);
13992 MVT SVT = In.getSimpleValueType();
13994 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13995 return LowerZERO_EXTEND_AVX512(Op, DAG);
13997 if (Subtarget->hasFp256()) {
13998 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14003 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14004 VT.getVectorNumElements() != SVT.getVectorNumElements());
14008 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14010 MVT VT = Op.getSimpleValueType();
14011 SDValue In = Op.getOperand(0);
14012 MVT InVT = In.getSimpleValueType();
14014 if (VT == MVT::i1) {
14015 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14016 "Invalid scalar TRUNCATE operation");
14017 if (InVT.getSizeInBits() >= 32)
14019 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14020 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14022 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14023 "Invalid TRUNCATE operation");
14025 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14026 if (VT.getVectorElementType().getSizeInBits() >=8)
14027 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14029 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14030 unsigned NumElts = InVT.getVectorNumElements();
14031 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14032 if (InVT.getSizeInBits() < 512) {
14033 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14034 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14038 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14039 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14040 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14041 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14042 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14043 MachinePointerInfo::getConstantPool(),
14044 false, false, false, Alignment);
14045 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14046 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14047 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14050 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14051 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14052 if (Subtarget->hasInt256()) {
14053 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14054 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14055 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14057 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14058 DAG.getIntPtrConstant(0));
14061 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14062 DAG.getIntPtrConstant(0));
14063 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14064 DAG.getIntPtrConstant(2));
14065 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14066 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14067 static const int ShufMask[] = {0, 2, 4, 6};
14068 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14071 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14072 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14073 if (Subtarget->hasInt256()) {
14074 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14076 SmallVector<SDValue,32> pshufbMask;
14077 for (unsigned i = 0; i < 2; ++i) {
14078 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14079 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14080 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14081 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14082 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14083 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14084 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14085 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14086 for (unsigned j = 0; j < 8; ++j)
14087 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14089 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14090 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14091 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14093 static const int ShufMask[] = {0, 2, -1, -1};
14094 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14096 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14097 DAG.getIntPtrConstant(0));
14098 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14101 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14102 DAG.getIntPtrConstant(0));
14104 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14105 DAG.getIntPtrConstant(4));
14107 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14108 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14110 // The PSHUFB mask:
14111 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14112 -1, -1, -1, -1, -1, -1, -1, -1};
14114 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14115 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14116 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14118 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14119 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14121 // The MOVLHPS Mask:
14122 static const int ShufMask2[] = {0, 1, 4, 5};
14123 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14124 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14127 // Handle truncation of V256 to V128 using shuffles.
14128 if (!VT.is128BitVector() || !InVT.is256BitVector())
14131 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14133 unsigned NumElems = VT.getVectorNumElements();
14134 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14136 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14137 // Prepare truncation shuffle mask
14138 for (unsigned i = 0; i != NumElems; ++i)
14139 MaskVec[i] = i * 2;
14140 SDValue V = DAG.getVectorShuffle(NVT, DL,
14141 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14142 DAG.getUNDEF(NVT), &MaskVec[0]);
14143 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14144 DAG.getIntPtrConstant(0));
14147 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14148 SelectionDAG &DAG) const {
14149 assert(!Op.getSimpleValueType().isVector());
14151 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14152 /*IsSigned=*/ true, /*IsReplace=*/ false);
14153 SDValue FIST = Vals.first, StackSlot = Vals.second;
14154 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14155 if (!FIST.getNode()) return Op;
14157 if (StackSlot.getNode())
14158 // Load the result.
14159 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14160 FIST, StackSlot, MachinePointerInfo(),
14161 false, false, false, 0);
14163 // The node is the result.
14167 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14168 SelectionDAG &DAG) const {
14169 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14170 /*IsSigned=*/ false, /*IsReplace=*/ false);
14171 SDValue FIST = Vals.first, StackSlot = Vals.second;
14172 assert(FIST.getNode() && "Unexpected failure");
14174 if (StackSlot.getNode())
14175 // Load the result.
14176 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14177 FIST, StackSlot, MachinePointerInfo(),
14178 false, false, false, 0);
14180 // The node is the result.
14184 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14186 MVT VT = Op.getSimpleValueType();
14187 SDValue In = Op.getOperand(0);
14188 MVT SVT = In.getSimpleValueType();
14190 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14192 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14193 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14194 In, DAG.getUNDEF(SVT)));
14197 /// The only differences between FABS and FNEG are the mask and the logic op.
14198 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14199 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14200 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14201 "Wrong opcode for lowering FABS or FNEG.");
14203 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14205 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14206 // into an FNABS. We'll lower the FABS after that if it is still in use.
14208 for (SDNode *User : Op->uses())
14209 if (User->getOpcode() == ISD::FNEG)
14212 SDValue Op0 = Op.getOperand(0);
14213 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14216 MVT VT = Op.getSimpleValueType();
14217 // Assume scalar op for initialization; update for vector if needed.
14218 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14219 // generate a 16-byte vector constant and logic op even for the scalar case.
14220 // Using a 16-byte mask allows folding the load of the mask with
14221 // the logic op, so it can save (~4 bytes) on code size.
14223 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14224 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14225 // decide if we should generate a 16-byte constant mask when we only need 4 or
14226 // 8 bytes for the scalar case.
14227 if (VT.isVector()) {
14228 EltVT = VT.getVectorElementType();
14229 NumElts = VT.getVectorNumElements();
14232 unsigned EltBits = EltVT.getSizeInBits();
14233 LLVMContext *Context = DAG.getContext();
14234 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14236 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14237 Constant *C = ConstantInt::get(*Context, MaskElt);
14238 C = ConstantVector::getSplat(NumElts, C);
14239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14240 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14241 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14242 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14243 MachinePointerInfo::getConstantPool(),
14244 false, false, false, Alignment);
14246 if (VT.isVector()) {
14247 // For a vector, cast operands to a vector type, perform the logic op,
14248 // and cast the result back to the original value type.
14249 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14250 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14251 SDValue Operand = IsFNABS ?
14252 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14253 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14254 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14255 return DAG.getNode(ISD::BITCAST, dl, VT,
14256 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14259 // If not vector, then scalar.
14260 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14261 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14262 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14265 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14266 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14267 LLVMContext *Context = DAG.getContext();
14268 SDValue Op0 = Op.getOperand(0);
14269 SDValue Op1 = Op.getOperand(1);
14271 MVT VT = Op.getSimpleValueType();
14272 MVT SrcVT = Op1.getSimpleValueType();
14274 // If second operand is smaller, extend it first.
14275 if (SrcVT.bitsLT(VT)) {
14276 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14279 // And if it is bigger, shrink it first.
14280 if (SrcVT.bitsGT(VT)) {
14281 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14285 // At this point the operands and the result should have the same
14286 // type, and that won't be f80 since that is not custom lowered.
14288 // First get the sign bit of second operand.
14289 SmallVector<Constant*,4> CV;
14290 if (SrcVT == MVT::f64) {
14291 const fltSemantics &Sem = APFloat::IEEEdouble;
14292 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14293 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14295 const fltSemantics &Sem = APFloat::IEEEsingle;
14296 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14297 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14298 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14299 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14301 Constant *C = ConstantVector::get(CV);
14302 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14303 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14304 MachinePointerInfo::getConstantPool(),
14305 false, false, false, 16);
14306 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14308 // Shift sign bit right or left if the two operands have different types.
14309 if (SrcVT.bitsGT(VT)) {
14310 // Op0 is MVT::f32, Op1 is MVT::f64.
14311 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14312 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14313 DAG.getConstant(32, MVT::i32));
14314 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14315 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14316 DAG.getIntPtrConstant(0));
14319 // Clear first operand sign bit.
14321 if (VT == MVT::f64) {
14322 const fltSemantics &Sem = APFloat::IEEEdouble;
14323 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14324 APInt(64, ~(1ULL << 63)))));
14325 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14327 const fltSemantics &Sem = APFloat::IEEEsingle;
14328 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14329 APInt(32, ~(1U << 31)))));
14330 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14331 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14332 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14334 C = ConstantVector::get(CV);
14335 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14336 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14337 MachinePointerInfo::getConstantPool(),
14338 false, false, false, 16);
14339 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14341 // Or the value with the sign bit.
14342 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14345 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14346 SDValue N0 = Op.getOperand(0);
14348 MVT VT = Op.getSimpleValueType();
14350 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14351 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14352 DAG.getConstant(1, VT));
14353 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14356 // Check whether an OR'd tree is PTEST-able.
14357 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14358 SelectionDAG &DAG) {
14359 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14361 if (!Subtarget->hasSSE41())
14364 if (!Op->hasOneUse())
14367 SDNode *N = Op.getNode();
14370 SmallVector<SDValue, 8> Opnds;
14371 DenseMap<SDValue, unsigned> VecInMap;
14372 SmallVector<SDValue, 8> VecIns;
14373 EVT VT = MVT::Other;
14375 // Recognize a special case where a vector is casted into wide integer to
14377 Opnds.push_back(N->getOperand(0));
14378 Opnds.push_back(N->getOperand(1));
14380 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14381 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14382 // BFS traverse all OR'd operands.
14383 if (I->getOpcode() == ISD::OR) {
14384 Opnds.push_back(I->getOperand(0));
14385 Opnds.push_back(I->getOperand(1));
14386 // Re-evaluate the number of nodes to be traversed.
14387 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14391 // Quit if a non-EXTRACT_VECTOR_ELT
14392 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14395 // Quit if without a constant index.
14396 SDValue Idx = I->getOperand(1);
14397 if (!isa<ConstantSDNode>(Idx))
14400 SDValue ExtractedFromVec = I->getOperand(0);
14401 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14402 if (M == VecInMap.end()) {
14403 VT = ExtractedFromVec.getValueType();
14404 // Quit if not 128/256-bit vector.
14405 if (!VT.is128BitVector() && !VT.is256BitVector())
14407 // Quit if not the same type.
14408 if (VecInMap.begin() != VecInMap.end() &&
14409 VT != VecInMap.begin()->first.getValueType())
14411 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14412 VecIns.push_back(ExtractedFromVec);
14414 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14417 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14418 "Not extracted from 128-/256-bit vector.");
14420 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14422 for (DenseMap<SDValue, unsigned>::const_iterator
14423 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14424 // Quit if not all elements are used.
14425 if (I->second != FullMask)
14429 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14431 // Cast all vectors into TestVT for PTEST.
14432 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14433 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14435 // If more than one full vectors are evaluated, OR them first before PTEST.
14436 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14437 // Each iteration will OR 2 nodes and append the result until there is only
14438 // 1 node left, i.e. the final OR'd value of all vectors.
14439 SDValue LHS = VecIns[Slot];
14440 SDValue RHS = VecIns[Slot + 1];
14441 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14444 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14445 VecIns.back(), VecIns.back());
14448 /// \brief return true if \c Op has a use that doesn't just read flags.
14449 static bool hasNonFlagsUse(SDValue Op) {
14450 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14452 SDNode *User = *UI;
14453 unsigned UOpNo = UI.getOperandNo();
14454 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14455 // Look pass truncate.
14456 UOpNo = User->use_begin().getOperandNo();
14457 User = *User->use_begin();
14460 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14461 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14467 /// Emit nodes that will be selected as "test Op0,Op0", or something
14469 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14470 SelectionDAG &DAG) const {
14471 if (Op.getValueType() == MVT::i1)
14472 // KORTEST instruction should be selected
14473 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14474 DAG.getConstant(0, Op.getValueType()));
14476 // CF and OF aren't always set the way we want. Determine which
14477 // of these we need.
14478 bool NeedCF = false;
14479 bool NeedOF = false;
14482 case X86::COND_A: case X86::COND_AE:
14483 case X86::COND_B: case X86::COND_BE:
14486 case X86::COND_G: case X86::COND_GE:
14487 case X86::COND_L: case X86::COND_LE:
14488 case X86::COND_O: case X86::COND_NO: {
14489 // Check if we really need to set the
14490 // Overflow flag. If NoSignedWrap is present
14491 // that is not actually needed.
14492 switch (Op->getOpcode()) {
14497 const BinaryWithFlagsSDNode *BinNode =
14498 cast<BinaryWithFlagsSDNode>(Op.getNode());
14499 if (BinNode->hasNoSignedWrap())
14509 // See if we can use the EFLAGS value from the operand instead of
14510 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14511 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14512 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14513 // Emit a CMP with 0, which is the TEST pattern.
14514 //if (Op.getValueType() == MVT::i1)
14515 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14516 // DAG.getConstant(0, MVT::i1));
14517 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14518 DAG.getConstant(0, Op.getValueType()));
14520 unsigned Opcode = 0;
14521 unsigned NumOperands = 0;
14523 // Truncate operations may prevent the merge of the SETCC instruction
14524 // and the arithmetic instruction before it. Attempt to truncate the operands
14525 // of the arithmetic instruction and use a reduced bit-width instruction.
14526 bool NeedTruncation = false;
14527 SDValue ArithOp = Op;
14528 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14529 SDValue Arith = Op->getOperand(0);
14530 // Both the trunc and the arithmetic op need to have one user each.
14531 if (Arith->hasOneUse())
14532 switch (Arith.getOpcode()) {
14539 NeedTruncation = true;
14545 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14546 // which may be the result of a CAST. We use the variable 'Op', which is the
14547 // non-casted variable when we check for possible users.
14548 switch (ArithOp.getOpcode()) {
14550 // Due to an isel shortcoming, be conservative if this add is likely to be
14551 // selected as part of a load-modify-store instruction. When the root node
14552 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14553 // uses of other nodes in the match, such as the ADD in this case. This
14554 // leads to the ADD being left around and reselected, with the result being
14555 // two adds in the output. Alas, even if none our users are stores, that
14556 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14557 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14558 // climbing the DAG back to the root, and it doesn't seem to be worth the
14560 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14561 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14562 if (UI->getOpcode() != ISD::CopyToReg &&
14563 UI->getOpcode() != ISD::SETCC &&
14564 UI->getOpcode() != ISD::STORE)
14567 if (ConstantSDNode *C =
14568 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14569 // An add of one will be selected as an INC.
14570 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14571 Opcode = X86ISD::INC;
14576 // An add of negative one (subtract of one) will be selected as a DEC.
14577 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14578 Opcode = X86ISD::DEC;
14584 // Otherwise use a regular EFLAGS-setting add.
14585 Opcode = X86ISD::ADD;
14590 // If we have a constant logical shift that's only used in a comparison
14591 // against zero turn it into an equivalent AND. This allows turning it into
14592 // a TEST instruction later.
14593 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14594 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14595 EVT VT = Op.getValueType();
14596 unsigned BitWidth = VT.getSizeInBits();
14597 unsigned ShAmt = Op->getConstantOperandVal(1);
14598 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14600 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14601 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14602 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14603 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14605 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14606 DAG.getConstant(Mask, VT));
14607 DAG.ReplaceAllUsesWith(Op, New);
14613 // If the primary and result isn't used, don't bother using X86ISD::AND,
14614 // because a TEST instruction will be better.
14615 if (!hasNonFlagsUse(Op))
14621 // Due to the ISEL shortcoming noted above, be conservative if this op is
14622 // likely to be selected as part of a load-modify-store instruction.
14623 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14624 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14625 if (UI->getOpcode() == ISD::STORE)
14628 // Otherwise use a regular EFLAGS-setting instruction.
14629 switch (ArithOp.getOpcode()) {
14630 default: llvm_unreachable("unexpected operator!");
14631 case ISD::SUB: Opcode = X86ISD::SUB; break;
14632 case ISD::XOR: Opcode = X86ISD::XOR; break;
14633 case ISD::AND: Opcode = X86ISD::AND; break;
14635 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14636 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14637 if (EFLAGS.getNode())
14640 Opcode = X86ISD::OR;
14654 return SDValue(Op.getNode(), 1);
14660 // If we found that truncation is beneficial, perform the truncation and
14662 if (NeedTruncation) {
14663 EVT VT = Op.getValueType();
14664 SDValue WideVal = Op->getOperand(0);
14665 EVT WideVT = WideVal.getValueType();
14666 unsigned ConvertedOp = 0;
14667 // Use a target machine opcode to prevent further DAGCombine
14668 // optimizations that may separate the arithmetic operations
14669 // from the setcc node.
14670 switch (WideVal.getOpcode()) {
14672 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14673 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14674 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14675 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14676 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14680 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14681 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14682 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14683 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14684 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14690 // Emit a CMP with 0, which is the TEST pattern.
14691 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14692 DAG.getConstant(0, Op.getValueType()));
14694 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14695 SmallVector<SDValue, 4> Ops;
14696 for (unsigned i = 0; i != NumOperands; ++i)
14697 Ops.push_back(Op.getOperand(i));
14699 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14700 DAG.ReplaceAllUsesWith(Op, New);
14701 return SDValue(New.getNode(), 1);
14704 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14706 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14707 SDLoc dl, SelectionDAG &DAG) const {
14708 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14709 if (C->getAPIntValue() == 0)
14710 return EmitTest(Op0, X86CC, dl, DAG);
14712 if (Op0.getValueType() == MVT::i1)
14713 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14716 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14717 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14718 // Do the comparison at i32 if it's smaller, besides the Atom case.
14719 // This avoids subregister aliasing issues. Keep the smaller reference
14720 // if we're optimizing for size, however, as that'll allow better folding
14721 // of memory operations.
14722 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14723 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14724 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14725 !Subtarget->isAtom()) {
14726 unsigned ExtendOp =
14727 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14728 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14729 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14731 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14732 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14733 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14735 return SDValue(Sub.getNode(), 1);
14737 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14740 /// Convert a comparison if required by the subtarget.
14741 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14742 SelectionDAG &DAG) const {
14743 // If the subtarget does not support the FUCOMI instruction, floating-point
14744 // comparisons have to be converted.
14745 if (Subtarget->hasCMov() ||
14746 Cmp.getOpcode() != X86ISD::CMP ||
14747 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14748 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14751 // The instruction selector will select an FUCOM instruction instead of
14752 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14753 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14754 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14756 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14757 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14758 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14759 DAG.getConstant(8, MVT::i8));
14760 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14761 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14764 /// The minimum architected relative accuracy is 2^-12. We need one
14765 /// Newton-Raphson step to have a good float result (24 bits of precision).
14766 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14767 DAGCombinerInfo &DCI,
14768 unsigned &RefinementSteps,
14769 bool &UseOneConstNR) const {
14770 // FIXME: We should use instruction latency models to calculate the cost of
14771 // each potential sequence, but this is very hard to do reliably because
14772 // at least Intel's Core* chips have variable timing based on the number of
14773 // significant digits in the divisor and/or sqrt operand.
14774 if (!Subtarget->useSqrtEst())
14777 EVT VT = Op.getValueType();
14779 // SSE1 has rsqrtss and rsqrtps.
14780 // TODO: Add support for AVX512 (v16f32).
14781 // It is likely not profitable to do this for f64 because a double-precision
14782 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14783 // instructions: convert to single, rsqrtss, convert back to double, refine
14784 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14785 // along with FMA, this could be a throughput win.
14786 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14787 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14788 RefinementSteps = 1;
14789 UseOneConstNR = false;
14790 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14795 /// The minimum architected relative accuracy is 2^-12. We need one
14796 /// Newton-Raphson step to have a good float result (24 bits of precision).
14797 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14798 DAGCombinerInfo &DCI,
14799 unsigned &RefinementSteps) const {
14800 // FIXME: We should use instruction latency models to calculate the cost of
14801 // each potential sequence, but this is very hard to do reliably because
14802 // at least Intel's Core* chips have variable timing based on the number of
14803 // significant digits in the divisor.
14804 if (!Subtarget->useReciprocalEst())
14807 EVT VT = Op.getValueType();
14809 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14810 // TODO: Add support for AVX512 (v16f32).
14811 // It is likely not profitable to do this for f64 because a double-precision
14812 // reciprocal estimate with refinement on x86 prior to FMA requires
14813 // 15 instructions: convert to single, rcpss, convert back to double, refine
14814 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14815 // along with FMA, this could be a throughput win.
14816 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14817 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14818 RefinementSteps = ReciprocalEstimateRefinementSteps;
14819 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14824 static bool isAllOnes(SDValue V) {
14825 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14826 return C && C->isAllOnesValue();
14829 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14830 /// if it's possible.
14831 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14832 SDLoc dl, SelectionDAG &DAG) const {
14833 SDValue Op0 = And.getOperand(0);
14834 SDValue Op1 = And.getOperand(1);
14835 if (Op0.getOpcode() == ISD::TRUNCATE)
14836 Op0 = Op0.getOperand(0);
14837 if (Op1.getOpcode() == ISD::TRUNCATE)
14838 Op1 = Op1.getOperand(0);
14841 if (Op1.getOpcode() == ISD::SHL)
14842 std::swap(Op0, Op1);
14843 if (Op0.getOpcode() == ISD::SHL) {
14844 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14845 if (And00C->getZExtValue() == 1) {
14846 // If we looked past a truncate, check that it's only truncating away
14848 unsigned BitWidth = Op0.getValueSizeInBits();
14849 unsigned AndBitWidth = And.getValueSizeInBits();
14850 if (BitWidth > AndBitWidth) {
14852 DAG.computeKnownBits(Op0, Zeros, Ones);
14853 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14857 RHS = Op0.getOperand(1);
14859 } else if (Op1.getOpcode() == ISD::Constant) {
14860 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14861 uint64_t AndRHSVal = AndRHS->getZExtValue();
14862 SDValue AndLHS = Op0;
14864 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14865 LHS = AndLHS.getOperand(0);
14866 RHS = AndLHS.getOperand(1);
14869 // Use BT if the immediate can't be encoded in a TEST instruction.
14870 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14872 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14876 if (LHS.getNode()) {
14877 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14878 // instruction. Since the shift amount is in-range-or-undefined, we know
14879 // that doing a bittest on the i32 value is ok. We extend to i32 because
14880 // the encoding for the i16 version is larger than the i32 version.
14881 // Also promote i16 to i32 for performance / code size reason.
14882 if (LHS.getValueType() == MVT::i8 ||
14883 LHS.getValueType() == MVT::i16)
14884 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14886 // If the operand types disagree, extend the shift amount to match. Since
14887 // BT ignores high bits (like shifts) we can use anyextend.
14888 if (LHS.getValueType() != RHS.getValueType())
14889 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14891 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14892 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14893 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14894 DAG.getConstant(Cond, MVT::i8), BT);
14900 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14902 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14907 // SSE Condition code mapping:
14916 switch (SetCCOpcode) {
14917 default: llvm_unreachable("Unexpected SETCC condition");
14919 case ISD::SETEQ: SSECC = 0; break;
14921 case ISD::SETGT: Swap = true; // Fallthrough
14923 case ISD::SETOLT: SSECC = 1; break;
14925 case ISD::SETGE: Swap = true; // Fallthrough
14927 case ISD::SETOLE: SSECC = 2; break;
14928 case ISD::SETUO: SSECC = 3; break;
14930 case ISD::SETNE: SSECC = 4; break;
14931 case ISD::SETULE: Swap = true; // Fallthrough
14932 case ISD::SETUGE: SSECC = 5; break;
14933 case ISD::SETULT: Swap = true; // Fallthrough
14934 case ISD::SETUGT: SSECC = 6; break;
14935 case ISD::SETO: SSECC = 7; break;
14937 case ISD::SETONE: SSECC = 8; break;
14940 std::swap(Op0, Op1);
14945 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14946 // ones, and then concatenate the result back.
14947 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14948 MVT VT = Op.getSimpleValueType();
14950 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14951 "Unsupported value type for operation");
14953 unsigned NumElems = VT.getVectorNumElements();
14955 SDValue CC = Op.getOperand(2);
14957 // Extract the LHS vectors
14958 SDValue LHS = Op.getOperand(0);
14959 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14960 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14962 // Extract the RHS vectors
14963 SDValue RHS = Op.getOperand(1);
14964 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14965 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14967 // Issue the operation on the smaller types and concatenate the result back
14968 MVT EltVT = VT.getVectorElementType();
14969 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14970 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14971 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14972 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14975 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14976 const X86Subtarget *Subtarget) {
14977 SDValue Op0 = Op.getOperand(0);
14978 SDValue Op1 = Op.getOperand(1);
14979 SDValue CC = Op.getOperand(2);
14980 MVT VT = Op.getSimpleValueType();
14983 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14984 Op.getValueType().getScalarType() == MVT::i1 &&
14985 "Cannot set masked compare for this operation");
14987 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14989 bool Unsigned = false;
14992 switch (SetCCOpcode) {
14993 default: llvm_unreachable("Unexpected SETCC condition");
14994 case ISD::SETNE: SSECC = 4; break;
14995 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14996 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14997 case ISD::SETLT: Swap = true; //fall-through
14998 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14999 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15000 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15001 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15002 case ISD::SETULE: Unsigned = true; //fall-through
15003 case ISD::SETLE: SSECC = 2; break;
15007 std::swap(Op0, Op1);
15009 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15010 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15011 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15012 DAG.getConstant(SSECC, MVT::i8));
15015 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15016 /// operand \p Op1. If non-trivial (for example because it's not constant)
15017 /// return an empty value.
15018 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15020 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15024 MVT VT = Op1.getSimpleValueType();
15025 MVT EVT = VT.getVectorElementType();
15026 unsigned n = VT.getVectorNumElements();
15027 SmallVector<SDValue, 8> ULTOp1;
15029 for (unsigned i = 0; i < n; ++i) {
15030 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15031 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15034 // Avoid underflow.
15035 APInt Val = Elt->getAPIntValue();
15039 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15042 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15045 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15046 SelectionDAG &DAG) {
15047 SDValue Op0 = Op.getOperand(0);
15048 SDValue Op1 = Op.getOperand(1);
15049 SDValue CC = Op.getOperand(2);
15050 MVT VT = Op.getSimpleValueType();
15051 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15052 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15057 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15058 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15061 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15062 unsigned Opc = X86ISD::CMPP;
15063 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15064 assert(VT.getVectorNumElements() <= 16);
15065 Opc = X86ISD::CMPM;
15067 // In the two special cases we can't handle, emit two comparisons.
15070 unsigned CombineOpc;
15071 if (SetCCOpcode == ISD::SETUEQ) {
15072 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15074 assert(SetCCOpcode == ISD::SETONE);
15075 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15078 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15079 DAG.getConstant(CC0, MVT::i8));
15080 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15081 DAG.getConstant(CC1, MVT::i8));
15082 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15084 // Handle all other FP comparisons here.
15085 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15086 DAG.getConstant(SSECC, MVT::i8));
15089 // Break 256-bit integer vector compare into smaller ones.
15090 if (VT.is256BitVector() && !Subtarget->hasInt256())
15091 return Lower256IntVSETCC(Op, DAG);
15093 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15094 EVT OpVT = Op1.getValueType();
15095 if (Subtarget->hasAVX512()) {
15096 if (Op1.getValueType().is512BitVector() ||
15097 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15098 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15099 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15101 // In AVX-512 architecture setcc returns mask with i1 elements,
15102 // But there is no compare instruction for i8 and i16 elements in KNL.
15103 // We are not talking about 512-bit operands in this case, these
15104 // types are illegal.
15106 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15107 OpVT.getVectorElementType().getSizeInBits() >= 8))
15108 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15109 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15112 // We are handling one of the integer comparisons here. Since SSE only has
15113 // GT and EQ comparisons for integer, swapping operands and multiple
15114 // operations may be required for some comparisons.
15116 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15117 bool Subus = false;
15119 switch (SetCCOpcode) {
15120 default: llvm_unreachable("Unexpected SETCC condition");
15121 case ISD::SETNE: Invert = true;
15122 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15123 case ISD::SETLT: Swap = true;
15124 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15125 case ISD::SETGE: Swap = true;
15126 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15127 Invert = true; break;
15128 case ISD::SETULT: Swap = true;
15129 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15130 FlipSigns = true; break;
15131 case ISD::SETUGE: Swap = true;
15132 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15133 FlipSigns = true; Invert = true; break;
15136 // Special case: Use min/max operations for SETULE/SETUGE
15137 MVT VET = VT.getVectorElementType();
15139 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15140 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15143 switch (SetCCOpcode) {
15145 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15146 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15149 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15152 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15153 if (!MinMax && hasSubus) {
15154 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15156 // t = psubus Op0, Op1
15157 // pcmpeq t, <0..0>
15158 switch (SetCCOpcode) {
15160 case ISD::SETULT: {
15161 // If the comparison is against a constant we can turn this into a
15162 // setule. With psubus, setule does not require a swap. This is
15163 // beneficial because the constant in the register is no longer
15164 // destructed as the destination so it can be hoisted out of a loop.
15165 // Only do this pre-AVX since vpcmp* is no longer destructive.
15166 if (Subtarget->hasAVX())
15168 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15169 if (ULEOp1.getNode()) {
15171 Subus = true; Invert = false; Swap = false;
15175 // Psubus is better than flip-sign because it requires no inversion.
15176 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15177 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15181 Opc = X86ISD::SUBUS;
15187 std::swap(Op0, Op1);
15189 // Check that the operation in question is available (most are plain SSE2,
15190 // but PCMPGTQ and PCMPEQQ have different requirements).
15191 if (VT == MVT::v2i64) {
15192 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15193 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15195 // First cast everything to the right type.
15196 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15197 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15199 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15200 // bits of the inputs before performing those operations. The lower
15201 // compare is always unsigned.
15204 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15206 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15207 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15208 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15209 Sign, Zero, Sign, Zero);
15211 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15212 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15214 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15215 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15216 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15218 // Create masks for only the low parts/high parts of the 64 bit integers.
15219 static const int MaskHi[] = { 1, 1, 3, 3 };
15220 static const int MaskLo[] = { 0, 0, 2, 2 };
15221 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15222 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15223 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15225 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15226 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15229 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15231 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15234 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15235 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15236 // pcmpeqd + pshufd + pand.
15237 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15239 // First cast everything to the right type.
15240 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15241 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15244 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15246 // Make sure the lower and upper halves are both all-ones.
15247 static const int Mask[] = { 1, 0, 3, 2 };
15248 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15249 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15252 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15254 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15258 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15259 // bits of the inputs before performing those operations.
15261 EVT EltVT = VT.getVectorElementType();
15262 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15263 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15264 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15267 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15269 // If the logical-not of the result is required, perform that now.
15271 Result = DAG.getNOT(dl, Result, VT);
15274 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15277 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15278 getZeroVector(VT, Subtarget, DAG, dl));
15283 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15285 MVT VT = Op.getSimpleValueType();
15287 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15289 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15290 && "SetCC type must be 8-bit or 1-bit integer");
15291 SDValue Op0 = Op.getOperand(0);
15292 SDValue Op1 = Op.getOperand(1);
15294 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15296 // Optimize to BT if possible.
15297 // Lower (X & (1 << N)) == 0 to BT(X, N).
15298 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15299 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15300 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15301 Op1.getOpcode() == ISD::Constant &&
15302 cast<ConstantSDNode>(Op1)->isNullValue() &&
15303 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15304 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15305 if (NewSetCC.getNode())
15309 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15311 if (Op1.getOpcode() == ISD::Constant &&
15312 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15313 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15314 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15316 // If the input is a setcc, then reuse the input setcc or use a new one with
15317 // the inverted condition.
15318 if (Op0.getOpcode() == X86ISD::SETCC) {
15319 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15320 bool Invert = (CC == ISD::SETNE) ^
15321 cast<ConstantSDNode>(Op1)->isNullValue();
15325 CCode = X86::GetOppositeBranchCondition(CCode);
15326 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15327 DAG.getConstant(CCode, MVT::i8),
15328 Op0.getOperand(1));
15330 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15334 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15335 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15336 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15338 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15339 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15342 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15343 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15344 if (X86CC == X86::COND_INVALID)
15347 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15348 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15349 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15350 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15352 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15356 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15357 static bool isX86LogicalCmp(SDValue Op) {
15358 unsigned Opc = Op.getNode()->getOpcode();
15359 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15360 Opc == X86ISD::SAHF)
15362 if (Op.getResNo() == 1 &&
15363 (Opc == X86ISD::ADD ||
15364 Opc == X86ISD::SUB ||
15365 Opc == X86ISD::ADC ||
15366 Opc == X86ISD::SBB ||
15367 Opc == X86ISD::SMUL ||
15368 Opc == X86ISD::UMUL ||
15369 Opc == X86ISD::INC ||
15370 Opc == X86ISD::DEC ||
15371 Opc == X86ISD::OR ||
15372 Opc == X86ISD::XOR ||
15373 Opc == X86ISD::AND))
15376 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15382 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15383 if (V.getOpcode() != ISD::TRUNCATE)
15386 SDValue VOp0 = V.getOperand(0);
15387 unsigned InBits = VOp0.getValueSizeInBits();
15388 unsigned Bits = V.getValueSizeInBits();
15389 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15392 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15393 bool addTest = true;
15394 SDValue Cond = Op.getOperand(0);
15395 SDValue Op1 = Op.getOperand(1);
15396 SDValue Op2 = Op.getOperand(2);
15398 EVT VT = Op1.getValueType();
15401 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15402 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15403 // sequence later on.
15404 if (Cond.getOpcode() == ISD::SETCC &&
15405 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15406 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15407 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15408 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15409 int SSECC = translateX86FSETCC(
15410 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15413 if (Subtarget->hasAVX512()) {
15414 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15415 DAG.getConstant(SSECC, MVT::i8));
15416 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15418 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15419 DAG.getConstant(SSECC, MVT::i8));
15420 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15421 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15422 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15426 if (Cond.getOpcode() == ISD::SETCC) {
15427 SDValue NewCond = LowerSETCC(Cond, DAG);
15428 if (NewCond.getNode())
15432 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15433 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15434 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15435 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15436 if (Cond.getOpcode() == X86ISD::SETCC &&
15437 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15438 isZero(Cond.getOperand(1).getOperand(1))) {
15439 SDValue Cmp = Cond.getOperand(1);
15441 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15443 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15444 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15445 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15447 SDValue CmpOp0 = Cmp.getOperand(0);
15448 // Apply further optimizations for special cases
15449 // (select (x != 0), -1, 0) -> neg & sbb
15450 // (select (x == 0), 0, -1) -> neg & sbb
15451 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15452 if (YC->isNullValue() &&
15453 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15454 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15455 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15456 DAG.getConstant(0, CmpOp0.getValueType()),
15458 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15459 DAG.getConstant(X86::COND_B, MVT::i8),
15460 SDValue(Neg.getNode(), 1));
15464 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15465 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15466 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15468 SDValue Res = // Res = 0 or -1.
15469 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15470 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15472 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15473 Res = DAG.getNOT(DL, Res, Res.getValueType());
15475 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15476 if (!N2C || !N2C->isNullValue())
15477 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15482 // Look past (and (setcc_carry (cmp ...)), 1).
15483 if (Cond.getOpcode() == ISD::AND &&
15484 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15485 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15486 if (C && C->getAPIntValue() == 1)
15487 Cond = Cond.getOperand(0);
15490 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15491 // setting operand in place of the X86ISD::SETCC.
15492 unsigned CondOpcode = Cond.getOpcode();
15493 if (CondOpcode == X86ISD::SETCC ||
15494 CondOpcode == X86ISD::SETCC_CARRY) {
15495 CC = Cond.getOperand(0);
15497 SDValue Cmp = Cond.getOperand(1);
15498 unsigned Opc = Cmp.getOpcode();
15499 MVT VT = Op.getSimpleValueType();
15501 bool IllegalFPCMov = false;
15502 if (VT.isFloatingPoint() && !VT.isVector() &&
15503 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15504 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15506 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15507 Opc == X86ISD::BT) { // FIXME
15511 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15512 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15513 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15514 Cond.getOperand(0).getValueType() != MVT::i8)) {
15515 SDValue LHS = Cond.getOperand(0);
15516 SDValue RHS = Cond.getOperand(1);
15517 unsigned X86Opcode;
15520 switch (CondOpcode) {
15521 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15522 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15523 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15524 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15525 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15526 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15527 default: llvm_unreachable("unexpected overflowing operator");
15529 if (CondOpcode == ISD::UMULO)
15530 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15533 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15535 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15537 if (CondOpcode == ISD::UMULO)
15538 Cond = X86Op.getValue(2);
15540 Cond = X86Op.getValue(1);
15542 CC = DAG.getConstant(X86Cond, MVT::i8);
15547 // Look pass the truncate if the high bits are known zero.
15548 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15549 Cond = Cond.getOperand(0);
15551 // We know the result of AND is compared against zero. Try to match
15553 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15554 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15555 if (NewSetCC.getNode()) {
15556 CC = NewSetCC.getOperand(0);
15557 Cond = NewSetCC.getOperand(1);
15564 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15565 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15568 // a < b ? -1 : 0 -> RES = ~setcc_carry
15569 // a < b ? 0 : -1 -> RES = setcc_carry
15570 // a >= b ? -1 : 0 -> RES = setcc_carry
15571 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15572 if (Cond.getOpcode() == X86ISD::SUB) {
15573 Cond = ConvertCmpIfNecessary(Cond, DAG);
15574 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15576 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15577 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15578 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15579 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15580 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15581 return DAG.getNOT(DL, Res, Res.getValueType());
15586 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15587 // widen the cmov and push the truncate through. This avoids introducing a new
15588 // branch during isel and doesn't add any extensions.
15589 if (Op.getValueType() == MVT::i8 &&
15590 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15591 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15592 if (T1.getValueType() == T2.getValueType() &&
15593 // Blacklist CopyFromReg to avoid partial register stalls.
15594 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15595 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15596 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15597 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15601 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15602 // condition is true.
15603 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15604 SDValue Ops[] = { Op2, Op1, CC, Cond };
15605 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15608 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15609 SelectionDAG &DAG) {
15610 MVT VT = Op->getSimpleValueType(0);
15611 SDValue In = Op->getOperand(0);
15612 MVT InVT = In.getSimpleValueType();
15613 MVT VTElt = VT.getVectorElementType();
15614 MVT InVTElt = InVT.getVectorElementType();
15618 if ((InVTElt == MVT::i1) &&
15619 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15620 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15622 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15623 VTElt.getSizeInBits() <= 16)) ||
15625 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15626 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15628 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15629 VTElt.getSizeInBits() >= 32))))
15630 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15632 unsigned int NumElts = VT.getVectorNumElements();
15634 if (NumElts != 8 && NumElts != 16)
15637 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15638 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15639 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15640 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15643 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15644 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15646 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15647 Constant *C = ConstantInt::get(*DAG.getContext(),
15648 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15650 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15651 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15652 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15653 MachinePointerInfo::getConstantPool(),
15654 false, false, false, Alignment);
15655 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15656 if (VT.is512BitVector())
15658 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15661 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15662 SelectionDAG &DAG) {
15663 MVT VT = Op->getSimpleValueType(0);
15664 SDValue In = Op->getOperand(0);
15665 MVT InVT = In.getSimpleValueType();
15668 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15669 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15671 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15672 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15673 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15676 if (Subtarget->hasInt256())
15677 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15679 // Optimize vectors in AVX mode
15680 // Sign extend v8i16 to v8i32 and
15683 // Divide input vector into two parts
15684 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15685 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15686 // concat the vectors to original VT
15688 unsigned NumElems = InVT.getVectorNumElements();
15689 SDValue Undef = DAG.getUNDEF(InVT);
15691 SmallVector<int,8> ShufMask1(NumElems, -1);
15692 for (unsigned i = 0; i != NumElems/2; ++i)
15695 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15697 SmallVector<int,8> ShufMask2(NumElems, -1);
15698 for (unsigned i = 0; i != NumElems/2; ++i)
15699 ShufMask2[i] = i + NumElems/2;
15701 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15703 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15704 VT.getVectorNumElements()/2);
15706 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15707 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15709 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15712 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15713 // may emit an illegal shuffle but the expansion is still better than scalar
15714 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15715 // we'll emit a shuffle and a arithmetic shift.
15716 // TODO: It is possible to support ZExt by zeroing the undef values during
15717 // the shuffle phase or after the shuffle.
15718 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15719 SelectionDAG &DAG) {
15720 MVT RegVT = Op.getSimpleValueType();
15721 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15722 assert(RegVT.isInteger() &&
15723 "We only custom lower integer vector sext loads.");
15725 // Nothing useful we can do without SSE2 shuffles.
15726 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15728 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15730 EVT MemVT = Ld->getMemoryVT();
15731 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15732 unsigned RegSz = RegVT.getSizeInBits();
15734 ISD::LoadExtType Ext = Ld->getExtensionType();
15736 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15737 && "Only anyext and sext are currently implemented.");
15738 assert(MemVT != RegVT && "Cannot extend to the same type");
15739 assert(MemVT.isVector() && "Must load a vector from memory");
15741 unsigned NumElems = RegVT.getVectorNumElements();
15742 unsigned MemSz = MemVT.getSizeInBits();
15743 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15745 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15746 // The only way in which we have a legal 256-bit vector result but not the
15747 // integer 256-bit operations needed to directly lower a sextload is if we
15748 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15749 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15750 // correctly legalized. We do this late to allow the canonical form of
15751 // sextload to persist throughout the rest of the DAG combiner -- it wants
15752 // to fold together any extensions it can, and so will fuse a sign_extend
15753 // of an sextload into a sextload targeting a wider value.
15755 if (MemSz == 128) {
15756 // Just switch this to a normal load.
15757 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15758 "it must be a legal 128-bit vector "
15760 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15761 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15762 Ld->isInvariant(), Ld->getAlignment());
15764 assert(MemSz < 128 &&
15765 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15766 // Do an sext load to a 128-bit vector type. We want to use the same
15767 // number of elements, but elements half as wide. This will end up being
15768 // recursively lowered by this routine, but will succeed as we definitely
15769 // have all the necessary features if we're using AVX1.
15771 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15772 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15774 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15775 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15776 Ld->isNonTemporal(), Ld->isInvariant(),
15777 Ld->getAlignment());
15780 // Replace chain users with the new chain.
15781 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15782 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15784 // Finally, do a normal sign-extend to the desired register.
15785 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15788 // All sizes must be a power of two.
15789 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15790 "Non-power-of-two elements are not custom lowered!");
15792 // Attempt to load the original value using scalar loads.
15793 // Find the largest scalar type that divides the total loaded size.
15794 MVT SclrLoadTy = MVT::i8;
15795 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15796 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15797 MVT Tp = (MVT::SimpleValueType)tp;
15798 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15803 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15804 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15806 SclrLoadTy = MVT::f64;
15808 // Calculate the number of scalar loads that we need to perform
15809 // in order to load our vector from memory.
15810 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15812 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15813 "Can only lower sext loads with a single scalar load!");
15815 unsigned loadRegZize = RegSz;
15816 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15819 // Represent our vector as a sequence of elements which are the
15820 // largest scalar that we can load.
15821 EVT LoadUnitVecVT = EVT::getVectorVT(
15822 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15824 // Represent the data using the same element type that is stored in
15825 // memory. In practice, we ''widen'' MemVT.
15827 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15828 loadRegZize / MemVT.getScalarType().getSizeInBits());
15830 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15831 "Invalid vector type");
15833 // We can't shuffle using an illegal type.
15834 assert(TLI.isTypeLegal(WideVecVT) &&
15835 "We only lower types that form legal widened vector types");
15837 SmallVector<SDValue, 8> Chains;
15838 SDValue Ptr = Ld->getBasePtr();
15839 SDValue Increment =
15840 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15841 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15843 for (unsigned i = 0; i < NumLoads; ++i) {
15844 // Perform a single load.
15845 SDValue ScalarLoad =
15846 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15847 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15848 Ld->getAlignment());
15849 Chains.push_back(ScalarLoad.getValue(1));
15850 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15851 // another round of DAGCombining.
15853 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15855 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15856 ScalarLoad, DAG.getIntPtrConstant(i));
15858 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15861 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15863 // Bitcast the loaded value to a vector of the original element type, in
15864 // the size of the target vector type.
15865 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15866 unsigned SizeRatio = RegSz / MemSz;
15868 if (Ext == ISD::SEXTLOAD) {
15869 // If we have SSE4.1, we can directly emit a VSEXT node.
15870 if (Subtarget->hasSSE41()) {
15871 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15872 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15876 // Otherwise we'll shuffle the small elements in the high bits of the
15877 // larger type and perform an arithmetic shift. If the shift is not legal
15878 // it's better to scalarize.
15879 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15880 "We can't implement a sext load without an arithmetic right shift!");
15882 // Redistribute the loaded elements into the different locations.
15883 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15884 for (unsigned i = 0; i != NumElems; ++i)
15885 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15887 SDValue Shuff = DAG.getVectorShuffle(
15888 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15890 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15892 // Build the arithmetic shift.
15893 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15894 MemVT.getVectorElementType().getSizeInBits();
15896 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15898 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15902 // Redistribute the loaded elements into the different locations.
15903 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15904 for (unsigned i = 0; i != NumElems; ++i)
15905 ShuffleVec[i * SizeRatio] = i;
15907 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15908 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15910 // Bitcast to the requested type.
15911 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15912 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15916 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15917 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15918 // from the AND / OR.
15919 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15920 Opc = Op.getOpcode();
15921 if (Opc != ISD::OR && Opc != ISD::AND)
15923 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15924 Op.getOperand(0).hasOneUse() &&
15925 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15926 Op.getOperand(1).hasOneUse());
15929 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15930 // 1 and that the SETCC node has a single use.
15931 static bool isXor1OfSetCC(SDValue Op) {
15932 if (Op.getOpcode() != ISD::XOR)
15934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15935 if (N1C && N1C->getAPIntValue() == 1) {
15936 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15937 Op.getOperand(0).hasOneUse();
15942 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15943 bool addTest = true;
15944 SDValue Chain = Op.getOperand(0);
15945 SDValue Cond = Op.getOperand(1);
15946 SDValue Dest = Op.getOperand(2);
15949 bool Inverted = false;
15951 if (Cond.getOpcode() == ISD::SETCC) {
15952 // Check for setcc([su]{add,sub,mul}o == 0).
15953 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15954 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15955 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15956 Cond.getOperand(0).getResNo() == 1 &&
15957 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15958 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15959 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15960 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15961 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15962 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15964 Cond = Cond.getOperand(0);
15966 SDValue NewCond = LowerSETCC(Cond, DAG);
15967 if (NewCond.getNode())
15972 // FIXME: LowerXALUO doesn't handle these!!
15973 else if (Cond.getOpcode() == X86ISD::ADD ||
15974 Cond.getOpcode() == X86ISD::SUB ||
15975 Cond.getOpcode() == X86ISD::SMUL ||
15976 Cond.getOpcode() == X86ISD::UMUL)
15977 Cond = LowerXALUO(Cond, DAG);
15980 // Look pass (and (setcc_carry (cmp ...)), 1).
15981 if (Cond.getOpcode() == ISD::AND &&
15982 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15983 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15984 if (C && C->getAPIntValue() == 1)
15985 Cond = Cond.getOperand(0);
15988 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15989 // setting operand in place of the X86ISD::SETCC.
15990 unsigned CondOpcode = Cond.getOpcode();
15991 if (CondOpcode == X86ISD::SETCC ||
15992 CondOpcode == X86ISD::SETCC_CARRY) {
15993 CC = Cond.getOperand(0);
15995 SDValue Cmp = Cond.getOperand(1);
15996 unsigned Opc = Cmp.getOpcode();
15997 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15998 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16002 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16006 // These can only come from an arithmetic instruction with overflow,
16007 // e.g. SADDO, UADDO.
16008 Cond = Cond.getNode()->getOperand(1);
16014 CondOpcode = Cond.getOpcode();
16015 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16016 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16017 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16018 Cond.getOperand(0).getValueType() != MVT::i8)) {
16019 SDValue LHS = Cond.getOperand(0);
16020 SDValue RHS = Cond.getOperand(1);
16021 unsigned X86Opcode;
16024 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16025 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16027 switch (CondOpcode) {
16028 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16032 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16035 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16036 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16038 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16040 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16043 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16044 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16045 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16046 default: llvm_unreachable("unexpected overflowing operator");
16049 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16050 if (CondOpcode == ISD::UMULO)
16051 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16054 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16056 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16058 if (CondOpcode == ISD::UMULO)
16059 Cond = X86Op.getValue(2);
16061 Cond = X86Op.getValue(1);
16063 CC = DAG.getConstant(X86Cond, MVT::i8);
16067 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16068 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16069 if (CondOpc == ISD::OR) {
16070 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16071 // two branches instead of an explicit OR instruction with a
16073 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16074 isX86LogicalCmp(Cmp)) {
16075 CC = Cond.getOperand(0).getOperand(0);
16076 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16077 Chain, Dest, CC, Cmp);
16078 CC = Cond.getOperand(1).getOperand(0);
16082 } else { // ISD::AND
16083 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16084 // two branches instead of an explicit AND instruction with a
16085 // separate test. However, we only do this if this block doesn't
16086 // have a fall-through edge, because this requires an explicit
16087 // jmp when the condition is false.
16088 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16089 isX86LogicalCmp(Cmp) &&
16090 Op.getNode()->hasOneUse()) {
16091 X86::CondCode CCode =
16092 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16093 CCode = X86::GetOppositeBranchCondition(CCode);
16094 CC = DAG.getConstant(CCode, MVT::i8);
16095 SDNode *User = *Op.getNode()->use_begin();
16096 // Look for an unconditional branch following this conditional branch.
16097 // We need this because we need to reverse the successors in order
16098 // to implement FCMP_OEQ.
16099 if (User->getOpcode() == ISD::BR) {
16100 SDValue FalseBB = User->getOperand(1);
16102 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16103 assert(NewBR == User);
16107 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16108 Chain, Dest, CC, Cmp);
16109 X86::CondCode CCode =
16110 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16111 CCode = X86::GetOppositeBranchCondition(CCode);
16112 CC = DAG.getConstant(CCode, MVT::i8);
16118 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16119 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16120 // It should be transformed during dag combiner except when the condition
16121 // is set by a arithmetics with overflow node.
16122 X86::CondCode CCode =
16123 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16124 CCode = X86::GetOppositeBranchCondition(CCode);
16125 CC = DAG.getConstant(CCode, MVT::i8);
16126 Cond = Cond.getOperand(0).getOperand(1);
16128 } else if (Cond.getOpcode() == ISD::SETCC &&
16129 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16130 // For FCMP_OEQ, we can emit
16131 // two branches instead of an explicit AND instruction with a
16132 // separate test. However, we only do this if this block doesn't
16133 // have a fall-through edge, because this requires an explicit
16134 // jmp when the condition is false.
16135 if (Op.getNode()->hasOneUse()) {
16136 SDNode *User = *Op.getNode()->use_begin();
16137 // Look for an unconditional branch following this conditional branch.
16138 // We need this because we need to reverse the successors in order
16139 // to implement FCMP_OEQ.
16140 if (User->getOpcode() == ISD::BR) {
16141 SDValue FalseBB = User->getOperand(1);
16143 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16144 assert(NewBR == User);
16148 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16149 Cond.getOperand(0), Cond.getOperand(1));
16150 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16151 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16152 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16153 Chain, Dest, CC, Cmp);
16154 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16159 } else if (Cond.getOpcode() == ISD::SETCC &&
16160 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16161 // For FCMP_UNE, we can emit
16162 // two branches instead of an explicit AND instruction with a
16163 // separate test. However, we only do this if this block doesn't
16164 // have a fall-through edge, because this requires an explicit
16165 // jmp when the condition is false.
16166 if (Op.getNode()->hasOneUse()) {
16167 SDNode *User = *Op.getNode()->use_begin();
16168 // Look for an unconditional branch following this conditional branch.
16169 // We need this because we need to reverse the successors in order
16170 // to implement FCMP_UNE.
16171 if (User->getOpcode() == ISD::BR) {
16172 SDValue FalseBB = User->getOperand(1);
16174 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16175 assert(NewBR == User);
16178 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16179 Cond.getOperand(0), Cond.getOperand(1));
16180 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16181 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16182 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16183 Chain, Dest, CC, Cmp);
16184 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16194 // Look pass the truncate if the high bits are known zero.
16195 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16196 Cond = Cond.getOperand(0);
16198 // We know the result of AND is compared against zero. Try to match
16200 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16201 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16202 if (NewSetCC.getNode()) {
16203 CC = NewSetCC.getOperand(0);
16204 Cond = NewSetCC.getOperand(1);
16211 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16212 CC = DAG.getConstant(X86Cond, MVT::i8);
16213 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16215 Cond = ConvertCmpIfNecessary(Cond, DAG);
16216 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16217 Chain, Dest, CC, Cond);
16220 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16221 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16222 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16223 // that the guard pages used by the OS virtual memory manager are allocated in
16224 // correct sequence.
16226 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16227 SelectionDAG &DAG) const {
16228 MachineFunction &MF = DAG.getMachineFunction();
16229 bool SplitStack = MF.shouldSplitStack();
16230 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16236 SDNode* Node = Op.getNode();
16238 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16239 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16240 " not tell us which reg is the stack pointer!");
16241 EVT VT = Node->getValueType(0);
16242 SDValue Tmp1 = SDValue(Node, 0);
16243 SDValue Tmp2 = SDValue(Node, 1);
16244 SDValue Tmp3 = Node->getOperand(2);
16245 SDValue Chain = Tmp1.getOperand(0);
16247 // Chain the dynamic stack allocation so that it doesn't modify the stack
16248 // pointer when other instructions are using the stack.
16249 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16252 SDValue Size = Tmp2.getOperand(1);
16253 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16254 Chain = SP.getValue(1);
16255 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16256 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16257 unsigned StackAlign = TFI.getStackAlignment();
16258 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16259 if (Align > StackAlign)
16260 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16261 DAG.getConstant(-(uint64_t)Align, VT));
16262 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16264 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16265 DAG.getIntPtrConstant(0, true), SDValue(),
16268 SDValue Ops[2] = { Tmp1, Tmp2 };
16269 return DAG.getMergeValues(Ops, dl);
16273 SDValue Chain = Op.getOperand(0);
16274 SDValue Size = Op.getOperand(1);
16275 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16276 EVT VT = Op.getNode()->getValueType(0);
16278 bool Is64Bit = Subtarget->is64Bit();
16279 EVT SPTy = getPointerTy();
16282 MachineRegisterInfo &MRI = MF.getRegInfo();
16285 // The 64 bit implementation of segmented stacks needs to clobber both r10
16286 // r11. This makes it impossible to use it along with nested parameters.
16287 const Function *F = MF.getFunction();
16289 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16291 if (I->hasNestAttr())
16292 report_fatal_error("Cannot use segmented stacks with functions that "
16293 "have nested arguments.");
16296 const TargetRegisterClass *AddrRegClass =
16297 getRegClassFor(getPointerTy());
16298 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16299 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16300 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16301 DAG.getRegister(Vreg, SPTy));
16302 SDValue Ops1[2] = { Value, Chain };
16303 return DAG.getMergeValues(Ops1, dl);
16306 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16308 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16309 Flag = Chain.getValue(1);
16310 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16312 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16314 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16315 DAG.getSubtarget().getRegisterInfo());
16316 unsigned SPReg = RegInfo->getStackRegister();
16317 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16318 Chain = SP.getValue(1);
16321 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16322 DAG.getConstant(-(uint64_t)Align, VT));
16323 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16326 SDValue Ops1[2] = { SP, Chain };
16327 return DAG.getMergeValues(Ops1, dl);
16331 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16332 MachineFunction &MF = DAG.getMachineFunction();
16333 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16335 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16338 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16339 // vastart just stores the address of the VarArgsFrameIndex slot into the
16340 // memory location argument.
16341 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16343 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16344 MachinePointerInfo(SV), false, false, 0);
16348 // gp_offset (0 - 6 * 8)
16349 // fp_offset (48 - 48 + 8 * 16)
16350 // overflow_arg_area (point to parameters coming in memory).
16352 SmallVector<SDValue, 8> MemOps;
16353 SDValue FIN = Op.getOperand(1);
16355 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16356 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16358 FIN, MachinePointerInfo(SV), false, false, 0);
16359 MemOps.push_back(Store);
16362 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16363 FIN, DAG.getIntPtrConstant(4));
16364 Store = DAG.getStore(Op.getOperand(0), DL,
16365 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16367 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16368 MemOps.push_back(Store);
16370 // Store ptr to overflow_arg_area
16371 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16372 FIN, DAG.getIntPtrConstant(4));
16373 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16375 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16376 MachinePointerInfo(SV, 8),
16378 MemOps.push_back(Store);
16380 // Store ptr to reg_save_area.
16381 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16382 FIN, DAG.getIntPtrConstant(8));
16383 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16385 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16386 MachinePointerInfo(SV, 16), false, false, 0);
16387 MemOps.push_back(Store);
16388 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16391 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16392 assert(Subtarget->is64Bit() &&
16393 "LowerVAARG only handles 64-bit va_arg!");
16394 assert((Subtarget->isTargetLinux() ||
16395 Subtarget->isTargetDarwin()) &&
16396 "Unhandled target in LowerVAARG");
16397 assert(Op.getNode()->getNumOperands() == 4);
16398 SDValue Chain = Op.getOperand(0);
16399 SDValue SrcPtr = Op.getOperand(1);
16400 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16401 unsigned Align = Op.getConstantOperandVal(3);
16404 EVT ArgVT = Op.getNode()->getValueType(0);
16405 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16406 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16409 // Decide which area this value should be read from.
16410 // TODO: Implement the AMD64 ABI in its entirety. This simple
16411 // selection mechanism works only for the basic types.
16412 if (ArgVT == MVT::f80) {
16413 llvm_unreachable("va_arg for f80 not yet implemented");
16414 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16415 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16416 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16417 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16419 llvm_unreachable("Unhandled argument type in LowerVAARG");
16422 if (ArgMode == 2) {
16423 // Sanity Check: Make sure using fp_offset makes sense.
16424 assert(!DAG.getTarget().Options.UseSoftFloat &&
16425 !(DAG.getMachineFunction()
16426 .getFunction()->getAttributes()
16427 .hasAttribute(AttributeSet::FunctionIndex,
16428 Attribute::NoImplicitFloat)) &&
16429 Subtarget->hasSSE1());
16432 // Insert VAARG_64 node into the DAG
16433 // VAARG_64 returns two values: Variable Argument Address, Chain
16434 SmallVector<SDValue, 11> InstOps;
16435 InstOps.push_back(Chain);
16436 InstOps.push_back(SrcPtr);
16437 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16438 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16439 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16440 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16441 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16442 VTs, InstOps, MVT::i64,
16443 MachinePointerInfo(SV),
16445 /*Volatile=*/false,
16447 /*WriteMem=*/true);
16448 Chain = VAARG.getValue(1);
16450 // Load the next argument and return it
16451 return DAG.getLoad(ArgVT, dl,
16454 MachinePointerInfo(),
16455 false, false, false, 0);
16458 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16459 SelectionDAG &DAG) {
16460 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16461 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16462 SDValue Chain = Op.getOperand(0);
16463 SDValue DstPtr = Op.getOperand(1);
16464 SDValue SrcPtr = Op.getOperand(2);
16465 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16466 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16469 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16470 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16472 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16475 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16476 // amount is a constant. Takes immediate version of shift as input.
16477 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16478 SDValue SrcOp, uint64_t ShiftAmt,
16479 SelectionDAG &DAG) {
16480 MVT ElementType = VT.getVectorElementType();
16482 // Fold this packed shift into its first operand if ShiftAmt is 0.
16486 // Check for ShiftAmt >= element width
16487 if (ShiftAmt >= ElementType.getSizeInBits()) {
16488 if (Opc == X86ISD::VSRAI)
16489 ShiftAmt = ElementType.getSizeInBits() - 1;
16491 return DAG.getConstant(0, VT);
16494 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16495 && "Unknown target vector shift-by-constant node");
16497 // Fold this packed vector shift into a build vector if SrcOp is a
16498 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16499 if (VT == SrcOp.getSimpleValueType() &&
16500 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16501 SmallVector<SDValue, 8> Elts;
16502 unsigned NumElts = SrcOp->getNumOperands();
16503 ConstantSDNode *ND;
16506 default: llvm_unreachable(nullptr);
16507 case X86ISD::VSHLI:
16508 for (unsigned i=0; i!=NumElts; ++i) {
16509 SDValue CurrentOp = SrcOp->getOperand(i);
16510 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16511 Elts.push_back(CurrentOp);
16514 ND = cast<ConstantSDNode>(CurrentOp);
16515 const APInt &C = ND->getAPIntValue();
16516 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16519 case X86ISD::VSRLI:
16520 for (unsigned i=0; i!=NumElts; ++i) {
16521 SDValue CurrentOp = SrcOp->getOperand(i);
16522 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16523 Elts.push_back(CurrentOp);
16526 ND = cast<ConstantSDNode>(CurrentOp);
16527 const APInt &C = ND->getAPIntValue();
16528 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16531 case X86ISD::VSRAI:
16532 for (unsigned i=0; i!=NumElts; ++i) {
16533 SDValue CurrentOp = SrcOp->getOperand(i);
16534 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16535 Elts.push_back(CurrentOp);
16538 ND = cast<ConstantSDNode>(CurrentOp);
16539 const APInt &C = ND->getAPIntValue();
16540 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16545 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16548 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16551 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16552 // may or may not be a constant. Takes immediate version of shift as input.
16553 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16554 SDValue SrcOp, SDValue ShAmt,
16555 SelectionDAG &DAG) {
16556 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16558 // Catch shift-by-constant.
16559 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16560 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16561 CShAmt->getZExtValue(), DAG);
16563 // Change opcode to non-immediate version
16565 default: llvm_unreachable("Unknown target vector shift node");
16566 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16567 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16568 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16571 // Need to build a vector containing shift amount
16572 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16575 ShOps[1] = DAG.getConstant(0, MVT::i32);
16576 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16577 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16579 // The return type has to be a 128-bit type with the same element
16580 // type as the input type.
16581 MVT EltVT = VT.getVectorElementType();
16582 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16584 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16585 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16588 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16589 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16590 /// necessary casting for \p Mask when lowering masking intrinsics.
16591 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16592 SDValue PreservedSrc,
16593 const X86Subtarget *Subtarget,
16594 SelectionDAG &DAG) {
16595 EVT VT = Op.getValueType();
16596 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16597 MVT::i1, VT.getVectorNumElements());
16598 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16599 Mask.getValueType().getSizeInBits());
16602 assert(MaskVT.isSimple() && "invalid mask type");
16604 if (isAllOnes(Mask))
16607 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16608 // are extracted by EXTRACT_SUBVECTOR.
16609 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16610 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16611 DAG.getIntPtrConstant(0));
16613 switch (Op.getOpcode()) {
16615 case X86ISD::PCMPEQM:
16616 case X86ISD::PCMPGTM:
16618 case X86ISD::CMPMU:
16619 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16621 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16622 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16623 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16626 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16628 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16629 case Intrinsic::x86_fma_vfmadd_ps:
16630 case Intrinsic::x86_fma_vfmadd_pd:
16631 case Intrinsic::x86_fma_vfmadd_ps_256:
16632 case Intrinsic::x86_fma_vfmadd_pd_256:
16633 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16634 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16635 return X86ISD::FMADD;
16636 case Intrinsic::x86_fma_vfmsub_ps:
16637 case Intrinsic::x86_fma_vfmsub_pd:
16638 case Intrinsic::x86_fma_vfmsub_ps_256:
16639 case Intrinsic::x86_fma_vfmsub_pd_256:
16640 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16641 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16642 return X86ISD::FMSUB;
16643 case Intrinsic::x86_fma_vfnmadd_ps:
16644 case Intrinsic::x86_fma_vfnmadd_pd:
16645 case Intrinsic::x86_fma_vfnmadd_ps_256:
16646 case Intrinsic::x86_fma_vfnmadd_pd_256:
16647 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16648 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16649 return X86ISD::FNMADD;
16650 case Intrinsic::x86_fma_vfnmsub_ps:
16651 case Intrinsic::x86_fma_vfnmsub_pd:
16652 case Intrinsic::x86_fma_vfnmsub_ps_256:
16653 case Intrinsic::x86_fma_vfnmsub_pd_256:
16654 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16655 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16656 return X86ISD::FNMSUB;
16657 case Intrinsic::x86_fma_vfmaddsub_ps:
16658 case Intrinsic::x86_fma_vfmaddsub_pd:
16659 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16660 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16661 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16662 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16663 return X86ISD::FMADDSUB;
16664 case Intrinsic::x86_fma_vfmsubadd_ps:
16665 case Intrinsic::x86_fma_vfmsubadd_pd:
16666 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16667 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16668 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16669 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16670 return X86ISD::FMSUBADD;
16674 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16675 SelectionDAG &DAG) {
16677 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16678 EVT VT = Op.getValueType();
16679 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16681 switch(IntrData->Type) {
16682 case INTR_TYPE_1OP:
16683 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16684 case INTR_TYPE_2OP:
16685 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16687 case INTR_TYPE_3OP:
16688 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16689 Op.getOperand(2), Op.getOperand(3));
16690 case INTR_TYPE_1OP_MASK_RM: {
16691 SDValue Src = Op.getOperand(1);
16692 SDValue Src0 = Op.getOperand(2);
16693 SDValue Mask = Op.getOperand(3);
16694 SDValue RoundingMode = Op.getOperand(4);
16695 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16697 Mask, Src0, Subtarget, DAG);
16701 case CMP_MASK_CC: {
16702 // Comparison intrinsics with masks.
16703 // Example of transformation:
16704 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16705 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16707 // (v8i1 (insert_subvector undef,
16708 // (v2i1 (and (PCMPEQM %a, %b),
16709 // (extract_subvector
16710 // (v8i1 (bitcast %mask)), 0))), 0))))
16711 EVT VT = Op.getOperand(1).getValueType();
16712 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16713 VT.getVectorNumElements());
16714 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16715 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16716 Mask.getValueType().getSizeInBits());
16718 if (IntrData->Type == CMP_MASK_CC) {
16719 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16720 Op.getOperand(2), Op.getOperand(3));
16722 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16723 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16726 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16727 DAG.getTargetConstant(0, MaskVT),
16729 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16730 DAG.getUNDEF(BitcastVT), CmpMask,
16731 DAG.getIntPtrConstant(0));
16732 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16734 case COMI: { // Comparison intrinsics
16735 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16736 SDValue LHS = Op.getOperand(1);
16737 SDValue RHS = Op.getOperand(2);
16738 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16739 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16740 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16741 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16742 DAG.getConstant(X86CC, MVT::i8), Cond);
16743 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16746 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16747 Op.getOperand(1), Op.getOperand(2), DAG);
16749 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16750 Op.getOperand(1), Op.getOperand(2), DAG),
16751 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16758 default: return SDValue(); // Don't custom lower most intrinsics.
16760 // Arithmetic intrinsics.
16761 case Intrinsic::x86_sse2_pmulu_dq:
16762 case Intrinsic::x86_avx2_pmulu_dq:
16763 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16764 Op.getOperand(1), Op.getOperand(2));
16766 case Intrinsic::x86_sse41_pmuldq:
16767 case Intrinsic::x86_avx2_pmul_dq:
16768 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16769 Op.getOperand(1), Op.getOperand(2));
16771 case Intrinsic::x86_sse2_pmulhu_w:
16772 case Intrinsic::x86_avx2_pmulhu_w:
16773 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16774 Op.getOperand(1), Op.getOperand(2));
16776 case Intrinsic::x86_sse2_pmulh_w:
16777 case Intrinsic::x86_avx2_pmulh_w:
16778 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16779 Op.getOperand(1), Op.getOperand(2));
16781 // SSE/SSE2/AVX floating point max/min intrinsics.
16782 case Intrinsic::x86_sse_max_ps:
16783 case Intrinsic::x86_sse2_max_pd:
16784 case Intrinsic::x86_avx_max_ps_256:
16785 case Intrinsic::x86_avx_max_pd_256:
16786 case Intrinsic::x86_sse_min_ps:
16787 case Intrinsic::x86_sse2_min_pd:
16788 case Intrinsic::x86_avx_min_ps_256:
16789 case Intrinsic::x86_avx_min_pd_256: {
16792 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16793 case Intrinsic::x86_sse_max_ps:
16794 case Intrinsic::x86_sse2_max_pd:
16795 case Intrinsic::x86_avx_max_ps_256:
16796 case Intrinsic::x86_avx_max_pd_256:
16797 Opcode = X86ISD::FMAX;
16799 case Intrinsic::x86_sse_min_ps:
16800 case Intrinsic::x86_sse2_min_pd:
16801 case Intrinsic::x86_avx_min_ps_256:
16802 case Intrinsic::x86_avx_min_pd_256:
16803 Opcode = X86ISD::FMIN;
16806 return DAG.getNode(Opcode, dl, Op.getValueType(),
16807 Op.getOperand(1), Op.getOperand(2));
16810 // AVX2 variable shift intrinsics
16811 case Intrinsic::x86_avx2_psllv_d:
16812 case Intrinsic::x86_avx2_psllv_q:
16813 case Intrinsic::x86_avx2_psllv_d_256:
16814 case Intrinsic::x86_avx2_psllv_q_256:
16815 case Intrinsic::x86_avx2_psrlv_d:
16816 case Intrinsic::x86_avx2_psrlv_q:
16817 case Intrinsic::x86_avx2_psrlv_d_256:
16818 case Intrinsic::x86_avx2_psrlv_q_256:
16819 case Intrinsic::x86_avx2_psrav_d:
16820 case Intrinsic::x86_avx2_psrav_d_256: {
16823 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16824 case Intrinsic::x86_avx2_psllv_d:
16825 case Intrinsic::x86_avx2_psllv_q:
16826 case Intrinsic::x86_avx2_psllv_d_256:
16827 case Intrinsic::x86_avx2_psllv_q_256:
16830 case Intrinsic::x86_avx2_psrlv_d:
16831 case Intrinsic::x86_avx2_psrlv_q:
16832 case Intrinsic::x86_avx2_psrlv_d_256:
16833 case Intrinsic::x86_avx2_psrlv_q_256:
16836 case Intrinsic::x86_avx2_psrav_d:
16837 case Intrinsic::x86_avx2_psrav_d_256:
16841 return DAG.getNode(Opcode, dl, Op.getValueType(),
16842 Op.getOperand(1), Op.getOperand(2));
16845 case Intrinsic::x86_sse2_packssdw_128:
16846 case Intrinsic::x86_sse2_packsswb_128:
16847 case Intrinsic::x86_avx2_packssdw:
16848 case Intrinsic::x86_avx2_packsswb:
16849 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16850 Op.getOperand(1), Op.getOperand(2));
16852 case Intrinsic::x86_sse2_packuswb_128:
16853 case Intrinsic::x86_sse41_packusdw:
16854 case Intrinsic::x86_avx2_packuswb:
16855 case Intrinsic::x86_avx2_packusdw:
16856 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16857 Op.getOperand(1), Op.getOperand(2));
16859 case Intrinsic::x86_ssse3_pshuf_b_128:
16860 case Intrinsic::x86_avx2_pshuf_b:
16861 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16862 Op.getOperand(1), Op.getOperand(2));
16864 case Intrinsic::x86_sse2_pshuf_d:
16865 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16866 Op.getOperand(1), Op.getOperand(2));
16868 case Intrinsic::x86_sse2_pshufl_w:
16869 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16870 Op.getOperand(1), Op.getOperand(2));
16872 case Intrinsic::x86_sse2_pshufh_w:
16873 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16874 Op.getOperand(1), Op.getOperand(2));
16876 case Intrinsic::x86_ssse3_psign_b_128:
16877 case Intrinsic::x86_ssse3_psign_w_128:
16878 case Intrinsic::x86_ssse3_psign_d_128:
16879 case Intrinsic::x86_avx2_psign_b:
16880 case Intrinsic::x86_avx2_psign_w:
16881 case Intrinsic::x86_avx2_psign_d:
16882 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16883 Op.getOperand(1), Op.getOperand(2));
16885 case Intrinsic::x86_avx2_permd:
16886 case Intrinsic::x86_avx2_permps:
16887 // Operands intentionally swapped. Mask is last operand to intrinsic,
16888 // but second operand for node/instruction.
16889 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16890 Op.getOperand(2), Op.getOperand(1));
16892 case Intrinsic::x86_avx512_mask_valign_q_512:
16893 case Intrinsic::x86_avx512_mask_valign_d_512:
16894 // Vector source operands are swapped.
16895 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16896 Op.getValueType(), Op.getOperand(2),
16899 Op.getOperand(5), Op.getOperand(4),
16902 // ptest and testp intrinsics. The intrinsic these come from are designed to
16903 // return an integer value, not just an instruction so lower it to the ptest
16904 // or testp pattern and a setcc for the result.
16905 case Intrinsic::x86_sse41_ptestz:
16906 case Intrinsic::x86_sse41_ptestc:
16907 case Intrinsic::x86_sse41_ptestnzc:
16908 case Intrinsic::x86_avx_ptestz_256:
16909 case Intrinsic::x86_avx_ptestc_256:
16910 case Intrinsic::x86_avx_ptestnzc_256:
16911 case Intrinsic::x86_avx_vtestz_ps:
16912 case Intrinsic::x86_avx_vtestc_ps:
16913 case Intrinsic::x86_avx_vtestnzc_ps:
16914 case Intrinsic::x86_avx_vtestz_pd:
16915 case Intrinsic::x86_avx_vtestc_pd:
16916 case Intrinsic::x86_avx_vtestnzc_pd:
16917 case Intrinsic::x86_avx_vtestz_ps_256:
16918 case Intrinsic::x86_avx_vtestc_ps_256:
16919 case Intrinsic::x86_avx_vtestnzc_ps_256:
16920 case Intrinsic::x86_avx_vtestz_pd_256:
16921 case Intrinsic::x86_avx_vtestc_pd_256:
16922 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16923 bool IsTestPacked = false;
16926 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16927 case Intrinsic::x86_avx_vtestz_ps:
16928 case Intrinsic::x86_avx_vtestz_pd:
16929 case Intrinsic::x86_avx_vtestz_ps_256:
16930 case Intrinsic::x86_avx_vtestz_pd_256:
16931 IsTestPacked = true; // Fallthrough
16932 case Intrinsic::x86_sse41_ptestz:
16933 case Intrinsic::x86_avx_ptestz_256:
16935 X86CC = X86::COND_E;
16937 case Intrinsic::x86_avx_vtestc_ps:
16938 case Intrinsic::x86_avx_vtestc_pd:
16939 case Intrinsic::x86_avx_vtestc_ps_256:
16940 case Intrinsic::x86_avx_vtestc_pd_256:
16941 IsTestPacked = true; // Fallthrough
16942 case Intrinsic::x86_sse41_ptestc:
16943 case Intrinsic::x86_avx_ptestc_256:
16945 X86CC = X86::COND_B;
16947 case Intrinsic::x86_avx_vtestnzc_ps:
16948 case Intrinsic::x86_avx_vtestnzc_pd:
16949 case Intrinsic::x86_avx_vtestnzc_ps_256:
16950 case Intrinsic::x86_avx_vtestnzc_pd_256:
16951 IsTestPacked = true; // Fallthrough
16952 case Intrinsic::x86_sse41_ptestnzc:
16953 case Intrinsic::x86_avx_ptestnzc_256:
16955 X86CC = X86::COND_A;
16959 SDValue LHS = Op.getOperand(1);
16960 SDValue RHS = Op.getOperand(2);
16961 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16962 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16963 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16964 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16965 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16967 case Intrinsic::x86_avx512_kortestz_w:
16968 case Intrinsic::x86_avx512_kortestc_w: {
16969 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16970 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16971 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16972 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16973 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16974 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16975 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16978 case Intrinsic::x86_sse42_pcmpistria128:
16979 case Intrinsic::x86_sse42_pcmpestria128:
16980 case Intrinsic::x86_sse42_pcmpistric128:
16981 case Intrinsic::x86_sse42_pcmpestric128:
16982 case Intrinsic::x86_sse42_pcmpistrio128:
16983 case Intrinsic::x86_sse42_pcmpestrio128:
16984 case Intrinsic::x86_sse42_pcmpistris128:
16985 case Intrinsic::x86_sse42_pcmpestris128:
16986 case Intrinsic::x86_sse42_pcmpistriz128:
16987 case Intrinsic::x86_sse42_pcmpestriz128: {
16991 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16992 case Intrinsic::x86_sse42_pcmpistria128:
16993 Opcode = X86ISD::PCMPISTRI;
16994 X86CC = X86::COND_A;
16996 case Intrinsic::x86_sse42_pcmpestria128:
16997 Opcode = X86ISD::PCMPESTRI;
16998 X86CC = X86::COND_A;
17000 case Intrinsic::x86_sse42_pcmpistric128:
17001 Opcode = X86ISD::PCMPISTRI;
17002 X86CC = X86::COND_B;
17004 case Intrinsic::x86_sse42_pcmpestric128:
17005 Opcode = X86ISD::PCMPESTRI;
17006 X86CC = X86::COND_B;
17008 case Intrinsic::x86_sse42_pcmpistrio128:
17009 Opcode = X86ISD::PCMPISTRI;
17010 X86CC = X86::COND_O;
17012 case Intrinsic::x86_sse42_pcmpestrio128:
17013 Opcode = X86ISD::PCMPESTRI;
17014 X86CC = X86::COND_O;
17016 case Intrinsic::x86_sse42_pcmpistris128:
17017 Opcode = X86ISD::PCMPISTRI;
17018 X86CC = X86::COND_S;
17020 case Intrinsic::x86_sse42_pcmpestris128:
17021 Opcode = X86ISD::PCMPESTRI;
17022 X86CC = X86::COND_S;
17024 case Intrinsic::x86_sse42_pcmpistriz128:
17025 Opcode = X86ISD::PCMPISTRI;
17026 X86CC = X86::COND_E;
17028 case Intrinsic::x86_sse42_pcmpestriz128:
17029 Opcode = X86ISD::PCMPESTRI;
17030 X86CC = X86::COND_E;
17033 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17034 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17035 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17036 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17037 DAG.getConstant(X86CC, MVT::i8),
17038 SDValue(PCMP.getNode(), 1));
17039 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17042 case Intrinsic::x86_sse42_pcmpistri128:
17043 case Intrinsic::x86_sse42_pcmpestri128: {
17045 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17046 Opcode = X86ISD::PCMPISTRI;
17048 Opcode = X86ISD::PCMPESTRI;
17050 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17051 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17052 return DAG.getNode(Opcode, dl, VTs, NewOps);
17055 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17056 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17057 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17058 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17059 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17060 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17061 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17062 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17063 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17064 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17065 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17066 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17067 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17068 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17069 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17070 dl, Op.getValueType(),
17074 Op.getOperand(4), Op.getOperand(1),
17080 case Intrinsic::x86_fma_vfmadd_ps:
17081 case Intrinsic::x86_fma_vfmadd_pd:
17082 case Intrinsic::x86_fma_vfmsub_ps:
17083 case Intrinsic::x86_fma_vfmsub_pd:
17084 case Intrinsic::x86_fma_vfnmadd_ps:
17085 case Intrinsic::x86_fma_vfnmadd_pd:
17086 case Intrinsic::x86_fma_vfnmsub_ps:
17087 case Intrinsic::x86_fma_vfnmsub_pd:
17088 case Intrinsic::x86_fma_vfmaddsub_ps:
17089 case Intrinsic::x86_fma_vfmaddsub_pd:
17090 case Intrinsic::x86_fma_vfmsubadd_ps:
17091 case Intrinsic::x86_fma_vfmsubadd_pd:
17092 case Intrinsic::x86_fma_vfmadd_ps_256:
17093 case Intrinsic::x86_fma_vfmadd_pd_256:
17094 case Intrinsic::x86_fma_vfmsub_ps_256:
17095 case Intrinsic::x86_fma_vfmsub_pd_256:
17096 case Intrinsic::x86_fma_vfnmadd_ps_256:
17097 case Intrinsic::x86_fma_vfnmadd_pd_256:
17098 case Intrinsic::x86_fma_vfnmsub_ps_256:
17099 case Intrinsic::x86_fma_vfnmsub_pd_256:
17100 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17101 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17102 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17103 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17104 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17105 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17109 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17110 SDValue Src, SDValue Mask, SDValue Base,
17111 SDValue Index, SDValue ScaleOp, SDValue Chain,
17112 const X86Subtarget * Subtarget) {
17114 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17115 assert(C && "Invalid scale type");
17116 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17117 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17118 Index.getSimpleValueType().getVectorNumElements());
17120 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17122 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17124 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17125 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17126 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17127 SDValue Segment = DAG.getRegister(0, MVT::i32);
17128 if (Src.getOpcode() == ISD::UNDEF)
17129 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17130 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17131 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17132 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17133 return DAG.getMergeValues(RetOps, dl);
17136 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17137 SDValue Src, SDValue Mask, SDValue Base,
17138 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17140 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17141 assert(C && "Invalid scale type");
17142 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17143 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17144 SDValue Segment = DAG.getRegister(0, MVT::i32);
17145 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17146 Index.getSimpleValueType().getVectorNumElements());
17148 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17150 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17152 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17153 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17154 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17155 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17156 return SDValue(Res, 1);
17159 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17160 SDValue Mask, SDValue Base, SDValue Index,
17161 SDValue ScaleOp, SDValue Chain) {
17163 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17164 assert(C && "Invalid scale type");
17165 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17166 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17167 SDValue Segment = DAG.getRegister(0, MVT::i32);
17169 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17171 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17173 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17175 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17176 //SDVTList VTs = DAG.getVTList(MVT::Other);
17177 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17178 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17179 return SDValue(Res, 0);
17182 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17183 // read performance monitor counters (x86_rdpmc).
17184 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17185 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17186 SmallVectorImpl<SDValue> &Results) {
17187 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17188 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17191 // The ECX register is used to select the index of the performance counter
17193 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17195 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17197 // Reads the content of a 64-bit performance counter and returns it in the
17198 // registers EDX:EAX.
17199 if (Subtarget->is64Bit()) {
17200 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17201 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17204 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17205 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17208 Chain = HI.getValue(1);
17210 if (Subtarget->is64Bit()) {
17211 // The EAX register is loaded with the low-order 32 bits. The EDX register
17212 // is loaded with the supported high-order bits of the counter.
17213 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17214 DAG.getConstant(32, MVT::i8));
17215 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17216 Results.push_back(Chain);
17220 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17221 SDValue Ops[] = { LO, HI };
17222 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17223 Results.push_back(Pair);
17224 Results.push_back(Chain);
17227 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17228 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17229 // also used to custom lower READCYCLECOUNTER nodes.
17230 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17231 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17232 SmallVectorImpl<SDValue> &Results) {
17233 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17234 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17237 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17238 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17239 // and the EAX register is loaded with the low-order 32 bits.
17240 if (Subtarget->is64Bit()) {
17241 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17242 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17245 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17246 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17249 SDValue Chain = HI.getValue(1);
17251 if (Opcode == X86ISD::RDTSCP_DAG) {
17252 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17254 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17255 // the ECX register. Add 'ecx' explicitly to the chain.
17256 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17258 // Explicitly store the content of ECX at the location passed in input
17259 // to the 'rdtscp' intrinsic.
17260 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17261 MachinePointerInfo(), false, false, 0);
17264 if (Subtarget->is64Bit()) {
17265 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17266 // the EAX register is loaded with the low-order 32 bits.
17267 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17268 DAG.getConstant(32, MVT::i8));
17269 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17270 Results.push_back(Chain);
17274 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17275 SDValue Ops[] = { LO, HI };
17276 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17277 Results.push_back(Pair);
17278 Results.push_back(Chain);
17281 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17282 SelectionDAG &DAG) {
17283 SmallVector<SDValue, 2> Results;
17285 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17287 return DAG.getMergeValues(Results, DL);
17291 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17292 SelectionDAG &DAG) {
17293 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17295 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17300 switch(IntrData->Type) {
17302 llvm_unreachable("Unknown Intrinsic Type");
17306 // Emit the node with the right value type.
17307 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17308 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17310 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17311 // Otherwise return the value from Rand, which is always 0, casted to i32.
17312 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17313 DAG.getConstant(1, Op->getValueType(1)),
17314 DAG.getConstant(X86::COND_B, MVT::i32),
17315 SDValue(Result.getNode(), 1) };
17316 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17317 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17320 // Return { result, isValid, chain }.
17321 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17322 SDValue(Result.getNode(), 2));
17325 //gather(v1, mask, index, base, scale);
17326 SDValue Chain = Op.getOperand(0);
17327 SDValue Src = Op.getOperand(2);
17328 SDValue Base = Op.getOperand(3);
17329 SDValue Index = Op.getOperand(4);
17330 SDValue Mask = Op.getOperand(5);
17331 SDValue Scale = Op.getOperand(6);
17332 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17336 //scatter(base, mask, index, v1, scale);
17337 SDValue Chain = Op.getOperand(0);
17338 SDValue Base = Op.getOperand(2);
17339 SDValue Mask = Op.getOperand(3);
17340 SDValue Index = Op.getOperand(4);
17341 SDValue Src = Op.getOperand(5);
17342 SDValue Scale = Op.getOperand(6);
17343 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17346 SDValue Hint = Op.getOperand(6);
17348 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17349 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17350 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17351 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17352 SDValue Chain = Op.getOperand(0);
17353 SDValue Mask = Op.getOperand(2);
17354 SDValue Index = Op.getOperand(3);
17355 SDValue Base = Op.getOperand(4);
17356 SDValue Scale = Op.getOperand(5);
17357 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17359 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17361 SmallVector<SDValue, 2> Results;
17362 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17363 return DAG.getMergeValues(Results, dl);
17365 // Read Performance Monitoring Counters.
17367 SmallVector<SDValue, 2> Results;
17368 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17369 return DAG.getMergeValues(Results, dl);
17371 // XTEST intrinsics.
17373 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17374 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17375 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17376 DAG.getConstant(X86::COND_NE, MVT::i8),
17378 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17379 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17380 Ret, SDValue(InTrans.getNode(), 1));
17384 SmallVector<SDValue, 2> Results;
17385 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17386 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17387 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17388 DAG.getConstant(-1, MVT::i8));
17389 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17390 Op.getOperand(4), GenCF.getValue(1));
17391 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17392 Op.getOperand(5), MachinePointerInfo(),
17394 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17395 DAG.getConstant(X86::COND_B, MVT::i8),
17397 Results.push_back(SetCC);
17398 Results.push_back(Store);
17399 return DAG.getMergeValues(Results, dl);
17404 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17405 SelectionDAG &DAG) const {
17406 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17407 MFI->setReturnAddressIsTaken(true);
17409 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17412 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17414 EVT PtrVT = getPointerTy();
17417 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17418 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17419 DAG.getSubtarget().getRegisterInfo());
17420 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17421 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17422 DAG.getNode(ISD::ADD, dl, PtrVT,
17423 FrameAddr, Offset),
17424 MachinePointerInfo(), false, false, false, 0);
17427 // Just load the return address.
17428 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17429 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17430 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17433 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17434 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17435 MFI->setFrameAddressIsTaken(true);
17437 EVT VT = Op.getValueType();
17438 SDLoc dl(Op); // FIXME probably not meaningful
17439 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17440 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17441 DAG.getSubtarget().getRegisterInfo());
17442 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17443 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17444 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17445 "Invalid Frame Register!");
17446 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17448 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17449 MachinePointerInfo(),
17450 false, false, false, 0);
17454 // FIXME? Maybe this could be a TableGen attribute on some registers and
17455 // this table could be generated automatically from RegInfo.
17456 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17458 unsigned Reg = StringSwitch<unsigned>(RegName)
17459 .Case("esp", X86::ESP)
17460 .Case("rsp", X86::RSP)
17464 report_fatal_error("Invalid register name global variable");
17467 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17468 SelectionDAG &DAG) const {
17469 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17470 DAG.getSubtarget().getRegisterInfo());
17471 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17474 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17475 SDValue Chain = Op.getOperand(0);
17476 SDValue Offset = Op.getOperand(1);
17477 SDValue Handler = Op.getOperand(2);
17480 EVT PtrVT = getPointerTy();
17481 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17482 DAG.getSubtarget().getRegisterInfo());
17483 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17484 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17485 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17486 "Invalid Frame Register!");
17487 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17488 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17490 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17491 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17492 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17493 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17495 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17497 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17498 DAG.getRegister(StoreAddrReg, PtrVT));
17501 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17502 SelectionDAG &DAG) const {
17504 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17505 DAG.getVTList(MVT::i32, MVT::Other),
17506 Op.getOperand(0), Op.getOperand(1));
17509 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17510 SelectionDAG &DAG) const {
17512 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17513 Op.getOperand(0), Op.getOperand(1));
17516 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17517 return Op.getOperand(0);
17520 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17521 SelectionDAG &DAG) const {
17522 SDValue Root = Op.getOperand(0);
17523 SDValue Trmp = Op.getOperand(1); // trampoline
17524 SDValue FPtr = Op.getOperand(2); // nested function
17525 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17528 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17529 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17531 if (Subtarget->is64Bit()) {
17532 SDValue OutChains[6];
17534 // Large code-model.
17535 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17536 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17538 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17539 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17541 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17543 // Load the pointer to the nested function into R11.
17544 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17545 SDValue Addr = Trmp;
17546 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17547 Addr, MachinePointerInfo(TrmpAddr),
17550 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17551 DAG.getConstant(2, MVT::i64));
17552 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17553 MachinePointerInfo(TrmpAddr, 2),
17556 // Load the 'nest' parameter value into R10.
17557 // R10 is specified in X86CallingConv.td
17558 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17559 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17560 DAG.getConstant(10, MVT::i64));
17561 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17562 Addr, MachinePointerInfo(TrmpAddr, 10),
17565 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17566 DAG.getConstant(12, MVT::i64));
17567 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17568 MachinePointerInfo(TrmpAddr, 12),
17571 // Jump to the nested function.
17572 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17573 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17574 DAG.getConstant(20, MVT::i64));
17575 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17576 Addr, MachinePointerInfo(TrmpAddr, 20),
17579 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17580 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17581 DAG.getConstant(22, MVT::i64));
17582 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17583 MachinePointerInfo(TrmpAddr, 22),
17586 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17588 const Function *Func =
17589 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17590 CallingConv::ID CC = Func->getCallingConv();
17595 llvm_unreachable("Unsupported calling convention");
17596 case CallingConv::C:
17597 case CallingConv::X86_StdCall: {
17598 // Pass 'nest' parameter in ECX.
17599 // Must be kept in sync with X86CallingConv.td
17600 NestReg = X86::ECX;
17602 // Check that ECX wasn't needed by an 'inreg' parameter.
17603 FunctionType *FTy = Func->getFunctionType();
17604 const AttributeSet &Attrs = Func->getAttributes();
17606 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17607 unsigned InRegCount = 0;
17610 for (FunctionType::param_iterator I = FTy->param_begin(),
17611 E = FTy->param_end(); I != E; ++I, ++Idx)
17612 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17613 // FIXME: should only count parameters that are lowered to integers.
17614 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17616 if (InRegCount > 2) {
17617 report_fatal_error("Nest register in use - reduce number of inreg"
17623 case CallingConv::X86_FastCall:
17624 case CallingConv::X86_ThisCall:
17625 case CallingConv::Fast:
17626 // Pass 'nest' parameter in EAX.
17627 // Must be kept in sync with X86CallingConv.td
17628 NestReg = X86::EAX;
17632 SDValue OutChains[4];
17633 SDValue Addr, Disp;
17635 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17636 DAG.getConstant(10, MVT::i32));
17637 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17639 // This is storing the opcode for MOV32ri.
17640 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17641 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17642 OutChains[0] = DAG.getStore(Root, dl,
17643 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17644 Trmp, MachinePointerInfo(TrmpAddr),
17647 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17648 DAG.getConstant(1, MVT::i32));
17649 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17650 MachinePointerInfo(TrmpAddr, 1),
17653 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17654 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17655 DAG.getConstant(5, MVT::i32));
17656 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17657 MachinePointerInfo(TrmpAddr, 5),
17660 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17661 DAG.getConstant(6, MVT::i32));
17662 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17663 MachinePointerInfo(TrmpAddr, 6),
17666 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17670 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17671 SelectionDAG &DAG) const {
17673 The rounding mode is in bits 11:10 of FPSR, and has the following
17675 00 Round to nearest
17680 FLT_ROUNDS, on the other hand, expects the following:
17687 To perform the conversion, we do:
17688 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17691 MachineFunction &MF = DAG.getMachineFunction();
17692 const TargetMachine &TM = MF.getTarget();
17693 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17694 unsigned StackAlignment = TFI.getStackAlignment();
17695 MVT VT = Op.getSimpleValueType();
17698 // Save FP Control Word to stack slot
17699 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17700 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17702 MachineMemOperand *MMO =
17703 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17704 MachineMemOperand::MOStore, 2, 2);
17706 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17707 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17708 DAG.getVTList(MVT::Other),
17709 Ops, MVT::i16, MMO);
17711 // Load FP Control Word from stack slot
17712 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17713 MachinePointerInfo(), false, false, false, 0);
17715 // Transform as necessary
17717 DAG.getNode(ISD::SRL, DL, MVT::i16,
17718 DAG.getNode(ISD::AND, DL, MVT::i16,
17719 CWD, DAG.getConstant(0x800, MVT::i16)),
17720 DAG.getConstant(11, MVT::i8));
17722 DAG.getNode(ISD::SRL, DL, MVT::i16,
17723 DAG.getNode(ISD::AND, DL, MVT::i16,
17724 CWD, DAG.getConstant(0x400, MVT::i16)),
17725 DAG.getConstant(9, MVT::i8));
17728 DAG.getNode(ISD::AND, DL, MVT::i16,
17729 DAG.getNode(ISD::ADD, DL, MVT::i16,
17730 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17731 DAG.getConstant(1, MVT::i16)),
17732 DAG.getConstant(3, MVT::i16));
17734 return DAG.getNode((VT.getSizeInBits() < 16 ?
17735 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17738 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17739 MVT VT = Op.getSimpleValueType();
17741 unsigned NumBits = VT.getSizeInBits();
17744 Op = Op.getOperand(0);
17745 if (VT == MVT::i8) {
17746 // Zero extend to i32 since there is not an i8 bsr.
17748 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17751 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17752 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17753 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17755 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17758 DAG.getConstant(NumBits+NumBits-1, OpVT),
17759 DAG.getConstant(X86::COND_E, MVT::i8),
17762 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17764 // Finally xor with NumBits-1.
17765 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17768 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17772 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17773 MVT VT = Op.getSimpleValueType();
17775 unsigned NumBits = VT.getSizeInBits();
17778 Op = Op.getOperand(0);
17779 if (VT == MVT::i8) {
17780 // Zero extend to i32 since there is not an i8 bsr.
17782 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17785 // Issue a bsr (scan bits in reverse).
17786 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17787 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17789 // And xor with NumBits-1.
17790 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17793 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17797 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17798 MVT VT = Op.getSimpleValueType();
17799 unsigned NumBits = VT.getSizeInBits();
17801 Op = Op.getOperand(0);
17803 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17804 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17805 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17807 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17810 DAG.getConstant(NumBits, VT),
17811 DAG.getConstant(X86::COND_E, MVT::i8),
17814 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17817 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17818 // ones, and then concatenate the result back.
17819 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17820 MVT VT = Op.getSimpleValueType();
17822 assert(VT.is256BitVector() && VT.isInteger() &&
17823 "Unsupported value type for operation");
17825 unsigned NumElems = VT.getVectorNumElements();
17828 // Extract the LHS vectors
17829 SDValue LHS = Op.getOperand(0);
17830 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17831 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17833 // Extract the RHS vectors
17834 SDValue RHS = Op.getOperand(1);
17835 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17836 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17838 MVT EltVT = VT.getVectorElementType();
17839 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17841 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17842 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17843 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17846 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17847 assert(Op.getSimpleValueType().is256BitVector() &&
17848 Op.getSimpleValueType().isInteger() &&
17849 "Only handle AVX 256-bit vector integer operation");
17850 return Lower256IntArith(Op, DAG);
17853 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17854 assert(Op.getSimpleValueType().is256BitVector() &&
17855 Op.getSimpleValueType().isInteger() &&
17856 "Only handle AVX 256-bit vector integer operation");
17857 return Lower256IntArith(Op, DAG);
17860 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17861 SelectionDAG &DAG) {
17863 MVT VT = Op.getSimpleValueType();
17865 // Decompose 256-bit ops into smaller 128-bit ops.
17866 if (VT.is256BitVector() && !Subtarget->hasInt256())
17867 return Lower256IntArith(Op, DAG);
17869 SDValue A = Op.getOperand(0);
17870 SDValue B = Op.getOperand(1);
17872 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17873 if (VT == MVT::v4i32) {
17874 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17875 "Should not custom lower when pmuldq is available!");
17877 // Extract the odd parts.
17878 static const int UnpackMask[] = { 1, -1, 3, -1 };
17879 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17880 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17882 // Multiply the even parts.
17883 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17884 // Now multiply odd parts.
17885 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17887 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17888 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17890 // Merge the two vectors back together with a shuffle. This expands into 2
17892 static const int ShufMask[] = { 0, 4, 2, 6 };
17893 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17896 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17897 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17899 // Ahi = psrlqi(a, 32);
17900 // Bhi = psrlqi(b, 32);
17902 // AloBlo = pmuludq(a, b);
17903 // AloBhi = pmuludq(a, Bhi);
17904 // AhiBlo = pmuludq(Ahi, b);
17906 // AloBhi = psllqi(AloBhi, 32);
17907 // AhiBlo = psllqi(AhiBlo, 32);
17908 // return AloBlo + AloBhi + AhiBlo;
17910 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17911 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17913 // Bit cast to 32-bit vectors for MULUDQ
17914 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17915 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17916 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17917 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17918 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17919 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17921 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17922 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17923 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17925 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17926 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17928 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17929 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17932 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17933 assert(Subtarget->isTargetWin64() && "Unexpected target");
17934 EVT VT = Op.getValueType();
17935 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17936 "Unexpected return type for lowering");
17940 switch (Op->getOpcode()) {
17941 default: llvm_unreachable("Unexpected request for libcall!");
17942 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17943 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17944 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17945 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17946 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17947 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17951 SDValue InChain = DAG.getEntryNode();
17953 TargetLowering::ArgListTy Args;
17954 TargetLowering::ArgListEntry Entry;
17955 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17956 EVT ArgVT = Op->getOperand(i).getValueType();
17957 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17958 "Unexpected argument type for lowering");
17959 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17960 Entry.Node = StackPtr;
17961 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17963 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17964 Entry.Ty = PointerType::get(ArgTy,0);
17965 Entry.isSExt = false;
17966 Entry.isZExt = false;
17967 Args.push_back(Entry);
17970 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17973 TargetLowering::CallLoweringInfo CLI(DAG);
17974 CLI.setDebugLoc(dl).setChain(InChain)
17975 .setCallee(getLibcallCallingConv(LC),
17976 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17977 Callee, std::move(Args), 0)
17978 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17980 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17981 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17984 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17985 SelectionDAG &DAG) {
17986 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17987 EVT VT = Op0.getValueType();
17990 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17991 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17993 // PMULxD operations multiply each even value (starting at 0) of LHS with
17994 // the related value of RHS and produce a widen result.
17995 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17996 // => <2 x i64> <ae|cg>
17998 // In other word, to have all the results, we need to perform two PMULxD:
17999 // 1. one with the even values.
18000 // 2. one with the odd values.
18001 // To achieve #2, with need to place the odd values at an even position.
18003 // Place the odd value at an even position (basically, shift all values 1
18004 // step to the left):
18005 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18006 // <a|b|c|d> => <b|undef|d|undef>
18007 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18008 // <e|f|g|h> => <f|undef|h|undef>
18009 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18011 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18013 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18014 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18016 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18017 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18018 // => <2 x i64> <ae|cg>
18019 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18020 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18021 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18022 // => <2 x i64> <bf|dh>
18023 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18024 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18026 // Shuffle it back into the right order.
18027 SDValue Highs, Lows;
18028 if (VT == MVT::v8i32) {
18029 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18030 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18031 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18032 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18034 const int HighMask[] = {1, 5, 3, 7};
18035 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18036 const int LowMask[] = {0, 4, 2, 6};
18037 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18040 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18041 // unsigned multiply.
18042 if (IsSigned && !Subtarget->hasSSE41()) {
18044 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18045 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18046 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18047 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18048 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18050 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18051 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18054 // The first result of MUL_LOHI is actually the low value, followed by the
18056 SDValue Ops[] = {Lows, Highs};
18057 return DAG.getMergeValues(Ops, dl);
18060 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18061 const X86Subtarget *Subtarget) {
18062 MVT VT = Op.getSimpleValueType();
18064 SDValue R = Op.getOperand(0);
18065 SDValue Amt = Op.getOperand(1);
18067 // Optimize shl/srl/sra with constant shift amount.
18068 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18069 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18070 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18072 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18073 (Subtarget->hasInt256() &&
18074 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18075 (Subtarget->hasAVX512() &&
18076 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18077 if (Op.getOpcode() == ISD::SHL)
18078 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18080 if (Op.getOpcode() == ISD::SRL)
18081 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18083 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18084 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18088 if (VT == MVT::v16i8) {
18089 if (Op.getOpcode() == ISD::SHL) {
18090 // Make a large shift.
18091 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18092 MVT::v8i16, R, ShiftAmt,
18094 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18095 // Zero out the rightmost bits.
18096 SmallVector<SDValue, 16> V(16,
18097 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18099 return DAG.getNode(ISD::AND, dl, VT, SHL,
18100 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18102 if (Op.getOpcode() == ISD::SRL) {
18103 // Make a large shift.
18104 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18105 MVT::v8i16, R, ShiftAmt,
18107 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18108 // Zero out the leftmost bits.
18109 SmallVector<SDValue, 16> V(16,
18110 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18112 return DAG.getNode(ISD::AND, dl, VT, SRL,
18113 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18115 if (Op.getOpcode() == ISD::SRA) {
18116 if (ShiftAmt == 7) {
18117 // R s>> 7 === R s< 0
18118 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18119 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18122 // R s>> a === ((R u>> a) ^ m) - m
18123 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18124 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18126 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18127 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18128 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18131 llvm_unreachable("Unknown shift opcode.");
18134 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18135 if (Op.getOpcode() == ISD::SHL) {
18136 // Make a large shift.
18137 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18138 MVT::v16i16, R, ShiftAmt,
18140 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18141 // Zero out the rightmost bits.
18142 SmallVector<SDValue, 32> V(32,
18143 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18145 return DAG.getNode(ISD::AND, dl, VT, SHL,
18146 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18148 if (Op.getOpcode() == ISD::SRL) {
18149 // Make a large shift.
18150 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18151 MVT::v16i16, R, ShiftAmt,
18153 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18154 // Zero out the leftmost bits.
18155 SmallVector<SDValue, 32> V(32,
18156 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18158 return DAG.getNode(ISD::AND, dl, VT, SRL,
18159 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18161 if (Op.getOpcode() == ISD::SRA) {
18162 if (ShiftAmt == 7) {
18163 // R s>> 7 === R s< 0
18164 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18165 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18168 // R s>> a === ((R u>> a) ^ m) - m
18169 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18170 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18172 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18173 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18174 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18177 llvm_unreachable("Unknown shift opcode.");
18182 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18183 if (!Subtarget->is64Bit() &&
18184 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18185 Amt.getOpcode() == ISD::BITCAST &&
18186 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18187 Amt = Amt.getOperand(0);
18188 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18189 VT.getVectorNumElements();
18190 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18191 uint64_t ShiftAmt = 0;
18192 for (unsigned i = 0; i != Ratio; ++i) {
18193 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18197 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18199 // Check remaining shift amounts.
18200 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18201 uint64_t ShAmt = 0;
18202 for (unsigned j = 0; j != Ratio; ++j) {
18203 ConstantSDNode *C =
18204 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18208 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18210 if (ShAmt != ShiftAmt)
18213 switch (Op.getOpcode()) {
18215 llvm_unreachable("Unknown shift opcode!");
18217 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18220 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18223 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18231 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18232 const X86Subtarget* Subtarget) {
18233 MVT VT = Op.getSimpleValueType();
18235 SDValue R = Op.getOperand(0);
18236 SDValue Amt = Op.getOperand(1);
18238 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18239 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18240 (Subtarget->hasInt256() &&
18241 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18242 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18243 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18245 EVT EltVT = VT.getVectorElementType();
18247 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18248 unsigned NumElts = VT.getVectorNumElements();
18250 for (i = 0; i != NumElts; ++i) {
18251 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18255 for (j = i; j != NumElts; ++j) {
18256 SDValue Arg = Amt.getOperand(j);
18257 if (Arg.getOpcode() == ISD::UNDEF) continue;
18258 if (Arg != Amt.getOperand(i))
18261 if (i != NumElts && j == NumElts)
18262 BaseShAmt = Amt.getOperand(i);
18264 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18265 Amt = Amt.getOperand(0);
18266 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18267 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18268 SDValue InVec = Amt.getOperand(0);
18269 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18270 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18272 for (; i != NumElts; ++i) {
18273 SDValue Arg = InVec.getOperand(i);
18274 if (Arg.getOpcode() == ISD::UNDEF) continue;
18278 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18279 if (ConstantSDNode *C =
18280 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18281 unsigned SplatIdx =
18282 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18283 if (C->getZExtValue() == SplatIdx)
18284 BaseShAmt = InVec.getOperand(1);
18287 if (!BaseShAmt.getNode())
18288 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18289 DAG.getIntPtrConstant(0));
18293 if (BaseShAmt.getNode()) {
18294 if (EltVT.bitsGT(MVT::i32))
18295 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18296 else if (EltVT.bitsLT(MVT::i32))
18297 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18299 switch (Op.getOpcode()) {
18301 llvm_unreachable("Unknown shift opcode!");
18303 switch (VT.SimpleTy) {
18304 default: return SDValue();
18313 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18316 switch (VT.SimpleTy) {
18317 default: return SDValue();
18324 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18327 switch (VT.SimpleTy) {
18328 default: return SDValue();
18337 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18343 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18344 if (!Subtarget->is64Bit() &&
18345 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18346 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18347 Amt.getOpcode() == ISD::BITCAST &&
18348 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18349 Amt = Amt.getOperand(0);
18350 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18351 VT.getVectorNumElements();
18352 std::vector<SDValue> Vals(Ratio);
18353 for (unsigned i = 0; i != Ratio; ++i)
18354 Vals[i] = Amt.getOperand(i);
18355 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18356 for (unsigned j = 0; j != Ratio; ++j)
18357 if (Vals[j] != Amt.getOperand(i + j))
18360 switch (Op.getOpcode()) {
18362 llvm_unreachable("Unknown shift opcode!");
18364 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18366 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18368 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18375 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18376 SelectionDAG &DAG) {
18377 MVT VT = Op.getSimpleValueType();
18379 SDValue R = Op.getOperand(0);
18380 SDValue Amt = Op.getOperand(1);
18383 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18384 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18386 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18390 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18394 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18396 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18397 if (Subtarget->hasInt256()) {
18398 if (Op.getOpcode() == ISD::SRL &&
18399 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18400 VT == MVT::v4i64 || VT == MVT::v8i32))
18402 if (Op.getOpcode() == ISD::SHL &&
18403 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18404 VT == MVT::v4i64 || VT == MVT::v8i32))
18406 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18410 // If possible, lower this packed shift into a vector multiply instead of
18411 // expanding it into a sequence of scalar shifts.
18412 // Do this only if the vector shift count is a constant build_vector.
18413 if (Op.getOpcode() == ISD::SHL &&
18414 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18415 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18416 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18417 SmallVector<SDValue, 8> Elts;
18418 EVT SVT = VT.getScalarType();
18419 unsigned SVTBits = SVT.getSizeInBits();
18420 const APInt &One = APInt(SVTBits, 1);
18421 unsigned NumElems = VT.getVectorNumElements();
18423 for (unsigned i=0; i !=NumElems; ++i) {
18424 SDValue Op = Amt->getOperand(i);
18425 if (Op->getOpcode() == ISD::UNDEF) {
18426 Elts.push_back(Op);
18430 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18431 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18432 uint64_t ShAmt = C.getZExtValue();
18433 if (ShAmt >= SVTBits) {
18434 Elts.push_back(DAG.getUNDEF(SVT));
18437 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18439 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18440 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18443 // Lower SHL with variable shift amount.
18444 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18445 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18447 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18448 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18449 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18450 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18453 // If possible, lower this shift as a sequence of two shifts by
18454 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18456 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18458 // Could be rewritten as:
18459 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18461 // The advantage is that the two shifts from the example would be
18462 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18463 // the vector shift into four scalar shifts plus four pairs of vector
18465 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18466 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18467 unsigned TargetOpcode = X86ISD::MOVSS;
18468 bool CanBeSimplified;
18469 // The splat value for the first packed shift (the 'X' from the example).
18470 SDValue Amt1 = Amt->getOperand(0);
18471 // The splat value for the second packed shift (the 'Y' from the example).
18472 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18473 Amt->getOperand(2);
18475 // See if it is possible to replace this node with a sequence of
18476 // two shifts followed by a MOVSS/MOVSD
18477 if (VT == MVT::v4i32) {
18478 // Check if it is legal to use a MOVSS.
18479 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18480 Amt2 == Amt->getOperand(3);
18481 if (!CanBeSimplified) {
18482 // Otherwise, check if we can still simplify this node using a MOVSD.
18483 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18484 Amt->getOperand(2) == Amt->getOperand(3);
18485 TargetOpcode = X86ISD::MOVSD;
18486 Amt2 = Amt->getOperand(2);
18489 // Do similar checks for the case where the machine value type
18491 CanBeSimplified = Amt1 == Amt->getOperand(1);
18492 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18493 CanBeSimplified = Amt2 == Amt->getOperand(i);
18495 if (!CanBeSimplified) {
18496 TargetOpcode = X86ISD::MOVSD;
18497 CanBeSimplified = true;
18498 Amt2 = Amt->getOperand(4);
18499 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18500 CanBeSimplified = Amt1 == Amt->getOperand(i);
18501 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18502 CanBeSimplified = Amt2 == Amt->getOperand(j);
18506 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18507 isa<ConstantSDNode>(Amt2)) {
18508 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18509 EVT CastVT = MVT::v4i32;
18511 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18512 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18514 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18515 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18516 if (TargetOpcode == X86ISD::MOVSD)
18517 CastVT = MVT::v2i64;
18518 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18519 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18520 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18522 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18526 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18527 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18530 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18531 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18533 // Turn 'a' into a mask suitable for VSELECT
18534 SDValue VSelM = DAG.getConstant(0x80, VT);
18535 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18536 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18538 SDValue CM1 = DAG.getConstant(0x0f, VT);
18539 SDValue CM2 = DAG.getConstant(0x3f, VT);
18541 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18542 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18543 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18544 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18545 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18548 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18549 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18550 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18552 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18553 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18554 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18555 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18556 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18559 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18560 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18561 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18563 // return VSELECT(r, r+r, a);
18564 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18565 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18569 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18570 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18571 // solution better.
18572 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18573 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18575 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18576 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18577 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18578 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18579 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18582 // Decompose 256-bit shifts into smaller 128-bit shifts.
18583 if (VT.is256BitVector()) {
18584 unsigned NumElems = VT.getVectorNumElements();
18585 MVT EltVT = VT.getVectorElementType();
18586 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18588 // Extract the two vectors
18589 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18590 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18592 // Recreate the shift amount vectors
18593 SDValue Amt1, Amt2;
18594 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18595 // Constant shift amount
18596 SmallVector<SDValue, 4> Amt1Csts;
18597 SmallVector<SDValue, 4> Amt2Csts;
18598 for (unsigned i = 0; i != NumElems/2; ++i)
18599 Amt1Csts.push_back(Amt->getOperand(i));
18600 for (unsigned i = NumElems/2; i != NumElems; ++i)
18601 Amt2Csts.push_back(Amt->getOperand(i));
18603 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18604 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18606 // Variable shift amount
18607 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18608 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18611 // Issue new vector shifts for the smaller types
18612 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18613 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18615 // Concatenate the result back
18616 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18622 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18623 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18624 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18625 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18626 // has only one use.
18627 SDNode *N = Op.getNode();
18628 SDValue LHS = N->getOperand(0);
18629 SDValue RHS = N->getOperand(1);
18630 unsigned BaseOp = 0;
18633 switch (Op.getOpcode()) {
18634 default: llvm_unreachable("Unknown ovf instruction!");
18636 // A subtract of one will be selected as a INC. Note that INC doesn't
18637 // set CF, so we can't do this for UADDO.
18638 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18640 BaseOp = X86ISD::INC;
18641 Cond = X86::COND_O;
18644 BaseOp = X86ISD::ADD;
18645 Cond = X86::COND_O;
18648 BaseOp = X86ISD::ADD;
18649 Cond = X86::COND_B;
18652 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18653 // set CF, so we can't do this for USUBO.
18654 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18656 BaseOp = X86ISD::DEC;
18657 Cond = X86::COND_O;
18660 BaseOp = X86ISD::SUB;
18661 Cond = X86::COND_O;
18664 BaseOp = X86ISD::SUB;
18665 Cond = X86::COND_B;
18668 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18669 Cond = X86::COND_O;
18671 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18672 if (N->getValueType(0) == MVT::i8) {
18673 BaseOp = X86ISD::UMUL8;
18674 Cond = X86::COND_O;
18677 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18679 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18682 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18683 DAG.getConstant(X86::COND_O, MVT::i32),
18684 SDValue(Sum.getNode(), 2));
18686 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18690 // Also sets EFLAGS.
18691 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18692 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18695 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18696 DAG.getConstant(Cond, MVT::i32),
18697 SDValue(Sum.getNode(), 1));
18699 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18702 // Sign extension of the low part of vector elements. This may be used either
18703 // when sign extend instructions are not available or if the vector element
18704 // sizes already match the sign-extended size. If the vector elements are in
18705 // their pre-extended size and sign extend instructions are available, that will
18706 // be handled by LowerSIGN_EXTEND.
18707 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18708 SelectionDAG &DAG) const {
18710 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18711 MVT VT = Op.getSimpleValueType();
18713 if (!Subtarget->hasSSE2() || !VT.isVector())
18716 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18717 ExtraVT.getScalarType().getSizeInBits();
18719 switch (VT.SimpleTy) {
18720 default: return SDValue();
18723 if (!Subtarget->hasFp256())
18725 if (!Subtarget->hasInt256()) {
18726 // needs to be split
18727 unsigned NumElems = VT.getVectorNumElements();
18729 // Extract the LHS vectors
18730 SDValue LHS = Op.getOperand(0);
18731 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18732 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18734 MVT EltVT = VT.getVectorElementType();
18735 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18737 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18738 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18739 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18741 SDValue Extra = DAG.getValueType(ExtraVT);
18743 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18744 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18746 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18751 SDValue Op0 = Op.getOperand(0);
18753 // This is a sign extension of some low part of vector elements without
18754 // changing the size of the vector elements themselves:
18755 // Shift-Left + Shift-Right-Algebraic.
18756 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18758 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18764 /// Returns true if the operand type is exactly twice the native width, and
18765 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18766 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18767 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18768 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18769 const X86Subtarget &Subtarget =
18770 getTargetMachine().getSubtarget<X86Subtarget>();
18771 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18774 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18775 else if (OpWidth == 128)
18776 return Subtarget.hasCmpxchg16b();
18781 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18782 return needsCmpXchgNb(SI->getValueOperand()->getType());
18785 // Note: this turns large loads into lock cmpxchg8b/16b.
18786 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18787 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18788 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18789 return needsCmpXchgNb(PTy->getElementType());
18792 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18793 const X86Subtarget &Subtarget =
18794 getTargetMachine().getSubtarget<X86Subtarget>();
18795 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18796 const Type *MemType = AI->getType();
18798 // If the operand is too big, we must see if cmpxchg8/16b is available
18799 // and default to library calls otherwise.
18800 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18801 return needsCmpXchgNb(MemType);
18803 AtomicRMWInst::BinOp Op = AI->getOperation();
18806 llvm_unreachable("Unknown atomic operation");
18807 case AtomicRMWInst::Xchg:
18808 case AtomicRMWInst::Add:
18809 case AtomicRMWInst::Sub:
18810 // It's better to use xadd, xsub or xchg for these in all cases.
18812 case AtomicRMWInst::Or:
18813 case AtomicRMWInst::And:
18814 case AtomicRMWInst::Xor:
18815 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18816 // prefix to a normal instruction for these operations.
18817 return !AI->use_empty();
18818 case AtomicRMWInst::Nand:
18819 case AtomicRMWInst::Max:
18820 case AtomicRMWInst::Min:
18821 case AtomicRMWInst::UMax:
18822 case AtomicRMWInst::UMin:
18823 // These always require a non-trivial set of data operations on x86. We must
18824 // use a cmpxchg loop.
18829 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18830 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18831 // no-sse2). There isn't any reason to disable it if the target processor
18833 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18837 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18838 const X86Subtarget &Subtarget =
18839 getTargetMachine().getSubtarget<X86Subtarget>();
18840 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18841 const Type *MemType = AI->getType();
18842 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18843 // there is no benefit in turning such RMWs into loads, and it is actually
18844 // harmful as it introduces a mfence.
18845 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18848 auto Builder = IRBuilder<>(AI);
18849 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18850 auto SynchScope = AI->getSynchScope();
18851 // We must restrict the ordering to avoid generating loads with Release or
18852 // ReleaseAcquire orderings.
18853 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18854 auto Ptr = AI->getPointerOperand();
18856 // Before the load we need a fence. Here is an example lifted from
18857 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18860 // x.store(1, relaxed);
18861 // r1 = y.fetch_add(0, release);
18863 // y.fetch_add(42, acquire);
18864 // r2 = x.load(relaxed);
18865 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18866 // lowered to just a load without a fence. A mfence flushes the store buffer,
18867 // making the optimization clearly correct.
18868 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18869 // otherwise, we might be able to be more agressive on relaxed idempotent
18870 // rmw. In practice, they do not look useful, so we don't try to be
18871 // especially clever.
18872 if (SynchScope == SingleThread) {
18873 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18874 // the IR level, so we must wrap it in an intrinsic.
18876 } else if (hasMFENCE(Subtarget)) {
18877 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18878 Intrinsic::x86_sse2_mfence);
18879 Builder.CreateCall(MFence);
18881 // FIXME: it might make sense to use a locked operation here but on a
18882 // different cache-line to prevent cache-line bouncing. In practice it
18883 // is probably a small win, and x86 processors without mfence are rare
18884 // enough that we do not bother.
18888 // Finally we can emit the atomic load.
18889 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18890 AI->getType()->getPrimitiveSizeInBits());
18891 Loaded->setAtomic(Order, SynchScope);
18892 AI->replaceAllUsesWith(Loaded);
18893 AI->eraseFromParent();
18897 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18898 SelectionDAG &DAG) {
18900 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18901 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18902 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18903 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18905 // The only fence that needs an instruction is a sequentially-consistent
18906 // cross-thread fence.
18907 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18908 if (hasMFENCE(*Subtarget))
18909 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18911 SDValue Chain = Op.getOperand(0);
18912 SDValue Zero = DAG.getConstant(0, MVT::i32);
18914 DAG.getRegister(X86::ESP, MVT::i32), // Base
18915 DAG.getTargetConstant(1, MVT::i8), // Scale
18916 DAG.getRegister(0, MVT::i32), // Index
18917 DAG.getTargetConstant(0, MVT::i32), // Disp
18918 DAG.getRegister(0, MVT::i32), // Segment.
18922 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18923 return SDValue(Res, 0);
18926 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18927 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18930 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18931 SelectionDAG &DAG) {
18932 MVT T = Op.getSimpleValueType();
18936 switch(T.SimpleTy) {
18937 default: llvm_unreachable("Invalid value type!");
18938 case MVT::i8: Reg = X86::AL; size = 1; break;
18939 case MVT::i16: Reg = X86::AX; size = 2; break;
18940 case MVT::i32: Reg = X86::EAX; size = 4; break;
18942 assert(Subtarget->is64Bit() && "Node not type legal!");
18943 Reg = X86::RAX; size = 8;
18946 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18947 Op.getOperand(2), SDValue());
18948 SDValue Ops[] = { cpIn.getValue(0),
18951 DAG.getTargetConstant(size, MVT::i8),
18952 cpIn.getValue(1) };
18953 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18954 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18955 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18959 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18960 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18961 MVT::i32, cpOut.getValue(2));
18962 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18963 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18965 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18966 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18967 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18971 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18972 SelectionDAG &DAG) {
18973 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18974 MVT DstVT = Op.getSimpleValueType();
18976 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18977 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18978 if (DstVT != MVT::f64)
18979 // This conversion needs to be expanded.
18982 SDValue InVec = Op->getOperand(0);
18984 unsigned NumElts = SrcVT.getVectorNumElements();
18985 EVT SVT = SrcVT.getVectorElementType();
18987 // Widen the vector in input in the case of MVT::v2i32.
18988 // Example: from MVT::v2i32 to MVT::v4i32.
18989 SmallVector<SDValue, 16> Elts;
18990 for (unsigned i = 0, e = NumElts; i != e; ++i)
18991 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18992 DAG.getIntPtrConstant(i)));
18994 // Explicitly mark the extra elements as Undef.
18995 SDValue Undef = DAG.getUNDEF(SVT);
18996 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18997 Elts.push_back(Undef);
18999 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19000 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19001 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19002 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19003 DAG.getIntPtrConstant(0));
19006 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19007 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19008 assert((DstVT == MVT::i64 ||
19009 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19010 "Unexpected custom BITCAST");
19011 // i64 <=> MMX conversions are Legal.
19012 if (SrcVT==MVT::i64 && DstVT.isVector())
19014 if (DstVT==MVT::i64 && SrcVT.isVector())
19016 // MMX <=> MMX conversions are Legal.
19017 if (SrcVT.isVector() && DstVT.isVector())
19019 // All other conversions need to be expanded.
19023 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19024 SDNode *Node = Op.getNode();
19026 EVT T = Node->getValueType(0);
19027 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19028 DAG.getConstant(0, T), Node->getOperand(2));
19029 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19030 cast<AtomicSDNode>(Node)->getMemoryVT(),
19031 Node->getOperand(0),
19032 Node->getOperand(1), negOp,
19033 cast<AtomicSDNode>(Node)->getMemOperand(),
19034 cast<AtomicSDNode>(Node)->getOrdering(),
19035 cast<AtomicSDNode>(Node)->getSynchScope());
19038 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19039 SDNode *Node = Op.getNode();
19041 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19043 // Convert seq_cst store -> xchg
19044 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19045 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19046 // (The only way to get a 16-byte store is cmpxchg16b)
19047 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19048 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19049 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19050 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19051 cast<AtomicSDNode>(Node)->getMemoryVT(),
19052 Node->getOperand(0),
19053 Node->getOperand(1), Node->getOperand(2),
19054 cast<AtomicSDNode>(Node)->getMemOperand(),
19055 cast<AtomicSDNode>(Node)->getOrdering(),
19056 cast<AtomicSDNode>(Node)->getSynchScope());
19057 return Swap.getValue(1);
19059 // Other atomic stores have a simple pattern.
19063 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19064 EVT VT = Op.getNode()->getSimpleValueType(0);
19066 // Let legalize expand this if it isn't a legal type yet.
19067 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19070 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19073 bool ExtraOp = false;
19074 switch (Op.getOpcode()) {
19075 default: llvm_unreachable("Invalid code");
19076 case ISD::ADDC: Opc = X86ISD::ADD; break;
19077 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19078 case ISD::SUBC: Opc = X86ISD::SUB; break;
19079 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19083 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19085 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19086 Op.getOperand(1), Op.getOperand(2));
19089 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19090 SelectionDAG &DAG) {
19091 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19093 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19094 // which returns the values as { float, float } (in XMM0) or
19095 // { double, double } (which is returned in XMM0, XMM1).
19097 SDValue Arg = Op.getOperand(0);
19098 EVT ArgVT = Arg.getValueType();
19099 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19101 TargetLowering::ArgListTy Args;
19102 TargetLowering::ArgListEntry Entry;
19106 Entry.isSExt = false;
19107 Entry.isZExt = false;
19108 Args.push_back(Entry);
19110 bool isF64 = ArgVT == MVT::f64;
19111 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19112 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19113 // the results are returned via SRet in memory.
19114 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19116 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19118 Type *RetTy = isF64
19119 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19120 : (Type*)VectorType::get(ArgTy, 4);
19122 TargetLowering::CallLoweringInfo CLI(DAG);
19123 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19124 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19126 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19129 // Returned in xmm0 and xmm1.
19130 return CallResult.first;
19132 // Returned in bits 0:31 and 32:64 xmm0.
19133 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19134 CallResult.first, DAG.getIntPtrConstant(0));
19135 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19136 CallResult.first, DAG.getIntPtrConstant(1));
19137 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19138 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19141 /// LowerOperation - Provide custom lowering hooks for some operations.
19143 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19144 switch (Op.getOpcode()) {
19145 default: llvm_unreachable("Should not custom lower this!");
19146 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19147 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19148 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19149 return LowerCMP_SWAP(Op, Subtarget, DAG);
19150 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19151 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19152 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19153 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19154 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19155 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19156 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19157 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19158 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19159 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19160 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19161 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19162 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19163 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19164 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19165 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19166 case ISD::SHL_PARTS:
19167 case ISD::SRA_PARTS:
19168 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19169 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19170 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19171 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19172 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19173 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19174 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19175 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19176 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19177 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19178 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19180 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19181 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19182 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19183 case ISD::SETCC: return LowerSETCC(Op, DAG);
19184 case ISD::SELECT: return LowerSELECT(Op, DAG);
19185 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19186 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19187 case ISD::VASTART: return LowerVASTART(Op, DAG);
19188 case ISD::VAARG: return LowerVAARG(Op, DAG);
19189 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19190 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19191 case ISD::INTRINSIC_VOID:
19192 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19193 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19194 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19195 case ISD::FRAME_TO_ARGS_OFFSET:
19196 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19197 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19198 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19199 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19200 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19201 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19202 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19203 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19204 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19205 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19206 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19207 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19208 case ISD::UMUL_LOHI:
19209 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19212 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19218 case ISD::UMULO: return LowerXALUO(Op, DAG);
19219 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19220 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19224 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19225 case ISD::ADD: return LowerADD(Op, DAG);
19226 case ISD::SUB: return LowerSUB(Op, DAG);
19227 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19231 /// ReplaceNodeResults - Replace a node with an illegal result type
19232 /// with a new node built out of custom code.
19233 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19234 SmallVectorImpl<SDValue>&Results,
19235 SelectionDAG &DAG) const {
19237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19238 switch (N->getOpcode()) {
19240 llvm_unreachable("Do not know how to custom type legalize this operation!");
19241 case ISD::SIGN_EXTEND_INREG:
19246 // We don't want to expand or promote these.
19253 case ISD::UDIVREM: {
19254 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19255 Results.push_back(V);
19258 case ISD::FP_TO_SINT:
19259 case ISD::FP_TO_UINT: {
19260 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19262 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19265 std::pair<SDValue,SDValue> Vals =
19266 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19267 SDValue FIST = Vals.first, StackSlot = Vals.second;
19268 if (FIST.getNode()) {
19269 EVT VT = N->getValueType(0);
19270 // Return a load from the stack slot.
19271 if (StackSlot.getNode())
19272 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19273 MachinePointerInfo(),
19274 false, false, false, 0));
19276 Results.push_back(FIST);
19280 case ISD::UINT_TO_FP: {
19281 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19282 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19283 N->getValueType(0) != MVT::v2f32)
19285 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19287 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19289 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19290 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19291 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19292 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19293 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19294 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19297 case ISD::FP_ROUND: {
19298 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19300 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19301 Results.push_back(V);
19304 case ISD::INTRINSIC_W_CHAIN: {
19305 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19307 default : llvm_unreachable("Do not know how to custom type "
19308 "legalize this intrinsic operation!");
19309 case Intrinsic::x86_rdtsc:
19310 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19312 case Intrinsic::x86_rdtscp:
19313 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19315 case Intrinsic::x86_rdpmc:
19316 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19319 case ISD::READCYCLECOUNTER: {
19320 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19323 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19324 EVT T = N->getValueType(0);
19325 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19326 bool Regs64bit = T == MVT::i128;
19327 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19328 SDValue cpInL, cpInH;
19329 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19330 DAG.getConstant(0, HalfT));
19331 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19332 DAG.getConstant(1, HalfT));
19333 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19334 Regs64bit ? X86::RAX : X86::EAX,
19336 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19337 Regs64bit ? X86::RDX : X86::EDX,
19338 cpInH, cpInL.getValue(1));
19339 SDValue swapInL, swapInH;
19340 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19341 DAG.getConstant(0, HalfT));
19342 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19343 DAG.getConstant(1, HalfT));
19344 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19345 Regs64bit ? X86::RBX : X86::EBX,
19346 swapInL, cpInH.getValue(1));
19347 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19348 Regs64bit ? X86::RCX : X86::ECX,
19349 swapInH, swapInL.getValue(1));
19350 SDValue Ops[] = { swapInH.getValue(0),
19352 swapInH.getValue(1) };
19353 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19354 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19355 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19356 X86ISD::LCMPXCHG8_DAG;
19357 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19358 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19359 Regs64bit ? X86::RAX : X86::EAX,
19360 HalfT, Result.getValue(1));
19361 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19362 Regs64bit ? X86::RDX : X86::EDX,
19363 HalfT, cpOutL.getValue(2));
19364 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19366 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19367 MVT::i32, cpOutH.getValue(2));
19369 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19370 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19371 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19373 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19374 Results.push_back(Success);
19375 Results.push_back(EFLAGS.getValue(1));
19378 case ISD::ATOMIC_SWAP:
19379 case ISD::ATOMIC_LOAD_ADD:
19380 case ISD::ATOMIC_LOAD_SUB:
19381 case ISD::ATOMIC_LOAD_AND:
19382 case ISD::ATOMIC_LOAD_OR:
19383 case ISD::ATOMIC_LOAD_XOR:
19384 case ISD::ATOMIC_LOAD_NAND:
19385 case ISD::ATOMIC_LOAD_MIN:
19386 case ISD::ATOMIC_LOAD_MAX:
19387 case ISD::ATOMIC_LOAD_UMIN:
19388 case ISD::ATOMIC_LOAD_UMAX:
19389 case ISD::ATOMIC_LOAD: {
19390 // Delegate to generic TypeLegalization. Situations we can really handle
19391 // should have already been dealt with by AtomicExpandPass.cpp.
19394 case ISD::BITCAST: {
19395 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19396 EVT DstVT = N->getValueType(0);
19397 EVT SrcVT = N->getOperand(0)->getValueType(0);
19399 if (SrcVT != MVT::f64 ||
19400 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19403 unsigned NumElts = DstVT.getVectorNumElements();
19404 EVT SVT = DstVT.getVectorElementType();
19405 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19406 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19407 MVT::v2f64, N->getOperand(0));
19408 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19410 if (ExperimentalVectorWideningLegalization) {
19411 // If we are legalizing vectors by widening, we already have the desired
19412 // legal vector type, just return it.
19413 Results.push_back(ToVecInt);
19417 SmallVector<SDValue, 8> Elts;
19418 for (unsigned i = 0, e = NumElts; i != e; ++i)
19419 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19420 ToVecInt, DAG.getIntPtrConstant(i)));
19422 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19427 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19429 default: return nullptr;
19430 case X86ISD::BSF: return "X86ISD::BSF";
19431 case X86ISD::BSR: return "X86ISD::BSR";
19432 case X86ISD::SHLD: return "X86ISD::SHLD";
19433 case X86ISD::SHRD: return "X86ISD::SHRD";
19434 case X86ISD::FAND: return "X86ISD::FAND";
19435 case X86ISD::FANDN: return "X86ISD::FANDN";
19436 case X86ISD::FOR: return "X86ISD::FOR";
19437 case X86ISD::FXOR: return "X86ISD::FXOR";
19438 case X86ISD::FSRL: return "X86ISD::FSRL";
19439 case X86ISD::FILD: return "X86ISD::FILD";
19440 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19441 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19442 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19443 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19444 case X86ISD::FLD: return "X86ISD::FLD";
19445 case X86ISD::FST: return "X86ISD::FST";
19446 case X86ISD::CALL: return "X86ISD::CALL";
19447 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19448 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19449 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19450 case X86ISD::BT: return "X86ISD::BT";
19451 case X86ISD::CMP: return "X86ISD::CMP";
19452 case X86ISD::COMI: return "X86ISD::COMI";
19453 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19454 case X86ISD::CMPM: return "X86ISD::CMPM";
19455 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19456 case X86ISD::SETCC: return "X86ISD::SETCC";
19457 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19458 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19459 case X86ISD::CMOV: return "X86ISD::CMOV";
19460 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19461 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19462 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19463 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19464 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19465 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19466 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19467 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19468 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19469 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19470 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19471 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19472 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19473 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19474 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19475 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19476 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19477 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19478 case X86ISD::HADD: return "X86ISD::HADD";
19479 case X86ISD::HSUB: return "X86ISD::HSUB";
19480 case X86ISD::FHADD: return "X86ISD::FHADD";
19481 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19482 case X86ISD::UMAX: return "X86ISD::UMAX";
19483 case X86ISD::UMIN: return "X86ISD::UMIN";
19484 case X86ISD::SMAX: return "X86ISD::SMAX";
19485 case X86ISD::SMIN: return "X86ISD::SMIN";
19486 case X86ISD::FMAX: return "X86ISD::FMAX";
19487 case X86ISD::FMIN: return "X86ISD::FMIN";
19488 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19489 case X86ISD::FMINC: return "X86ISD::FMINC";
19490 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19491 case X86ISD::FRCP: return "X86ISD::FRCP";
19492 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19493 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19494 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19495 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19496 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19497 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19498 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19499 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19500 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19501 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19502 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19503 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19504 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19505 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19506 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19507 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19508 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19509 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19510 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19511 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19512 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19513 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19514 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19515 case X86ISD::VSHL: return "X86ISD::VSHL";
19516 case X86ISD::VSRL: return "X86ISD::VSRL";
19517 case X86ISD::VSRA: return "X86ISD::VSRA";
19518 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19519 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19520 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19521 case X86ISD::CMPP: return "X86ISD::CMPP";
19522 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19523 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19524 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19525 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19526 case X86ISD::ADD: return "X86ISD::ADD";
19527 case X86ISD::SUB: return "X86ISD::SUB";
19528 case X86ISD::ADC: return "X86ISD::ADC";
19529 case X86ISD::SBB: return "X86ISD::SBB";
19530 case X86ISD::SMUL: return "X86ISD::SMUL";
19531 case X86ISD::UMUL: return "X86ISD::UMUL";
19532 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19533 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19534 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19535 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19536 case X86ISD::INC: return "X86ISD::INC";
19537 case X86ISD::DEC: return "X86ISD::DEC";
19538 case X86ISD::OR: return "X86ISD::OR";
19539 case X86ISD::XOR: return "X86ISD::XOR";
19540 case X86ISD::AND: return "X86ISD::AND";
19541 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19542 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19543 case X86ISD::PTEST: return "X86ISD::PTEST";
19544 case X86ISD::TESTP: return "X86ISD::TESTP";
19545 case X86ISD::TESTM: return "X86ISD::TESTM";
19546 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19547 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19548 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19549 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19550 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19551 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19552 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19553 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19554 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19555 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19556 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19557 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19558 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19559 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19560 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19561 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19562 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19563 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19564 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19565 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19566 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19567 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19568 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19569 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19570 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19571 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19572 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19573 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19574 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19575 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19576 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19577 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19578 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19579 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19580 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19581 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19582 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19583 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19584 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19585 case X86ISD::SAHF: return "X86ISD::SAHF";
19586 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19587 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19588 case X86ISD::FMADD: return "X86ISD::FMADD";
19589 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19590 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19591 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19592 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19593 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19594 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19595 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19596 case X86ISD::XTEST: return "X86ISD::XTEST";
19600 // isLegalAddressingMode - Return true if the addressing mode represented
19601 // by AM is legal for this target, for a load/store of the specified type.
19602 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19604 // X86 supports extremely general addressing modes.
19605 CodeModel::Model M = getTargetMachine().getCodeModel();
19606 Reloc::Model R = getTargetMachine().getRelocationModel();
19608 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19609 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19614 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19616 // If a reference to this global requires an extra load, we can't fold it.
19617 if (isGlobalStubReference(GVFlags))
19620 // If BaseGV requires a register for the PIC base, we cannot also have a
19621 // BaseReg specified.
19622 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19625 // If lower 4G is not available, then we must use rip-relative addressing.
19626 if ((M != CodeModel::Small || R != Reloc::Static) &&
19627 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19631 switch (AM.Scale) {
19637 // These scales always work.
19642 // These scales are formed with basereg+scalereg. Only accept if there is
19647 default: // Other stuff never works.
19654 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19655 unsigned Bits = Ty->getScalarSizeInBits();
19657 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19658 // particularly cheaper than those without.
19662 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19663 // variable shifts just as cheap as scalar ones.
19664 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19667 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19668 // fully general vector.
19672 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19673 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19675 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19676 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19677 return NumBits1 > NumBits2;
19680 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19681 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19684 if (!isTypeLegal(EVT::getEVT(Ty1)))
19687 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19689 // Assuming the caller doesn't have a zeroext or signext return parameter,
19690 // truncation all the way down to i1 is valid.
19694 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19695 return isInt<32>(Imm);
19698 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19699 // Can also use sub to handle negated immediates.
19700 return isInt<32>(Imm);
19703 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19704 if (!VT1.isInteger() || !VT2.isInteger())
19706 unsigned NumBits1 = VT1.getSizeInBits();
19707 unsigned NumBits2 = VT2.getSizeInBits();
19708 return NumBits1 > NumBits2;
19711 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19712 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19713 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19716 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19717 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19718 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19721 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19722 EVT VT1 = Val.getValueType();
19723 if (isZExtFree(VT1, VT2))
19726 if (Val.getOpcode() != ISD::LOAD)
19729 if (!VT1.isSimple() || !VT1.isInteger() ||
19730 !VT2.isSimple() || !VT2.isInteger())
19733 switch (VT1.getSimpleVT().SimpleTy) {
19738 // X86 has 8, 16, and 32-bit zero-extending loads.
19746 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19747 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19750 VT = VT.getScalarType();
19752 if (!VT.isSimple())
19755 switch (VT.getSimpleVT().SimpleTy) {
19766 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19767 // i16 instructions are longer (0x66 prefix) and potentially slower.
19768 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19771 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19772 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19773 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19774 /// are assumed to be legal.
19776 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19778 if (!VT.isSimple())
19781 MVT SVT = VT.getSimpleVT();
19783 // Very little shuffling can be done for 64-bit vectors right now.
19784 if (VT.getSizeInBits() == 64)
19787 // If this is a single-input shuffle with no 128 bit lane crossings we can
19788 // lower it into pshufb.
19789 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19790 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19791 bool isLegal = true;
19792 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19793 if (M[I] >= (int)SVT.getVectorNumElements() ||
19794 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19803 // FIXME: blends, shifts.
19804 return (SVT.getVectorNumElements() == 2 ||
19805 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19806 isMOVLMask(M, SVT) ||
19807 isMOVHLPSMask(M, SVT) ||
19808 isSHUFPMask(M, SVT) ||
19809 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19810 isPSHUFDMask(M, SVT) ||
19811 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19812 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19813 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19814 isPALIGNRMask(M, SVT, Subtarget) ||
19815 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19816 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19817 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19818 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19819 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19820 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19824 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19826 if (!VT.isSimple())
19829 MVT SVT = VT.getSimpleVT();
19830 unsigned NumElts = SVT.getVectorNumElements();
19831 // FIXME: This collection of masks seems suspect.
19834 if (NumElts == 4 && SVT.is128BitVector()) {
19835 return (isMOVLMask(Mask, SVT) ||
19836 isCommutedMOVLMask(Mask, SVT, true) ||
19837 isSHUFPMask(Mask, SVT) ||
19838 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19839 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19840 Subtarget->hasInt256()));
19845 //===----------------------------------------------------------------------===//
19846 // X86 Scheduler Hooks
19847 //===----------------------------------------------------------------------===//
19849 /// Utility function to emit xbegin specifying the start of an RTM region.
19850 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19851 const TargetInstrInfo *TII) {
19852 DebugLoc DL = MI->getDebugLoc();
19854 const BasicBlock *BB = MBB->getBasicBlock();
19855 MachineFunction::iterator I = MBB;
19858 // For the v = xbegin(), we generate
19869 MachineBasicBlock *thisMBB = MBB;
19870 MachineFunction *MF = MBB->getParent();
19871 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19872 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19873 MF->insert(I, mainMBB);
19874 MF->insert(I, sinkMBB);
19876 // Transfer the remainder of BB and its successor edges to sinkMBB.
19877 sinkMBB->splice(sinkMBB->begin(), MBB,
19878 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19879 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19883 // # fallthrough to mainMBB
19884 // # abortion to sinkMBB
19885 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19886 thisMBB->addSuccessor(mainMBB);
19887 thisMBB->addSuccessor(sinkMBB);
19891 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19892 mainMBB->addSuccessor(sinkMBB);
19895 // EAX is live into the sinkMBB
19896 sinkMBB->addLiveIn(X86::EAX);
19897 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19898 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19901 MI->eraseFromParent();
19905 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19906 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19907 // in the .td file.
19908 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19909 const TargetInstrInfo *TII) {
19911 switch (MI->getOpcode()) {
19912 default: llvm_unreachable("illegal opcode!");
19913 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19914 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19915 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19916 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19917 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19918 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19919 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19920 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19923 DebugLoc dl = MI->getDebugLoc();
19924 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19926 unsigned NumArgs = MI->getNumOperands();
19927 for (unsigned i = 1; i < NumArgs; ++i) {
19928 MachineOperand &Op = MI->getOperand(i);
19929 if (!(Op.isReg() && Op.isImplicit()))
19930 MIB.addOperand(Op);
19932 if (MI->hasOneMemOperand())
19933 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19935 BuildMI(*BB, MI, dl,
19936 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19937 .addReg(X86::XMM0);
19939 MI->eraseFromParent();
19943 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19944 // defs in an instruction pattern
19945 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19946 const TargetInstrInfo *TII) {
19948 switch (MI->getOpcode()) {
19949 default: llvm_unreachable("illegal opcode!");
19950 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19951 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19952 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19953 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19954 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19955 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19956 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19957 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19960 DebugLoc dl = MI->getDebugLoc();
19961 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19963 unsigned NumArgs = MI->getNumOperands(); // remove the results
19964 for (unsigned i = 1; i < NumArgs; ++i) {
19965 MachineOperand &Op = MI->getOperand(i);
19966 if (!(Op.isReg() && Op.isImplicit()))
19967 MIB.addOperand(Op);
19969 if (MI->hasOneMemOperand())
19970 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19972 BuildMI(*BB, MI, dl,
19973 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19976 MI->eraseFromParent();
19980 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19981 const TargetInstrInfo *TII,
19982 const X86Subtarget* Subtarget) {
19983 DebugLoc dl = MI->getDebugLoc();
19985 // Address into RAX/EAX, other two args into ECX, EDX.
19986 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19987 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19988 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19989 for (int i = 0; i < X86::AddrNumOperands; ++i)
19990 MIB.addOperand(MI->getOperand(i));
19992 unsigned ValOps = X86::AddrNumOperands;
19993 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19994 .addReg(MI->getOperand(ValOps).getReg());
19995 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19996 .addReg(MI->getOperand(ValOps+1).getReg());
19998 // The instruction doesn't actually take any operands though.
19999 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20001 MI->eraseFromParent(); // The pseudo is gone now.
20005 MachineBasicBlock *
20006 X86TargetLowering::EmitVAARG64WithCustomInserter(
20008 MachineBasicBlock *MBB) const {
20009 // Emit va_arg instruction on X86-64.
20011 // Operands to this pseudo-instruction:
20012 // 0 ) Output : destination address (reg)
20013 // 1-5) Input : va_list address (addr, i64mem)
20014 // 6 ) ArgSize : Size (in bytes) of vararg type
20015 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20016 // 8 ) Align : Alignment of type
20017 // 9 ) EFLAGS (implicit-def)
20019 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20020 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20022 unsigned DestReg = MI->getOperand(0).getReg();
20023 MachineOperand &Base = MI->getOperand(1);
20024 MachineOperand &Scale = MI->getOperand(2);
20025 MachineOperand &Index = MI->getOperand(3);
20026 MachineOperand &Disp = MI->getOperand(4);
20027 MachineOperand &Segment = MI->getOperand(5);
20028 unsigned ArgSize = MI->getOperand(6).getImm();
20029 unsigned ArgMode = MI->getOperand(7).getImm();
20030 unsigned Align = MI->getOperand(8).getImm();
20032 // Memory Reference
20033 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20034 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20035 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20037 // Machine Information
20038 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20039 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20040 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20041 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20042 DebugLoc DL = MI->getDebugLoc();
20044 // struct va_list {
20047 // i64 overflow_area (address)
20048 // i64 reg_save_area (address)
20050 // sizeof(va_list) = 24
20051 // alignment(va_list) = 8
20053 unsigned TotalNumIntRegs = 6;
20054 unsigned TotalNumXMMRegs = 8;
20055 bool UseGPOffset = (ArgMode == 1);
20056 bool UseFPOffset = (ArgMode == 2);
20057 unsigned MaxOffset = TotalNumIntRegs * 8 +
20058 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20060 /* Align ArgSize to a multiple of 8 */
20061 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20062 bool NeedsAlign = (Align > 8);
20064 MachineBasicBlock *thisMBB = MBB;
20065 MachineBasicBlock *overflowMBB;
20066 MachineBasicBlock *offsetMBB;
20067 MachineBasicBlock *endMBB;
20069 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20070 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20071 unsigned OffsetReg = 0;
20073 if (!UseGPOffset && !UseFPOffset) {
20074 // If we only pull from the overflow region, we don't create a branch.
20075 // We don't need to alter control flow.
20076 OffsetDestReg = 0; // unused
20077 OverflowDestReg = DestReg;
20079 offsetMBB = nullptr;
20080 overflowMBB = thisMBB;
20083 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20084 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20085 // If not, pull from overflow_area. (branch to overflowMBB)
20090 // offsetMBB overflowMBB
20095 // Registers for the PHI in endMBB
20096 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20097 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20099 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20100 MachineFunction *MF = MBB->getParent();
20101 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20102 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20103 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20105 MachineFunction::iterator MBBIter = MBB;
20108 // Insert the new basic blocks
20109 MF->insert(MBBIter, offsetMBB);
20110 MF->insert(MBBIter, overflowMBB);
20111 MF->insert(MBBIter, endMBB);
20113 // Transfer the remainder of MBB and its successor edges to endMBB.
20114 endMBB->splice(endMBB->begin(), thisMBB,
20115 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20116 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20118 // Make offsetMBB and overflowMBB successors of thisMBB
20119 thisMBB->addSuccessor(offsetMBB);
20120 thisMBB->addSuccessor(overflowMBB);
20122 // endMBB is a successor of both offsetMBB and overflowMBB
20123 offsetMBB->addSuccessor(endMBB);
20124 overflowMBB->addSuccessor(endMBB);
20126 // Load the offset value into a register
20127 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20128 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20132 .addDisp(Disp, UseFPOffset ? 4 : 0)
20133 .addOperand(Segment)
20134 .setMemRefs(MMOBegin, MMOEnd);
20136 // Check if there is enough room left to pull this argument.
20137 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20139 .addImm(MaxOffset + 8 - ArgSizeA8);
20141 // Branch to "overflowMBB" if offset >= max
20142 // Fall through to "offsetMBB" otherwise
20143 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20144 .addMBB(overflowMBB);
20147 // In offsetMBB, emit code to use the reg_save_area.
20149 assert(OffsetReg != 0);
20151 // Read the reg_save_area address.
20152 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20153 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20158 .addOperand(Segment)
20159 .setMemRefs(MMOBegin, MMOEnd);
20161 // Zero-extend the offset
20162 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20163 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20166 .addImm(X86::sub_32bit);
20168 // Add the offset to the reg_save_area to get the final address.
20169 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20170 .addReg(OffsetReg64)
20171 .addReg(RegSaveReg);
20173 // Compute the offset for the next argument
20174 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20175 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20177 .addImm(UseFPOffset ? 16 : 8);
20179 // Store it back into the va_list.
20180 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20184 .addDisp(Disp, UseFPOffset ? 4 : 0)
20185 .addOperand(Segment)
20186 .addReg(NextOffsetReg)
20187 .setMemRefs(MMOBegin, MMOEnd);
20190 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20195 // Emit code to use overflow area
20198 // Load the overflow_area address into a register.
20199 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20200 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20205 .addOperand(Segment)
20206 .setMemRefs(MMOBegin, MMOEnd);
20208 // If we need to align it, do so. Otherwise, just copy the address
20209 // to OverflowDestReg.
20211 // Align the overflow address
20212 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20213 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20215 // aligned_addr = (addr + (align-1)) & ~(align-1)
20216 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20217 .addReg(OverflowAddrReg)
20220 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20222 .addImm(~(uint64_t)(Align-1));
20224 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20225 .addReg(OverflowAddrReg);
20228 // Compute the next overflow address after this argument.
20229 // (the overflow address should be kept 8-byte aligned)
20230 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20231 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20232 .addReg(OverflowDestReg)
20233 .addImm(ArgSizeA8);
20235 // Store the new overflow address.
20236 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20241 .addOperand(Segment)
20242 .addReg(NextAddrReg)
20243 .setMemRefs(MMOBegin, MMOEnd);
20245 // If we branched, emit the PHI to the front of endMBB.
20247 BuildMI(*endMBB, endMBB->begin(), DL,
20248 TII->get(X86::PHI), DestReg)
20249 .addReg(OffsetDestReg).addMBB(offsetMBB)
20250 .addReg(OverflowDestReg).addMBB(overflowMBB);
20253 // Erase the pseudo instruction
20254 MI->eraseFromParent();
20259 MachineBasicBlock *
20260 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20262 MachineBasicBlock *MBB) const {
20263 // Emit code to save XMM registers to the stack. The ABI says that the
20264 // number of registers to save is given in %al, so it's theoretically
20265 // possible to do an indirect jump trick to avoid saving all of them,
20266 // however this code takes a simpler approach and just executes all
20267 // of the stores if %al is non-zero. It's less code, and it's probably
20268 // easier on the hardware branch predictor, and stores aren't all that
20269 // expensive anyway.
20271 // Create the new basic blocks. One block contains all the XMM stores,
20272 // and one block is the final destination regardless of whether any
20273 // stores were performed.
20274 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20275 MachineFunction *F = MBB->getParent();
20276 MachineFunction::iterator MBBIter = MBB;
20278 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20279 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20280 F->insert(MBBIter, XMMSaveMBB);
20281 F->insert(MBBIter, EndMBB);
20283 // Transfer the remainder of MBB and its successor edges to EndMBB.
20284 EndMBB->splice(EndMBB->begin(), MBB,
20285 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20286 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20288 // The original block will now fall through to the XMM save block.
20289 MBB->addSuccessor(XMMSaveMBB);
20290 // The XMMSaveMBB will fall through to the end block.
20291 XMMSaveMBB->addSuccessor(EndMBB);
20293 // Now add the instructions.
20294 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20295 DebugLoc DL = MI->getDebugLoc();
20297 unsigned CountReg = MI->getOperand(0).getReg();
20298 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20299 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20301 if (!Subtarget->isTargetWin64()) {
20302 // If %al is 0, branch around the XMM save block.
20303 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20304 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20305 MBB->addSuccessor(EndMBB);
20308 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20309 // that was just emitted, but clearly shouldn't be "saved".
20310 assert((MI->getNumOperands() <= 3 ||
20311 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20312 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20313 && "Expected last argument to be EFLAGS");
20314 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20315 // In the XMM save block, save all the XMM argument registers.
20316 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20317 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20318 MachineMemOperand *MMO =
20319 F->getMachineMemOperand(
20320 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20321 MachineMemOperand::MOStore,
20322 /*Size=*/16, /*Align=*/16);
20323 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20324 .addFrameIndex(RegSaveFrameIndex)
20325 .addImm(/*Scale=*/1)
20326 .addReg(/*IndexReg=*/0)
20327 .addImm(/*Disp=*/Offset)
20328 .addReg(/*Segment=*/0)
20329 .addReg(MI->getOperand(i).getReg())
20330 .addMemOperand(MMO);
20333 MI->eraseFromParent(); // The pseudo instruction is gone now.
20338 // The EFLAGS operand of SelectItr might be missing a kill marker
20339 // because there were multiple uses of EFLAGS, and ISel didn't know
20340 // which to mark. Figure out whether SelectItr should have had a
20341 // kill marker, and set it if it should. Returns the correct kill
20343 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20344 MachineBasicBlock* BB,
20345 const TargetRegisterInfo* TRI) {
20346 // Scan forward through BB for a use/def of EFLAGS.
20347 MachineBasicBlock::iterator miI(std::next(SelectItr));
20348 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20349 const MachineInstr& mi = *miI;
20350 if (mi.readsRegister(X86::EFLAGS))
20352 if (mi.definesRegister(X86::EFLAGS))
20353 break; // Should have kill-flag - update below.
20356 // If we hit the end of the block, check whether EFLAGS is live into a
20358 if (miI == BB->end()) {
20359 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20360 sEnd = BB->succ_end();
20361 sItr != sEnd; ++sItr) {
20362 MachineBasicBlock* succ = *sItr;
20363 if (succ->isLiveIn(X86::EFLAGS))
20368 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20369 // out. SelectMI should have a kill flag on EFLAGS.
20370 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20374 MachineBasicBlock *
20375 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20376 MachineBasicBlock *BB) const {
20377 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20378 DebugLoc DL = MI->getDebugLoc();
20380 // To "insert" a SELECT_CC instruction, we actually have to insert the
20381 // diamond control-flow pattern. The incoming instruction knows the
20382 // destination vreg to set, the condition code register to branch on, the
20383 // true/false values to select between, and a branch opcode to use.
20384 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20385 MachineFunction::iterator It = BB;
20391 // cmpTY ccX, r1, r2
20393 // fallthrough --> copy0MBB
20394 MachineBasicBlock *thisMBB = BB;
20395 MachineFunction *F = BB->getParent();
20396 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20397 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20398 F->insert(It, copy0MBB);
20399 F->insert(It, sinkMBB);
20401 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20402 // live into the sink and copy blocks.
20403 const TargetRegisterInfo *TRI =
20404 BB->getParent()->getSubtarget().getRegisterInfo();
20405 if (!MI->killsRegister(X86::EFLAGS) &&
20406 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20407 copy0MBB->addLiveIn(X86::EFLAGS);
20408 sinkMBB->addLiveIn(X86::EFLAGS);
20411 // Transfer the remainder of BB and its successor edges to sinkMBB.
20412 sinkMBB->splice(sinkMBB->begin(), BB,
20413 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20414 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20416 // Add the true and fallthrough blocks as its successors.
20417 BB->addSuccessor(copy0MBB);
20418 BB->addSuccessor(sinkMBB);
20420 // Create the conditional branch instruction.
20422 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20423 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20426 // %FalseValue = ...
20427 // # fallthrough to sinkMBB
20428 copy0MBB->addSuccessor(sinkMBB);
20431 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20433 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20434 TII->get(X86::PHI), MI->getOperand(0).getReg())
20435 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20436 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20438 MI->eraseFromParent(); // The pseudo instruction is gone now.
20442 MachineBasicBlock *
20443 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20444 MachineBasicBlock *BB) const {
20445 MachineFunction *MF = BB->getParent();
20446 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20447 DebugLoc DL = MI->getDebugLoc();
20448 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20450 assert(MF->shouldSplitStack());
20452 const bool Is64Bit = Subtarget->is64Bit();
20453 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20455 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20456 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20459 // ... [Till the alloca]
20460 // If stacklet is not large enough, jump to mallocMBB
20463 // Allocate by subtracting from RSP
20464 // Jump to continueMBB
20467 // Allocate by call to runtime
20471 // [rest of original BB]
20474 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20475 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20476 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20478 MachineRegisterInfo &MRI = MF->getRegInfo();
20479 const TargetRegisterClass *AddrRegClass =
20480 getRegClassFor(getPointerTy());
20482 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20483 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20484 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20485 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20486 sizeVReg = MI->getOperand(1).getReg(),
20487 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20489 MachineFunction::iterator MBBIter = BB;
20492 MF->insert(MBBIter, bumpMBB);
20493 MF->insert(MBBIter, mallocMBB);
20494 MF->insert(MBBIter, continueMBB);
20496 continueMBB->splice(continueMBB->begin(), BB,
20497 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20498 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20500 // Add code to the main basic block to check if the stack limit has been hit,
20501 // and if so, jump to mallocMBB otherwise to bumpMBB.
20502 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20503 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20504 .addReg(tmpSPVReg).addReg(sizeVReg);
20505 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20506 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20507 .addReg(SPLimitVReg);
20508 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20510 // bumpMBB simply decreases the stack pointer, since we know the current
20511 // stacklet has enough space.
20512 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20513 .addReg(SPLimitVReg);
20514 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20515 .addReg(SPLimitVReg);
20516 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20518 // Calls into a routine in libgcc to allocate more space from the heap.
20519 const uint32_t *RegMask = MF->getTarget()
20520 .getSubtargetImpl()
20521 ->getRegisterInfo()
20522 ->getCallPreservedMask(CallingConv::C);
20524 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20526 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20527 .addExternalSymbol("__morestack_allocate_stack_space")
20528 .addRegMask(RegMask)
20529 .addReg(X86::RDI, RegState::Implicit)
20530 .addReg(X86::RAX, RegState::ImplicitDefine);
20531 } else if (Is64Bit) {
20532 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20534 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20535 .addExternalSymbol("__morestack_allocate_stack_space")
20536 .addRegMask(RegMask)
20537 .addReg(X86::EDI, RegState::Implicit)
20538 .addReg(X86::EAX, RegState::ImplicitDefine);
20540 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20542 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20543 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20544 .addExternalSymbol("__morestack_allocate_stack_space")
20545 .addRegMask(RegMask)
20546 .addReg(X86::EAX, RegState::ImplicitDefine);
20550 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20553 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20554 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20555 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20557 // Set up the CFG correctly.
20558 BB->addSuccessor(bumpMBB);
20559 BB->addSuccessor(mallocMBB);
20560 mallocMBB->addSuccessor(continueMBB);
20561 bumpMBB->addSuccessor(continueMBB);
20563 // Take care of the PHI nodes.
20564 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20565 MI->getOperand(0).getReg())
20566 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20567 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20569 // Delete the original pseudo instruction.
20570 MI->eraseFromParent();
20573 return continueMBB;
20576 MachineBasicBlock *
20577 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20578 MachineBasicBlock *BB) const {
20579 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20580 DebugLoc DL = MI->getDebugLoc();
20582 assert(!Subtarget->isTargetMacho());
20584 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20585 // non-trivial part is impdef of ESP.
20587 if (Subtarget->isTargetWin64()) {
20588 if (Subtarget->isTargetCygMing()) {
20589 // ___chkstk(Mingw64):
20590 // Clobbers R10, R11, RAX and EFLAGS.
20592 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20593 .addExternalSymbol("___chkstk")
20594 .addReg(X86::RAX, RegState::Implicit)
20595 .addReg(X86::RSP, RegState::Implicit)
20596 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20597 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20598 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20600 // __chkstk(MSVCRT): does not update stack pointer.
20601 // Clobbers R10, R11 and EFLAGS.
20602 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20603 .addExternalSymbol("__chkstk")
20604 .addReg(X86::RAX, RegState::Implicit)
20605 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20606 // RAX has the offset to be subtracted from RSP.
20607 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20612 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20613 Subtarget->isTargetWindowsItanium())
20617 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20618 .addExternalSymbol(StackProbeSymbol)
20619 .addReg(X86::EAX, RegState::Implicit)
20620 .addReg(X86::ESP, RegState::Implicit)
20621 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20622 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20623 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20626 MI->eraseFromParent(); // The pseudo instruction is gone now.
20630 MachineBasicBlock *
20631 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20632 MachineBasicBlock *BB) const {
20633 // This is pretty easy. We're taking the value that we received from
20634 // our load from the relocation, sticking it in either RDI (x86-64)
20635 // or EAX and doing an indirect call. The return value will then
20636 // be in the normal return register.
20637 MachineFunction *F = BB->getParent();
20638 const X86InstrInfo *TII =
20639 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20640 DebugLoc DL = MI->getDebugLoc();
20642 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20643 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20645 // Get a register mask for the lowered call.
20646 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20647 // proper register mask.
20648 const uint32_t *RegMask = F->getTarget()
20649 .getSubtargetImpl()
20650 ->getRegisterInfo()
20651 ->getCallPreservedMask(CallingConv::C);
20652 if (Subtarget->is64Bit()) {
20653 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20654 TII->get(X86::MOV64rm), X86::RDI)
20656 .addImm(0).addReg(0)
20657 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20658 MI->getOperand(3).getTargetFlags())
20660 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20661 addDirectMem(MIB, X86::RDI);
20662 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20663 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20664 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20665 TII->get(X86::MOV32rm), X86::EAX)
20667 .addImm(0).addReg(0)
20668 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20669 MI->getOperand(3).getTargetFlags())
20671 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20672 addDirectMem(MIB, X86::EAX);
20673 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20675 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20676 TII->get(X86::MOV32rm), X86::EAX)
20677 .addReg(TII->getGlobalBaseReg(F))
20678 .addImm(0).addReg(0)
20679 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20680 MI->getOperand(3).getTargetFlags())
20682 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20683 addDirectMem(MIB, X86::EAX);
20684 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20687 MI->eraseFromParent(); // The pseudo instruction is gone now.
20691 MachineBasicBlock *
20692 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20693 MachineBasicBlock *MBB) const {
20694 DebugLoc DL = MI->getDebugLoc();
20695 MachineFunction *MF = MBB->getParent();
20696 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20697 MachineRegisterInfo &MRI = MF->getRegInfo();
20699 const BasicBlock *BB = MBB->getBasicBlock();
20700 MachineFunction::iterator I = MBB;
20703 // Memory Reference
20704 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20705 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20708 unsigned MemOpndSlot = 0;
20710 unsigned CurOp = 0;
20712 DstReg = MI->getOperand(CurOp++).getReg();
20713 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20714 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20715 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20716 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20718 MemOpndSlot = CurOp;
20720 MVT PVT = getPointerTy();
20721 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20722 "Invalid Pointer Size!");
20724 // For v = setjmp(buf), we generate
20727 // buf[LabelOffset] = restoreMBB
20728 // SjLjSetup restoreMBB
20734 // v = phi(main, restore)
20739 MachineBasicBlock *thisMBB = MBB;
20740 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20741 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20742 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20743 MF->insert(I, mainMBB);
20744 MF->insert(I, sinkMBB);
20745 MF->push_back(restoreMBB);
20747 MachineInstrBuilder MIB;
20749 // Transfer the remainder of BB and its successor edges to sinkMBB.
20750 sinkMBB->splice(sinkMBB->begin(), MBB,
20751 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20752 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20755 unsigned PtrStoreOpc = 0;
20756 unsigned LabelReg = 0;
20757 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20758 Reloc::Model RM = MF->getTarget().getRelocationModel();
20759 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20760 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20762 // Prepare IP either in reg or imm.
20763 if (!UseImmLabel) {
20764 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20765 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20766 LabelReg = MRI.createVirtualRegister(PtrRC);
20767 if (Subtarget->is64Bit()) {
20768 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20772 .addMBB(restoreMBB)
20775 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20776 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20777 .addReg(XII->getGlobalBaseReg(MF))
20780 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20784 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20786 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20787 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20788 if (i == X86::AddrDisp)
20789 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20791 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20794 MIB.addReg(LabelReg);
20796 MIB.addMBB(restoreMBB);
20797 MIB.setMemRefs(MMOBegin, MMOEnd);
20799 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20800 .addMBB(restoreMBB);
20802 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20803 MF->getSubtarget().getRegisterInfo());
20804 MIB.addRegMask(RegInfo->getNoPreservedMask());
20805 thisMBB->addSuccessor(mainMBB);
20806 thisMBB->addSuccessor(restoreMBB);
20810 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20811 mainMBB->addSuccessor(sinkMBB);
20814 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20815 TII->get(X86::PHI), DstReg)
20816 .addReg(mainDstReg).addMBB(mainMBB)
20817 .addReg(restoreDstReg).addMBB(restoreMBB);
20820 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20821 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20822 restoreMBB->addSuccessor(sinkMBB);
20824 MI->eraseFromParent();
20828 MachineBasicBlock *
20829 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20830 MachineBasicBlock *MBB) const {
20831 DebugLoc DL = MI->getDebugLoc();
20832 MachineFunction *MF = MBB->getParent();
20833 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20834 MachineRegisterInfo &MRI = MF->getRegInfo();
20836 // Memory Reference
20837 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20838 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20840 MVT PVT = getPointerTy();
20841 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20842 "Invalid Pointer Size!");
20844 const TargetRegisterClass *RC =
20845 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20846 unsigned Tmp = MRI.createVirtualRegister(RC);
20847 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20848 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20849 MF->getSubtarget().getRegisterInfo());
20850 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20851 unsigned SP = RegInfo->getStackRegister();
20853 MachineInstrBuilder MIB;
20855 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20856 const int64_t SPOffset = 2 * PVT.getStoreSize();
20858 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20859 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20862 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20863 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20864 MIB.addOperand(MI->getOperand(i));
20865 MIB.setMemRefs(MMOBegin, MMOEnd);
20867 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20868 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20869 if (i == X86::AddrDisp)
20870 MIB.addDisp(MI->getOperand(i), LabelOffset);
20872 MIB.addOperand(MI->getOperand(i));
20874 MIB.setMemRefs(MMOBegin, MMOEnd);
20876 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20877 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20878 if (i == X86::AddrDisp)
20879 MIB.addDisp(MI->getOperand(i), SPOffset);
20881 MIB.addOperand(MI->getOperand(i));
20883 MIB.setMemRefs(MMOBegin, MMOEnd);
20885 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20887 MI->eraseFromParent();
20891 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20892 // accumulator loops. Writing back to the accumulator allows the coalescer
20893 // to remove extra copies in the loop.
20894 MachineBasicBlock *
20895 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20896 MachineBasicBlock *MBB) const {
20897 MachineOperand &AddendOp = MI->getOperand(3);
20899 // Bail out early if the addend isn't a register - we can't switch these.
20900 if (!AddendOp.isReg())
20903 MachineFunction &MF = *MBB->getParent();
20904 MachineRegisterInfo &MRI = MF.getRegInfo();
20906 // Check whether the addend is defined by a PHI:
20907 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20908 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20909 if (!AddendDef.isPHI())
20912 // Look for the following pattern:
20914 // %addend = phi [%entry, 0], [%loop, %result]
20916 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20920 // %addend = phi [%entry, 0], [%loop, %result]
20922 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20924 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20925 assert(AddendDef.getOperand(i).isReg());
20926 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20927 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20928 if (&PHISrcInst == MI) {
20929 // Found a matching instruction.
20930 unsigned NewFMAOpc = 0;
20931 switch (MI->getOpcode()) {
20932 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20933 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20934 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20935 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20936 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20937 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20938 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20939 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20940 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20941 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20942 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20943 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20944 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20945 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20946 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20947 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20948 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20949 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20950 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20951 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20953 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20954 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20955 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20956 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20957 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20958 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20959 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20960 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20961 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20962 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20963 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20964 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20965 default: llvm_unreachable("Unrecognized FMA variant.");
20968 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20969 MachineInstrBuilder MIB =
20970 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20971 .addOperand(MI->getOperand(0))
20972 .addOperand(MI->getOperand(3))
20973 .addOperand(MI->getOperand(2))
20974 .addOperand(MI->getOperand(1));
20975 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20976 MI->eraseFromParent();
20983 MachineBasicBlock *
20984 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20985 MachineBasicBlock *BB) const {
20986 switch (MI->getOpcode()) {
20987 default: llvm_unreachable("Unexpected instr type to insert");
20988 case X86::TAILJMPd64:
20989 case X86::TAILJMPr64:
20990 case X86::TAILJMPm64:
20991 llvm_unreachable("TAILJMP64 would not be touched here.");
20992 case X86::TCRETURNdi64:
20993 case X86::TCRETURNri64:
20994 case X86::TCRETURNmi64:
20996 case X86::WIN_ALLOCA:
20997 return EmitLoweredWinAlloca(MI, BB);
20998 case X86::SEG_ALLOCA_32:
20999 case X86::SEG_ALLOCA_64:
21000 return EmitLoweredSegAlloca(MI, BB);
21001 case X86::TLSCall_32:
21002 case X86::TLSCall_64:
21003 return EmitLoweredTLSCall(MI, BB);
21004 case X86::CMOV_GR8:
21005 case X86::CMOV_FR32:
21006 case X86::CMOV_FR64:
21007 case X86::CMOV_V4F32:
21008 case X86::CMOV_V2F64:
21009 case X86::CMOV_V2I64:
21010 case X86::CMOV_V8F32:
21011 case X86::CMOV_V4F64:
21012 case X86::CMOV_V4I64:
21013 case X86::CMOV_V16F32:
21014 case X86::CMOV_V8F64:
21015 case X86::CMOV_V8I64:
21016 case X86::CMOV_GR16:
21017 case X86::CMOV_GR32:
21018 case X86::CMOV_RFP32:
21019 case X86::CMOV_RFP64:
21020 case X86::CMOV_RFP80:
21021 return EmitLoweredSelect(MI, BB);
21023 case X86::FP32_TO_INT16_IN_MEM:
21024 case X86::FP32_TO_INT32_IN_MEM:
21025 case X86::FP32_TO_INT64_IN_MEM:
21026 case X86::FP64_TO_INT16_IN_MEM:
21027 case X86::FP64_TO_INT32_IN_MEM:
21028 case X86::FP64_TO_INT64_IN_MEM:
21029 case X86::FP80_TO_INT16_IN_MEM:
21030 case X86::FP80_TO_INT32_IN_MEM:
21031 case X86::FP80_TO_INT64_IN_MEM: {
21032 MachineFunction *F = BB->getParent();
21033 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21034 DebugLoc DL = MI->getDebugLoc();
21036 // Change the floating point control register to use "round towards zero"
21037 // mode when truncating to an integer value.
21038 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21039 addFrameReference(BuildMI(*BB, MI, DL,
21040 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21042 // Load the old value of the high byte of the control word...
21044 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21045 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21048 // Set the high part to be round to zero...
21049 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21052 // Reload the modified control word now...
21053 addFrameReference(BuildMI(*BB, MI, DL,
21054 TII->get(X86::FLDCW16m)), CWFrameIdx);
21056 // Restore the memory image of control word to original value
21057 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21060 // Get the X86 opcode to use.
21062 switch (MI->getOpcode()) {
21063 default: llvm_unreachable("illegal opcode!");
21064 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21065 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21066 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21067 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21068 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21069 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21070 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21071 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21072 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21076 MachineOperand &Op = MI->getOperand(0);
21078 AM.BaseType = X86AddressMode::RegBase;
21079 AM.Base.Reg = Op.getReg();
21081 AM.BaseType = X86AddressMode::FrameIndexBase;
21082 AM.Base.FrameIndex = Op.getIndex();
21084 Op = MI->getOperand(1);
21086 AM.Scale = Op.getImm();
21087 Op = MI->getOperand(2);
21089 AM.IndexReg = Op.getImm();
21090 Op = MI->getOperand(3);
21091 if (Op.isGlobal()) {
21092 AM.GV = Op.getGlobal();
21094 AM.Disp = Op.getImm();
21096 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21097 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21099 // Reload the original control word now.
21100 addFrameReference(BuildMI(*BB, MI, DL,
21101 TII->get(X86::FLDCW16m)), CWFrameIdx);
21103 MI->eraseFromParent(); // The pseudo instruction is gone now.
21106 // String/text processing lowering.
21107 case X86::PCMPISTRM128REG:
21108 case X86::VPCMPISTRM128REG:
21109 case X86::PCMPISTRM128MEM:
21110 case X86::VPCMPISTRM128MEM:
21111 case X86::PCMPESTRM128REG:
21112 case X86::VPCMPESTRM128REG:
21113 case X86::PCMPESTRM128MEM:
21114 case X86::VPCMPESTRM128MEM:
21115 assert(Subtarget->hasSSE42() &&
21116 "Target must have SSE4.2 or AVX features enabled");
21117 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21119 // String/text processing lowering.
21120 case X86::PCMPISTRIREG:
21121 case X86::VPCMPISTRIREG:
21122 case X86::PCMPISTRIMEM:
21123 case X86::VPCMPISTRIMEM:
21124 case X86::PCMPESTRIREG:
21125 case X86::VPCMPESTRIREG:
21126 case X86::PCMPESTRIMEM:
21127 case X86::VPCMPESTRIMEM:
21128 assert(Subtarget->hasSSE42() &&
21129 "Target must have SSE4.2 or AVX features enabled");
21130 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21132 // Thread synchronization.
21134 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21139 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21141 case X86::VASTART_SAVE_XMM_REGS:
21142 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21144 case X86::VAARG_64:
21145 return EmitVAARG64WithCustomInserter(MI, BB);
21147 case X86::EH_SjLj_SetJmp32:
21148 case X86::EH_SjLj_SetJmp64:
21149 return emitEHSjLjSetJmp(MI, BB);
21151 case X86::EH_SjLj_LongJmp32:
21152 case X86::EH_SjLj_LongJmp64:
21153 return emitEHSjLjLongJmp(MI, BB);
21155 case TargetOpcode::STACKMAP:
21156 case TargetOpcode::PATCHPOINT:
21157 return emitPatchPoint(MI, BB);
21159 case X86::VFMADDPDr213r:
21160 case X86::VFMADDPSr213r:
21161 case X86::VFMADDSDr213r:
21162 case X86::VFMADDSSr213r:
21163 case X86::VFMSUBPDr213r:
21164 case X86::VFMSUBPSr213r:
21165 case X86::VFMSUBSDr213r:
21166 case X86::VFMSUBSSr213r:
21167 case X86::VFNMADDPDr213r:
21168 case X86::VFNMADDPSr213r:
21169 case X86::VFNMADDSDr213r:
21170 case X86::VFNMADDSSr213r:
21171 case X86::VFNMSUBPDr213r:
21172 case X86::VFNMSUBPSr213r:
21173 case X86::VFNMSUBSDr213r:
21174 case X86::VFNMSUBSSr213r:
21175 case X86::VFMADDSUBPDr213r:
21176 case X86::VFMADDSUBPSr213r:
21177 case X86::VFMSUBADDPDr213r:
21178 case X86::VFMSUBADDPSr213r:
21179 case X86::VFMADDPDr213rY:
21180 case X86::VFMADDPSr213rY:
21181 case X86::VFMSUBPDr213rY:
21182 case X86::VFMSUBPSr213rY:
21183 case X86::VFNMADDPDr213rY:
21184 case X86::VFNMADDPSr213rY:
21185 case X86::VFNMSUBPDr213rY:
21186 case X86::VFNMSUBPSr213rY:
21187 case X86::VFMADDSUBPDr213rY:
21188 case X86::VFMADDSUBPSr213rY:
21189 case X86::VFMSUBADDPDr213rY:
21190 case X86::VFMSUBADDPSr213rY:
21191 return emitFMA3Instr(MI, BB);
21195 //===----------------------------------------------------------------------===//
21196 // X86 Optimization Hooks
21197 //===----------------------------------------------------------------------===//
21199 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21202 const SelectionDAG &DAG,
21203 unsigned Depth) const {
21204 unsigned BitWidth = KnownZero.getBitWidth();
21205 unsigned Opc = Op.getOpcode();
21206 assert((Opc >= ISD::BUILTIN_OP_END ||
21207 Opc == ISD::INTRINSIC_WO_CHAIN ||
21208 Opc == ISD::INTRINSIC_W_CHAIN ||
21209 Opc == ISD::INTRINSIC_VOID) &&
21210 "Should use MaskedValueIsZero if you don't know whether Op"
21211 " is a target node!");
21213 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21227 // These nodes' second result is a boolean.
21228 if (Op.getResNo() == 0)
21231 case X86ISD::SETCC:
21232 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21234 case ISD::INTRINSIC_WO_CHAIN: {
21235 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21236 unsigned NumLoBits = 0;
21239 case Intrinsic::x86_sse_movmsk_ps:
21240 case Intrinsic::x86_avx_movmsk_ps_256:
21241 case Intrinsic::x86_sse2_movmsk_pd:
21242 case Intrinsic::x86_avx_movmsk_pd_256:
21243 case Intrinsic::x86_mmx_pmovmskb:
21244 case Intrinsic::x86_sse2_pmovmskb_128:
21245 case Intrinsic::x86_avx2_pmovmskb: {
21246 // High bits of movmskp{s|d}, pmovmskb are known zero.
21248 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21249 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21250 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21251 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21252 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21253 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21254 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21255 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21257 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21266 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21268 const SelectionDAG &,
21269 unsigned Depth) const {
21270 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21271 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21272 return Op.getValueType().getScalarType().getSizeInBits();
21278 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21279 /// node is a GlobalAddress + offset.
21280 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21281 const GlobalValue* &GA,
21282 int64_t &Offset) const {
21283 if (N->getOpcode() == X86ISD::Wrapper) {
21284 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21285 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21286 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21290 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21293 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21294 /// same as extracting the high 128-bit part of 256-bit vector and then
21295 /// inserting the result into the low part of a new 256-bit vector
21296 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21297 EVT VT = SVOp->getValueType(0);
21298 unsigned NumElems = VT.getVectorNumElements();
21300 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21301 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21302 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21303 SVOp->getMaskElt(j) >= 0)
21309 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21310 /// same as extracting the low 128-bit part of 256-bit vector and then
21311 /// inserting the result into the high part of a new 256-bit vector
21312 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21313 EVT VT = SVOp->getValueType(0);
21314 unsigned NumElems = VT.getVectorNumElements();
21316 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21317 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21318 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21319 SVOp->getMaskElt(j) >= 0)
21325 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21326 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21327 TargetLowering::DAGCombinerInfo &DCI,
21328 const X86Subtarget* Subtarget) {
21330 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21331 SDValue V1 = SVOp->getOperand(0);
21332 SDValue V2 = SVOp->getOperand(1);
21333 EVT VT = SVOp->getValueType(0);
21334 unsigned NumElems = VT.getVectorNumElements();
21336 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21337 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21341 // V UNDEF BUILD_VECTOR UNDEF
21343 // CONCAT_VECTOR CONCAT_VECTOR
21346 // RESULT: V + zero extended
21348 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21349 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21350 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21353 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21356 // To match the shuffle mask, the first half of the mask should
21357 // be exactly the first vector, and all the rest a splat with the
21358 // first element of the second one.
21359 for (unsigned i = 0; i != NumElems/2; ++i)
21360 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21361 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21364 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21365 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21366 if (Ld->hasNUsesOfValue(1, 0)) {
21367 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21368 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21370 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21372 Ld->getPointerInfo(),
21373 Ld->getAlignment(),
21374 false/*isVolatile*/, true/*ReadMem*/,
21375 false/*WriteMem*/);
21377 // Make sure the newly-created LOAD is in the same position as Ld in
21378 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21379 // and update uses of Ld's output chain to use the TokenFactor.
21380 if (Ld->hasAnyUseOfValue(1)) {
21381 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21382 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21383 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21384 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21385 SDValue(ResNode.getNode(), 1));
21388 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21392 // Emit a zeroed vector and insert the desired subvector on its
21394 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21395 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21396 return DCI.CombineTo(N, InsV);
21399 //===--------------------------------------------------------------------===//
21400 // Combine some shuffles into subvector extracts and inserts:
21403 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21404 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21405 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21406 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21407 return DCI.CombineTo(N, InsV);
21410 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21411 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21412 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21413 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21414 return DCI.CombineTo(N, InsV);
21420 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21423 /// This is the leaf of the recursive combinine below. When we have found some
21424 /// chain of single-use x86 shuffle instructions and accumulated the combined
21425 /// shuffle mask represented by them, this will try to pattern match that mask
21426 /// into either a single instruction if there is a special purpose instruction
21427 /// for this operation, or into a PSHUFB instruction which is a fully general
21428 /// instruction but should only be used to replace chains over a certain depth.
21429 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21430 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21431 TargetLowering::DAGCombinerInfo &DCI,
21432 const X86Subtarget *Subtarget) {
21433 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21435 // Find the operand that enters the chain. Note that multiple uses are OK
21436 // here, we're not going to remove the operand we find.
21437 SDValue Input = Op.getOperand(0);
21438 while (Input.getOpcode() == ISD::BITCAST)
21439 Input = Input.getOperand(0);
21441 MVT VT = Input.getSimpleValueType();
21442 MVT RootVT = Root.getSimpleValueType();
21445 // Just remove no-op shuffle masks.
21446 if (Mask.size() == 1) {
21447 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21452 // Use the float domain if the operand type is a floating point type.
21453 bool FloatDomain = VT.isFloatingPoint();
21455 // For floating point shuffles, we don't have free copies in the shuffle
21456 // instructions or the ability to load as part of the instruction, so
21457 // canonicalize their shuffles to UNPCK or MOV variants.
21459 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21460 // vectors because it can have a load folded into it that UNPCK cannot. This
21461 // doesn't preclude something switching to the shorter encoding post-RA.
21463 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21464 bool Lo = Mask.equals(0, 0);
21467 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21468 // is no slower than UNPCKLPD but has the option to fold the input operand
21469 // into even an unaligned memory load.
21470 if (Lo && Subtarget->hasSSE3()) {
21471 Shuffle = X86ISD::MOVDDUP;
21472 ShuffleVT = MVT::v2f64;
21474 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21475 // than the UNPCK variants.
21476 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21477 ShuffleVT = MVT::v4f32;
21479 if (Depth == 1 && Root->getOpcode() == Shuffle)
21480 return false; // Nothing to do!
21481 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21482 DCI.AddToWorklist(Op.getNode());
21483 if (Shuffle == X86ISD::MOVDDUP)
21484 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21486 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21487 DCI.AddToWorklist(Op.getNode());
21488 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21492 if (Subtarget->hasSSE3() &&
21493 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21494 bool Lo = Mask.equals(0, 0, 2, 2);
21495 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21496 MVT ShuffleVT = MVT::v4f32;
21497 if (Depth == 1 && Root->getOpcode() == Shuffle)
21498 return false; // Nothing to do!
21499 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21500 DCI.AddToWorklist(Op.getNode());
21501 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21502 DCI.AddToWorklist(Op.getNode());
21503 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21507 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21508 bool Lo = Mask.equals(0, 0, 1, 1);
21509 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21510 MVT ShuffleVT = MVT::v4f32;
21511 if (Depth == 1 && Root->getOpcode() == Shuffle)
21512 return false; // Nothing to do!
21513 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21514 DCI.AddToWorklist(Op.getNode());
21515 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21516 DCI.AddToWorklist(Op.getNode());
21517 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21523 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21524 // variants as none of these have single-instruction variants that are
21525 // superior to the UNPCK formulation.
21526 if (!FloatDomain &&
21527 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21528 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21529 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21530 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21532 bool Lo = Mask[0] == 0;
21533 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21534 if (Depth == 1 && Root->getOpcode() == Shuffle)
21535 return false; // Nothing to do!
21537 switch (Mask.size()) {
21539 ShuffleVT = MVT::v8i16;
21542 ShuffleVT = MVT::v16i8;
21545 llvm_unreachable("Impossible mask size!");
21547 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21548 DCI.AddToWorklist(Op.getNode());
21549 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21550 DCI.AddToWorklist(Op.getNode());
21551 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21556 // Don't try to re-form single instruction chains under any circumstances now
21557 // that we've done encoding canonicalization for them.
21561 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21562 // can replace them with a single PSHUFB instruction profitably. Intel's
21563 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21564 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21565 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21566 SmallVector<SDValue, 16> PSHUFBMask;
21567 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21568 int Ratio = 16 / Mask.size();
21569 for (unsigned i = 0; i < 16; ++i) {
21570 if (Mask[i / Ratio] == SM_SentinelUndef) {
21571 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21574 int M = Mask[i / Ratio] != SM_SentinelZero
21575 ? Ratio * Mask[i / Ratio] + i % Ratio
21577 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21579 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21580 DCI.AddToWorklist(Op.getNode());
21581 SDValue PSHUFBMaskOp =
21582 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21583 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21584 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21585 DCI.AddToWorklist(Op.getNode());
21586 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21591 // Failed to find any combines.
21595 /// \brief Fully generic combining of x86 shuffle instructions.
21597 /// This should be the last combine run over the x86 shuffle instructions. Once
21598 /// they have been fully optimized, this will recursively consider all chains
21599 /// of single-use shuffle instructions, build a generic model of the cumulative
21600 /// shuffle operation, and check for simpler instructions which implement this
21601 /// operation. We use this primarily for two purposes:
21603 /// 1) Collapse generic shuffles to specialized single instructions when
21604 /// equivalent. In most cases, this is just an encoding size win, but
21605 /// sometimes we will collapse multiple generic shuffles into a single
21606 /// special-purpose shuffle.
21607 /// 2) Look for sequences of shuffle instructions with 3 or more total
21608 /// instructions, and replace them with the slightly more expensive SSSE3
21609 /// PSHUFB instruction if available. We do this as the last combining step
21610 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21611 /// a suitable short sequence of other instructions. The PHUFB will either
21612 /// use a register or have to read from memory and so is slightly (but only
21613 /// slightly) more expensive than the other shuffle instructions.
21615 /// Because this is inherently a quadratic operation (for each shuffle in
21616 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21617 /// This should never be an issue in practice as the shuffle lowering doesn't
21618 /// produce sequences of more than 8 instructions.
21620 /// FIXME: We will currently miss some cases where the redundant shuffling
21621 /// would simplify under the threshold for PSHUFB formation because of
21622 /// combine-ordering. To fix this, we should do the redundant instruction
21623 /// combining in this recursive walk.
21624 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21625 ArrayRef<int> RootMask,
21626 int Depth, bool HasPSHUFB,
21628 TargetLowering::DAGCombinerInfo &DCI,
21629 const X86Subtarget *Subtarget) {
21630 // Bound the depth of our recursive combine because this is ultimately
21631 // quadratic in nature.
21635 // Directly rip through bitcasts to find the underlying operand.
21636 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21637 Op = Op.getOperand(0);
21639 MVT VT = Op.getSimpleValueType();
21640 if (!VT.isVector())
21641 return false; // Bail if we hit a non-vector.
21642 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21643 // version should be added.
21644 if (VT.getSizeInBits() != 128)
21647 assert(Root.getSimpleValueType().isVector() &&
21648 "Shuffles operate on vector types!");
21649 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21650 "Can only combine shuffles of the same vector register size.");
21652 if (!isTargetShuffle(Op.getOpcode()))
21654 SmallVector<int, 16> OpMask;
21656 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21657 // We only can combine unary shuffles which we can decode the mask for.
21658 if (!HaveMask || !IsUnary)
21661 assert(VT.getVectorNumElements() == OpMask.size() &&
21662 "Different mask size from vector size!");
21663 assert(((RootMask.size() > OpMask.size() &&
21664 RootMask.size() % OpMask.size() == 0) ||
21665 (OpMask.size() > RootMask.size() &&
21666 OpMask.size() % RootMask.size() == 0) ||
21667 OpMask.size() == RootMask.size()) &&
21668 "The smaller number of elements must divide the larger.");
21669 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21670 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21671 assert(((RootRatio == 1 && OpRatio == 1) ||
21672 (RootRatio == 1) != (OpRatio == 1)) &&
21673 "Must not have a ratio for both incoming and op masks!");
21675 SmallVector<int, 16> Mask;
21676 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21678 // Merge this shuffle operation's mask into our accumulated mask. Note that
21679 // this shuffle's mask will be the first applied to the input, followed by the
21680 // root mask to get us all the way to the root value arrangement. The reason
21681 // for this order is that we are recursing up the operation chain.
21682 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21683 int RootIdx = i / RootRatio;
21684 if (RootMask[RootIdx] < 0) {
21685 // This is a zero or undef lane, we're done.
21686 Mask.push_back(RootMask[RootIdx]);
21690 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21691 int OpIdx = RootMaskedIdx / OpRatio;
21692 if (OpMask[OpIdx] < 0) {
21693 // The incoming lanes are zero or undef, it doesn't matter which ones we
21695 Mask.push_back(OpMask[OpIdx]);
21699 // Ok, we have non-zero lanes, map them through.
21700 Mask.push_back(OpMask[OpIdx] * OpRatio +
21701 RootMaskedIdx % OpRatio);
21704 // See if we can recurse into the operand to combine more things.
21705 switch (Op.getOpcode()) {
21706 case X86ISD::PSHUFB:
21708 case X86ISD::PSHUFD:
21709 case X86ISD::PSHUFHW:
21710 case X86ISD::PSHUFLW:
21711 if (Op.getOperand(0).hasOneUse() &&
21712 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21713 HasPSHUFB, DAG, DCI, Subtarget))
21717 case X86ISD::UNPCKL:
21718 case X86ISD::UNPCKH:
21719 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21720 // We can't check for single use, we have to check that this shuffle is the only user.
21721 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21722 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21723 HasPSHUFB, DAG, DCI, Subtarget))
21728 // Minor canonicalization of the accumulated shuffle mask to make it easier
21729 // to match below. All this does is detect masks with squential pairs of
21730 // elements, and shrink them to the half-width mask. It does this in a loop
21731 // so it will reduce the size of the mask to the minimal width mask which
21732 // performs an equivalent shuffle.
21733 SmallVector<int, 16> WidenedMask;
21734 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21735 Mask = std::move(WidenedMask);
21736 WidenedMask.clear();
21739 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21743 /// \brief Get the PSHUF-style mask from PSHUF node.
21745 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21746 /// PSHUF-style masks that can be reused with such instructions.
21747 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21748 SmallVector<int, 4> Mask;
21750 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21754 switch (N.getOpcode()) {
21755 case X86ISD::PSHUFD:
21757 case X86ISD::PSHUFLW:
21760 case X86ISD::PSHUFHW:
21761 Mask.erase(Mask.begin(), Mask.begin() + 4);
21762 for (int &M : Mask)
21766 llvm_unreachable("No valid shuffle instruction found!");
21770 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21772 /// We walk up the chain and look for a combinable shuffle, skipping over
21773 /// shuffles that we could hoist this shuffle's transformation past without
21774 /// altering anything.
21776 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21778 TargetLowering::DAGCombinerInfo &DCI) {
21779 assert(N.getOpcode() == X86ISD::PSHUFD &&
21780 "Called with something other than an x86 128-bit half shuffle!");
21783 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21784 // of the shuffles in the chain so that we can form a fresh chain to replace
21786 SmallVector<SDValue, 8> Chain;
21787 SDValue V = N.getOperand(0);
21788 for (; V.hasOneUse(); V = V.getOperand(0)) {
21789 switch (V.getOpcode()) {
21791 return SDValue(); // Nothing combined!
21794 // Skip bitcasts as we always know the type for the target specific
21798 case X86ISD::PSHUFD:
21799 // Found another dword shuffle.
21802 case X86ISD::PSHUFLW:
21803 // Check that the low words (being shuffled) are the identity in the
21804 // dword shuffle, and the high words are self-contained.
21805 if (Mask[0] != 0 || Mask[1] != 1 ||
21806 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21809 Chain.push_back(V);
21812 case X86ISD::PSHUFHW:
21813 // Check that the high words (being shuffled) are the identity in the
21814 // dword shuffle, and the low words are self-contained.
21815 if (Mask[2] != 2 || Mask[3] != 3 ||
21816 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21819 Chain.push_back(V);
21822 case X86ISD::UNPCKL:
21823 case X86ISD::UNPCKH:
21824 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21825 // shuffle into a preceding word shuffle.
21826 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21829 // Search for a half-shuffle which we can combine with.
21830 unsigned CombineOp =
21831 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21832 if (V.getOperand(0) != V.getOperand(1) ||
21833 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21835 Chain.push_back(V);
21836 V = V.getOperand(0);
21838 switch (V.getOpcode()) {
21840 return SDValue(); // Nothing to combine.
21842 case X86ISD::PSHUFLW:
21843 case X86ISD::PSHUFHW:
21844 if (V.getOpcode() == CombineOp)
21847 Chain.push_back(V);
21851 V = V.getOperand(0);
21855 } while (V.hasOneUse());
21858 // Break out of the loop if we break out of the switch.
21862 if (!V.hasOneUse())
21863 // We fell out of the loop without finding a viable combining instruction.
21866 // Merge this node's mask and our incoming mask.
21867 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21868 for (int &M : Mask)
21870 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21871 getV4X86ShuffleImm8ForMask(Mask, DAG));
21873 // Rebuild the chain around this new shuffle.
21874 while (!Chain.empty()) {
21875 SDValue W = Chain.pop_back_val();
21877 if (V.getValueType() != W.getOperand(0).getValueType())
21878 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21880 switch (W.getOpcode()) {
21882 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21884 case X86ISD::UNPCKL:
21885 case X86ISD::UNPCKH:
21886 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21889 case X86ISD::PSHUFD:
21890 case X86ISD::PSHUFLW:
21891 case X86ISD::PSHUFHW:
21892 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21896 if (V.getValueType() != N.getValueType())
21897 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21899 // Return the new chain to replace N.
21903 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21905 /// We walk up the chain, skipping shuffles of the other half and looking
21906 /// through shuffles which switch halves trying to find a shuffle of the same
21907 /// pair of dwords.
21908 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21910 TargetLowering::DAGCombinerInfo &DCI) {
21912 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21913 "Called with something other than an x86 128-bit half shuffle!");
21915 unsigned CombineOpcode = N.getOpcode();
21917 // Walk up a single-use chain looking for a combinable shuffle.
21918 SDValue V = N.getOperand(0);
21919 for (; V.hasOneUse(); V = V.getOperand(0)) {
21920 switch (V.getOpcode()) {
21922 return false; // Nothing combined!
21925 // Skip bitcasts as we always know the type for the target specific
21929 case X86ISD::PSHUFLW:
21930 case X86ISD::PSHUFHW:
21931 if (V.getOpcode() == CombineOpcode)
21934 // Other-half shuffles are no-ops.
21937 // Break out of the loop if we break out of the switch.
21941 if (!V.hasOneUse())
21942 // We fell out of the loop without finding a viable combining instruction.
21945 // Combine away the bottom node as its shuffle will be accumulated into
21946 // a preceding shuffle.
21947 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21949 // Record the old value.
21952 // Merge this node's mask and our incoming mask (adjusted to account for all
21953 // the pshufd instructions encountered).
21954 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21955 for (int &M : Mask)
21957 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21958 getV4X86ShuffleImm8ForMask(Mask, DAG));
21960 // Check that the shuffles didn't cancel each other out. If not, we need to
21961 // combine to the new one.
21963 // Replace the combinable shuffle with the combined one, updating all users
21964 // so that we re-evaluate the chain here.
21965 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21970 /// \brief Try to combine x86 target specific shuffles.
21971 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21972 TargetLowering::DAGCombinerInfo &DCI,
21973 const X86Subtarget *Subtarget) {
21975 MVT VT = N.getSimpleValueType();
21976 SmallVector<int, 4> Mask;
21978 switch (N.getOpcode()) {
21979 case X86ISD::PSHUFD:
21980 case X86ISD::PSHUFLW:
21981 case X86ISD::PSHUFHW:
21982 Mask = getPSHUFShuffleMask(N);
21983 assert(Mask.size() == 4);
21989 // Nuke no-op shuffles that show up after combining.
21990 if (isNoopShuffleMask(Mask))
21991 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21993 // Look for simplifications involving one or two shuffle instructions.
21994 SDValue V = N.getOperand(0);
21995 switch (N.getOpcode()) {
21998 case X86ISD::PSHUFLW:
21999 case X86ISD::PSHUFHW:
22000 assert(VT == MVT::v8i16);
22003 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22004 return SDValue(); // We combined away this shuffle, so we're done.
22006 // See if this reduces to a PSHUFD which is no more expensive and can
22007 // combine with more operations. Note that it has to at least flip the
22008 // dwords as otherwise it would have been removed as a no-op.
22009 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22010 int DMask[] = {0, 1, 2, 3};
22011 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22012 DMask[DOffset + 0] = DOffset + 1;
22013 DMask[DOffset + 1] = DOffset + 0;
22014 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22015 DCI.AddToWorklist(V.getNode());
22016 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22017 getV4X86ShuffleImm8ForMask(DMask, DAG));
22018 DCI.AddToWorklist(V.getNode());
22019 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22022 // Look for shuffle patterns which can be implemented as a single unpack.
22023 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22024 // only works when we have a PSHUFD followed by two half-shuffles.
22025 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22026 (V.getOpcode() == X86ISD::PSHUFLW ||
22027 V.getOpcode() == X86ISD::PSHUFHW) &&
22028 V.getOpcode() != N.getOpcode() &&
22030 SDValue D = V.getOperand(0);
22031 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22032 D = D.getOperand(0);
22033 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22034 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22035 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22036 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22037 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22039 for (int i = 0; i < 4; ++i) {
22040 WordMask[i + NOffset] = Mask[i] + NOffset;
22041 WordMask[i + VOffset] = VMask[i] + VOffset;
22043 // Map the word mask through the DWord mask.
22045 for (int i = 0; i < 8; ++i)
22046 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22047 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22048 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22049 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22050 std::begin(UnpackLoMask)) ||
22051 std::equal(std::begin(MappedMask), std::end(MappedMask),
22052 std::begin(UnpackHiMask))) {
22053 // We can replace all three shuffles with an unpack.
22054 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22055 DCI.AddToWorklist(V.getNode());
22056 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22058 DL, MVT::v8i16, V, V);
22065 case X86ISD::PSHUFD:
22066 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22075 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22077 /// We combine this directly on the abstract vector shuffle nodes so it is
22078 /// easier to generically match. We also insert dummy vector shuffle nodes for
22079 /// the operands which explicitly discard the lanes which are unused by this
22080 /// operation to try to flow through the rest of the combiner the fact that
22081 /// they're unused.
22082 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22084 EVT VT = N->getValueType(0);
22086 // We only handle target-independent shuffles.
22087 // FIXME: It would be easy and harmless to use the target shuffle mask
22088 // extraction tool to support more.
22089 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22092 auto *SVN = cast<ShuffleVectorSDNode>(N);
22093 ArrayRef<int> Mask = SVN->getMask();
22094 SDValue V1 = N->getOperand(0);
22095 SDValue V2 = N->getOperand(1);
22097 // We require the first shuffle operand to be the SUB node, and the second to
22098 // be the ADD node.
22099 // FIXME: We should support the commuted patterns.
22100 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22103 // If there are other uses of these operations we can't fold them.
22104 if (!V1->hasOneUse() || !V2->hasOneUse())
22107 // Ensure that both operations have the same operands. Note that we can
22108 // commute the FADD operands.
22109 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22110 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22111 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22114 // We're looking for blends between FADD and FSUB nodes. We insist on these
22115 // nodes being lined up in a specific expected pattern.
22116 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22117 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22118 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22121 // Only specific types are legal at this point, assert so we notice if and
22122 // when these change.
22123 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22124 VT == MVT::v4f64) &&
22125 "Unknown vector type encountered!");
22127 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22130 /// PerformShuffleCombine - Performs several different shuffle combines.
22131 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22132 TargetLowering::DAGCombinerInfo &DCI,
22133 const X86Subtarget *Subtarget) {
22135 SDValue N0 = N->getOperand(0);
22136 SDValue N1 = N->getOperand(1);
22137 EVT VT = N->getValueType(0);
22139 // Don't create instructions with illegal types after legalize types has run.
22140 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22141 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22144 // If we have legalized the vector types, look for blends of FADD and FSUB
22145 // nodes that we can fuse into an ADDSUB node.
22146 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22147 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22150 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22151 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22152 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22153 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22155 // During Type Legalization, when promoting illegal vector types,
22156 // the backend might introduce new shuffle dag nodes and bitcasts.
22158 // This code performs the following transformation:
22159 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22160 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22162 // We do this only if both the bitcast and the BINOP dag nodes have
22163 // one use. Also, perform this transformation only if the new binary
22164 // operation is legal. This is to avoid introducing dag nodes that
22165 // potentially need to be further expanded (or custom lowered) into a
22166 // less optimal sequence of dag nodes.
22167 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22168 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22169 N0.getOpcode() == ISD::BITCAST) {
22170 SDValue BC0 = N0.getOperand(0);
22171 EVT SVT = BC0.getValueType();
22172 unsigned Opcode = BC0.getOpcode();
22173 unsigned NumElts = VT.getVectorNumElements();
22175 if (BC0.hasOneUse() && SVT.isVector() &&
22176 SVT.getVectorNumElements() * 2 == NumElts &&
22177 TLI.isOperationLegal(Opcode, VT)) {
22178 bool CanFold = false;
22190 unsigned SVTNumElts = SVT.getVectorNumElements();
22191 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22192 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22193 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22194 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22195 CanFold = SVOp->getMaskElt(i) < 0;
22198 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22199 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22200 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22201 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22206 // Only handle 128 wide vector from here on.
22207 if (!VT.is128BitVector())
22210 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22211 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22212 // consecutive, non-overlapping, and in the right order.
22213 SmallVector<SDValue, 16> Elts;
22214 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22215 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22217 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22221 if (isTargetShuffle(N->getOpcode())) {
22223 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22224 if (Shuffle.getNode())
22227 // Try recursively combining arbitrary sequences of x86 shuffle
22228 // instructions into higher-order shuffles. We do this after combining
22229 // specific PSHUF instruction sequences into their minimal form so that we
22230 // can evaluate how many specialized shuffle instructions are involved in
22231 // a particular chain.
22232 SmallVector<int, 1> NonceMask; // Just a placeholder.
22233 NonceMask.push_back(0);
22234 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22235 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22237 return SDValue(); // This routine will use CombineTo to replace N.
22243 /// PerformTruncateCombine - Converts truncate operation to
22244 /// a sequence of vector shuffle operations.
22245 /// It is possible when we truncate 256-bit vector to 128-bit vector
22246 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22247 TargetLowering::DAGCombinerInfo &DCI,
22248 const X86Subtarget *Subtarget) {
22252 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22253 /// specific shuffle of a load can be folded into a single element load.
22254 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22255 /// shuffles have been custom lowered so we need to handle those here.
22256 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22257 TargetLowering::DAGCombinerInfo &DCI) {
22258 if (DCI.isBeforeLegalizeOps())
22261 SDValue InVec = N->getOperand(0);
22262 SDValue EltNo = N->getOperand(1);
22264 if (!isa<ConstantSDNode>(EltNo))
22267 EVT OriginalVT = InVec.getValueType();
22269 if (InVec.getOpcode() == ISD::BITCAST) {
22270 // Don't duplicate a load with other uses.
22271 if (!InVec.hasOneUse())
22273 EVT BCVT = InVec.getOperand(0).getValueType();
22274 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22276 InVec = InVec.getOperand(0);
22279 EVT CurrentVT = InVec.getValueType();
22281 if (!isTargetShuffle(InVec.getOpcode()))
22284 // Don't duplicate a load with other uses.
22285 if (!InVec.hasOneUse())
22288 SmallVector<int, 16> ShuffleMask;
22290 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22291 ShuffleMask, UnaryShuffle))
22294 // Select the input vector, guarding against out of range extract vector.
22295 unsigned NumElems = CurrentVT.getVectorNumElements();
22296 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22297 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22298 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22299 : InVec.getOperand(1);
22301 // If inputs to shuffle are the same for both ops, then allow 2 uses
22302 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22304 if (LdNode.getOpcode() == ISD::BITCAST) {
22305 // Don't duplicate a load with other uses.
22306 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22309 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22310 LdNode = LdNode.getOperand(0);
22313 if (!ISD::isNormalLoad(LdNode.getNode()))
22316 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22318 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22321 EVT EltVT = N->getValueType(0);
22322 // If there's a bitcast before the shuffle, check if the load type and
22323 // alignment is valid.
22324 unsigned Align = LN0->getAlignment();
22325 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22326 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22327 EltVT.getTypeForEVT(*DAG.getContext()));
22329 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22332 // All checks match so transform back to vector_shuffle so that DAG combiner
22333 // can finish the job
22336 // Create shuffle node taking into account the case that its a unary shuffle
22337 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22338 : InVec.getOperand(1);
22339 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22340 InVec.getOperand(0), Shuffle,
22342 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22343 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22347 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22348 /// generation and convert it from being a bunch of shuffles and extracts
22349 /// to a simple store and scalar loads to extract the elements.
22350 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22351 TargetLowering::DAGCombinerInfo &DCI) {
22352 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22353 if (NewOp.getNode())
22356 SDValue InputVector = N->getOperand(0);
22358 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22359 // from mmx to v2i32 has a single usage.
22360 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22361 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22362 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22363 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22364 N->getValueType(0),
22365 InputVector.getNode()->getOperand(0));
22367 // Only operate on vectors of 4 elements, where the alternative shuffling
22368 // gets to be more expensive.
22369 if (InputVector.getValueType() != MVT::v4i32)
22372 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22373 // single use which is a sign-extend or zero-extend, and all elements are
22375 SmallVector<SDNode *, 4> Uses;
22376 unsigned ExtractedElements = 0;
22377 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22378 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22379 if (UI.getUse().getResNo() != InputVector.getResNo())
22382 SDNode *Extract = *UI;
22383 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22386 if (Extract->getValueType(0) != MVT::i32)
22388 if (!Extract->hasOneUse())
22390 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22391 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22393 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22396 // Record which element was extracted.
22397 ExtractedElements |=
22398 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22400 Uses.push_back(Extract);
22403 // If not all the elements were used, this may not be worthwhile.
22404 if (ExtractedElements != 15)
22407 // Ok, we've now decided to do the transformation.
22408 SDLoc dl(InputVector);
22410 // Store the value to a temporary stack slot.
22411 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22412 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22413 MachinePointerInfo(), false, false, 0);
22415 // Replace each use (extract) with a load of the appropriate element.
22416 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22417 UE = Uses.end(); UI != UE; ++UI) {
22418 SDNode *Extract = *UI;
22420 // cOMpute the element's address.
22421 SDValue Idx = Extract->getOperand(1);
22423 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22424 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22426 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22428 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22429 StackPtr, OffsetVal);
22431 // Load the scalar.
22432 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22433 ScalarAddr, MachinePointerInfo(),
22434 false, false, false, 0);
22436 // Replace the exact with the load.
22437 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22440 // The replacement was made in place; don't return anything.
22444 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22445 static std::pair<unsigned, bool>
22446 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22447 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22448 if (!VT.isVector())
22449 return std::make_pair(0, false);
22451 bool NeedSplit = false;
22452 switch (VT.getSimpleVT().SimpleTy) {
22453 default: return std::make_pair(0, false);
22457 if (!Subtarget->hasAVX2())
22459 if (!Subtarget->hasAVX())
22460 return std::make_pair(0, false);
22465 if (!Subtarget->hasSSE2())
22466 return std::make_pair(0, false);
22469 // SSE2 has only a small subset of the operations.
22470 bool hasUnsigned = Subtarget->hasSSE41() ||
22471 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22472 bool hasSigned = Subtarget->hasSSE41() ||
22473 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22475 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22478 // Check for x CC y ? x : y.
22479 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22480 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22485 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22488 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22491 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22494 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22496 // Check for x CC y ? y : x -- a min/max with reversed arms.
22497 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22498 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22503 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22506 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22509 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22512 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22516 return std::make_pair(Opc, NeedSplit);
22520 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22521 const X86Subtarget *Subtarget) {
22523 SDValue Cond = N->getOperand(0);
22524 SDValue LHS = N->getOperand(1);
22525 SDValue RHS = N->getOperand(2);
22527 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22528 SDValue CondSrc = Cond->getOperand(0);
22529 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22530 Cond = CondSrc->getOperand(0);
22533 MVT VT = N->getSimpleValueType(0);
22534 MVT EltVT = VT.getVectorElementType();
22535 unsigned NumElems = VT.getVectorNumElements();
22536 // There is no blend with immediate in AVX-512.
22537 if (VT.is512BitVector())
22540 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22542 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22545 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22548 // A vselect where all conditions and data are constants can be optimized into
22549 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22550 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22551 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22554 unsigned MaskValue = 0;
22555 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22558 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22559 for (unsigned i = 0; i < NumElems; ++i) {
22560 // Be sure we emit undef where we can.
22561 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22562 ShuffleMask[i] = -1;
22564 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22567 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22570 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22572 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22573 TargetLowering::DAGCombinerInfo &DCI,
22574 const X86Subtarget *Subtarget) {
22576 SDValue Cond = N->getOperand(0);
22577 // Get the LHS/RHS of the select.
22578 SDValue LHS = N->getOperand(1);
22579 SDValue RHS = N->getOperand(2);
22580 EVT VT = LHS.getValueType();
22581 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22583 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22584 // instructions match the semantics of the common C idiom x<y?x:y but not
22585 // x<=y?x:y, because of how they handle negative zero (which can be
22586 // ignored in unsafe-math mode).
22587 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22588 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22589 (Subtarget->hasSSE2() ||
22590 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22591 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22593 unsigned Opcode = 0;
22594 // Check for x CC y ? x : y.
22595 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22596 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22600 // Converting this to a min would handle NaNs incorrectly, and swapping
22601 // the operands would cause it to handle comparisons between positive
22602 // and negative zero incorrectly.
22603 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22604 if (!DAG.getTarget().Options.UnsafeFPMath &&
22605 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22607 std::swap(LHS, RHS);
22609 Opcode = X86ISD::FMIN;
22612 // Converting this to a min would handle comparisons between positive
22613 // and negative zero incorrectly.
22614 if (!DAG.getTarget().Options.UnsafeFPMath &&
22615 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22617 Opcode = X86ISD::FMIN;
22620 // Converting this to a min would handle both negative zeros and NaNs
22621 // incorrectly, but we can swap the operands to fix both.
22622 std::swap(LHS, RHS);
22626 Opcode = X86ISD::FMIN;
22630 // Converting this to a max would handle comparisons between positive
22631 // and negative zero incorrectly.
22632 if (!DAG.getTarget().Options.UnsafeFPMath &&
22633 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22635 Opcode = X86ISD::FMAX;
22638 // Converting this to a max would handle NaNs incorrectly, and swapping
22639 // the operands would cause it to handle comparisons between positive
22640 // and negative zero incorrectly.
22641 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22642 if (!DAG.getTarget().Options.UnsafeFPMath &&
22643 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22645 std::swap(LHS, RHS);
22647 Opcode = X86ISD::FMAX;
22650 // Converting this to a max would handle both negative zeros and NaNs
22651 // incorrectly, but we can swap the operands to fix both.
22652 std::swap(LHS, RHS);
22656 Opcode = X86ISD::FMAX;
22659 // Check for x CC y ? y : x -- a min/max with reversed arms.
22660 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22661 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22665 // Converting this to a min would handle comparisons between positive
22666 // and negative zero incorrectly, and swapping the operands would
22667 // cause it to handle NaNs incorrectly.
22668 if (!DAG.getTarget().Options.UnsafeFPMath &&
22669 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22670 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22672 std::swap(LHS, RHS);
22674 Opcode = X86ISD::FMIN;
22677 // Converting this to a min would handle NaNs incorrectly.
22678 if (!DAG.getTarget().Options.UnsafeFPMath &&
22679 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22681 Opcode = X86ISD::FMIN;
22684 // Converting this to a min would handle both negative zeros and NaNs
22685 // incorrectly, but we can swap the operands to fix both.
22686 std::swap(LHS, RHS);
22690 Opcode = X86ISD::FMIN;
22694 // Converting this to a max would handle NaNs incorrectly.
22695 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22697 Opcode = X86ISD::FMAX;
22700 // Converting this to a max would handle comparisons between positive
22701 // and negative zero incorrectly, and swapping the operands would
22702 // cause it to handle NaNs incorrectly.
22703 if (!DAG.getTarget().Options.UnsafeFPMath &&
22704 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22705 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22707 std::swap(LHS, RHS);
22709 Opcode = X86ISD::FMAX;
22712 // Converting this to a max would handle both negative zeros and NaNs
22713 // incorrectly, but we can swap the operands to fix both.
22714 std::swap(LHS, RHS);
22718 Opcode = X86ISD::FMAX;
22724 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22727 EVT CondVT = Cond.getValueType();
22728 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22729 CondVT.getVectorElementType() == MVT::i1) {
22730 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22731 // lowering on KNL. In this case we convert it to
22732 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22733 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22734 // Since SKX these selects have a proper lowering.
22735 EVT OpVT = LHS.getValueType();
22736 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22737 (OpVT.getVectorElementType() == MVT::i8 ||
22738 OpVT.getVectorElementType() == MVT::i16) &&
22739 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22740 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22741 DCI.AddToWorklist(Cond.getNode());
22742 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22745 // If this is a select between two integer constants, try to do some
22747 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22748 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22749 // Don't do this for crazy integer types.
22750 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22751 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22752 // so that TrueC (the true value) is larger than FalseC.
22753 bool NeedsCondInvert = false;
22755 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22756 // Efficiently invertible.
22757 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22758 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22759 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22760 NeedsCondInvert = true;
22761 std::swap(TrueC, FalseC);
22764 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22765 if (FalseC->getAPIntValue() == 0 &&
22766 TrueC->getAPIntValue().isPowerOf2()) {
22767 if (NeedsCondInvert) // Invert the condition if needed.
22768 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22769 DAG.getConstant(1, Cond.getValueType()));
22771 // Zero extend the condition if needed.
22772 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22774 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22775 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22776 DAG.getConstant(ShAmt, MVT::i8));
22779 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22780 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22781 if (NeedsCondInvert) // Invert the condition if needed.
22782 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22783 DAG.getConstant(1, Cond.getValueType()));
22785 // Zero extend the condition if needed.
22786 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22787 FalseC->getValueType(0), Cond);
22788 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22789 SDValue(FalseC, 0));
22792 // Optimize cases that will turn into an LEA instruction. This requires
22793 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22794 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22795 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22796 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22798 bool isFastMultiplier = false;
22800 switch ((unsigned char)Diff) {
22802 case 1: // result = add base, cond
22803 case 2: // result = lea base( , cond*2)
22804 case 3: // result = lea base(cond, cond*2)
22805 case 4: // result = lea base( , cond*4)
22806 case 5: // result = lea base(cond, cond*4)
22807 case 8: // result = lea base( , cond*8)
22808 case 9: // result = lea base(cond, cond*8)
22809 isFastMultiplier = true;
22814 if (isFastMultiplier) {
22815 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22816 if (NeedsCondInvert) // Invert the condition if needed.
22817 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22818 DAG.getConstant(1, Cond.getValueType()));
22820 // Zero extend the condition if needed.
22821 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22823 // Scale the condition by the difference.
22825 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22826 DAG.getConstant(Diff, Cond.getValueType()));
22828 // Add the base if non-zero.
22829 if (FalseC->getAPIntValue() != 0)
22830 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22831 SDValue(FalseC, 0));
22838 // Canonicalize max and min:
22839 // (x > y) ? x : y -> (x >= y) ? x : y
22840 // (x < y) ? x : y -> (x <= y) ? x : y
22841 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22842 // the need for an extra compare
22843 // against zero. e.g.
22844 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22846 // testl %edi, %edi
22848 // cmovgl %edi, %eax
22852 // cmovsl %eax, %edi
22853 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22854 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22855 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22856 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22861 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22862 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22863 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22864 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22869 // Early exit check
22870 if (!TLI.isTypeLegal(VT))
22873 // Match VSELECTs into subs with unsigned saturation.
22874 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22875 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22876 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22877 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22878 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22880 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22881 // left side invert the predicate to simplify logic below.
22883 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22885 CC = ISD::getSetCCInverse(CC, true);
22886 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22890 if (Other.getNode() && Other->getNumOperands() == 2 &&
22891 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22892 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22893 SDValue CondRHS = Cond->getOperand(1);
22895 // Look for a general sub with unsigned saturation first.
22896 // x >= y ? x-y : 0 --> subus x, y
22897 // x > y ? x-y : 0 --> subus x, y
22898 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22899 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22900 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22902 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22903 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22904 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22905 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22906 // If the RHS is a constant we have to reverse the const
22907 // canonicalization.
22908 // x > C-1 ? x+-C : 0 --> subus x, C
22909 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22910 CondRHSConst->getAPIntValue() ==
22911 (-OpRHSConst->getAPIntValue() - 1))
22912 return DAG.getNode(
22913 X86ISD::SUBUS, DL, VT, OpLHS,
22914 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22916 // Another special case: If C was a sign bit, the sub has been
22917 // canonicalized into a xor.
22918 // FIXME: Would it be better to use computeKnownBits to determine
22919 // whether it's safe to decanonicalize the xor?
22920 // x s< 0 ? x^C : 0 --> subus x, C
22921 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22922 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22923 OpRHSConst->getAPIntValue().isSignBit())
22924 // Note that we have to rebuild the RHS constant here to ensure we
22925 // don't rely on particular values of undef lanes.
22926 return DAG.getNode(
22927 X86ISD::SUBUS, DL, VT, OpLHS,
22928 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22933 // Try to match a min/max vector operation.
22934 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22935 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22936 unsigned Opc = ret.first;
22937 bool NeedSplit = ret.second;
22939 if (Opc && NeedSplit) {
22940 unsigned NumElems = VT.getVectorNumElements();
22941 // Extract the LHS vectors
22942 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22943 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22945 // Extract the RHS vectors
22946 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22947 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22949 // Create min/max for each subvector
22950 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22951 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22953 // Merge the result
22954 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22956 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22959 // Simplify vector selection if condition value type matches vselect
22961 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22962 assert(Cond.getValueType().isVector() &&
22963 "vector select expects a vector selector!");
22965 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22966 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22968 // Try invert the condition if true value is not all 1s and false value
22970 if (!TValIsAllOnes && !FValIsAllZeros &&
22971 // Check if the selector will be produced by CMPP*/PCMP*
22972 Cond.getOpcode() == ISD::SETCC &&
22973 // Check if SETCC has already been promoted
22974 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22975 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22976 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22978 if (TValIsAllZeros || FValIsAllOnes) {
22979 SDValue CC = Cond.getOperand(2);
22980 ISD::CondCode NewCC =
22981 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22982 Cond.getOperand(0).getValueType().isInteger());
22983 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22984 std::swap(LHS, RHS);
22985 TValIsAllOnes = FValIsAllOnes;
22986 FValIsAllZeros = TValIsAllZeros;
22990 if (TValIsAllOnes || FValIsAllZeros) {
22993 if (TValIsAllOnes && FValIsAllZeros)
22995 else if (TValIsAllOnes)
22996 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22997 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22998 else if (FValIsAllZeros)
22999 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23000 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23002 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23006 // Try to fold this VSELECT into a MOVSS/MOVSD
23007 if (N->getOpcode() == ISD::VSELECT &&
23008 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
23009 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
23010 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
23011 bool CanFold = false;
23012 unsigned NumElems = Cond.getNumOperands();
23016 if (isZero(Cond.getOperand(0))) {
23019 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
23020 // fold (vselect <0,-1> -> (movsd A, B)
23021 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23022 CanFold = isAllOnes(Cond.getOperand(i));
23023 } else if (isAllOnes(Cond.getOperand(0))) {
23027 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
23028 // fold (vselect <-1,0> -> (movsd B, A)
23029 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23030 CanFold = isZero(Cond.getOperand(i));
23034 if (VT == MVT::v4i32 || VT == MVT::v4f32)
23035 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
23036 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
23039 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
23040 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
23041 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
23042 // (v2i64 (bitcast B)))))
23044 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
23045 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
23046 // (v2f64 (bitcast B)))))
23048 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
23049 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
23050 // (v2i64 (bitcast A)))))
23052 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
23053 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
23054 // (v2f64 (bitcast A)))))
23056 CanFold = (isZero(Cond.getOperand(0)) &&
23057 isZero(Cond.getOperand(1)) &&
23058 isAllOnes(Cond.getOperand(2)) &&
23059 isAllOnes(Cond.getOperand(3)));
23061 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
23062 isAllOnes(Cond.getOperand(1)) &&
23063 isZero(Cond.getOperand(2)) &&
23064 isZero(Cond.getOperand(3))) {
23066 std::swap(LHS, RHS);
23070 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
23071 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
23072 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
23073 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
23075 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
23081 // If we know that this node is legal then we know that it is going to be
23082 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23083 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23084 // to simplify previous instructions.
23085 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23086 !DCI.isBeforeLegalize() &&
23087 // We explicitly check against v8i16 and v16i16 because, although
23088 // they're marked as Custom, they might only be legal when Cond is a
23089 // build_vector of constants. This will be taken care in a later
23091 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23092 VT != MVT::v8i16) &&
23093 // Don't optimize vector of constants. Those are handled by
23094 // the generic code and all the bits must be properly set for
23095 // the generic optimizer.
23096 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23097 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23099 // Don't optimize vector selects that map to mask-registers.
23103 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23104 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23106 APInt KnownZero, KnownOne;
23107 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23108 DCI.isBeforeLegalizeOps());
23109 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23110 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23112 // If we changed the computation somewhere in the DAG, this change
23113 // will affect all users of Cond.
23114 // Make sure it is fine and update all the nodes so that we do not
23115 // use the generic VSELECT anymore. Otherwise, we may perform
23116 // wrong optimizations as we messed up with the actual expectation
23117 // for the vector boolean values.
23118 if (Cond != TLO.Old) {
23119 // Check all uses of that condition operand to check whether it will be
23120 // consumed by non-BLEND instructions, which may depend on all bits are
23122 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23124 if (I->getOpcode() != ISD::VSELECT)
23125 // TODO: Add other opcodes eventually lowered into BLEND.
23128 // Update all the users of the condition, before committing the change,
23129 // so that the VSELECT optimizations that expect the correct vector
23130 // boolean value will not be triggered.
23131 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23133 DAG.ReplaceAllUsesOfValueWith(
23135 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23136 Cond, I->getOperand(1), I->getOperand(2)));
23137 DCI.CommitTargetLoweringOpt(TLO);
23140 // At this point, only Cond is changed. Change the condition
23141 // just for N to keep the opportunity to optimize all other
23142 // users their own way.
23143 DAG.ReplaceAllUsesOfValueWith(
23145 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23146 TLO.New, N->getOperand(1), N->getOperand(2)));
23151 // We should generate an X86ISD::BLENDI from a vselect if its argument
23152 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23153 // constants. This specific pattern gets generated when we split a
23154 // selector for a 512 bit vector in a machine without AVX512 (but with
23155 // 256-bit vectors), during legalization:
23157 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23159 // Iff we find this pattern and the build_vectors are built from
23160 // constants, we translate the vselect into a shuffle_vector that we
23161 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23162 if ((N->getOpcode() == ISD::VSELECT ||
23163 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23164 !DCI.isBeforeLegalize()) {
23165 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23166 if (Shuffle.getNode())
23173 // Check whether a boolean test is testing a boolean value generated by
23174 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23177 // Simplify the following patterns:
23178 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23179 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23180 // to (Op EFLAGS Cond)
23182 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23183 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23184 // to (Op EFLAGS !Cond)
23186 // where Op could be BRCOND or CMOV.
23188 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23189 // Quit if not CMP and SUB with its value result used.
23190 if (Cmp.getOpcode() != X86ISD::CMP &&
23191 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23194 // Quit if not used as a boolean value.
23195 if (CC != X86::COND_E && CC != X86::COND_NE)
23198 // Check CMP operands. One of them should be 0 or 1 and the other should be
23199 // an SetCC or extended from it.
23200 SDValue Op1 = Cmp.getOperand(0);
23201 SDValue Op2 = Cmp.getOperand(1);
23204 const ConstantSDNode* C = nullptr;
23205 bool needOppositeCond = (CC == X86::COND_E);
23206 bool checkAgainstTrue = false; // Is it a comparison against 1?
23208 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23210 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23212 else // Quit if all operands are not constants.
23215 if (C->getZExtValue() == 1) {
23216 needOppositeCond = !needOppositeCond;
23217 checkAgainstTrue = true;
23218 } else if (C->getZExtValue() != 0)
23219 // Quit if the constant is neither 0 or 1.
23222 bool truncatedToBoolWithAnd = false;
23223 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23224 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23225 SetCC.getOpcode() == ISD::TRUNCATE ||
23226 SetCC.getOpcode() == ISD::AND) {
23227 if (SetCC.getOpcode() == ISD::AND) {
23229 ConstantSDNode *CS;
23230 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23231 CS->getZExtValue() == 1)
23233 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23234 CS->getZExtValue() == 1)
23238 SetCC = SetCC.getOperand(OpIdx);
23239 truncatedToBoolWithAnd = true;
23241 SetCC = SetCC.getOperand(0);
23244 switch (SetCC.getOpcode()) {
23245 case X86ISD::SETCC_CARRY:
23246 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23247 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23248 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23249 // truncated to i1 using 'and'.
23250 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23252 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23253 "Invalid use of SETCC_CARRY!");
23255 case X86ISD::SETCC:
23256 // Set the condition code or opposite one if necessary.
23257 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23258 if (needOppositeCond)
23259 CC = X86::GetOppositeBranchCondition(CC);
23260 return SetCC.getOperand(1);
23261 case X86ISD::CMOV: {
23262 // Check whether false/true value has canonical one, i.e. 0 or 1.
23263 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23264 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23265 // Quit if true value is not a constant.
23268 // Quit if false value is not a constant.
23270 SDValue Op = SetCC.getOperand(0);
23271 // Skip 'zext' or 'trunc' node.
23272 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23273 Op.getOpcode() == ISD::TRUNCATE)
23274 Op = Op.getOperand(0);
23275 // A special case for rdrand/rdseed, where 0 is set if false cond is
23277 if ((Op.getOpcode() != X86ISD::RDRAND &&
23278 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23281 // Quit if false value is not the constant 0 or 1.
23282 bool FValIsFalse = true;
23283 if (FVal && FVal->getZExtValue() != 0) {
23284 if (FVal->getZExtValue() != 1)
23286 // If FVal is 1, opposite cond is needed.
23287 needOppositeCond = !needOppositeCond;
23288 FValIsFalse = false;
23290 // Quit if TVal is not the constant opposite of FVal.
23291 if (FValIsFalse && TVal->getZExtValue() != 1)
23293 if (!FValIsFalse && TVal->getZExtValue() != 0)
23295 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23296 if (needOppositeCond)
23297 CC = X86::GetOppositeBranchCondition(CC);
23298 return SetCC.getOperand(3);
23305 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23306 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23307 TargetLowering::DAGCombinerInfo &DCI,
23308 const X86Subtarget *Subtarget) {
23311 // If the flag operand isn't dead, don't touch this CMOV.
23312 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23315 SDValue FalseOp = N->getOperand(0);
23316 SDValue TrueOp = N->getOperand(1);
23317 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23318 SDValue Cond = N->getOperand(3);
23320 if (CC == X86::COND_E || CC == X86::COND_NE) {
23321 switch (Cond.getOpcode()) {
23325 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23326 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23327 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23333 Flags = checkBoolTestSetCCCombine(Cond, CC);
23334 if (Flags.getNode() &&
23335 // Extra check as FCMOV only supports a subset of X86 cond.
23336 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23337 SDValue Ops[] = { FalseOp, TrueOp,
23338 DAG.getConstant(CC, MVT::i8), Flags };
23339 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23342 // If this is a select between two integer constants, try to do some
23343 // optimizations. Note that the operands are ordered the opposite of SELECT
23345 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23346 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23347 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23348 // larger than FalseC (the false value).
23349 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23350 CC = X86::GetOppositeBranchCondition(CC);
23351 std::swap(TrueC, FalseC);
23352 std::swap(TrueOp, FalseOp);
23355 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23356 // This is efficient for any integer data type (including i8/i16) and
23358 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23359 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23360 DAG.getConstant(CC, MVT::i8), Cond);
23362 // Zero extend the condition if needed.
23363 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23365 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23366 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23367 DAG.getConstant(ShAmt, MVT::i8));
23368 if (N->getNumValues() == 2) // Dead flag value?
23369 return DCI.CombineTo(N, Cond, SDValue());
23373 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23374 // for any integer data type, including i8/i16.
23375 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23376 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23377 DAG.getConstant(CC, MVT::i8), Cond);
23379 // Zero extend the condition if needed.
23380 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23381 FalseC->getValueType(0), Cond);
23382 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23383 SDValue(FalseC, 0));
23385 if (N->getNumValues() == 2) // Dead flag value?
23386 return DCI.CombineTo(N, Cond, SDValue());
23390 // Optimize cases that will turn into an LEA instruction. This requires
23391 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23392 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23393 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23394 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23396 bool isFastMultiplier = false;
23398 switch ((unsigned char)Diff) {
23400 case 1: // result = add base, cond
23401 case 2: // result = lea base( , cond*2)
23402 case 3: // result = lea base(cond, cond*2)
23403 case 4: // result = lea base( , cond*4)
23404 case 5: // result = lea base(cond, cond*4)
23405 case 8: // result = lea base( , cond*8)
23406 case 9: // result = lea base(cond, cond*8)
23407 isFastMultiplier = true;
23412 if (isFastMultiplier) {
23413 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23414 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23415 DAG.getConstant(CC, MVT::i8), Cond);
23416 // Zero extend the condition if needed.
23417 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23419 // Scale the condition by the difference.
23421 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23422 DAG.getConstant(Diff, Cond.getValueType()));
23424 // Add the base if non-zero.
23425 if (FalseC->getAPIntValue() != 0)
23426 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23427 SDValue(FalseC, 0));
23428 if (N->getNumValues() == 2) // Dead flag value?
23429 return DCI.CombineTo(N, Cond, SDValue());
23436 // Handle these cases:
23437 // (select (x != c), e, c) -> select (x != c), e, x),
23438 // (select (x == c), c, e) -> select (x == c), x, e)
23439 // where the c is an integer constant, and the "select" is the combination
23440 // of CMOV and CMP.
23442 // The rationale for this change is that the conditional-move from a constant
23443 // needs two instructions, however, conditional-move from a register needs
23444 // only one instruction.
23446 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23447 // some instruction-combining opportunities. This opt needs to be
23448 // postponed as late as possible.
23450 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23451 // the DCI.xxxx conditions are provided to postpone the optimization as
23452 // late as possible.
23454 ConstantSDNode *CmpAgainst = nullptr;
23455 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23456 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23457 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23459 if (CC == X86::COND_NE &&
23460 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23461 CC = X86::GetOppositeBranchCondition(CC);
23462 std::swap(TrueOp, FalseOp);
23465 if (CC == X86::COND_E &&
23466 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23467 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23468 DAG.getConstant(CC, MVT::i8), Cond };
23469 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23477 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23478 const X86Subtarget *Subtarget) {
23479 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23481 default: return SDValue();
23482 // SSE/AVX/AVX2 blend intrinsics.
23483 case Intrinsic::x86_avx2_pblendvb:
23484 case Intrinsic::x86_avx2_pblendw:
23485 case Intrinsic::x86_avx2_pblendd_128:
23486 case Intrinsic::x86_avx2_pblendd_256:
23487 // Don't try to simplify this intrinsic if we don't have AVX2.
23488 if (!Subtarget->hasAVX2())
23491 case Intrinsic::x86_avx_blend_pd_256:
23492 case Intrinsic::x86_avx_blend_ps_256:
23493 case Intrinsic::x86_avx_blendv_pd_256:
23494 case Intrinsic::x86_avx_blendv_ps_256:
23495 // Don't try to simplify this intrinsic if we don't have AVX.
23496 if (!Subtarget->hasAVX())
23499 case Intrinsic::x86_sse41_pblendw:
23500 case Intrinsic::x86_sse41_blendpd:
23501 case Intrinsic::x86_sse41_blendps:
23502 case Intrinsic::x86_sse41_blendvps:
23503 case Intrinsic::x86_sse41_blendvpd:
23504 case Intrinsic::x86_sse41_pblendvb: {
23505 SDValue Op0 = N->getOperand(1);
23506 SDValue Op1 = N->getOperand(2);
23507 SDValue Mask = N->getOperand(3);
23509 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23510 if (!Subtarget->hasSSE41())
23513 // fold (blend A, A, Mask) -> A
23516 // fold (blend A, B, allZeros) -> A
23517 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23519 // fold (blend A, B, allOnes) -> B
23520 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23523 // Simplify the case where the mask is a constant i32 value.
23524 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23525 if (C->isNullValue())
23527 if (C->isAllOnesValue())
23534 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23535 case Intrinsic::x86_sse2_psrai_w:
23536 case Intrinsic::x86_sse2_psrai_d:
23537 case Intrinsic::x86_avx2_psrai_w:
23538 case Intrinsic::x86_avx2_psrai_d:
23539 case Intrinsic::x86_sse2_psra_w:
23540 case Intrinsic::x86_sse2_psra_d:
23541 case Intrinsic::x86_avx2_psra_w:
23542 case Intrinsic::x86_avx2_psra_d: {
23543 SDValue Op0 = N->getOperand(1);
23544 SDValue Op1 = N->getOperand(2);
23545 EVT VT = Op0.getValueType();
23546 assert(VT.isVector() && "Expected a vector type!");
23548 if (isa<BuildVectorSDNode>(Op1))
23549 Op1 = Op1.getOperand(0);
23551 if (!isa<ConstantSDNode>(Op1))
23554 EVT SVT = VT.getVectorElementType();
23555 unsigned SVTBits = SVT.getSizeInBits();
23557 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23558 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23559 uint64_t ShAmt = C.getZExtValue();
23561 // Don't try to convert this shift into a ISD::SRA if the shift
23562 // count is bigger than or equal to the element size.
23563 if (ShAmt >= SVTBits)
23566 // Trivial case: if the shift count is zero, then fold this
23567 // into the first operand.
23571 // Replace this packed shift intrinsic with a target independent
23573 SDValue Splat = DAG.getConstant(C, VT);
23574 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23579 /// PerformMulCombine - Optimize a single multiply with constant into two
23580 /// in order to implement it with two cheaper instructions, e.g.
23581 /// LEA + SHL, LEA + LEA.
23582 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23583 TargetLowering::DAGCombinerInfo &DCI) {
23584 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23587 EVT VT = N->getValueType(0);
23588 if (VT != MVT::i64)
23591 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23594 uint64_t MulAmt = C->getZExtValue();
23595 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23598 uint64_t MulAmt1 = 0;
23599 uint64_t MulAmt2 = 0;
23600 if ((MulAmt % 9) == 0) {
23602 MulAmt2 = MulAmt / 9;
23603 } else if ((MulAmt % 5) == 0) {
23605 MulAmt2 = MulAmt / 5;
23606 } else if ((MulAmt % 3) == 0) {
23608 MulAmt2 = MulAmt / 3;
23611 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23614 if (isPowerOf2_64(MulAmt2) &&
23615 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23616 // If second multiplifer is pow2, issue it first. We want the multiply by
23617 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23619 std::swap(MulAmt1, MulAmt2);
23622 if (isPowerOf2_64(MulAmt1))
23623 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23624 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23626 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23627 DAG.getConstant(MulAmt1, VT));
23629 if (isPowerOf2_64(MulAmt2))
23630 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23631 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23633 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23634 DAG.getConstant(MulAmt2, VT));
23636 // Do not add new nodes to DAG combiner worklist.
23637 DCI.CombineTo(N, NewMul, false);
23642 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23643 SDValue N0 = N->getOperand(0);
23644 SDValue N1 = N->getOperand(1);
23645 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23646 EVT VT = N0.getValueType();
23648 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23649 // since the result of setcc_c is all zero's or all ones.
23650 if (VT.isInteger() && !VT.isVector() &&
23651 N1C && N0.getOpcode() == ISD::AND &&
23652 N0.getOperand(1).getOpcode() == ISD::Constant) {
23653 SDValue N00 = N0.getOperand(0);
23654 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23655 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23656 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23657 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23658 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23659 APInt ShAmt = N1C->getAPIntValue();
23660 Mask = Mask.shl(ShAmt);
23662 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23663 N00, DAG.getConstant(Mask, VT));
23667 // Hardware support for vector shifts is sparse which makes us scalarize the
23668 // vector operations in many cases. Also, on sandybridge ADD is faster than
23670 // (shl V, 1) -> add V,V
23671 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23672 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23673 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23674 // We shift all of the values by one. In many cases we do not have
23675 // hardware support for this operation. This is better expressed as an ADD
23677 if (N1SplatC->getZExtValue() == 1)
23678 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23684 /// \brief Returns a vector of 0s if the node in input is a vector logical
23685 /// shift by a constant amount which is known to be bigger than or equal
23686 /// to the vector element size in bits.
23687 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23688 const X86Subtarget *Subtarget) {
23689 EVT VT = N->getValueType(0);
23691 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23692 (!Subtarget->hasInt256() ||
23693 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23696 SDValue Amt = N->getOperand(1);
23698 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23699 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23700 APInt ShiftAmt = AmtSplat->getAPIntValue();
23701 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23703 // SSE2/AVX2 logical shifts always return a vector of 0s
23704 // if the shift amount is bigger than or equal to
23705 // the element size. The constant shift amount will be
23706 // encoded as a 8-bit immediate.
23707 if (ShiftAmt.trunc(8).uge(MaxAmount))
23708 return getZeroVector(VT, Subtarget, DAG, DL);
23714 /// PerformShiftCombine - Combine shifts.
23715 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23716 TargetLowering::DAGCombinerInfo &DCI,
23717 const X86Subtarget *Subtarget) {
23718 if (N->getOpcode() == ISD::SHL) {
23719 SDValue V = PerformSHLCombine(N, DAG);
23720 if (V.getNode()) return V;
23723 if (N->getOpcode() != ISD::SRA) {
23724 // Try to fold this logical shift into a zero vector.
23725 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23726 if (V.getNode()) return V;
23732 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23733 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23734 // and friends. Likewise for OR -> CMPNEQSS.
23735 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23736 TargetLowering::DAGCombinerInfo &DCI,
23737 const X86Subtarget *Subtarget) {
23740 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23741 // we're requiring SSE2 for both.
23742 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23743 SDValue N0 = N->getOperand(0);
23744 SDValue N1 = N->getOperand(1);
23745 SDValue CMP0 = N0->getOperand(1);
23746 SDValue CMP1 = N1->getOperand(1);
23749 // The SETCCs should both refer to the same CMP.
23750 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23753 SDValue CMP00 = CMP0->getOperand(0);
23754 SDValue CMP01 = CMP0->getOperand(1);
23755 EVT VT = CMP00.getValueType();
23757 if (VT == MVT::f32 || VT == MVT::f64) {
23758 bool ExpectingFlags = false;
23759 // Check for any users that want flags:
23760 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23761 !ExpectingFlags && UI != UE; ++UI)
23762 switch (UI->getOpcode()) {
23767 ExpectingFlags = true;
23769 case ISD::CopyToReg:
23770 case ISD::SIGN_EXTEND:
23771 case ISD::ZERO_EXTEND:
23772 case ISD::ANY_EXTEND:
23776 if (!ExpectingFlags) {
23777 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23778 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23780 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23781 X86::CondCode tmp = cc0;
23786 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23787 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23788 // FIXME: need symbolic constants for these magic numbers.
23789 // See X86ATTInstPrinter.cpp:printSSECC().
23790 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23791 if (Subtarget->hasAVX512()) {
23792 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23793 CMP01, DAG.getConstant(x86cc, MVT::i8));
23794 if (N->getValueType(0) != MVT::i1)
23795 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23799 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23800 CMP00.getValueType(), CMP00, CMP01,
23801 DAG.getConstant(x86cc, MVT::i8));
23803 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23804 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23806 if (is64BitFP && !Subtarget->is64Bit()) {
23807 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23808 // 64-bit integer, since that's not a legal type. Since
23809 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23810 // bits, but can do this little dance to extract the lowest 32 bits
23811 // and work with those going forward.
23812 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23814 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23816 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23817 Vector32, DAG.getIntPtrConstant(0));
23821 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23822 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23823 DAG.getConstant(1, IntVT));
23824 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23825 return OneBitOfTruth;
23833 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23834 /// so it can be folded inside ANDNP.
23835 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23836 EVT VT = N->getValueType(0);
23838 // Match direct AllOnes for 128 and 256-bit vectors
23839 if (ISD::isBuildVectorAllOnes(N))
23842 // Look through a bit convert.
23843 if (N->getOpcode() == ISD::BITCAST)
23844 N = N->getOperand(0).getNode();
23846 // Sometimes the operand may come from a insert_subvector building a 256-bit
23848 if (VT.is256BitVector() &&
23849 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23850 SDValue V1 = N->getOperand(0);
23851 SDValue V2 = N->getOperand(1);
23853 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23854 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23855 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23856 ISD::isBuildVectorAllOnes(V2.getNode()))
23863 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23864 // register. In most cases we actually compare or select YMM-sized registers
23865 // and mixing the two types creates horrible code. This method optimizes
23866 // some of the transition sequences.
23867 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23868 TargetLowering::DAGCombinerInfo &DCI,
23869 const X86Subtarget *Subtarget) {
23870 EVT VT = N->getValueType(0);
23871 if (!VT.is256BitVector())
23874 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23875 N->getOpcode() == ISD::ZERO_EXTEND ||
23876 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23878 SDValue Narrow = N->getOperand(0);
23879 EVT NarrowVT = Narrow->getValueType(0);
23880 if (!NarrowVT.is128BitVector())
23883 if (Narrow->getOpcode() != ISD::XOR &&
23884 Narrow->getOpcode() != ISD::AND &&
23885 Narrow->getOpcode() != ISD::OR)
23888 SDValue N0 = Narrow->getOperand(0);
23889 SDValue N1 = Narrow->getOperand(1);
23892 // The Left side has to be a trunc.
23893 if (N0.getOpcode() != ISD::TRUNCATE)
23896 // The type of the truncated inputs.
23897 EVT WideVT = N0->getOperand(0)->getValueType(0);
23901 // The right side has to be a 'trunc' or a constant vector.
23902 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23903 ConstantSDNode *RHSConstSplat = nullptr;
23904 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23905 RHSConstSplat = RHSBV->getConstantSplatNode();
23906 if (!RHSTrunc && !RHSConstSplat)
23909 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23911 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23914 // Set N0 and N1 to hold the inputs to the new wide operation.
23915 N0 = N0->getOperand(0);
23916 if (RHSConstSplat) {
23917 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23918 SDValue(RHSConstSplat, 0));
23919 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23920 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23921 } else if (RHSTrunc) {
23922 N1 = N1->getOperand(0);
23925 // Generate the wide operation.
23926 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23927 unsigned Opcode = N->getOpcode();
23929 case ISD::ANY_EXTEND:
23931 case ISD::ZERO_EXTEND: {
23932 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23933 APInt Mask = APInt::getAllOnesValue(InBits);
23934 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23935 return DAG.getNode(ISD::AND, DL, VT,
23936 Op, DAG.getConstant(Mask, VT));
23938 case ISD::SIGN_EXTEND:
23939 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23940 Op, DAG.getValueType(NarrowVT));
23942 llvm_unreachable("Unexpected opcode");
23946 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23947 TargetLowering::DAGCombinerInfo &DCI,
23948 const X86Subtarget *Subtarget) {
23949 EVT VT = N->getValueType(0);
23950 if (DCI.isBeforeLegalizeOps())
23953 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23957 // Create BEXTR instructions
23958 // BEXTR is ((X >> imm) & (2**size-1))
23959 if (VT == MVT::i32 || VT == MVT::i64) {
23960 SDValue N0 = N->getOperand(0);
23961 SDValue N1 = N->getOperand(1);
23964 // Check for BEXTR.
23965 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23966 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23967 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23968 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23969 if (MaskNode && ShiftNode) {
23970 uint64_t Mask = MaskNode->getZExtValue();
23971 uint64_t Shift = ShiftNode->getZExtValue();
23972 if (isMask_64(Mask)) {
23973 uint64_t MaskSize = CountPopulation_64(Mask);
23974 if (Shift + MaskSize <= VT.getSizeInBits())
23975 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23976 DAG.getConstant(Shift | (MaskSize << 8), VT));
23984 // Want to form ANDNP nodes:
23985 // 1) In the hopes of then easily combining them with OR and AND nodes
23986 // to form PBLEND/PSIGN.
23987 // 2) To match ANDN packed intrinsics
23988 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23991 SDValue N0 = N->getOperand(0);
23992 SDValue N1 = N->getOperand(1);
23995 // Check LHS for vnot
23996 if (N0.getOpcode() == ISD::XOR &&
23997 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23998 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23999 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24001 // Check RHS for vnot
24002 if (N1.getOpcode() == ISD::XOR &&
24003 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24004 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24005 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24010 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24011 TargetLowering::DAGCombinerInfo &DCI,
24012 const X86Subtarget *Subtarget) {
24013 if (DCI.isBeforeLegalizeOps())
24016 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24020 SDValue N0 = N->getOperand(0);
24021 SDValue N1 = N->getOperand(1);
24022 EVT VT = N->getValueType(0);
24024 // look for psign/blend
24025 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24026 if (!Subtarget->hasSSSE3() ||
24027 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24030 // Canonicalize pandn to RHS
24031 if (N0.getOpcode() == X86ISD::ANDNP)
24033 // or (and (m, y), (pandn m, x))
24034 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24035 SDValue Mask = N1.getOperand(0);
24036 SDValue X = N1.getOperand(1);
24038 if (N0.getOperand(0) == Mask)
24039 Y = N0.getOperand(1);
24040 if (N0.getOperand(1) == Mask)
24041 Y = N0.getOperand(0);
24043 // Check to see if the mask appeared in both the AND and ANDNP and
24047 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24048 // Look through mask bitcast.
24049 if (Mask.getOpcode() == ISD::BITCAST)
24050 Mask = Mask.getOperand(0);
24051 if (X.getOpcode() == ISD::BITCAST)
24052 X = X.getOperand(0);
24053 if (Y.getOpcode() == ISD::BITCAST)
24054 Y = Y.getOperand(0);
24056 EVT MaskVT = Mask.getValueType();
24058 // Validate that the Mask operand is a vector sra node.
24059 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24060 // there is no psrai.b
24061 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24062 unsigned SraAmt = ~0;
24063 if (Mask.getOpcode() == ISD::SRA) {
24064 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24065 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24066 SraAmt = AmtConst->getZExtValue();
24067 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24068 SDValue SraC = Mask.getOperand(1);
24069 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24071 if ((SraAmt + 1) != EltBits)
24076 // Now we know we at least have a plendvb with the mask val. See if
24077 // we can form a psignb/w/d.
24078 // psign = x.type == y.type == mask.type && y = sub(0, x);
24079 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24080 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24081 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24082 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24083 "Unsupported VT for PSIGN");
24084 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24085 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24087 // PBLENDVB only available on SSE 4.1
24088 if (!Subtarget->hasSSE41())
24091 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24093 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24094 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24095 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24096 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24097 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24101 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24104 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24105 MachineFunction &MF = DAG.getMachineFunction();
24106 bool OptForSize = MF.getFunction()->getAttributes().
24107 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24109 // SHLD/SHRD instructions have lower register pressure, but on some
24110 // platforms they have higher latency than the equivalent
24111 // series of shifts/or that would otherwise be generated.
24112 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24113 // have higher latencies and we are not optimizing for size.
24114 if (!OptForSize && Subtarget->isSHLDSlow())
24117 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24119 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24121 if (!N0.hasOneUse() || !N1.hasOneUse())
24124 SDValue ShAmt0 = N0.getOperand(1);
24125 if (ShAmt0.getValueType() != MVT::i8)
24127 SDValue ShAmt1 = N1.getOperand(1);
24128 if (ShAmt1.getValueType() != MVT::i8)
24130 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24131 ShAmt0 = ShAmt0.getOperand(0);
24132 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24133 ShAmt1 = ShAmt1.getOperand(0);
24136 unsigned Opc = X86ISD::SHLD;
24137 SDValue Op0 = N0.getOperand(0);
24138 SDValue Op1 = N1.getOperand(0);
24139 if (ShAmt0.getOpcode() == ISD::SUB) {
24140 Opc = X86ISD::SHRD;
24141 std::swap(Op0, Op1);
24142 std::swap(ShAmt0, ShAmt1);
24145 unsigned Bits = VT.getSizeInBits();
24146 if (ShAmt1.getOpcode() == ISD::SUB) {
24147 SDValue Sum = ShAmt1.getOperand(0);
24148 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24149 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24150 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24151 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24152 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24153 return DAG.getNode(Opc, DL, VT,
24155 DAG.getNode(ISD::TRUNCATE, DL,
24158 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24159 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24161 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24162 return DAG.getNode(Opc, DL, VT,
24163 N0.getOperand(0), N1.getOperand(0),
24164 DAG.getNode(ISD::TRUNCATE, DL,
24171 // Generate NEG and CMOV for integer abs.
24172 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24173 EVT VT = N->getValueType(0);
24175 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24176 // 8-bit integer abs to NEG and CMOV.
24177 if (VT.isInteger() && VT.getSizeInBits() == 8)
24180 SDValue N0 = N->getOperand(0);
24181 SDValue N1 = N->getOperand(1);
24184 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24185 // and change it to SUB and CMOV.
24186 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24187 N0.getOpcode() == ISD::ADD &&
24188 N0.getOperand(1) == N1 &&
24189 N1.getOpcode() == ISD::SRA &&
24190 N1.getOperand(0) == N0.getOperand(0))
24191 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24192 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24193 // Generate SUB & CMOV.
24194 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24195 DAG.getConstant(0, VT), N0.getOperand(0));
24197 SDValue Ops[] = { N0.getOperand(0), Neg,
24198 DAG.getConstant(X86::COND_GE, MVT::i8),
24199 SDValue(Neg.getNode(), 1) };
24200 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24205 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24206 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24207 TargetLowering::DAGCombinerInfo &DCI,
24208 const X86Subtarget *Subtarget) {
24209 if (DCI.isBeforeLegalizeOps())
24212 if (Subtarget->hasCMov()) {
24213 SDValue RV = performIntegerAbsCombine(N, DAG);
24221 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24222 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24223 TargetLowering::DAGCombinerInfo &DCI,
24224 const X86Subtarget *Subtarget) {
24225 LoadSDNode *Ld = cast<LoadSDNode>(N);
24226 EVT RegVT = Ld->getValueType(0);
24227 EVT MemVT = Ld->getMemoryVT();
24229 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24231 // On Sandybridge unaligned 256bit loads are inefficient.
24232 ISD::LoadExtType Ext = Ld->getExtensionType();
24233 unsigned Alignment = Ld->getAlignment();
24234 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24235 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
24236 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24237 unsigned NumElems = RegVT.getVectorNumElements();
24241 SDValue Ptr = Ld->getBasePtr();
24242 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24244 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24246 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24247 Ld->getPointerInfo(), Ld->isVolatile(),
24248 Ld->isNonTemporal(), Ld->isInvariant(),
24250 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24251 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24252 Ld->getPointerInfo(), Ld->isVolatile(),
24253 Ld->isNonTemporal(), Ld->isInvariant(),
24254 std::min(16U, Alignment));
24255 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24257 Load2.getValue(1));
24259 SDValue NewVec = DAG.getUNDEF(RegVT);
24260 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24261 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24262 return DCI.CombineTo(N, NewVec, TF, true);
24268 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24269 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24270 const X86Subtarget *Subtarget) {
24271 StoreSDNode *St = cast<StoreSDNode>(N);
24272 EVT VT = St->getValue().getValueType();
24273 EVT StVT = St->getMemoryVT();
24275 SDValue StoredVal = St->getOperand(1);
24276 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24278 // If we are saving a concatenation of two XMM registers, perform two stores.
24279 // On Sandy Bridge, 256-bit memory operations are executed by two
24280 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
24281 // memory operation.
24282 unsigned Alignment = St->getAlignment();
24283 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24284 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
24285 StVT == VT && !IsAligned) {
24286 unsigned NumElems = VT.getVectorNumElements();
24290 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24291 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24293 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24294 SDValue Ptr0 = St->getBasePtr();
24295 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24297 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24298 St->getPointerInfo(), St->isVolatile(),
24299 St->isNonTemporal(), Alignment);
24300 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24301 St->getPointerInfo(), St->isVolatile(),
24302 St->isNonTemporal(),
24303 std::min(16U, Alignment));
24304 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24307 // Optimize trunc store (of multiple scalars) to shuffle and store.
24308 // First, pack all of the elements in one place. Next, store to memory
24309 // in fewer chunks.
24310 if (St->isTruncatingStore() && VT.isVector()) {
24311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24312 unsigned NumElems = VT.getVectorNumElements();
24313 assert(StVT != VT && "Cannot truncate to the same type");
24314 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24315 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24317 // From, To sizes and ElemCount must be pow of two
24318 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24319 // We are going to use the original vector elt for storing.
24320 // Accumulated smaller vector elements must be a multiple of the store size.
24321 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24323 unsigned SizeRatio = FromSz / ToSz;
24325 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24327 // Create a type on which we perform the shuffle
24328 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24329 StVT.getScalarType(), NumElems*SizeRatio);
24331 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24333 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24334 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24335 for (unsigned i = 0; i != NumElems; ++i)
24336 ShuffleVec[i] = i * SizeRatio;
24338 // Can't shuffle using an illegal type.
24339 if (!TLI.isTypeLegal(WideVecVT))
24342 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24343 DAG.getUNDEF(WideVecVT),
24345 // At this point all of the data is stored at the bottom of the
24346 // register. We now need to save it to mem.
24348 // Find the largest store unit
24349 MVT StoreType = MVT::i8;
24350 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24351 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24352 MVT Tp = (MVT::SimpleValueType)tp;
24353 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24357 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24358 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24359 (64 <= NumElems * ToSz))
24360 StoreType = MVT::f64;
24362 // Bitcast the original vector into a vector of store-size units
24363 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24364 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24365 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24366 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24367 SmallVector<SDValue, 8> Chains;
24368 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24369 TLI.getPointerTy());
24370 SDValue Ptr = St->getBasePtr();
24372 // Perform one or more big stores into memory.
24373 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24374 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24375 StoreType, ShuffWide,
24376 DAG.getIntPtrConstant(i));
24377 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24378 St->getPointerInfo(), St->isVolatile(),
24379 St->isNonTemporal(), St->getAlignment());
24380 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24381 Chains.push_back(Ch);
24384 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24387 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24388 // the FP state in cases where an emms may be missing.
24389 // A preferable solution to the general problem is to figure out the right
24390 // places to insert EMMS. This qualifies as a quick hack.
24392 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24393 if (VT.getSizeInBits() != 64)
24396 const Function *F = DAG.getMachineFunction().getFunction();
24397 bool NoImplicitFloatOps = F->getAttributes().
24398 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24399 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24400 && Subtarget->hasSSE2();
24401 if ((VT.isVector() ||
24402 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24403 isa<LoadSDNode>(St->getValue()) &&
24404 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24405 St->getChain().hasOneUse() && !St->isVolatile()) {
24406 SDNode* LdVal = St->getValue().getNode();
24407 LoadSDNode *Ld = nullptr;
24408 int TokenFactorIndex = -1;
24409 SmallVector<SDValue, 8> Ops;
24410 SDNode* ChainVal = St->getChain().getNode();
24411 // Must be a store of a load. We currently handle two cases: the load
24412 // is a direct child, and it's under an intervening TokenFactor. It is
24413 // possible to dig deeper under nested TokenFactors.
24414 if (ChainVal == LdVal)
24415 Ld = cast<LoadSDNode>(St->getChain());
24416 else if (St->getValue().hasOneUse() &&
24417 ChainVal->getOpcode() == ISD::TokenFactor) {
24418 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24419 if (ChainVal->getOperand(i).getNode() == LdVal) {
24420 TokenFactorIndex = i;
24421 Ld = cast<LoadSDNode>(St->getValue());
24423 Ops.push_back(ChainVal->getOperand(i));
24427 if (!Ld || !ISD::isNormalLoad(Ld))
24430 // If this is not the MMX case, i.e. we are just turning i64 load/store
24431 // into f64 load/store, avoid the transformation if there are multiple
24432 // uses of the loaded value.
24433 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24438 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24439 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24441 if (Subtarget->is64Bit() || F64IsLegal) {
24442 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24443 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24444 Ld->getPointerInfo(), Ld->isVolatile(),
24445 Ld->isNonTemporal(), Ld->isInvariant(),
24446 Ld->getAlignment());
24447 SDValue NewChain = NewLd.getValue(1);
24448 if (TokenFactorIndex != -1) {
24449 Ops.push_back(NewChain);
24450 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24452 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24453 St->getPointerInfo(),
24454 St->isVolatile(), St->isNonTemporal(),
24455 St->getAlignment());
24458 // Otherwise, lower to two pairs of 32-bit loads / stores.
24459 SDValue LoAddr = Ld->getBasePtr();
24460 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24461 DAG.getConstant(4, MVT::i32));
24463 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24464 Ld->getPointerInfo(),
24465 Ld->isVolatile(), Ld->isNonTemporal(),
24466 Ld->isInvariant(), Ld->getAlignment());
24467 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24468 Ld->getPointerInfo().getWithOffset(4),
24469 Ld->isVolatile(), Ld->isNonTemporal(),
24471 MinAlign(Ld->getAlignment(), 4));
24473 SDValue NewChain = LoLd.getValue(1);
24474 if (TokenFactorIndex != -1) {
24475 Ops.push_back(LoLd);
24476 Ops.push_back(HiLd);
24477 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24480 LoAddr = St->getBasePtr();
24481 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24482 DAG.getConstant(4, MVT::i32));
24484 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24485 St->getPointerInfo(),
24486 St->isVolatile(), St->isNonTemporal(),
24487 St->getAlignment());
24488 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24489 St->getPointerInfo().getWithOffset(4),
24491 St->isNonTemporal(),
24492 MinAlign(St->getAlignment(), 4));
24493 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24498 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24499 /// and return the operands for the horizontal operation in LHS and RHS. A
24500 /// horizontal operation performs the binary operation on successive elements
24501 /// of its first operand, then on successive elements of its second operand,
24502 /// returning the resulting values in a vector. For example, if
24503 /// A = < float a0, float a1, float a2, float a3 >
24505 /// B = < float b0, float b1, float b2, float b3 >
24506 /// then the result of doing a horizontal operation on A and B is
24507 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24508 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24509 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24510 /// set to A, RHS to B, and the routine returns 'true'.
24511 /// Note that the binary operation should have the property that if one of the
24512 /// operands is UNDEF then the result is UNDEF.
24513 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24514 // Look for the following pattern: if
24515 // A = < float a0, float a1, float a2, float a3 >
24516 // B = < float b0, float b1, float b2, float b3 >
24518 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24519 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24520 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24521 // which is A horizontal-op B.
24523 // At least one of the operands should be a vector shuffle.
24524 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24525 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24528 MVT VT = LHS.getSimpleValueType();
24530 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24531 "Unsupported vector type for horizontal add/sub");
24533 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24534 // operate independently on 128-bit lanes.
24535 unsigned NumElts = VT.getVectorNumElements();
24536 unsigned NumLanes = VT.getSizeInBits()/128;
24537 unsigned NumLaneElts = NumElts / NumLanes;
24538 assert((NumLaneElts % 2 == 0) &&
24539 "Vector type should have an even number of elements in each lane");
24540 unsigned HalfLaneElts = NumLaneElts/2;
24542 // View LHS in the form
24543 // LHS = VECTOR_SHUFFLE A, B, LMask
24544 // If LHS is not a shuffle then pretend it is the shuffle
24545 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24546 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24549 SmallVector<int, 16> LMask(NumElts);
24550 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24551 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24552 A = LHS.getOperand(0);
24553 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24554 B = LHS.getOperand(1);
24555 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24556 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24558 if (LHS.getOpcode() != ISD::UNDEF)
24560 for (unsigned i = 0; i != NumElts; ++i)
24564 // Likewise, view RHS in the form
24565 // RHS = VECTOR_SHUFFLE C, D, RMask
24567 SmallVector<int, 16> RMask(NumElts);
24568 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24569 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24570 C = RHS.getOperand(0);
24571 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24572 D = RHS.getOperand(1);
24573 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24574 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24576 if (RHS.getOpcode() != ISD::UNDEF)
24578 for (unsigned i = 0; i != NumElts; ++i)
24582 // Check that the shuffles are both shuffling the same vectors.
24583 if (!(A == C && B == D) && !(A == D && B == C))
24586 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24587 if (!A.getNode() && !B.getNode())
24590 // If A and B occur in reverse order in RHS, then "swap" them (which means
24591 // rewriting the mask).
24593 CommuteVectorShuffleMask(RMask, NumElts);
24595 // At this point LHS and RHS are equivalent to
24596 // LHS = VECTOR_SHUFFLE A, B, LMask
24597 // RHS = VECTOR_SHUFFLE A, B, RMask
24598 // Check that the masks correspond to performing a horizontal operation.
24599 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24600 for (unsigned i = 0; i != NumLaneElts; ++i) {
24601 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24603 // Ignore any UNDEF components.
24604 if (LIdx < 0 || RIdx < 0 ||
24605 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24606 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24609 // Check that successive elements are being operated on. If not, this is
24610 // not a horizontal operation.
24611 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24612 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24613 if (!(LIdx == Index && RIdx == Index + 1) &&
24614 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24619 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24620 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24624 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24625 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24626 const X86Subtarget *Subtarget) {
24627 EVT VT = N->getValueType(0);
24628 SDValue LHS = N->getOperand(0);
24629 SDValue RHS = N->getOperand(1);
24631 // Try to synthesize horizontal adds from adds of shuffles.
24632 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24633 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24634 isHorizontalBinOp(LHS, RHS, true))
24635 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24639 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24640 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24641 const X86Subtarget *Subtarget) {
24642 EVT VT = N->getValueType(0);
24643 SDValue LHS = N->getOperand(0);
24644 SDValue RHS = N->getOperand(1);
24646 // Try to synthesize horizontal subs from subs of shuffles.
24647 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24648 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24649 isHorizontalBinOp(LHS, RHS, false))
24650 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24654 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24655 /// X86ISD::FXOR nodes.
24656 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24657 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24658 // F[X]OR(0.0, x) -> x
24659 // F[X]OR(x, 0.0) -> x
24660 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24661 if (C->getValueAPF().isPosZero())
24662 return N->getOperand(1);
24663 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24664 if (C->getValueAPF().isPosZero())
24665 return N->getOperand(0);
24669 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24670 /// X86ISD::FMAX nodes.
24671 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24672 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24674 // Only perform optimizations if UnsafeMath is used.
24675 if (!DAG.getTarget().Options.UnsafeFPMath)
24678 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24679 // into FMINC and FMAXC, which are Commutative operations.
24680 unsigned NewOp = 0;
24681 switch (N->getOpcode()) {
24682 default: llvm_unreachable("unknown opcode");
24683 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24684 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24687 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24688 N->getOperand(0), N->getOperand(1));
24691 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24692 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24693 // FAND(0.0, x) -> 0.0
24694 // FAND(x, 0.0) -> 0.0
24695 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24696 if (C->getValueAPF().isPosZero())
24697 return N->getOperand(0);
24698 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24699 if (C->getValueAPF().isPosZero())
24700 return N->getOperand(1);
24704 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24705 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24706 // FANDN(x, 0.0) -> 0.0
24707 // FANDN(0.0, x) -> x
24708 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24709 if (C->getValueAPF().isPosZero())
24710 return N->getOperand(1);
24711 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24712 if (C->getValueAPF().isPosZero())
24713 return N->getOperand(1);
24717 static SDValue PerformBTCombine(SDNode *N,
24719 TargetLowering::DAGCombinerInfo &DCI) {
24720 // BT ignores high bits in the bit index operand.
24721 SDValue Op1 = N->getOperand(1);
24722 if (Op1.hasOneUse()) {
24723 unsigned BitWidth = Op1.getValueSizeInBits();
24724 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24725 APInt KnownZero, KnownOne;
24726 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24727 !DCI.isBeforeLegalizeOps());
24728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24729 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24730 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24731 DCI.CommitTargetLoweringOpt(TLO);
24736 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24737 SDValue Op = N->getOperand(0);
24738 if (Op.getOpcode() == ISD::BITCAST)
24739 Op = Op.getOperand(0);
24740 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24741 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24742 VT.getVectorElementType().getSizeInBits() ==
24743 OpVT.getVectorElementType().getSizeInBits()) {
24744 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24749 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24750 const X86Subtarget *Subtarget) {
24751 EVT VT = N->getValueType(0);
24752 if (!VT.isVector())
24755 SDValue N0 = N->getOperand(0);
24756 SDValue N1 = N->getOperand(1);
24757 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24760 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24761 // both SSE and AVX2 since there is no sign-extended shift right
24762 // operation on a vector with 64-bit elements.
24763 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24764 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24765 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24766 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24767 SDValue N00 = N0.getOperand(0);
24769 // EXTLOAD has a better solution on AVX2,
24770 // it may be replaced with X86ISD::VSEXT node.
24771 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24772 if (!ISD::isNormalLoad(N00.getNode()))
24775 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24776 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24778 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24784 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24785 TargetLowering::DAGCombinerInfo &DCI,
24786 const X86Subtarget *Subtarget) {
24787 SDValue N0 = N->getOperand(0);
24788 EVT VT = N->getValueType(0);
24790 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24791 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24792 // This exposes the sext to the sdivrem lowering, so that it directly extends
24793 // from AH (which we otherwise need to do contortions to access).
24794 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24795 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24797 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24798 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24799 N0.getOperand(0), N0.getOperand(1));
24800 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24801 return R.getValue(1);
24804 if (!DCI.isBeforeLegalizeOps())
24807 if (!Subtarget->hasFp256())
24810 if (VT.isVector() && VT.getSizeInBits() == 256) {
24811 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24819 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24820 const X86Subtarget* Subtarget) {
24822 EVT VT = N->getValueType(0);
24824 // Let legalize expand this if it isn't a legal type yet.
24825 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24828 EVT ScalarVT = VT.getScalarType();
24829 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24830 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24833 SDValue A = N->getOperand(0);
24834 SDValue B = N->getOperand(1);
24835 SDValue C = N->getOperand(2);
24837 bool NegA = (A.getOpcode() == ISD::FNEG);
24838 bool NegB = (B.getOpcode() == ISD::FNEG);
24839 bool NegC = (C.getOpcode() == ISD::FNEG);
24841 // Negative multiplication when NegA xor NegB
24842 bool NegMul = (NegA != NegB);
24844 A = A.getOperand(0);
24846 B = B.getOperand(0);
24848 C = C.getOperand(0);
24852 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24854 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24856 return DAG.getNode(Opcode, dl, VT, A, B, C);
24859 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24860 TargetLowering::DAGCombinerInfo &DCI,
24861 const X86Subtarget *Subtarget) {
24862 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24863 // (and (i32 x86isd::setcc_carry), 1)
24864 // This eliminates the zext. This transformation is necessary because
24865 // ISD::SETCC is always legalized to i8.
24867 SDValue N0 = N->getOperand(0);
24868 EVT VT = N->getValueType(0);
24870 if (N0.getOpcode() == ISD::AND &&
24872 N0.getOperand(0).hasOneUse()) {
24873 SDValue N00 = N0.getOperand(0);
24874 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24875 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24876 if (!C || C->getZExtValue() != 1)
24878 return DAG.getNode(ISD::AND, dl, VT,
24879 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24880 N00.getOperand(0), N00.getOperand(1)),
24881 DAG.getConstant(1, VT));
24885 if (N0.getOpcode() == ISD::TRUNCATE &&
24887 N0.getOperand(0).hasOneUse()) {
24888 SDValue N00 = N0.getOperand(0);
24889 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24890 return DAG.getNode(ISD::AND, dl, VT,
24891 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24892 N00.getOperand(0), N00.getOperand(1)),
24893 DAG.getConstant(1, VT));
24896 if (VT.is256BitVector()) {
24897 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24902 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24903 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24904 // This exposes the zext to the udivrem lowering, so that it directly extends
24905 // from AH (which we otherwise need to do contortions to access).
24906 if (N0.getOpcode() == ISD::UDIVREM &&
24907 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24908 (VT == MVT::i32 || VT == MVT::i64)) {
24909 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24910 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24911 N0.getOperand(0), N0.getOperand(1));
24912 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24913 return R.getValue(1);
24919 // Optimize x == -y --> x+y == 0
24920 // x != -y --> x+y != 0
24921 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24922 const X86Subtarget* Subtarget) {
24923 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24924 SDValue LHS = N->getOperand(0);
24925 SDValue RHS = N->getOperand(1);
24926 EVT VT = N->getValueType(0);
24929 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24930 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24931 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24932 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24933 LHS.getValueType(), RHS, LHS.getOperand(1));
24934 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24935 addV, DAG.getConstant(0, addV.getValueType()), CC);
24937 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24938 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24939 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24940 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24941 RHS.getValueType(), LHS, RHS.getOperand(1));
24942 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24943 addV, DAG.getConstant(0, addV.getValueType()), CC);
24946 if (VT.getScalarType() == MVT::i1) {
24947 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24948 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24949 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24950 if (!IsSEXT0 && !IsVZero0)
24952 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24953 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24954 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24956 if (!IsSEXT1 && !IsVZero1)
24959 if (IsSEXT0 && IsVZero1) {
24960 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24961 if (CC == ISD::SETEQ)
24962 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24963 return LHS.getOperand(0);
24965 if (IsSEXT1 && IsVZero0) {
24966 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24967 if (CC == ISD::SETEQ)
24968 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24969 return RHS.getOperand(0);
24976 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24977 const X86Subtarget *Subtarget) {
24979 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24980 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24981 "X86insertps is only defined for v4x32");
24983 SDValue Ld = N->getOperand(1);
24984 if (MayFoldLoad(Ld)) {
24985 // Extract the countS bits from the immediate so we can get the proper
24986 // address when narrowing the vector load to a specific element.
24987 // When the second source op is a memory address, interps doesn't use
24988 // countS and just gets an f32 from that address.
24989 unsigned DestIndex =
24990 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24991 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24995 // Create this as a scalar to vector to match the instruction pattern.
24996 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24997 // countS bits are ignored when loading from memory on insertps, which
24998 // means we don't need to explicitly set them to 0.
24999 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25000 LoadScalarToVector, N->getOperand(2));
25003 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25004 // as "sbb reg,reg", since it can be extended without zext and produces
25005 // an all-ones bit which is more useful than 0/1 in some cases.
25006 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25009 return DAG.getNode(ISD::AND, DL, VT,
25010 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25011 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25012 DAG.getConstant(1, VT));
25013 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25014 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25015 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25016 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25019 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25020 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25021 TargetLowering::DAGCombinerInfo &DCI,
25022 const X86Subtarget *Subtarget) {
25024 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25025 SDValue EFLAGS = N->getOperand(1);
25027 if (CC == X86::COND_A) {
25028 // Try to convert COND_A into COND_B in an attempt to facilitate
25029 // materializing "setb reg".
25031 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25032 // cannot take an immediate as its first operand.
25034 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25035 EFLAGS.getValueType().isInteger() &&
25036 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25037 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25038 EFLAGS.getNode()->getVTList(),
25039 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25040 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25041 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25045 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25046 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25048 if (CC == X86::COND_B)
25049 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25053 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25054 if (Flags.getNode()) {
25055 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25056 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25062 // Optimize branch condition evaluation.
25064 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25065 TargetLowering::DAGCombinerInfo &DCI,
25066 const X86Subtarget *Subtarget) {
25068 SDValue Chain = N->getOperand(0);
25069 SDValue Dest = N->getOperand(1);
25070 SDValue EFLAGS = N->getOperand(3);
25071 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25075 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25076 if (Flags.getNode()) {
25077 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25078 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25085 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25086 SelectionDAG &DAG) {
25087 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25088 // optimize away operation when it's from a constant.
25090 // The general transformation is:
25091 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25092 // AND(VECTOR_CMP(x,y), constant2)
25093 // constant2 = UNARYOP(constant)
25095 // Early exit if this isn't a vector operation, the operand of the
25096 // unary operation isn't a bitwise AND, or if the sizes of the operations
25097 // aren't the same.
25098 EVT VT = N->getValueType(0);
25099 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25100 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25101 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25104 // Now check that the other operand of the AND is a constant. We could
25105 // make the transformation for non-constant splats as well, but it's unclear
25106 // that would be a benefit as it would not eliminate any operations, just
25107 // perform one more step in scalar code before moving to the vector unit.
25108 if (BuildVectorSDNode *BV =
25109 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25110 // Bail out if the vector isn't a constant.
25111 if (!BV->isConstant())
25114 // Everything checks out. Build up the new and improved node.
25116 EVT IntVT = BV->getValueType(0);
25117 // Create a new constant of the appropriate type for the transformed
25119 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25120 // The AND node needs bitcasts to/from an integer vector type around it.
25121 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25122 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25123 N->getOperand(0)->getOperand(0), MaskConst);
25124 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25131 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25132 const X86TargetLowering *XTLI) {
25133 // First try to optimize away the conversion entirely when it's
25134 // conditionally from a constant. Vectors only.
25135 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25136 if (Res != SDValue())
25139 // Now move on to more general possibilities.
25140 SDValue Op0 = N->getOperand(0);
25141 EVT InVT = Op0->getValueType(0);
25143 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25144 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25146 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25147 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25148 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25151 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25152 // a 32-bit target where SSE doesn't support i64->FP operations.
25153 if (Op0.getOpcode() == ISD::LOAD) {
25154 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25155 EVT VT = Ld->getValueType(0);
25156 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25157 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25158 !XTLI->getSubtarget()->is64Bit() &&
25160 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25161 Ld->getChain(), Op0, DAG);
25162 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25169 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25170 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25171 X86TargetLowering::DAGCombinerInfo &DCI) {
25172 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25173 // the result is either zero or one (depending on the input carry bit).
25174 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25175 if (X86::isZeroNode(N->getOperand(0)) &&
25176 X86::isZeroNode(N->getOperand(1)) &&
25177 // We don't have a good way to replace an EFLAGS use, so only do this when
25179 SDValue(N, 1).use_empty()) {
25181 EVT VT = N->getValueType(0);
25182 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25183 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25184 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25185 DAG.getConstant(X86::COND_B,MVT::i8),
25187 DAG.getConstant(1, VT));
25188 return DCI.CombineTo(N, Res1, CarryOut);
25194 // fold (add Y, (sete X, 0)) -> adc 0, Y
25195 // (add Y, (setne X, 0)) -> sbb -1, Y
25196 // (sub (sete X, 0), Y) -> sbb 0, Y
25197 // (sub (setne X, 0), Y) -> adc -1, Y
25198 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25201 // Look through ZExts.
25202 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25203 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25206 SDValue SetCC = Ext.getOperand(0);
25207 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25210 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25211 if (CC != X86::COND_E && CC != X86::COND_NE)
25214 SDValue Cmp = SetCC.getOperand(1);
25215 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25216 !X86::isZeroNode(Cmp.getOperand(1)) ||
25217 !Cmp.getOperand(0).getValueType().isInteger())
25220 SDValue CmpOp0 = Cmp.getOperand(0);
25221 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25222 DAG.getConstant(1, CmpOp0.getValueType()));
25224 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25225 if (CC == X86::COND_NE)
25226 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25227 DL, OtherVal.getValueType(), OtherVal,
25228 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25229 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25230 DL, OtherVal.getValueType(), OtherVal,
25231 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25234 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25235 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25236 const X86Subtarget *Subtarget) {
25237 EVT VT = N->getValueType(0);
25238 SDValue Op0 = N->getOperand(0);
25239 SDValue Op1 = N->getOperand(1);
25241 // Try to synthesize horizontal adds from adds of shuffles.
25242 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25243 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25244 isHorizontalBinOp(Op0, Op1, true))
25245 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25247 return OptimizeConditionalInDecrement(N, DAG);
25250 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25251 const X86Subtarget *Subtarget) {
25252 SDValue Op0 = N->getOperand(0);
25253 SDValue Op1 = N->getOperand(1);
25255 // X86 can't encode an immediate LHS of a sub. See if we can push the
25256 // negation into a preceding instruction.
25257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25258 // If the RHS of the sub is a XOR with one use and a constant, invert the
25259 // immediate. Then add one to the LHS of the sub so we can turn
25260 // X-Y -> X+~Y+1, saving one register.
25261 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25262 isa<ConstantSDNode>(Op1.getOperand(1))) {
25263 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25264 EVT VT = Op0.getValueType();
25265 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25267 DAG.getConstant(~XorC, VT));
25268 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25269 DAG.getConstant(C->getAPIntValue()+1, VT));
25273 // Try to synthesize horizontal adds from adds of shuffles.
25274 EVT VT = N->getValueType(0);
25275 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25276 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25277 isHorizontalBinOp(Op0, Op1, true))
25278 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25280 return OptimizeConditionalInDecrement(N, DAG);
25283 /// performVZEXTCombine - Performs build vector combines
25284 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25285 TargetLowering::DAGCombinerInfo &DCI,
25286 const X86Subtarget *Subtarget) {
25288 MVT VT = N->getSimpleValueType(0);
25289 SDValue Op = N->getOperand(0);
25290 MVT OpVT = Op.getSimpleValueType();
25291 MVT OpEltVT = OpVT.getVectorElementType();
25292 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25294 // (vzext (bitcast (vzext (x)) -> (vzext x)
25296 while (V.getOpcode() == ISD::BITCAST)
25297 V = V.getOperand(0);
25299 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25300 MVT InnerVT = V.getSimpleValueType();
25301 MVT InnerEltVT = InnerVT.getVectorElementType();
25303 // If the element sizes match exactly, we can just do one larger vzext. This
25304 // is always an exact type match as vzext operates on integer types.
25305 if (OpEltVT == InnerEltVT) {
25306 assert(OpVT == InnerVT && "Types must match for vzext!");
25307 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25310 // The only other way we can combine them is if only a single element of the
25311 // inner vzext is used in the input to the outer vzext.
25312 if (InnerEltVT.getSizeInBits() < InputBits)
25315 // In this case, the inner vzext is completely dead because we're going to
25316 // only look at bits inside of the low element. Just do the outer vzext on
25317 // a bitcast of the input to the inner.
25318 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25319 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25322 // Check if we can bypass extracting and re-inserting an element of an input
25323 // vector. Essentialy:
25324 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25325 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25326 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25327 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25328 SDValue ExtractedV = V.getOperand(0);
25329 SDValue OrigV = ExtractedV.getOperand(0);
25330 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25331 if (ExtractIdx->getZExtValue() == 0) {
25332 MVT OrigVT = OrigV.getSimpleValueType();
25333 // Extract a subvector if necessary...
25334 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25335 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25336 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25337 OrigVT.getVectorNumElements() / Ratio);
25338 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25339 DAG.getIntPtrConstant(0));
25341 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25342 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25349 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25350 DAGCombinerInfo &DCI) const {
25351 SelectionDAG &DAG = DCI.DAG;
25352 switch (N->getOpcode()) {
25354 case ISD::EXTRACT_VECTOR_ELT:
25355 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25358 case X86ISD::SHRUNKBLEND:
25359 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25360 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25361 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25362 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25363 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25364 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25367 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25368 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25369 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25370 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25371 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25372 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25373 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25374 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25375 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25377 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25379 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25380 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25381 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25382 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25383 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25384 case ISD::ANY_EXTEND:
25385 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25386 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25387 case ISD::SIGN_EXTEND_INREG:
25388 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25389 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25390 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25391 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25392 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25393 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25394 case X86ISD::SHUFP: // Handle all target specific shuffles
25395 case X86ISD::PALIGNR:
25396 case X86ISD::UNPCKH:
25397 case X86ISD::UNPCKL:
25398 case X86ISD::MOVHLPS:
25399 case X86ISD::MOVLHPS:
25400 case X86ISD::PSHUFB:
25401 case X86ISD::PSHUFD:
25402 case X86ISD::PSHUFHW:
25403 case X86ISD::PSHUFLW:
25404 case X86ISD::MOVSS:
25405 case X86ISD::MOVSD:
25406 case X86ISD::VPERMILPI:
25407 case X86ISD::VPERM2X128:
25408 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25409 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25410 case ISD::INTRINSIC_WO_CHAIN:
25411 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25412 case X86ISD::INSERTPS:
25413 return PerformINSERTPSCombine(N, DAG, Subtarget);
25414 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25420 /// isTypeDesirableForOp - Return true if the target has native support for
25421 /// the specified value type and it is 'desirable' to use the type for the
25422 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25423 /// instruction encodings are longer and some i16 instructions are slow.
25424 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25425 if (!isTypeLegal(VT))
25427 if (VT != MVT::i16)
25434 case ISD::SIGN_EXTEND:
25435 case ISD::ZERO_EXTEND:
25436 case ISD::ANY_EXTEND:
25449 /// IsDesirableToPromoteOp - This method query the target whether it is
25450 /// beneficial for dag combiner to promote the specified node. If true, it
25451 /// should return the desired promotion type by reference.
25452 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25453 EVT VT = Op.getValueType();
25454 if (VT != MVT::i16)
25457 bool Promote = false;
25458 bool Commute = false;
25459 switch (Op.getOpcode()) {
25462 LoadSDNode *LD = cast<LoadSDNode>(Op);
25463 // If the non-extending load has a single use and it's not live out, then it
25464 // might be folded.
25465 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25466 Op.hasOneUse()*/) {
25467 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25468 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25469 // The only case where we'd want to promote LOAD (rather then it being
25470 // promoted as an operand is when it's only use is liveout.
25471 if (UI->getOpcode() != ISD::CopyToReg)
25478 case ISD::SIGN_EXTEND:
25479 case ISD::ZERO_EXTEND:
25480 case ISD::ANY_EXTEND:
25485 SDValue N0 = Op.getOperand(0);
25486 // Look out for (store (shl (load), x)).
25487 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25500 SDValue N0 = Op.getOperand(0);
25501 SDValue N1 = Op.getOperand(1);
25502 if (!Commute && MayFoldLoad(N1))
25504 // Avoid disabling potential load folding opportunities.
25505 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25507 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25517 //===----------------------------------------------------------------------===//
25518 // X86 Inline Assembly Support
25519 //===----------------------------------------------------------------------===//
25522 // Helper to match a string separated by whitespace.
25523 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25524 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25526 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25527 StringRef piece(*args[i]);
25528 if (!s.startswith(piece)) // Check if the piece matches.
25531 s = s.substr(piece.size());
25532 StringRef::size_type pos = s.find_first_not_of(" \t");
25533 if (pos == 0) // We matched a prefix.
25541 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25544 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25546 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25547 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25548 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25549 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25551 if (AsmPieces.size() == 3)
25553 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25560 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25561 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25563 std::string AsmStr = IA->getAsmString();
25565 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25566 if (!Ty || Ty->getBitWidth() % 16 != 0)
25569 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25570 SmallVector<StringRef, 4> AsmPieces;
25571 SplitString(AsmStr, AsmPieces, ";\n");
25573 switch (AsmPieces.size()) {
25574 default: return false;
25576 // FIXME: this should verify that we are targeting a 486 or better. If not,
25577 // we will turn this bswap into something that will be lowered to logical
25578 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25579 // lower so don't worry about this.
25581 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25582 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25583 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25584 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25585 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25586 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25587 // No need to check constraints, nothing other than the equivalent of
25588 // "=r,0" would be valid here.
25589 return IntrinsicLowering::LowerToByteSwap(CI);
25592 // rorw $$8, ${0:w} --> llvm.bswap.i16
25593 if (CI->getType()->isIntegerTy(16) &&
25594 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25595 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25596 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25598 const std::string &ConstraintsStr = IA->getConstraintString();
25599 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25600 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25601 if (clobbersFlagRegisters(AsmPieces))
25602 return IntrinsicLowering::LowerToByteSwap(CI);
25606 if (CI->getType()->isIntegerTy(32) &&
25607 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25608 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25609 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25610 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25612 const std::string &ConstraintsStr = IA->getConstraintString();
25613 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25614 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25615 if (clobbersFlagRegisters(AsmPieces))
25616 return IntrinsicLowering::LowerToByteSwap(CI);
25619 if (CI->getType()->isIntegerTy(64)) {
25620 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25621 if (Constraints.size() >= 2 &&
25622 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25623 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25624 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25625 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25626 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25627 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25628 return IntrinsicLowering::LowerToByteSwap(CI);
25636 /// getConstraintType - Given a constraint letter, return the type of
25637 /// constraint it is for this target.
25638 X86TargetLowering::ConstraintType
25639 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25640 if (Constraint.size() == 1) {
25641 switch (Constraint[0]) {
25652 return C_RegisterClass;
25676 return TargetLowering::getConstraintType(Constraint);
25679 /// Examine constraint type and operand type and determine a weight value.
25680 /// This object must already have been set up with the operand type
25681 /// and the current alternative constraint selected.
25682 TargetLowering::ConstraintWeight
25683 X86TargetLowering::getSingleConstraintMatchWeight(
25684 AsmOperandInfo &info, const char *constraint) const {
25685 ConstraintWeight weight = CW_Invalid;
25686 Value *CallOperandVal = info.CallOperandVal;
25687 // If we don't have a value, we can't do a match,
25688 // but allow it at the lowest weight.
25689 if (!CallOperandVal)
25691 Type *type = CallOperandVal->getType();
25692 // Look at the constraint type.
25693 switch (*constraint) {
25695 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25706 if (CallOperandVal->getType()->isIntegerTy())
25707 weight = CW_SpecificReg;
25712 if (type->isFloatingPointTy())
25713 weight = CW_SpecificReg;
25716 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25717 weight = CW_SpecificReg;
25721 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25722 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25723 weight = CW_Register;
25726 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25727 if (C->getZExtValue() <= 31)
25728 weight = CW_Constant;
25732 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25733 if (C->getZExtValue() <= 63)
25734 weight = CW_Constant;
25738 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25739 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25740 weight = CW_Constant;
25744 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25745 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25746 weight = CW_Constant;
25750 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25751 if (C->getZExtValue() <= 3)
25752 weight = CW_Constant;
25756 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25757 if (C->getZExtValue() <= 0xff)
25758 weight = CW_Constant;
25763 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25764 weight = CW_Constant;
25768 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25769 if ((C->getSExtValue() >= -0x80000000LL) &&
25770 (C->getSExtValue() <= 0x7fffffffLL))
25771 weight = CW_Constant;
25775 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25776 if (C->getZExtValue() <= 0xffffffff)
25777 weight = CW_Constant;
25784 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25785 /// with another that has more specific requirements based on the type of the
25786 /// corresponding operand.
25787 const char *X86TargetLowering::
25788 LowerXConstraint(EVT ConstraintVT) const {
25789 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25790 // 'f' like normal targets.
25791 if (ConstraintVT.isFloatingPoint()) {
25792 if (Subtarget->hasSSE2())
25794 if (Subtarget->hasSSE1())
25798 return TargetLowering::LowerXConstraint(ConstraintVT);
25801 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25802 /// vector. If it is invalid, don't add anything to Ops.
25803 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25804 std::string &Constraint,
25805 std::vector<SDValue>&Ops,
25806 SelectionDAG &DAG) const {
25809 // Only support length 1 constraints for now.
25810 if (Constraint.length() > 1) return;
25812 char ConstraintLetter = Constraint[0];
25813 switch (ConstraintLetter) {
25816 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25817 if (C->getZExtValue() <= 31) {
25818 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25824 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25825 if (C->getZExtValue() <= 63) {
25826 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25833 if (isInt<8>(C->getSExtValue())) {
25834 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25841 if (C->getZExtValue() <= 255) {
25842 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25848 // 32-bit signed value
25849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25850 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25851 C->getSExtValue())) {
25852 // Widen to 64 bits here to get it sign extended.
25853 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25856 // FIXME gcc accepts some relocatable values here too, but only in certain
25857 // memory models; it's complicated.
25862 // 32-bit unsigned value
25863 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25864 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25865 C->getZExtValue())) {
25866 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25870 // FIXME gcc accepts some relocatable values here too, but only in certain
25871 // memory models; it's complicated.
25875 // Literal immediates are always ok.
25876 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25877 // Widen to 64 bits here to get it sign extended.
25878 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25882 // In any sort of PIC mode addresses need to be computed at runtime by
25883 // adding in a register or some sort of table lookup. These can't
25884 // be used as immediates.
25885 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25888 // If we are in non-pic codegen mode, we allow the address of a global (with
25889 // an optional displacement) to be used with 'i'.
25890 GlobalAddressSDNode *GA = nullptr;
25891 int64_t Offset = 0;
25893 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25895 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25896 Offset += GA->getOffset();
25898 } else if (Op.getOpcode() == ISD::ADD) {
25899 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25900 Offset += C->getZExtValue();
25901 Op = Op.getOperand(0);
25904 } else if (Op.getOpcode() == ISD::SUB) {
25905 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25906 Offset += -C->getZExtValue();
25907 Op = Op.getOperand(0);
25912 // Otherwise, this isn't something we can handle, reject it.
25916 const GlobalValue *GV = GA->getGlobal();
25917 // If we require an extra load to get this address, as in PIC mode, we
25918 // can't accept it.
25919 if (isGlobalStubReference(
25920 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25923 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25924 GA->getValueType(0), Offset);
25929 if (Result.getNode()) {
25930 Ops.push_back(Result);
25933 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25936 std::pair<unsigned, const TargetRegisterClass*>
25937 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25939 // First, see if this is a constraint that directly corresponds to an LLVM
25941 if (Constraint.size() == 1) {
25942 // GCC Constraint Letters
25943 switch (Constraint[0]) {
25945 // TODO: Slight differences here in allocation order and leaving
25946 // RIP in the class. Do they matter any more here than they do
25947 // in the normal allocation?
25948 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25949 if (Subtarget->is64Bit()) {
25950 if (VT == MVT::i32 || VT == MVT::f32)
25951 return std::make_pair(0U, &X86::GR32RegClass);
25952 if (VT == MVT::i16)
25953 return std::make_pair(0U, &X86::GR16RegClass);
25954 if (VT == MVT::i8 || VT == MVT::i1)
25955 return std::make_pair(0U, &X86::GR8RegClass);
25956 if (VT == MVT::i64 || VT == MVT::f64)
25957 return std::make_pair(0U, &X86::GR64RegClass);
25960 // 32-bit fallthrough
25961 case 'Q': // Q_REGS
25962 if (VT == MVT::i32 || VT == MVT::f32)
25963 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25964 if (VT == MVT::i16)
25965 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25966 if (VT == MVT::i8 || VT == MVT::i1)
25967 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25968 if (VT == MVT::i64)
25969 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25971 case 'r': // GENERAL_REGS
25972 case 'l': // INDEX_REGS
25973 if (VT == MVT::i8 || VT == MVT::i1)
25974 return std::make_pair(0U, &X86::GR8RegClass);
25975 if (VT == MVT::i16)
25976 return std::make_pair(0U, &X86::GR16RegClass);
25977 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25978 return std::make_pair(0U, &X86::GR32RegClass);
25979 return std::make_pair(0U, &X86::GR64RegClass);
25980 case 'R': // LEGACY_REGS
25981 if (VT == MVT::i8 || VT == MVT::i1)
25982 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25983 if (VT == MVT::i16)
25984 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25985 if (VT == MVT::i32 || !Subtarget->is64Bit())
25986 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25987 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25988 case 'f': // FP Stack registers.
25989 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25990 // value to the correct fpstack register class.
25991 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25992 return std::make_pair(0U, &X86::RFP32RegClass);
25993 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25994 return std::make_pair(0U, &X86::RFP64RegClass);
25995 return std::make_pair(0U, &X86::RFP80RegClass);
25996 case 'y': // MMX_REGS if MMX allowed.
25997 if (!Subtarget->hasMMX()) break;
25998 return std::make_pair(0U, &X86::VR64RegClass);
25999 case 'Y': // SSE_REGS if SSE2 allowed
26000 if (!Subtarget->hasSSE2()) break;
26002 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26003 if (!Subtarget->hasSSE1()) break;
26005 switch (VT.SimpleTy) {
26007 // Scalar SSE types.
26010 return std::make_pair(0U, &X86::FR32RegClass);
26013 return std::make_pair(0U, &X86::FR64RegClass);
26021 return std::make_pair(0U, &X86::VR128RegClass);
26029 return std::make_pair(0U, &X86::VR256RegClass);
26034 return std::make_pair(0U, &X86::VR512RegClass);
26040 // Use the default implementation in TargetLowering to convert the register
26041 // constraint into a member of a register class.
26042 std::pair<unsigned, const TargetRegisterClass*> Res;
26043 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26045 // Not found as a standard register?
26047 // Map st(0) -> st(7) -> ST0
26048 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26049 tolower(Constraint[1]) == 's' &&
26050 tolower(Constraint[2]) == 't' &&
26051 Constraint[3] == '(' &&
26052 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26053 Constraint[5] == ')' &&
26054 Constraint[6] == '}') {
26056 Res.first = X86::FP0+Constraint[4]-'0';
26057 Res.second = &X86::RFP80RegClass;
26061 // GCC allows "st(0)" to be called just plain "st".
26062 if (StringRef("{st}").equals_lower(Constraint)) {
26063 Res.first = X86::FP0;
26064 Res.second = &X86::RFP80RegClass;
26069 if (StringRef("{flags}").equals_lower(Constraint)) {
26070 Res.first = X86::EFLAGS;
26071 Res.second = &X86::CCRRegClass;
26075 // 'A' means EAX + EDX.
26076 if (Constraint == "A") {
26077 Res.first = X86::EAX;
26078 Res.second = &X86::GR32_ADRegClass;
26084 // Otherwise, check to see if this is a register class of the wrong value
26085 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26086 // turn into {ax},{dx}.
26087 if (Res.second->hasType(VT))
26088 return Res; // Correct type already, nothing to do.
26090 // All of the single-register GCC register classes map their values onto
26091 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26092 // really want an 8-bit or 32-bit register, map to the appropriate register
26093 // class and return the appropriate register.
26094 if (Res.second == &X86::GR16RegClass) {
26095 if (VT == MVT::i8 || VT == MVT::i1) {
26096 unsigned DestReg = 0;
26097 switch (Res.first) {
26099 case X86::AX: DestReg = X86::AL; break;
26100 case X86::DX: DestReg = X86::DL; break;
26101 case X86::CX: DestReg = X86::CL; break;
26102 case X86::BX: DestReg = X86::BL; break;
26105 Res.first = DestReg;
26106 Res.second = &X86::GR8RegClass;
26108 } else if (VT == MVT::i32 || VT == MVT::f32) {
26109 unsigned DestReg = 0;
26110 switch (Res.first) {
26112 case X86::AX: DestReg = X86::EAX; break;
26113 case X86::DX: DestReg = X86::EDX; break;
26114 case X86::CX: DestReg = X86::ECX; break;
26115 case X86::BX: DestReg = X86::EBX; break;
26116 case X86::SI: DestReg = X86::ESI; break;
26117 case X86::DI: DestReg = X86::EDI; break;
26118 case X86::BP: DestReg = X86::EBP; break;
26119 case X86::SP: DestReg = X86::ESP; break;
26122 Res.first = DestReg;
26123 Res.second = &X86::GR32RegClass;
26125 } else if (VT == MVT::i64 || VT == MVT::f64) {
26126 unsigned DestReg = 0;
26127 switch (Res.first) {
26129 case X86::AX: DestReg = X86::RAX; break;
26130 case X86::DX: DestReg = X86::RDX; break;
26131 case X86::CX: DestReg = X86::RCX; break;
26132 case X86::BX: DestReg = X86::RBX; break;
26133 case X86::SI: DestReg = X86::RSI; break;
26134 case X86::DI: DestReg = X86::RDI; break;
26135 case X86::BP: DestReg = X86::RBP; break;
26136 case X86::SP: DestReg = X86::RSP; break;
26139 Res.first = DestReg;
26140 Res.second = &X86::GR64RegClass;
26143 } else if (Res.second == &X86::FR32RegClass ||
26144 Res.second == &X86::FR64RegClass ||
26145 Res.second == &X86::VR128RegClass ||
26146 Res.second == &X86::VR256RegClass ||
26147 Res.second == &X86::FR32XRegClass ||
26148 Res.second == &X86::FR64XRegClass ||
26149 Res.second == &X86::VR128XRegClass ||
26150 Res.second == &X86::VR256XRegClass ||
26151 Res.second == &X86::VR512RegClass) {
26152 // Handle references to XMM physical registers that got mapped into the
26153 // wrong class. This can happen with constraints like {xmm0} where the
26154 // target independent register mapper will just pick the first match it can
26155 // find, ignoring the required type.
26157 if (VT == MVT::f32 || VT == MVT::i32)
26158 Res.second = &X86::FR32RegClass;
26159 else if (VT == MVT::f64 || VT == MVT::i64)
26160 Res.second = &X86::FR64RegClass;
26161 else if (X86::VR128RegClass.hasType(VT))
26162 Res.second = &X86::VR128RegClass;
26163 else if (X86::VR256RegClass.hasType(VT))
26164 Res.second = &X86::VR256RegClass;
26165 else if (X86::VR512RegClass.hasType(VT))
26166 Res.second = &X86::VR512RegClass;
26172 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26174 // Scaling factors are not free at all.
26175 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26176 // will take 2 allocations in the out of order engine instead of 1
26177 // for plain addressing mode, i.e. inst (reg1).
26179 // vaddps (%rsi,%drx), %ymm0, %ymm1
26180 // Requires two allocations (one for the load, one for the computation)
26182 // vaddps (%rsi), %ymm0, %ymm1
26183 // Requires just 1 allocation, i.e., freeing allocations for other operations
26184 // and having less micro operations to execute.
26186 // For some X86 architectures, this is even worse because for instance for
26187 // stores, the complex addressing mode forces the instruction to use the
26188 // "load" ports instead of the dedicated "store" port.
26189 // E.g., on Haswell:
26190 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26191 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26192 if (isLegalAddressingMode(AM, Ty))
26193 // Scale represents reg2 * scale, thus account for 1
26194 // as soon as we use a second register.
26195 return AM.Scale != 0;
26199 bool X86TargetLowering::isTargetFTOL() const {
26200 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();