1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (TM.getOptLevel() >= CodeGenOpt::Default) {
253 if (Subtarget->hasSlowDivide32())
254 addBypassSlowDiv(32, 8);
255 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
256 addBypassSlowDiv(64, 16);
259 if (Subtarget->isTargetKnownWindowsMSVC()) {
260 // Setup Windows compiler runtime calls.
261 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
262 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
263 setLibcallName(RTLIB::SREM_I64, "_allrem");
264 setLibcallName(RTLIB::UREM_I64, "_aullrem");
265 setLibcallName(RTLIB::MUL_I64, "_allmul");
266 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
272 // The _ftol2 runtime function has an unusual calling conv, which
273 // is modeled by a special pseudo-instruction.
274 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
280 if (Subtarget->isTargetDarwin()) {
281 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
282 setUseUnderscoreSetJmp(false);
283 setUseUnderscoreLongJmp(false);
284 } else if (Subtarget->isTargetWindowsGNU()) {
285 // MS runtime is weird: it exports _setjmp, but longjmp!
286 setUseUnderscoreSetJmp(true);
287 setUseUnderscoreLongJmp(false);
289 setUseUnderscoreSetJmp(true);
290 setUseUnderscoreLongJmp(true);
293 // Set up the register classes.
294 addRegisterClass(MVT::i8, &X86::GR8RegClass);
295 addRegisterClass(MVT::i16, &X86::GR16RegClass);
296 addRegisterClass(MVT::i32, &X86::GR32RegClass);
297 if (Subtarget->is64Bit())
298 addRegisterClass(MVT::i64, &X86::GR64RegClass);
300 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
302 // We don't accept any truncstore of integer registers.
303 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
307 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
308 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
310 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
312 // SETOEQ and SETUNE require checking two conditions.
313 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
315 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
320 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
322 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
324 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
328 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
329 } else if (!TM.Options.UseSoftFloat) {
330 // We have an algorithm for SSE2->double, and we turn this into a
331 // 64-bit FILD followed by conditional FADD for other targets.
332 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
333 // We have an algorithm for SSE2, and we turn this into a 64-bit
334 // FILD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
338 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
340 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
343 if (!TM.Options.UseSoftFloat) {
344 // SSE has no i16 to fp conversion, only i32
345 if (X86ScalarSSEf32) {
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 // f32 and f64 cases are Legal, f80 case is not
348 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
358 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
359 // are Legal, f80 is custom lowered.
360 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
363 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
365 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
368 if (X86ScalarSSEf32) {
369 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
370 // f32 and f64 cases are Legal, f80 case is not
371 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
377 // Handle FP_TO_UINT by promoting the destination to a larger signed
379 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
381 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
383 if (Subtarget->is64Bit()) {
384 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
385 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
386 } else if (!TM.Options.UseSoftFloat) {
387 // Since AVX is a superset of SSE3, only check for SSE here.
388 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
389 // Expand FP_TO_UINT into a select.
390 // FIXME: We would like to use a Custom expander here eventually to do
391 // the optimal thing for SSE vs. the default expansion in the legalizer.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
394 // With SSE3 we can use fisttpll to convert to a signed i64; without
395 // SSE, we're stuck with a fistpll.
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
399 if (isTargetFTOL()) {
400 // Use the _ftol2 runtime function, which has a pseudo-instruction
401 // to handle its weird calling convention.
402 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
405 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
406 if (!X86ScalarSSEf64) {
407 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
408 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
409 if (Subtarget->is64Bit()) {
410 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
411 // Without SSE, i64->f64 goes through memory.
412 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
416 // Scalar integer divide and remainder are lowered to use operations that
417 // produce two results, to match the available instructions. This exposes
418 // the two-result form to trivial CSE, which is able to combine x/y and x%y
419 // into a single instruction.
421 // Scalar integer multiply-high is also lowered to use two-result
422 // operations, to match the available instructions. However, plain multiply
423 // (low) operations are left as Legal, as there are single-result
424 // instructions for this in x86. Using the two-result multiply instructions
425 // when both high and low results are needed must be arranged by dagcombine.
426 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
428 setOperationAction(ISD::MULHS, VT, Expand);
429 setOperationAction(ISD::MULHU, VT, Expand);
430 setOperationAction(ISD::SDIV, VT, Expand);
431 setOperationAction(ISD::UDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UREM, VT, Expand);
435 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
436 setOperationAction(ISD::ADDC, VT, Custom);
437 setOperationAction(ISD::ADDE, VT, Custom);
438 setOperationAction(ISD::SUBC, VT, Custom);
439 setOperationAction(ISD::SUBE, VT, Custom);
442 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
443 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
444 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
446 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
458 if (Subtarget->is64Bit())
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
463 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f32 , Expand);
465 setOperationAction(ISD::FREM , MVT::f64 , Expand);
466 setOperationAction(ISD::FREM , MVT::f80 , Expand);
467 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
469 // Promote the i8 variants and force them on up to i32 which has a shorter
471 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
474 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
475 if (Subtarget->hasBMI()) {
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
481 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
482 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
483 if (Subtarget->is64Bit())
484 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
487 if (Subtarget->hasLZCNT()) {
488 // When promoting the i8 variants, force them to i32 for a shorter
490 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
493 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
496 if (Subtarget->is64Bit())
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
499 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
501 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
505 if (Subtarget->is64Bit()) {
506 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
511 // Special handling for half-precision floating point conversions.
512 // If we don't have F16C support, then lower half float conversions
513 // into library calls.
514 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
515 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
516 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
519 // There's never any support for operations beyond MVT::f32.
520 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
521 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
525 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
528 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
530 if (Subtarget->hasPOPCNT()) {
531 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
533 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
535 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
536 if (Subtarget->is64Bit())
537 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
540 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
542 if (!Subtarget->hasMOVBE())
543 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
545 // These should be promoted to a larger select which is supported.
546 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
547 // X86 wants to expand cmov itself.
548 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
550 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
553 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
556 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
559 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
560 if (Subtarget->is64Bit()) {
561 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
564 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
565 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
566 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
567 // support continuation, user-level threading, and etc.. As a result, no
568 // other SjLj exception interfaces are implemented and please don't build
569 // your own exception handling based on them.
570 // LLVM/Clang supports zero-cost DWARF exception handling.
571 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
572 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
575 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
576 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
579 if (Subtarget->is64Bit())
580 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
581 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
582 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
583 if (Subtarget->is64Bit()) {
584 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
585 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
586 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
587 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
588 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
590 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
591 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
597 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
600 if (Subtarget->hasSSE1())
601 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
603 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
605 // Expand certain atomics
606 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
608 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
609 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
610 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
613 if (Subtarget->hasCmpxchg16b()) {
614 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
617 // FIXME - use subtarget debug flags
618 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
619 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
620 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
623 if (Subtarget->is64Bit()) {
624 setExceptionPointerRegister(X86::RAX);
625 setExceptionSelectorRegister(X86::RDX);
627 setExceptionPointerRegister(X86::EAX);
628 setExceptionSelectorRegister(X86::EDX);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
631 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
633 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
636 setOperationAction(ISD::TRAP, MVT::Other, Legal);
637 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
639 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
640 setOperationAction(ISD::VASTART , MVT::Other, Custom);
641 setOperationAction(ISD::VAEND , MVT::Other, Expand);
642 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
643 // TargetInfo::X86_64ABIBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Custom);
645 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
647 // TargetInfo::CharPtrBuiltinVaList
648 setOperationAction(ISD::VAARG , MVT::Other, Expand);
649 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
652 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
653 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
655 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
657 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
658 // f32 and f64 use SSE.
659 // Set up the FP register classes.
660 addRegisterClass(MVT::f32, &X86::FR32RegClass);
661 addRegisterClass(MVT::f64, &X86::FR64RegClass);
663 // Use ANDPD to simulate FABS.
664 setOperationAction(ISD::FABS , MVT::f64, Custom);
665 setOperationAction(ISD::FABS , MVT::f32, Custom);
667 // Use XORP to simulate FNEG.
668 setOperationAction(ISD::FNEG , MVT::f64, Custom);
669 setOperationAction(ISD::FNEG , MVT::f32, Custom);
671 // Use ANDPD and ORPD to simulate FCOPYSIGN.
672 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
673 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
675 // Lower this to FGETSIGNx86 plus an AND.
676 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
677 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
679 // We don't support sin/cos/fmod
680 setOperationAction(ISD::FSIN , MVT::f64, Expand);
681 setOperationAction(ISD::FCOS , MVT::f64, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
683 setOperationAction(ISD::FSIN , MVT::f32, Expand);
684 setOperationAction(ISD::FCOS , MVT::f32, Expand);
685 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
687 // Expand FP immediates into loads from the stack, except for the special
689 addLegalFPImmediate(APFloat(+0.0)); // xorpd
690 addLegalFPImmediate(APFloat(+0.0f)); // xorps
691 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
692 // Use SSE for f32, x87 for f64.
693 // Set up the FP register classes.
694 addRegisterClass(MVT::f32, &X86::FR32RegClass);
695 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
697 // Use ANDPS to simulate FABS.
698 setOperationAction(ISD::FABS , MVT::f32, Custom);
700 // Use XORP to simulate FNEG.
701 setOperationAction(ISD::FNEG , MVT::f32, Custom);
703 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
705 // Use ANDPS and ORPS to simulate FCOPYSIGN.
706 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
707 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
709 // We don't support sin/cos/fmod
710 setOperationAction(ISD::FSIN , MVT::f32, Expand);
711 setOperationAction(ISD::FCOS , MVT::f32, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
714 // Special cases we handle for FP constants.
715 addLegalFPImmediate(APFloat(+0.0f)); // xorps
716 addLegalFPImmediate(APFloat(+0.0)); // FLD0
717 addLegalFPImmediate(APFloat(+1.0)); // FLD1
718 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
719 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
721 if (!TM.Options.UnsafeFPMath) {
722 setOperationAction(ISD::FSIN , MVT::f64, Expand);
723 setOperationAction(ISD::FCOS , MVT::f64, Expand);
724 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
726 } else if (!TM.Options.UseSoftFloat) {
727 // f32 and f64 in x87.
728 // Set up the FP register classes.
729 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
730 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
732 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
733 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
735 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
737 if (!TM.Options.UnsafeFPMath) {
738 setOperationAction(ISD::FSIN , MVT::f64, Expand);
739 setOperationAction(ISD::FSIN , MVT::f32, Expand);
740 setOperationAction(ISD::FCOS , MVT::f64, Expand);
741 setOperationAction(ISD::FCOS , MVT::f32, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
743 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
745 addLegalFPImmediate(APFloat(+0.0)); // FLD0
746 addLegalFPImmediate(APFloat(+1.0)); // FLD1
747 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
748 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
749 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
750 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
751 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
752 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
755 // We don't support FMA.
756 setOperationAction(ISD::FMA, MVT::f64, Expand);
757 setOperationAction(ISD::FMA, MVT::f32, Expand);
759 // Long double always uses X87.
760 if (!TM.Options.UseSoftFloat) {
761 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
762 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
763 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
765 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
766 addLegalFPImmediate(TmpFlt); // FLD0
768 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
771 APFloat TmpFlt2(+1.0);
772 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
774 addLegalFPImmediate(TmpFlt2); // FLD1
775 TmpFlt2.changeSign();
776 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
779 if (!TM.Options.UnsafeFPMath) {
780 setOperationAction(ISD::FSIN , MVT::f80, Expand);
781 setOperationAction(ISD::FCOS , MVT::f80, Expand);
782 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
785 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
786 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
787 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
788 setOperationAction(ISD::FRINT, MVT::f80, Expand);
789 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
790 setOperationAction(ISD::FMA, MVT::f80, Expand);
793 // Always use a library call for pow.
794 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
796 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
798 setOperationAction(ISD::FLOG, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
800 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP, MVT::f80, Expand);
802 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
803 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
804 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
806 // First set operation action for all vector types to either promote
807 // (for widening) or expand (for scalarization). Then we will selectively
808 // turn on ones that can be effectively codegen'd.
809 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
810 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
811 MVT VT = (MVT::SimpleValueType)i;
812 setOperationAction(ISD::ADD , VT, Expand);
813 setOperationAction(ISD::SUB , VT, Expand);
814 setOperationAction(ISD::FADD, VT, Expand);
815 setOperationAction(ISD::FNEG, VT, Expand);
816 setOperationAction(ISD::FSUB, VT, Expand);
817 setOperationAction(ISD::MUL , VT, Expand);
818 setOperationAction(ISD::FMUL, VT, Expand);
819 setOperationAction(ISD::SDIV, VT, Expand);
820 setOperationAction(ISD::UDIV, VT, Expand);
821 setOperationAction(ISD::FDIV, VT, Expand);
822 setOperationAction(ISD::SREM, VT, Expand);
823 setOperationAction(ISD::UREM, VT, Expand);
824 setOperationAction(ISD::LOAD, VT, Expand);
825 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
828 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
830 setOperationAction(ISD::FABS, VT, Expand);
831 setOperationAction(ISD::FSIN, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FCOS, VT, Expand);
834 setOperationAction(ISD::FSINCOS, VT, Expand);
835 setOperationAction(ISD::FREM, VT, Expand);
836 setOperationAction(ISD::FMA, VT, Expand);
837 setOperationAction(ISD::FPOWI, VT, Expand);
838 setOperationAction(ISD::FSQRT, VT, Expand);
839 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
840 setOperationAction(ISD::FFLOOR, VT, Expand);
841 setOperationAction(ISD::FCEIL, VT, Expand);
842 setOperationAction(ISD::FTRUNC, VT, Expand);
843 setOperationAction(ISD::FRINT, VT, Expand);
844 setOperationAction(ISD::FNEARBYINT, VT, Expand);
845 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHS, VT, Expand);
847 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
848 setOperationAction(ISD::MULHU, VT, Expand);
849 setOperationAction(ISD::SDIVREM, VT, Expand);
850 setOperationAction(ISD::UDIVREM, VT, Expand);
851 setOperationAction(ISD::FPOW, VT, Expand);
852 setOperationAction(ISD::CTPOP, VT, Expand);
853 setOperationAction(ISD::CTTZ, VT, Expand);
854 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::CTLZ, VT, Expand);
856 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
857 setOperationAction(ISD::SHL, VT, Expand);
858 setOperationAction(ISD::SRA, VT, Expand);
859 setOperationAction(ISD::SRL, VT, Expand);
860 setOperationAction(ISD::ROTL, VT, Expand);
861 setOperationAction(ISD::ROTR, VT, Expand);
862 setOperationAction(ISD::BSWAP, VT, Expand);
863 setOperationAction(ISD::SETCC, VT, Expand);
864 setOperationAction(ISD::FLOG, VT, Expand);
865 setOperationAction(ISD::FLOG2, VT, Expand);
866 setOperationAction(ISD::FLOG10, VT, Expand);
867 setOperationAction(ISD::FEXP, VT, Expand);
868 setOperationAction(ISD::FEXP2, VT, Expand);
869 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
870 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
871 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
874 setOperationAction(ISD::TRUNCATE, VT, Expand);
875 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
876 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
877 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
878 setOperationAction(ISD::VSELECT, VT, Expand);
879 setOperationAction(ISD::SELECT_CC, VT, Expand);
880 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
881 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
882 setTruncStoreAction(VT,
883 (MVT::SimpleValueType)InnerVT, Expand);
884 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
885 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
887 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
888 // we have to deal with them whether we ask for Expansion or not. Setting
889 // Expand causes its own optimisation problems though, so leave them legal.
890 if (VT.getVectorElementType() == MVT::i1)
891 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
894 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
895 // with -msoft-float, disable use of MMX as well.
896 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
897 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
898 // No operations on x86mmx supported, everything uses intrinsics.
901 // MMX-sized vectors (other than x86mmx) are expected to be expanded
902 // into smaller operations.
903 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
904 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
905 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
906 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
907 setOperationAction(ISD::AND, MVT::v8i8, Expand);
908 setOperationAction(ISD::AND, MVT::v4i16, Expand);
909 setOperationAction(ISD::AND, MVT::v2i32, Expand);
910 setOperationAction(ISD::AND, MVT::v1i64, Expand);
911 setOperationAction(ISD::OR, MVT::v8i8, Expand);
912 setOperationAction(ISD::OR, MVT::v4i16, Expand);
913 setOperationAction(ISD::OR, MVT::v2i32, Expand);
914 setOperationAction(ISD::OR, MVT::v1i64, Expand);
915 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
916 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
917 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
918 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
924 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
925 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
926 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
927 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
931 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
933 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
934 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
936 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
937 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
938 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
939 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
940 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
941 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
942 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
943 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
944 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
945 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
947 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
948 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
951 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
952 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
954 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
955 // registers cannot be used even for integer operations.
956 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
957 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
958 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
959 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
961 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
962 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
963 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
964 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
965 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
966 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
967 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
969 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
970 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
972 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
973 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
974 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
975 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
976 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
977 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
978 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
979 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
980 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
981 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
982 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
985 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
986 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
987 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
990 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
995 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to custom lower non-power-of-2 vectors
999 if (!isPowerOf2_32(VT.getVectorNumElements()))
1001 // Do not attempt to custom lower non-128-bit vectors
1002 if (!VT.is128BitVector())
1004 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1005 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1006 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1009 // We support custom legalizing of sext and anyext loads for specific
1010 // memory vector types which we can load as a scalar (or sequence of
1011 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1012 // loads these must work with a single scalar load.
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1015 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1024 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1026 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1027 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1028 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1030 if (Subtarget->is64Bit()) {
1031 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1032 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1035 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1036 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1037 MVT VT = (MVT::SimpleValueType)i;
1039 // Do not attempt to promote non-128-bit vectors
1040 if (!VT.is128BitVector())
1043 setOperationAction(ISD::AND, VT, Promote);
1044 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1045 setOperationAction(ISD::OR, VT, Promote);
1046 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1047 setOperationAction(ISD::XOR, VT, Promote);
1048 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1049 setOperationAction(ISD::LOAD, VT, Promote);
1050 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1051 setOperationAction(ISD::SELECT, VT, Promote);
1052 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1055 // Custom lower v2i64 and v2f64 selects.
1056 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1058 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1059 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1061 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1065 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1066 // As there is no 64-bit GPR available, we need build a special custom
1067 // sequence to convert from v2i32 to v2f32.
1068 if (!Subtarget->is64Bit())
1069 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1072 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1074 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1076 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1078 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1081 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1082 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1087 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1088 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1089 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1090 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1104 // FIXME: Do we need to handle scalar-to-vector here?
1105 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1107 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1112 // There is no BLENDI for byte vectors. We don't need to custom lower
1113 // some vselects for now.
1114 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1116 // SSE41 brings specific instructions for doing vector sign extend even in
1117 // cases where we don't have SRA.
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1120 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1122 // i8 and i16 vectors are custom because the source register and source
1123 // source memory operand types are not the same width. f32 vectors are
1124 // custom since the immediate controlling the insert encodes additional
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1136 // FIXME: these should be Legal, but that's only for the case where
1137 // the index is constant. For now custom expand to deal with that.
1138 if (Subtarget->is64Bit()) {
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1144 if (Subtarget->hasSSE2()) {
1145 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1146 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1148 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1154 // In the customized shift lowering, the legal cases in AVX2 will be
1156 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1157 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1159 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1165 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1166 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1173 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1175 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1177 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1190 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1201 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1203 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1204 // even though v8i16 is a legal type.
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1207 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1210 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1211 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1214 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1218 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1219 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1221 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1234 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1252 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1254 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1255 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1259 setOperationAction(ISD::FMA, MVT::f32, Legal);
1260 setOperationAction(ISD::FMA, MVT::f64, Legal);
1263 if (Subtarget->hasInt256()) {
1264 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1265 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1266 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1267 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1269 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1270 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1271 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1272 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1274 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1275 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1276 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1277 // Don't lower v32i8 because there is no 128-bit byte mul
1279 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1281 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1282 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1284 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1285 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1287 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1288 // when we have a 256bit-wide blend with immediate.
1289 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1292 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1293 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1294 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1296 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1297 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1299 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1301 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1302 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1303 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1304 // Don't lower v32i8 because there is no 128-bit byte mul
1307 // In the customized shift lowering, the legal cases in AVX2 will be
1309 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1312 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1315 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1317 // Custom lower several nodes for 256-bit types.
1318 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1319 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1320 MVT VT = (MVT::SimpleValueType)i;
1322 // Extract subvector is special because the value type
1323 // (result) is 128-bit but the source is 256-bit wide.
1324 if (VT.is128BitVector()) {
1325 if (VT.getScalarSizeInBits() >= 32) {
1326 setOperationAction(ISD::MLOAD, VT, Custom);
1327 setOperationAction(ISD::MSTORE, VT, Custom);
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1340 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1341 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1342 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1343 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1344 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1345 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1348 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1349 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1350 MVT VT = (MVT::SimpleValueType)i;
1352 // Do not attempt to promote non-256-bit vectors
1353 if (!VT.is256BitVector())
1356 setOperationAction(ISD::AND, VT, Promote);
1357 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1358 setOperationAction(ISD::OR, VT, Promote);
1359 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1360 setOperationAction(ISD::XOR, VT, Promote);
1361 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1362 setOperationAction(ISD::LOAD, VT, Promote);
1363 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1364 setOperationAction(ISD::SELECT, VT, Promote);
1365 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1369 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1370 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1371 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1372 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1373 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1375 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1376 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1377 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1379 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1380 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1381 setOperationAction(ISD::XOR, MVT::i1, Legal);
1382 setOperationAction(ISD::OR, MVT::i1, Legal);
1383 setOperationAction(ISD::AND, MVT::i1, Legal);
1384 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1387 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1388 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1389 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1391 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1394 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1395 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1396 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1398 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1402 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1403 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1404 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1405 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1411 if (Subtarget->is64Bit()) {
1412 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1415 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1417 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1418 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1419 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1421 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1425 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1426 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1427 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1428 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1429 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1430 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1432 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1433 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1434 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1435 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1436 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1437 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1438 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1439 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1443 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1444 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1450 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1451 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1453 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1454 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1456 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1458 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1459 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1460 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1461 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1462 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1463 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1465 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1468 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1469 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1471 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1472 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1474 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1476 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1477 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1479 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1480 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1482 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1483 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1485 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1486 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1487 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1488 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1489 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1490 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1492 if (Subtarget->hasCDI()) {
1493 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1494 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1497 // Custom lower several nodes.
1498 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1499 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1500 MVT VT = (MVT::SimpleValueType)i;
1502 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1503 // Extract subvector is special because the value type
1504 // (result) is 256/128-bit but the source is 512-bit wide.
1505 if (VT.is128BitVector() || VT.is256BitVector()) {
1506 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::MLOAD, VT, Legal);
1509 setOperationAction(ISD::MSTORE, VT, Legal);
1512 if (VT.getVectorElementType() == MVT::i1)
1513 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1515 // Do not attempt to custom lower other non-512-bit vectors
1516 if (!VT.is512BitVector())
1519 if ( EltSize >= 32) {
1520 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1521 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1522 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1523 setOperationAction(ISD::VSELECT, VT, Legal);
1524 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1525 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1526 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1527 setOperationAction(ISD::MLOAD, VT, Legal);
1528 setOperationAction(ISD::MSTORE, VT, Legal);
1531 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1532 MVT VT = (MVT::SimpleValueType)i;
1534 // Do not attempt to promote non-256-bit vectors
1535 if (!VT.is512BitVector())
1538 setOperationAction(ISD::SELECT, VT, Promote);
1539 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1543 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1544 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1545 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1547 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1548 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1550 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1551 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1552 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1553 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1555 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1556 const MVT VT = (MVT::SimpleValueType)i;
1558 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1560 // Do not attempt to promote non-256-bit vectors
1561 if (!VT.is512BitVector())
1564 if ( EltSize < 32) {
1565 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1566 setOperationAction(ISD::VSELECT, VT, Legal);
1571 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1572 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1573 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1575 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1576 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1577 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1580 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1581 // of this type with custom code.
1582 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1583 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1584 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1588 // We want to custom lower some of our intrinsics.
1589 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1590 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1591 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1592 if (!Subtarget->is64Bit())
1593 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1595 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1596 // handle type legalization for these operations here.
1598 // FIXME: We really should do custom legalization for addition and
1599 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1600 // than generic legalization for 64-bit multiplication-with-overflow, though.
1601 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1602 // Add/Sub/Mul with overflow operations are custom lowered.
1604 setOperationAction(ISD::SADDO, VT, Custom);
1605 setOperationAction(ISD::UADDO, VT, Custom);
1606 setOperationAction(ISD::SSUBO, VT, Custom);
1607 setOperationAction(ISD::USUBO, VT, Custom);
1608 setOperationAction(ISD::SMULO, VT, Custom);
1609 setOperationAction(ISD::UMULO, VT, Custom);
1613 if (!Subtarget->is64Bit()) {
1614 // These libcalls are not available in 32-bit.
1615 setLibcallName(RTLIB::SHL_I128, nullptr);
1616 setLibcallName(RTLIB::SRL_I128, nullptr);
1617 setLibcallName(RTLIB::SRA_I128, nullptr);
1620 // Combine sin / cos into one node or libcall if possible.
1621 if (Subtarget->hasSinCos()) {
1622 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1623 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1624 if (Subtarget->isTargetDarwin()) {
1625 // For MacOSX, we don't want to the normal expansion of a libcall to
1626 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1628 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1629 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1633 if (Subtarget->isTargetWin64()) {
1634 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1635 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1636 setOperationAction(ISD::SREM, MVT::i128, Custom);
1637 setOperationAction(ISD::UREM, MVT::i128, Custom);
1638 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1639 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1642 // We have target-specific dag combine patterns for the following nodes:
1643 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1644 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1645 setTargetDAGCombine(ISD::VSELECT);
1646 setTargetDAGCombine(ISD::SELECT);
1647 setTargetDAGCombine(ISD::SHL);
1648 setTargetDAGCombine(ISD::SRA);
1649 setTargetDAGCombine(ISD::SRL);
1650 setTargetDAGCombine(ISD::OR);
1651 setTargetDAGCombine(ISD::AND);
1652 setTargetDAGCombine(ISD::ADD);
1653 setTargetDAGCombine(ISD::FADD);
1654 setTargetDAGCombine(ISD::FSUB);
1655 setTargetDAGCombine(ISD::FMA);
1656 setTargetDAGCombine(ISD::SUB);
1657 setTargetDAGCombine(ISD::LOAD);
1658 setTargetDAGCombine(ISD::STORE);
1659 setTargetDAGCombine(ISD::ZERO_EXTEND);
1660 setTargetDAGCombine(ISD::ANY_EXTEND);
1661 setTargetDAGCombine(ISD::SIGN_EXTEND);
1662 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1663 setTargetDAGCombine(ISD::TRUNCATE);
1664 setTargetDAGCombine(ISD::SINT_TO_FP);
1665 setTargetDAGCombine(ISD::SETCC);
1666 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1667 setTargetDAGCombine(ISD::BUILD_VECTOR);
1668 if (Subtarget->is64Bit())
1669 setTargetDAGCombine(ISD::MUL);
1670 setTargetDAGCombine(ISD::XOR);
1672 computeRegisterProperties();
1674 // On Darwin, -Os means optimize for size without hurting performance,
1675 // do not reduce the limit.
1676 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1677 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1678 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1679 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1680 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1681 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1682 setPrefLoopAlignment(4); // 2^4 bytes.
1684 // Predictable cmov don't hurt on atom because it's in-order.
1685 PredictableSelectIsExpensive = !Subtarget->isAtom();
1687 setPrefFunctionAlignment(4); // 2^4 bytes.
1689 verifyIntrinsicTables();
1692 // This has so far only been implemented for 64-bit MachO.
1693 bool X86TargetLowering::useLoadStackGuardNode() const {
1694 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1695 Subtarget->is64Bit();
1698 TargetLoweringBase::LegalizeTypeAction
1699 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1700 if (ExperimentalVectorWideningLegalization &&
1701 VT.getVectorNumElements() != 1 &&
1702 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1703 return TypeWidenVector;
1705 return TargetLoweringBase::getPreferredVectorAction(VT);
1708 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1710 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1712 const unsigned NumElts = VT.getVectorNumElements();
1713 const EVT EltVT = VT.getVectorElementType();
1714 if (VT.is512BitVector()) {
1715 if (Subtarget->hasAVX512())
1716 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1717 EltVT == MVT::f32 || EltVT == MVT::f64)
1719 case 8: return MVT::v8i1;
1720 case 16: return MVT::v16i1;
1722 if (Subtarget->hasBWI())
1723 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1725 case 32: return MVT::v32i1;
1726 case 64: return MVT::v64i1;
1730 if (VT.is256BitVector() || VT.is128BitVector()) {
1731 if (Subtarget->hasVLX())
1732 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1733 EltVT == MVT::f32 || EltVT == MVT::f64)
1735 case 2: return MVT::v2i1;
1736 case 4: return MVT::v4i1;
1737 case 8: return MVT::v8i1;
1739 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1740 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1742 case 8: return MVT::v8i1;
1743 case 16: return MVT::v16i1;
1744 case 32: return MVT::v32i1;
1748 return VT.changeVectorElementTypeToInteger();
1751 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1752 /// the desired ByVal argument alignment.
1753 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1756 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1757 if (VTy->getBitWidth() == 128)
1759 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1760 unsigned EltAlign = 0;
1761 getMaxByValAlign(ATy->getElementType(), EltAlign);
1762 if (EltAlign > MaxAlign)
1763 MaxAlign = EltAlign;
1764 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1765 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1766 unsigned EltAlign = 0;
1767 getMaxByValAlign(STy->getElementType(i), EltAlign);
1768 if (EltAlign > MaxAlign)
1769 MaxAlign = EltAlign;
1776 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1777 /// function arguments in the caller parameter area. For X86, aggregates
1778 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1779 /// are at 4-byte boundaries.
1780 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1781 if (Subtarget->is64Bit()) {
1782 // Max of 8 and alignment of type.
1783 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1790 if (Subtarget->hasSSE1())
1791 getMaxByValAlign(Ty, Align);
1795 /// getOptimalMemOpType - Returns the target specific optimal type for load
1796 /// and store operations as a result of memset, memcpy, and memmove
1797 /// lowering. If DstAlign is zero that means it's safe to destination
1798 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1799 /// means there isn't a need to check it against alignment requirement,
1800 /// probably because the source does not need to be loaded. If 'IsMemset' is
1801 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1802 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1803 /// source is constant so it does not need to be loaded.
1804 /// It returns EVT::Other if the type should be determined using generic
1805 /// target-independent logic.
1807 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1808 unsigned DstAlign, unsigned SrcAlign,
1809 bool IsMemset, bool ZeroMemset,
1811 MachineFunction &MF) const {
1812 const Function *F = MF.getFunction();
1813 if ((!IsMemset || ZeroMemset) &&
1814 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1815 Attribute::NoImplicitFloat)) {
1817 (Subtarget->isUnalignedMemAccessFast() ||
1818 ((DstAlign == 0 || DstAlign >= 16) &&
1819 (SrcAlign == 0 || SrcAlign >= 16)))) {
1821 if (Subtarget->hasInt256())
1823 if (Subtarget->hasFp256())
1826 if (Subtarget->hasSSE2())
1828 if (Subtarget->hasSSE1())
1830 } else if (!MemcpyStrSrc && Size >= 8 &&
1831 !Subtarget->is64Bit() &&
1832 Subtarget->hasSSE2()) {
1833 // Do not use f64 to lower memcpy if source is string constant. It's
1834 // better to use i32 to avoid the loads.
1838 if (Subtarget->is64Bit() && Size >= 8)
1843 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1845 return X86ScalarSSEf32;
1846 else if (VT == MVT::f64)
1847 return X86ScalarSSEf64;
1852 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1857 *Fast = Subtarget->isUnalignedMemAccessFast();
1861 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1862 /// current function. The returned value is a member of the
1863 /// MachineJumpTableInfo::JTEntryKind enum.
1864 unsigned X86TargetLowering::getJumpTableEncoding() const {
1865 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1867 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT())
1869 return MachineJumpTableInfo::EK_Custom32;
1871 // Otherwise, use the normal jump table encoding heuristics.
1872 return TargetLowering::getJumpTableEncoding();
1876 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1877 const MachineBasicBlock *MBB,
1878 unsigned uid,MCContext &Ctx) const{
1879 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1880 Subtarget->isPICStyleGOT());
1881 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1883 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1884 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1887 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1889 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1890 SelectionDAG &DAG) const {
1891 if (!Subtarget->is64Bit())
1892 // This doesn't have SDLoc associated with it, but is not really the
1893 // same as a Register.
1894 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1898 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1899 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1901 const MCExpr *X86TargetLowering::
1902 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1903 MCContext &Ctx) const {
1904 // X86-64 uses RIP relative addressing based on the jump table label.
1905 if (Subtarget->isPICStyleRIPRel())
1906 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1908 // Otherwise, the reference is relative to the PIC base.
1909 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1912 // FIXME: Why this routine is here? Move to RegInfo!
1913 std::pair<const TargetRegisterClass*, uint8_t>
1914 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1915 const TargetRegisterClass *RRC = nullptr;
1917 switch (VT.SimpleTy) {
1919 return TargetLowering::findRepresentativeClass(VT);
1920 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1921 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1924 RRC = &X86::VR64RegClass;
1926 case MVT::f32: case MVT::f64:
1927 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1928 case MVT::v4f32: case MVT::v2f64:
1929 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1931 RRC = &X86::VR128RegClass;
1934 return std::make_pair(RRC, Cost);
1937 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1938 unsigned &Offset) const {
1939 if (!Subtarget->isTargetLinux())
1942 if (Subtarget->is64Bit()) {
1943 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1945 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1957 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1958 unsigned DestAS) const {
1959 assert(SrcAS != DestAS && "Expected different address spaces!");
1961 return SrcAS < 256 && DestAS < 256;
1964 //===----------------------------------------------------------------------===//
1965 // Return Value Calling Convention Implementation
1966 //===----------------------------------------------------------------------===//
1968 #include "X86GenCallingConv.inc"
1971 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1972 MachineFunction &MF, bool isVarArg,
1973 const SmallVectorImpl<ISD::OutputArg> &Outs,
1974 LLVMContext &Context) const {
1975 SmallVector<CCValAssign, 16> RVLocs;
1976 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1977 return CCInfo.CheckReturn(Outs, RetCC_X86);
1980 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1981 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1986 X86TargetLowering::LowerReturn(SDValue Chain,
1987 CallingConv::ID CallConv, bool isVarArg,
1988 const SmallVectorImpl<ISD::OutputArg> &Outs,
1989 const SmallVectorImpl<SDValue> &OutVals,
1990 SDLoc dl, SelectionDAG &DAG) const {
1991 MachineFunction &MF = DAG.getMachineFunction();
1992 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1994 SmallVector<CCValAssign, 16> RVLocs;
1995 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1996 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1999 SmallVector<SDValue, 6> RetOps;
2000 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2001 // Operand #1 = Bytes To Pop
2002 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2005 // Copy the result values into the output registers.
2006 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2007 CCValAssign &VA = RVLocs[i];
2008 assert(VA.isRegLoc() && "Can only return in registers!");
2009 SDValue ValToCopy = OutVals[i];
2010 EVT ValVT = ValToCopy.getValueType();
2012 // Promote values to the appropriate types
2013 if (VA.getLocInfo() == CCValAssign::SExt)
2014 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2015 else if (VA.getLocInfo() == CCValAssign::ZExt)
2016 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2017 else if (VA.getLocInfo() == CCValAssign::AExt)
2018 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2019 else if (VA.getLocInfo() == CCValAssign::BCvt)
2020 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2022 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2023 "Unexpected FP-extend for return value.");
2025 // If this is x86-64, and we disabled SSE, we can't return FP values,
2026 // or SSE or MMX vectors.
2027 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2028 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2029 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2030 report_fatal_error("SSE register return with SSE disabled");
2032 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2033 // llvm-gcc has never done it right and no one has noticed, so this
2034 // should be OK for now.
2035 if (ValVT == MVT::f64 &&
2036 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2037 report_fatal_error("SSE2 register return with SSE2 disabled");
2039 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2040 // the RET instruction and handled by the FP Stackifier.
2041 if (VA.getLocReg() == X86::FP0 ||
2042 VA.getLocReg() == X86::FP1) {
2043 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2044 // change the value to the FP stack register class.
2045 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2046 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2047 RetOps.push_back(ValToCopy);
2048 // Don't emit a copytoreg.
2052 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2053 // which is returned in RAX / RDX.
2054 if (Subtarget->is64Bit()) {
2055 if (ValVT == MVT::x86mmx) {
2056 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2057 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2058 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2060 // If we don't have SSE2 available, convert to v4f32 so the generated
2061 // register is legal.
2062 if (!Subtarget->hasSSE2())
2063 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2068 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2069 Flag = Chain.getValue(1);
2070 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2073 // The x86-64 ABIs require that for returning structs by value we copy
2074 // the sret argument into %rax/%eax (depending on ABI) for the return.
2075 // Win32 requires us to put the sret argument to %eax as well.
2076 // We saved the argument into a virtual register in the entry block,
2077 // so now we copy the value out and into %rax/%eax.
2078 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2079 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2080 MachineFunction &MF = DAG.getMachineFunction();
2081 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2082 unsigned Reg = FuncInfo->getSRetReturnReg();
2084 "SRetReturnReg should have been set in LowerFormalArguments().");
2085 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2088 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2089 X86::RAX : X86::EAX;
2090 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2091 Flag = Chain.getValue(1);
2093 // RAX/EAX now acts like a return value.
2094 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2097 RetOps[0] = Chain; // Update chain.
2099 // Add the flag if we have it.
2101 RetOps.push_back(Flag);
2103 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2106 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2107 if (N->getNumValues() != 1)
2109 if (!N->hasNUsesOfValue(1, 0))
2112 SDValue TCChain = Chain;
2113 SDNode *Copy = *N->use_begin();
2114 if (Copy->getOpcode() == ISD::CopyToReg) {
2115 // If the copy has a glue operand, we conservatively assume it isn't safe to
2116 // perform a tail call.
2117 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2119 TCChain = Copy->getOperand(0);
2120 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2123 bool HasRet = false;
2124 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2126 if (UI->getOpcode() != X86ISD::RET_FLAG)
2128 // If we are returning more than one value, we can definitely
2129 // not make a tail call see PR19530
2130 if (UI->getNumOperands() > 4)
2132 if (UI->getNumOperands() == 4 &&
2133 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2146 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2147 ISD::NodeType ExtendKind) const {
2149 // TODO: Is this also valid on 32-bit?
2150 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2151 ReturnMVT = MVT::i8;
2153 ReturnMVT = MVT::i32;
2155 EVT MinVT = getRegisterType(Context, ReturnMVT);
2156 return VT.bitsLT(MinVT) ? MinVT : VT;
2159 /// LowerCallResult - Lower the result values of a call into the
2160 /// appropriate copies out of appropriate physical registers.
2163 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2164 CallingConv::ID CallConv, bool isVarArg,
2165 const SmallVectorImpl<ISD::InputArg> &Ins,
2166 SDLoc dl, SelectionDAG &DAG,
2167 SmallVectorImpl<SDValue> &InVals) const {
2169 // Assign locations to each value returned by this call.
2170 SmallVector<CCValAssign, 16> RVLocs;
2171 bool Is64Bit = Subtarget->is64Bit();
2172 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2174 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2176 // Copy all of the result registers out of their specified physreg.
2177 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2178 CCValAssign &VA = RVLocs[i];
2179 EVT CopyVT = VA.getValVT();
2181 // If this is x86-64, and we disabled SSE, we can't return FP values
2182 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2183 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2184 report_fatal_error("SSE register return with SSE disabled");
2187 // If we prefer to use the value in xmm registers, copy it out as f80 and
2188 // use a truncate to move it from fp stack reg to xmm reg.
2189 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2190 isScalarFPTypeInSSEReg(VA.getValVT()))
2193 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2194 CopyVT, InFlag).getValue(1);
2195 SDValue Val = Chain.getValue(0);
2197 if (CopyVT != VA.getValVT())
2198 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2199 // This truncation won't change the value.
2200 DAG.getIntPtrConstant(1));
2202 InFlag = Chain.getValue(2);
2203 InVals.push_back(Val);
2209 //===----------------------------------------------------------------------===//
2210 // C & StdCall & Fast Calling Convention implementation
2211 //===----------------------------------------------------------------------===//
2212 // StdCall calling convention seems to be standard for many Windows' API
2213 // routines and around. It differs from C calling convention just a little:
2214 // callee should clean up the stack, not caller. Symbols should be also
2215 // decorated in some fancy way :) It doesn't support any vector arguments.
2216 // For info on fast calling convention see Fast Calling Convention (tail call)
2217 // implementation LowerX86_32FastCCCallTo.
2219 /// CallIsStructReturn - Determines whether a call uses struct return
2221 enum StructReturnType {
2226 static StructReturnType
2227 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2229 return NotStructReturn;
2231 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2232 if (!Flags.isSRet())
2233 return NotStructReturn;
2234 if (Flags.isInReg())
2235 return RegStructReturn;
2236 return StackStructReturn;
2239 /// ArgsAreStructReturn - Determines whether a function uses struct
2240 /// return semantics.
2241 static StructReturnType
2242 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2244 return NotStructReturn;
2246 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2247 if (!Flags.isSRet())
2248 return NotStructReturn;
2249 if (Flags.isInReg())
2250 return RegStructReturn;
2251 return StackStructReturn;
2254 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2255 /// by "Src" to address "Dst" with size and alignment information specified by
2256 /// the specific parameter attribute. The copy will be passed as a byval
2257 /// function parameter.
2259 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2260 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2262 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2264 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2265 /*isVolatile*/false, /*AlwaysInline=*/true,
2266 MachinePointerInfo(), MachinePointerInfo());
2269 /// IsTailCallConvention - Return true if the calling convention is one that
2270 /// supports tail call optimization.
2271 static bool IsTailCallConvention(CallingConv::ID CC) {
2272 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2273 CC == CallingConv::HiPE);
2276 /// \brief Return true if the calling convention is a C calling convention.
2277 static bool IsCCallConvention(CallingConv::ID CC) {
2278 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2279 CC == CallingConv::X86_64_SysV);
2282 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2283 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2287 CallingConv::ID CalleeCC = CS.getCallingConv();
2288 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2294 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2295 /// a tailcall target by changing its ABI.
2296 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2297 bool GuaranteedTailCallOpt) {
2298 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2302 X86TargetLowering::LowerMemArgument(SDValue Chain,
2303 CallingConv::ID CallConv,
2304 const SmallVectorImpl<ISD::InputArg> &Ins,
2305 SDLoc dl, SelectionDAG &DAG,
2306 const CCValAssign &VA,
2307 MachineFrameInfo *MFI,
2309 // Create the nodes corresponding to a load from this parameter slot.
2310 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2311 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2312 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2313 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2316 // If value is passed by pointer we have address passed instead of the value
2318 if (VA.getLocInfo() == CCValAssign::Indirect)
2319 ValVT = VA.getLocVT();
2321 ValVT = VA.getValVT();
2323 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2324 // changed with more analysis.
2325 // In case of tail call optimization mark all arguments mutable. Since they
2326 // could be overwritten by lowering of arguments in case of a tail call.
2327 if (Flags.isByVal()) {
2328 unsigned Bytes = Flags.getByValSize();
2329 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2330 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2331 return DAG.getFrameIndex(FI, getPointerTy());
2333 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2334 VA.getLocMemOffset(), isImmutable);
2335 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2336 return DAG.getLoad(ValVT, dl, Chain, FIN,
2337 MachinePointerInfo::getFixedStack(FI),
2338 false, false, false, 0);
2342 // FIXME: Get this from tablegen.
2343 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2344 const X86Subtarget *Subtarget) {
2345 assert(Subtarget->is64Bit());
2347 if (Subtarget->isCallingConvWin64(CallConv)) {
2348 static const MCPhysReg GPR64ArgRegsWin64[] = {
2349 X86::RCX, X86::RDX, X86::R8, X86::R9
2351 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2354 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2355 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2357 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2360 // FIXME: Get this from tablegen.
2361 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2362 CallingConv::ID CallConv,
2363 const X86Subtarget *Subtarget) {
2364 assert(Subtarget->is64Bit());
2365 if (Subtarget->isCallingConvWin64(CallConv)) {
2366 // The XMM registers which might contain var arg parameters are shadowed
2367 // in their paired GPR. So we only need to save the GPR to their home
2369 // TODO: __vectorcall will change this.
2373 const Function *Fn = MF.getFunction();
2374 bool NoImplicitFloatOps = Fn->getAttributes().
2375 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2376 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2377 "SSE register cannot be used when SSE is disabled!");
2378 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2379 !Subtarget->hasSSE1())
2380 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2384 static const MCPhysReg XMMArgRegs64Bit[] = {
2385 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2386 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2388 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2392 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2393 CallingConv::ID CallConv,
2395 const SmallVectorImpl<ISD::InputArg> &Ins,
2398 SmallVectorImpl<SDValue> &InVals)
2400 MachineFunction &MF = DAG.getMachineFunction();
2401 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2403 const Function* Fn = MF.getFunction();
2404 if (Fn->hasExternalLinkage() &&
2405 Subtarget->isTargetCygMing() &&
2406 Fn->getName() == "main")
2407 FuncInfo->setForceFramePointer(true);
2409 MachineFrameInfo *MFI = MF.getFrameInfo();
2410 bool Is64Bit = Subtarget->is64Bit();
2411 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2413 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2414 "Var args not supported with calling convention fastcc, ghc or hipe");
2416 // Assign locations to all of the incoming arguments.
2417 SmallVector<CCValAssign, 16> ArgLocs;
2418 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2420 // Allocate shadow area for Win64
2422 CCInfo.AllocateStack(32, 8);
2424 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2426 unsigned LastVal = ~0U;
2428 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2429 CCValAssign &VA = ArgLocs[i];
2430 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2432 assert(VA.getValNo() != LastVal &&
2433 "Don't support value assigned to multiple locs yet");
2435 LastVal = VA.getValNo();
2437 if (VA.isRegLoc()) {
2438 EVT RegVT = VA.getLocVT();
2439 const TargetRegisterClass *RC;
2440 if (RegVT == MVT::i32)
2441 RC = &X86::GR32RegClass;
2442 else if (Is64Bit && RegVT == MVT::i64)
2443 RC = &X86::GR64RegClass;
2444 else if (RegVT == MVT::f32)
2445 RC = &X86::FR32RegClass;
2446 else if (RegVT == MVT::f64)
2447 RC = &X86::FR64RegClass;
2448 else if (RegVT.is512BitVector())
2449 RC = &X86::VR512RegClass;
2450 else if (RegVT.is256BitVector())
2451 RC = &X86::VR256RegClass;
2452 else if (RegVT.is128BitVector())
2453 RC = &X86::VR128RegClass;
2454 else if (RegVT == MVT::x86mmx)
2455 RC = &X86::VR64RegClass;
2456 else if (RegVT == MVT::i1)
2457 RC = &X86::VK1RegClass;
2458 else if (RegVT == MVT::v8i1)
2459 RC = &X86::VK8RegClass;
2460 else if (RegVT == MVT::v16i1)
2461 RC = &X86::VK16RegClass;
2462 else if (RegVT == MVT::v32i1)
2463 RC = &X86::VK32RegClass;
2464 else if (RegVT == MVT::v64i1)
2465 RC = &X86::VK64RegClass;
2467 llvm_unreachable("Unknown argument type!");
2469 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2470 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2472 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2473 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2475 if (VA.getLocInfo() == CCValAssign::SExt)
2476 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2477 DAG.getValueType(VA.getValVT()));
2478 else if (VA.getLocInfo() == CCValAssign::ZExt)
2479 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2480 DAG.getValueType(VA.getValVT()));
2481 else if (VA.getLocInfo() == CCValAssign::BCvt)
2482 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2484 if (VA.isExtInLoc()) {
2485 // Handle MMX values passed in XMM regs.
2486 if (RegVT.isVector())
2487 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2489 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2492 assert(VA.isMemLoc());
2493 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2496 // If value is passed via pointer - do a load.
2497 if (VA.getLocInfo() == CCValAssign::Indirect)
2498 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2499 MachinePointerInfo(), false, false, false, 0);
2501 InVals.push_back(ArgValue);
2504 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2505 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2506 // The x86-64 ABIs require that for returning structs by value we copy
2507 // the sret argument into %rax/%eax (depending on ABI) for the return.
2508 // Win32 requires us to put the sret argument to %eax as well.
2509 // Save the argument into a virtual register so that we can access it
2510 // from the return points.
2511 if (Ins[i].Flags.isSRet()) {
2512 unsigned Reg = FuncInfo->getSRetReturnReg();
2514 MVT PtrTy = getPointerTy();
2515 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2516 FuncInfo->setSRetReturnReg(Reg);
2518 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2519 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2525 unsigned StackSize = CCInfo.getNextStackOffset();
2526 // Align stack specially for tail calls.
2527 if (FuncIsMadeTailCallSafe(CallConv,
2528 MF.getTarget().Options.GuaranteedTailCallOpt))
2529 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2531 // If the function takes variable number of arguments, make a frame index for
2532 // the start of the first vararg value... for expansion of llvm.va_start. We
2533 // can skip this if there are no va_start calls.
2534 if (MFI->hasVAStart() &&
2535 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2536 CallConv != CallingConv::X86_ThisCall))) {
2537 FuncInfo->setVarArgsFrameIndex(
2538 MFI->CreateFixedObject(1, StackSize, true));
2541 // 64-bit calling conventions support varargs and register parameters, so we
2542 // have to do extra work to spill them in the prologue or forward them to
2544 if (Is64Bit && isVarArg &&
2545 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2546 // Find the first unallocated argument registers.
2547 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2548 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2549 unsigned NumIntRegs =
2550 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2551 unsigned NumXMMRegs =
2552 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2553 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2554 "SSE register cannot be used when SSE is disabled!");
2556 // Gather all the live in physical registers.
2557 SmallVector<SDValue, 6> LiveGPRs;
2558 SmallVector<SDValue, 8> LiveXMMRegs;
2560 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2561 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2563 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2565 if (!ArgXMMs.empty()) {
2566 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2567 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2568 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2569 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2570 LiveXMMRegs.push_back(
2571 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2575 // Store them to the va_list returned by va_start.
2576 if (MFI->hasVAStart()) {
2578 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2579 // Get to the caller-allocated home save location. Add 8 to account
2580 // for the return address.
2581 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2582 FuncInfo->setRegSaveFrameIndex(
2583 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2584 // Fixup to set vararg frame on shadow area (4 x i64).
2586 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2588 // For X86-64, if there are vararg parameters that are passed via
2589 // registers, then we must store them to their spots on the stack so
2590 // they may be loaded by deferencing the result of va_next.
2591 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2592 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2593 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2594 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2597 // Store the integer parameter registers.
2598 SmallVector<SDValue, 8> MemOps;
2599 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2601 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2602 for (SDValue Val : LiveGPRs) {
2603 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2604 DAG.getIntPtrConstant(Offset));
2606 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2607 MachinePointerInfo::getFixedStack(
2608 FuncInfo->getRegSaveFrameIndex(), Offset),
2610 MemOps.push_back(Store);
2614 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2615 // Now store the XMM (fp + vector) parameter registers.
2616 SmallVector<SDValue, 12> SaveXMMOps;
2617 SaveXMMOps.push_back(Chain);
2618 SaveXMMOps.push_back(ALVal);
2619 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2620 FuncInfo->getRegSaveFrameIndex()));
2621 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2622 FuncInfo->getVarArgsFPOffset()));
2623 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2625 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2626 MVT::Other, SaveXMMOps));
2629 if (!MemOps.empty())
2630 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2632 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2633 // to the liveout set on a musttail call.
2634 assert(MFI->hasMustTailInVarArgFunc());
2635 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2636 typedef X86MachineFunctionInfo::Forward Forward;
2638 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2640 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2641 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2642 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2645 if (!ArgXMMs.empty()) {
2647 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2648 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2649 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2651 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2653 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2654 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2656 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2662 // Some CCs need callee pop.
2663 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2664 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2665 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2667 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2668 // If this is an sret function, the return should pop the hidden pointer.
2669 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2670 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2671 argsAreStructReturn(Ins) == StackStructReturn)
2672 FuncInfo->setBytesToPopOnReturn(4);
2676 // RegSaveFrameIndex is X86-64 only.
2677 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2678 if (CallConv == CallingConv::X86_FastCall ||
2679 CallConv == CallingConv::X86_ThisCall)
2680 // fastcc functions can't have varargs.
2681 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2684 FuncInfo->setArgumentStackSize(StackSize);
2690 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2691 SDValue StackPtr, SDValue Arg,
2692 SDLoc dl, SelectionDAG &DAG,
2693 const CCValAssign &VA,
2694 ISD::ArgFlagsTy Flags) const {
2695 unsigned LocMemOffset = VA.getLocMemOffset();
2696 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2697 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2698 if (Flags.isByVal())
2699 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2701 return DAG.getStore(Chain, dl, Arg, PtrOff,
2702 MachinePointerInfo::getStack(LocMemOffset),
2706 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2707 /// optimization is performed and it is required.
2709 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2710 SDValue &OutRetAddr, SDValue Chain,
2711 bool IsTailCall, bool Is64Bit,
2712 int FPDiff, SDLoc dl) const {
2713 // Adjust the Return address stack slot.
2714 EVT VT = getPointerTy();
2715 OutRetAddr = getReturnAddressFrameIndex(DAG);
2717 // Load the "old" Return address.
2718 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2719 false, false, false, 0);
2720 return SDValue(OutRetAddr.getNode(), 1);
2723 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2724 /// optimization is performed and it is required (FPDiff!=0).
2725 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2726 SDValue Chain, SDValue RetAddrFrIdx,
2727 EVT PtrVT, unsigned SlotSize,
2728 int FPDiff, SDLoc dl) {
2729 // Store the return address to the appropriate stack slot.
2730 if (!FPDiff) return Chain;
2731 // Calculate the new stack slot for the return address.
2732 int NewReturnAddrFI =
2733 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2735 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2736 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2737 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2743 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2744 SmallVectorImpl<SDValue> &InVals) const {
2745 SelectionDAG &DAG = CLI.DAG;
2747 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2748 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2749 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2750 SDValue Chain = CLI.Chain;
2751 SDValue Callee = CLI.Callee;
2752 CallingConv::ID CallConv = CLI.CallConv;
2753 bool &isTailCall = CLI.IsTailCall;
2754 bool isVarArg = CLI.IsVarArg;
2756 MachineFunction &MF = DAG.getMachineFunction();
2757 bool Is64Bit = Subtarget->is64Bit();
2758 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2759 StructReturnType SR = callIsStructReturn(Outs);
2760 bool IsSibcall = false;
2761 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2763 if (MF.getTarget().Options.DisableTailCalls)
2766 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2768 // Force this to be a tail call. The verifier rules are enough to ensure
2769 // that we can lower this successfully without moving the return address
2772 } else if (isTailCall) {
2773 // Check if it's really possible to do a tail call.
2774 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2775 isVarArg, SR != NotStructReturn,
2776 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2777 Outs, OutVals, Ins, DAG);
2779 // Sibcalls are automatically detected tailcalls which do not require
2781 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2788 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2789 "Var args not supported with calling convention fastcc, ghc or hipe");
2791 // Analyze operands of the call, assigning locations to each operand.
2792 SmallVector<CCValAssign, 16> ArgLocs;
2793 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2795 // Allocate shadow area for Win64
2797 CCInfo.AllocateStack(32, 8);
2799 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2801 // Get a count of how many bytes are to be pushed on the stack.
2802 unsigned NumBytes = CCInfo.getNextStackOffset();
2804 // This is a sibcall. The memory operands are available in caller's
2805 // own caller's stack.
2807 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2808 IsTailCallConvention(CallConv))
2809 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2812 if (isTailCall && !IsSibcall && !IsMustTail) {
2813 // Lower arguments at fp - stackoffset + fpdiff.
2814 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2816 FPDiff = NumBytesCallerPushed - NumBytes;
2818 // Set the delta of movement of the returnaddr stackslot.
2819 // But only set if delta is greater than previous delta.
2820 if (FPDiff < X86Info->getTCReturnAddrDelta())
2821 X86Info->setTCReturnAddrDelta(FPDiff);
2824 unsigned NumBytesToPush = NumBytes;
2825 unsigned NumBytesToPop = NumBytes;
2827 // If we have an inalloca argument, all stack space has already been allocated
2828 // for us and be right at the top of the stack. We don't support multiple
2829 // arguments passed in memory when using inalloca.
2830 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2832 if (!ArgLocs.back().isMemLoc())
2833 report_fatal_error("cannot use inalloca attribute on a register "
2835 if (ArgLocs.back().getLocMemOffset() != 0)
2836 report_fatal_error("any parameter with the inalloca attribute must be "
2837 "the only memory argument");
2841 Chain = DAG.getCALLSEQ_START(
2842 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2844 SDValue RetAddrFrIdx;
2845 // Load return address for tail calls.
2846 if (isTailCall && FPDiff)
2847 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2848 Is64Bit, FPDiff, dl);
2850 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2851 SmallVector<SDValue, 8> MemOpChains;
2854 // Walk the register/memloc assignments, inserting copies/loads. In the case
2855 // of tail call optimization arguments are handle later.
2856 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2857 DAG.getSubtarget().getRegisterInfo());
2858 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2859 // Skip inalloca arguments, they have already been written.
2860 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2861 if (Flags.isInAlloca())
2864 CCValAssign &VA = ArgLocs[i];
2865 EVT RegVT = VA.getLocVT();
2866 SDValue Arg = OutVals[i];
2867 bool isByVal = Flags.isByVal();
2869 // Promote the value if needed.
2870 switch (VA.getLocInfo()) {
2871 default: llvm_unreachable("Unknown loc info!");
2872 case CCValAssign::Full: break;
2873 case CCValAssign::SExt:
2874 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::ZExt:
2877 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2879 case CCValAssign::AExt:
2880 if (RegVT.is128BitVector()) {
2881 // Special case: passing MMX values in XMM registers.
2882 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2883 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2884 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2886 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2888 case CCValAssign::BCvt:
2889 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2891 case CCValAssign::Indirect: {
2892 // Store the argument.
2893 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2894 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2895 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2896 MachinePointerInfo::getFixedStack(FI),
2903 if (VA.isRegLoc()) {
2904 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2905 if (isVarArg && IsWin64) {
2906 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2907 // shadow reg if callee is a varargs function.
2908 unsigned ShadowReg = 0;
2909 switch (VA.getLocReg()) {
2910 case X86::XMM0: ShadowReg = X86::RCX; break;
2911 case X86::XMM1: ShadowReg = X86::RDX; break;
2912 case X86::XMM2: ShadowReg = X86::R8; break;
2913 case X86::XMM3: ShadowReg = X86::R9; break;
2916 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2918 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2919 assert(VA.isMemLoc());
2920 if (!StackPtr.getNode())
2921 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2923 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2924 dl, DAG, VA, Flags));
2928 if (!MemOpChains.empty())
2929 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2931 if (Subtarget->isPICStyleGOT()) {
2932 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2935 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2936 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2938 // If we are tail calling and generating PIC/GOT style code load the
2939 // address of the callee into ECX. The value in ecx is used as target of
2940 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2941 // for tail calls on PIC/GOT architectures. Normally we would just put the
2942 // address of GOT into ebx and then call target@PLT. But for tail calls
2943 // ebx would be restored (since ebx is callee saved) before jumping to the
2946 // Note: The actual moving to ECX is done further down.
2947 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2948 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2949 !G->getGlobal()->hasProtectedVisibility())
2950 Callee = LowerGlobalAddress(Callee, DAG);
2951 else if (isa<ExternalSymbolSDNode>(Callee))
2952 Callee = LowerExternalSymbol(Callee, DAG);
2956 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2957 // From AMD64 ABI document:
2958 // For calls that may call functions that use varargs or stdargs
2959 // (prototype-less calls or calls to functions containing ellipsis (...) in
2960 // the declaration) %al is used as hidden argument to specify the number
2961 // of SSE registers used. The contents of %al do not need to match exactly
2962 // the number of registers, but must be an ubound on the number of SSE
2963 // registers used and is in the range 0 - 8 inclusive.
2965 // Count the number of XMM registers allocated.
2966 static const MCPhysReg XMMArgRegs[] = {
2967 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2968 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2970 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2971 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2972 && "SSE registers cannot be used when SSE is disabled");
2974 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2975 DAG.getConstant(NumXMMRegs, MVT::i8)));
2978 if (Is64Bit && isVarArg && IsMustTail) {
2979 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2980 for (const auto &F : Forwards) {
2981 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2982 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2986 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2987 // don't need this because the eligibility check rejects calls that require
2988 // shuffling arguments passed in memory.
2989 if (!IsSibcall && isTailCall) {
2990 // Force all the incoming stack arguments to be loaded from the stack
2991 // before any new outgoing arguments are stored to the stack, because the
2992 // outgoing stack slots may alias the incoming argument stack slots, and
2993 // the alias isn't otherwise explicit. This is slightly more conservative
2994 // than necessary, because it means that each store effectively depends
2995 // on every argument instead of just those arguments it would clobber.
2996 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2998 SmallVector<SDValue, 8> MemOpChains2;
3001 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3002 CCValAssign &VA = ArgLocs[i];
3005 assert(VA.isMemLoc());
3006 SDValue Arg = OutVals[i];
3007 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3008 // Skip inalloca arguments. They don't require any work.
3009 if (Flags.isInAlloca())
3011 // Create frame index.
3012 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3013 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3014 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3015 FIN = DAG.getFrameIndex(FI, getPointerTy());
3017 if (Flags.isByVal()) {
3018 // Copy relative to framepointer.
3019 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3020 if (!StackPtr.getNode())
3021 StackPtr = DAG.getCopyFromReg(Chain, dl,
3022 RegInfo->getStackRegister(),
3024 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3026 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3030 // Store relative to framepointer.
3031 MemOpChains2.push_back(
3032 DAG.getStore(ArgChain, dl, Arg, FIN,
3033 MachinePointerInfo::getFixedStack(FI),
3038 if (!MemOpChains2.empty())
3039 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3041 // Store the return address to the appropriate stack slot.
3042 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3043 getPointerTy(), RegInfo->getSlotSize(),
3047 // Build a sequence of copy-to-reg nodes chained together with token chain
3048 // and flag operands which copy the outgoing args into registers.
3050 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3051 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3052 RegsToPass[i].second, InFlag);
3053 InFlag = Chain.getValue(1);
3056 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3057 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3058 // In the 64-bit large code model, we have to make all calls
3059 // through a register, since the call instruction's 32-bit
3060 // pc-relative offset may not be large enough to hold the whole
3062 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3063 // If the callee is a GlobalAddress node (quite common, every direct call
3064 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3067 // We should use extra load for direct calls to dllimported functions in
3069 const GlobalValue *GV = G->getGlobal();
3070 if (!GV->hasDLLImportStorageClass()) {
3071 unsigned char OpFlags = 0;
3072 bool ExtraLoad = false;
3073 unsigned WrapperKind = ISD::DELETED_NODE;
3075 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3076 // external symbols most go through the PLT in PIC mode. If the symbol
3077 // has hidden or protected visibility, or if it is static or local, then
3078 // we don't need to use the PLT - we can directly call it.
3079 if (Subtarget->isTargetELF() &&
3080 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3081 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3082 OpFlags = X86II::MO_PLT;
3083 } else if (Subtarget->isPICStyleStubAny() &&
3084 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3085 (!Subtarget->getTargetTriple().isMacOSX() ||
3086 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3087 // PC-relative references to external symbols should go through $stub,
3088 // unless we're building with the leopard linker or later, which
3089 // automatically synthesizes these stubs.
3090 OpFlags = X86II::MO_DARWIN_STUB;
3091 } else if (Subtarget->isPICStyleRIPRel() &&
3092 isa<Function>(GV) &&
3093 cast<Function>(GV)->getAttributes().
3094 hasAttribute(AttributeSet::FunctionIndex,
3095 Attribute::NonLazyBind)) {
3096 // If the function is marked as non-lazy, generate an indirect call
3097 // which loads from the GOT directly. This avoids runtime overhead
3098 // at the cost of eager binding (and one extra byte of encoding).
3099 OpFlags = X86II::MO_GOTPCREL;
3100 WrapperKind = X86ISD::WrapperRIP;
3104 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3105 G->getOffset(), OpFlags);
3107 // Add a wrapper if needed.
3108 if (WrapperKind != ISD::DELETED_NODE)
3109 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3110 // Add extra indirection if needed.
3112 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3113 MachinePointerInfo::getGOT(),
3114 false, false, false, 0);
3116 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3117 unsigned char OpFlags = 0;
3119 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3120 // external symbols should go through the PLT.
3121 if (Subtarget->isTargetELF() &&
3122 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3123 OpFlags = X86II::MO_PLT;
3124 } else if (Subtarget->isPICStyleStubAny() &&
3125 (!Subtarget->getTargetTriple().isMacOSX() ||
3126 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3127 // PC-relative references to external symbols should go through $stub,
3128 // unless we're building with the leopard linker or later, which
3129 // automatically synthesizes these stubs.
3130 OpFlags = X86II::MO_DARWIN_STUB;
3133 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3135 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3136 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3137 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3140 // Returns a chain & a flag for retval copy to use.
3141 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3142 SmallVector<SDValue, 8> Ops;
3144 if (!IsSibcall && isTailCall) {
3145 Chain = DAG.getCALLSEQ_END(Chain,
3146 DAG.getIntPtrConstant(NumBytesToPop, true),
3147 DAG.getIntPtrConstant(0, true), InFlag, dl);
3148 InFlag = Chain.getValue(1);
3151 Ops.push_back(Chain);
3152 Ops.push_back(Callee);
3155 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3157 // Add argument registers to the end of the list so that they are known live
3159 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3160 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3161 RegsToPass[i].second.getValueType()));
3163 // Add a register mask operand representing the call-preserved registers.
3164 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3165 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3166 assert(Mask && "Missing call preserved mask for calling convention");
3167 Ops.push_back(DAG.getRegisterMask(Mask));
3169 if (InFlag.getNode())
3170 Ops.push_back(InFlag);
3174 //// If this is the first return lowered for this function, add the regs
3175 //// to the liveout set for the function.
3176 // This isn't right, although it's probably harmless on x86; liveouts
3177 // should be computed from returns not tail calls. Consider a void
3178 // function making a tail call to a function returning int.
3179 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3182 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3183 InFlag = Chain.getValue(1);
3185 // Create the CALLSEQ_END node.
3186 unsigned NumBytesForCalleeToPop;
3187 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3188 DAG.getTarget().Options.GuaranteedTailCallOpt))
3189 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3190 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3191 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3192 SR == StackStructReturn)
3193 // If this is a call to a struct-return function, the callee
3194 // pops the hidden struct pointer, so we have to push it back.
3195 // This is common for Darwin/X86, Linux & Mingw32 targets.
3196 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3197 NumBytesForCalleeToPop = 4;
3199 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3201 // Returns a flag for retval copy to use.
3203 Chain = DAG.getCALLSEQ_END(Chain,
3204 DAG.getIntPtrConstant(NumBytesToPop, true),
3205 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3208 InFlag = Chain.getValue(1);
3211 // Handle result values, copying them out of physregs into vregs that we
3213 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3214 Ins, dl, DAG, InVals);
3217 //===----------------------------------------------------------------------===//
3218 // Fast Calling Convention (tail call) implementation
3219 //===----------------------------------------------------------------------===//
3221 // Like std call, callee cleans arguments, convention except that ECX is
3222 // reserved for storing the tail called function address. Only 2 registers are
3223 // free for argument passing (inreg). Tail call optimization is performed
3225 // * tailcallopt is enabled
3226 // * caller/callee are fastcc
3227 // On X86_64 architecture with GOT-style position independent code only local
3228 // (within module) calls are supported at the moment.
3229 // To keep the stack aligned according to platform abi the function
3230 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3231 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3232 // If a tail called function callee has more arguments than the caller the
3233 // caller needs to make sure that there is room to move the RETADDR to. This is
3234 // achieved by reserving an area the size of the argument delta right after the
3235 // original RETADDR, but before the saved framepointer or the spilled registers
3236 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3248 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3249 /// for a 16 byte align requirement.
3251 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3252 SelectionDAG& DAG) const {
3253 MachineFunction &MF = DAG.getMachineFunction();
3254 const TargetMachine &TM = MF.getTarget();
3255 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3256 TM.getSubtargetImpl()->getRegisterInfo());
3257 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3258 unsigned StackAlignment = TFI.getStackAlignment();
3259 uint64_t AlignMask = StackAlignment - 1;
3260 int64_t Offset = StackSize;
3261 unsigned SlotSize = RegInfo->getSlotSize();
3262 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3263 // Number smaller than 12 so just add the difference.
3264 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3266 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3267 Offset = ((~AlignMask) & Offset) + StackAlignment +
3268 (StackAlignment-SlotSize);
3273 /// MatchingStackOffset - Return true if the given stack call argument is
3274 /// already available in the same position (relatively) of the caller's
3275 /// incoming argument stack.
3277 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3278 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3279 const X86InstrInfo *TII) {
3280 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3282 if (Arg.getOpcode() == ISD::CopyFromReg) {
3283 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3284 if (!TargetRegisterInfo::isVirtualRegister(VR))
3286 MachineInstr *Def = MRI->getVRegDef(VR);
3289 if (!Flags.isByVal()) {
3290 if (!TII->isLoadFromStackSlot(Def, FI))
3293 unsigned Opcode = Def->getOpcode();
3294 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3295 Def->getOperand(1).isFI()) {
3296 FI = Def->getOperand(1).getIndex();
3297 Bytes = Flags.getByValSize();
3301 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3302 if (Flags.isByVal())
3303 // ByVal argument is passed in as a pointer but it's now being
3304 // dereferenced. e.g.
3305 // define @foo(%struct.X* %A) {
3306 // tail call @bar(%struct.X* byval %A)
3309 SDValue Ptr = Ld->getBasePtr();
3310 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3313 FI = FINode->getIndex();
3314 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3315 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3316 FI = FINode->getIndex();
3317 Bytes = Flags.getByValSize();
3321 assert(FI != INT_MAX);
3322 if (!MFI->isFixedObjectIndex(FI))
3324 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3327 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3328 /// for tail call optimization. Targets which want to do tail call
3329 /// optimization should implement this function.
3331 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3332 CallingConv::ID CalleeCC,
3334 bool isCalleeStructRet,
3335 bool isCallerStructRet,
3337 const SmallVectorImpl<ISD::OutputArg> &Outs,
3338 const SmallVectorImpl<SDValue> &OutVals,
3339 const SmallVectorImpl<ISD::InputArg> &Ins,
3340 SelectionDAG &DAG) const {
3341 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3344 // If -tailcallopt is specified, make fastcc functions tail-callable.
3345 const MachineFunction &MF = DAG.getMachineFunction();
3346 const Function *CallerF = MF.getFunction();
3348 // If the function return type is x86_fp80 and the callee return type is not,
3349 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3350 // perform a tailcall optimization here.
3351 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3354 CallingConv::ID CallerCC = CallerF->getCallingConv();
3355 bool CCMatch = CallerCC == CalleeCC;
3356 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3357 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3359 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3360 if (IsTailCallConvention(CalleeCC) && CCMatch)
3365 // Look for obvious safe cases to perform tail call optimization that do not
3366 // require ABI changes. This is what gcc calls sibcall.
3368 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3369 // emit a special epilogue.
3370 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3371 DAG.getSubtarget().getRegisterInfo());
3372 if (RegInfo->needsStackRealignment(MF))
3375 // Also avoid sibcall optimization if either caller or callee uses struct
3376 // return semantics.
3377 if (isCalleeStructRet || isCallerStructRet)
3380 // An stdcall/thiscall caller is expected to clean up its arguments; the
3381 // callee isn't going to do that.
3382 // FIXME: this is more restrictive than needed. We could produce a tailcall
3383 // when the stack adjustment matches. For example, with a thiscall that takes
3384 // only one argument.
3385 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3386 CallerCC == CallingConv::X86_ThisCall))
3389 // Do not sibcall optimize vararg calls unless all arguments are passed via
3391 if (isVarArg && !Outs.empty()) {
3393 // Optimizing for varargs on Win64 is unlikely to be safe without
3394 // additional testing.
3395 if (IsCalleeWin64 || IsCallerWin64)
3398 SmallVector<CCValAssign, 16> ArgLocs;
3399 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3402 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3403 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3404 if (!ArgLocs[i].isRegLoc())
3408 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3409 // stack. Therefore, if it's not used by the call it is not safe to optimize
3410 // this into a sibcall.
3411 bool Unused = false;
3412 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3419 SmallVector<CCValAssign, 16> RVLocs;
3420 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3422 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3423 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3424 CCValAssign &VA = RVLocs[i];
3425 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3430 // If the calling conventions do not match, then we'd better make sure the
3431 // results are returned in the same way as what the caller expects.
3433 SmallVector<CCValAssign, 16> RVLocs1;
3434 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3436 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3438 SmallVector<CCValAssign, 16> RVLocs2;
3439 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3441 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3443 if (RVLocs1.size() != RVLocs2.size())
3445 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3446 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3448 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3450 if (RVLocs1[i].isRegLoc()) {
3451 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3454 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3460 // If the callee takes no arguments then go on to check the results of the
3462 if (!Outs.empty()) {
3463 // Check if stack adjustment is needed. For now, do not do this if any
3464 // argument is passed on the stack.
3465 SmallVector<CCValAssign, 16> ArgLocs;
3466 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3469 // Allocate shadow area for Win64
3471 CCInfo.AllocateStack(32, 8);
3473 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3474 if (CCInfo.getNextStackOffset()) {
3475 MachineFunction &MF = DAG.getMachineFunction();
3476 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3479 // Check if the arguments are already laid out in the right way as
3480 // the caller's fixed stack objects.
3481 MachineFrameInfo *MFI = MF.getFrameInfo();
3482 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3483 const X86InstrInfo *TII =
3484 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3485 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3486 CCValAssign &VA = ArgLocs[i];
3487 SDValue Arg = OutVals[i];
3488 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3489 if (VA.getLocInfo() == CCValAssign::Indirect)
3491 if (!VA.isRegLoc()) {
3492 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3499 // If the tailcall address may be in a register, then make sure it's
3500 // possible to register allocate for it. In 32-bit, the call address can
3501 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3502 // callee-saved registers are restored. These happen to be the same
3503 // registers used to pass 'inreg' arguments so watch out for those.
3504 if (!Subtarget->is64Bit() &&
3505 ((!isa<GlobalAddressSDNode>(Callee) &&
3506 !isa<ExternalSymbolSDNode>(Callee)) ||
3507 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3508 unsigned NumInRegs = 0;
3509 // In PIC we need an extra register to formulate the address computation
3511 unsigned MaxInRegs =
3512 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3514 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3515 CCValAssign &VA = ArgLocs[i];
3518 unsigned Reg = VA.getLocReg();
3521 case X86::EAX: case X86::EDX: case X86::ECX:
3522 if (++NumInRegs == MaxInRegs)
3534 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3535 const TargetLibraryInfo *libInfo) const {
3536 return X86::createFastISel(funcInfo, libInfo);
3539 //===----------------------------------------------------------------------===//
3540 // Other Lowering Hooks
3541 //===----------------------------------------------------------------------===//
3543 static bool MayFoldLoad(SDValue Op) {
3544 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3547 static bool MayFoldIntoStore(SDValue Op) {
3548 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3551 static bool isTargetShuffle(unsigned Opcode) {
3553 default: return false;
3554 case X86ISD::BLENDI:
3555 case X86ISD::PSHUFB:
3556 case X86ISD::PSHUFD:
3557 case X86ISD::PSHUFHW:
3558 case X86ISD::PSHUFLW:
3560 case X86ISD::PALIGNR:
3561 case X86ISD::MOVLHPS:
3562 case X86ISD::MOVLHPD:
3563 case X86ISD::MOVHLPS:
3564 case X86ISD::MOVLPS:
3565 case X86ISD::MOVLPD:
3566 case X86ISD::MOVSHDUP:
3567 case X86ISD::MOVSLDUP:
3568 case X86ISD::MOVDDUP:
3571 case X86ISD::UNPCKL:
3572 case X86ISD::UNPCKH:
3573 case X86ISD::VPERMILPI:
3574 case X86ISD::VPERM2X128:
3575 case X86ISD::VPERMI:
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::MOVSHDUP:
3585 case X86ISD::MOVSLDUP:
3586 case X86ISD::MOVDDUP:
3587 return DAG.getNode(Opc, dl, VT, V1);
3591 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3592 SDValue V1, unsigned TargetMask,
3593 SelectionDAG &DAG) {
3595 default: llvm_unreachable("Unknown x86 shuffle node");
3596 case X86ISD::PSHUFD:
3597 case X86ISD::PSHUFHW:
3598 case X86ISD::PSHUFLW:
3599 case X86ISD::VPERMILPI:
3600 case X86ISD::VPERMI:
3601 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3605 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3606 SDValue V1, SDValue V2, unsigned TargetMask,
3607 SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::PALIGNR:
3611 case X86ISD::VALIGN:
3613 case X86ISD::VPERM2X128:
3614 return DAG.getNode(Opc, dl, VT, V1, V2,
3615 DAG.getConstant(TargetMask, MVT::i8));
3619 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3620 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3622 default: llvm_unreachable("Unknown x86 shuffle node");
3623 case X86ISD::MOVLHPS:
3624 case X86ISD::MOVLHPD:
3625 case X86ISD::MOVHLPS:
3626 case X86ISD::MOVLPS:
3627 case X86ISD::MOVLPD:
3630 case X86ISD::UNPCKL:
3631 case X86ISD::UNPCKH:
3632 return DAG.getNode(Opc, dl, VT, V1, V2);
3636 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3637 MachineFunction &MF = DAG.getMachineFunction();
3638 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3639 DAG.getSubtarget().getRegisterInfo());
3640 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3641 int ReturnAddrIndex = FuncInfo->getRAIndex();
3643 if (ReturnAddrIndex == 0) {
3644 // Set up a frame object for the return address.
3645 unsigned SlotSize = RegInfo->getSlotSize();
3646 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3649 FuncInfo->setRAIndex(ReturnAddrIndex);
3652 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3655 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3656 bool hasSymbolicDisplacement) {
3657 // Offset should fit into 32 bit immediate field.
3658 if (!isInt<32>(Offset))
3661 // If we don't have a symbolic displacement - we don't have any extra
3663 if (!hasSymbolicDisplacement)
3666 // FIXME: Some tweaks might be needed for medium code model.
3667 if (M != CodeModel::Small && M != CodeModel::Kernel)
3670 // For small code model we assume that latest object is 16MB before end of 31
3671 // bits boundary. We may also accept pretty large negative constants knowing
3672 // that all objects are in the positive half of address space.
3673 if (M == CodeModel::Small && Offset < 16*1024*1024)
3676 // For kernel code model we know that all object resist in the negative half
3677 // of 32bits address space. We may not accept negative offsets, since they may
3678 // be just off and we may accept pretty large positive ones.
3679 if (M == CodeModel::Kernel && Offset > 0)
3685 /// isCalleePop - Determines whether the callee is required to pop its
3686 /// own arguments. Callee pop is necessary to support tail calls.
3687 bool X86::isCalleePop(CallingConv::ID CallingConv,
3688 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3689 switch (CallingConv) {
3692 case CallingConv::X86_StdCall:
3693 case CallingConv::X86_FastCall:
3694 case CallingConv::X86_ThisCall:
3696 case CallingConv::Fast:
3697 case CallingConv::GHC:
3698 case CallingConv::HiPE:
3705 /// \brief Return true if the condition is an unsigned comparison operation.
3706 static bool isX86CCUnsigned(unsigned X86CC) {
3708 default: llvm_unreachable("Invalid integer condition!");
3709 case X86::COND_E: return true;
3710 case X86::COND_G: return false;
3711 case X86::COND_GE: return false;
3712 case X86::COND_L: return false;
3713 case X86::COND_LE: return false;
3714 case X86::COND_NE: return true;
3715 case X86::COND_B: return true;
3716 case X86::COND_A: return true;
3717 case X86::COND_BE: return true;
3718 case X86::COND_AE: return true;
3720 llvm_unreachable("covered switch fell through?!");
3723 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3724 /// specific condition code, returning the condition code and the LHS/RHS of the
3725 /// comparison to make.
3726 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3727 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3729 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3730 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3731 // X > -1 -> X == 0, jump !sign.
3732 RHS = DAG.getConstant(0, RHS.getValueType());
3733 return X86::COND_NS;
3735 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3736 // X < 0 -> X == 0, jump on sign.
3739 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3741 RHS = DAG.getConstant(0, RHS.getValueType());
3742 return X86::COND_LE;
3746 switch (SetCCOpcode) {
3747 default: llvm_unreachable("Invalid integer condition!");
3748 case ISD::SETEQ: return X86::COND_E;
3749 case ISD::SETGT: return X86::COND_G;
3750 case ISD::SETGE: return X86::COND_GE;
3751 case ISD::SETLT: return X86::COND_L;
3752 case ISD::SETLE: return X86::COND_LE;
3753 case ISD::SETNE: return X86::COND_NE;
3754 case ISD::SETULT: return X86::COND_B;
3755 case ISD::SETUGT: return X86::COND_A;
3756 case ISD::SETULE: return X86::COND_BE;
3757 case ISD::SETUGE: return X86::COND_AE;
3761 // First determine if it is required or is profitable to flip the operands.
3763 // If LHS is a foldable load, but RHS is not, flip the condition.
3764 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3765 !ISD::isNON_EXTLoad(RHS.getNode())) {
3766 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3767 std::swap(LHS, RHS);
3770 switch (SetCCOpcode) {
3776 std::swap(LHS, RHS);
3780 // On a floating point condition, the flags are set as follows:
3782 // 0 | 0 | 0 | X > Y
3783 // 0 | 0 | 1 | X < Y
3784 // 1 | 0 | 0 | X == Y
3785 // 1 | 1 | 1 | unordered
3786 switch (SetCCOpcode) {
3787 default: llvm_unreachable("Condcode should be pre-legalized away");
3789 case ISD::SETEQ: return X86::COND_E;
3790 case ISD::SETOLT: // flipped
3792 case ISD::SETGT: return X86::COND_A;
3793 case ISD::SETOLE: // flipped
3795 case ISD::SETGE: return X86::COND_AE;
3796 case ISD::SETUGT: // flipped
3798 case ISD::SETLT: return X86::COND_B;
3799 case ISD::SETUGE: // flipped
3801 case ISD::SETLE: return X86::COND_BE;
3803 case ISD::SETNE: return X86::COND_NE;
3804 case ISD::SETUO: return X86::COND_P;
3805 case ISD::SETO: return X86::COND_NP;
3807 case ISD::SETUNE: return X86::COND_INVALID;
3811 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3812 /// code. Current x86 isa includes the following FP cmov instructions:
3813 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3814 static bool hasFPCMov(unsigned X86CC) {
3830 /// isFPImmLegal - Returns true if the target can instruction select the
3831 /// specified FP immediate natively. If false, the legalizer will
3832 /// materialize the FP immediate as a load from a constant pool.
3833 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3834 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3835 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3841 /// \brief Returns true if it is beneficial to convert a load of a constant
3842 /// to just the constant itself.
3843 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3845 assert(Ty->isIntegerTy());
3847 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3848 if (BitSize == 0 || BitSize > 64)
3853 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3854 /// the specified range (L, H].
3855 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3856 return (Val < 0) || (Val >= Low && Val < Hi);
3859 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3860 /// specified value.
3861 static bool isUndefOrEqual(int Val, int CmpVal) {
3862 return (Val < 0 || Val == CmpVal);
3865 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3866 /// from position Pos and ending in Pos+Size, falls within the specified
3867 /// sequential range (L, L+Pos]. or is undef.
3868 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3869 unsigned Pos, unsigned Size, int Low) {
3870 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3871 if (!isUndefOrEqual(Mask[i], Low))
3876 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3878 /// operand - by default will match for first operand.
3879 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3880 bool TestSecondOperand = false) {
3881 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3882 VT != MVT::v2f64 && VT != MVT::v2i64)
3885 unsigned NumElems = VT.getVectorNumElements();
3886 unsigned Lo = TestSecondOperand ? NumElems : 0;
3887 unsigned Hi = Lo + NumElems;
3889 for (unsigned i = 0; i < NumElems; ++i)
3890 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3896 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3897 /// is suitable for input to PSHUFHW.
3898 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3899 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3902 // Lower quadword copied in order or undef.
3903 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3906 // Upper quadword shuffled.
3907 for (unsigned i = 4; i != 8; ++i)
3908 if (!isUndefOrInRange(Mask[i], 4, 8))
3911 if (VT == MVT::v16i16) {
3912 // Lower quadword copied in order or undef.
3913 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3916 // Upper quadword shuffled.
3917 for (unsigned i = 12; i != 16; ++i)
3918 if (!isUndefOrInRange(Mask[i], 12, 16))
3925 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3926 /// is suitable for input to PSHUFLW.
3927 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3928 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3931 // Upper quadword copied in order.
3932 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3935 // Lower quadword shuffled.
3936 for (unsigned i = 0; i != 4; ++i)
3937 if (!isUndefOrInRange(Mask[i], 0, 4))
3940 if (VT == MVT::v16i16) {
3941 // Upper quadword copied in order.
3942 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3945 // Lower quadword shuffled.
3946 for (unsigned i = 8; i != 12; ++i)
3947 if (!isUndefOrInRange(Mask[i], 8, 12))
3954 /// \brief Return true if the mask specifies a shuffle of elements that is
3955 /// suitable for input to intralane (palignr) or interlane (valign) vector
3957 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3958 unsigned NumElts = VT.getVectorNumElements();
3959 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3960 unsigned NumLaneElts = NumElts/NumLanes;
3962 // Do not handle 64-bit element shuffles with palignr.
3963 if (NumLaneElts == 2)
3966 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3968 for (i = 0; i != NumLaneElts; ++i) {
3973 // Lane is all undef, go to next lane
3974 if (i == NumLaneElts)
3977 int Start = Mask[i+l];
3979 // Make sure its in this lane in one of the sources
3980 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3981 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3984 // If not lane 0, then we must match lane 0
3985 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3988 // Correct second source to be contiguous with first source
3989 if (Start >= (int)NumElts)
3990 Start -= NumElts - NumLaneElts;
3992 // Make sure we're shifting in the right direction.
3993 if (Start <= (int)(i+l))
3998 // Check the rest of the elements to see if they are consecutive.
3999 for (++i; i != NumLaneElts; ++i) {
4000 int Idx = Mask[i+l];
4002 // Make sure its in this lane
4003 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4004 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4007 // If not lane 0, then we must match lane 0
4008 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4011 if (Idx >= (int)NumElts)
4012 Idx -= NumElts - NumLaneElts;
4014 if (!isUndefOrEqual(Idx, Start+i))
4023 /// \brief Return true if the node specifies a shuffle of elements that is
4024 /// suitable for input to PALIGNR.
4025 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4026 const X86Subtarget *Subtarget) {
4027 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4028 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4029 VT.is512BitVector())
4030 // FIXME: Add AVX512BW.
4033 return isAlignrMask(Mask, VT, false);
4036 /// \brief Return true if the node specifies a shuffle of elements that is
4037 /// suitable for input to VALIGN.
4038 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4039 const X86Subtarget *Subtarget) {
4040 // FIXME: Add AVX512VL.
4041 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4043 return isAlignrMask(Mask, VT, true);
4046 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4047 /// the two vector operands have swapped position.
4048 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4049 unsigned NumElems) {
4050 for (unsigned i = 0; i != NumElems; ++i) {
4054 else if (idx < (int)NumElems)
4055 Mask[i] = idx + NumElems;
4057 Mask[i] = idx - NumElems;
4061 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4062 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4063 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4064 /// reverse of what x86 shuffles want.
4065 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4067 unsigned NumElems = VT.getVectorNumElements();
4068 unsigned NumLanes = VT.getSizeInBits()/128;
4069 unsigned NumLaneElems = NumElems/NumLanes;
4071 if (NumLaneElems != 2 && NumLaneElems != 4)
4074 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4075 bool symetricMaskRequired =
4076 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4078 // VSHUFPSY divides the resulting vector into 4 chunks.
4079 // The sources are also splitted into 4 chunks, and each destination
4080 // chunk must come from a different source chunk.
4082 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4083 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4085 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4086 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4088 // VSHUFPDY divides the resulting vector into 4 chunks.
4089 // The sources are also splitted into 4 chunks, and each destination
4090 // chunk must come from a different source chunk.
4092 // SRC1 => X3 X2 X1 X0
4093 // SRC2 => Y3 Y2 Y1 Y0
4095 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4097 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4098 unsigned HalfLaneElems = NumLaneElems/2;
4099 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4100 for (unsigned i = 0; i != NumLaneElems; ++i) {
4101 int Idx = Mask[i+l];
4102 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4103 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4105 // For VSHUFPSY, the mask of the second half must be the same as the
4106 // first but with the appropriate offsets. This works in the same way as
4107 // VPERMILPS works with masks.
4108 if (!symetricMaskRequired || Idx < 0)
4110 if (MaskVal[i] < 0) {
4111 MaskVal[i] = Idx - l;
4114 if ((signed)(Idx - l) != MaskVal[i])
4122 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4123 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4124 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4125 if (!VT.is128BitVector())
4128 unsigned NumElems = VT.getVectorNumElements();
4133 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4134 return isUndefOrEqual(Mask[0], 6) &&
4135 isUndefOrEqual(Mask[1], 7) &&
4136 isUndefOrEqual(Mask[2], 2) &&
4137 isUndefOrEqual(Mask[3], 3);
4140 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4141 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4143 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4144 if (!VT.is128BitVector())
4147 unsigned NumElems = VT.getVectorNumElements();
4152 return isUndefOrEqual(Mask[0], 2) &&
4153 isUndefOrEqual(Mask[1], 3) &&
4154 isUndefOrEqual(Mask[2], 2) &&
4155 isUndefOrEqual(Mask[3], 3);
4158 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4160 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i + NumElems))
4173 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i], i))
4180 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4182 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4183 if (!VT.is128BitVector())
4186 unsigned NumElems = VT.getVectorNumElements();
4188 if (NumElems != 2 && NumElems != 4)
4191 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4192 if (!isUndefOrEqual(Mask[i], i))
4195 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4196 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4202 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4203 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4204 /// i. e: If all but one element come from the same vector.
4205 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4206 // TODO: Deal with AVX's VINSERTPS
4207 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4210 unsigned CorrectPosV1 = 0;
4211 unsigned CorrectPosV2 = 0;
4212 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4213 if (Mask[i] == -1) {
4221 else if (Mask[i] == i + 4)
4225 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4226 // We have 3 elements (undefs count as elements from any vector) from one
4227 // vector, and one from another.
4234 // Some special combinations that can be optimized.
4237 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4238 SelectionDAG &DAG) {
4239 MVT VT = SVOp->getSimpleValueType(0);
4242 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4245 ArrayRef<int> Mask = SVOp->getMask();
4247 // These are the special masks that may be optimized.
4248 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4249 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4250 bool MatchEvenMask = true;
4251 bool MatchOddMask = true;
4252 for (int i=0; i<8; ++i) {
4253 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4254 MatchEvenMask = false;
4255 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4256 MatchOddMask = false;
4259 if (!MatchEvenMask && !MatchOddMask)
4262 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4264 SDValue Op0 = SVOp->getOperand(0);
4265 SDValue Op1 = SVOp->getOperand(1);
4267 if (MatchEvenMask) {
4268 // Shift the second operand right to 32 bits.
4269 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4270 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4272 // Shift the first operand left to 32 bits.
4273 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4274 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4276 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4277 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4280 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4281 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4282 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4283 bool HasInt256, bool V2IsSplat = false) {
4285 assert(VT.getSizeInBits() >= 128 &&
4286 "Unsupported vector type for unpckl");
4288 unsigned NumElts = VT.getVectorNumElements();
4289 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4290 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4293 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4294 "Unsupported vector type for unpckh");
4296 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4297 unsigned NumLanes = VT.getSizeInBits()/128;
4298 unsigned NumLaneElts = NumElts/NumLanes;
4300 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4301 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4302 int BitI = Mask[l+i];
4303 int BitI1 = Mask[l+i+1];
4304 if (!isUndefOrEqual(BitI, j))
4307 if (!isUndefOrEqual(BitI1, NumElts))
4310 if (!isUndefOrEqual(BitI1, j + NumElts))
4319 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4320 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4321 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4322 bool HasInt256, bool V2IsSplat = false) {
4323 assert(VT.getSizeInBits() >= 128 &&
4324 "Unsupported vector type for unpckh");
4326 unsigned NumElts = VT.getVectorNumElements();
4327 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4328 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4331 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4332 "Unsupported vector type for unpckh");
4334 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4335 unsigned NumLanes = VT.getSizeInBits()/128;
4336 unsigned NumLaneElts = NumElts/NumLanes;
4338 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4339 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4340 int BitI = Mask[l+i];
4341 int BitI1 = Mask[l+i+1];
4342 if (!isUndefOrEqual(BitI, j))
4345 if (isUndefOrEqual(BitI1, NumElts))
4348 if (!isUndefOrEqual(BitI1, j+NumElts))
4356 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4357 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4359 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4360 unsigned NumElts = VT.getVectorNumElements();
4361 bool Is256BitVec = VT.is256BitVector();
4363 if (VT.is512BitVector())
4365 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4366 "Unsupported vector type for unpckh");
4368 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4369 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4372 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4373 // FIXME: Need a better way to get rid of this, there's no latency difference
4374 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4375 // the former later. We should also remove the "_undef" special mask.
4376 if (NumElts == 4 && Is256BitVec)
4379 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4380 // independently on 128-bit lanes.
4381 unsigned NumLanes = VT.getSizeInBits()/128;
4382 unsigned NumLaneElts = NumElts/NumLanes;
4384 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4385 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4386 int BitI = Mask[l+i];
4387 int BitI1 = Mask[l+i+1];
4389 if (!isUndefOrEqual(BitI, j))
4391 if (!isUndefOrEqual(BitI1, j))
4399 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4400 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4402 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4403 unsigned NumElts = VT.getVectorNumElements();
4405 if (VT.is512BitVector())
4408 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4409 "Unsupported vector type for unpckh");
4411 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4412 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4415 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4416 // independently on 128-bit lanes.
4417 unsigned NumLanes = VT.getSizeInBits()/128;
4418 unsigned NumLaneElts = NumElts/NumLanes;
4420 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4421 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4422 int BitI = Mask[l+i];
4423 int BitI1 = Mask[l+i+1];
4424 if (!isUndefOrEqual(BitI, j))
4426 if (!isUndefOrEqual(BitI1, j))
4433 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4434 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4435 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4436 if (!VT.is512BitVector())
4439 unsigned NumElts = VT.getVectorNumElements();
4440 unsigned HalfSize = NumElts/2;
4441 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4442 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4447 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4448 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4456 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4457 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4458 /// MOVSD, and MOVD, i.e. setting the lowest element.
4459 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4460 if (VT.getVectorElementType().getSizeInBits() < 32)
4462 if (!VT.is128BitVector())
4465 unsigned NumElts = VT.getVectorNumElements();
4467 if (!isUndefOrEqual(Mask[0], NumElts))
4470 for (unsigned i = 1; i != NumElts; ++i)
4471 if (!isUndefOrEqual(Mask[i], i))
4477 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4478 /// as permutations between 128-bit chunks or halves. As an example: this
4480 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4481 /// The first half comes from the second half of V1 and the second half from the
4482 /// the second half of V2.
4483 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4484 if (!HasFp256 || !VT.is256BitVector())
4487 // The shuffle result is divided into half A and half B. In total the two
4488 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4489 // B must come from C, D, E or F.
4490 unsigned HalfSize = VT.getVectorNumElements()/2;
4491 bool MatchA = false, MatchB = false;
4493 // Check if A comes from one of C, D, E, F.
4494 for (unsigned Half = 0; Half != 4; ++Half) {
4495 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4501 // Check if B comes from one of C, D, E, F.
4502 for (unsigned Half = 0; Half != 4; ++Half) {
4503 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4509 return MatchA && MatchB;
4512 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4513 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4514 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4515 MVT VT = SVOp->getSimpleValueType(0);
4517 unsigned HalfSize = VT.getVectorNumElements()/2;
4519 unsigned FstHalf = 0, SndHalf = 0;
4520 for (unsigned i = 0; i < HalfSize; ++i) {
4521 if (SVOp->getMaskElt(i) > 0) {
4522 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4526 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4527 if (SVOp->getMaskElt(i) > 0) {
4528 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4533 return (FstHalf | (SndHalf << 4));
4536 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4537 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4538 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4542 unsigned NumElts = VT.getVectorNumElements();
4544 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4545 for (unsigned i = 0; i != NumElts; ++i) {
4548 Imm8 |= Mask[i] << (i*2);
4553 unsigned LaneSize = 4;
4554 SmallVector<int, 4> MaskVal(LaneSize, -1);
4556 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4557 for (unsigned i = 0; i != LaneSize; ++i) {
4558 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4562 if (MaskVal[i] < 0) {
4563 MaskVal[i] = Mask[i+l] - l;
4564 Imm8 |= MaskVal[i] << (i*2);
4567 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4574 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4575 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4576 /// Note that VPERMIL mask matching is different depending whether theunderlying
4577 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4578 /// to the same elements of the low, but to the higher half of the source.
4579 /// In VPERMILPD the two lanes could be shuffled independently of each other
4580 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4581 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4582 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4583 if (VT.getSizeInBits() < 256 || EltSize < 32)
4585 bool symetricMaskRequired = (EltSize == 32);
4586 unsigned NumElts = VT.getVectorNumElements();
4588 unsigned NumLanes = VT.getSizeInBits()/128;
4589 unsigned LaneSize = NumElts/NumLanes;
4590 // 2 or 4 elements in one lane
4592 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4593 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4594 for (unsigned i = 0; i != LaneSize; ++i) {
4595 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4597 if (symetricMaskRequired) {
4598 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4599 ExpectedMaskVal[i] = Mask[i+l] - l;
4602 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4610 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4611 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4612 /// element of vector 2 and the other elements to come from vector 1 in order.
4613 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4614 bool V2IsSplat = false, bool V2IsUndef = false) {
4615 if (!VT.is128BitVector())
4618 unsigned NumOps = VT.getVectorNumElements();
4619 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4622 if (!isUndefOrEqual(Mask[0], 0))
4625 for (unsigned i = 1; i != NumOps; ++i)
4626 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4627 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4628 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4634 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4635 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4636 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4637 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4638 const X86Subtarget *Subtarget) {
4639 if (!Subtarget->hasSSE3())
4642 unsigned NumElems = VT.getVectorNumElements();
4644 if ((VT.is128BitVector() && NumElems != 4) ||
4645 (VT.is256BitVector() && NumElems != 8) ||
4646 (VT.is512BitVector() && NumElems != 16))
4649 // "i+1" is the value the indexed mask element must have
4650 for (unsigned i = 0; i != NumElems; i += 2)
4651 if (!isUndefOrEqual(Mask[i], i+1) ||
4652 !isUndefOrEqual(Mask[i+1], i+1))
4658 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4659 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4660 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4661 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4662 const X86Subtarget *Subtarget) {
4663 if (!Subtarget->hasSSE3())
4666 unsigned NumElems = VT.getVectorNumElements();
4668 if ((VT.is128BitVector() && NumElems != 4) ||
4669 (VT.is256BitVector() && NumElems != 8) ||
4670 (VT.is512BitVector() && NumElems != 16))
4673 // "i" is the value the indexed mask element must have
4674 for (unsigned i = 0; i != NumElems; i += 2)
4675 if (!isUndefOrEqual(Mask[i], i) ||
4676 !isUndefOrEqual(Mask[i+1], i))
4682 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 256-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4686 if (!HasFp256 || !VT.is256BitVector())
4689 unsigned NumElts = VT.getVectorNumElements();
4693 for (unsigned i = 0; i != NumElts/2; ++i)
4694 if (!isUndefOrEqual(Mask[i], 0))
4696 for (unsigned i = NumElts/2; i != NumElts; ++i)
4697 if (!isUndefOrEqual(Mask[i], NumElts/2))
4702 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4703 /// specifies a shuffle of elements that is suitable for input to 128-bit
4704 /// version of MOVDDUP.
4705 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4706 if (!VT.is128BitVector())
4709 unsigned e = VT.getVectorNumElements() / 2;
4710 for (unsigned i = 0; i != e; ++i)
4711 if (!isUndefOrEqual(Mask[i], i))
4713 for (unsigned i = 0; i != e; ++i)
4714 if (!isUndefOrEqual(Mask[e+i], i))
4719 /// isVEXTRACTIndex - Return true if the specified
4720 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4721 /// suitable for instruction that extract 128 or 256 bit vectors
4722 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4723 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4724 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4727 // The index should be aligned on a vecWidth-bit boundary.
4729 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4731 MVT VT = N->getSimpleValueType(0);
4732 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4733 bool Result = (Index * ElSize) % vecWidth == 0;
4738 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4739 /// operand specifies a subvector insert that is suitable for input to
4740 /// insertion of 128 or 256-bit subvectors
4741 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4742 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4743 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4745 // The index should be aligned on a vecWidth-bit boundary.
4747 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4749 MVT VT = N->getSimpleValueType(0);
4750 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4751 bool Result = (Index * ElSize) % vecWidth == 0;
4756 bool X86::isVINSERT128Index(SDNode *N) {
4757 return isVINSERTIndex(N, 128);
4760 bool X86::isVINSERT256Index(SDNode *N) {
4761 return isVINSERTIndex(N, 256);
4764 bool X86::isVEXTRACT128Index(SDNode *N) {
4765 return isVEXTRACTIndex(N, 128);
4768 bool X86::isVEXTRACT256Index(SDNode *N) {
4769 return isVEXTRACTIndex(N, 256);
4772 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4773 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4774 /// Handles 128-bit and 256-bit.
4775 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4776 MVT VT = N->getSimpleValueType(0);
4778 assert((VT.getSizeInBits() >= 128) &&
4779 "Unsupported vector type for PSHUF/SHUFP");
4781 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4782 // independently on 128-bit lanes.
4783 unsigned NumElts = VT.getVectorNumElements();
4784 unsigned NumLanes = VT.getSizeInBits()/128;
4785 unsigned NumLaneElts = NumElts/NumLanes;
4787 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4788 "Only supports 2, 4 or 8 elements per lane");
4790 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4792 for (unsigned i = 0; i != NumElts; ++i) {
4793 int Elt = N->getMaskElt(i);
4794 if (Elt < 0) continue;
4795 Elt &= NumLaneElts - 1;
4796 unsigned ShAmt = (i << Shift) % 8;
4797 Mask |= Elt << ShAmt;
4803 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4804 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4805 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4806 MVT VT = N->getSimpleValueType(0);
4808 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4809 "Unsupported vector type for PSHUFHW");
4811 unsigned NumElts = VT.getVectorNumElements();
4814 for (unsigned l = 0; l != NumElts; l += 8) {
4815 // 8 nodes per lane, but we only care about the last 4.
4816 for (unsigned i = 0; i < 4; ++i) {
4817 int Elt = N->getMaskElt(l+i+4);
4818 if (Elt < 0) continue;
4819 Elt &= 0x3; // only 2-bits.
4820 Mask |= Elt << (i * 2);
4827 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4828 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4829 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4830 MVT VT = N->getSimpleValueType(0);
4832 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4833 "Unsupported vector type for PSHUFHW");
4835 unsigned NumElts = VT.getVectorNumElements();
4838 for (unsigned l = 0; l != NumElts; l += 8) {
4839 // 8 nodes per lane, but we only care about the first 4.
4840 for (unsigned i = 0; i < 4; ++i) {
4841 int Elt = N->getMaskElt(l+i);
4842 if (Elt < 0) continue;
4843 Elt &= 0x3; // only 2-bits
4844 Mask |= Elt << (i * 2);
4851 /// \brief Return the appropriate immediate to shuffle the specified
4852 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4853 /// VALIGN (if Interlane is true) instructions.
4854 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4856 MVT VT = SVOp->getSimpleValueType(0);
4857 unsigned EltSize = InterLane ? 1 :
4858 VT.getVectorElementType().getSizeInBits() >> 3;
4860 unsigned NumElts = VT.getVectorNumElements();
4861 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4862 unsigned NumLaneElts = NumElts/NumLanes;
4866 for (i = 0; i != NumElts; ++i) {
4867 Val = SVOp->getMaskElt(i);
4871 if (Val >= (int)NumElts)
4872 Val -= NumElts - NumLaneElts;
4874 assert(Val - i > 0 && "PALIGNR imm should be positive");
4875 return (Val - i) * EltSize;
4878 /// \brief Return the appropriate immediate to shuffle the specified
4879 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4880 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4881 return getShuffleAlignrImmediate(SVOp, false);
4884 /// \brief Return the appropriate immediate to shuffle the specified
4885 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4886 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4887 return getShuffleAlignrImmediate(SVOp, true);
4891 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4892 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4893 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4894 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4897 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4899 MVT VecVT = N->getOperand(0).getSimpleValueType();
4900 MVT ElVT = VecVT.getVectorElementType();
4902 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4903 return Index / NumElemsPerChunk;
4906 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4907 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4908 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4909 llvm_unreachable("Illegal insert subvector for VINSERT");
4912 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4914 MVT VecVT = N->getSimpleValueType(0);
4915 MVT ElVT = VecVT.getVectorElementType();
4917 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4918 return Index / NumElemsPerChunk;
4921 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4922 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4923 /// and VINSERTI128 instructions.
4924 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4925 return getExtractVEXTRACTImmediate(N, 128);
4928 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4929 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4930 /// and VINSERTI64x4 instructions.
4931 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4932 return getExtractVEXTRACTImmediate(N, 256);
4935 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4936 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4937 /// and VINSERTI128 instructions.
4938 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4939 return getInsertVINSERTImmediate(N, 128);
4942 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4943 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4944 /// and VINSERTI64x4 instructions.
4945 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4946 return getInsertVINSERTImmediate(N, 256);
4949 /// isZero - Returns true if Elt is a constant integer zero
4950 static bool isZero(SDValue V) {
4951 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4952 return C && C->isNullValue();
4955 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4957 bool X86::isZeroNode(SDValue Elt) {
4960 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4961 return CFP->getValueAPF().isPosZero();
4965 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4966 /// match movhlps. The lower half elements should come from upper half of
4967 /// V1 (and in order), and the upper half elements should come from the upper
4968 /// half of V2 (and in order).
4969 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4970 if (!VT.is128BitVector())
4972 if (VT.getVectorNumElements() != 4)
4974 for (unsigned i = 0, e = 2; i != e; ++i)
4975 if (!isUndefOrEqual(Mask[i], i+2))
4977 for (unsigned i = 2; i != 4; ++i)
4978 if (!isUndefOrEqual(Mask[i], i+4))
4983 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4984 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4986 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4987 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4989 N = N->getOperand(0).getNode();
4990 if (!ISD::isNON_EXTLoad(N))
4993 *LD = cast<LoadSDNode>(N);
4997 // Test whether the given value is a vector value which will be legalized
4999 static bool WillBeConstantPoolLoad(SDNode *N) {
5000 if (N->getOpcode() != ISD::BUILD_VECTOR)
5003 // Check for any non-constant elements.
5004 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5005 switch (N->getOperand(i).getNode()->getOpcode()) {
5007 case ISD::ConstantFP:
5014 // Vectors of all-zeros and all-ones are materialized with special
5015 // instructions rather than being loaded.
5016 return !ISD::isBuildVectorAllZeros(N) &&
5017 !ISD::isBuildVectorAllOnes(N);
5020 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5021 /// match movlp{s|d}. The lower half elements should come from lower half of
5022 /// V1 (and in order), and the upper half elements should come from the upper
5023 /// half of V2 (and in order). And since V1 will become the source of the
5024 /// MOVLP, it must be either a vector load or a scalar load to vector.
5025 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5026 ArrayRef<int> Mask, MVT VT) {
5027 if (!VT.is128BitVector())
5030 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5032 // Is V2 is a vector load, don't do this transformation. We will try to use
5033 // load folding shufps op.
5034 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5037 unsigned NumElems = VT.getVectorNumElements();
5039 if (NumElems != 2 && NumElems != 4)
5041 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5042 if (!isUndefOrEqual(Mask[i], i))
5044 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5045 if (!isUndefOrEqual(Mask[i], i+NumElems))
5050 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5051 /// to an zero vector.
5052 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5053 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5054 SDValue V1 = N->getOperand(0);
5055 SDValue V2 = N->getOperand(1);
5056 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5057 for (unsigned i = 0; i != NumElems; ++i) {
5058 int Idx = N->getMaskElt(i);
5059 if (Idx >= (int)NumElems) {
5060 unsigned Opc = V2.getOpcode();
5061 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5063 if (Opc != ISD::BUILD_VECTOR ||
5064 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5066 } else if (Idx >= 0) {
5067 unsigned Opc = V1.getOpcode();
5068 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5070 if (Opc != ISD::BUILD_VECTOR ||
5071 !X86::isZeroNode(V1.getOperand(Idx)))
5078 /// getZeroVector - Returns a vector of specified type with all zero elements.
5080 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5081 SelectionDAG &DAG, SDLoc dl) {
5082 assert(VT.isVector() && "Expected a vector type");
5084 // Always build SSE zero vectors as <4 x i32> bitcasted
5085 // to their dest type. This ensures they get CSE'd.
5087 if (VT.is128BitVector()) { // SSE
5088 if (Subtarget->hasSSE2()) { // SSE2
5089 SDValue Cst = DAG.getConstant(0, MVT::i32);
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5092 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5093 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5095 } else if (VT.is256BitVector()) { // AVX
5096 if (Subtarget->hasInt256()) { // AVX2
5097 SDValue Cst = DAG.getConstant(0, MVT::i32);
5098 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5099 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5101 // 256-bit logic and arithmetic instructions in AVX are all
5102 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5103 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5104 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5105 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5107 } else if (VT.is512BitVector()) { // AVX-512
5108 SDValue Cst = DAG.getConstant(0, MVT::i32);
5109 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5110 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5111 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5112 } else if (VT.getScalarType() == MVT::i1) {
5113 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5114 SDValue Cst = DAG.getConstant(0, MVT::i1);
5115 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5116 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5118 llvm_unreachable("Unexpected vector type");
5120 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5123 /// getOnesVector - Returns a vector of specified type with all bits set.
5124 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5125 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5126 /// Then bitcast to their original type, ensuring they get CSE'd.
5127 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5129 assert(VT.isVector() && "Expected a vector type");
5131 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5133 if (VT.is256BitVector()) {
5134 if (HasInt256) { // AVX2
5135 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5136 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5138 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5139 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5141 } else if (VT.is128BitVector()) {
5142 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5144 llvm_unreachable("Unexpected vector type");
5146 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5149 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5150 /// that point to V2 points to its first element.
5151 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5152 for (unsigned i = 0; i != NumElems; ++i) {
5153 if (Mask[i] > (int)NumElems) {
5159 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5160 /// operation of specified width.
5161 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5163 unsigned NumElems = VT.getVectorNumElements();
5164 SmallVector<int, 8> Mask;
5165 Mask.push_back(NumElems);
5166 for (unsigned i = 1; i != NumElems; ++i)
5168 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5171 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5172 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5174 unsigned NumElems = VT.getVectorNumElements();
5175 SmallVector<int, 8> Mask;
5176 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5178 Mask.push_back(i + NumElems);
5180 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5183 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5184 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5186 unsigned NumElems = VT.getVectorNumElements();
5187 SmallVector<int, 8> Mask;
5188 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5189 Mask.push_back(i + Half);
5190 Mask.push_back(i + NumElems + Half);
5192 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5195 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5196 // a generic shuffle instruction because the target has no such instructions.
5197 // Generate shuffles which repeat i16 and i8 several times until they can be
5198 // represented by v4f32 and then be manipulated by target suported shuffles.
5199 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5200 MVT VT = V.getSimpleValueType();
5201 int NumElems = VT.getVectorNumElements();
5204 while (NumElems > 4) {
5205 if (EltNo < NumElems/2) {
5206 V = getUnpackl(DAG, dl, VT, V, V);
5208 V = getUnpackh(DAG, dl, VT, V, V);
5209 EltNo -= NumElems/2;
5216 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5217 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5218 MVT VT = V.getSimpleValueType();
5221 if (VT.is128BitVector()) {
5222 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5223 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5224 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5226 } else if (VT.is256BitVector()) {
5227 // To use VPERMILPS to splat scalars, the second half of indicies must
5228 // refer to the higher part, which is a duplication of the lower one,
5229 // because VPERMILPS can only handle in-lane permutations.
5230 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5231 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5233 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5234 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5237 llvm_unreachable("Vector size not supported");
5239 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5242 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5243 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5244 MVT SrcVT = SV->getSimpleValueType(0);
5245 SDValue V1 = SV->getOperand(0);
5248 int EltNo = SV->getSplatIndex();
5249 int NumElems = SrcVT.getVectorNumElements();
5250 bool Is256BitVec = SrcVT.is256BitVector();
5252 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5253 "Unknown how to promote splat for type");
5255 // Extract the 128-bit part containing the splat element and update
5256 // the splat element index when it refers to the higher register.
5258 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5259 if (EltNo >= NumElems/2)
5260 EltNo -= NumElems/2;
5263 // All i16 and i8 vector types can't be used directly by a generic shuffle
5264 // instruction because the target has no such instruction. Generate shuffles
5265 // which repeat i16 and i8 several times until they fit in i32, and then can
5266 // be manipulated by target suported shuffles.
5267 MVT EltVT = SrcVT.getVectorElementType();
5268 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5269 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5271 // Recreate the 256-bit vector and place the same 128-bit vector
5272 // into the low and high part. This is necessary because we want
5273 // to use VPERM* to shuffle the vectors
5275 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5278 return getLegalSplat(DAG, V1, EltNo);
5281 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5282 /// vector of zero or undef vector. This produces a shuffle where the low
5283 /// element of V2 is swizzled into the zero/undef vector, landing at element
5284 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5285 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5287 const X86Subtarget *Subtarget,
5288 SelectionDAG &DAG) {
5289 MVT VT = V2.getSimpleValueType();
5291 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5292 unsigned NumElems = VT.getVectorNumElements();
5293 SmallVector<int, 16> MaskVec;
5294 for (unsigned i = 0; i != NumElems; ++i)
5295 // If this is the insertion idx, put the low elt of V2 here.
5296 MaskVec.push_back(i == Idx ? NumElems : i);
5297 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5300 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5301 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5302 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5303 /// shuffles which use a single input multiple times, and in those cases it will
5304 /// adjust the mask to only have indices within that single input.
5305 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5306 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5307 unsigned NumElems = VT.getVectorNumElements();
5311 bool IsFakeUnary = false;
5312 switch(N->getOpcode()) {
5313 case X86ISD::BLENDI:
5314 ImmN = N->getOperand(N->getNumOperands()-1);
5315 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5320 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5322 case X86ISD::UNPCKH:
5323 DecodeUNPCKHMask(VT, Mask);
5324 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5326 case X86ISD::UNPCKL:
5327 DecodeUNPCKLMask(VT, Mask);
5328 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5330 case X86ISD::MOVHLPS:
5331 DecodeMOVHLPSMask(NumElems, Mask);
5332 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5334 case X86ISD::MOVLHPS:
5335 DecodeMOVLHPSMask(NumElems, Mask);
5336 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5338 case X86ISD::PALIGNR:
5339 ImmN = N->getOperand(N->getNumOperands()-1);
5340 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5342 case X86ISD::PSHUFD:
5343 case X86ISD::VPERMILPI:
5344 ImmN = N->getOperand(N->getNumOperands()-1);
5345 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5348 case X86ISD::PSHUFHW:
5349 ImmN = N->getOperand(N->getNumOperands()-1);
5350 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5353 case X86ISD::PSHUFLW:
5354 ImmN = N->getOperand(N->getNumOperands()-1);
5355 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5358 case X86ISD::PSHUFB: {
5360 SDValue MaskNode = N->getOperand(1);
5361 while (MaskNode->getOpcode() == ISD::BITCAST)
5362 MaskNode = MaskNode->getOperand(0);
5364 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5365 // If we have a build-vector, then things are easy.
5366 EVT VT = MaskNode.getValueType();
5367 assert(VT.isVector() &&
5368 "Can't produce a non-vector with a build_vector!");
5369 if (!VT.isInteger())
5372 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5374 SmallVector<uint64_t, 32> RawMask;
5375 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5376 SDValue Op = MaskNode->getOperand(i);
5377 if (Op->getOpcode() == ISD::UNDEF) {
5378 RawMask.push_back((uint64_t)SM_SentinelUndef);
5381 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5384 APInt MaskElement = CN->getAPIntValue();
5386 // We now have to decode the element which could be any integer size and
5387 // extract each byte of it.
5388 for (int j = 0; j < NumBytesPerElement; ++j) {
5389 // Note that this is x86 and so always little endian: the low byte is
5390 // the first byte of the mask.
5391 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5392 MaskElement = MaskElement.lshr(8);
5395 DecodePSHUFBMask(RawMask, Mask);
5399 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5403 SDValue Ptr = MaskLoad->getBasePtr();
5404 if (Ptr->getOpcode() == X86ISD::Wrapper)
5405 Ptr = Ptr->getOperand(0);
5407 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5408 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5411 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5412 // FIXME: Support AVX-512 here.
5413 Type *Ty = C->getType();
5414 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5415 Ty->getVectorNumElements() != 32))
5418 DecodePSHUFBMask(C, Mask);
5424 case X86ISD::VPERMI:
5425 ImmN = N->getOperand(N->getNumOperands()-1);
5426 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5430 case X86ISD::MOVSD: {
5431 // The index 0 always comes from the first element of the second source,
5432 // this is why MOVSS and MOVSD are used in the first place. The other
5433 // elements come from the other positions of the first source vector
5434 Mask.push_back(NumElems);
5435 for (unsigned i = 1; i != NumElems; ++i) {
5440 case X86ISD::VPERM2X128:
5441 ImmN = N->getOperand(N->getNumOperands()-1);
5442 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5443 if (Mask.empty()) return false;
5445 case X86ISD::MOVSLDUP:
5446 DecodeMOVSLDUPMask(VT, Mask);
5448 case X86ISD::MOVSHDUP:
5449 DecodeMOVSHDUPMask(VT, Mask);
5451 case X86ISD::MOVDDUP:
5452 case X86ISD::MOVLHPD:
5453 case X86ISD::MOVLPD:
5454 case X86ISD::MOVLPS:
5455 // Not yet implemented
5457 default: llvm_unreachable("unknown target shuffle node");
5460 // If we have a fake unary shuffle, the shuffle mask is spread across two
5461 // inputs that are actually the same node. Re-map the mask to always point
5462 // into the first input.
5465 if (M >= (int)Mask.size())
5471 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5472 /// element of the result of the vector shuffle.
5473 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5476 return SDValue(); // Limit search depth.
5478 SDValue V = SDValue(N, 0);
5479 EVT VT = V.getValueType();
5480 unsigned Opcode = V.getOpcode();
5482 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5483 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5484 int Elt = SV->getMaskElt(Index);
5487 return DAG.getUNDEF(VT.getVectorElementType());
5489 unsigned NumElems = VT.getVectorNumElements();
5490 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5491 : SV->getOperand(1);
5492 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5495 // Recurse into target specific vector shuffles to find scalars.
5496 if (isTargetShuffle(Opcode)) {
5497 MVT ShufVT = V.getSimpleValueType();
5498 unsigned NumElems = ShufVT.getVectorNumElements();
5499 SmallVector<int, 16> ShuffleMask;
5502 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5505 int Elt = ShuffleMask[Index];
5507 return DAG.getUNDEF(ShufVT.getVectorElementType());
5509 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5511 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5515 // Actual nodes that may contain scalar elements
5516 if (Opcode == ISD::BITCAST) {
5517 V = V.getOperand(0);
5518 EVT SrcVT = V.getValueType();
5519 unsigned NumElems = VT.getVectorNumElements();
5521 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5525 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5526 return (Index == 0) ? V.getOperand(0)
5527 : DAG.getUNDEF(VT.getVectorElementType());
5529 if (V.getOpcode() == ISD::BUILD_VECTOR)
5530 return V.getOperand(Index);
5535 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5536 /// shuffle operation which come from a consecutively from a zero. The
5537 /// search can start in two different directions, from left or right.
5538 /// We count undefs as zeros until PreferredNum is reached.
5539 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5540 unsigned NumElems, bool ZerosFromLeft,
5542 unsigned PreferredNum = -1U) {
5543 unsigned NumZeros = 0;
5544 for (unsigned i = 0; i != NumElems; ++i) {
5545 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5546 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5550 if (X86::isZeroNode(Elt))
5552 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5553 NumZeros = std::min(NumZeros + 1, PreferredNum);
5561 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5562 /// correspond consecutively to elements from one of the vector operands,
5563 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5565 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5566 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5567 unsigned NumElems, unsigned &OpNum) {
5568 bool SeenV1 = false;
5569 bool SeenV2 = false;
5571 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5572 int Idx = SVOp->getMaskElt(i);
5573 // Ignore undef indicies
5577 if (Idx < (int)NumElems)
5582 // Only accept consecutive elements from the same vector
5583 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5587 OpNum = SeenV1 ? 0 : 1;
5591 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5592 /// logical left shift of a vector.
5593 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5594 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5596 SVOp->getSimpleValueType(0).getVectorNumElements();
5597 unsigned NumZeros = getNumOfConsecutiveZeros(
5598 SVOp, NumElems, false /* check zeros from right */, DAG,
5599 SVOp->getMaskElt(0));
5605 // Considering the elements in the mask that are not consecutive zeros,
5606 // check if they consecutively come from only one of the source vectors.
5608 // V1 = {X, A, B, C} 0
5610 // vector_shuffle V1, V2 <1, 2, 3, X>
5612 if (!isShuffleMaskConsecutive(SVOp,
5613 0, // Mask Start Index
5614 NumElems-NumZeros, // Mask End Index(exclusive)
5615 NumZeros, // Where to start looking in the src vector
5616 NumElems, // Number of elements in vector
5617 OpSrc)) // Which source operand ?
5622 ShVal = SVOp->getOperand(OpSrc);
5626 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5627 /// logical left shift of a vector.
5628 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5629 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5631 SVOp->getSimpleValueType(0).getVectorNumElements();
5632 unsigned NumZeros = getNumOfConsecutiveZeros(
5633 SVOp, NumElems, true /* check zeros from left */, DAG,
5634 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5640 // Considering the elements in the mask that are not consecutive zeros,
5641 // check if they consecutively come from only one of the source vectors.
5643 // 0 { A, B, X, X } = V2
5645 // vector_shuffle V1, V2 <X, X, 4, 5>
5647 if (!isShuffleMaskConsecutive(SVOp,
5648 NumZeros, // Mask Start Index
5649 NumElems, // Mask End Index(exclusive)
5650 0, // Where to start looking in the src vector
5651 NumElems, // Number of elements in vector
5652 OpSrc)) // Which source operand ?
5657 ShVal = SVOp->getOperand(OpSrc);
5661 /// isVectorShift - Returns true if the shuffle can be implemented as a
5662 /// logical left or right shift of a vector.
5663 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5664 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5665 // Although the logic below support any bitwidth size, there are no
5666 // shift instructions which handle more than 128-bit vectors.
5667 if (!SVOp->getSimpleValueType(0).is128BitVector())
5670 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5671 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5677 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5679 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5680 unsigned NumNonZero, unsigned NumZero,
5682 const X86Subtarget* Subtarget,
5683 const TargetLowering &TLI) {
5690 for (unsigned i = 0; i < 16; ++i) {
5691 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5692 if (ThisIsNonZero && First) {
5694 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5696 V = DAG.getUNDEF(MVT::v8i16);
5701 SDValue ThisElt, LastElt;
5702 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5703 if (LastIsNonZero) {
5704 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5705 MVT::i16, Op.getOperand(i-1));
5707 if (ThisIsNonZero) {
5708 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5709 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5710 ThisElt, DAG.getConstant(8, MVT::i8));
5712 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5716 if (ThisElt.getNode())
5717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5718 DAG.getIntPtrConstant(i/2));
5722 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5725 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5727 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5728 unsigned NumNonZero, unsigned NumZero,
5730 const X86Subtarget* Subtarget,
5731 const TargetLowering &TLI) {
5738 for (unsigned i = 0; i < 8; ++i) {
5739 bool isNonZero = (NonZeros & (1 << i)) != 0;
5743 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5745 V = DAG.getUNDEF(MVT::v8i16);
5748 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5749 MVT::v8i16, V, Op.getOperand(i),
5750 DAG.getIntPtrConstant(i));
5757 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5758 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5759 const X86Subtarget *Subtarget,
5760 const TargetLowering &TLI) {
5761 // Find all zeroable elements.
5763 for (int i=0; i < 4; ++i) {
5764 SDValue Elt = Op->getOperand(i);
5765 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5767 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5768 [](bool M) { return !M; }) > 1 &&
5769 "We expect at least two non-zero elements!");
5771 // We only know how to deal with build_vector nodes where elements are either
5772 // zeroable or extract_vector_elt with constant index.
5773 SDValue FirstNonZero;
5774 for (int i=0; i < 4; ++i) {
5777 SDValue Elt = Op->getOperand(i);
5778 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5779 !isa<ConstantSDNode>(Elt.getOperand(1)))
5781 // Make sure that this node is extracting from a 128-bit vector.
5782 MVT VT = Elt.getOperand(0).getSimpleValueType();
5783 if (!VT.is128BitVector())
5785 if (!FirstNonZero.getNode())
5789 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5790 SDValue V1 = FirstNonZero.getOperand(0);
5791 MVT VT = V1.getSimpleValueType();
5793 // See if this build_vector can be lowered as a blend with zero.
5795 unsigned EltMaskIdx, EltIdx;
5797 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5798 if (Zeroable[EltIdx]) {
5799 // The zero vector will be on the right hand side.
5800 Mask[EltIdx] = EltIdx+4;
5804 Elt = Op->getOperand(EltIdx);
5805 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5806 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5807 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5809 Mask[EltIdx] = EltIdx;
5813 // Let the shuffle legalizer deal with blend operations.
5814 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5815 if (V1.getSimpleValueType() != VT)
5816 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5817 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5820 // See if we can lower this build_vector to a INSERTPS.
5821 if (!Subtarget->hasSSE41())
5824 SDValue V2 = Elt.getOperand(0);
5825 if (Elt == FirstNonZero)
5828 bool CanFold = true;
5829 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5833 SDValue Current = Op->getOperand(i);
5834 SDValue SrcVector = Current->getOperand(0);
5837 CanFold = SrcVector == V1 &&
5838 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5844 assert(V1.getNode() && "Expected at least two non-zero elements!");
5845 if (V1.getSimpleValueType() != MVT::v4f32)
5846 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5847 if (V2.getSimpleValueType() != MVT::v4f32)
5848 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5850 // Ok, we can emit an INSERTPS instruction.
5852 for (int i = 0; i < 4; ++i)
5856 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5857 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5858 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5859 DAG.getIntPtrConstant(InsertPSMask));
5860 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5863 /// getVShift - Return a vector logical shift node.
5865 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5866 unsigned NumBits, SelectionDAG &DAG,
5867 const TargetLowering &TLI, SDLoc dl) {
5868 assert(VT.is128BitVector() && "Unknown type for VShift");
5869 EVT ShVT = MVT::v2i64;
5870 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5871 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5872 return DAG.getNode(ISD::BITCAST, dl, VT,
5873 DAG.getNode(Opc, dl, ShVT, SrcOp,
5874 DAG.getConstant(NumBits,
5875 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5879 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5881 // Check if the scalar load can be widened into a vector load. And if
5882 // the address is "base + cst" see if the cst can be "absorbed" into
5883 // the shuffle mask.
5884 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5885 SDValue Ptr = LD->getBasePtr();
5886 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5888 EVT PVT = LD->getValueType(0);
5889 if (PVT != MVT::i32 && PVT != MVT::f32)
5894 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5895 FI = FINode->getIndex();
5897 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5898 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5899 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5900 Offset = Ptr.getConstantOperandVal(1);
5901 Ptr = Ptr.getOperand(0);
5906 // FIXME: 256-bit vector instructions don't require a strict alignment,
5907 // improve this code to support it better.
5908 unsigned RequiredAlign = VT.getSizeInBits()/8;
5909 SDValue Chain = LD->getChain();
5910 // Make sure the stack object alignment is at least 16 or 32.
5911 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5912 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5913 if (MFI->isFixedObjectIndex(FI)) {
5914 // Can't change the alignment. FIXME: It's possible to compute
5915 // the exact stack offset and reference FI + adjust offset instead.
5916 // If someone *really* cares about this. That's the way to implement it.
5919 MFI->setObjectAlignment(FI, RequiredAlign);
5923 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5924 // Ptr + (Offset & ~15).
5927 if ((Offset % RequiredAlign) & 3)
5929 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5931 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5932 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5934 int EltNo = (Offset - StartOffset) >> 2;
5935 unsigned NumElems = VT.getVectorNumElements();
5937 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5938 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5939 LD->getPointerInfo().getWithOffset(StartOffset),
5940 false, false, false, 0);
5942 SmallVector<int, 8> Mask;
5943 for (unsigned i = 0; i != NumElems; ++i)
5944 Mask.push_back(EltNo);
5946 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5952 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5953 /// vector of type 'VT', see if the elements can be replaced by a single large
5954 /// load which has the same value as a build_vector whose operands are 'elts'.
5956 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5958 /// FIXME: we'd also like to handle the case where the last elements are zero
5959 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5960 /// There's even a handy isZeroNode for that purpose.
5961 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5962 SDLoc &DL, SelectionDAG &DAG,
5963 bool isAfterLegalize) {
5964 EVT EltVT = VT.getVectorElementType();
5965 unsigned NumElems = Elts.size();
5967 LoadSDNode *LDBase = nullptr;
5968 unsigned LastLoadedElt = -1U;
5970 // For each element in the initializer, see if we've found a load or an undef.
5971 // If we don't find an initial load element, or later load elements are
5972 // non-consecutive, bail out.
5973 for (unsigned i = 0; i < NumElems; ++i) {
5974 SDValue Elt = Elts[i];
5976 if (!Elt.getNode() ||
5977 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5980 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5982 LDBase = cast<LoadSDNode>(Elt.getNode());
5986 if (Elt.getOpcode() == ISD::UNDEF)
5989 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5990 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5995 // If we have found an entire vector of loads and undefs, then return a large
5996 // load of the entire vector width starting at the base pointer. If we found
5997 // consecutive loads for the low half, generate a vzext_load node.
5998 if (LastLoadedElt == NumElems - 1) {
6000 if (isAfterLegalize &&
6001 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6004 SDValue NewLd = SDValue();
6006 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
6007 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6008 LDBase->getPointerInfo(),
6009 LDBase->isVolatile(), LDBase->isNonTemporal(),
6010 LDBase->isInvariant(), 0);
6011 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6012 LDBase->getPointerInfo(),
6013 LDBase->isVolatile(), LDBase->isNonTemporal(),
6014 LDBase->isInvariant(), LDBase->getAlignment());
6016 if (LDBase->hasAnyUseOfValue(1)) {
6017 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6019 SDValue(NewLd.getNode(), 1));
6020 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6021 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6022 SDValue(NewLd.getNode(), 1));
6027 if (NumElems == 4 && LastLoadedElt == 1 &&
6028 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6029 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6030 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6032 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6033 LDBase->getPointerInfo(),
6034 LDBase->getAlignment(),
6035 false/*isVolatile*/, true/*ReadMem*/,
6038 // Make sure the newly-created LOAD is in the same position as LDBase in
6039 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6040 // update uses of LDBase's output chain to use the TokenFactor.
6041 if (LDBase->hasAnyUseOfValue(1)) {
6042 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6043 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6044 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6045 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6046 SDValue(ResNode.getNode(), 1));
6049 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6054 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6055 /// to generate a splat value for the following cases:
6056 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6057 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6058 /// a scalar load, or a constant.
6059 /// The VBROADCAST node is returned when a pattern is found,
6060 /// or SDValue() otherwise.
6061 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6062 SelectionDAG &DAG) {
6063 // VBROADCAST requires AVX.
6064 // TODO: Splats could be generated for non-AVX CPUs using SSE
6065 // instructions, but there's less potential gain for only 128-bit vectors.
6066 if (!Subtarget->hasAVX())
6069 MVT VT = Op.getSimpleValueType();
6072 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6073 "Unsupported vector type for broadcast.");
6078 switch (Op.getOpcode()) {
6080 // Unknown pattern found.
6083 case ISD::BUILD_VECTOR: {
6084 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6085 BitVector UndefElements;
6086 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6088 // We need a splat of a single value to use broadcast, and it doesn't
6089 // make any sense if the value is only in one element of the vector.
6090 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6094 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6095 Ld.getOpcode() == ISD::ConstantFP);
6097 // Make sure that all of the users of a non-constant load are from the
6098 // BUILD_VECTOR node.
6099 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6104 case ISD::VECTOR_SHUFFLE: {
6105 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6107 // Shuffles must have a splat mask where the first element is
6109 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6112 SDValue Sc = Op.getOperand(0);
6113 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6114 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6116 if (!Subtarget->hasInt256())
6119 // Use the register form of the broadcast instruction available on AVX2.
6120 if (VT.getSizeInBits() >= 256)
6121 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6122 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6125 Ld = Sc.getOperand(0);
6126 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6127 Ld.getOpcode() == ISD::ConstantFP);
6129 // The scalar_to_vector node and the suspected
6130 // load node must have exactly one user.
6131 // Constants may have multiple users.
6133 // AVX-512 has register version of the broadcast
6134 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6135 Ld.getValueType().getSizeInBits() >= 32;
6136 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6143 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6144 bool IsGE256 = (VT.getSizeInBits() >= 256);
6146 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6147 // instruction to save 8 or more bytes of constant pool data.
6148 // TODO: If multiple splats are generated to load the same constant,
6149 // it may be detrimental to overall size. There needs to be a way to detect
6150 // that condition to know if this is truly a size win.
6151 const Function *F = DAG.getMachineFunction().getFunction();
6152 bool OptForSize = F->getAttributes().
6153 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6155 // Handle broadcasting a single constant scalar from the constant pool
6157 // On Sandybridge (no AVX2), it is still better to load a constant vector
6158 // from the constant pool and not to broadcast it from a scalar.
6159 // But override that restriction when optimizing for size.
6160 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6161 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6162 EVT CVT = Ld.getValueType();
6163 assert(!CVT.isVector() && "Must not broadcast a vector type");
6165 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6166 // For size optimization, also splat v2f64 and v2i64, and for size opt
6167 // with AVX2, also splat i8 and i16.
6168 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6169 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6170 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6171 const Constant *C = nullptr;
6172 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6173 C = CI->getConstantIntValue();
6174 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6175 C = CF->getConstantFPValue();
6177 assert(C && "Invalid constant type");
6179 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6180 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6181 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6182 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6183 MachinePointerInfo::getConstantPool(),
6184 false, false, false, Alignment);
6186 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6190 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6192 // Handle AVX2 in-register broadcasts.
6193 if (!IsLoad && Subtarget->hasInt256() &&
6194 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6195 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6197 // The scalar source must be a normal load.
6201 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6202 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6204 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6205 // double since there is no vbroadcastsd xmm
6206 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6207 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6208 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6211 // Unsupported broadcast.
6215 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6216 /// underlying vector and index.
6218 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6220 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6222 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6223 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6226 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6228 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6230 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6231 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6234 // In this case the vector is the extract_subvector expression and the index
6235 // is 2, as specified by the shuffle.
6236 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6237 SDValue ShuffleVec = SVOp->getOperand(0);
6238 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6239 assert(ShuffleVecVT.getVectorElementType() ==
6240 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6242 int ShuffleIdx = SVOp->getMaskElt(Idx);
6243 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6244 ExtractedFromVec = ShuffleVec;
6250 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6251 MVT VT = Op.getSimpleValueType();
6253 // Skip if insert_vec_elt is not supported.
6254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6255 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6259 unsigned NumElems = Op.getNumOperands();
6263 SmallVector<unsigned, 4> InsertIndices;
6264 SmallVector<int, 8> Mask(NumElems, -1);
6266 for (unsigned i = 0; i != NumElems; ++i) {
6267 unsigned Opc = Op.getOperand(i).getOpcode();
6269 if (Opc == ISD::UNDEF)
6272 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6273 // Quit if more than 1 elements need inserting.
6274 if (InsertIndices.size() > 1)
6277 InsertIndices.push_back(i);
6281 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6282 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6283 // Quit if non-constant index.
6284 if (!isa<ConstantSDNode>(ExtIdx))
6286 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6288 // Quit if extracted from vector of different type.
6289 if (ExtractedFromVec.getValueType() != VT)
6292 if (!VecIn1.getNode())
6293 VecIn1 = ExtractedFromVec;
6294 else if (VecIn1 != ExtractedFromVec) {
6295 if (!VecIn2.getNode())
6296 VecIn2 = ExtractedFromVec;
6297 else if (VecIn2 != ExtractedFromVec)
6298 // Quit if more than 2 vectors to shuffle
6302 if (ExtractedFromVec == VecIn1)
6304 else if (ExtractedFromVec == VecIn2)
6305 Mask[i] = Idx + NumElems;
6308 if (!VecIn1.getNode())
6311 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6312 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6313 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6314 unsigned Idx = InsertIndices[i];
6315 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6316 DAG.getIntPtrConstant(Idx));
6322 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6324 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6326 MVT VT = Op.getSimpleValueType();
6327 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6328 "Unexpected type in LowerBUILD_VECTORvXi1!");
6331 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6332 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6333 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6334 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6337 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6338 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6339 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6340 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6343 bool AllContants = true;
6344 uint64_t Immediate = 0;
6345 int NonConstIdx = -1;
6346 bool IsSplat = true;
6347 unsigned NumNonConsts = 0;
6348 unsigned NumConsts = 0;
6349 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6350 SDValue In = Op.getOperand(idx);
6351 if (In.getOpcode() == ISD::UNDEF)
6353 if (!isa<ConstantSDNode>(In)) {
6354 AllContants = false;
6360 if (cast<ConstantSDNode>(In)->getZExtValue())
6361 Immediate |= (1ULL << idx);
6363 if (In != Op.getOperand(0))
6368 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6369 DAG.getConstant(Immediate, MVT::i16));
6370 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6371 DAG.getIntPtrConstant(0));
6374 if (NumNonConsts == 1 && NonConstIdx != 0) {
6377 SDValue VecAsImm = DAG.getConstant(Immediate,
6378 MVT::getIntegerVT(VT.getSizeInBits()));
6379 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6382 DstVec = DAG.getUNDEF(VT);
6383 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6384 Op.getOperand(NonConstIdx),
6385 DAG.getIntPtrConstant(NonConstIdx));
6387 if (!IsSplat && (NonConstIdx != 0))
6388 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6389 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6392 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6393 DAG.getConstant(-1, SelectVT),
6394 DAG.getConstant(0, SelectVT));
6396 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6397 DAG.getConstant((Immediate | 1), SelectVT),
6398 DAG.getConstant(Immediate, SelectVT));
6399 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6402 /// \brief Return true if \p N implements a horizontal binop and return the
6403 /// operands for the horizontal binop into V0 and V1.
6405 /// This is a helper function of PerformBUILD_VECTORCombine.
6406 /// This function checks that the build_vector \p N in input implements a
6407 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6408 /// operation to match.
6409 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6410 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6411 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6414 /// This function only analyzes elements of \p N whose indices are
6415 /// in range [BaseIdx, LastIdx).
6416 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6418 unsigned BaseIdx, unsigned LastIdx,
6419 SDValue &V0, SDValue &V1) {
6420 EVT VT = N->getValueType(0);
6422 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6423 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6424 "Invalid Vector in input!");
6426 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6427 bool CanFold = true;
6428 unsigned ExpectedVExtractIdx = BaseIdx;
6429 unsigned NumElts = LastIdx - BaseIdx;
6430 V0 = DAG.getUNDEF(VT);
6431 V1 = DAG.getUNDEF(VT);
6433 // Check if N implements a horizontal binop.
6434 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6435 SDValue Op = N->getOperand(i + BaseIdx);
6438 if (Op->getOpcode() == ISD::UNDEF) {
6439 // Update the expected vector extract index.
6440 if (i * 2 == NumElts)
6441 ExpectedVExtractIdx = BaseIdx;
6442 ExpectedVExtractIdx += 2;
6446 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6451 SDValue Op0 = Op.getOperand(0);
6452 SDValue Op1 = Op.getOperand(1);
6454 // Try to match the following pattern:
6455 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6456 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6457 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6458 Op0.getOperand(0) == Op1.getOperand(0) &&
6459 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6460 isa<ConstantSDNode>(Op1.getOperand(1)));
6464 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6465 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6467 if (i * 2 < NumElts) {
6468 if (V0.getOpcode() == ISD::UNDEF)
6469 V0 = Op0.getOperand(0);
6471 if (V1.getOpcode() == ISD::UNDEF)
6472 V1 = Op0.getOperand(0);
6473 if (i * 2 == NumElts)
6474 ExpectedVExtractIdx = BaseIdx;
6477 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6478 if (I0 == ExpectedVExtractIdx)
6479 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6480 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6481 // Try to match the following dag sequence:
6482 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6483 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6487 ExpectedVExtractIdx += 2;
6493 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6494 /// a concat_vector.
6496 /// This is a helper function of PerformBUILD_VECTORCombine.
6497 /// This function expects two 256-bit vectors called V0 and V1.
6498 /// At first, each vector is split into two separate 128-bit vectors.
6499 /// Then, the resulting 128-bit vectors are used to implement two
6500 /// horizontal binary operations.
6502 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6504 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6505 /// the two new horizontal binop.
6506 /// When Mode is set, the first horizontal binop dag node would take as input
6507 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6508 /// horizontal binop dag node would take as input the lower 128-bit of V1
6509 /// and the upper 128-bit of V1.
6511 /// HADD V0_LO, V0_HI
6512 /// HADD V1_LO, V1_HI
6514 /// Otherwise, the first horizontal binop dag node takes as input the lower
6515 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6516 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6518 /// HADD V0_LO, V1_LO
6519 /// HADD V0_HI, V1_HI
6521 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6522 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6523 /// the upper 128-bits of the result.
6524 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6525 SDLoc DL, SelectionDAG &DAG,
6526 unsigned X86Opcode, bool Mode,
6527 bool isUndefLO, bool isUndefHI) {
6528 EVT VT = V0.getValueType();
6529 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6530 "Invalid nodes in input!");
6532 unsigned NumElts = VT.getVectorNumElements();
6533 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6534 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6535 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6536 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6537 EVT NewVT = V0_LO.getValueType();
6539 SDValue LO = DAG.getUNDEF(NewVT);
6540 SDValue HI = DAG.getUNDEF(NewVT);
6543 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6544 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6545 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6546 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6547 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6549 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6550 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6551 V1_LO->getOpcode() != ISD::UNDEF))
6552 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6554 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6555 V1_HI->getOpcode() != ISD::UNDEF))
6556 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6559 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6562 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6563 /// sequence of 'vadd + vsub + blendi'.
6564 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6565 const X86Subtarget *Subtarget) {
6567 EVT VT = BV->getValueType(0);
6568 unsigned NumElts = VT.getVectorNumElements();
6569 SDValue InVec0 = DAG.getUNDEF(VT);
6570 SDValue InVec1 = DAG.getUNDEF(VT);
6572 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6573 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6575 // Odd-numbered elements in the input build vector are obtained from
6576 // adding two integer/float elements.
6577 // Even-numbered elements in the input build vector are obtained from
6578 // subtracting two integer/float elements.
6579 unsigned ExpectedOpcode = ISD::FSUB;
6580 unsigned NextExpectedOpcode = ISD::FADD;
6581 bool AddFound = false;
6582 bool SubFound = false;
6584 for (unsigned i = 0, e = NumElts; i != e; i++) {
6585 SDValue Op = BV->getOperand(i);
6587 // Skip 'undef' values.
6588 unsigned Opcode = Op.getOpcode();
6589 if (Opcode == ISD::UNDEF) {
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6594 // Early exit if we found an unexpected opcode.
6595 if (Opcode != ExpectedOpcode)
6598 SDValue Op0 = Op.getOperand(0);
6599 SDValue Op1 = Op.getOperand(1);
6601 // Try to match the following pattern:
6602 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6603 // Early exit if we cannot match that sequence.
6604 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6605 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6606 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6607 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6608 Op0.getOperand(1) != Op1.getOperand(1))
6611 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6615 // We found a valid add/sub node. Update the information accordingly.
6621 // Update InVec0 and InVec1.
6622 if (InVec0.getOpcode() == ISD::UNDEF)
6623 InVec0 = Op0.getOperand(0);
6624 if (InVec1.getOpcode() == ISD::UNDEF)
6625 InVec1 = Op1.getOperand(0);
6627 // Make sure that operands in input to each add/sub node always
6628 // come from a same pair of vectors.
6629 if (InVec0 != Op0.getOperand(0)) {
6630 if (ExpectedOpcode == ISD::FSUB)
6633 // FADD is commutable. Try to commute the operands
6634 // and then test again.
6635 std::swap(Op0, Op1);
6636 if (InVec0 != Op0.getOperand(0))
6640 if (InVec1 != Op1.getOperand(0))
6643 // Update the pair of expected opcodes.
6644 std::swap(ExpectedOpcode, NextExpectedOpcode);
6647 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6648 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6649 InVec1.getOpcode() != ISD::UNDEF)
6650 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6655 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6656 const X86Subtarget *Subtarget) {
6658 EVT VT = N->getValueType(0);
6659 unsigned NumElts = VT.getVectorNumElements();
6660 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6661 SDValue InVec0, InVec1;
6663 // Try to match an ADDSUB.
6664 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6665 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6666 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6667 if (Value.getNode())
6671 // Try to match horizontal ADD/SUB.
6672 unsigned NumUndefsLO = 0;
6673 unsigned NumUndefsHI = 0;
6674 unsigned Half = NumElts/2;
6676 // Count the number of UNDEF operands in the build_vector in input.
6677 for (unsigned i = 0, e = Half; i != e; ++i)
6678 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6681 for (unsigned i = Half, e = NumElts; i != e; ++i)
6682 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6685 // Early exit if this is either a build_vector of all UNDEFs or all the
6686 // operands but one are UNDEF.
6687 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6690 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6691 // Try to match an SSE3 float HADD/HSUB.
6692 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6693 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6695 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6696 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6697 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6698 // Try to match an SSSE3 integer HADD/HSUB.
6699 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6700 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6702 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6703 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6706 if (!Subtarget->hasAVX())
6709 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6710 // Try to match an AVX horizontal add/sub of packed single/double
6711 // precision floating point values from 256-bit vectors.
6712 SDValue InVec2, InVec3;
6713 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6714 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6715 ((InVec0.getOpcode() == ISD::UNDEF ||
6716 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6717 ((InVec1.getOpcode() == ISD::UNDEF ||
6718 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6719 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6721 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6722 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6723 ((InVec0.getOpcode() == ISD::UNDEF ||
6724 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6725 ((InVec1.getOpcode() == ISD::UNDEF ||
6726 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6727 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6728 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6729 // Try to match an AVX2 horizontal add/sub of signed integers.
6730 SDValue InVec2, InVec3;
6732 bool CanFold = true;
6734 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6735 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6736 ((InVec0.getOpcode() == ISD::UNDEF ||
6737 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6738 ((InVec1.getOpcode() == ISD::UNDEF ||
6739 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6740 X86Opcode = X86ISD::HADD;
6741 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6742 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6743 ((InVec0.getOpcode() == ISD::UNDEF ||
6744 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6745 ((InVec1.getOpcode() == ISD::UNDEF ||
6746 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6747 X86Opcode = X86ISD::HSUB;
6752 // Fold this build_vector into a single horizontal add/sub.
6753 // Do this only if the target has AVX2.
6754 if (Subtarget->hasAVX2())
6755 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6757 // Do not try to expand this build_vector into a pair of horizontal
6758 // add/sub if we can emit a pair of scalar add/sub.
6759 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6762 // Convert this build_vector into a pair of horizontal binop followed by
6764 bool isUndefLO = NumUndefsLO == Half;
6765 bool isUndefHI = NumUndefsHI == Half;
6766 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6767 isUndefLO, isUndefHI);
6771 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6772 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6774 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6775 X86Opcode = X86ISD::HADD;
6776 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6777 X86Opcode = X86ISD::HSUB;
6778 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6779 X86Opcode = X86ISD::FHADD;
6780 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6781 X86Opcode = X86ISD::FHSUB;
6785 // Don't try to expand this build_vector into a pair of horizontal add/sub
6786 // if we can simply emit a pair of scalar add/sub.
6787 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6790 // Convert this build_vector into two horizontal add/sub followed by
6792 bool isUndefLO = NumUndefsLO == Half;
6793 bool isUndefHI = NumUndefsHI == Half;
6794 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6795 isUndefLO, isUndefHI);
6802 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6805 MVT VT = Op.getSimpleValueType();
6806 MVT ExtVT = VT.getVectorElementType();
6807 unsigned NumElems = Op.getNumOperands();
6809 // Generate vectors for predicate vectors.
6810 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6811 return LowerBUILD_VECTORvXi1(Op, DAG);
6813 // Vectors containing all zeros can be matched by pxor and xorps later
6814 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6815 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6816 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6817 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6820 return getZeroVector(VT, Subtarget, DAG, dl);
6823 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6824 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6825 // vpcmpeqd on 256-bit vectors.
6826 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6827 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6830 if (!VT.is512BitVector())
6831 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6834 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6835 if (Broadcast.getNode())
6838 unsigned EVTBits = ExtVT.getSizeInBits();
6840 unsigned NumZero = 0;
6841 unsigned NumNonZero = 0;
6842 unsigned NonZeros = 0;
6843 bool IsAllConstants = true;
6844 SmallSet<SDValue, 8> Values;
6845 for (unsigned i = 0; i < NumElems; ++i) {
6846 SDValue Elt = Op.getOperand(i);
6847 if (Elt.getOpcode() == ISD::UNDEF)
6850 if (Elt.getOpcode() != ISD::Constant &&
6851 Elt.getOpcode() != ISD::ConstantFP)
6852 IsAllConstants = false;
6853 if (X86::isZeroNode(Elt))
6856 NonZeros |= (1 << i);
6861 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6862 if (NumNonZero == 0)
6863 return DAG.getUNDEF(VT);
6865 // Special case for single non-zero, non-undef, element.
6866 if (NumNonZero == 1) {
6867 unsigned Idx = countTrailingZeros(NonZeros);
6868 SDValue Item = Op.getOperand(Idx);
6870 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6871 // the value are obviously zero, truncate the value to i32 and do the
6872 // insertion that way. Only do this if the value is non-constant or if the
6873 // value is a constant being inserted into element 0. It is cheaper to do
6874 // a constant pool load than it is to do a movd + shuffle.
6875 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6876 (!IsAllConstants || Idx == 0)) {
6877 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6879 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6880 EVT VecVT = MVT::v4i32;
6881 unsigned VecElts = 4;
6883 // Truncate the value (which may itself be a constant) to i32, and
6884 // convert it to a vector with movd (S2V+shuffle to zero extend).
6885 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6886 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6888 // If using the new shuffle lowering, just directly insert this.
6889 if (ExperimentalVectorShuffleLowering)
6891 ISD::BITCAST, dl, VT,
6892 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6894 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6896 // Now we have our 32-bit value zero extended in the low element of
6897 // a vector. If Idx != 0, swizzle it into place.
6899 SmallVector<int, 4> Mask;
6900 Mask.push_back(Idx);
6901 for (unsigned i = 1; i != VecElts; ++i)
6903 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6906 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6910 // If we have a constant or non-constant insertion into the low element of
6911 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6912 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6913 // depending on what the source datatype is.
6916 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6918 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6919 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6920 if (VT.is256BitVector() || VT.is512BitVector()) {
6921 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6922 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6923 Item, DAG.getIntPtrConstant(0));
6925 assert(VT.is128BitVector() && "Expected an SSE value type!");
6926 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6927 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6928 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6931 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6932 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6933 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6934 if (VT.is256BitVector()) {
6935 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6936 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6938 assert(VT.is128BitVector() && "Expected an SSE value type!");
6939 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6941 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6945 // Is it a vector logical left shift?
6946 if (NumElems == 2 && Idx == 1 &&
6947 X86::isZeroNode(Op.getOperand(0)) &&
6948 !X86::isZeroNode(Op.getOperand(1))) {
6949 unsigned NumBits = VT.getSizeInBits();
6950 return getVShift(true, VT,
6951 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6952 VT, Op.getOperand(1)),
6953 NumBits/2, DAG, *this, dl);
6956 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6959 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6960 // is a non-constant being inserted into an element other than the low one,
6961 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6962 // movd/movss) to move this into the low element, then shuffle it into
6964 if (EVTBits == 32) {
6965 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6967 // If using the new shuffle lowering, just directly insert this.
6968 if (ExperimentalVectorShuffleLowering)
6969 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6971 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6972 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6973 SmallVector<int, 8> MaskVec;
6974 for (unsigned i = 0; i != NumElems; ++i)
6975 MaskVec.push_back(i == Idx ? 0 : 1);
6976 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6980 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6981 if (Values.size() == 1) {
6982 if (EVTBits == 32) {
6983 // Instead of a shuffle like this:
6984 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6985 // Check if it's possible to issue this instead.
6986 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6987 unsigned Idx = countTrailingZeros(NonZeros);
6988 SDValue Item = Op.getOperand(Idx);
6989 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6990 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6995 // A vector full of immediates; various special cases are already
6996 // handled, so this is best done with a single constant-pool load.
7000 // For AVX-length vectors, build the individual 128-bit pieces and use
7001 // shuffles to put them in place.
7002 if (VT.is256BitVector() || VT.is512BitVector()) {
7003 SmallVector<SDValue, 64> V;
7004 for (unsigned i = 0; i != NumElems; ++i)
7005 V.push_back(Op.getOperand(i));
7007 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7009 // Build both the lower and upper subvector.
7010 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7011 makeArrayRef(&V[0], NumElems/2));
7012 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7013 makeArrayRef(&V[NumElems / 2], NumElems/2));
7015 // Recreate the wider vector with the lower and upper part.
7016 if (VT.is256BitVector())
7017 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7018 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7021 // Let legalizer expand 2-wide build_vectors.
7022 if (EVTBits == 64) {
7023 if (NumNonZero == 1) {
7024 // One half is zero or undef.
7025 unsigned Idx = countTrailingZeros(NonZeros);
7026 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7027 Op.getOperand(Idx));
7028 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7033 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7034 if (EVTBits == 8 && NumElems == 16) {
7035 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7037 if (V.getNode()) return V;
7040 if (EVTBits == 16 && NumElems == 8) {
7041 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7043 if (V.getNode()) return V;
7046 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7047 if (EVTBits == 32 && NumElems == 4) {
7048 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7053 // If element VT is == 32 bits, turn it into a number of shuffles.
7054 SmallVector<SDValue, 8> V(NumElems);
7055 if (NumElems == 4 && NumZero > 0) {
7056 for (unsigned i = 0; i < 4; ++i) {
7057 bool isZero = !(NonZeros & (1 << i));
7059 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7061 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7064 for (unsigned i = 0; i < 2; ++i) {
7065 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7068 V[i] = V[i*2]; // Must be a zero vector.
7071 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7074 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7077 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7082 bool Reverse1 = (NonZeros & 0x3) == 2;
7083 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7087 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7088 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7090 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7093 if (Values.size() > 1 && VT.is128BitVector()) {
7094 // Check for a build vector of consecutive loads.
7095 for (unsigned i = 0; i < NumElems; ++i)
7096 V[i] = Op.getOperand(i);
7098 // Check for elements which are consecutive loads.
7099 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7103 // Check for a build vector from mostly shuffle plus few inserting.
7104 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7108 // For SSE 4.1, use insertps to put the high elements into the low element.
7109 if (getSubtarget()->hasSSE41()) {
7111 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7112 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7114 Result = DAG.getUNDEF(VT);
7116 for (unsigned i = 1; i < NumElems; ++i) {
7117 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7118 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7119 Op.getOperand(i), DAG.getIntPtrConstant(i));
7124 // Otherwise, expand into a number of unpckl*, start by extending each of
7125 // our (non-undef) elements to the full vector width with the element in the
7126 // bottom slot of the vector (which generates no code for SSE).
7127 for (unsigned i = 0; i < NumElems; ++i) {
7128 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7129 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7131 V[i] = DAG.getUNDEF(VT);
7134 // Next, we iteratively mix elements, e.g. for v4f32:
7135 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7136 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7137 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7138 unsigned EltStride = NumElems >> 1;
7139 while (EltStride != 0) {
7140 for (unsigned i = 0; i < EltStride; ++i) {
7141 // If V[i+EltStride] is undef and this is the first round of mixing,
7142 // then it is safe to just drop this shuffle: V[i] is already in the
7143 // right place, the one element (since it's the first round) being
7144 // inserted as undef can be dropped. This isn't safe for successive
7145 // rounds because they will permute elements within both vectors.
7146 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7147 EltStride == NumElems/2)
7150 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7159 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7160 // to create 256-bit vectors from two other 128-bit ones.
7161 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7163 MVT ResVT = Op.getSimpleValueType();
7165 assert((ResVT.is256BitVector() ||
7166 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7168 SDValue V1 = Op.getOperand(0);
7169 SDValue V2 = Op.getOperand(1);
7170 unsigned NumElems = ResVT.getVectorNumElements();
7171 if(ResVT.is256BitVector())
7172 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7174 if (Op.getNumOperands() == 4) {
7175 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7176 ResVT.getVectorNumElements()/2);
7177 SDValue V3 = Op.getOperand(2);
7178 SDValue V4 = Op.getOperand(3);
7179 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7180 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7182 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7185 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7186 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7187 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7188 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7189 Op.getNumOperands() == 4)));
7191 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7192 // from two other 128-bit ones.
7194 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7195 return LowerAVXCONCAT_VECTORS(Op, DAG);
7199 //===----------------------------------------------------------------------===//
7200 // Vector shuffle lowering
7202 // This is an experimental code path for lowering vector shuffles on x86. It is
7203 // designed to handle arbitrary vector shuffles and blends, gracefully
7204 // degrading performance as necessary. It works hard to recognize idiomatic
7205 // shuffles and lower them to optimal instruction patterns without leaving
7206 // a framework that allows reasonably efficient handling of all vector shuffle
7208 //===----------------------------------------------------------------------===//
7210 /// \brief Tiny helper function to identify a no-op mask.
7212 /// This is a somewhat boring predicate function. It checks whether the mask
7213 /// array input, which is assumed to be a single-input shuffle mask of the kind
7214 /// used by the X86 shuffle instructions (not a fully general
7215 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7216 /// in-place shuffle are 'no-op's.
7217 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7218 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7219 if (Mask[i] != -1 && Mask[i] != i)
7224 /// \brief Helper function to classify a mask as a single-input mask.
7226 /// This isn't a generic single-input test because in the vector shuffle
7227 /// lowering we canonicalize single inputs to be the first input operand. This
7228 /// means we can more quickly test for a single input by only checking whether
7229 /// an input from the second operand exists. We also assume that the size of
7230 /// mask corresponds to the size of the input vectors which isn't true in the
7231 /// fully general case.
7232 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7234 if (M >= (int)Mask.size())
7239 /// \brief Test whether there are elements crossing 128-bit lanes in this
7242 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7243 /// and we routinely test for these.
7244 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7245 int LaneSize = 128 / VT.getScalarSizeInBits();
7246 int Size = Mask.size();
7247 for (int i = 0; i < Size; ++i)
7248 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7253 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7255 /// This checks a shuffle mask to see if it is performing the same
7256 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7257 /// that it is also not lane-crossing. It may however involve a blend from the
7258 /// same lane of a second vector.
7260 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7261 /// non-trivial to compute in the face of undef lanes. The representation is
7262 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7263 /// entries from both V1 and V2 inputs to the wider mask.
7265 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7266 SmallVectorImpl<int> &RepeatedMask) {
7267 int LaneSize = 128 / VT.getScalarSizeInBits();
7268 RepeatedMask.resize(LaneSize, -1);
7269 int Size = Mask.size();
7270 for (int i = 0; i < Size; ++i) {
7273 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7274 // This entry crosses lanes, so there is no way to model this shuffle.
7277 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7278 if (RepeatedMask[i % LaneSize] == -1)
7279 // This is the first non-undef entry in this slot of a 128-bit lane.
7280 RepeatedMask[i % LaneSize] =
7281 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7282 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7283 // Found a mismatch with the repeated mask.
7289 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7290 // 2013 will allow us to use it as a non-type template parameter.
7293 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7295 /// See its documentation for details.
7296 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7297 if (Mask.size() != Args.size())
7299 for (int i = 0, e = Mask.size(); i < e; ++i) {
7300 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7301 if (Mask[i] != -1 && Mask[i] != *Args[i])
7309 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7312 /// This is a fast way to test a shuffle mask against a fixed pattern:
7314 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7316 /// It returns true if the mask is exactly as wide as the argument list, and
7317 /// each element of the mask is either -1 (signifying undef) or the value given
7318 /// in the argument.
7319 static const VariadicFunction1<
7320 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7322 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7324 /// This helper function produces an 8-bit shuffle immediate corresponding to
7325 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7326 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7329 /// NB: We rely heavily on "undef" masks preserving the input lane.
7330 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7331 SelectionDAG &DAG) {
7332 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7333 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7334 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7335 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7336 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7339 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7340 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7341 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7342 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7343 return DAG.getConstant(Imm, MVT::i8);
7346 /// \brief Try to emit a blend instruction for a shuffle.
7348 /// This doesn't do any checks for the availability of instructions for blending
7349 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7350 /// be matched in the backend with the type given. What it does check for is
7351 /// that the shuffle mask is in fact a blend.
7352 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7353 SDValue V2, ArrayRef<int> Mask,
7354 const X86Subtarget *Subtarget,
7355 SelectionDAG &DAG) {
7357 unsigned BlendMask = 0;
7358 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7359 if (Mask[i] >= Size) {
7360 if (Mask[i] != i + Size)
7361 return SDValue(); // Shuffled V2 input!
7362 BlendMask |= 1u << i;
7365 if (Mask[i] >= 0 && Mask[i] != i)
7366 return SDValue(); // Shuffled V1 input!
7368 switch (VT.SimpleTy) {
7373 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7374 DAG.getConstant(BlendMask, MVT::i8));
7378 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7382 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7383 // that instruction.
7384 if (Subtarget->hasAVX2()) {
7385 // Scale the blend by the number of 32-bit dwords per element.
7386 int Scale = VT.getScalarSizeInBits() / 32;
7388 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7389 if (Mask[i] >= Size)
7390 for (int j = 0; j < Scale; ++j)
7391 BlendMask |= 1u << (i * Scale + j);
7393 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7394 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7395 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7396 return DAG.getNode(ISD::BITCAST, DL, VT,
7397 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7398 DAG.getConstant(BlendMask, MVT::i8)));
7402 // For integer shuffles we need to expand the mask and cast the inputs to
7403 // v8i16s prior to blending.
7404 int Scale = 8 / VT.getVectorNumElements();
7406 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7407 if (Mask[i] >= Size)
7408 for (int j = 0; j < Scale; ++j)
7409 BlendMask |= 1u << (i * Scale + j);
7411 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7412 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7413 return DAG.getNode(ISD::BITCAST, DL, VT,
7414 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7415 DAG.getConstant(BlendMask, MVT::i8)));
7419 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7420 SmallVector<int, 8> RepeatedMask;
7421 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7422 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7423 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7425 for (int i = 0; i < 8; ++i)
7426 if (RepeatedMask[i] >= 16)
7427 BlendMask |= 1u << i;
7428 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7429 DAG.getConstant(BlendMask, MVT::i8));
7434 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7435 // Scale the blend by the number of bytes per element.
7436 int Scale = VT.getScalarSizeInBits() / 8;
7437 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7439 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7440 // mix of LLVM's code generator and the x86 backend. We tell the code
7441 // generator that boolean values in the elements of an x86 vector register
7442 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7443 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7444 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7445 // of the element (the remaining are ignored) and 0 in that high bit would
7446 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7447 // the LLVM model for boolean values in vector elements gets the relevant
7448 // bit set, it is set backwards and over constrained relative to x86's
7450 SDValue VSELECTMask[32];
7451 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7452 for (int j = 0; j < Scale; ++j)
7453 VSELECTMask[Scale * i + j] =
7454 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7455 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7457 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7458 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7460 ISD::BITCAST, DL, VT,
7461 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7462 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7467 llvm_unreachable("Not a supported integer vector type!");
7471 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7472 /// unblended shuffles followed by an unshuffled blend.
7474 /// This matches the extremely common pattern for handling combined
7475 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7477 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7481 SelectionDAG &DAG) {
7482 // Shuffle the input elements into the desired positions in V1 and V2 and
7483 // blend them together.
7484 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7485 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7486 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7487 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7488 if (Mask[i] >= 0 && Mask[i] < Size) {
7489 V1Mask[i] = Mask[i];
7491 } else if (Mask[i] >= Size) {
7492 V2Mask[i] = Mask[i] - Size;
7493 BlendMask[i] = i + Size;
7496 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7497 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7498 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7501 /// \brief Try to lower a vector shuffle as a byte rotation.
7503 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7504 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7505 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7506 /// try to generically lower a vector shuffle through such an pattern. It
7507 /// does not check for the profitability of lowering either as PALIGNR or
7508 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7509 /// This matches shuffle vectors that look like:
7511 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7513 /// Essentially it concatenates V1 and V2, shifts right by some number of
7514 /// elements, and takes the low elements as the result. Note that while this is
7515 /// specified as a *right shift* because x86 is little-endian, it is a *left
7516 /// rotate* of the vector lanes.
7518 /// Note that this only handles 128-bit vector widths currently.
7519 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7522 const X86Subtarget *Subtarget,
7523 SelectionDAG &DAG) {
7524 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7526 // We need to detect various ways of spelling a rotation:
7527 // [11, 12, 13, 14, 15, 0, 1, 2]
7528 // [-1, 12, 13, 14, -1, -1, 1, -1]
7529 // [-1, -1, -1, -1, -1, -1, 1, 2]
7530 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7531 // [-1, 4, 5, 6, -1, -1, 9, -1]
7532 // [-1, 4, 5, 6, -1, -1, -1, -1]
7535 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7538 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7540 // Based on the mod-Size value of this mask element determine where
7541 // a rotated vector would have started.
7542 int StartIdx = i - (Mask[i] % Size);
7544 // The identity rotation isn't interesting, stop.
7547 // If we found the tail of a vector the rotation must be the missing
7548 // front. If we found the head of a vector, it must be how much of the head.
7549 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7552 Rotation = CandidateRotation;
7553 else if (Rotation != CandidateRotation)
7554 // The rotations don't match, so we can't match this mask.
7557 // Compute which value this mask is pointing at.
7558 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7560 // Compute which of the two target values this index should be assigned to.
7561 // This reflects whether the high elements are remaining or the low elements
7563 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7565 // Either set up this value if we've not encountered it before, or check
7566 // that it remains consistent.
7569 else if (TargetV != MaskV)
7570 // This may be a rotation, but it pulls from the inputs in some
7571 // unsupported interleaving.
7575 // Check that we successfully analyzed the mask, and normalize the results.
7576 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7577 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7583 assert(VT.getSizeInBits() == 128 &&
7584 "Rotate-based lowering only supports 128-bit lowering!");
7585 assert(Mask.size() <= 16 &&
7586 "Can shuffle at most 16 bytes in a 128-bit vector!");
7588 // The actual rotate instruction rotates bytes, so we need to scale the
7589 // rotation based on how many bytes are in the vector.
7590 int Scale = 16 / Mask.size();
7592 // SSSE3 targets can use the palignr instruction
7593 if (Subtarget->hasSSSE3()) {
7594 // Cast the inputs to v16i8 to match PALIGNR.
7595 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7596 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7598 return DAG.getNode(ISD::BITCAST, DL, VT,
7599 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7600 DAG.getConstant(Rotation * Scale, MVT::i8)));
7603 // Default SSE2 implementation
7604 int LoByteShift = 16 - Rotation * Scale;
7605 int HiByteShift = Rotation * Scale;
7607 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7608 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7609 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7611 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7612 DAG.getConstant(8 * LoByteShift, MVT::i8));
7613 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7614 DAG.getConstant(8 * HiByteShift, MVT::i8));
7615 return DAG.getNode(ISD::BITCAST, DL, VT,
7616 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7619 /// \brief Compute whether each element of a shuffle is zeroable.
7621 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7622 /// Either it is an undef element in the shuffle mask, the element of the input
7623 /// referenced is undef, or the element of the input referenced is known to be
7624 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7625 /// as many lanes with this technique as possible to simplify the remaining
7627 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7628 SDValue V1, SDValue V2) {
7629 SmallBitVector Zeroable(Mask.size(), false);
7631 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7632 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7634 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7636 // Handle the easy cases.
7637 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7642 // If this is an index into a build_vector node, dig out the input value and
7644 SDValue V = M < Size ? V1 : V2;
7645 if (V.getOpcode() != ISD::BUILD_VECTOR)
7648 SDValue Input = V.getOperand(M % Size);
7649 // The UNDEF opcode check really should be dead code here, but not quite
7650 // worth asserting on (it isn't invalid, just unexpected).
7651 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7658 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7660 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7661 /// byte-shift instructions. The mask must consist of a shifted sequential
7662 /// shuffle from one of the input vectors and zeroable elements for the
7663 /// remaining 'shifted in' elements.
7665 /// Note that this only handles 128-bit vector widths currently.
7666 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7667 SDValue V2, ArrayRef<int> Mask,
7668 SelectionDAG &DAG) {
7669 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7671 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7673 int Size = Mask.size();
7674 int Scale = 16 / Size;
7676 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7677 ArrayRef<int> Mask) {
7678 for (int i = StartIndex; i < EndIndex; i++) {
7681 if (i + Base != Mask[i] - MaskOffset)
7687 for (int Shift = 1; Shift < Size; Shift++) {
7688 int ByteShift = Shift * Scale;
7690 // PSRLDQ : (little-endian) right byte shift
7691 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7692 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7693 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7694 bool ZeroableRight = true;
7695 for (int i = Size - Shift; i < Size; i++) {
7696 ZeroableRight &= Zeroable[i];
7699 if (ZeroableRight) {
7700 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7701 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7703 if (ValidShiftRight1 || ValidShiftRight2) {
7704 // Cast the inputs to v2i64 to match PSRLDQ.
7705 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7706 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7707 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7708 DAG.getConstant(ByteShift * 8, MVT::i8));
7709 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7713 // PSLLDQ : (little-endian) left byte shift
7714 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7715 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7716 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7717 bool ZeroableLeft = true;
7718 for (int i = 0; i < Shift; i++) {
7719 ZeroableLeft &= Zeroable[i];
7723 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7724 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7726 if (ValidShiftLeft1 || ValidShiftLeft2) {
7727 // Cast the inputs to v2i64 to match PSLLDQ.
7728 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7729 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7730 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7731 DAG.getConstant(ByteShift * 8, MVT::i8));
7732 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7740 /// \brief Lower a vector shuffle as a zero or any extension.
7742 /// Given a specific number of elements, element bit width, and extension
7743 /// stride, produce either a zero or any extension based on the available
7744 /// features of the subtarget.
7745 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7746 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7747 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7748 assert(Scale > 1 && "Need a scale to extend.");
7749 int EltBits = VT.getSizeInBits() / NumElements;
7750 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7751 "Only 8, 16, and 32 bit elements can be extended.");
7752 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7754 // Found a valid zext mask! Try various lowering strategies based on the
7755 // input type and available ISA extensions.
7756 if (Subtarget->hasSSE41()) {
7757 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7758 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7759 NumElements / Scale);
7760 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7761 return DAG.getNode(ISD::BITCAST, DL, VT,
7762 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7765 // For any extends we can cheat for larger element sizes and use shuffle
7766 // instructions that can fold with a load and/or copy.
7767 if (AnyExt && EltBits == 32) {
7768 int PSHUFDMask[4] = {0, -1, 1, -1};
7770 ISD::BITCAST, DL, VT,
7771 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7772 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7773 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7775 if (AnyExt && EltBits == 16 && Scale > 2) {
7776 int PSHUFDMask[4] = {0, -1, 0, -1};
7777 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7778 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7779 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7780 int PSHUFHWMask[4] = {1, -1, -1, -1};
7782 ISD::BITCAST, DL, VT,
7783 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7784 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7785 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7788 // If this would require more than 2 unpack instructions to expand, use
7789 // pshufb when available. We can only use more than 2 unpack instructions
7790 // when zero extending i8 elements which also makes it easier to use pshufb.
7791 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7792 assert(NumElements == 16 && "Unexpected byte vector width!");
7793 SDValue PSHUFBMask[16];
7794 for (int i = 0; i < 16; ++i)
7796 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7797 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7798 return DAG.getNode(ISD::BITCAST, DL, VT,
7799 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7800 DAG.getNode(ISD::BUILD_VECTOR, DL,
7801 MVT::v16i8, PSHUFBMask)));
7804 // Otherwise emit a sequence of unpacks.
7806 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7807 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7808 : getZeroVector(InputVT, Subtarget, DAG, DL);
7809 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7810 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7814 } while (Scale > 1);
7815 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7818 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7820 /// This routine will try to do everything in its power to cleverly lower
7821 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7822 /// check for the profitability of this lowering, it tries to aggressively
7823 /// match this pattern. It will use all of the micro-architectural details it
7824 /// can to emit an efficient lowering. It handles both blends with all-zero
7825 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7826 /// masking out later).
7828 /// The reason we have dedicated lowering for zext-style shuffles is that they
7829 /// are both incredibly common and often quite performance sensitive.
7830 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7831 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7832 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7833 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7835 int Bits = VT.getSizeInBits();
7836 int NumElements = Mask.size();
7838 // Define a helper function to check a particular ext-scale and lower to it if
7840 auto Lower = [&](int Scale) -> SDValue {
7843 for (int i = 0; i < NumElements; ++i) {
7845 continue; // Valid anywhere but doesn't tell us anything.
7846 if (i % Scale != 0) {
7847 // Each of the extend elements needs to be zeroable.
7851 // We no lorger are in the anyext case.
7856 // Each of the base elements needs to be consecutive indices into the
7857 // same input vector.
7858 SDValue V = Mask[i] < NumElements ? V1 : V2;
7861 else if (InputV != V)
7862 return SDValue(); // Flip-flopping inputs.
7864 if (Mask[i] % NumElements != i / Scale)
7865 return SDValue(); // Non-consecutive strided elemenst.
7868 // If we fail to find an input, we have a zero-shuffle which should always
7869 // have already been handled.
7870 // FIXME: Maybe handle this here in case during blending we end up with one?
7874 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7875 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7878 // The widest scale possible for extending is to a 64-bit integer.
7879 assert(Bits % 64 == 0 &&
7880 "The number of bits in a vector must be divisible by 64 on x86!");
7881 int NumExtElements = Bits / 64;
7883 // Each iteration, try extending the elements half as much, but into twice as
7885 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7886 assert(NumElements % NumExtElements == 0 &&
7887 "The input vector size must be divisble by the extended size.");
7888 if (SDValue V = Lower(NumElements / NumExtElements))
7892 // No viable ext lowering found.
7896 /// \brief Try to get a scalar value for a specific element of a vector.
7898 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7899 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7900 SelectionDAG &DAG) {
7901 MVT VT = V.getSimpleValueType();
7902 MVT EltVT = VT.getVectorElementType();
7903 while (V.getOpcode() == ISD::BITCAST)
7904 V = V.getOperand(0);
7905 // If the bitcasts shift the element size, we can't extract an equivalent
7907 MVT NewVT = V.getSimpleValueType();
7908 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7911 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7912 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7913 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7918 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7920 /// This is particularly important because the set of instructions varies
7921 /// significantly based on whether the operand is a load or not.
7922 static bool isShuffleFoldableLoad(SDValue V) {
7923 while (V.getOpcode() == ISD::BITCAST)
7924 V = V.getOperand(0);
7926 return ISD::isNON_EXTLoad(V.getNode());
7929 /// \brief Try to lower insertion of a single element into a zero vector.
7931 /// This is a common pattern that we have especially efficient patterns to lower
7932 /// across all subtarget feature sets.
7933 static SDValue lowerVectorShuffleAsElementInsertion(
7934 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7935 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7936 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7938 MVT EltVT = VT.getVectorElementType();
7940 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7941 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7943 bool IsV1Zeroable = true;
7944 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7945 if (i != V2Index && !Zeroable[i]) {
7946 IsV1Zeroable = false;
7950 // Check for a single input from a SCALAR_TO_VECTOR node.
7951 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7952 // all the smarts here sunk into that routine. However, the current
7953 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7954 // vector shuffle lowering is dead.
7955 if (SDValue V2S = getScalarValueForVectorElement(
7956 V2, Mask[V2Index] - Mask.size(), DAG)) {
7957 // We need to zext the scalar if it is smaller than an i32.
7958 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7959 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7960 // Using zext to expand a narrow element won't work for non-zero
7965 // Zero-extend directly to i32.
7967 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7969 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7970 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7971 EltVT == MVT::i16) {
7972 // Either not inserting from the low element of the input or the input
7973 // element size is too small to use VZEXT_MOVL to clear the high bits.
7977 if (!IsV1Zeroable) {
7978 // If V1 can't be treated as a zero vector we have fewer options to lower
7979 // this. We can't support integer vectors or non-zero targets cheaply, and
7980 // the V1 elements can't be permuted in any way.
7981 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7982 if (!VT.isFloatingPoint() || V2Index != 0)
7984 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7985 V1Mask[V2Index] = -1;
7986 if (!isNoopShuffleMask(V1Mask))
7988 // This is essentially a special case blend operation, but if we have
7989 // general purpose blend operations, they are always faster. Bail and let
7990 // the rest of the lowering handle these as blends.
7991 if (Subtarget->hasSSE41())
7994 // Otherwise, use MOVSD or MOVSS.
7995 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7996 "Only two types of floating point element types to handle!");
7997 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8001 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8003 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8006 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8007 // the desired position. Otherwise it is more efficient to do a vector
8008 // shift left. We know that we can do a vector shift left because all
8009 // the inputs are zero.
8010 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8011 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8012 V2Shuffle[V2Index] = 0;
8013 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8015 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8017 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8019 V2Index * EltVT.getSizeInBits(),
8020 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8021 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8027 /// \brief Try to lower broadcast of a single element.
8029 /// For convenience, this code also bundles all of the subtarget feature set
8030 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8031 /// a convenient way to factor it out.
8032 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8034 const X86Subtarget *Subtarget,
8035 SelectionDAG &DAG) {
8036 if (!Subtarget->hasAVX())
8038 if (VT.isInteger() && !Subtarget->hasAVX2())
8041 // Check that the mask is a broadcast.
8042 int BroadcastIdx = -1;
8044 if (M >= 0 && BroadcastIdx == -1)
8046 else if (M >= 0 && M != BroadcastIdx)
8049 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8050 "a sorted mask where the broadcast "
8053 // Go up the chain of (vector) values to try and find a scalar load that
8054 // we can combine with the broadcast.
8056 switch (V.getOpcode()) {
8057 case ISD::CONCAT_VECTORS: {
8058 int OperandSize = Mask.size() / V.getNumOperands();
8059 V = V.getOperand(BroadcastIdx / OperandSize);
8060 BroadcastIdx %= OperandSize;
8064 case ISD::INSERT_SUBVECTOR: {
8065 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8066 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8070 int BeginIdx = (int)ConstantIdx->getZExtValue();
8072 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8073 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8074 BroadcastIdx -= BeginIdx;
8085 // Check if this is a broadcast of a scalar. We special case lowering
8086 // for scalars so that we can more effectively fold with loads.
8087 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8088 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8089 V = V.getOperand(BroadcastIdx);
8091 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8093 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8095 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8096 // We can't broadcast from a vector register w/o AVX2, and we can only
8097 // broadcast from the zero-element of a vector register.
8101 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8104 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8106 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8107 /// support for floating point shuffles but not integer shuffles. These
8108 /// instructions will incur a domain crossing penalty on some chips though so
8109 /// it is better to avoid lowering through this for integer vectors where
8111 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8112 const X86Subtarget *Subtarget,
8113 SelectionDAG &DAG) {
8115 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8116 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8117 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8118 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8119 ArrayRef<int> Mask = SVOp->getMask();
8120 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8122 if (isSingleInputShuffleMask(Mask)) {
8123 // Straight shuffle of a single input vector. Simulate this by using the
8124 // single input as both of the "inputs" to this instruction..
8125 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8127 if (Subtarget->hasAVX()) {
8128 // If we have AVX, we can use VPERMILPS which will allow folding a load
8129 // into the shuffle.
8130 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8131 DAG.getConstant(SHUFPDMask, MVT::i8));
8134 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8135 DAG.getConstant(SHUFPDMask, MVT::i8));
8137 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8138 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8140 // Use dedicated unpack instructions for masks that match their pattern.
8141 if (isShuffleEquivalent(Mask, 0, 2))
8142 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8143 if (isShuffleEquivalent(Mask, 1, 3))
8144 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8146 // If we have a single input, insert that into V1 if we can do so cheaply.
8147 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8148 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8149 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8151 // Try inverting the insertion since for v2 masks it is easy to do and we
8152 // can't reliably sort the mask one way or the other.
8153 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8154 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8155 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8156 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8160 // Try to use one of the special instruction patterns to handle two common
8161 // blend patterns if a zero-blend above didn't work.
8162 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8163 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8164 // We can either use a special instruction to load over the low double or
8165 // to move just the low double.
8167 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8169 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8171 if (Subtarget->hasSSE41())
8172 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8176 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8177 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8178 DAG.getConstant(SHUFPDMask, MVT::i8));
8181 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8183 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8184 /// the integer unit to minimize domain crossing penalties. However, for blends
8185 /// it falls back to the floating point shuffle operation with appropriate bit
8187 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8188 const X86Subtarget *Subtarget,
8189 SelectionDAG &DAG) {
8191 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8192 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8193 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8194 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8195 ArrayRef<int> Mask = SVOp->getMask();
8196 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8198 if (isSingleInputShuffleMask(Mask)) {
8199 // Check for being able to broadcast a single element.
8200 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8201 Mask, Subtarget, DAG))
8204 // Straight shuffle of a single input vector. For everything from SSE2
8205 // onward this has a single fast instruction with no scary immediates.
8206 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8207 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8208 int WidenedMask[4] = {
8209 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8210 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8212 ISD::BITCAST, DL, MVT::v2i64,
8213 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8214 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8217 // If we have a single input from V2 insert that into V1 if we can do so
8219 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8220 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8221 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8223 // Try inverting the insertion since for v2 masks it is easy to do and we
8224 // can't reliably sort the mask one way or the other.
8225 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8226 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8227 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8228 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8232 // Use dedicated unpack instructions for masks that match their pattern.
8233 if (isShuffleEquivalent(Mask, 0, 2))
8234 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8235 if (isShuffleEquivalent(Mask, 1, 3))
8236 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8238 if (Subtarget->hasSSE41())
8239 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8243 // Try to use byte shift instructions.
8244 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8245 DL, MVT::v2i64, V1, V2, Mask, DAG))
8248 // Try to use byte rotation instructions.
8249 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8250 if (Subtarget->hasSSSE3())
8251 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8252 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8255 // We implement this with SHUFPD which is pretty lame because it will likely
8256 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8257 // However, all the alternatives are still more cycles and newer chips don't
8258 // have this problem. It would be really nice if x86 had better shuffles here.
8259 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8260 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8261 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8262 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8265 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8267 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8268 /// It makes no assumptions about whether this is the *best* lowering, it simply
8270 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8271 ArrayRef<int> Mask, SDValue V1,
8272 SDValue V2, SelectionDAG &DAG) {
8273 SDValue LowV = V1, HighV = V2;
8274 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8277 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8279 if (NumV2Elements == 1) {
8281 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8284 // Compute the index adjacent to V2Index and in the same half by toggling
8286 int V2AdjIndex = V2Index ^ 1;
8288 if (Mask[V2AdjIndex] == -1) {
8289 // Handles all the cases where we have a single V2 element and an undef.
8290 // This will only ever happen in the high lanes because we commute the
8291 // vector otherwise.
8293 std::swap(LowV, HighV);
8294 NewMask[V2Index] -= 4;
8296 // Handle the case where the V2 element ends up adjacent to a V1 element.
8297 // To make this work, blend them together as the first step.
8298 int V1Index = V2AdjIndex;
8299 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8300 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8301 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8303 // Now proceed to reconstruct the final blend as we have the necessary
8304 // high or low half formed.
8311 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8312 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8314 } else if (NumV2Elements == 2) {
8315 if (Mask[0] < 4 && Mask[1] < 4) {
8316 // Handle the easy case where we have V1 in the low lanes and V2 in the
8320 } else if (Mask[2] < 4 && Mask[3] < 4) {
8321 // We also handle the reversed case because this utility may get called
8322 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8323 // arrange things in the right direction.
8329 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8330 // trying to place elements directly, just blend them and set up the final
8331 // shuffle to place them.
8333 // The first two blend mask elements are for V1, the second two are for
8335 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8336 Mask[2] < 4 ? Mask[2] : Mask[3],
8337 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8338 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8339 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8340 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8342 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8345 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8346 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8347 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8348 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8351 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8352 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8355 /// \brief Lower 4-lane 32-bit floating point shuffles.
8357 /// Uses instructions exclusively from the floating point unit to minimize
8358 /// domain crossing penalties, as these are sufficient to implement all v4f32
8360 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8361 const X86Subtarget *Subtarget,
8362 SelectionDAG &DAG) {
8364 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8365 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8366 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8367 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8368 ArrayRef<int> Mask = SVOp->getMask();
8369 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8372 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8374 if (NumV2Elements == 0) {
8375 // Check for being able to broadcast a single element.
8376 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8377 Mask, Subtarget, DAG))
8380 if (Subtarget->hasAVX()) {
8381 // If we have AVX, we can use VPERMILPS which will allow folding a load
8382 // into the shuffle.
8383 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8384 getV4X86ShuffleImm8ForMask(Mask, DAG));
8387 // Otherwise, use a straight shuffle of a single input vector. We pass the
8388 // input vector to both operands to simulate this with a SHUFPS.
8389 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8390 getV4X86ShuffleImm8ForMask(Mask, DAG));
8393 // Use dedicated unpack instructions for masks that match their pattern.
8394 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8395 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8396 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8397 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8399 // There are special ways we can lower some single-element blends. However, we
8400 // have custom ways we can lower more complex single-element blends below that
8401 // we defer to if both this and BLENDPS fail to match, so restrict this to
8402 // when the V2 input is targeting element 0 of the mask -- that is the fast
8404 if (NumV2Elements == 1 && Mask[0] >= 4)
8405 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8406 Mask, Subtarget, DAG))
8409 if (Subtarget->hasSSE41())
8410 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8414 // Check for whether we can use INSERTPS to perform the blend. We only use
8415 // INSERTPS when the V1 elements are already in the correct locations
8416 // because otherwise we can just always use two SHUFPS instructions which
8417 // are much smaller to encode than a SHUFPS and an INSERTPS.
8418 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8420 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8423 // When using INSERTPS we can zero any lane of the destination. Collect
8424 // the zero inputs into a mask and drop them from the lanes of V1 which
8425 // actually need to be present as inputs to the INSERTPS.
8426 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8428 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8429 bool InsertNeedsShuffle = false;
8431 for (int i = 0; i < 4; ++i)
8435 } else if (Mask[i] != i) {
8436 InsertNeedsShuffle = true;
8441 // We don't want to use INSERTPS or other insertion techniques if it will
8442 // require shuffling anyways.
8443 if (!InsertNeedsShuffle) {
8444 // If all of V1 is zeroable, replace it with undef.
8445 if ((ZMask | 1 << V2Index) == 0xF)
8446 V1 = DAG.getUNDEF(MVT::v4f32);
8448 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8449 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8451 // Insert the V2 element into the desired position.
8452 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8453 DAG.getConstant(InsertPSMask, MVT::i8));
8457 // Otherwise fall back to a SHUFPS lowering strategy.
8458 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8461 /// \brief Lower 4-lane i32 vector shuffles.
8463 /// We try to handle these with integer-domain shuffles where we can, but for
8464 /// blends we use the floating point domain blend instructions.
8465 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8466 const X86Subtarget *Subtarget,
8467 SelectionDAG &DAG) {
8469 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8470 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8471 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8472 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8473 ArrayRef<int> Mask = SVOp->getMask();
8474 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8476 // Whenever we can lower this as a zext, that instruction is strictly faster
8477 // than any alternative. It also allows us to fold memory operands into the
8478 // shuffle in many cases.
8479 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8480 Mask, Subtarget, DAG))
8484 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8486 if (NumV2Elements == 0) {
8487 // Check for being able to broadcast a single element.
8488 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8489 Mask, Subtarget, DAG))
8492 // Straight shuffle of a single input vector. For everything from SSE2
8493 // onward this has a single fast instruction with no scary immediates.
8494 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8495 // but we aren't actually going to use the UNPCK instruction because doing
8496 // so prevents folding a load into this instruction or making a copy.
8497 const int UnpackLoMask[] = {0, 0, 1, 1};
8498 const int UnpackHiMask[] = {2, 2, 3, 3};
8499 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8500 Mask = UnpackLoMask;
8501 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8502 Mask = UnpackHiMask;
8504 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8505 getV4X86ShuffleImm8ForMask(Mask, DAG));
8508 // There are special ways we can lower some single-element blends.
8509 if (NumV2Elements == 1)
8510 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8511 Mask, Subtarget, DAG))
8514 // Use dedicated unpack instructions for masks that match their pattern.
8515 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8516 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8517 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8518 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8520 if (Subtarget->hasSSE41())
8521 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8525 // Try to use byte shift instructions.
8526 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8527 DL, MVT::v4i32, V1, V2, Mask, DAG))
8530 // Try to use byte rotation instructions.
8531 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8532 if (Subtarget->hasSSSE3())
8533 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8534 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8537 // We implement this with SHUFPS because it can blend from two vectors.
8538 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8539 // up the inputs, bypassing domain shift penalties that we would encur if we
8540 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8542 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8543 DAG.getVectorShuffle(
8545 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8546 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8549 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8550 /// shuffle lowering, and the most complex part.
8552 /// The lowering strategy is to try to form pairs of input lanes which are
8553 /// targeted at the same half of the final vector, and then use a dword shuffle
8554 /// to place them onto the right half, and finally unpack the paired lanes into
8555 /// their final position.
8557 /// The exact breakdown of how to form these dword pairs and align them on the
8558 /// correct sides is really tricky. See the comments within the function for
8559 /// more of the details.
8560 static SDValue lowerV8I16SingleInputVectorShuffle(
8561 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8562 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8563 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8564 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8565 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8567 SmallVector<int, 4> LoInputs;
8568 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8569 [](int M) { return M >= 0; });
8570 std::sort(LoInputs.begin(), LoInputs.end());
8571 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8572 SmallVector<int, 4> HiInputs;
8573 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8574 [](int M) { return M >= 0; });
8575 std::sort(HiInputs.begin(), HiInputs.end());
8576 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8578 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8579 int NumHToL = LoInputs.size() - NumLToL;
8581 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8582 int NumHToH = HiInputs.size() - NumLToH;
8583 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8584 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8585 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8586 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8588 // Check for being able to broadcast a single element.
8589 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8590 Mask, Subtarget, DAG))
8593 // Use dedicated unpack instructions for masks that match their pattern.
8594 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8595 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8596 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8597 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8599 // Try to use byte shift instructions.
8600 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8601 DL, MVT::v8i16, V, V, Mask, DAG))
8604 // Try to use byte rotation instructions.
8605 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8606 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8609 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8610 // such inputs we can swap two of the dwords across the half mark and end up
8611 // with <=2 inputs to each half in each half. Once there, we can fall through
8612 // to the generic code below. For example:
8614 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8615 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8617 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8618 // and an existing 2-into-2 on the other half. In this case we may have to
8619 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8620 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8621 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8622 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8623 // half than the one we target for fixing) will be fixed when we re-enter this
8624 // path. We will also combine away any sequence of PSHUFD instructions that
8625 // result into a single instruction. Here is an example of the tricky case:
8627 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8628 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8630 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8632 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8633 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8635 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8636 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8638 // The result is fine to be handled by the generic logic.
8639 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8640 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8641 int AOffset, int BOffset) {
8642 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8643 "Must call this with A having 3 or 1 inputs from the A half.");
8644 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8645 "Must call this with B having 1 or 3 inputs from the B half.");
8646 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8647 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8649 // Compute the index of dword with only one word among the three inputs in
8650 // a half by taking the sum of the half with three inputs and subtracting
8651 // the sum of the actual three inputs. The difference is the remaining
8654 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8655 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8656 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8657 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8658 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8659 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8660 int TripleNonInputIdx =
8661 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8662 TripleDWord = TripleNonInputIdx / 2;
8664 // We use xor with one to compute the adjacent DWord to whichever one the
8666 OneInputDWord = (OneInput / 2) ^ 1;
8668 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8669 // and BToA inputs. If there is also such a problem with the BToB and AToB
8670 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8671 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8672 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8673 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8674 // Compute how many inputs will be flipped by swapping these DWords. We
8676 // to balance this to ensure we don't form a 3-1 shuffle in the other
8678 int NumFlippedAToBInputs =
8679 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8680 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8681 int NumFlippedBToBInputs =
8682 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8683 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8684 if ((NumFlippedAToBInputs == 1 &&
8685 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8686 (NumFlippedBToBInputs == 1 &&
8687 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8688 // We choose whether to fix the A half or B half based on whether that
8689 // half has zero flipped inputs. At zero, we may not be able to fix it
8690 // with that half. We also bias towards fixing the B half because that
8691 // will more commonly be the high half, and we have to bias one way.
8692 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8693 ArrayRef<int> Inputs) {
8694 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8695 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8696 PinnedIdx ^ 1) != Inputs.end();
8697 // Determine whether the free index is in the flipped dword or the
8698 // unflipped dword based on where the pinned index is. We use this bit
8699 // in an xor to conditionally select the adjacent dword.
8700 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8701 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8702 FixFreeIdx) != Inputs.end();
8703 if (IsFixIdxInput == IsFixFreeIdxInput)
8705 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8706 FixFreeIdx) != Inputs.end();
8707 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8708 "We need to be changing the number of flipped inputs!");
8709 int PSHUFHalfMask[] = {0, 1, 2, 3};
8710 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8711 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8713 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8716 if (M != -1 && M == FixIdx)
8718 else if (M != -1 && M == FixFreeIdx)
8721 if (NumFlippedBToBInputs != 0) {
8723 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8724 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8726 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8728 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8729 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8734 int PSHUFDMask[] = {0, 1, 2, 3};
8735 PSHUFDMask[ADWord] = BDWord;
8736 PSHUFDMask[BDWord] = ADWord;
8737 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8738 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8739 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8740 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8742 // Adjust the mask to match the new locations of A and B.
8744 if (M != -1 && M/2 == ADWord)
8745 M = 2 * BDWord + M % 2;
8746 else if (M != -1 && M/2 == BDWord)
8747 M = 2 * ADWord + M % 2;
8749 // Recurse back into this routine to re-compute state now that this isn't
8750 // a 3 and 1 problem.
8751 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8754 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8755 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8756 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8757 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8759 // At this point there are at most two inputs to the low and high halves from
8760 // each half. That means the inputs can always be grouped into dwords and
8761 // those dwords can then be moved to the correct half with a dword shuffle.
8762 // We use at most one low and one high word shuffle to collect these paired
8763 // inputs into dwords, and finally a dword shuffle to place them.
8764 int PSHUFLMask[4] = {-1, -1, -1, -1};
8765 int PSHUFHMask[4] = {-1, -1, -1, -1};
8766 int PSHUFDMask[4] = {-1, -1, -1, -1};
8768 // First fix the masks for all the inputs that are staying in their
8769 // original halves. This will then dictate the targets of the cross-half
8771 auto fixInPlaceInputs =
8772 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8773 MutableArrayRef<int> SourceHalfMask,
8774 MutableArrayRef<int> HalfMask, int HalfOffset) {
8775 if (InPlaceInputs.empty())
8777 if (InPlaceInputs.size() == 1) {
8778 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8779 InPlaceInputs[0] - HalfOffset;
8780 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8783 if (IncomingInputs.empty()) {
8784 // Just fix all of the in place inputs.
8785 for (int Input : InPlaceInputs) {
8786 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8787 PSHUFDMask[Input / 2] = Input / 2;
8792 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8793 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8794 InPlaceInputs[0] - HalfOffset;
8795 // Put the second input next to the first so that they are packed into
8796 // a dword. We find the adjacent index by toggling the low bit.
8797 int AdjIndex = InPlaceInputs[0] ^ 1;
8798 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8799 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8800 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8802 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8803 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8805 // Now gather the cross-half inputs and place them into a free dword of
8806 // their target half.
8807 // FIXME: This operation could almost certainly be simplified dramatically to
8808 // look more like the 3-1 fixing operation.
8809 auto moveInputsToRightHalf = [&PSHUFDMask](
8810 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8811 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8812 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8814 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8815 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8817 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8819 int LowWord = Word & ~1;
8820 int HighWord = Word | 1;
8821 return isWordClobbered(SourceHalfMask, LowWord) ||
8822 isWordClobbered(SourceHalfMask, HighWord);
8825 if (IncomingInputs.empty())
8828 if (ExistingInputs.empty()) {
8829 // Map any dwords with inputs from them into the right half.
8830 for (int Input : IncomingInputs) {
8831 // If the source half mask maps over the inputs, turn those into
8832 // swaps and use the swapped lane.
8833 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8834 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8835 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8836 Input - SourceOffset;
8837 // We have to swap the uses in our half mask in one sweep.
8838 for (int &M : HalfMask)
8839 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8841 else if (M == Input)
8842 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8844 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8845 Input - SourceOffset &&
8846 "Previous placement doesn't match!");
8848 // Note that this correctly re-maps both when we do a swap and when
8849 // we observe the other side of the swap above. We rely on that to
8850 // avoid swapping the members of the input list directly.
8851 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8854 // Map the input's dword into the correct half.
8855 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8856 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8858 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8860 "Previous placement doesn't match!");
8863 // And just directly shift any other-half mask elements to be same-half
8864 // as we will have mirrored the dword containing the element into the
8865 // same position within that half.
8866 for (int &M : HalfMask)
8867 if (M >= SourceOffset && M < SourceOffset + 4) {
8868 M = M - SourceOffset + DestOffset;
8869 assert(M >= 0 && "This should never wrap below zero!");
8874 // Ensure we have the input in a viable dword of its current half. This
8875 // is particularly tricky because the original position may be clobbered
8876 // by inputs being moved and *staying* in that half.
8877 if (IncomingInputs.size() == 1) {
8878 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8879 int InputFixed = std::find(std::begin(SourceHalfMask),
8880 std::end(SourceHalfMask), -1) -
8881 std::begin(SourceHalfMask) + SourceOffset;
8882 SourceHalfMask[InputFixed - SourceOffset] =
8883 IncomingInputs[0] - SourceOffset;
8884 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8886 IncomingInputs[0] = InputFixed;
8888 } else if (IncomingInputs.size() == 2) {
8889 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8890 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8891 // We have two non-adjacent or clobbered inputs we need to extract from
8892 // the source half. To do this, we need to map them into some adjacent
8893 // dword slot in the source mask.
8894 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8895 IncomingInputs[1] - SourceOffset};
8897 // If there is a free slot in the source half mask adjacent to one of
8898 // the inputs, place the other input in it. We use (Index XOR 1) to
8899 // compute an adjacent index.
8900 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8901 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8902 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8903 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8904 InputsFixed[1] = InputsFixed[0] ^ 1;
8905 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8906 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8907 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8908 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8909 InputsFixed[0] = InputsFixed[1] ^ 1;
8910 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8911 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8912 // The two inputs are in the same DWord but it is clobbered and the
8913 // adjacent DWord isn't used at all. Move both inputs to the free
8915 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8916 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8917 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8918 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8920 // The only way we hit this point is if there is no clobbering
8921 // (because there are no off-half inputs to this half) and there is no
8922 // free slot adjacent to one of the inputs. In this case, we have to
8923 // swap an input with a non-input.
8924 for (int i = 0; i < 4; ++i)
8925 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8926 "We can't handle any clobbers here!");
8927 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8928 "Cannot have adjacent inputs here!");
8930 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8931 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8933 // We also have to update the final source mask in this case because
8934 // it may need to undo the above swap.
8935 for (int &M : FinalSourceHalfMask)
8936 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8937 M = InputsFixed[1] + SourceOffset;
8938 else if (M == InputsFixed[1] + SourceOffset)
8939 M = (InputsFixed[0] ^ 1) + SourceOffset;
8941 InputsFixed[1] = InputsFixed[0] ^ 1;
8944 // Point everything at the fixed inputs.
8945 for (int &M : HalfMask)
8946 if (M == IncomingInputs[0])
8947 M = InputsFixed[0] + SourceOffset;
8948 else if (M == IncomingInputs[1])
8949 M = InputsFixed[1] + SourceOffset;
8951 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8952 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8955 llvm_unreachable("Unhandled input size!");
8958 // Now hoist the DWord down to the right half.
8959 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8960 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8961 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8962 for (int &M : HalfMask)
8963 for (int Input : IncomingInputs)
8965 M = FreeDWord * 2 + Input % 2;
8967 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8968 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8969 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8970 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8972 // Now enact all the shuffles we've computed to move the inputs into their
8974 if (!isNoopShuffleMask(PSHUFLMask))
8975 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8976 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8977 if (!isNoopShuffleMask(PSHUFHMask))
8978 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8979 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8980 if (!isNoopShuffleMask(PSHUFDMask))
8981 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8982 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8983 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8984 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8986 // At this point, each half should contain all its inputs, and we can then
8987 // just shuffle them into their final position.
8988 assert(std::count_if(LoMask.begin(), LoMask.end(),
8989 [](int M) { return M >= 4; }) == 0 &&
8990 "Failed to lift all the high half inputs to the low mask!");
8991 assert(std::count_if(HiMask.begin(), HiMask.end(),
8992 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8993 "Failed to lift all the low half inputs to the high mask!");
8995 // Do a half shuffle for the low mask.
8996 if (!isNoopShuffleMask(LoMask))
8997 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8998 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9000 // Do a half shuffle with the high mask after shifting its values down.
9001 for (int &M : HiMask)
9004 if (!isNoopShuffleMask(HiMask))
9005 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9006 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9011 /// \brief Detect whether the mask pattern should be lowered through
9014 /// This essentially tests whether viewing the mask as an interleaving of two
9015 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9016 /// lowering it through interleaving is a significantly better strategy.
9017 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9018 int NumEvenInputs[2] = {0, 0};
9019 int NumOddInputs[2] = {0, 0};
9020 int NumLoInputs[2] = {0, 0};
9021 int NumHiInputs[2] = {0, 0};
9022 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9026 int InputIdx = Mask[i] >= Size;
9029 ++NumLoInputs[InputIdx];
9031 ++NumHiInputs[InputIdx];
9034 ++NumEvenInputs[InputIdx];
9036 ++NumOddInputs[InputIdx];
9039 // The minimum number of cross-input results for both the interleaved and
9040 // split cases. If interleaving results in fewer cross-input results, return
9042 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9043 NumEvenInputs[0] + NumOddInputs[1]);
9044 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9045 NumLoInputs[0] + NumHiInputs[1]);
9046 return InterleavedCrosses < SplitCrosses;
9049 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9051 /// This strategy only works when the inputs from each vector fit into a single
9052 /// half of that vector, and generally there are not so many inputs as to leave
9053 /// the in-place shuffles required highly constrained (and thus expensive). It
9054 /// shifts all the inputs into a single side of both input vectors and then
9055 /// uses an unpack to interleave these inputs in a single vector. At that
9056 /// point, we will fall back on the generic single input shuffle lowering.
9057 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9059 MutableArrayRef<int> Mask,
9060 const X86Subtarget *Subtarget,
9061 SelectionDAG &DAG) {
9062 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9063 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9064 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9065 for (int i = 0; i < 8; ++i)
9066 if (Mask[i] >= 0 && Mask[i] < 4)
9067 LoV1Inputs.push_back(i);
9068 else if (Mask[i] >= 4 && Mask[i] < 8)
9069 HiV1Inputs.push_back(i);
9070 else if (Mask[i] >= 8 && Mask[i] < 12)
9071 LoV2Inputs.push_back(i);
9072 else if (Mask[i] >= 12)
9073 HiV2Inputs.push_back(i);
9075 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9076 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9079 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9080 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9081 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9083 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9084 HiV1Inputs.size() + HiV2Inputs.size();
9086 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9087 ArrayRef<int> HiInputs, bool MoveToLo,
9089 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9090 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9091 if (BadInputs.empty())
9094 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9095 int MoveOffset = MoveToLo ? 0 : 4;
9097 if (GoodInputs.empty()) {
9098 for (int BadInput : BadInputs) {
9099 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9100 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9103 if (GoodInputs.size() == 2) {
9104 // If the low inputs are spread across two dwords, pack them into
9106 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9107 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9108 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9109 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9111 // Otherwise pin the good inputs.
9112 for (int GoodInput : GoodInputs)
9113 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9116 if (BadInputs.size() == 2) {
9117 // If we have two bad inputs then there may be either one or two good
9118 // inputs fixed in place. Find a fixed input, and then find the *other*
9119 // two adjacent indices by using modular arithmetic.
9121 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9122 [](int M) { return M >= 0; }) -
9123 std::begin(MoveMask);
9125 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9126 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9127 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9128 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9129 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9130 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9131 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9133 assert(BadInputs.size() == 1 && "All sizes handled");
9134 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9135 std::end(MoveMask), -1) -
9136 std::begin(MoveMask);
9137 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9138 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9142 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9145 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9147 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9150 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9151 // cross-half traffic in the final shuffle.
9153 // Munge the mask to be a single-input mask after the unpack merges the
9157 M = 2 * (M % 4) + (M / 8);
9159 return DAG.getVectorShuffle(
9160 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9161 DL, MVT::v8i16, V1, V2),
9162 DAG.getUNDEF(MVT::v8i16), Mask);
9165 /// \brief Generic lowering of 8-lane i16 shuffles.
9167 /// This handles both single-input shuffles and combined shuffle/blends with
9168 /// two inputs. The single input shuffles are immediately delegated to
9169 /// a dedicated lowering routine.
9171 /// The blends are lowered in one of three fundamental ways. If there are few
9172 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9173 /// of the input is significantly cheaper when lowered as an interleaving of
9174 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9175 /// halves of the inputs separately (making them have relatively few inputs)
9176 /// and then concatenate them.
9177 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9178 const X86Subtarget *Subtarget,
9179 SelectionDAG &DAG) {
9181 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9182 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9183 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9184 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9185 ArrayRef<int> OrigMask = SVOp->getMask();
9186 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9187 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9188 MutableArrayRef<int> Mask(MaskStorage);
9190 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9192 // Whenever we can lower this as a zext, that instruction is strictly faster
9193 // than any alternative.
9194 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9195 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9198 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9199 auto isV2 = [](int M) { return M >= 8; };
9201 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9202 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9204 if (NumV2Inputs == 0)
9205 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9207 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9208 "to be V1-input shuffles.");
9210 // There are special ways we can lower some single-element blends.
9211 if (NumV2Inputs == 1)
9212 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9213 Mask, Subtarget, DAG))
9216 // Use dedicated unpack instructions for masks that match their pattern.
9217 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9218 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9219 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9220 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9222 if (Subtarget->hasSSE41())
9223 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9227 // Try to use byte shift instructions.
9228 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9229 DL, MVT::v8i16, V1, V2, Mask, DAG))
9232 // Try to use byte rotation instructions.
9233 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9234 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9237 if (NumV1Inputs + NumV2Inputs <= 4)
9238 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9240 // Check whether an interleaving lowering is likely to be more efficient.
9241 // This isn't perfect but it is a strong heuristic that tends to work well on
9242 // the kinds of shuffles that show up in practice.
9244 // FIXME: Handle 1x, 2x, and 4x interleaving.
9245 if (shouldLowerAsInterleaving(Mask)) {
9246 // FIXME: Figure out whether we should pack these into the low or high
9249 int EMask[8], OMask[8];
9250 for (int i = 0; i < 4; ++i) {
9251 EMask[i] = Mask[2*i];
9252 OMask[i] = Mask[2*i + 1];
9257 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9258 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9260 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9263 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9264 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9266 for (int i = 0; i < 4; ++i) {
9267 LoBlendMask[i] = Mask[i];
9268 HiBlendMask[i] = Mask[i + 4];
9271 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9272 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9273 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9274 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9276 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9277 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9280 /// \brief Check whether a compaction lowering can be done by dropping even
9281 /// elements and compute how many times even elements must be dropped.
9283 /// This handles shuffles which take every Nth element where N is a power of
9284 /// two. Example shuffle masks:
9286 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9287 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9288 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9289 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9290 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9291 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9293 /// Any of these lanes can of course be undef.
9295 /// This routine only supports N <= 3.
9296 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9299 /// \returns N above, or the number of times even elements must be dropped if
9300 /// there is such a number. Otherwise returns zero.
9301 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9302 // Figure out whether we're looping over two inputs or just one.
9303 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9305 // The modulus for the shuffle vector entries is based on whether this is
9306 // a single input or not.
9307 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9308 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9309 "We should only be called with masks with a power-of-2 size!");
9311 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9313 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9314 // and 2^3 simultaneously. This is because we may have ambiguity with
9315 // partially undef inputs.
9316 bool ViableForN[3] = {true, true, true};
9318 for (int i = 0, e = Mask.size(); i < e; ++i) {
9319 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9324 bool IsAnyViable = false;
9325 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9326 if (ViableForN[j]) {
9329 // The shuffle mask must be equal to (i * 2^N) % M.
9330 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9333 ViableForN[j] = false;
9335 // Early exit if we exhaust the possible powers of two.
9340 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9344 // Return 0 as there is no viable power of two.
9348 /// \brief Generic lowering of v16i8 shuffles.
9350 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9351 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9352 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9353 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9355 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9356 const X86Subtarget *Subtarget,
9357 SelectionDAG &DAG) {
9359 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9360 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9361 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9363 ArrayRef<int> OrigMask = SVOp->getMask();
9364 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9366 // Try to use byte shift instructions.
9367 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9368 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9371 // Try to use byte rotation instructions.
9372 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9373 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9376 // Try to use a zext lowering.
9377 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9378 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9381 int MaskStorage[16] = {
9382 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9383 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9384 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9385 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9386 MutableArrayRef<int> Mask(MaskStorage);
9387 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9388 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9391 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9393 // For single-input shuffles, there are some nicer lowering tricks we can use.
9394 if (NumV2Elements == 0) {
9395 // Check for being able to broadcast a single element.
9396 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9397 Mask, Subtarget, DAG))
9400 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9401 // Notably, this handles splat and partial-splat shuffles more efficiently.
9402 // However, it only makes sense if the pre-duplication shuffle simplifies
9403 // things significantly. Currently, this means we need to be able to
9404 // express the pre-duplication shuffle as an i16 shuffle.
9406 // FIXME: We should check for other patterns which can be widened into an
9407 // i16 shuffle as well.
9408 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9409 for (int i = 0; i < 16; i += 2)
9410 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9415 auto tryToWidenViaDuplication = [&]() -> SDValue {
9416 if (!canWidenViaDuplication(Mask))
9418 SmallVector<int, 4> LoInputs;
9419 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9420 [](int M) { return M >= 0 && M < 8; });
9421 std::sort(LoInputs.begin(), LoInputs.end());
9422 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9424 SmallVector<int, 4> HiInputs;
9425 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9426 [](int M) { return M >= 8; });
9427 std::sort(HiInputs.begin(), HiInputs.end());
9428 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9431 bool TargetLo = LoInputs.size() >= HiInputs.size();
9432 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9433 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9435 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9436 SmallDenseMap<int, int, 8> LaneMap;
9437 for (int I : InPlaceInputs) {
9438 PreDupI16Shuffle[I/2] = I/2;
9441 int j = TargetLo ? 0 : 4, je = j + 4;
9442 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9443 // Check if j is already a shuffle of this input. This happens when
9444 // there are two adjacent bytes after we move the low one.
9445 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9446 // If we haven't yet mapped the input, search for a slot into which
9448 while (j < je && PreDupI16Shuffle[j] != -1)
9452 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9455 // Map this input with the i16 shuffle.
9456 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9459 // Update the lane map based on the mapping we ended up with.
9460 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9463 ISD::BITCAST, DL, MVT::v16i8,
9464 DAG.getVectorShuffle(MVT::v8i16, DL,
9465 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9466 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9468 // Unpack the bytes to form the i16s that will be shuffled into place.
9469 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9470 MVT::v16i8, V1, V1);
9472 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9473 for (int i = 0; i < 16; ++i)
9474 if (Mask[i] != -1) {
9475 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9476 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9477 if (PostDupI16Shuffle[i / 2] == -1)
9478 PostDupI16Shuffle[i / 2] = MappedMask;
9480 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9481 "Conflicting entrties in the original shuffle!");
9484 ISD::BITCAST, DL, MVT::v16i8,
9485 DAG.getVectorShuffle(MVT::v8i16, DL,
9486 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9487 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9489 if (SDValue V = tryToWidenViaDuplication())
9493 // Check whether an interleaving lowering is likely to be more efficient.
9494 // This isn't perfect but it is a strong heuristic that tends to work well on
9495 // the kinds of shuffles that show up in practice.
9497 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9498 if (shouldLowerAsInterleaving(Mask)) {
9499 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9500 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9502 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9503 return (M >= 8 && M < 16) || M >= 24;
9505 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9506 -1, -1, -1, -1, -1, -1, -1, -1};
9507 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9508 -1, -1, -1, -1, -1, -1, -1, -1};
9509 bool UnpackLo = NumLoHalf >= NumHiHalf;
9510 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9511 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9512 for (int i = 0; i < 8; ++i) {
9513 TargetEMask[i] = Mask[2 * i];
9514 TargetOMask[i] = Mask[2 * i + 1];
9517 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9518 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9520 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9521 MVT::v16i8, Evens, Odds);
9524 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9525 // with PSHUFB. It is important to do this before we attempt to generate any
9526 // blends but after all of the single-input lowerings. If the single input
9527 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9528 // want to preserve that and we can DAG combine any longer sequences into
9529 // a PSHUFB in the end. But once we start blending from multiple inputs,
9530 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9531 // and there are *very* few patterns that would actually be faster than the
9532 // PSHUFB approach because of its ability to zero lanes.
9534 // FIXME: The only exceptions to the above are blends which are exact
9535 // interleavings with direct instructions supporting them. We currently don't
9536 // handle those well here.
9537 if (Subtarget->hasSSSE3()) {
9540 for (int i = 0; i < 16; ++i)
9541 if (Mask[i] == -1) {
9542 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9544 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9546 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9548 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9549 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9550 if (isSingleInputShuffleMask(Mask))
9551 return V1; // Single inputs are easy.
9553 // Otherwise, blend the two.
9554 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9555 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9556 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9559 // There are special ways we can lower some single-element blends.
9560 if (NumV2Elements == 1)
9561 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9562 Mask, Subtarget, DAG))
9565 // Check whether a compaction lowering can be done. This handles shuffles
9566 // which take every Nth element for some even N. See the helper function for
9569 // We special case these as they can be particularly efficiently handled with
9570 // the PACKUSB instruction on x86 and they show up in common patterns of
9571 // rearranging bytes to truncate wide elements.
9572 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9573 // NumEvenDrops is the power of two stride of the elements. Another way of
9574 // thinking about it is that we need to drop the even elements this many
9575 // times to get the original input.
9576 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9578 // First we need to zero all the dropped bytes.
9579 assert(NumEvenDrops <= 3 &&
9580 "No support for dropping even elements more than 3 times.");
9581 // We use the mask type to pick which bytes are preserved based on how many
9582 // elements are dropped.
9583 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9584 SDValue ByteClearMask =
9585 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9586 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9587 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9589 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9591 // Now pack things back together.
9592 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9593 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9594 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9595 for (int i = 1; i < NumEvenDrops; ++i) {
9596 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9597 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9603 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9604 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9605 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9606 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9608 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9609 MutableArrayRef<int> V1HalfBlendMask,
9610 MutableArrayRef<int> V2HalfBlendMask) {
9611 for (int i = 0; i < 8; ++i)
9612 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9613 V1HalfBlendMask[i] = HalfMask[i];
9615 } else if (HalfMask[i] >= 16) {
9616 V2HalfBlendMask[i] = HalfMask[i] - 16;
9617 HalfMask[i] = i + 8;
9620 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9621 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9623 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9625 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9626 MutableArrayRef<int> HiBlendMask) {
9628 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9629 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9631 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9632 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9633 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9634 [](int M) { return M >= 0 && M % 2 == 1; })) {
9635 // Use a mask to drop the high bytes.
9636 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9637 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9638 DAG.getConstant(0x00FF, MVT::v8i16));
9640 // This will be a single vector shuffle instead of a blend so nuke V2.
9641 V2 = DAG.getUNDEF(MVT::v8i16);
9643 // Squash the masks to point directly into V1.
9644 for (int &M : LoBlendMask)
9647 for (int &M : HiBlendMask)
9651 // Otherwise just unpack the low half of V into V1 and the high half into
9652 // V2 so that we can blend them as i16s.
9653 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9654 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9655 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9656 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9659 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9660 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9661 return std::make_pair(BlendedLo, BlendedHi);
9663 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9664 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9665 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9667 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9668 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9670 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9673 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9675 /// This routine breaks down the specific type of 128-bit shuffle and
9676 /// dispatches to the lowering routines accordingly.
9677 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9678 MVT VT, const X86Subtarget *Subtarget,
9679 SelectionDAG &DAG) {
9680 switch (VT.SimpleTy) {
9682 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9684 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9686 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9688 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9690 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9692 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9695 llvm_unreachable("Unimplemented!");
9699 /// \brief Helper function to test whether a shuffle mask could be
9700 /// simplified by widening the elements being shuffled.
9702 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9703 /// leaves it in an unspecified state.
9705 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9706 /// shuffle masks. The latter have the special property of a '-2' representing
9707 /// a zero-ed lane of a vector.
9708 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9709 SmallVectorImpl<int> &WidenedMask) {
9710 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9711 // If both elements are undef, its trivial.
9712 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9713 WidenedMask.push_back(SM_SentinelUndef);
9717 // Check for an undef mask and a mask value properly aligned to fit with
9718 // a pair of values. If we find such a case, use the non-undef mask's value.
9719 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9720 WidenedMask.push_back(Mask[i + 1] / 2);
9723 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9724 WidenedMask.push_back(Mask[i] / 2);
9728 // When zeroing, we need to spread the zeroing across both lanes to widen.
9729 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9730 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9731 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9732 WidenedMask.push_back(SM_SentinelZero);
9738 // Finally check if the two mask values are adjacent and aligned with
9740 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9741 WidenedMask.push_back(Mask[i] / 2);
9745 // Otherwise we can't safely widen the elements used in this shuffle.
9748 assert(WidenedMask.size() == Mask.size() / 2 &&
9749 "Incorrect size of mask after widening the elements!");
9754 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9756 /// This routine just extracts two subvectors, shuffles them independently, and
9757 /// then concatenates them back together. This should work effectively with all
9758 /// AVX vector shuffle types.
9759 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9760 SDValue V2, ArrayRef<int> Mask,
9761 SelectionDAG &DAG) {
9762 assert(VT.getSizeInBits() >= 256 &&
9763 "Only for 256-bit or wider vector shuffles!");
9764 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9765 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9767 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9768 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9770 int NumElements = VT.getVectorNumElements();
9771 int SplitNumElements = NumElements / 2;
9772 MVT ScalarVT = VT.getScalarType();
9773 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9775 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9776 DAG.getIntPtrConstant(0));
9777 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9778 DAG.getIntPtrConstant(SplitNumElements));
9779 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9780 DAG.getIntPtrConstant(0));
9781 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9782 DAG.getIntPtrConstant(SplitNumElements));
9784 // Now create two 4-way blends of these half-width vectors.
9785 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9786 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9787 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9788 for (int i = 0; i < SplitNumElements; ++i) {
9789 int M = HalfMask[i];
9790 if (M >= NumElements) {
9791 if (M >= NumElements + SplitNumElements)
9795 V2BlendMask.push_back(M - NumElements);
9796 V1BlendMask.push_back(-1);
9797 BlendMask.push_back(SplitNumElements + i);
9798 } else if (M >= 0) {
9799 if (M >= SplitNumElements)
9803 V2BlendMask.push_back(-1);
9804 V1BlendMask.push_back(M);
9805 BlendMask.push_back(i);
9807 V2BlendMask.push_back(-1);
9808 V1BlendMask.push_back(-1);
9809 BlendMask.push_back(-1);
9813 // Because the lowering happens after all combining takes place, we need to
9814 // manually combine these blend masks as much as possible so that we create
9815 // a minimal number of high-level vector shuffle nodes.
9817 // First try just blending the halves of V1 or V2.
9818 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9819 return DAG.getUNDEF(SplitVT);
9820 if (!UseLoV2 && !UseHiV2)
9821 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9822 if (!UseLoV1 && !UseHiV1)
9823 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9825 SDValue V1Blend, V2Blend;
9826 if (UseLoV1 && UseHiV1) {
9828 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9830 // We only use half of V1 so map the usage down into the final blend mask.
9831 V1Blend = UseLoV1 ? LoV1 : HiV1;
9832 for (int i = 0; i < SplitNumElements; ++i)
9833 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9834 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9836 if (UseLoV2 && UseHiV2) {
9838 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9840 // We only use half of V2 so map the usage down into the final blend mask.
9841 V2Blend = UseLoV2 ? LoV2 : HiV2;
9842 for (int i = 0; i < SplitNumElements; ++i)
9843 if (BlendMask[i] >= SplitNumElements)
9844 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9846 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9848 SDValue Lo = HalfBlend(LoMask);
9849 SDValue Hi = HalfBlend(HiMask);
9850 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9853 /// \brief Either split a vector in halves or decompose the shuffles and the
9856 /// This is provided as a good fallback for many lowerings of non-single-input
9857 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9858 /// between splitting the shuffle into 128-bit components and stitching those
9859 /// back together vs. extracting the single-input shuffles and blending those
9861 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9862 SDValue V2, ArrayRef<int> Mask,
9863 SelectionDAG &DAG) {
9864 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9865 "lower single-input shuffles as it "
9866 "could then recurse on itself.");
9867 int Size = Mask.size();
9869 // If this can be modeled as a broadcast of two elements followed by a blend,
9870 // prefer that lowering. This is especially important because broadcasts can
9871 // often fold with memory operands.
9872 auto DoBothBroadcast = [&] {
9873 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9876 if (V2BroadcastIdx == -1)
9877 V2BroadcastIdx = M - Size;
9878 else if (M - Size != V2BroadcastIdx)
9880 } else if (M >= 0) {
9881 if (V1BroadcastIdx == -1)
9883 else if (M != V1BroadcastIdx)
9888 if (DoBothBroadcast())
9889 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9892 // If the inputs all stem from a single 128-bit lane of each input, then we
9893 // split them rather than blending because the split will decompose to
9894 // unusually few instructions.
9895 int LaneCount = VT.getSizeInBits() / 128;
9896 int LaneSize = Size / LaneCount;
9897 SmallBitVector LaneInputs[2];
9898 LaneInputs[0].resize(LaneCount, false);
9899 LaneInputs[1].resize(LaneCount, false);
9900 for (int i = 0; i < Size; ++i)
9902 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9903 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9904 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9906 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9907 // that the decomposed single-input shuffles don't end up here.
9908 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9911 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9912 /// a permutation and blend of those lanes.
9914 /// This essentially blends the out-of-lane inputs to each lane into the lane
9915 /// from a permuted copy of the vector. This lowering strategy results in four
9916 /// instructions in the worst case for a single-input cross lane shuffle which
9917 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9918 /// of. Special cases for each particular shuffle pattern should be handled
9919 /// prior to trying this lowering.
9920 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9921 SDValue V1, SDValue V2,
9923 SelectionDAG &DAG) {
9924 // FIXME: This should probably be generalized for 512-bit vectors as well.
9925 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9926 int LaneSize = Mask.size() / 2;
9928 // If there are only inputs from one 128-bit lane, splitting will in fact be
9929 // less expensive. The flags track wether the given lane contains an element
9930 // that crosses to another lane.
9931 bool LaneCrossing[2] = {false, false};
9932 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9933 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9934 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9935 if (!LaneCrossing[0] || !LaneCrossing[1])
9936 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9938 if (isSingleInputShuffleMask(Mask)) {
9939 SmallVector<int, 32> FlippedBlendMask;
9940 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9941 FlippedBlendMask.push_back(
9942 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9944 : Mask[i] % LaneSize +
9945 (i / LaneSize) * LaneSize + Size));
9947 // Flip the vector, and blend the results which should now be in-lane. The
9948 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9949 // 5 for the high source. The value 3 selects the high half of source 2 and
9950 // the value 2 selects the low half of source 2. We only use source 2 to
9951 // allow folding it into a memory operand.
9952 unsigned PERMMask = 3 | 2 << 4;
9953 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9954 V1, DAG.getConstant(PERMMask, MVT::i8));
9955 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9958 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9959 // will be handled by the above logic and a blend of the results, much like
9960 // other patterns in AVX.
9961 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9964 /// \brief Handle lowering 2-lane 128-bit shuffles.
9965 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9966 SDValue V2, ArrayRef<int> Mask,
9967 const X86Subtarget *Subtarget,
9968 SelectionDAG &DAG) {
9969 // Blends are faster and handle all the non-lane-crossing cases.
9970 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9974 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9975 VT.getVectorNumElements() / 2);
9976 // Check for patterns which can be matched with a single insert of a 128-bit
9978 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9979 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9980 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9981 DAG.getIntPtrConstant(0));
9982 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9983 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9984 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9986 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9987 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9988 DAG.getIntPtrConstant(0));
9989 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9990 DAG.getIntPtrConstant(2));
9991 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9994 // Otherwise form a 128-bit permutation.
9995 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9996 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9997 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9998 DAG.getConstant(PermMask, MVT::i8));
10001 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10002 /// shuffling each lane.
10004 /// This will only succeed when the result of fixing the 128-bit lanes results
10005 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10006 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10007 /// the lane crosses early and then use simpler shuffles within each lane.
10009 /// FIXME: It might be worthwhile at some point to support this without
10010 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10011 /// in x86 only floating point has interesting non-repeating shuffles, and even
10012 /// those are still *marginally* more expensive.
10013 static SDValue lowerVectorShuffleByMerging128BitLanes(
10014 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10015 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10016 assert(!isSingleInputShuffleMask(Mask) &&
10017 "This is only useful with multiple inputs.");
10019 int Size = Mask.size();
10020 int LaneSize = 128 / VT.getScalarSizeInBits();
10021 int NumLanes = Size / LaneSize;
10022 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10024 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10025 // check whether the in-128-bit lane shuffles share a repeating pattern.
10026 SmallVector<int, 4> Lanes;
10027 Lanes.resize(NumLanes, -1);
10028 SmallVector<int, 4> InLaneMask;
10029 InLaneMask.resize(LaneSize, -1);
10030 for (int i = 0; i < Size; ++i) {
10034 int j = i / LaneSize;
10036 if (Lanes[j] < 0) {
10037 // First entry we've seen for this lane.
10038 Lanes[j] = Mask[i] / LaneSize;
10039 } else if (Lanes[j] != Mask[i] / LaneSize) {
10040 // This doesn't match the lane selected previously!
10044 // Check that within each lane we have a consistent shuffle mask.
10045 int k = i % LaneSize;
10046 if (InLaneMask[k] < 0) {
10047 InLaneMask[k] = Mask[i] % LaneSize;
10048 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10049 // This doesn't fit a repeating in-lane mask.
10054 // First shuffle the lanes into place.
10055 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10056 VT.getSizeInBits() / 64);
10057 SmallVector<int, 8> LaneMask;
10058 LaneMask.resize(NumLanes * 2, -1);
10059 for (int i = 0; i < NumLanes; ++i)
10060 if (Lanes[i] >= 0) {
10061 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10062 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10065 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10066 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10067 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10069 // Cast it back to the type we actually want.
10070 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10072 // Now do a simple shuffle that isn't lane crossing.
10073 SmallVector<int, 8> NewMask;
10074 NewMask.resize(Size, -1);
10075 for (int i = 0; i < Size; ++i)
10077 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10078 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10079 "Must not introduce lane crosses at this point!");
10081 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10084 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10087 /// This returns true if the elements from a particular input are already in the
10088 /// slot required by the given mask and require no permutation.
10089 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10090 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10091 int Size = Mask.size();
10092 for (int i = 0; i < Size; ++i)
10093 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10099 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10101 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10102 /// isn't available.
10103 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10104 const X86Subtarget *Subtarget,
10105 SelectionDAG &DAG) {
10107 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10108 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10109 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10110 ArrayRef<int> Mask = SVOp->getMask();
10111 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10113 SmallVector<int, 4> WidenedMask;
10114 if (canWidenShuffleElements(Mask, WidenedMask))
10115 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10118 if (isSingleInputShuffleMask(Mask)) {
10119 // Check for being able to broadcast a single element.
10120 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10121 Mask, Subtarget, DAG))
10124 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10125 // Non-half-crossing single input shuffles can be lowerid with an
10126 // interleaved permutation.
10127 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10128 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10129 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10130 DAG.getConstant(VPERMILPMask, MVT::i8));
10133 // With AVX2 we have direct support for this permutation.
10134 if (Subtarget->hasAVX2())
10135 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10136 getV4X86ShuffleImm8ForMask(Mask, DAG));
10138 // Otherwise, fall back.
10139 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10143 // X86 has dedicated unpack instructions that can handle specific blend
10144 // operations: UNPCKH and UNPCKL.
10145 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10146 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10147 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10148 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10150 // If we have a single input to the zero element, insert that into V1 if we
10151 // can do so cheaply.
10152 int NumV2Elements =
10153 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10154 if (NumV2Elements == 1 && Mask[0] >= 4)
10155 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10156 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10159 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10163 // Check if the blend happens to exactly fit that of SHUFPD.
10164 if ((Mask[0] == -1 || Mask[0] < 2) &&
10165 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10166 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10167 (Mask[3] == -1 || Mask[3] >= 6)) {
10168 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10169 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10170 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10171 DAG.getConstant(SHUFPDMask, MVT::i8));
10173 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10174 (Mask[1] == -1 || Mask[1] < 2) &&
10175 (Mask[2] == -1 || Mask[2] >= 6) &&
10176 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10177 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10178 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10179 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10180 DAG.getConstant(SHUFPDMask, MVT::i8));
10183 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10184 // shuffle. However, if we have AVX2 and either inputs are already in place,
10185 // we will be able to shuffle even across lanes the other input in a single
10186 // instruction so skip this pattern.
10187 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10188 isShuffleMaskInputInPlace(1, Mask))))
10189 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10190 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10193 // If we have AVX2 then we always want to lower with a blend because an v4 we
10194 // can fully permute the elements.
10195 if (Subtarget->hasAVX2())
10196 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10199 // Otherwise fall back on generic lowering.
10200 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10203 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10205 /// This routine is only called when we have AVX2 and thus a reasonable
10206 /// instruction set for v4i64 shuffling..
10207 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10208 const X86Subtarget *Subtarget,
10209 SelectionDAG &DAG) {
10211 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10212 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10213 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10214 ArrayRef<int> Mask = SVOp->getMask();
10215 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10216 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10218 SmallVector<int, 4> WidenedMask;
10219 if (canWidenShuffleElements(Mask, WidenedMask))
10220 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10223 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10227 // Check for being able to broadcast a single element.
10228 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10229 Mask, Subtarget, DAG))
10232 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10233 // use lower latency instructions that will operate on both 128-bit lanes.
10234 SmallVector<int, 2> RepeatedMask;
10235 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10236 if (isSingleInputShuffleMask(Mask)) {
10237 int PSHUFDMask[] = {-1, -1, -1, -1};
10238 for (int i = 0; i < 2; ++i)
10239 if (RepeatedMask[i] >= 0) {
10240 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10241 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10243 return DAG.getNode(
10244 ISD::BITCAST, DL, MVT::v4i64,
10245 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10246 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10247 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10250 // Use dedicated unpack instructions for masks that match their pattern.
10251 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10252 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10253 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10254 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10257 // AVX2 provides a direct instruction for permuting a single input across
10259 if (isSingleInputShuffleMask(Mask))
10260 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10261 getV4X86ShuffleImm8ForMask(Mask, DAG));
10263 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10264 // shuffle. However, if we have AVX2 and either inputs are already in place,
10265 // we will be able to shuffle even across lanes the other input in a single
10266 // instruction so skip this pattern.
10267 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10268 isShuffleMaskInputInPlace(1, Mask))))
10269 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10270 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10273 // Otherwise fall back on generic blend lowering.
10274 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10278 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10280 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10281 /// isn't available.
10282 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10283 const X86Subtarget *Subtarget,
10284 SelectionDAG &DAG) {
10286 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10287 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10288 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10289 ArrayRef<int> Mask = SVOp->getMask();
10290 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10292 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10296 // Check for being able to broadcast a single element.
10297 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10298 Mask, Subtarget, DAG))
10301 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10302 // options to efficiently lower the shuffle.
10303 SmallVector<int, 4> RepeatedMask;
10304 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10305 assert(RepeatedMask.size() == 4 &&
10306 "Repeated masks must be half the mask width!");
10307 if (isSingleInputShuffleMask(Mask))
10308 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10309 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10311 // Use dedicated unpack instructions for masks that match their pattern.
10312 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10313 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10314 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10315 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10317 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10318 // have already handled any direct blends. We also need to squash the
10319 // repeated mask into a simulated v4f32 mask.
10320 for (int i = 0; i < 4; ++i)
10321 if (RepeatedMask[i] >= 8)
10322 RepeatedMask[i] -= 4;
10323 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10326 // If we have a single input shuffle with different shuffle patterns in the
10327 // two 128-bit lanes use the variable mask to VPERMILPS.
10328 if (isSingleInputShuffleMask(Mask)) {
10329 SDValue VPermMask[8];
10330 for (int i = 0; i < 8; ++i)
10331 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10332 : DAG.getConstant(Mask[i], MVT::i32);
10333 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10334 return DAG.getNode(
10335 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10336 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10338 if (Subtarget->hasAVX2())
10339 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10340 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10341 DAG.getNode(ISD::BUILD_VECTOR, DL,
10342 MVT::v8i32, VPermMask)),
10345 // Otherwise, fall back.
10346 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10350 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10352 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10353 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10356 // If we have AVX2 then we always want to lower with a blend because at v8 we
10357 // can fully permute the elements.
10358 if (Subtarget->hasAVX2())
10359 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10362 // Otherwise fall back on generic lowering.
10363 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10366 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10368 /// This routine is only called when we have AVX2 and thus a reasonable
10369 /// instruction set for v8i32 shuffling..
10370 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10371 const X86Subtarget *Subtarget,
10372 SelectionDAG &DAG) {
10374 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10375 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10376 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10377 ArrayRef<int> Mask = SVOp->getMask();
10378 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10379 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10381 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10385 // Check for being able to broadcast a single element.
10386 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10387 Mask, Subtarget, DAG))
10390 // If the shuffle mask is repeated in each 128-bit lane we can use more
10391 // efficient instructions that mirror the shuffles across the two 128-bit
10393 SmallVector<int, 4> RepeatedMask;
10394 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10395 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10396 if (isSingleInputShuffleMask(Mask))
10397 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10398 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10400 // Use dedicated unpack instructions for masks that match their pattern.
10401 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10402 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10403 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10404 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10407 // If the shuffle patterns aren't repeated but it is a single input, directly
10408 // generate a cross-lane VPERMD instruction.
10409 if (isSingleInputShuffleMask(Mask)) {
10410 SDValue VPermMask[8];
10411 for (int i = 0; i < 8; ++i)
10412 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10413 : DAG.getConstant(Mask[i], MVT::i32);
10414 return DAG.getNode(
10415 X86ISD::VPERMV, DL, MVT::v8i32,
10416 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10419 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10421 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10422 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10425 // Otherwise fall back on generic blend lowering.
10426 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10430 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10432 /// This routine is only called when we have AVX2 and thus a reasonable
10433 /// instruction set for v16i16 shuffling..
10434 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10435 const X86Subtarget *Subtarget,
10436 SelectionDAG &DAG) {
10438 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10439 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10440 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10441 ArrayRef<int> Mask = SVOp->getMask();
10442 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10443 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10445 // Check for being able to broadcast a single element.
10446 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10447 Mask, Subtarget, DAG))
10450 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10454 // Use dedicated unpack instructions for masks that match their pattern.
10455 if (isShuffleEquivalent(Mask,
10456 // First 128-bit lane:
10457 0, 16, 1, 17, 2, 18, 3, 19,
10458 // Second 128-bit lane:
10459 8, 24, 9, 25, 10, 26, 11, 27))
10460 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10461 if (isShuffleEquivalent(Mask,
10462 // First 128-bit lane:
10463 4, 20, 5, 21, 6, 22, 7, 23,
10464 // Second 128-bit lane:
10465 12, 28, 13, 29, 14, 30, 15, 31))
10466 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10468 if (isSingleInputShuffleMask(Mask)) {
10469 // There are no generalized cross-lane shuffle operations available on i16
10471 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10472 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10475 SDValue PSHUFBMask[32];
10476 for (int i = 0; i < 16; ++i) {
10477 if (Mask[i] == -1) {
10478 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10482 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10483 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10484 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10485 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10487 return DAG.getNode(
10488 ISD::BITCAST, DL, MVT::v16i16,
10490 X86ISD::PSHUFB, DL, MVT::v32i8,
10491 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10492 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10495 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10497 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10498 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10501 // Otherwise fall back on generic lowering.
10502 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10505 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10507 /// This routine is only called when we have AVX2 and thus a reasonable
10508 /// instruction set for v32i8 shuffling..
10509 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10510 const X86Subtarget *Subtarget,
10511 SelectionDAG &DAG) {
10513 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10514 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10515 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10516 ArrayRef<int> Mask = SVOp->getMask();
10517 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10518 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10520 // Check for being able to broadcast a single element.
10521 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10522 Mask, Subtarget, DAG))
10525 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10529 // Use dedicated unpack instructions for masks that match their pattern.
10530 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10532 if (isShuffleEquivalent(
10534 // First 128-bit lane:
10535 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10536 // Second 128-bit lane:
10537 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10538 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10539 if (isShuffleEquivalent(
10541 // First 128-bit lane:
10542 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10543 // Second 128-bit lane:
10544 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10545 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10547 if (isSingleInputShuffleMask(Mask)) {
10548 // There are no generalized cross-lane shuffle operations available on i8
10550 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10551 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10554 SDValue PSHUFBMask[32];
10555 for (int i = 0; i < 32; ++i)
10558 ? DAG.getUNDEF(MVT::i8)
10559 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10561 return DAG.getNode(
10562 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10563 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10566 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10568 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10569 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10572 // Otherwise fall back on generic lowering.
10573 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10576 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10578 /// This routine either breaks down the specific type of a 256-bit x86 vector
10579 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10580 /// together based on the available instructions.
10581 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10582 MVT VT, const X86Subtarget *Subtarget,
10583 SelectionDAG &DAG) {
10585 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10586 ArrayRef<int> Mask = SVOp->getMask();
10588 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10589 // check for those subtargets here and avoid much of the subtarget querying in
10590 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10591 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10592 // floating point types there eventually, just immediately cast everything to
10593 // a float and operate entirely in that domain.
10594 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10595 int ElementBits = VT.getScalarSizeInBits();
10596 if (ElementBits < 32)
10597 // No floating point type available, decompose into 128-bit vectors.
10598 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10600 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10601 VT.getVectorNumElements());
10602 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10603 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10604 return DAG.getNode(ISD::BITCAST, DL, VT,
10605 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10608 switch (VT.SimpleTy) {
10610 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10612 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10614 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10616 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10618 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10620 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10623 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10627 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10628 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10629 const X86Subtarget *Subtarget,
10630 SelectionDAG &DAG) {
10632 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10633 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10634 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10635 ArrayRef<int> Mask = SVOp->getMask();
10636 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10638 // FIXME: Implement direct support for this type!
10639 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10642 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10643 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10644 const X86Subtarget *Subtarget,
10645 SelectionDAG &DAG) {
10647 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10648 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10649 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10650 ArrayRef<int> Mask = SVOp->getMask();
10651 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10653 // FIXME: Implement direct support for this type!
10654 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10657 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10658 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10659 const X86Subtarget *Subtarget,
10660 SelectionDAG &DAG) {
10662 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10663 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10664 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10665 ArrayRef<int> Mask = SVOp->getMask();
10666 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10668 // FIXME: Implement direct support for this type!
10669 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10672 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10673 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10674 const X86Subtarget *Subtarget,
10675 SelectionDAG &DAG) {
10677 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10678 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10679 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10680 ArrayRef<int> Mask = SVOp->getMask();
10681 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10683 // FIXME: Implement direct support for this type!
10684 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10687 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10688 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10689 const X86Subtarget *Subtarget,
10690 SelectionDAG &DAG) {
10692 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10693 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10694 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10695 ArrayRef<int> Mask = SVOp->getMask();
10696 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10697 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10699 // FIXME: Implement direct support for this type!
10700 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10703 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10704 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10705 const X86Subtarget *Subtarget,
10706 SelectionDAG &DAG) {
10708 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10709 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10710 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10711 ArrayRef<int> Mask = SVOp->getMask();
10712 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10713 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10715 // FIXME: Implement direct support for this type!
10716 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10719 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10721 /// This routine either breaks down the specific type of a 512-bit x86 vector
10722 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10723 /// together based on the available instructions.
10724 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10725 MVT VT, const X86Subtarget *Subtarget,
10726 SelectionDAG &DAG) {
10728 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10729 ArrayRef<int> Mask = SVOp->getMask();
10730 assert(Subtarget->hasAVX512() &&
10731 "Cannot lower 512-bit vectors w/ basic ISA!");
10733 // Check for being able to broadcast a single element.
10734 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10735 Mask, Subtarget, DAG))
10738 // Dispatch to each element type for lowering. If we don't have supprot for
10739 // specific element type shuffles at 512 bits, immediately split them and
10740 // lower them. Each lowering routine of a given type is allowed to assume that
10741 // the requisite ISA extensions for that element type are available.
10742 switch (VT.SimpleTy) {
10744 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10746 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10748 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10750 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10752 if (Subtarget->hasBWI())
10753 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10756 if (Subtarget->hasBWI())
10757 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10761 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10764 // Otherwise fall back on splitting.
10765 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10768 /// \brief Top-level lowering for x86 vector shuffles.
10770 /// This handles decomposition, canonicalization, and lowering of all x86
10771 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10772 /// above in helper routines. The canonicalization attempts to widen shuffles
10773 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10774 /// s.t. only one of the two inputs needs to be tested, etc.
10775 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10776 SelectionDAG &DAG) {
10777 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10778 ArrayRef<int> Mask = SVOp->getMask();
10779 SDValue V1 = Op.getOperand(0);
10780 SDValue V2 = Op.getOperand(1);
10781 MVT VT = Op.getSimpleValueType();
10782 int NumElements = VT.getVectorNumElements();
10785 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10787 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10788 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10789 if (V1IsUndef && V2IsUndef)
10790 return DAG.getUNDEF(VT);
10792 // When we create a shuffle node we put the UNDEF node to second operand,
10793 // but in some cases the first operand may be transformed to UNDEF.
10794 // In this case we should just commute the node.
10796 return DAG.getCommutedVectorShuffle(*SVOp);
10798 // Check for non-undef masks pointing at an undef vector and make the masks
10799 // undef as well. This makes it easier to match the shuffle based solely on
10803 if (M >= NumElements) {
10804 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10805 for (int &M : NewMask)
10806 if (M >= NumElements)
10808 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10811 // Try to collapse shuffles into using a vector type with fewer elements but
10812 // wider element types. We cap this to not form integers or floating point
10813 // elements wider than 64 bits, but it might be interesting to form i128
10814 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10815 SmallVector<int, 16> WidenedMask;
10816 if (VT.getScalarSizeInBits() < 64 &&
10817 canWidenShuffleElements(Mask, WidenedMask)) {
10818 MVT NewEltVT = VT.isFloatingPoint()
10819 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10820 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10821 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10822 // Make sure that the new vector type is legal. For example, v2f64 isn't
10824 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10825 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10826 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10827 return DAG.getNode(ISD::BITCAST, dl, VT,
10828 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10832 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10833 for (int M : SVOp->getMask())
10835 ++NumUndefElements;
10836 else if (M < NumElements)
10841 // Commute the shuffle as needed such that more elements come from V1 than
10842 // V2. This allows us to match the shuffle pattern strictly on how many
10843 // elements come from V1 without handling the symmetric cases.
10844 if (NumV2Elements > NumV1Elements)
10845 return DAG.getCommutedVectorShuffle(*SVOp);
10847 // When the number of V1 and V2 elements are the same, try to minimize the
10848 // number of uses of V2 in the low half of the vector. When that is tied,
10849 // ensure that the sum of indices for V1 is equal to or lower than the sum
10850 // indices for V2. When those are equal, try to ensure that the number of odd
10851 // indices for V1 is lower than the number of odd indices for V2.
10852 if (NumV1Elements == NumV2Elements) {
10853 int LowV1Elements = 0, LowV2Elements = 0;
10854 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10855 if (M >= NumElements)
10859 if (LowV2Elements > LowV1Elements) {
10860 return DAG.getCommutedVectorShuffle(*SVOp);
10861 } else if (LowV2Elements == LowV1Elements) {
10862 int SumV1Indices = 0, SumV2Indices = 0;
10863 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10864 if (SVOp->getMask()[i] >= NumElements)
10866 else if (SVOp->getMask()[i] >= 0)
10868 if (SumV2Indices < SumV1Indices) {
10869 return DAG.getCommutedVectorShuffle(*SVOp);
10870 } else if (SumV2Indices == SumV1Indices) {
10871 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10872 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10873 if (SVOp->getMask()[i] >= NumElements)
10874 NumV2OddIndices += i % 2;
10875 else if (SVOp->getMask()[i] >= 0)
10876 NumV1OddIndices += i % 2;
10877 if (NumV2OddIndices < NumV1OddIndices)
10878 return DAG.getCommutedVectorShuffle(*SVOp);
10883 // For each vector width, delegate to a specialized lowering routine.
10884 if (VT.getSizeInBits() == 128)
10885 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10887 if (VT.getSizeInBits() == 256)
10888 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10890 // Force AVX-512 vectors to be scalarized for now.
10891 // FIXME: Implement AVX-512 support!
10892 if (VT.getSizeInBits() == 512)
10893 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10895 llvm_unreachable("Unimplemented!");
10899 //===----------------------------------------------------------------------===//
10900 // Legacy vector shuffle lowering
10902 // This code is the legacy code handling vector shuffles until the above
10903 // replaces its functionality and performance.
10904 //===----------------------------------------------------------------------===//
10906 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10907 bool hasInt256, unsigned *MaskOut = nullptr) {
10908 MVT EltVT = VT.getVectorElementType();
10910 // There is no blend with immediate in AVX-512.
10911 if (VT.is512BitVector())
10914 if (!hasSSE41 || EltVT == MVT::i8)
10916 if (!hasInt256 && VT == MVT::v16i16)
10919 unsigned MaskValue = 0;
10920 unsigned NumElems = VT.getVectorNumElements();
10921 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10922 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10923 unsigned NumElemsInLane = NumElems / NumLanes;
10925 // Blend for v16i16 should be symetric for the both lanes.
10926 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10928 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10929 int EltIdx = MaskVals[i];
10931 if ((EltIdx < 0 || EltIdx == (int)i) &&
10932 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10935 if (((unsigned)EltIdx == (i + NumElems)) &&
10936 (SndLaneEltIdx < 0 ||
10937 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10938 MaskValue |= (1 << i);
10944 *MaskOut = MaskValue;
10948 // Try to lower a shuffle node into a simple blend instruction.
10949 // This function assumes isBlendMask returns true for this
10950 // SuffleVectorSDNode
10951 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10952 unsigned MaskValue,
10953 const X86Subtarget *Subtarget,
10954 SelectionDAG &DAG) {
10955 MVT VT = SVOp->getSimpleValueType(0);
10956 MVT EltVT = VT.getVectorElementType();
10957 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10958 Subtarget->hasInt256() && "Trying to lower a "
10959 "VECTOR_SHUFFLE to a Blend but "
10960 "with the wrong mask"));
10961 SDValue V1 = SVOp->getOperand(0);
10962 SDValue V2 = SVOp->getOperand(1);
10964 unsigned NumElems = VT.getVectorNumElements();
10966 // Convert i32 vectors to floating point if it is not AVX2.
10967 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10969 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10970 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10972 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10973 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10976 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10977 DAG.getConstant(MaskValue, MVT::i32));
10978 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10981 /// In vector type \p VT, return true if the element at index \p InputIdx
10982 /// falls on a different 128-bit lane than \p OutputIdx.
10983 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10984 unsigned OutputIdx) {
10985 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10986 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10989 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10990 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10991 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10992 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10994 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10995 SelectionDAG &DAG) {
10996 MVT VT = V1.getSimpleValueType();
10997 assert(VT.is128BitVector() || VT.is256BitVector());
10999 MVT EltVT = VT.getVectorElementType();
11000 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11001 unsigned NumElts = VT.getVectorNumElements();
11003 SmallVector<SDValue, 32> PshufbMask;
11004 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11005 int InputIdx = MaskVals[OutputIdx];
11006 unsigned InputByteIdx;
11008 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11009 InputByteIdx = 0x80;
11011 // Cross lane is not allowed.
11012 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11014 InputByteIdx = InputIdx * EltSizeInBytes;
11015 // Index is an byte offset within the 128-bit lane.
11016 InputByteIdx &= 0xf;
11019 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11020 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11021 if (InputByteIdx != 0x80)
11026 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11028 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11029 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11030 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11033 // v8i16 shuffles - Prefer shuffles in the following order:
11034 // 1. [all] pshuflw, pshufhw, optional move
11035 // 2. [ssse3] 1 x pshufb
11036 // 3. [ssse3] 2 x pshufb + 1 x por
11037 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11039 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11040 SelectionDAG &DAG) {
11041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11042 SDValue V1 = SVOp->getOperand(0);
11043 SDValue V2 = SVOp->getOperand(1);
11045 SmallVector<int, 8> MaskVals;
11047 // Determine if more than 1 of the words in each of the low and high quadwords
11048 // of the result come from the same quadword of one of the two inputs. Undef
11049 // mask values count as coming from any quadword, for better codegen.
11051 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11052 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11053 unsigned LoQuad[] = { 0, 0, 0, 0 };
11054 unsigned HiQuad[] = { 0, 0, 0, 0 };
11055 // Indices of quads used.
11056 std::bitset<4> InputQuads;
11057 for (unsigned i = 0; i < 8; ++i) {
11058 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11059 int EltIdx = SVOp->getMaskElt(i);
11060 MaskVals.push_back(EltIdx);
11068 ++Quad[EltIdx / 4];
11069 InputQuads.set(EltIdx / 4);
11072 int BestLoQuad = -1;
11073 unsigned MaxQuad = 1;
11074 for (unsigned i = 0; i < 4; ++i) {
11075 if (LoQuad[i] > MaxQuad) {
11077 MaxQuad = LoQuad[i];
11081 int BestHiQuad = -1;
11083 for (unsigned i = 0; i < 4; ++i) {
11084 if (HiQuad[i] > MaxQuad) {
11086 MaxQuad = HiQuad[i];
11090 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11091 // of the two input vectors, shuffle them into one input vector so only a
11092 // single pshufb instruction is necessary. If there are more than 2 input
11093 // quads, disable the next transformation since it does not help SSSE3.
11094 bool V1Used = InputQuads[0] || InputQuads[1];
11095 bool V2Used = InputQuads[2] || InputQuads[3];
11096 if (Subtarget->hasSSSE3()) {
11097 if (InputQuads.count() == 2 && V1Used && V2Used) {
11098 BestLoQuad = InputQuads[0] ? 0 : 1;
11099 BestHiQuad = InputQuads[2] ? 2 : 3;
11101 if (InputQuads.count() > 2) {
11107 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11108 // the shuffle mask. If a quad is scored as -1, that means that it contains
11109 // words from all 4 input quadwords.
11111 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11113 BestLoQuad < 0 ? 0 : BestLoQuad,
11114 BestHiQuad < 0 ? 1 : BestHiQuad
11116 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11117 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11118 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11119 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11121 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11122 // source words for the shuffle, to aid later transformations.
11123 bool AllWordsInNewV = true;
11124 bool InOrder[2] = { true, true };
11125 for (unsigned i = 0; i != 8; ++i) {
11126 int idx = MaskVals[i];
11128 InOrder[i/4] = false;
11129 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11131 AllWordsInNewV = false;
11135 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11136 if (AllWordsInNewV) {
11137 for (int i = 0; i != 8; ++i) {
11138 int idx = MaskVals[i];
11141 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11142 if ((idx != i) && idx < 4)
11144 if ((idx != i) && idx > 3)
11153 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11154 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11155 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11156 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11157 unsigned TargetMask = 0;
11158 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11159 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11161 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11162 getShufflePSHUFLWImmediate(SVOp);
11163 V1 = NewV.getOperand(0);
11164 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11168 // Promote splats to a larger type which usually leads to more efficient code.
11169 // FIXME: Is this true if pshufb is available?
11170 if (SVOp->isSplat())
11171 return PromoteSplat(SVOp, DAG);
11173 // If we have SSSE3, and all words of the result are from 1 input vector,
11174 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11175 // is present, fall back to case 4.
11176 if (Subtarget->hasSSSE3()) {
11177 SmallVector<SDValue,16> pshufbMask;
11179 // If we have elements from both input vectors, set the high bit of the
11180 // shuffle mask element to zero out elements that come from V2 in the V1
11181 // mask, and elements that come from V1 in the V2 mask, so that the two
11182 // results can be OR'd together.
11183 bool TwoInputs = V1Used && V2Used;
11184 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11186 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11188 // Calculate the shuffle mask for the second input, shuffle it, and
11189 // OR it with the first shuffled input.
11190 CommuteVectorShuffleMask(MaskVals, 8);
11191 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11192 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11193 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11196 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11197 // and update MaskVals with new element order.
11198 std::bitset<8> InOrder;
11199 if (BestLoQuad >= 0) {
11200 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11201 for (int i = 0; i != 4; ++i) {
11202 int idx = MaskVals[i];
11205 } else if ((idx / 4) == BestLoQuad) {
11206 MaskV[i] = idx & 3;
11210 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11213 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11214 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11215 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11216 NewV.getOperand(0),
11217 getShufflePSHUFLWImmediate(SVOp), DAG);
11221 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11222 // and update MaskVals with the new element order.
11223 if (BestHiQuad >= 0) {
11224 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11225 for (unsigned i = 4; i != 8; ++i) {
11226 int idx = MaskVals[i];
11229 } else if ((idx / 4) == BestHiQuad) {
11230 MaskV[i] = (idx & 3) + 4;
11234 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11237 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11238 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11239 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11240 NewV.getOperand(0),
11241 getShufflePSHUFHWImmediate(SVOp), DAG);
11245 // In case BestHi & BestLo were both -1, which means each quadword has a word
11246 // from each of the four input quadwords, calculate the InOrder bitvector now
11247 // before falling through to the insert/extract cleanup.
11248 if (BestLoQuad == -1 && BestHiQuad == -1) {
11250 for (int i = 0; i != 8; ++i)
11251 if (MaskVals[i] < 0 || MaskVals[i] == i)
11255 // The other elements are put in the right place using pextrw and pinsrw.
11256 for (unsigned i = 0; i != 8; ++i) {
11259 int EltIdx = MaskVals[i];
11262 SDValue ExtOp = (EltIdx < 8) ?
11263 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11264 DAG.getIntPtrConstant(EltIdx)) :
11265 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11266 DAG.getIntPtrConstant(EltIdx - 8));
11267 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11268 DAG.getIntPtrConstant(i));
11273 /// \brief v16i16 shuffles
11275 /// FIXME: We only support generation of a single pshufb currently. We can
11276 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11277 /// well (e.g 2 x pshufb + 1 x por).
11279 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11280 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11281 SDValue V1 = SVOp->getOperand(0);
11282 SDValue V2 = SVOp->getOperand(1);
11285 if (V2.getOpcode() != ISD::UNDEF)
11288 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11289 return getPSHUFB(MaskVals, V1, dl, DAG);
11292 // v16i8 shuffles - Prefer shuffles in the following order:
11293 // 1. [ssse3] 1 x pshufb
11294 // 2. [ssse3] 2 x pshufb + 1 x por
11295 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11296 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11297 const X86Subtarget* Subtarget,
11298 SelectionDAG &DAG) {
11299 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11300 SDValue V1 = SVOp->getOperand(0);
11301 SDValue V2 = SVOp->getOperand(1);
11303 ArrayRef<int> MaskVals = SVOp->getMask();
11305 // Promote splats to a larger type which usually leads to more efficient code.
11306 // FIXME: Is this true if pshufb is available?
11307 if (SVOp->isSplat())
11308 return PromoteSplat(SVOp, DAG);
11310 // If we have SSSE3, case 1 is generated when all result bytes come from
11311 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11312 // present, fall back to case 3.
11314 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11315 if (Subtarget->hasSSSE3()) {
11316 SmallVector<SDValue,16> pshufbMask;
11318 // If all result elements are from one input vector, then only translate
11319 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11321 // Otherwise, we have elements from both input vectors, and must zero out
11322 // elements that come from V2 in the first mask, and V1 in the second mask
11323 // so that we can OR them together.
11324 for (unsigned i = 0; i != 16; ++i) {
11325 int EltIdx = MaskVals[i];
11326 if (EltIdx < 0 || EltIdx >= 16)
11328 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11330 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11331 DAG.getNode(ISD::BUILD_VECTOR, dl,
11332 MVT::v16i8, pshufbMask));
11334 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11335 // the 2nd operand if it's undefined or zero.
11336 if (V2.getOpcode() == ISD::UNDEF ||
11337 ISD::isBuildVectorAllZeros(V2.getNode()))
11340 // Calculate the shuffle mask for the second input, shuffle it, and
11341 // OR it with the first shuffled input.
11342 pshufbMask.clear();
11343 for (unsigned i = 0; i != 16; ++i) {
11344 int EltIdx = MaskVals[i];
11345 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11346 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11348 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11349 DAG.getNode(ISD::BUILD_VECTOR, dl,
11350 MVT::v16i8, pshufbMask));
11351 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11354 // No SSSE3 - Calculate in place words and then fix all out of place words
11355 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11356 // the 16 different words that comprise the two doublequadword input vectors.
11357 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11358 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11360 for (int i = 0; i != 8; ++i) {
11361 int Elt0 = MaskVals[i*2];
11362 int Elt1 = MaskVals[i*2+1];
11364 // This word of the result is all undef, skip it.
11365 if (Elt0 < 0 && Elt1 < 0)
11368 // This word of the result is already in the correct place, skip it.
11369 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11372 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11373 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11376 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11377 // using a single extract together, load it and store it.
11378 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11379 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11380 DAG.getIntPtrConstant(Elt1 / 2));
11381 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11382 DAG.getIntPtrConstant(i));
11386 // If Elt1 is defined, extract it from the appropriate source. If the
11387 // source byte is not also odd, shift the extracted word left 8 bits
11388 // otherwise clear the bottom 8 bits if we need to do an or.
11390 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11391 DAG.getIntPtrConstant(Elt1 / 2));
11392 if ((Elt1 & 1) == 0)
11393 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11395 TLI.getShiftAmountTy(InsElt.getValueType())));
11396 else if (Elt0 >= 0)
11397 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11398 DAG.getConstant(0xFF00, MVT::i16));
11400 // If Elt0 is defined, extract it from the appropriate source. If the
11401 // source byte is not also even, shift the extracted word right 8 bits. If
11402 // Elt1 was also defined, OR the extracted values together before
11403 // inserting them in the result.
11405 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11406 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11407 if ((Elt0 & 1) != 0)
11408 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11410 TLI.getShiftAmountTy(InsElt0.getValueType())));
11411 else if (Elt1 >= 0)
11412 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11413 DAG.getConstant(0x00FF, MVT::i16));
11414 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11417 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11418 DAG.getIntPtrConstant(i));
11420 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11423 // v32i8 shuffles - Translate to VPSHUFB if possible.
11425 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11426 const X86Subtarget *Subtarget,
11427 SelectionDAG &DAG) {
11428 MVT VT = SVOp->getSimpleValueType(0);
11429 SDValue V1 = SVOp->getOperand(0);
11430 SDValue V2 = SVOp->getOperand(1);
11432 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11434 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11435 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11436 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11438 // VPSHUFB may be generated if
11439 // (1) one of input vector is undefined or zeroinitializer.
11440 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11441 // And (2) the mask indexes don't cross the 128-bit lane.
11442 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11443 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11446 if (V1IsAllZero && !V2IsAllZero) {
11447 CommuteVectorShuffleMask(MaskVals, 32);
11450 return getPSHUFB(MaskVals, V1, dl, DAG);
11453 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11454 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11455 /// done when every pair / quad of shuffle mask elements point to elements in
11456 /// the right sequence. e.g.
11457 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11459 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11460 SelectionDAG &DAG) {
11461 MVT VT = SVOp->getSimpleValueType(0);
11463 unsigned NumElems = VT.getVectorNumElements();
11466 switch (VT.SimpleTy) {
11467 default: llvm_unreachable("Unexpected!");
11470 return SDValue(SVOp, 0);
11471 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11472 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11473 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11474 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11475 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11476 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11479 SmallVector<int, 8> MaskVec;
11480 for (unsigned i = 0; i != NumElems; i += Scale) {
11482 for (unsigned j = 0; j != Scale; ++j) {
11483 int EltIdx = SVOp->getMaskElt(i+j);
11487 StartIdx = (EltIdx / Scale);
11488 if (EltIdx != (int)(StartIdx*Scale + j))
11491 MaskVec.push_back(StartIdx);
11494 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11495 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11496 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11499 /// getVZextMovL - Return a zero-extending vector move low node.
11501 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11502 SDValue SrcOp, SelectionDAG &DAG,
11503 const X86Subtarget *Subtarget, SDLoc dl) {
11504 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11505 LoadSDNode *LD = nullptr;
11506 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11507 LD = dyn_cast<LoadSDNode>(SrcOp);
11509 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11511 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11512 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11513 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11514 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11515 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11517 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11518 return DAG.getNode(ISD::BITCAST, dl, VT,
11519 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11520 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11522 SrcOp.getOperand(0)
11528 return DAG.getNode(ISD::BITCAST, dl, VT,
11529 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11530 DAG.getNode(ISD::BITCAST, dl,
11534 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11535 /// which could not be matched by any known target speficic shuffle
11537 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11539 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11540 if (NewOp.getNode())
11543 MVT VT = SVOp->getSimpleValueType(0);
11545 unsigned NumElems = VT.getVectorNumElements();
11546 unsigned NumLaneElems = NumElems / 2;
11549 MVT EltVT = VT.getVectorElementType();
11550 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11553 SmallVector<int, 16> Mask;
11554 for (unsigned l = 0; l < 2; ++l) {
11555 // Build a shuffle mask for the output, discovering on the fly which
11556 // input vectors to use as shuffle operands (recorded in InputUsed).
11557 // If building a suitable shuffle vector proves too hard, then bail
11558 // out with UseBuildVector set.
11559 bool UseBuildVector = false;
11560 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11561 unsigned LaneStart = l * NumLaneElems;
11562 for (unsigned i = 0; i != NumLaneElems; ++i) {
11563 // The mask element. This indexes into the input.
11564 int Idx = SVOp->getMaskElt(i+LaneStart);
11566 // the mask element does not index into any input vector.
11567 Mask.push_back(-1);
11571 // The input vector this mask element indexes into.
11572 int Input = Idx / NumLaneElems;
11574 // Turn the index into an offset from the start of the input vector.
11575 Idx -= Input * NumLaneElems;
11577 // Find or create a shuffle vector operand to hold this input.
11579 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11580 if (InputUsed[OpNo] == Input)
11581 // This input vector is already an operand.
11583 if (InputUsed[OpNo] < 0) {
11584 // Create a new operand for this input vector.
11585 InputUsed[OpNo] = Input;
11590 if (OpNo >= array_lengthof(InputUsed)) {
11591 // More than two input vectors used! Give up on trying to create a
11592 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11593 UseBuildVector = true;
11597 // Add the mask index for the new shuffle vector.
11598 Mask.push_back(Idx + OpNo * NumLaneElems);
11601 if (UseBuildVector) {
11602 SmallVector<SDValue, 16> SVOps;
11603 for (unsigned i = 0; i != NumLaneElems; ++i) {
11604 // The mask element. This indexes into the input.
11605 int Idx = SVOp->getMaskElt(i+LaneStart);
11607 SVOps.push_back(DAG.getUNDEF(EltVT));
11611 // The input vector this mask element indexes into.
11612 int Input = Idx / NumElems;
11614 // Turn the index into an offset from the start of the input vector.
11615 Idx -= Input * NumElems;
11617 // Extract the vector element by hand.
11618 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11619 SVOp->getOperand(Input),
11620 DAG.getIntPtrConstant(Idx)));
11623 // Construct the output using a BUILD_VECTOR.
11624 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11625 } else if (InputUsed[0] < 0) {
11626 // No input vectors were used! The result is undefined.
11627 Output[l] = DAG.getUNDEF(NVT);
11629 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11630 (InputUsed[0] % 2) * NumLaneElems,
11632 // If only one input was used, use an undefined vector for the other.
11633 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11634 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11635 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11636 // At least one input vector was used. Create a new shuffle vector.
11637 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11643 // Concatenate the result back
11644 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11647 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11648 /// 4 elements, and match them with several different shuffle types.
11650 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11651 SDValue V1 = SVOp->getOperand(0);
11652 SDValue V2 = SVOp->getOperand(1);
11654 MVT VT = SVOp->getSimpleValueType(0);
11656 assert(VT.is128BitVector() && "Unsupported vector size");
11658 std::pair<int, int> Locs[4];
11659 int Mask1[] = { -1, -1, -1, -1 };
11660 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11662 unsigned NumHi = 0;
11663 unsigned NumLo = 0;
11664 for (unsigned i = 0; i != 4; ++i) {
11665 int Idx = PermMask[i];
11667 Locs[i] = std::make_pair(-1, -1);
11669 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11671 Locs[i] = std::make_pair(0, NumLo);
11672 Mask1[NumLo] = Idx;
11675 Locs[i] = std::make_pair(1, NumHi);
11677 Mask1[2+NumHi] = Idx;
11683 if (NumLo <= 2 && NumHi <= 2) {
11684 // If no more than two elements come from either vector. This can be
11685 // implemented with two shuffles. First shuffle gather the elements.
11686 // The second shuffle, which takes the first shuffle as both of its
11687 // vector operands, put the elements into the right order.
11688 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11690 int Mask2[] = { -1, -1, -1, -1 };
11692 for (unsigned i = 0; i != 4; ++i)
11693 if (Locs[i].first != -1) {
11694 unsigned Idx = (i < 2) ? 0 : 4;
11695 Idx += Locs[i].first * 2 + Locs[i].second;
11699 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11702 if (NumLo == 3 || NumHi == 3) {
11703 // Otherwise, we must have three elements from one vector, call it X, and
11704 // one element from the other, call it Y. First, use a shufps to build an
11705 // intermediate vector with the one element from Y and the element from X
11706 // that will be in the same half in the final destination (the indexes don't
11707 // matter). Then, use a shufps to build the final vector, taking the half
11708 // containing the element from Y from the intermediate, and the other half
11711 // Normalize it so the 3 elements come from V1.
11712 CommuteVectorShuffleMask(PermMask, 4);
11716 // Find the element from V2.
11718 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11719 int Val = PermMask[HiIndex];
11726 Mask1[0] = PermMask[HiIndex];
11728 Mask1[2] = PermMask[HiIndex^1];
11730 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11732 if (HiIndex >= 2) {
11733 Mask1[0] = PermMask[0];
11734 Mask1[1] = PermMask[1];
11735 Mask1[2] = HiIndex & 1 ? 6 : 4;
11736 Mask1[3] = HiIndex & 1 ? 4 : 6;
11737 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11740 Mask1[0] = HiIndex & 1 ? 2 : 0;
11741 Mask1[1] = HiIndex & 1 ? 0 : 2;
11742 Mask1[2] = PermMask[2];
11743 Mask1[3] = PermMask[3];
11748 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11751 // Break it into (shuffle shuffle_hi, shuffle_lo).
11752 int LoMask[] = { -1, -1, -1, -1 };
11753 int HiMask[] = { -1, -1, -1, -1 };
11755 int *MaskPtr = LoMask;
11756 unsigned MaskIdx = 0;
11757 unsigned LoIdx = 0;
11758 unsigned HiIdx = 2;
11759 for (unsigned i = 0; i != 4; ++i) {
11766 int Idx = PermMask[i];
11768 Locs[i] = std::make_pair(-1, -1);
11769 } else if (Idx < 4) {
11770 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11771 MaskPtr[LoIdx] = Idx;
11774 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11775 MaskPtr[HiIdx] = Idx;
11780 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11781 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11782 int MaskOps[] = { -1, -1, -1, -1 };
11783 for (unsigned i = 0; i != 4; ++i)
11784 if (Locs[i].first != -1)
11785 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11786 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11789 static bool MayFoldVectorLoad(SDValue V) {
11790 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11791 V = V.getOperand(0);
11793 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11794 V = V.getOperand(0);
11795 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11796 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11797 // BUILD_VECTOR (load), undef
11798 V = V.getOperand(0);
11800 return MayFoldLoad(V);
11804 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11805 MVT VT = Op.getSimpleValueType();
11807 // Canonizalize to v2f64.
11808 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11809 return DAG.getNode(ISD::BITCAST, dl, VT,
11810 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11815 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11817 SDValue V1 = Op.getOperand(0);
11818 SDValue V2 = Op.getOperand(1);
11819 MVT VT = Op.getSimpleValueType();
11821 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11823 if (HasSSE2 && VT == MVT::v2f64)
11824 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11826 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11827 return DAG.getNode(ISD::BITCAST, dl, VT,
11828 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11829 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11830 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11834 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11835 SDValue V1 = Op.getOperand(0);
11836 SDValue V2 = Op.getOperand(1);
11837 MVT VT = Op.getSimpleValueType();
11839 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11840 "unsupported shuffle type");
11842 if (V2.getOpcode() == ISD::UNDEF)
11846 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11850 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11851 SDValue V1 = Op.getOperand(0);
11852 SDValue V2 = Op.getOperand(1);
11853 MVT VT = Op.getSimpleValueType();
11854 unsigned NumElems = VT.getVectorNumElements();
11856 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11857 // operand of these instructions is only memory, so check if there's a
11858 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11860 bool CanFoldLoad = false;
11862 // Trivial case, when V2 comes from a load.
11863 if (MayFoldVectorLoad(V2))
11864 CanFoldLoad = true;
11866 // When V1 is a load, it can be folded later into a store in isel, example:
11867 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11869 // (MOVLPSmr addr:$src1, VR128:$src2)
11870 // So, recognize this potential and also use MOVLPS or MOVLPD
11871 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11872 CanFoldLoad = true;
11874 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11876 if (HasSSE2 && NumElems == 2)
11877 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11880 // If we don't care about the second element, proceed to use movss.
11881 if (SVOp->getMaskElt(1) != -1)
11882 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11885 // movl and movlp will both match v2i64, but v2i64 is never matched by
11886 // movl earlier because we make it strict to avoid messing with the movlp load
11887 // folding logic (see the code above getMOVLP call). Match it here then,
11888 // this is horrible, but will stay like this until we move all shuffle
11889 // matching to x86 specific nodes. Note that for the 1st condition all
11890 // types are matched with movsd.
11892 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11893 // as to remove this logic from here, as much as possible
11894 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11895 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11896 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11899 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11901 // Invert the operand order and use SHUFPS to match it.
11902 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11903 getShuffleSHUFImmediate(SVOp), DAG);
11906 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11907 SelectionDAG &DAG) {
11909 MVT VT = Load->getSimpleValueType(0);
11910 MVT EVT = VT.getVectorElementType();
11911 SDValue Addr = Load->getOperand(1);
11912 SDValue NewAddr = DAG.getNode(
11913 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11914 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11917 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11918 DAG.getMachineFunction().getMachineMemOperand(
11919 Load->getMemOperand(), 0, EVT.getStoreSize()));
11923 // It is only safe to call this function if isINSERTPSMask is true for
11924 // this shufflevector mask.
11925 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11926 SelectionDAG &DAG) {
11927 // Generate an insertps instruction when inserting an f32 from memory onto a
11928 // v4f32 or when copying a member from one v4f32 to another.
11929 // We also use it for transferring i32 from one register to another,
11930 // since it simply copies the same bits.
11931 // If we're transferring an i32 from memory to a specific element in a
11932 // register, we output a generic DAG that will match the PINSRD
11934 MVT VT = SVOp->getSimpleValueType(0);
11935 MVT EVT = VT.getVectorElementType();
11936 SDValue V1 = SVOp->getOperand(0);
11937 SDValue V2 = SVOp->getOperand(1);
11938 auto Mask = SVOp->getMask();
11939 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11940 "unsupported vector type for insertps/pinsrd");
11942 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11943 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11944 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11948 unsigned DestIndex;
11952 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11955 // If we have 1 element from each vector, we have to check if we're
11956 // changing V1's element's place. If so, we're done. Otherwise, we
11957 // should assume we're changing V2's element's place and behave
11959 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11960 assert(DestIndex <= INT32_MAX && "truncated destination index");
11961 if (FromV1 == FromV2 &&
11962 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11966 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11969 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11970 "More than one element from V1 and from V2, or no elements from one "
11971 "of the vectors. This case should not have returned true from "
11976 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11979 // Get an index into the source vector in the range [0,4) (the mask is
11980 // in the range [0,8) because it can address V1 and V2)
11981 unsigned SrcIndex = Mask[DestIndex] % 4;
11982 if (MayFoldLoad(From)) {
11983 // Trivial case, when From comes from a load and is only used by the
11984 // shuffle. Make it use insertps from the vector that we need from that
11987 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11988 if (!NewLoad.getNode())
11991 if (EVT == MVT::f32) {
11992 // Create this as a scalar to vector to match the instruction pattern.
11993 SDValue LoadScalarToVector =
11994 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11995 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11996 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11998 } else { // EVT == MVT::i32
11999 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12000 // instruction, to match the PINSRD instruction, which loads an i32 to a
12001 // certain vector element.
12002 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12003 DAG.getConstant(DestIndex, MVT::i32));
12007 // Vector-element-to-vector
12008 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12009 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12012 // Reduce a vector shuffle to zext.
12013 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12014 SelectionDAG &DAG) {
12015 // PMOVZX is only available from SSE41.
12016 if (!Subtarget->hasSSE41())
12019 MVT VT = Op.getSimpleValueType();
12021 // Only AVX2 support 256-bit vector integer extending.
12022 if (!Subtarget->hasInt256() && VT.is256BitVector())
12025 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12027 SDValue V1 = Op.getOperand(0);
12028 SDValue V2 = Op.getOperand(1);
12029 unsigned NumElems = VT.getVectorNumElements();
12031 // Extending is an unary operation and the element type of the source vector
12032 // won't be equal to or larger than i64.
12033 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12034 VT.getVectorElementType() == MVT::i64)
12037 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12038 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12039 while ((1U << Shift) < NumElems) {
12040 if (SVOp->getMaskElt(1U << Shift) == 1)
12043 // The maximal ratio is 8, i.e. from i8 to i64.
12048 // Check the shuffle mask.
12049 unsigned Mask = (1U << Shift) - 1;
12050 for (unsigned i = 0; i != NumElems; ++i) {
12051 int EltIdx = SVOp->getMaskElt(i);
12052 if ((i & Mask) != 0 && EltIdx != -1)
12054 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12058 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12059 MVT NeVT = MVT::getIntegerVT(NBits);
12060 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12062 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12065 return DAG.getNode(ISD::BITCAST, DL, VT,
12066 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12069 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12070 SelectionDAG &DAG) {
12071 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12072 MVT VT = Op.getSimpleValueType();
12074 SDValue V1 = Op.getOperand(0);
12075 SDValue V2 = Op.getOperand(1);
12077 if (isZeroShuffle(SVOp))
12078 return getZeroVector(VT, Subtarget, DAG, dl);
12080 // Handle splat operations
12081 if (SVOp->isSplat()) {
12082 // Use vbroadcast whenever the splat comes from a foldable load
12083 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12084 if (Broadcast.getNode())
12088 // Check integer expanding shuffles.
12089 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12090 if (NewOp.getNode())
12093 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12095 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12096 VT == MVT::v32i8) {
12097 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12098 if (NewOp.getNode())
12099 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12100 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12101 // FIXME: Figure out a cleaner way to do this.
12102 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12103 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12104 if (NewOp.getNode()) {
12105 MVT NewVT = NewOp.getSimpleValueType();
12106 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12107 NewVT, true, false))
12108 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12111 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12112 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12113 if (NewOp.getNode()) {
12114 MVT NewVT = NewOp.getSimpleValueType();
12115 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12116 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12125 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12126 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12127 SDValue V1 = Op.getOperand(0);
12128 SDValue V2 = Op.getOperand(1);
12129 MVT VT = Op.getSimpleValueType();
12131 unsigned NumElems = VT.getVectorNumElements();
12132 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12133 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12134 bool V1IsSplat = false;
12135 bool V2IsSplat = false;
12136 bool HasSSE2 = Subtarget->hasSSE2();
12137 bool HasFp256 = Subtarget->hasFp256();
12138 bool HasInt256 = Subtarget->hasInt256();
12139 MachineFunction &MF = DAG.getMachineFunction();
12140 bool OptForSize = MF.getFunction()->getAttributes().
12141 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12143 // Check if we should use the experimental vector shuffle lowering. If so,
12144 // delegate completely to that code path.
12145 if (ExperimentalVectorShuffleLowering)
12146 return lowerVectorShuffle(Op, Subtarget, DAG);
12148 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12150 if (V1IsUndef && V2IsUndef)
12151 return DAG.getUNDEF(VT);
12153 // When we create a shuffle node we put the UNDEF node to second operand,
12154 // but in some cases the first operand may be transformed to UNDEF.
12155 // In this case we should just commute the node.
12157 return DAG.getCommutedVectorShuffle(*SVOp);
12159 // Vector shuffle lowering takes 3 steps:
12161 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12162 // narrowing and commutation of operands should be handled.
12163 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12165 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12166 // so the shuffle can be broken into other shuffles and the legalizer can
12167 // try the lowering again.
12169 // The general idea is that no vector_shuffle operation should be left to
12170 // be matched during isel, all of them must be converted to a target specific
12173 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12174 // narrowing and commutation of operands should be handled. The actual code
12175 // doesn't include all of those, work in progress...
12176 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12177 if (NewOp.getNode())
12180 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12182 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12183 // unpckh_undef). Only use pshufd if speed is more important than size.
12184 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12185 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12186 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12187 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12189 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12190 V2IsUndef && MayFoldVectorLoad(V1))
12191 return getMOVDDup(Op, dl, V1, DAG);
12193 if (isMOVHLPS_v_undef_Mask(M, VT))
12194 return getMOVHighToLow(Op, dl, DAG);
12196 // Use to match splats
12197 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12198 (VT == MVT::v2f64 || VT == MVT::v2i64))
12199 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12201 if (isPSHUFDMask(M, VT)) {
12202 // The actual implementation will match the mask in the if above and then
12203 // during isel it can match several different instructions, not only pshufd
12204 // as its name says, sad but true, emulate the behavior for now...
12205 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12206 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12208 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12210 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12211 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12213 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12214 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12217 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12221 if (isPALIGNRMask(M, VT, Subtarget))
12222 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12223 getShufflePALIGNRImmediate(SVOp),
12226 if (isVALIGNMask(M, VT, Subtarget))
12227 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12228 getShuffleVALIGNImmediate(SVOp),
12231 // Check if this can be converted into a logical shift.
12232 bool isLeft = false;
12233 unsigned ShAmt = 0;
12235 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12236 if (isShift && ShVal.hasOneUse()) {
12237 // If the shifted value has multiple uses, it may be cheaper to use
12238 // v_set0 + movlhps or movhlps, etc.
12239 MVT EltVT = VT.getVectorElementType();
12240 ShAmt *= EltVT.getSizeInBits();
12241 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12244 if (isMOVLMask(M, VT)) {
12245 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12246 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12247 if (!isMOVLPMask(M, VT)) {
12248 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12249 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12251 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12252 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12256 // FIXME: fold these into legal mask.
12257 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12258 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12260 if (isMOVHLPSMask(M, VT))
12261 return getMOVHighToLow(Op, dl, DAG);
12263 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12264 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12266 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12267 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12269 if (isMOVLPMask(M, VT))
12270 return getMOVLP(Op, dl, DAG, HasSSE2);
12272 if (ShouldXformToMOVHLPS(M, VT) ||
12273 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12274 return DAG.getCommutedVectorShuffle(*SVOp);
12277 // No better options. Use a vshldq / vsrldq.
12278 MVT EltVT = VT.getVectorElementType();
12279 ShAmt *= EltVT.getSizeInBits();
12280 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12283 bool Commuted = false;
12284 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12285 // 1,1,1,1 -> v8i16 though.
12286 BitVector UndefElements;
12287 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12288 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12290 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12291 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12294 // Canonicalize the splat or undef, if present, to be on the RHS.
12295 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12296 CommuteVectorShuffleMask(M, NumElems);
12298 std::swap(V1IsSplat, V2IsSplat);
12302 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12303 // Shuffling low element of v1 into undef, just return v1.
12306 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12307 // the instruction selector will not match, so get a canonical MOVL with
12308 // swapped operands to undo the commute.
12309 return getMOVL(DAG, dl, VT, V2, V1);
12312 if (isUNPCKLMask(M, VT, HasInt256))
12313 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12315 if (isUNPCKHMask(M, VT, HasInt256))
12316 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12319 // Normalize mask so all entries that point to V2 points to its first
12320 // element then try to match unpck{h|l} again. If match, return a
12321 // new vector_shuffle with the corrected mask.p
12322 SmallVector<int, 8> NewMask(M.begin(), M.end());
12323 NormalizeMask(NewMask, NumElems);
12324 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12325 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12326 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12327 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12331 // Commute is back and try unpck* again.
12332 // FIXME: this seems wrong.
12333 CommuteVectorShuffleMask(M, NumElems);
12335 std::swap(V1IsSplat, V2IsSplat);
12337 if (isUNPCKLMask(M, VT, HasInt256))
12338 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12340 if (isUNPCKHMask(M, VT, HasInt256))
12341 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12344 // Normalize the node to match x86 shuffle ops if needed
12345 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12346 return DAG.getCommutedVectorShuffle(*SVOp);
12348 // The checks below are all present in isShuffleMaskLegal, but they are
12349 // inlined here right now to enable us to directly emit target specific
12350 // nodes, and remove one by one until they don't return Op anymore.
12352 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12353 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12354 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12355 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12358 if (isPSHUFHWMask(M, VT, HasInt256))
12359 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12360 getShufflePSHUFHWImmediate(SVOp),
12363 if (isPSHUFLWMask(M, VT, HasInt256))
12364 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12365 getShufflePSHUFLWImmediate(SVOp),
12368 unsigned MaskValue;
12369 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12371 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12373 if (isSHUFPMask(M, VT))
12374 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12375 getShuffleSHUFImmediate(SVOp), DAG);
12377 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12378 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12379 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12380 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12382 //===--------------------------------------------------------------------===//
12383 // Generate target specific nodes for 128 or 256-bit shuffles only
12384 // supported in the AVX instruction set.
12387 // Handle VMOVDDUPY permutations
12388 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12389 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12391 // Handle VPERMILPS/D* permutations
12392 if (isVPERMILPMask(M, VT)) {
12393 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12394 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12395 getShuffleSHUFImmediate(SVOp), DAG);
12396 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12397 getShuffleSHUFImmediate(SVOp), DAG);
12401 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12402 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12403 Idx*(NumElems/2), DAG, dl);
12405 // Handle VPERM2F128/VPERM2I128 permutations
12406 if (isVPERM2X128Mask(M, VT, HasFp256))
12407 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12408 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12410 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12411 return getINSERTPS(SVOp, dl, DAG);
12414 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12415 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12417 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12418 VT.is512BitVector()) {
12419 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12420 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12421 SmallVector<SDValue, 16> permclMask;
12422 for (unsigned i = 0; i != NumElems; ++i) {
12423 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12426 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12428 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12429 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12430 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12431 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12432 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12435 //===--------------------------------------------------------------------===//
12436 // Since no target specific shuffle was selected for this generic one,
12437 // lower it into other known shuffles. FIXME: this isn't true yet, but
12438 // this is the plan.
12441 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12442 if (VT == MVT::v8i16) {
12443 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12444 if (NewOp.getNode())
12448 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12449 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12450 if (NewOp.getNode())
12454 if (VT == MVT::v16i8) {
12455 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12456 if (NewOp.getNode())
12460 if (VT == MVT::v32i8) {
12461 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12462 if (NewOp.getNode())
12466 // Handle all 128-bit wide vectors with 4 elements, and match them with
12467 // several different shuffle types.
12468 if (NumElems == 4 && VT.is128BitVector())
12469 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12471 // Handle general 256-bit shuffles
12472 if (VT.is256BitVector())
12473 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12478 // This function assumes its argument is a BUILD_VECTOR of constants or
12479 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12481 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12482 unsigned &MaskValue) {
12484 unsigned NumElems = BuildVector->getNumOperands();
12485 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12486 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12487 unsigned NumElemsInLane = NumElems / NumLanes;
12489 // Blend for v16i16 should be symetric for the both lanes.
12490 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12491 SDValue EltCond = BuildVector->getOperand(i);
12492 SDValue SndLaneEltCond =
12493 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12495 int Lane1Cond = -1, Lane2Cond = -1;
12496 if (isa<ConstantSDNode>(EltCond))
12497 Lane1Cond = !isZero(EltCond);
12498 if (isa<ConstantSDNode>(SndLaneEltCond))
12499 Lane2Cond = !isZero(SndLaneEltCond);
12501 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12502 // Lane1Cond != 0, means we want the first argument.
12503 // Lane1Cond == 0, means we want the second argument.
12504 // The encoding of this argument is 0 for the first argument, 1
12505 // for the second. Therefore, invert the condition.
12506 MaskValue |= !Lane1Cond << i;
12507 else if (Lane1Cond < 0)
12508 MaskValue |= !Lane2Cond << i;
12515 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12517 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12518 SelectionDAG &DAG) {
12519 SDValue Cond = Op.getOperand(0);
12520 SDValue LHS = Op.getOperand(1);
12521 SDValue RHS = Op.getOperand(2);
12523 MVT VT = Op.getSimpleValueType();
12524 MVT EltVT = VT.getVectorElementType();
12525 unsigned NumElems = VT.getVectorNumElements();
12527 // There is no blend with immediate in AVX-512.
12528 if (VT.is512BitVector())
12531 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12533 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12536 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12539 // Check the mask for BLEND and build the value.
12540 unsigned MaskValue = 0;
12541 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12544 // Convert i32 vectors to floating point if it is not AVX2.
12545 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12547 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12548 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12550 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12551 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12554 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12555 DAG.getConstant(MaskValue, MVT::i32));
12556 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12559 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12560 // A vselect where all conditions and data are constants can be optimized into
12561 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12562 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12563 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12564 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12567 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12568 if (BlendOp.getNode())
12571 // Some types for vselect were previously set to Expand, not Legal or
12572 // Custom. Return an empty SDValue so we fall-through to Expand, after
12573 // the Custom lowering phase.
12574 MVT VT = Op.getSimpleValueType();
12575 switch (VT.SimpleTy) {
12580 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12585 // We couldn't create a "Blend with immediate" node.
12586 // This node should still be legal, but we'll have to emit a blendv*
12591 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12592 MVT VT = Op.getSimpleValueType();
12595 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12598 if (VT.getSizeInBits() == 8) {
12599 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12600 Op.getOperand(0), Op.getOperand(1));
12601 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12602 DAG.getValueType(VT));
12603 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12606 if (VT.getSizeInBits() == 16) {
12607 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12608 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12610 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12611 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12612 DAG.getNode(ISD::BITCAST, dl,
12615 Op.getOperand(1)));
12616 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12617 Op.getOperand(0), Op.getOperand(1));
12618 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12619 DAG.getValueType(VT));
12620 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12623 if (VT == MVT::f32) {
12624 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12625 // the result back to FR32 register. It's only worth matching if the
12626 // result has a single use which is a store or a bitcast to i32. And in
12627 // the case of a store, it's not worth it if the index is a constant 0,
12628 // because a MOVSSmr can be used instead, which is smaller and faster.
12629 if (!Op.hasOneUse())
12631 SDNode *User = *Op.getNode()->use_begin();
12632 if ((User->getOpcode() != ISD::STORE ||
12633 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12634 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12635 (User->getOpcode() != ISD::BITCAST ||
12636 User->getValueType(0) != MVT::i32))
12638 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12639 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12642 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12645 if (VT == MVT::i32 || VT == MVT::i64) {
12646 // ExtractPS/pextrq works with constant index.
12647 if (isa<ConstantSDNode>(Op.getOperand(1)))
12653 /// Extract one bit from mask vector, like v16i1 or v8i1.
12654 /// AVX-512 feature.
12656 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12657 SDValue Vec = Op.getOperand(0);
12659 MVT VecVT = Vec.getSimpleValueType();
12660 SDValue Idx = Op.getOperand(1);
12661 MVT EltVT = Op.getSimpleValueType();
12663 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12665 // variable index can't be handled in mask registers,
12666 // extend vector to VR512
12667 if (!isa<ConstantSDNode>(Idx)) {
12668 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12669 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12670 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12671 ExtVT.getVectorElementType(), Ext, Idx);
12672 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12675 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12676 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12677 unsigned MaxSift = rc->getSize()*8 - 1;
12678 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12679 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12680 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12681 DAG.getConstant(MaxSift, MVT::i8));
12682 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12683 DAG.getIntPtrConstant(0));
12687 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12688 SelectionDAG &DAG) const {
12690 SDValue Vec = Op.getOperand(0);
12691 MVT VecVT = Vec.getSimpleValueType();
12692 SDValue Idx = Op.getOperand(1);
12694 if (Op.getSimpleValueType() == MVT::i1)
12695 return ExtractBitFromMaskVector(Op, DAG);
12697 if (!isa<ConstantSDNode>(Idx)) {
12698 if (VecVT.is512BitVector() ||
12699 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12700 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12703 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12704 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12705 MaskEltVT.getSizeInBits());
12707 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12708 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12709 getZeroVector(MaskVT, Subtarget, DAG, dl),
12710 Idx, DAG.getConstant(0, getPointerTy()));
12711 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12712 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12713 Perm, DAG.getConstant(0, getPointerTy()));
12718 // If this is a 256-bit vector result, first extract the 128-bit vector and
12719 // then extract the element from the 128-bit vector.
12720 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12722 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12723 // Get the 128-bit vector.
12724 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12725 MVT EltVT = VecVT.getVectorElementType();
12727 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12729 //if (IdxVal >= NumElems/2)
12730 // IdxVal -= NumElems/2;
12731 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12732 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12733 DAG.getConstant(IdxVal, MVT::i32));
12736 assert(VecVT.is128BitVector() && "Unexpected vector length");
12738 if (Subtarget->hasSSE41()) {
12739 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12744 MVT VT = Op.getSimpleValueType();
12745 // TODO: handle v16i8.
12746 if (VT.getSizeInBits() == 16) {
12747 SDValue Vec = Op.getOperand(0);
12748 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12750 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12751 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12752 DAG.getNode(ISD::BITCAST, dl,
12754 Op.getOperand(1)));
12755 // Transform it so it match pextrw which produces a 32-bit result.
12756 MVT EltVT = MVT::i32;
12757 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12758 Op.getOperand(0), Op.getOperand(1));
12759 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12760 DAG.getValueType(VT));
12761 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12764 if (VT.getSizeInBits() == 32) {
12765 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12769 // SHUFPS the element to the lowest double word, then movss.
12770 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12771 MVT VVT = Op.getOperand(0).getSimpleValueType();
12772 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12773 DAG.getUNDEF(VVT), Mask);
12774 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12775 DAG.getIntPtrConstant(0));
12778 if (VT.getSizeInBits() == 64) {
12779 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12780 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12781 // to match extract_elt for f64.
12782 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12786 // UNPCKHPD the element to the lowest double word, then movsd.
12787 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12788 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12789 int Mask[2] = { 1, -1 };
12790 MVT VVT = Op.getOperand(0).getSimpleValueType();
12791 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12792 DAG.getUNDEF(VVT), Mask);
12793 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12794 DAG.getIntPtrConstant(0));
12800 /// Insert one bit to mask vector, like v16i1 or v8i1.
12801 /// AVX-512 feature.
12803 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12805 SDValue Vec = Op.getOperand(0);
12806 SDValue Elt = Op.getOperand(1);
12807 SDValue Idx = Op.getOperand(2);
12808 MVT VecVT = Vec.getSimpleValueType();
12810 if (!isa<ConstantSDNode>(Idx)) {
12811 // Non constant index. Extend source and destination,
12812 // insert element and then truncate the result.
12813 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12814 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12815 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12816 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12817 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12818 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12821 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12822 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12823 if (Vec.getOpcode() == ISD::UNDEF)
12824 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12825 DAG.getConstant(IdxVal, MVT::i8));
12826 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12827 unsigned MaxSift = rc->getSize()*8 - 1;
12828 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12829 DAG.getConstant(MaxSift, MVT::i8));
12830 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12831 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12832 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12835 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12836 SelectionDAG &DAG) const {
12837 MVT VT = Op.getSimpleValueType();
12838 MVT EltVT = VT.getVectorElementType();
12840 if (EltVT == MVT::i1)
12841 return InsertBitToMaskVector(Op, DAG);
12844 SDValue N0 = Op.getOperand(0);
12845 SDValue N1 = Op.getOperand(1);
12846 SDValue N2 = Op.getOperand(2);
12847 if (!isa<ConstantSDNode>(N2))
12849 auto *N2C = cast<ConstantSDNode>(N2);
12850 unsigned IdxVal = N2C->getZExtValue();
12852 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12853 // into that, and then insert the subvector back into the result.
12854 if (VT.is256BitVector() || VT.is512BitVector()) {
12855 // Get the desired 128-bit vector half.
12856 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12858 // Insert the element into the desired half.
12859 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12860 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12862 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12863 DAG.getConstant(IdxIn128, MVT::i32));
12865 // Insert the changed part back to the 256-bit vector
12866 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12868 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12870 if (Subtarget->hasSSE41()) {
12871 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12873 if (VT == MVT::v8i16) {
12874 Opc = X86ISD::PINSRW;
12876 assert(VT == MVT::v16i8);
12877 Opc = X86ISD::PINSRB;
12880 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12882 if (N1.getValueType() != MVT::i32)
12883 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12884 if (N2.getValueType() != MVT::i32)
12885 N2 = DAG.getIntPtrConstant(IdxVal);
12886 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12889 if (EltVT == MVT::f32) {
12890 // Bits [7:6] of the constant are the source select. This will always be
12891 // zero here. The DAG Combiner may combine an extract_elt index into
12893 // bits. For example (insert (extract, 3), 2) could be matched by
12895 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12896 // Bits [5:4] of the constant are the destination select. This is the
12897 // value of the incoming immediate.
12898 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12899 // combine either bitwise AND or insert of float 0.0 to set these bits.
12900 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12901 // Create this as a scalar to vector..
12902 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12903 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12906 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12907 // PINSR* works with constant index.
12912 if (EltVT == MVT::i8)
12915 if (EltVT.getSizeInBits() == 16) {
12916 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12917 // as its second argument.
12918 if (N1.getValueType() != MVT::i32)
12919 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12920 if (N2.getValueType() != MVT::i32)
12921 N2 = DAG.getIntPtrConstant(IdxVal);
12922 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12927 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12929 MVT OpVT = Op.getSimpleValueType();
12931 // If this is a 256-bit vector result, first insert into a 128-bit
12932 // vector and then insert into the 256-bit vector.
12933 if (!OpVT.is128BitVector()) {
12934 // Insert into a 128-bit vector.
12935 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12936 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12937 OpVT.getVectorNumElements() / SizeFactor);
12939 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12941 // Insert the 128-bit vector.
12942 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12945 if (OpVT == MVT::v1i64 &&
12946 Op.getOperand(0).getValueType() == MVT::i64)
12947 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12949 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12950 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12951 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12952 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12955 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12956 // a simple subregister reference or explicit instructions to grab
12957 // upper bits of a vector.
12958 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12959 SelectionDAG &DAG) {
12961 SDValue In = Op.getOperand(0);
12962 SDValue Idx = Op.getOperand(1);
12963 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12964 MVT ResVT = Op.getSimpleValueType();
12965 MVT InVT = In.getSimpleValueType();
12967 if (Subtarget->hasFp256()) {
12968 if (ResVT.is128BitVector() &&
12969 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12970 isa<ConstantSDNode>(Idx)) {
12971 return Extract128BitVector(In, IdxVal, DAG, dl);
12973 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12974 isa<ConstantSDNode>(Idx)) {
12975 return Extract256BitVector(In, IdxVal, DAG, dl);
12981 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12982 // simple superregister reference or explicit instructions to insert
12983 // the upper bits of a vector.
12984 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12985 SelectionDAG &DAG) {
12986 if (Subtarget->hasFp256()) {
12987 SDLoc dl(Op.getNode());
12988 SDValue Vec = Op.getNode()->getOperand(0);
12989 SDValue SubVec = Op.getNode()->getOperand(1);
12990 SDValue Idx = Op.getNode()->getOperand(2);
12992 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12993 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12994 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12995 isa<ConstantSDNode>(Idx)) {
12996 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12997 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13000 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13001 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13002 isa<ConstantSDNode>(Idx)) {
13003 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13004 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13010 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13011 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13012 // one of the above mentioned nodes. It has to be wrapped because otherwise
13013 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13014 // be used to form addressing mode. These wrapped nodes will be selected
13017 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13018 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13020 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13021 // global base reg.
13022 unsigned char OpFlag = 0;
13023 unsigned WrapperKind = X86ISD::Wrapper;
13024 CodeModel::Model M = DAG.getTarget().getCodeModel();
13026 if (Subtarget->isPICStyleRIPRel() &&
13027 (M == CodeModel::Small || M == CodeModel::Kernel))
13028 WrapperKind = X86ISD::WrapperRIP;
13029 else if (Subtarget->isPICStyleGOT())
13030 OpFlag = X86II::MO_GOTOFF;
13031 else if (Subtarget->isPICStyleStubPIC())
13032 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13034 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13035 CP->getAlignment(),
13036 CP->getOffset(), OpFlag);
13038 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13039 // With PIC, the address is actually $g + Offset.
13041 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13042 DAG.getNode(X86ISD::GlobalBaseReg,
13043 SDLoc(), getPointerTy()),
13050 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13051 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13053 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13054 // global base reg.
13055 unsigned char OpFlag = 0;
13056 unsigned WrapperKind = X86ISD::Wrapper;
13057 CodeModel::Model M = DAG.getTarget().getCodeModel();
13059 if (Subtarget->isPICStyleRIPRel() &&
13060 (M == CodeModel::Small || M == CodeModel::Kernel))
13061 WrapperKind = X86ISD::WrapperRIP;
13062 else if (Subtarget->isPICStyleGOT())
13063 OpFlag = X86II::MO_GOTOFF;
13064 else if (Subtarget->isPICStyleStubPIC())
13065 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13067 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13070 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13072 // With PIC, the address is actually $g + Offset.
13074 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13075 DAG.getNode(X86ISD::GlobalBaseReg,
13076 SDLoc(), getPointerTy()),
13083 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13084 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13086 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13087 // global base reg.
13088 unsigned char OpFlag = 0;
13089 unsigned WrapperKind = X86ISD::Wrapper;
13090 CodeModel::Model M = DAG.getTarget().getCodeModel();
13092 if (Subtarget->isPICStyleRIPRel() &&
13093 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13094 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13095 OpFlag = X86II::MO_GOTPCREL;
13096 WrapperKind = X86ISD::WrapperRIP;
13097 } else if (Subtarget->isPICStyleGOT()) {
13098 OpFlag = X86II::MO_GOT;
13099 } else if (Subtarget->isPICStyleStubPIC()) {
13100 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13101 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13102 OpFlag = X86II::MO_DARWIN_NONLAZY;
13105 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13108 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13110 // With PIC, the address is actually $g + Offset.
13111 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13112 !Subtarget->is64Bit()) {
13113 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13114 DAG.getNode(X86ISD::GlobalBaseReg,
13115 SDLoc(), getPointerTy()),
13119 // For symbols that require a load from a stub to get the address, emit the
13121 if (isGlobalStubReference(OpFlag))
13122 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13123 MachinePointerInfo::getGOT(), false, false, false, 0);
13129 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13130 // Create the TargetBlockAddressAddress node.
13131 unsigned char OpFlags =
13132 Subtarget->ClassifyBlockAddressReference();
13133 CodeModel::Model M = DAG.getTarget().getCodeModel();
13134 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13135 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13137 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13140 if (Subtarget->isPICStyleRIPRel() &&
13141 (M == CodeModel::Small || M == CodeModel::Kernel))
13142 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13144 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13146 // With PIC, the address is actually $g + Offset.
13147 if (isGlobalRelativeToPICBase(OpFlags)) {
13148 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13149 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13157 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13158 int64_t Offset, SelectionDAG &DAG) const {
13159 // Create the TargetGlobalAddress node, folding in the constant
13160 // offset if it is legal.
13161 unsigned char OpFlags =
13162 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13163 CodeModel::Model M = DAG.getTarget().getCodeModel();
13165 if (OpFlags == X86II::MO_NO_FLAG &&
13166 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13167 // A direct static reference to a global.
13168 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13171 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13174 if (Subtarget->isPICStyleRIPRel() &&
13175 (M == CodeModel::Small || M == CodeModel::Kernel))
13176 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13178 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13180 // With PIC, the address is actually $g + Offset.
13181 if (isGlobalRelativeToPICBase(OpFlags)) {
13182 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13183 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13187 // For globals that require a load from a stub to get the address, emit the
13189 if (isGlobalStubReference(OpFlags))
13190 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13191 MachinePointerInfo::getGOT(), false, false, false, 0);
13193 // If there was a non-zero offset that we didn't fold, create an explicit
13194 // addition for it.
13196 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13197 DAG.getConstant(Offset, getPointerTy()));
13203 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13204 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13205 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13206 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13210 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13211 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13212 unsigned char OperandFlags, bool LocalDynamic = false) {
13213 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13214 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13216 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13217 GA->getValueType(0),
13221 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13225 SDValue Ops[] = { Chain, TGA, *InFlag };
13226 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13228 SDValue Ops[] = { Chain, TGA };
13229 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13232 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13233 MFI->setAdjustsStack(true);
13234 MFI->setHasCalls(true);
13236 SDValue Flag = Chain.getValue(1);
13237 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13240 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13242 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13245 SDLoc dl(GA); // ? function entry point might be better
13246 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13247 DAG.getNode(X86ISD::GlobalBaseReg,
13248 SDLoc(), PtrVT), InFlag);
13249 InFlag = Chain.getValue(1);
13251 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13254 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13256 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13258 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13259 X86::RAX, X86II::MO_TLSGD);
13262 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13268 // Get the start address of the TLS block for this module.
13269 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13270 .getInfo<X86MachineFunctionInfo>();
13271 MFI->incNumLocalDynamicTLSAccesses();
13275 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13276 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13279 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13280 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13281 InFlag = Chain.getValue(1);
13282 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13283 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13286 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13290 unsigned char OperandFlags = X86II::MO_DTPOFF;
13291 unsigned WrapperKind = X86ISD::Wrapper;
13292 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13293 GA->getValueType(0),
13294 GA->getOffset(), OperandFlags);
13295 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13297 // Add x@dtpoff with the base.
13298 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13301 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13302 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13303 const EVT PtrVT, TLSModel::Model model,
13304 bool is64Bit, bool isPIC) {
13307 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13308 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13309 is64Bit ? 257 : 256));
13311 SDValue ThreadPointer =
13312 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13313 MachinePointerInfo(Ptr), false, false, false, 0);
13315 unsigned char OperandFlags = 0;
13316 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13318 unsigned WrapperKind = X86ISD::Wrapper;
13319 if (model == TLSModel::LocalExec) {
13320 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13321 } else if (model == TLSModel::InitialExec) {
13323 OperandFlags = X86II::MO_GOTTPOFF;
13324 WrapperKind = X86ISD::WrapperRIP;
13326 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13329 llvm_unreachable("Unexpected model");
13332 // emit "addl x@ntpoff,%eax" (local exec)
13333 // or "addl x@indntpoff,%eax" (initial exec)
13334 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13336 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13337 GA->getOffset(), OperandFlags);
13338 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13340 if (model == TLSModel::InitialExec) {
13341 if (isPIC && !is64Bit) {
13342 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13343 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13347 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13348 MachinePointerInfo::getGOT(), false, false, false, 0);
13351 // The address of the thread local variable is the add of the thread
13352 // pointer with the offset of the variable.
13353 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13357 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13359 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13360 const GlobalValue *GV = GA->getGlobal();
13362 if (Subtarget->isTargetELF()) {
13363 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13366 case TLSModel::GeneralDynamic:
13367 if (Subtarget->is64Bit())
13368 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13369 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13370 case TLSModel::LocalDynamic:
13371 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13372 Subtarget->is64Bit());
13373 case TLSModel::InitialExec:
13374 case TLSModel::LocalExec:
13375 return LowerToTLSExecModel(
13376 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13377 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13379 llvm_unreachable("Unknown TLS model.");
13382 if (Subtarget->isTargetDarwin()) {
13383 // Darwin only has one model of TLS. Lower to that.
13384 unsigned char OpFlag = 0;
13385 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13386 X86ISD::WrapperRIP : X86ISD::Wrapper;
13388 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13389 // global base reg.
13390 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13391 !Subtarget->is64Bit();
13393 OpFlag = X86II::MO_TLVP_PIC_BASE;
13395 OpFlag = X86II::MO_TLVP;
13397 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13398 GA->getValueType(0),
13399 GA->getOffset(), OpFlag);
13400 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13402 // With PIC32, the address is actually $g + Offset.
13404 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13405 DAG.getNode(X86ISD::GlobalBaseReg,
13406 SDLoc(), getPointerTy()),
13409 // Lowering the machine isd will make sure everything is in the right
13411 SDValue Chain = DAG.getEntryNode();
13412 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13413 SDValue Args[] = { Chain, Offset };
13414 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13416 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13417 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13418 MFI->setAdjustsStack(true);
13420 // And our return value (tls address) is in the standard call return value
13422 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13423 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13424 Chain.getValue(1));
13427 if (Subtarget->isTargetKnownWindowsMSVC() ||
13428 Subtarget->isTargetWindowsGNU()) {
13429 // Just use the implicit TLS architecture
13430 // Need to generate someting similar to:
13431 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13433 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13434 // mov rcx, qword [rdx+rcx*8]
13435 // mov eax, .tls$:tlsvar
13436 // [rax+rcx] contains the address
13437 // Windows 64bit: gs:0x58
13438 // Windows 32bit: fs:__tls_array
13441 SDValue Chain = DAG.getEntryNode();
13443 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13444 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13445 // use its literal value of 0x2C.
13446 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13447 ? Type::getInt8PtrTy(*DAG.getContext(),
13449 : Type::getInt32PtrTy(*DAG.getContext(),
13453 Subtarget->is64Bit()
13454 ? DAG.getIntPtrConstant(0x58)
13455 : (Subtarget->isTargetWindowsGNU()
13456 ? DAG.getIntPtrConstant(0x2C)
13457 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13459 SDValue ThreadPointer =
13460 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13461 MachinePointerInfo(Ptr), false, false, false, 0);
13463 // Load the _tls_index variable
13464 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13465 if (Subtarget->is64Bit())
13466 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13467 IDX, MachinePointerInfo(), MVT::i32,
13468 false, false, false, 0);
13470 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13471 false, false, false, 0);
13473 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13475 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13477 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13478 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13479 false, false, false, 0);
13481 // Get the offset of start of .tls section
13482 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13483 GA->getValueType(0),
13484 GA->getOffset(), X86II::MO_SECREL);
13485 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13487 // The address of the thread local variable is the add of the thread
13488 // pointer with the offset of the variable.
13489 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13492 llvm_unreachable("TLS not implemented for this target.");
13495 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13496 /// and take a 2 x i32 value to shift plus a shift amount.
13497 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13498 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13499 MVT VT = Op.getSimpleValueType();
13500 unsigned VTBits = VT.getSizeInBits();
13502 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13503 SDValue ShOpLo = Op.getOperand(0);
13504 SDValue ShOpHi = Op.getOperand(1);
13505 SDValue ShAmt = Op.getOperand(2);
13506 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13507 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13509 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13510 DAG.getConstant(VTBits - 1, MVT::i8));
13511 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13512 DAG.getConstant(VTBits - 1, MVT::i8))
13513 : DAG.getConstant(0, VT);
13515 SDValue Tmp2, Tmp3;
13516 if (Op.getOpcode() == ISD::SHL_PARTS) {
13517 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13518 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13520 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13521 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13524 // If the shift amount is larger or equal than the width of a part we can't
13525 // rely on the results of shld/shrd. Insert a test and select the appropriate
13526 // values for large shift amounts.
13527 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13528 DAG.getConstant(VTBits, MVT::i8));
13529 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13530 AndNode, DAG.getConstant(0, MVT::i8));
13533 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13534 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13535 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13537 if (Op.getOpcode() == ISD::SHL_PARTS) {
13538 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13539 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13541 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13542 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13545 SDValue Ops[2] = { Lo, Hi };
13546 return DAG.getMergeValues(Ops, dl);
13549 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13550 SelectionDAG &DAG) const {
13551 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13554 if (SrcVT.isVector()) {
13555 if (SrcVT.getVectorElementType() == MVT::i1) {
13556 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13557 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13558 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13559 Op.getOperand(0)));
13564 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13565 "Unknown SINT_TO_FP to lower!");
13567 // These are really Legal; return the operand so the caller accepts it as
13569 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13571 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13572 Subtarget->is64Bit()) {
13576 unsigned Size = SrcVT.getSizeInBits()/8;
13577 MachineFunction &MF = DAG.getMachineFunction();
13578 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13579 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13580 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13582 MachinePointerInfo::getFixedStack(SSFI),
13584 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13587 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13589 SelectionDAG &DAG) const {
13593 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13595 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13597 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13599 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13601 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13602 MachineMemOperand *MMO;
13604 int SSFI = FI->getIndex();
13606 DAG.getMachineFunction()
13607 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13608 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13610 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13611 StackSlot = StackSlot.getOperand(1);
13613 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13614 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13616 Tys, Ops, SrcVT, MMO);
13619 Chain = Result.getValue(1);
13620 SDValue InFlag = Result.getValue(2);
13622 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13623 // shouldn't be necessary except that RFP cannot be live across
13624 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13625 MachineFunction &MF = DAG.getMachineFunction();
13626 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13627 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13628 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13629 Tys = DAG.getVTList(MVT::Other);
13631 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13633 MachineMemOperand *MMO =
13634 DAG.getMachineFunction()
13635 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13636 MachineMemOperand::MOStore, SSFISize, SSFISize);
13638 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13639 Ops, Op.getValueType(), MMO);
13640 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13641 MachinePointerInfo::getFixedStack(SSFI),
13642 false, false, false, 0);
13648 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13649 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13650 SelectionDAG &DAG) const {
13651 // This algorithm is not obvious. Here it is what we're trying to output:
13654 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13655 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13657 haddpd %xmm0, %xmm0
13659 pshufd $0x4e, %xmm0, %xmm1
13665 LLVMContext *Context = DAG.getContext();
13667 // Build some magic constants.
13668 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13669 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13670 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13672 SmallVector<Constant*,2> CV1;
13674 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13675 APInt(64, 0x4330000000000000ULL))));
13677 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13678 APInt(64, 0x4530000000000000ULL))));
13679 Constant *C1 = ConstantVector::get(CV1);
13680 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13682 // Load the 64-bit value into an XMM register.
13683 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13685 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13686 MachinePointerInfo::getConstantPool(),
13687 false, false, false, 16);
13688 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13689 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13692 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13693 MachinePointerInfo::getConstantPool(),
13694 false, false, false, 16);
13695 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13696 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13699 if (Subtarget->hasSSE3()) {
13700 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13701 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13703 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13704 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13706 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13707 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13711 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13712 DAG.getIntPtrConstant(0));
13715 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13716 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13717 SelectionDAG &DAG) const {
13719 // FP constant to bias correct the final result.
13720 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13723 // Load the 32-bit value into an XMM register.
13724 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13727 // Zero out the upper parts of the register.
13728 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13730 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13731 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13732 DAG.getIntPtrConstant(0));
13734 // Or the load with the bias.
13735 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13736 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13737 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13738 MVT::v2f64, Load)),
13739 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13740 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13741 MVT::v2f64, Bias)));
13742 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13743 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13744 DAG.getIntPtrConstant(0));
13746 // Subtract the bias.
13747 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13749 // Handle final rounding.
13750 EVT DestVT = Op.getValueType();
13752 if (DestVT.bitsLT(MVT::f64))
13753 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13754 DAG.getIntPtrConstant(0));
13755 if (DestVT.bitsGT(MVT::f64))
13756 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13758 // Handle final rounding.
13762 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13763 const X86Subtarget &Subtarget) {
13764 // The algorithm is the following:
13765 // #ifdef __SSE4_1__
13766 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13767 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13768 // (uint4) 0x53000000, 0xaa);
13770 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13771 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13773 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13774 // return (float4) lo + fhi;
13777 SDValue V = Op->getOperand(0);
13778 EVT VecIntVT = V.getValueType();
13779 bool Is128 = VecIntVT == MVT::v4i32;
13780 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13781 // If we convert to something else than the supported type, e.g., to v4f64,
13783 if (VecFloatVT != Op->getValueType(0))
13786 unsigned NumElts = VecIntVT.getVectorNumElements();
13787 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13788 "Unsupported custom type");
13789 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13791 // In the #idef/#else code, we have in common:
13792 // - The vector of constants:
13798 // Create the splat vector for 0x4b000000.
13799 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13800 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13801 CstLow, CstLow, CstLow, CstLow};
13802 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13803 makeArrayRef(&CstLowArray[0], NumElts));
13804 // Create the splat vector for 0x53000000.
13805 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13806 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13807 CstHigh, CstHigh, CstHigh, CstHigh};
13808 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13809 makeArrayRef(&CstHighArray[0], NumElts));
13811 // Create the right shift.
13812 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13813 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13814 CstShift, CstShift, CstShift, CstShift};
13815 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13816 makeArrayRef(&CstShiftArray[0], NumElts));
13817 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13820 if (Subtarget.hasSSE41()) {
13821 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13822 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13823 SDValue VecCstLowBitcast =
13824 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13825 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13826 // Low will be bitcasted right away, so do not bother bitcasting back to its
13828 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13829 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13830 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13831 // (uint4) 0x53000000, 0xaa);
13832 SDValue VecCstHighBitcast =
13833 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13834 SDValue VecShiftBitcast =
13835 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13836 // High will be bitcasted right away, so do not bother bitcasting back to
13837 // its original type.
13838 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13839 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13841 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13842 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13843 CstMask, CstMask, CstMask);
13844 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13845 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13846 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13848 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13849 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13852 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13853 SDValue CstFAdd = DAG.getConstantFP(
13854 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13855 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13856 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13857 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13858 makeArrayRef(&CstFAddArray[0], NumElts));
13860 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13861 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13863 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13864 // return (float4) lo + fhi;
13865 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13866 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13869 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13870 SelectionDAG &DAG) const {
13871 SDValue N0 = Op.getOperand(0);
13872 MVT SVT = N0.getSimpleValueType();
13875 switch (SVT.SimpleTy) {
13877 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13882 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13883 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13884 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13888 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13890 llvm_unreachable(nullptr);
13893 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13894 SelectionDAG &DAG) const {
13895 SDValue N0 = Op.getOperand(0);
13898 if (Op.getValueType().isVector())
13899 return lowerUINT_TO_FP_vec(Op, DAG);
13901 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13902 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13903 // the optimization here.
13904 if (DAG.SignBitIsZero(N0))
13905 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13907 MVT SrcVT = N0.getSimpleValueType();
13908 MVT DstVT = Op.getSimpleValueType();
13909 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13910 return LowerUINT_TO_FP_i64(Op, DAG);
13911 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13912 return LowerUINT_TO_FP_i32(Op, DAG);
13913 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13916 // Make a 64-bit buffer, and use it to build an FILD.
13917 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13918 if (SrcVT == MVT::i32) {
13919 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13920 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13921 getPointerTy(), StackSlot, WordOff);
13922 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13923 StackSlot, MachinePointerInfo(),
13925 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13926 OffsetSlot, MachinePointerInfo(),
13928 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13932 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13933 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13934 StackSlot, MachinePointerInfo(),
13936 // For i64 source, we need to add the appropriate power of 2 if the input
13937 // was negative. This is the same as the optimization in
13938 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13939 // we must be careful to do the computation in x87 extended precision, not
13940 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13941 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13942 MachineMemOperand *MMO =
13943 DAG.getMachineFunction()
13944 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13945 MachineMemOperand::MOLoad, 8, 8);
13947 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13948 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13949 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13952 APInt FF(32, 0x5F800000ULL);
13954 // Check whether the sign bit is set.
13955 SDValue SignSet = DAG.getSetCC(dl,
13956 getSetCCResultType(*DAG.getContext(), MVT::i64),
13957 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13960 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13961 SDValue FudgePtr = DAG.getConstantPool(
13962 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13965 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13966 SDValue Zero = DAG.getIntPtrConstant(0);
13967 SDValue Four = DAG.getIntPtrConstant(4);
13968 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13970 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13972 // Load the value out, extending it from f32 to f80.
13973 // FIXME: Avoid the extend by constructing the right constant pool?
13974 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13975 FudgePtr, MachinePointerInfo::getConstantPool(),
13976 MVT::f32, false, false, false, 4);
13977 // Extend everything to 80 bits to force it to be done on x87.
13978 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13979 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13982 std::pair<SDValue,SDValue>
13983 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13984 bool IsSigned, bool IsReplace) const {
13987 EVT DstTy = Op.getValueType();
13989 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13990 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13994 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13995 DstTy.getSimpleVT() >= MVT::i16 &&
13996 "Unknown FP_TO_INT to lower!");
13998 // These are really Legal.
13999 if (DstTy == MVT::i32 &&
14000 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14001 return std::make_pair(SDValue(), SDValue());
14002 if (Subtarget->is64Bit() &&
14003 DstTy == MVT::i64 &&
14004 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14005 return std::make_pair(SDValue(), SDValue());
14007 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14008 // stack slot, or into the FTOL runtime function.
14009 MachineFunction &MF = DAG.getMachineFunction();
14010 unsigned MemSize = DstTy.getSizeInBits()/8;
14011 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14012 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14015 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14016 Opc = X86ISD::WIN_FTOL;
14018 switch (DstTy.getSimpleVT().SimpleTy) {
14019 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14020 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14021 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14022 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14025 SDValue Chain = DAG.getEntryNode();
14026 SDValue Value = Op.getOperand(0);
14027 EVT TheVT = Op.getOperand(0).getValueType();
14028 // FIXME This causes a redundant load/store if the SSE-class value is already
14029 // in memory, such as if it is on the callstack.
14030 if (isScalarFPTypeInSSEReg(TheVT)) {
14031 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14032 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14033 MachinePointerInfo::getFixedStack(SSFI),
14035 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14037 Chain, StackSlot, DAG.getValueType(TheVT)
14040 MachineMemOperand *MMO =
14041 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14042 MachineMemOperand::MOLoad, MemSize, MemSize);
14043 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14044 Chain = Value.getValue(1);
14045 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14046 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14049 MachineMemOperand *MMO =
14050 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14051 MachineMemOperand::MOStore, MemSize, MemSize);
14053 if (Opc != X86ISD::WIN_FTOL) {
14054 // Build the FP_TO_INT*_IN_MEM
14055 SDValue Ops[] = { Chain, Value, StackSlot };
14056 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14058 return std::make_pair(FIST, StackSlot);
14060 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14061 DAG.getVTList(MVT::Other, MVT::Glue),
14063 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14064 MVT::i32, ftol.getValue(1));
14065 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14066 MVT::i32, eax.getValue(2));
14067 SDValue Ops[] = { eax, edx };
14068 SDValue pair = IsReplace
14069 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14070 : DAG.getMergeValues(Ops, DL);
14071 return std::make_pair(pair, SDValue());
14075 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14076 const X86Subtarget *Subtarget) {
14077 MVT VT = Op->getSimpleValueType(0);
14078 SDValue In = Op->getOperand(0);
14079 MVT InVT = In.getSimpleValueType();
14082 // Optimize vectors in AVX mode:
14085 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14086 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14087 // Concat upper and lower parts.
14090 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14091 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14092 // Concat upper and lower parts.
14095 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14096 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14097 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14100 if (Subtarget->hasInt256())
14101 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14103 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14104 SDValue Undef = DAG.getUNDEF(InVT);
14105 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14106 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14107 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14109 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14110 VT.getVectorNumElements()/2);
14112 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14113 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14115 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14118 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14119 SelectionDAG &DAG) {
14120 MVT VT = Op->getSimpleValueType(0);
14121 SDValue In = Op->getOperand(0);
14122 MVT InVT = In.getSimpleValueType();
14124 unsigned int NumElts = VT.getVectorNumElements();
14125 if (NumElts != 8 && NumElts != 16)
14128 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14129 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14131 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14132 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14133 // Now we have only mask extension
14134 assert(InVT.getVectorElementType() == MVT::i1);
14135 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14136 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14137 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14138 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14139 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14140 MachinePointerInfo::getConstantPool(),
14141 false, false, false, Alignment);
14143 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14144 if (VT.is512BitVector())
14146 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14149 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14150 SelectionDAG &DAG) {
14151 if (Subtarget->hasFp256()) {
14152 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14160 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14161 SelectionDAG &DAG) {
14163 MVT VT = Op.getSimpleValueType();
14164 SDValue In = Op.getOperand(0);
14165 MVT SVT = In.getSimpleValueType();
14167 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14168 return LowerZERO_EXTEND_AVX512(Op, DAG);
14170 if (Subtarget->hasFp256()) {
14171 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14176 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14177 VT.getVectorNumElements() != SVT.getVectorNumElements());
14181 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14183 MVT VT = Op.getSimpleValueType();
14184 SDValue In = Op.getOperand(0);
14185 MVT InVT = In.getSimpleValueType();
14187 if (VT == MVT::i1) {
14188 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14189 "Invalid scalar TRUNCATE operation");
14190 if (InVT.getSizeInBits() >= 32)
14192 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14193 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14195 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14196 "Invalid TRUNCATE operation");
14198 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14199 if (VT.getVectorElementType().getSizeInBits() >=8)
14200 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14202 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14203 unsigned NumElts = InVT.getVectorNumElements();
14204 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14205 if (InVT.getSizeInBits() < 512) {
14206 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14207 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14211 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14212 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14213 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14214 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14215 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14216 MachinePointerInfo::getConstantPool(),
14217 false, false, false, Alignment);
14218 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14219 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14220 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14223 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14224 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14225 if (Subtarget->hasInt256()) {
14226 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14227 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14228 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14230 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14231 DAG.getIntPtrConstant(0));
14234 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14235 DAG.getIntPtrConstant(0));
14236 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14237 DAG.getIntPtrConstant(2));
14238 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14239 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14240 static const int ShufMask[] = {0, 2, 4, 6};
14241 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14244 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14245 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14246 if (Subtarget->hasInt256()) {
14247 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14249 SmallVector<SDValue,32> pshufbMask;
14250 for (unsigned i = 0; i < 2; ++i) {
14251 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14252 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14253 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14254 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14255 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14256 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14257 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14258 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14259 for (unsigned j = 0; j < 8; ++j)
14260 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14262 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14263 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14264 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14266 static const int ShufMask[] = {0, 2, -1, -1};
14267 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14269 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14270 DAG.getIntPtrConstant(0));
14271 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14274 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14275 DAG.getIntPtrConstant(0));
14277 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14278 DAG.getIntPtrConstant(4));
14280 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14281 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14283 // The PSHUFB mask:
14284 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14285 -1, -1, -1, -1, -1, -1, -1, -1};
14287 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14288 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14289 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14291 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14292 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14294 // The MOVLHPS Mask:
14295 static const int ShufMask2[] = {0, 1, 4, 5};
14296 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14297 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14300 // Handle truncation of V256 to V128 using shuffles.
14301 if (!VT.is128BitVector() || !InVT.is256BitVector())
14304 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14306 unsigned NumElems = VT.getVectorNumElements();
14307 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14309 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14310 // Prepare truncation shuffle mask
14311 for (unsigned i = 0; i != NumElems; ++i)
14312 MaskVec[i] = i * 2;
14313 SDValue V = DAG.getVectorShuffle(NVT, DL,
14314 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14315 DAG.getUNDEF(NVT), &MaskVec[0]);
14316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14317 DAG.getIntPtrConstant(0));
14320 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14321 SelectionDAG &DAG) const {
14322 assert(!Op.getSimpleValueType().isVector());
14324 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14325 /*IsSigned=*/ true, /*IsReplace=*/ false);
14326 SDValue FIST = Vals.first, StackSlot = Vals.second;
14327 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14328 if (!FIST.getNode()) return Op;
14330 if (StackSlot.getNode())
14331 // Load the result.
14332 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14333 FIST, StackSlot, MachinePointerInfo(),
14334 false, false, false, 0);
14336 // The node is the result.
14340 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14341 SelectionDAG &DAG) const {
14342 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14343 /*IsSigned=*/ false, /*IsReplace=*/ false);
14344 SDValue FIST = Vals.first, StackSlot = Vals.second;
14345 assert(FIST.getNode() && "Unexpected failure");
14347 if (StackSlot.getNode())
14348 // Load the result.
14349 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14350 FIST, StackSlot, MachinePointerInfo(),
14351 false, false, false, 0);
14353 // The node is the result.
14357 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14359 MVT VT = Op.getSimpleValueType();
14360 SDValue In = Op.getOperand(0);
14361 MVT SVT = In.getSimpleValueType();
14363 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14365 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14366 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14367 In, DAG.getUNDEF(SVT)));
14370 /// The only differences between FABS and FNEG are the mask and the logic op.
14371 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14372 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14373 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14374 "Wrong opcode for lowering FABS or FNEG.");
14376 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14378 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14379 // into an FNABS. We'll lower the FABS after that if it is still in use.
14381 for (SDNode *User : Op->uses())
14382 if (User->getOpcode() == ISD::FNEG)
14385 SDValue Op0 = Op.getOperand(0);
14386 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14389 MVT VT = Op.getSimpleValueType();
14390 // Assume scalar op for initialization; update for vector if needed.
14391 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14392 // generate a 16-byte vector constant and logic op even for the scalar case.
14393 // Using a 16-byte mask allows folding the load of the mask with
14394 // the logic op, so it can save (~4 bytes) on code size.
14396 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14397 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14398 // decide if we should generate a 16-byte constant mask when we only need 4 or
14399 // 8 bytes for the scalar case.
14400 if (VT.isVector()) {
14401 EltVT = VT.getVectorElementType();
14402 NumElts = VT.getVectorNumElements();
14405 unsigned EltBits = EltVT.getSizeInBits();
14406 LLVMContext *Context = DAG.getContext();
14407 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14409 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14410 Constant *C = ConstantInt::get(*Context, MaskElt);
14411 C = ConstantVector::getSplat(NumElts, C);
14412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14413 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14414 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14415 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14416 MachinePointerInfo::getConstantPool(),
14417 false, false, false, Alignment);
14419 if (VT.isVector()) {
14420 // For a vector, cast operands to a vector type, perform the logic op,
14421 // and cast the result back to the original value type.
14422 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14423 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14424 SDValue Operand = IsFNABS ?
14425 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14426 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14427 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14428 return DAG.getNode(ISD::BITCAST, dl, VT,
14429 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14432 // If not vector, then scalar.
14433 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14434 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14435 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14438 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14439 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14440 LLVMContext *Context = DAG.getContext();
14441 SDValue Op0 = Op.getOperand(0);
14442 SDValue Op1 = Op.getOperand(1);
14444 MVT VT = Op.getSimpleValueType();
14445 MVT SrcVT = Op1.getSimpleValueType();
14447 // If second operand is smaller, extend it first.
14448 if (SrcVT.bitsLT(VT)) {
14449 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14452 // And if it is bigger, shrink it first.
14453 if (SrcVT.bitsGT(VT)) {
14454 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14458 // At this point the operands and the result should have the same
14459 // type, and that won't be f80 since that is not custom lowered.
14461 // First get the sign bit of second operand.
14462 SmallVector<Constant*,4> CV;
14463 if (SrcVT == MVT::f64) {
14464 const fltSemantics &Sem = APFloat::IEEEdouble;
14465 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14466 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14468 const fltSemantics &Sem = APFloat::IEEEsingle;
14469 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14470 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14471 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14472 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14474 Constant *C = ConstantVector::get(CV);
14475 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14476 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14477 MachinePointerInfo::getConstantPool(),
14478 false, false, false, 16);
14479 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14481 // Shift sign bit right or left if the two operands have different types.
14482 if (SrcVT.bitsGT(VT)) {
14483 // Op0 is MVT::f32, Op1 is MVT::f64.
14484 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14485 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14486 DAG.getConstant(32, MVT::i32));
14487 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14488 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14489 DAG.getIntPtrConstant(0));
14492 // Clear first operand sign bit.
14494 if (VT == MVT::f64) {
14495 const fltSemantics &Sem = APFloat::IEEEdouble;
14496 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14497 APInt(64, ~(1ULL << 63)))));
14498 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14500 const fltSemantics &Sem = APFloat::IEEEsingle;
14501 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14502 APInt(32, ~(1U << 31)))));
14503 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14504 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14505 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14507 C = ConstantVector::get(CV);
14508 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14509 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14510 MachinePointerInfo::getConstantPool(),
14511 false, false, false, 16);
14512 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14514 // Or the value with the sign bit.
14515 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14518 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14519 SDValue N0 = Op.getOperand(0);
14521 MVT VT = Op.getSimpleValueType();
14523 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14524 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14525 DAG.getConstant(1, VT));
14526 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14529 // Check whether an OR'd tree is PTEST-able.
14530 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14531 SelectionDAG &DAG) {
14532 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14534 if (!Subtarget->hasSSE41())
14537 if (!Op->hasOneUse())
14540 SDNode *N = Op.getNode();
14543 SmallVector<SDValue, 8> Opnds;
14544 DenseMap<SDValue, unsigned> VecInMap;
14545 SmallVector<SDValue, 8> VecIns;
14546 EVT VT = MVT::Other;
14548 // Recognize a special case where a vector is casted into wide integer to
14550 Opnds.push_back(N->getOperand(0));
14551 Opnds.push_back(N->getOperand(1));
14553 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14554 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14555 // BFS traverse all OR'd operands.
14556 if (I->getOpcode() == ISD::OR) {
14557 Opnds.push_back(I->getOperand(0));
14558 Opnds.push_back(I->getOperand(1));
14559 // Re-evaluate the number of nodes to be traversed.
14560 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14564 // Quit if a non-EXTRACT_VECTOR_ELT
14565 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14568 // Quit if without a constant index.
14569 SDValue Idx = I->getOperand(1);
14570 if (!isa<ConstantSDNode>(Idx))
14573 SDValue ExtractedFromVec = I->getOperand(0);
14574 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14575 if (M == VecInMap.end()) {
14576 VT = ExtractedFromVec.getValueType();
14577 // Quit if not 128/256-bit vector.
14578 if (!VT.is128BitVector() && !VT.is256BitVector())
14580 // Quit if not the same type.
14581 if (VecInMap.begin() != VecInMap.end() &&
14582 VT != VecInMap.begin()->first.getValueType())
14584 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14585 VecIns.push_back(ExtractedFromVec);
14587 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14590 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14591 "Not extracted from 128-/256-bit vector.");
14593 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14595 for (DenseMap<SDValue, unsigned>::const_iterator
14596 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14597 // Quit if not all elements are used.
14598 if (I->second != FullMask)
14602 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14604 // Cast all vectors into TestVT for PTEST.
14605 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14606 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14608 // If more than one full vectors are evaluated, OR them first before PTEST.
14609 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14610 // Each iteration will OR 2 nodes and append the result until there is only
14611 // 1 node left, i.e. the final OR'd value of all vectors.
14612 SDValue LHS = VecIns[Slot];
14613 SDValue RHS = VecIns[Slot + 1];
14614 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14617 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14618 VecIns.back(), VecIns.back());
14621 /// \brief return true if \c Op has a use that doesn't just read flags.
14622 static bool hasNonFlagsUse(SDValue Op) {
14623 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14625 SDNode *User = *UI;
14626 unsigned UOpNo = UI.getOperandNo();
14627 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14628 // Look pass truncate.
14629 UOpNo = User->use_begin().getOperandNo();
14630 User = *User->use_begin();
14633 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14634 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14640 /// Emit nodes that will be selected as "test Op0,Op0", or something
14642 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14643 SelectionDAG &DAG) const {
14644 if (Op.getValueType() == MVT::i1)
14645 // KORTEST instruction should be selected
14646 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14647 DAG.getConstant(0, Op.getValueType()));
14649 // CF and OF aren't always set the way we want. Determine which
14650 // of these we need.
14651 bool NeedCF = false;
14652 bool NeedOF = false;
14655 case X86::COND_A: case X86::COND_AE:
14656 case X86::COND_B: case X86::COND_BE:
14659 case X86::COND_G: case X86::COND_GE:
14660 case X86::COND_L: case X86::COND_LE:
14661 case X86::COND_O: case X86::COND_NO: {
14662 // Check if we really need to set the
14663 // Overflow flag. If NoSignedWrap is present
14664 // that is not actually needed.
14665 switch (Op->getOpcode()) {
14670 const BinaryWithFlagsSDNode *BinNode =
14671 cast<BinaryWithFlagsSDNode>(Op.getNode());
14672 if (BinNode->hasNoSignedWrap())
14682 // See if we can use the EFLAGS value from the operand instead of
14683 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14684 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14685 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14686 // Emit a CMP with 0, which is the TEST pattern.
14687 //if (Op.getValueType() == MVT::i1)
14688 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14689 // DAG.getConstant(0, MVT::i1));
14690 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14691 DAG.getConstant(0, Op.getValueType()));
14693 unsigned Opcode = 0;
14694 unsigned NumOperands = 0;
14696 // Truncate operations may prevent the merge of the SETCC instruction
14697 // and the arithmetic instruction before it. Attempt to truncate the operands
14698 // of the arithmetic instruction and use a reduced bit-width instruction.
14699 bool NeedTruncation = false;
14700 SDValue ArithOp = Op;
14701 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14702 SDValue Arith = Op->getOperand(0);
14703 // Both the trunc and the arithmetic op need to have one user each.
14704 if (Arith->hasOneUse())
14705 switch (Arith.getOpcode()) {
14712 NeedTruncation = true;
14718 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14719 // which may be the result of a CAST. We use the variable 'Op', which is the
14720 // non-casted variable when we check for possible users.
14721 switch (ArithOp.getOpcode()) {
14723 // Due to an isel shortcoming, be conservative if this add is likely to be
14724 // selected as part of a load-modify-store instruction. When the root node
14725 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14726 // uses of other nodes in the match, such as the ADD in this case. This
14727 // leads to the ADD being left around and reselected, with the result being
14728 // two adds in the output. Alas, even if none our users are stores, that
14729 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14730 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14731 // climbing the DAG back to the root, and it doesn't seem to be worth the
14733 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14734 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14735 if (UI->getOpcode() != ISD::CopyToReg &&
14736 UI->getOpcode() != ISD::SETCC &&
14737 UI->getOpcode() != ISD::STORE)
14740 if (ConstantSDNode *C =
14741 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14742 // An add of one will be selected as an INC.
14743 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14744 Opcode = X86ISD::INC;
14749 // An add of negative one (subtract of one) will be selected as a DEC.
14750 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14751 Opcode = X86ISD::DEC;
14757 // Otherwise use a regular EFLAGS-setting add.
14758 Opcode = X86ISD::ADD;
14763 // If we have a constant logical shift that's only used in a comparison
14764 // against zero turn it into an equivalent AND. This allows turning it into
14765 // a TEST instruction later.
14766 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14767 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14768 EVT VT = Op.getValueType();
14769 unsigned BitWidth = VT.getSizeInBits();
14770 unsigned ShAmt = Op->getConstantOperandVal(1);
14771 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14773 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14774 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14775 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14776 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14778 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14779 DAG.getConstant(Mask, VT));
14780 DAG.ReplaceAllUsesWith(Op, New);
14786 // If the primary and result isn't used, don't bother using X86ISD::AND,
14787 // because a TEST instruction will be better.
14788 if (!hasNonFlagsUse(Op))
14794 // Due to the ISEL shortcoming noted above, be conservative if this op is
14795 // likely to be selected as part of a load-modify-store instruction.
14796 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14797 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14798 if (UI->getOpcode() == ISD::STORE)
14801 // Otherwise use a regular EFLAGS-setting instruction.
14802 switch (ArithOp.getOpcode()) {
14803 default: llvm_unreachable("unexpected operator!");
14804 case ISD::SUB: Opcode = X86ISD::SUB; break;
14805 case ISD::XOR: Opcode = X86ISD::XOR; break;
14806 case ISD::AND: Opcode = X86ISD::AND; break;
14808 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14809 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14810 if (EFLAGS.getNode())
14813 Opcode = X86ISD::OR;
14827 return SDValue(Op.getNode(), 1);
14833 // If we found that truncation is beneficial, perform the truncation and
14835 if (NeedTruncation) {
14836 EVT VT = Op.getValueType();
14837 SDValue WideVal = Op->getOperand(0);
14838 EVT WideVT = WideVal.getValueType();
14839 unsigned ConvertedOp = 0;
14840 // Use a target machine opcode to prevent further DAGCombine
14841 // optimizations that may separate the arithmetic operations
14842 // from the setcc node.
14843 switch (WideVal.getOpcode()) {
14845 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14846 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14847 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14848 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14849 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14854 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14855 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14856 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14857 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14863 // Emit a CMP with 0, which is the TEST pattern.
14864 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14865 DAG.getConstant(0, Op.getValueType()));
14867 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14868 SmallVector<SDValue, 4> Ops;
14869 for (unsigned i = 0; i != NumOperands; ++i)
14870 Ops.push_back(Op.getOperand(i));
14872 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14873 DAG.ReplaceAllUsesWith(Op, New);
14874 return SDValue(New.getNode(), 1);
14877 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14879 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14880 SDLoc dl, SelectionDAG &DAG) const {
14881 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14882 if (C->getAPIntValue() == 0)
14883 return EmitTest(Op0, X86CC, dl, DAG);
14885 if (Op0.getValueType() == MVT::i1)
14886 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14889 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14890 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14891 // Do the comparison at i32 if it's smaller, besides the Atom case.
14892 // This avoids subregister aliasing issues. Keep the smaller reference
14893 // if we're optimizing for size, however, as that'll allow better folding
14894 // of memory operations.
14895 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14896 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14897 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14898 !Subtarget->isAtom()) {
14899 unsigned ExtendOp =
14900 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14901 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14902 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14904 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14905 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14906 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14908 return SDValue(Sub.getNode(), 1);
14910 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14913 /// Convert a comparison if required by the subtarget.
14914 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14915 SelectionDAG &DAG) const {
14916 // If the subtarget does not support the FUCOMI instruction, floating-point
14917 // comparisons have to be converted.
14918 if (Subtarget->hasCMov() ||
14919 Cmp.getOpcode() != X86ISD::CMP ||
14920 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14921 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14924 // The instruction selector will select an FUCOM instruction instead of
14925 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14926 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14927 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14929 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14930 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14931 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14932 DAG.getConstant(8, MVT::i8));
14933 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14934 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14937 /// The minimum architected relative accuracy is 2^-12. We need one
14938 /// Newton-Raphson step to have a good float result (24 bits of precision).
14939 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14940 DAGCombinerInfo &DCI,
14941 unsigned &RefinementSteps,
14942 bool &UseOneConstNR) const {
14943 // FIXME: We should use instruction latency models to calculate the cost of
14944 // each potential sequence, but this is very hard to do reliably because
14945 // at least Intel's Core* chips have variable timing based on the number of
14946 // significant digits in the divisor and/or sqrt operand.
14947 if (!Subtarget->useSqrtEst())
14950 EVT VT = Op.getValueType();
14952 // SSE1 has rsqrtss and rsqrtps.
14953 // TODO: Add support for AVX512 (v16f32).
14954 // It is likely not profitable to do this for f64 because a double-precision
14955 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14956 // instructions: convert to single, rsqrtss, convert back to double, refine
14957 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14958 // along with FMA, this could be a throughput win.
14959 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14960 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14961 RefinementSteps = 1;
14962 UseOneConstNR = false;
14963 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14968 /// The minimum architected relative accuracy is 2^-12. We need one
14969 /// Newton-Raphson step to have a good float result (24 bits of precision).
14970 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14971 DAGCombinerInfo &DCI,
14972 unsigned &RefinementSteps) const {
14973 // FIXME: We should use instruction latency models to calculate the cost of
14974 // each potential sequence, but this is very hard to do reliably because
14975 // at least Intel's Core* chips have variable timing based on the number of
14976 // significant digits in the divisor.
14977 if (!Subtarget->useReciprocalEst())
14980 EVT VT = Op.getValueType();
14982 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14983 // TODO: Add support for AVX512 (v16f32).
14984 // It is likely not profitable to do this for f64 because a double-precision
14985 // reciprocal estimate with refinement on x86 prior to FMA requires
14986 // 15 instructions: convert to single, rcpss, convert back to double, refine
14987 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14988 // along with FMA, this could be a throughput win.
14989 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14990 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14991 RefinementSteps = ReciprocalEstimateRefinementSteps;
14992 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14997 static bool isAllOnes(SDValue V) {
14998 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14999 return C && C->isAllOnesValue();
15002 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15003 /// if it's possible.
15004 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15005 SDLoc dl, SelectionDAG &DAG) const {
15006 SDValue Op0 = And.getOperand(0);
15007 SDValue Op1 = And.getOperand(1);
15008 if (Op0.getOpcode() == ISD::TRUNCATE)
15009 Op0 = Op0.getOperand(0);
15010 if (Op1.getOpcode() == ISD::TRUNCATE)
15011 Op1 = Op1.getOperand(0);
15014 if (Op1.getOpcode() == ISD::SHL)
15015 std::swap(Op0, Op1);
15016 if (Op0.getOpcode() == ISD::SHL) {
15017 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15018 if (And00C->getZExtValue() == 1) {
15019 // If we looked past a truncate, check that it's only truncating away
15021 unsigned BitWidth = Op0.getValueSizeInBits();
15022 unsigned AndBitWidth = And.getValueSizeInBits();
15023 if (BitWidth > AndBitWidth) {
15025 DAG.computeKnownBits(Op0, Zeros, Ones);
15026 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15030 RHS = Op0.getOperand(1);
15032 } else if (Op1.getOpcode() == ISD::Constant) {
15033 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15034 uint64_t AndRHSVal = AndRHS->getZExtValue();
15035 SDValue AndLHS = Op0;
15037 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15038 LHS = AndLHS.getOperand(0);
15039 RHS = AndLHS.getOperand(1);
15042 // Use BT if the immediate can't be encoded in a TEST instruction.
15043 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15045 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15049 if (LHS.getNode()) {
15050 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15051 // instruction. Since the shift amount is in-range-or-undefined, we know
15052 // that doing a bittest on the i32 value is ok. We extend to i32 because
15053 // the encoding for the i16 version is larger than the i32 version.
15054 // Also promote i16 to i32 for performance / code size reason.
15055 if (LHS.getValueType() == MVT::i8 ||
15056 LHS.getValueType() == MVT::i16)
15057 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15059 // If the operand types disagree, extend the shift amount to match. Since
15060 // BT ignores high bits (like shifts) we can use anyextend.
15061 if (LHS.getValueType() != RHS.getValueType())
15062 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15064 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15065 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15066 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15067 DAG.getConstant(Cond, MVT::i8), BT);
15073 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15075 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15080 // SSE Condition code mapping:
15089 switch (SetCCOpcode) {
15090 default: llvm_unreachable("Unexpected SETCC condition");
15092 case ISD::SETEQ: SSECC = 0; break;
15094 case ISD::SETGT: Swap = true; // Fallthrough
15096 case ISD::SETOLT: SSECC = 1; break;
15098 case ISD::SETGE: Swap = true; // Fallthrough
15100 case ISD::SETOLE: SSECC = 2; break;
15101 case ISD::SETUO: SSECC = 3; break;
15103 case ISD::SETNE: SSECC = 4; break;
15104 case ISD::SETULE: Swap = true; // Fallthrough
15105 case ISD::SETUGE: SSECC = 5; break;
15106 case ISD::SETULT: Swap = true; // Fallthrough
15107 case ISD::SETUGT: SSECC = 6; break;
15108 case ISD::SETO: SSECC = 7; break;
15110 case ISD::SETONE: SSECC = 8; break;
15113 std::swap(Op0, Op1);
15118 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15119 // ones, and then concatenate the result back.
15120 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15121 MVT VT = Op.getSimpleValueType();
15123 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15124 "Unsupported value type for operation");
15126 unsigned NumElems = VT.getVectorNumElements();
15128 SDValue CC = Op.getOperand(2);
15130 // Extract the LHS vectors
15131 SDValue LHS = Op.getOperand(0);
15132 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15133 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15135 // Extract the RHS vectors
15136 SDValue RHS = Op.getOperand(1);
15137 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15138 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15140 // Issue the operation on the smaller types and concatenate the result back
15141 MVT EltVT = VT.getVectorElementType();
15142 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15143 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15144 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15145 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15148 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15149 const X86Subtarget *Subtarget) {
15150 SDValue Op0 = Op.getOperand(0);
15151 SDValue Op1 = Op.getOperand(1);
15152 SDValue CC = Op.getOperand(2);
15153 MVT VT = Op.getSimpleValueType();
15156 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15157 Op.getValueType().getScalarType() == MVT::i1 &&
15158 "Cannot set masked compare for this operation");
15160 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15162 bool Unsigned = false;
15165 switch (SetCCOpcode) {
15166 default: llvm_unreachable("Unexpected SETCC condition");
15167 case ISD::SETNE: SSECC = 4; break;
15168 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15169 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15170 case ISD::SETLT: Swap = true; //fall-through
15171 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15172 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15173 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15174 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15175 case ISD::SETULE: Unsigned = true; //fall-through
15176 case ISD::SETLE: SSECC = 2; break;
15180 std::swap(Op0, Op1);
15182 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15183 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15184 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15185 DAG.getConstant(SSECC, MVT::i8));
15188 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15189 /// operand \p Op1. If non-trivial (for example because it's not constant)
15190 /// return an empty value.
15191 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15193 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15197 MVT VT = Op1.getSimpleValueType();
15198 MVT EVT = VT.getVectorElementType();
15199 unsigned n = VT.getVectorNumElements();
15200 SmallVector<SDValue, 8> ULTOp1;
15202 for (unsigned i = 0; i < n; ++i) {
15203 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15204 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15207 // Avoid underflow.
15208 APInt Val = Elt->getAPIntValue();
15212 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15215 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15218 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15219 SelectionDAG &DAG) {
15220 SDValue Op0 = Op.getOperand(0);
15221 SDValue Op1 = Op.getOperand(1);
15222 SDValue CC = Op.getOperand(2);
15223 MVT VT = Op.getSimpleValueType();
15224 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15225 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15230 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15231 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15234 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15235 unsigned Opc = X86ISD::CMPP;
15236 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15237 assert(VT.getVectorNumElements() <= 16);
15238 Opc = X86ISD::CMPM;
15240 // In the two special cases we can't handle, emit two comparisons.
15243 unsigned CombineOpc;
15244 if (SetCCOpcode == ISD::SETUEQ) {
15245 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15247 assert(SetCCOpcode == ISD::SETONE);
15248 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15251 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15252 DAG.getConstant(CC0, MVT::i8));
15253 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15254 DAG.getConstant(CC1, MVT::i8));
15255 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15257 // Handle all other FP comparisons here.
15258 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15259 DAG.getConstant(SSECC, MVT::i8));
15262 // Break 256-bit integer vector compare into smaller ones.
15263 if (VT.is256BitVector() && !Subtarget->hasInt256())
15264 return Lower256IntVSETCC(Op, DAG);
15266 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15267 EVT OpVT = Op1.getValueType();
15268 if (Subtarget->hasAVX512()) {
15269 if (Op1.getValueType().is512BitVector() ||
15270 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15271 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15272 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15274 // In AVX-512 architecture setcc returns mask with i1 elements,
15275 // But there is no compare instruction for i8 and i16 elements in KNL.
15276 // We are not talking about 512-bit operands in this case, these
15277 // types are illegal.
15279 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15280 OpVT.getVectorElementType().getSizeInBits() >= 8))
15281 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15282 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15285 // We are handling one of the integer comparisons here. Since SSE only has
15286 // GT and EQ comparisons for integer, swapping operands and multiple
15287 // operations may be required for some comparisons.
15289 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15290 bool Subus = false;
15292 switch (SetCCOpcode) {
15293 default: llvm_unreachable("Unexpected SETCC condition");
15294 case ISD::SETNE: Invert = true;
15295 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15296 case ISD::SETLT: Swap = true;
15297 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15298 case ISD::SETGE: Swap = true;
15299 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15300 Invert = true; break;
15301 case ISD::SETULT: Swap = true;
15302 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15303 FlipSigns = true; break;
15304 case ISD::SETUGE: Swap = true;
15305 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15306 FlipSigns = true; Invert = true; break;
15309 // Special case: Use min/max operations for SETULE/SETUGE
15310 MVT VET = VT.getVectorElementType();
15312 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15313 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15316 switch (SetCCOpcode) {
15318 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15319 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15322 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15325 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15326 if (!MinMax && hasSubus) {
15327 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15329 // t = psubus Op0, Op1
15330 // pcmpeq t, <0..0>
15331 switch (SetCCOpcode) {
15333 case ISD::SETULT: {
15334 // If the comparison is against a constant we can turn this into a
15335 // setule. With psubus, setule does not require a swap. This is
15336 // beneficial because the constant in the register is no longer
15337 // destructed as the destination so it can be hoisted out of a loop.
15338 // Only do this pre-AVX since vpcmp* is no longer destructive.
15339 if (Subtarget->hasAVX())
15341 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15342 if (ULEOp1.getNode()) {
15344 Subus = true; Invert = false; Swap = false;
15348 // Psubus is better than flip-sign because it requires no inversion.
15349 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15350 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15354 Opc = X86ISD::SUBUS;
15360 std::swap(Op0, Op1);
15362 // Check that the operation in question is available (most are plain SSE2,
15363 // but PCMPGTQ and PCMPEQQ have different requirements).
15364 if (VT == MVT::v2i64) {
15365 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15366 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15368 // First cast everything to the right type.
15369 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15370 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15372 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15373 // bits of the inputs before performing those operations. The lower
15374 // compare is always unsigned.
15377 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15379 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15380 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15381 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15382 Sign, Zero, Sign, Zero);
15384 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15385 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15387 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15388 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15389 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15391 // Create masks for only the low parts/high parts of the 64 bit integers.
15392 static const int MaskHi[] = { 1, 1, 3, 3 };
15393 static const int MaskLo[] = { 0, 0, 2, 2 };
15394 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15395 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15396 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15398 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15399 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15402 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15404 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15407 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15408 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15409 // pcmpeqd + pshufd + pand.
15410 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15412 // First cast everything to the right type.
15413 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15414 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15417 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15419 // Make sure the lower and upper halves are both all-ones.
15420 static const int Mask[] = { 1, 0, 3, 2 };
15421 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15422 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15425 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15427 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15431 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15432 // bits of the inputs before performing those operations.
15434 EVT EltVT = VT.getVectorElementType();
15435 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15436 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15437 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15440 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15442 // If the logical-not of the result is required, perform that now.
15444 Result = DAG.getNOT(dl, Result, VT);
15447 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15450 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15451 getZeroVector(VT, Subtarget, DAG, dl));
15456 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15458 MVT VT = Op.getSimpleValueType();
15460 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15462 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15463 && "SetCC type must be 8-bit or 1-bit integer");
15464 SDValue Op0 = Op.getOperand(0);
15465 SDValue Op1 = Op.getOperand(1);
15467 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15469 // Optimize to BT if possible.
15470 // Lower (X & (1 << N)) == 0 to BT(X, N).
15471 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15472 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15473 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15474 Op1.getOpcode() == ISD::Constant &&
15475 cast<ConstantSDNode>(Op1)->isNullValue() &&
15476 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15477 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15478 if (NewSetCC.getNode())
15482 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15484 if (Op1.getOpcode() == ISD::Constant &&
15485 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15486 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15487 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15489 // If the input is a setcc, then reuse the input setcc or use a new one with
15490 // the inverted condition.
15491 if (Op0.getOpcode() == X86ISD::SETCC) {
15492 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15493 bool Invert = (CC == ISD::SETNE) ^
15494 cast<ConstantSDNode>(Op1)->isNullValue();
15498 CCode = X86::GetOppositeBranchCondition(CCode);
15499 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15500 DAG.getConstant(CCode, MVT::i8),
15501 Op0.getOperand(1));
15503 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15507 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15508 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15509 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15511 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15512 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15515 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15516 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15517 if (X86CC == X86::COND_INVALID)
15520 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15521 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15522 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15523 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15525 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15529 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15530 static bool isX86LogicalCmp(SDValue Op) {
15531 unsigned Opc = Op.getNode()->getOpcode();
15532 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15533 Opc == X86ISD::SAHF)
15535 if (Op.getResNo() == 1 &&
15536 (Opc == X86ISD::ADD ||
15537 Opc == X86ISD::SUB ||
15538 Opc == X86ISD::ADC ||
15539 Opc == X86ISD::SBB ||
15540 Opc == X86ISD::SMUL ||
15541 Opc == X86ISD::UMUL ||
15542 Opc == X86ISD::INC ||
15543 Opc == X86ISD::DEC ||
15544 Opc == X86ISD::OR ||
15545 Opc == X86ISD::XOR ||
15546 Opc == X86ISD::AND))
15549 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15555 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15556 if (V.getOpcode() != ISD::TRUNCATE)
15559 SDValue VOp0 = V.getOperand(0);
15560 unsigned InBits = VOp0.getValueSizeInBits();
15561 unsigned Bits = V.getValueSizeInBits();
15562 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15565 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15566 bool addTest = true;
15567 SDValue Cond = Op.getOperand(0);
15568 SDValue Op1 = Op.getOperand(1);
15569 SDValue Op2 = Op.getOperand(2);
15571 EVT VT = Op1.getValueType();
15574 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15575 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15576 // sequence later on.
15577 if (Cond.getOpcode() == ISD::SETCC &&
15578 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15579 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15580 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15581 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15582 int SSECC = translateX86FSETCC(
15583 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15586 if (Subtarget->hasAVX512()) {
15587 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15588 DAG.getConstant(SSECC, MVT::i8));
15589 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15591 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15592 DAG.getConstant(SSECC, MVT::i8));
15593 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15594 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15595 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15599 if (Cond.getOpcode() == ISD::SETCC) {
15600 SDValue NewCond = LowerSETCC(Cond, DAG);
15601 if (NewCond.getNode())
15605 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15606 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15607 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15608 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15609 if (Cond.getOpcode() == X86ISD::SETCC &&
15610 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15611 isZero(Cond.getOperand(1).getOperand(1))) {
15612 SDValue Cmp = Cond.getOperand(1);
15614 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15616 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15617 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15618 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15620 SDValue CmpOp0 = Cmp.getOperand(0);
15621 // Apply further optimizations for special cases
15622 // (select (x != 0), -1, 0) -> neg & sbb
15623 // (select (x == 0), 0, -1) -> neg & sbb
15624 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15625 if (YC->isNullValue() &&
15626 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15627 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15628 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15629 DAG.getConstant(0, CmpOp0.getValueType()),
15631 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15632 DAG.getConstant(X86::COND_B, MVT::i8),
15633 SDValue(Neg.getNode(), 1));
15637 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15638 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15639 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15641 SDValue Res = // Res = 0 or -1.
15642 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15643 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15645 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15646 Res = DAG.getNOT(DL, Res, Res.getValueType());
15648 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15649 if (!N2C || !N2C->isNullValue())
15650 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15655 // Look past (and (setcc_carry (cmp ...)), 1).
15656 if (Cond.getOpcode() == ISD::AND &&
15657 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15658 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15659 if (C && C->getAPIntValue() == 1)
15660 Cond = Cond.getOperand(0);
15663 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15664 // setting operand in place of the X86ISD::SETCC.
15665 unsigned CondOpcode = Cond.getOpcode();
15666 if (CondOpcode == X86ISD::SETCC ||
15667 CondOpcode == X86ISD::SETCC_CARRY) {
15668 CC = Cond.getOperand(0);
15670 SDValue Cmp = Cond.getOperand(1);
15671 unsigned Opc = Cmp.getOpcode();
15672 MVT VT = Op.getSimpleValueType();
15674 bool IllegalFPCMov = false;
15675 if (VT.isFloatingPoint() && !VT.isVector() &&
15676 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15677 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15679 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15680 Opc == X86ISD::BT) { // FIXME
15684 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15685 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15686 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15687 Cond.getOperand(0).getValueType() != MVT::i8)) {
15688 SDValue LHS = Cond.getOperand(0);
15689 SDValue RHS = Cond.getOperand(1);
15690 unsigned X86Opcode;
15693 switch (CondOpcode) {
15694 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15695 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15696 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15697 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15698 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15699 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15700 default: llvm_unreachable("unexpected overflowing operator");
15702 if (CondOpcode == ISD::UMULO)
15703 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15706 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15708 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15710 if (CondOpcode == ISD::UMULO)
15711 Cond = X86Op.getValue(2);
15713 Cond = X86Op.getValue(1);
15715 CC = DAG.getConstant(X86Cond, MVT::i8);
15720 // Look pass the truncate if the high bits are known zero.
15721 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15722 Cond = Cond.getOperand(0);
15724 // We know the result of AND is compared against zero. Try to match
15726 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15727 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15728 if (NewSetCC.getNode()) {
15729 CC = NewSetCC.getOperand(0);
15730 Cond = NewSetCC.getOperand(1);
15737 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15738 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15741 // a < b ? -1 : 0 -> RES = ~setcc_carry
15742 // a < b ? 0 : -1 -> RES = setcc_carry
15743 // a >= b ? -1 : 0 -> RES = setcc_carry
15744 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15745 if (Cond.getOpcode() == X86ISD::SUB) {
15746 Cond = ConvertCmpIfNecessary(Cond, DAG);
15747 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15749 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15750 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15751 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15752 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15753 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15754 return DAG.getNOT(DL, Res, Res.getValueType());
15759 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15760 // widen the cmov and push the truncate through. This avoids introducing a new
15761 // branch during isel and doesn't add any extensions.
15762 if (Op.getValueType() == MVT::i8 &&
15763 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15764 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15765 if (T1.getValueType() == T2.getValueType() &&
15766 // Blacklist CopyFromReg to avoid partial register stalls.
15767 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15768 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15769 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15770 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15774 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15775 // condition is true.
15776 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15777 SDValue Ops[] = { Op2, Op1, CC, Cond };
15778 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15781 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15782 SelectionDAG &DAG) {
15783 MVT VT = Op->getSimpleValueType(0);
15784 SDValue In = Op->getOperand(0);
15785 MVT InVT = In.getSimpleValueType();
15786 MVT VTElt = VT.getVectorElementType();
15787 MVT InVTElt = InVT.getVectorElementType();
15791 if ((InVTElt == MVT::i1) &&
15792 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15793 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15795 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15796 VTElt.getSizeInBits() <= 16)) ||
15798 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15799 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15801 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15802 VTElt.getSizeInBits() >= 32))))
15803 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15805 unsigned int NumElts = VT.getVectorNumElements();
15807 if (NumElts != 8 && NumElts != 16)
15810 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15811 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15812 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15813 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15816 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15817 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15819 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15820 Constant *C = ConstantInt::get(*DAG.getContext(),
15821 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15823 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15824 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15825 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15826 MachinePointerInfo::getConstantPool(),
15827 false, false, false, Alignment);
15828 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15829 if (VT.is512BitVector())
15831 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15834 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15835 SelectionDAG &DAG) {
15836 MVT VT = Op->getSimpleValueType(0);
15837 SDValue In = Op->getOperand(0);
15838 MVT InVT = In.getSimpleValueType();
15841 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15842 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15844 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15845 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15846 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15849 if (Subtarget->hasInt256())
15850 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15852 // Optimize vectors in AVX mode
15853 // Sign extend v8i16 to v8i32 and
15856 // Divide input vector into two parts
15857 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15858 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15859 // concat the vectors to original VT
15861 unsigned NumElems = InVT.getVectorNumElements();
15862 SDValue Undef = DAG.getUNDEF(InVT);
15864 SmallVector<int,8> ShufMask1(NumElems, -1);
15865 for (unsigned i = 0; i != NumElems/2; ++i)
15868 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15870 SmallVector<int,8> ShufMask2(NumElems, -1);
15871 for (unsigned i = 0; i != NumElems/2; ++i)
15872 ShufMask2[i] = i + NumElems/2;
15874 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15876 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15877 VT.getVectorNumElements()/2);
15879 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15880 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15882 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15885 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15886 // may emit an illegal shuffle but the expansion is still better than scalar
15887 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15888 // we'll emit a shuffle and a arithmetic shift.
15889 // TODO: It is possible to support ZExt by zeroing the undef values during
15890 // the shuffle phase or after the shuffle.
15891 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15892 SelectionDAG &DAG) {
15893 MVT RegVT = Op.getSimpleValueType();
15894 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15895 assert(RegVT.isInteger() &&
15896 "We only custom lower integer vector sext loads.");
15898 // Nothing useful we can do without SSE2 shuffles.
15899 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15901 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15903 EVT MemVT = Ld->getMemoryVT();
15904 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15905 unsigned RegSz = RegVT.getSizeInBits();
15907 ISD::LoadExtType Ext = Ld->getExtensionType();
15909 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15910 && "Only anyext and sext are currently implemented.");
15911 assert(MemVT != RegVT && "Cannot extend to the same type");
15912 assert(MemVT.isVector() && "Must load a vector from memory");
15914 unsigned NumElems = RegVT.getVectorNumElements();
15915 unsigned MemSz = MemVT.getSizeInBits();
15916 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15918 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15919 // The only way in which we have a legal 256-bit vector result but not the
15920 // integer 256-bit operations needed to directly lower a sextload is if we
15921 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15922 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15923 // correctly legalized. We do this late to allow the canonical form of
15924 // sextload to persist throughout the rest of the DAG combiner -- it wants
15925 // to fold together any extensions it can, and so will fuse a sign_extend
15926 // of an sextload into a sextload targeting a wider value.
15928 if (MemSz == 128) {
15929 // Just switch this to a normal load.
15930 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15931 "it must be a legal 128-bit vector "
15933 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15934 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15935 Ld->isInvariant(), Ld->getAlignment());
15937 assert(MemSz < 128 &&
15938 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15939 // Do an sext load to a 128-bit vector type. We want to use the same
15940 // number of elements, but elements half as wide. This will end up being
15941 // recursively lowered by this routine, but will succeed as we definitely
15942 // have all the necessary features if we're using AVX1.
15944 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15945 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15947 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15948 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15949 Ld->isNonTemporal(), Ld->isInvariant(),
15950 Ld->getAlignment());
15953 // Replace chain users with the new chain.
15954 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15955 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15957 // Finally, do a normal sign-extend to the desired register.
15958 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15961 // All sizes must be a power of two.
15962 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15963 "Non-power-of-two elements are not custom lowered!");
15965 // Attempt to load the original value using scalar loads.
15966 // Find the largest scalar type that divides the total loaded size.
15967 MVT SclrLoadTy = MVT::i8;
15968 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15969 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15970 MVT Tp = (MVT::SimpleValueType)tp;
15971 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15976 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15977 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15979 SclrLoadTy = MVT::f64;
15981 // Calculate the number of scalar loads that we need to perform
15982 // in order to load our vector from memory.
15983 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15985 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15986 "Can only lower sext loads with a single scalar load!");
15988 unsigned loadRegZize = RegSz;
15989 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15992 // Represent our vector as a sequence of elements which are the
15993 // largest scalar that we can load.
15994 EVT LoadUnitVecVT = EVT::getVectorVT(
15995 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15997 // Represent the data using the same element type that is stored in
15998 // memory. In practice, we ''widen'' MemVT.
16000 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16001 loadRegZize / MemVT.getScalarType().getSizeInBits());
16003 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16004 "Invalid vector type");
16006 // We can't shuffle using an illegal type.
16007 assert(TLI.isTypeLegal(WideVecVT) &&
16008 "We only lower types that form legal widened vector types");
16010 SmallVector<SDValue, 8> Chains;
16011 SDValue Ptr = Ld->getBasePtr();
16012 SDValue Increment =
16013 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16014 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16016 for (unsigned i = 0; i < NumLoads; ++i) {
16017 // Perform a single load.
16018 SDValue ScalarLoad =
16019 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16020 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16021 Ld->getAlignment());
16022 Chains.push_back(ScalarLoad.getValue(1));
16023 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16024 // another round of DAGCombining.
16026 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16028 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16029 ScalarLoad, DAG.getIntPtrConstant(i));
16031 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16034 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16036 // Bitcast the loaded value to a vector of the original element type, in
16037 // the size of the target vector type.
16038 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16039 unsigned SizeRatio = RegSz / MemSz;
16041 if (Ext == ISD::SEXTLOAD) {
16042 // If we have SSE4.1, we can directly emit a VSEXT node.
16043 if (Subtarget->hasSSE41()) {
16044 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16045 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16049 // Otherwise we'll shuffle the small elements in the high bits of the
16050 // larger type and perform an arithmetic shift. If the shift is not legal
16051 // it's better to scalarize.
16052 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16053 "We can't implement a sext load without an arithmetic right shift!");
16055 // Redistribute the loaded elements into the different locations.
16056 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16057 for (unsigned i = 0; i != NumElems; ++i)
16058 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16060 SDValue Shuff = DAG.getVectorShuffle(
16061 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16063 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16065 // Build the arithmetic shift.
16066 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16067 MemVT.getVectorElementType().getSizeInBits();
16069 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16071 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16075 // Redistribute the loaded elements into the different locations.
16076 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16077 for (unsigned i = 0; i != NumElems; ++i)
16078 ShuffleVec[i * SizeRatio] = i;
16080 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16081 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16083 // Bitcast to the requested type.
16084 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16085 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16089 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16090 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16091 // from the AND / OR.
16092 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16093 Opc = Op.getOpcode();
16094 if (Opc != ISD::OR && Opc != ISD::AND)
16096 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16097 Op.getOperand(0).hasOneUse() &&
16098 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16099 Op.getOperand(1).hasOneUse());
16102 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16103 // 1 and that the SETCC node has a single use.
16104 static bool isXor1OfSetCC(SDValue Op) {
16105 if (Op.getOpcode() != ISD::XOR)
16107 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16108 if (N1C && N1C->getAPIntValue() == 1) {
16109 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16110 Op.getOperand(0).hasOneUse();
16115 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16116 bool addTest = true;
16117 SDValue Chain = Op.getOperand(0);
16118 SDValue Cond = Op.getOperand(1);
16119 SDValue Dest = Op.getOperand(2);
16122 bool Inverted = false;
16124 if (Cond.getOpcode() == ISD::SETCC) {
16125 // Check for setcc([su]{add,sub,mul}o == 0).
16126 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16127 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16128 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16129 Cond.getOperand(0).getResNo() == 1 &&
16130 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16131 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16132 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16133 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16134 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16135 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16137 Cond = Cond.getOperand(0);
16139 SDValue NewCond = LowerSETCC(Cond, DAG);
16140 if (NewCond.getNode())
16145 // FIXME: LowerXALUO doesn't handle these!!
16146 else if (Cond.getOpcode() == X86ISD::ADD ||
16147 Cond.getOpcode() == X86ISD::SUB ||
16148 Cond.getOpcode() == X86ISD::SMUL ||
16149 Cond.getOpcode() == X86ISD::UMUL)
16150 Cond = LowerXALUO(Cond, DAG);
16153 // Look pass (and (setcc_carry (cmp ...)), 1).
16154 if (Cond.getOpcode() == ISD::AND &&
16155 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16156 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16157 if (C && C->getAPIntValue() == 1)
16158 Cond = Cond.getOperand(0);
16161 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16162 // setting operand in place of the X86ISD::SETCC.
16163 unsigned CondOpcode = Cond.getOpcode();
16164 if (CondOpcode == X86ISD::SETCC ||
16165 CondOpcode == X86ISD::SETCC_CARRY) {
16166 CC = Cond.getOperand(0);
16168 SDValue Cmp = Cond.getOperand(1);
16169 unsigned Opc = Cmp.getOpcode();
16170 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16171 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16175 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16179 // These can only come from an arithmetic instruction with overflow,
16180 // e.g. SADDO, UADDO.
16181 Cond = Cond.getNode()->getOperand(1);
16187 CondOpcode = Cond.getOpcode();
16188 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16189 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16190 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16191 Cond.getOperand(0).getValueType() != MVT::i8)) {
16192 SDValue LHS = Cond.getOperand(0);
16193 SDValue RHS = Cond.getOperand(1);
16194 unsigned X86Opcode;
16197 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16198 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16200 switch (CondOpcode) {
16201 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16203 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16205 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16208 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16209 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16213 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16216 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16217 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16218 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16219 default: llvm_unreachable("unexpected overflowing operator");
16222 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16223 if (CondOpcode == ISD::UMULO)
16224 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16227 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16229 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16231 if (CondOpcode == ISD::UMULO)
16232 Cond = X86Op.getValue(2);
16234 Cond = X86Op.getValue(1);
16236 CC = DAG.getConstant(X86Cond, MVT::i8);
16240 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16241 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16242 if (CondOpc == ISD::OR) {
16243 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16244 // two branches instead of an explicit OR instruction with a
16246 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16247 isX86LogicalCmp(Cmp)) {
16248 CC = Cond.getOperand(0).getOperand(0);
16249 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16250 Chain, Dest, CC, Cmp);
16251 CC = Cond.getOperand(1).getOperand(0);
16255 } else { // ISD::AND
16256 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16257 // two branches instead of an explicit AND instruction with a
16258 // separate test. However, we only do this if this block doesn't
16259 // have a fall-through edge, because this requires an explicit
16260 // jmp when the condition is false.
16261 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16262 isX86LogicalCmp(Cmp) &&
16263 Op.getNode()->hasOneUse()) {
16264 X86::CondCode CCode =
16265 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16266 CCode = X86::GetOppositeBranchCondition(CCode);
16267 CC = DAG.getConstant(CCode, MVT::i8);
16268 SDNode *User = *Op.getNode()->use_begin();
16269 // Look for an unconditional branch following this conditional branch.
16270 // We need this because we need to reverse the successors in order
16271 // to implement FCMP_OEQ.
16272 if (User->getOpcode() == ISD::BR) {
16273 SDValue FalseBB = User->getOperand(1);
16275 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16276 assert(NewBR == User);
16280 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16281 Chain, Dest, CC, Cmp);
16282 X86::CondCode CCode =
16283 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16284 CCode = X86::GetOppositeBranchCondition(CCode);
16285 CC = DAG.getConstant(CCode, MVT::i8);
16291 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16292 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16293 // It should be transformed during dag combiner except when the condition
16294 // is set by a arithmetics with overflow node.
16295 X86::CondCode CCode =
16296 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16297 CCode = X86::GetOppositeBranchCondition(CCode);
16298 CC = DAG.getConstant(CCode, MVT::i8);
16299 Cond = Cond.getOperand(0).getOperand(1);
16301 } else if (Cond.getOpcode() == ISD::SETCC &&
16302 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16303 // For FCMP_OEQ, we can emit
16304 // two branches instead of an explicit AND instruction with a
16305 // separate test. However, we only do this if this block doesn't
16306 // have a fall-through edge, because this requires an explicit
16307 // jmp when the condition is false.
16308 if (Op.getNode()->hasOneUse()) {
16309 SDNode *User = *Op.getNode()->use_begin();
16310 // Look for an unconditional branch following this conditional branch.
16311 // We need this because we need to reverse the successors in order
16312 // to implement FCMP_OEQ.
16313 if (User->getOpcode() == ISD::BR) {
16314 SDValue FalseBB = User->getOperand(1);
16316 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16317 assert(NewBR == User);
16321 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16322 Cond.getOperand(0), Cond.getOperand(1));
16323 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16324 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16325 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16326 Chain, Dest, CC, Cmp);
16327 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16332 } else if (Cond.getOpcode() == ISD::SETCC &&
16333 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16334 // For FCMP_UNE, we can emit
16335 // two branches instead of an explicit AND instruction with a
16336 // separate test. However, we only do this if this block doesn't
16337 // have a fall-through edge, because this requires an explicit
16338 // jmp when the condition is false.
16339 if (Op.getNode()->hasOneUse()) {
16340 SDNode *User = *Op.getNode()->use_begin();
16341 // Look for an unconditional branch following this conditional branch.
16342 // We need this because we need to reverse the successors in order
16343 // to implement FCMP_UNE.
16344 if (User->getOpcode() == ISD::BR) {
16345 SDValue FalseBB = User->getOperand(1);
16347 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16348 assert(NewBR == User);
16351 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16352 Cond.getOperand(0), Cond.getOperand(1));
16353 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16354 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16355 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16356 Chain, Dest, CC, Cmp);
16357 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16367 // Look pass the truncate if the high bits are known zero.
16368 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16369 Cond = Cond.getOperand(0);
16371 // We know the result of AND is compared against zero. Try to match
16373 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16374 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16375 if (NewSetCC.getNode()) {
16376 CC = NewSetCC.getOperand(0);
16377 Cond = NewSetCC.getOperand(1);
16384 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16385 CC = DAG.getConstant(X86Cond, MVT::i8);
16386 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16388 Cond = ConvertCmpIfNecessary(Cond, DAG);
16389 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16390 Chain, Dest, CC, Cond);
16393 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16394 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16395 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16396 // that the guard pages used by the OS virtual memory manager are allocated in
16397 // correct sequence.
16399 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16400 SelectionDAG &DAG) const {
16401 MachineFunction &MF = DAG.getMachineFunction();
16402 bool SplitStack = MF.shouldSplitStack();
16403 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16408 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16409 SDNode* Node = Op.getNode();
16411 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16412 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16413 " not tell us which reg is the stack pointer!");
16414 EVT VT = Node->getValueType(0);
16415 SDValue Tmp1 = SDValue(Node, 0);
16416 SDValue Tmp2 = SDValue(Node, 1);
16417 SDValue Tmp3 = Node->getOperand(2);
16418 SDValue Chain = Tmp1.getOperand(0);
16420 // Chain the dynamic stack allocation so that it doesn't modify the stack
16421 // pointer when other instructions are using the stack.
16422 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16425 SDValue Size = Tmp2.getOperand(1);
16426 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16427 Chain = SP.getValue(1);
16428 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16429 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16430 unsigned StackAlign = TFI.getStackAlignment();
16431 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16432 if (Align > StackAlign)
16433 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16434 DAG.getConstant(-(uint64_t)Align, VT));
16435 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16437 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16438 DAG.getIntPtrConstant(0, true), SDValue(),
16441 SDValue Ops[2] = { Tmp1, Tmp2 };
16442 return DAG.getMergeValues(Ops, dl);
16446 SDValue Chain = Op.getOperand(0);
16447 SDValue Size = Op.getOperand(1);
16448 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16449 EVT VT = Op.getNode()->getValueType(0);
16451 bool Is64Bit = Subtarget->is64Bit();
16452 EVT SPTy = getPointerTy();
16455 MachineRegisterInfo &MRI = MF.getRegInfo();
16458 // The 64 bit implementation of segmented stacks needs to clobber both r10
16459 // r11. This makes it impossible to use it along with nested parameters.
16460 const Function *F = MF.getFunction();
16462 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16464 if (I->hasNestAttr())
16465 report_fatal_error("Cannot use segmented stacks with functions that "
16466 "have nested arguments.");
16469 const TargetRegisterClass *AddrRegClass =
16470 getRegClassFor(getPointerTy());
16471 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16472 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16473 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16474 DAG.getRegister(Vreg, SPTy));
16475 SDValue Ops1[2] = { Value, Chain };
16476 return DAG.getMergeValues(Ops1, dl);
16479 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16481 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16482 Flag = Chain.getValue(1);
16483 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16485 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16487 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16488 DAG.getSubtarget().getRegisterInfo());
16489 unsigned SPReg = RegInfo->getStackRegister();
16490 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16491 Chain = SP.getValue(1);
16494 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16495 DAG.getConstant(-(uint64_t)Align, VT));
16496 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16499 SDValue Ops1[2] = { SP, Chain };
16500 return DAG.getMergeValues(Ops1, dl);
16504 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16505 MachineFunction &MF = DAG.getMachineFunction();
16506 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16508 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16511 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16512 // vastart just stores the address of the VarArgsFrameIndex slot into the
16513 // memory location argument.
16514 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16516 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16517 MachinePointerInfo(SV), false, false, 0);
16521 // gp_offset (0 - 6 * 8)
16522 // fp_offset (48 - 48 + 8 * 16)
16523 // overflow_arg_area (point to parameters coming in memory).
16525 SmallVector<SDValue, 8> MemOps;
16526 SDValue FIN = Op.getOperand(1);
16528 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16529 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16531 FIN, MachinePointerInfo(SV), false, false, 0);
16532 MemOps.push_back(Store);
16535 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16536 FIN, DAG.getIntPtrConstant(4));
16537 Store = DAG.getStore(Op.getOperand(0), DL,
16538 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16540 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16541 MemOps.push_back(Store);
16543 // Store ptr to overflow_arg_area
16544 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16545 FIN, DAG.getIntPtrConstant(4));
16546 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16548 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16549 MachinePointerInfo(SV, 8),
16551 MemOps.push_back(Store);
16553 // Store ptr to reg_save_area.
16554 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16555 FIN, DAG.getIntPtrConstant(8));
16556 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16558 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16559 MachinePointerInfo(SV, 16), false, false, 0);
16560 MemOps.push_back(Store);
16561 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16564 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16565 assert(Subtarget->is64Bit() &&
16566 "LowerVAARG only handles 64-bit va_arg!");
16567 assert((Subtarget->isTargetLinux() ||
16568 Subtarget->isTargetDarwin()) &&
16569 "Unhandled target in LowerVAARG");
16570 assert(Op.getNode()->getNumOperands() == 4);
16571 SDValue Chain = Op.getOperand(0);
16572 SDValue SrcPtr = Op.getOperand(1);
16573 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16574 unsigned Align = Op.getConstantOperandVal(3);
16577 EVT ArgVT = Op.getNode()->getValueType(0);
16578 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16579 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16582 // Decide which area this value should be read from.
16583 // TODO: Implement the AMD64 ABI in its entirety. This simple
16584 // selection mechanism works only for the basic types.
16585 if (ArgVT == MVT::f80) {
16586 llvm_unreachable("va_arg for f80 not yet implemented");
16587 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16588 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16589 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16590 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16592 llvm_unreachable("Unhandled argument type in LowerVAARG");
16595 if (ArgMode == 2) {
16596 // Sanity Check: Make sure using fp_offset makes sense.
16597 assert(!DAG.getTarget().Options.UseSoftFloat &&
16598 !(DAG.getMachineFunction()
16599 .getFunction()->getAttributes()
16600 .hasAttribute(AttributeSet::FunctionIndex,
16601 Attribute::NoImplicitFloat)) &&
16602 Subtarget->hasSSE1());
16605 // Insert VAARG_64 node into the DAG
16606 // VAARG_64 returns two values: Variable Argument Address, Chain
16607 SmallVector<SDValue, 11> InstOps;
16608 InstOps.push_back(Chain);
16609 InstOps.push_back(SrcPtr);
16610 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16611 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16612 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16613 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16614 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16615 VTs, InstOps, MVT::i64,
16616 MachinePointerInfo(SV),
16618 /*Volatile=*/false,
16620 /*WriteMem=*/true);
16621 Chain = VAARG.getValue(1);
16623 // Load the next argument and return it
16624 return DAG.getLoad(ArgVT, dl,
16627 MachinePointerInfo(),
16628 false, false, false, 0);
16631 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16632 SelectionDAG &DAG) {
16633 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16634 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16635 SDValue Chain = Op.getOperand(0);
16636 SDValue DstPtr = Op.getOperand(1);
16637 SDValue SrcPtr = Op.getOperand(2);
16638 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16639 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16642 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16643 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16645 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16648 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16649 // amount is a constant. Takes immediate version of shift as input.
16650 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16651 SDValue SrcOp, uint64_t ShiftAmt,
16652 SelectionDAG &DAG) {
16653 MVT ElementType = VT.getVectorElementType();
16655 // Fold this packed shift into its first operand if ShiftAmt is 0.
16659 // Check for ShiftAmt >= element width
16660 if (ShiftAmt >= ElementType.getSizeInBits()) {
16661 if (Opc == X86ISD::VSRAI)
16662 ShiftAmt = ElementType.getSizeInBits() - 1;
16664 return DAG.getConstant(0, VT);
16667 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16668 && "Unknown target vector shift-by-constant node");
16670 // Fold this packed vector shift into a build vector if SrcOp is a
16671 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16672 if (VT == SrcOp.getSimpleValueType() &&
16673 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16674 SmallVector<SDValue, 8> Elts;
16675 unsigned NumElts = SrcOp->getNumOperands();
16676 ConstantSDNode *ND;
16679 default: llvm_unreachable(nullptr);
16680 case X86ISD::VSHLI:
16681 for (unsigned i=0; i!=NumElts; ++i) {
16682 SDValue CurrentOp = SrcOp->getOperand(i);
16683 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16684 Elts.push_back(CurrentOp);
16687 ND = cast<ConstantSDNode>(CurrentOp);
16688 const APInt &C = ND->getAPIntValue();
16689 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16692 case X86ISD::VSRLI:
16693 for (unsigned i=0; i!=NumElts; ++i) {
16694 SDValue CurrentOp = SrcOp->getOperand(i);
16695 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16696 Elts.push_back(CurrentOp);
16699 ND = cast<ConstantSDNode>(CurrentOp);
16700 const APInt &C = ND->getAPIntValue();
16701 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16704 case X86ISD::VSRAI:
16705 for (unsigned i=0; i!=NumElts; ++i) {
16706 SDValue CurrentOp = SrcOp->getOperand(i);
16707 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16708 Elts.push_back(CurrentOp);
16711 ND = cast<ConstantSDNode>(CurrentOp);
16712 const APInt &C = ND->getAPIntValue();
16713 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16718 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16721 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16724 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16725 // may or may not be a constant. Takes immediate version of shift as input.
16726 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16727 SDValue SrcOp, SDValue ShAmt,
16728 SelectionDAG &DAG) {
16729 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16731 // Catch shift-by-constant.
16732 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16733 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16734 CShAmt->getZExtValue(), DAG);
16736 // Change opcode to non-immediate version
16738 default: llvm_unreachable("Unknown target vector shift node");
16739 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16740 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16741 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16744 // Need to build a vector containing shift amount
16745 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16748 ShOps[1] = DAG.getConstant(0, MVT::i32);
16749 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16750 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16752 // The return type has to be a 128-bit type with the same element
16753 // type as the input type.
16754 MVT EltVT = VT.getVectorElementType();
16755 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16757 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16758 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16761 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16762 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16763 /// necessary casting for \p Mask when lowering masking intrinsics.
16764 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16765 SDValue PreservedSrc,
16766 const X86Subtarget *Subtarget,
16767 SelectionDAG &DAG) {
16768 EVT VT = Op.getValueType();
16769 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16770 MVT::i1, VT.getVectorNumElements());
16771 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16772 Mask.getValueType().getSizeInBits());
16775 assert(MaskVT.isSimple() && "invalid mask type");
16777 if (isAllOnes(Mask))
16780 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16781 // are extracted by EXTRACT_SUBVECTOR.
16782 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16783 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16784 DAG.getIntPtrConstant(0));
16786 switch (Op.getOpcode()) {
16788 case X86ISD::PCMPEQM:
16789 case X86ISD::PCMPGTM:
16791 case X86ISD::CMPMU:
16792 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16794 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16795 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16796 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16799 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16801 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16802 case Intrinsic::x86_fma_vfmadd_ps:
16803 case Intrinsic::x86_fma_vfmadd_pd:
16804 case Intrinsic::x86_fma_vfmadd_ps_256:
16805 case Intrinsic::x86_fma_vfmadd_pd_256:
16806 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16807 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16808 return X86ISD::FMADD;
16809 case Intrinsic::x86_fma_vfmsub_ps:
16810 case Intrinsic::x86_fma_vfmsub_pd:
16811 case Intrinsic::x86_fma_vfmsub_ps_256:
16812 case Intrinsic::x86_fma_vfmsub_pd_256:
16813 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16814 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16815 return X86ISD::FMSUB;
16816 case Intrinsic::x86_fma_vfnmadd_ps:
16817 case Intrinsic::x86_fma_vfnmadd_pd:
16818 case Intrinsic::x86_fma_vfnmadd_ps_256:
16819 case Intrinsic::x86_fma_vfnmadd_pd_256:
16820 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16821 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16822 return X86ISD::FNMADD;
16823 case Intrinsic::x86_fma_vfnmsub_ps:
16824 case Intrinsic::x86_fma_vfnmsub_pd:
16825 case Intrinsic::x86_fma_vfnmsub_ps_256:
16826 case Intrinsic::x86_fma_vfnmsub_pd_256:
16827 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16828 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16829 return X86ISD::FNMSUB;
16830 case Intrinsic::x86_fma_vfmaddsub_ps:
16831 case Intrinsic::x86_fma_vfmaddsub_pd:
16832 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16833 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16834 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16835 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16836 return X86ISD::FMADDSUB;
16837 case Intrinsic::x86_fma_vfmsubadd_ps:
16838 case Intrinsic::x86_fma_vfmsubadd_pd:
16839 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16840 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16841 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16842 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16843 return X86ISD::FMSUBADD;
16847 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16848 SelectionDAG &DAG) {
16850 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16851 EVT VT = Op.getValueType();
16852 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16854 switch(IntrData->Type) {
16855 case INTR_TYPE_1OP:
16856 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16857 case INTR_TYPE_2OP:
16858 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16860 case INTR_TYPE_3OP:
16861 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16862 Op.getOperand(2), Op.getOperand(3));
16863 case INTR_TYPE_1OP_MASK_RM: {
16864 SDValue Src = Op.getOperand(1);
16865 SDValue Src0 = Op.getOperand(2);
16866 SDValue Mask = Op.getOperand(3);
16867 SDValue RoundingMode = Op.getOperand(4);
16868 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16870 Mask, Src0, Subtarget, DAG);
16874 case CMP_MASK_CC: {
16875 // Comparison intrinsics with masks.
16876 // Example of transformation:
16877 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16878 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16880 // (v8i1 (insert_subvector undef,
16881 // (v2i1 (and (PCMPEQM %a, %b),
16882 // (extract_subvector
16883 // (v8i1 (bitcast %mask)), 0))), 0))))
16884 EVT VT = Op.getOperand(1).getValueType();
16885 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16886 VT.getVectorNumElements());
16887 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16888 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16889 Mask.getValueType().getSizeInBits());
16891 if (IntrData->Type == CMP_MASK_CC) {
16892 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16893 Op.getOperand(2), Op.getOperand(3));
16895 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16896 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16899 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16900 DAG.getTargetConstant(0, MaskVT),
16902 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16903 DAG.getUNDEF(BitcastVT), CmpMask,
16904 DAG.getIntPtrConstant(0));
16905 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16907 case COMI: { // Comparison intrinsics
16908 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16909 SDValue LHS = Op.getOperand(1);
16910 SDValue RHS = Op.getOperand(2);
16911 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16912 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16913 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16914 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16915 DAG.getConstant(X86CC, MVT::i8), Cond);
16916 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16919 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16920 Op.getOperand(1), Op.getOperand(2), DAG);
16922 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16923 Op.getOperand(1), Op.getOperand(2), DAG),
16924 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16931 default: return SDValue(); // Don't custom lower most intrinsics.
16933 // Arithmetic intrinsics.
16934 case Intrinsic::x86_sse2_pmulu_dq:
16935 case Intrinsic::x86_avx2_pmulu_dq:
16936 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16937 Op.getOperand(1), Op.getOperand(2));
16939 case Intrinsic::x86_sse41_pmuldq:
16940 case Intrinsic::x86_avx2_pmul_dq:
16941 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16942 Op.getOperand(1), Op.getOperand(2));
16944 case Intrinsic::x86_sse2_pmulhu_w:
16945 case Intrinsic::x86_avx2_pmulhu_w:
16946 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16947 Op.getOperand(1), Op.getOperand(2));
16949 case Intrinsic::x86_sse2_pmulh_w:
16950 case Intrinsic::x86_avx2_pmulh_w:
16951 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16952 Op.getOperand(1), Op.getOperand(2));
16954 // SSE/SSE2/AVX floating point max/min intrinsics.
16955 case Intrinsic::x86_sse_max_ps:
16956 case Intrinsic::x86_sse2_max_pd:
16957 case Intrinsic::x86_avx_max_ps_256:
16958 case Intrinsic::x86_avx_max_pd_256:
16959 case Intrinsic::x86_sse_min_ps:
16960 case Intrinsic::x86_sse2_min_pd:
16961 case Intrinsic::x86_avx_min_ps_256:
16962 case Intrinsic::x86_avx_min_pd_256: {
16965 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16966 case Intrinsic::x86_sse_max_ps:
16967 case Intrinsic::x86_sse2_max_pd:
16968 case Intrinsic::x86_avx_max_ps_256:
16969 case Intrinsic::x86_avx_max_pd_256:
16970 Opcode = X86ISD::FMAX;
16972 case Intrinsic::x86_sse_min_ps:
16973 case Intrinsic::x86_sse2_min_pd:
16974 case Intrinsic::x86_avx_min_ps_256:
16975 case Intrinsic::x86_avx_min_pd_256:
16976 Opcode = X86ISD::FMIN;
16979 return DAG.getNode(Opcode, dl, Op.getValueType(),
16980 Op.getOperand(1), Op.getOperand(2));
16983 // AVX2 variable shift intrinsics
16984 case Intrinsic::x86_avx2_psllv_d:
16985 case Intrinsic::x86_avx2_psllv_q:
16986 case Intrinsic::x86_avx2_psllv_d_256:
16987 case Intrinsic::x86_avx2_psllv_q_256:
16988 case Intrinsic::x86_avx2_psrlv_d:
16989 case Intrinsic::x86_avx2_psrlv_q:
16990 case Intrinsic::x86_avx2_psrlv_d_256:
16991 case Intrinsic::x86_avx2_psrlv_q_256:
16992 case Intrinsic::x86_avx2_psrav_d:
16993 case Intrinsic::x86_avx2_psrav_d_256: {
16996 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16997 case Intrinsic::x86_avx2_psllv_d:
16998 case Intrinsic::x86_avx2_psllv_q:
16999 case Intrinsic::x86_avx2_psllv_d_256:
17000 case Intrinsic::x86_avx2_psllv_q_256:
17003 case Intrinsic::x86_avx2_psrlv_d:
17004 case Intrinsic::x86_avx2_psrlv_q:
17005 case Intrinsic::x86_avx2_psrlv_d_256:
17006 case Intrinsic::x86_avx2_psrlv_q_256:
17009 case Intrinsic::x86_avx2_psrav_d:
17010 case Intrinsic::x86_avx2_psrav_d_256:
17014 return DAG.getNode(Opcode, dl, Op.getValueType(),
17015 Op.getOperand(1), Op.getOperand(2));
17018 case Intrinsic::x86_sse2_packssdw_128:
17019 case Intrinsic::x86_sse2_packsswb_128:
17020 case Intrinsic::x86_avx2_packssdw:
17021 case Intrinsic::x86_avx2_packsswb:
17022 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
17023 Op.getOperand(1), Op.getOperand(2));
17025 case Intrinsic::x86_sse2_packuswb_128:
17026 case Intrinsic::x86_sse41_packusdw:
17027 case Intrinsic::x86_avx2_packuswb:
17028 case Intrinsic::x86_avx2_packusdw:
17029 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
17030 Op.getOperand(1), Op.getOperand(2));
17032 case Intrinsic::x86_ssse3_pshuf_b_128:
17033 case Intrinsic::x86_avx2_pshuf_b:
17034 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
17035 Op.getOperand(1), Op.getOperand(2));
17037 case Intrinsic::x86_sse2_pshuf_d:
17038 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
17039 Op.getOperand(1), Op.getOperand(2));
17041 case Intrinsic::x86_sse2_pshufl_w:
17042 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
17043 Op.getOperand(1), Op.getOperand(2));
17045 case Intrinsic::x86_sse2_pshufh_w:
17046 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
17047 Op.getOperand(1), Op.getOperand(2));
17049 case Intrinsic::x86_ssse3_psign_b_128:
17050 case Intrinsic::x86_ssse3_psign_w_128:
17051 case Intrinsic::x86_ssse3_psign_d_128:
17052 case Intrinsic::x86_avx2_psign_b:
17053 case Intrinsic::x86_avx2_psign_w:
17054 case Intrinsic::x86_avx2_psign_d:
17055 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
17056 Op.getOperand(1), Op.getOperand(2));
17058 case Intrinsic::x86_avx2_permd:
17059 case Intrinsic::x86_avx2_permps:
17060 // Operands intentionally swapped. Mask is last operand to intrinsic,
17061 // but second operand for node/instruction.
17062 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
17063 Op.getOperand(2), Op.getOperand(1));
17065 case Intrinsic::x86_avx512_mask_valign_q_512:
17066 case Intrinsic::x86_avx512_mask_valign_d_512:
17067 // Vector source operands are swapped.
17068 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17069 Op.getValueType(), Op.getOperand(2),
17072 Op.getOperand(5), Op.getOperand(4),
17075 // ptest and testp intrinsics. The intrinsic these come from are designed to
17076 // return an integer value, not just an instruction so lower it to the ptest
17077 // or testp pattern and a setcc for the result.
17078 case Intrinsic::x86_sse41_ptestz:
17079 case Intrinsic::x86_sse41_ptestc:
17080 case Intrinsic::x86_sse41_ptestnzc:
17081 case Intrinsic::x86_avx_ptestz_256:
17082 case Intrinsic::x86_avx_ptestc_256:
17083 case Intrinsic::x86_avx_ptestnzc_256:
17084 case Intrinsic::x86_avx_vtestz_ps:
17085 case Intrinsic::x86_avx_vtestc_ps:
17086 case Intrinsic::x86_avx_vtestnzc_ps:
17087 case Intrinsic::x86_avx_vtestz_pd:
17088 case Intrinsic::x86_avx_vtestc_pd:
17089 case Intrinsic::x86_avx_vtestnzc_pd:
17090 case Intrinsic::x86_avx_vtestz_ps_256:
17091 case Intrinsic::x86_avx_vtestc_ps_256:
17092 case Intrinsic::x86_avx_vtestnzc_ps_256:
17093 case Intrinsic::x86_avx_vtestz_pd_256:
17094 case Intrinsic::x86_avx_vtestc_pd_256:
17095 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17096 bool IsTestPacked = false;
17099 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17100 case Intrinsic::x86_avx_vtestz_ps:
17101 case Intrinsic::x86_avx_vtestz_pd:
17102 case Intrinsic::x86_avx_vtestz_ps_256:
17103 case Intrinsic::x86_avx_vtestz_pd_256:
17104 IsTestPacked = true; // Fallthrough
17105 case Intrinsic::x86_sse41_ptestz:
17106 case Intrinsic::x86_avx_ptestz_256:
17108 X86CC = X86::COND_E;
17110 case Intrinsic::x86_avx_vtestc_ps:
17111 case Intrinsic::x86_avx_vtestc_pd:
17112 case Intrinsic::x86_avx_vtestc_ps_256:
17113 case Intrinsic::x86_avx_vtestc_pd_256:
17114 IsTestPacked = true; // Fallthrough
17115 case Intrinsic::x86_sse41_ptestc:
17116 case Intrinsic::x86_avx_ptestc_256:
17118 X86CC = X86::COND_B;
17120 case Intrinsic::x86_avx_vtestnzc_ps:
17121 case Intrinsic::x86_avx_vtestnzc_pd:
17122 case Intrinsic::x86_avx_vtestnzc_ps_256:
17123 case Intrinsic::x86_avx_vtestnzc_pd_256:
17124 IsTestPacked = true; // Fallthrough
17125 case Intrinsic::x86_sse41_ptestnzc:
17126 case Intrinsic::x86_avx_ptestnzc_256:
17128 X86CC = X86::COND_A;
17132 SDValue LHS = Op.getOperand(1);
17133 SDValue RHS = Op.getOperand(2);
17134 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17135 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17136 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17137 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17138 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17140 case Intrinsic::x86_avx512_kortestz_w:
17141 case Intrinsic::x86_avx512_kortestc_w: {
17142 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17143 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17144 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17145 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17146 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17147 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17148 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17151 case Intrinsic::x86_sse42_pcmpistria128:
17152 case Intrinsic::x86_sse42_pcmpestria128:
17153 case Intrinsic::x86_sse42_pcmpistric128:
17154 case Intrinsic::x86_sse42_pcmpestric128:
17155 case Intrinsic::x86_sse42_pcmpistrio128:
17156 case Intrinsic::x86_sse42_pcmpestrio128:
17157 case Intrinsic::x86_sse42_pcmpistris128:
17158 case Intrinsic::x86_sse42_pcmpestris128:
17159 case Intrinsic::x86_sse42_pcmpistriz128:
17160 case Intrinsic::x86_sse42_pcmpestriz128: {
17164 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17165 case Intrinsic::x86_sse42_pcmpistria128:
17166 Opcode = X86ISD::PCMPISTRI;
17167 X86CC = X86::COND_A;
17169 case Intrinsic::x86_sse42_pcmpestria128:
17170 Opcode = X86ISD::PCMPESTRI;
17171 X86CC = X86::COND_A;
17173 case Intrinsic::x86_sse42_pcmpistric128:
17174 Opcode = X86ISD::PCMPISTRI;
17175 X86CC = X86::COND_B;
17177 case Intrinsic::x86_sse42_pcmpestric128:
17178 Opcode = X86ISD::PCMPESTRI;
17179 X86CC = X86::COND_B;
17181 case Intrinsic::x86_sse42_pcmpistrio128:
17182 Opcode = X86ISD::PCMPISTRI;
17183 X86CC = X86::COND_O;
17185 case Intrinsic::x86_sse42_pcmpestrio128:
17186 Opcode = X86ISD::PCMPESTRI;
17187 X86CC = X86::COND_O;
17189 case Intrinsic::x86_sse42_pcmpistris128:
17190 Opcode = X86ISD::PCMPISTRI;
17191 X86CC = X86::COND_S;
17193 case Intrinsic::x86_sse42_pcmpestris128:
17194 Opcode = X86ISD::PCMPESTRI;
17195 X86CC = X86::COND_S;
17197 case Intrinsic::x86_sse42_pcmpistriz128:
17198 Opcode = X86ISD::PCMPISTRI;
17199 X86CC = X86::COND_E;
17201 case Intrinsic::x86_sse42_pcmpestriz128:
17202 Opcode = X86ISD::PCMPESTRI;
17203 X86CC = X86::COND_E;
17206 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17207 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17208 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17209 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17210 DAG.getConstant(X86CC, MVT::i8),
17211 SDValue(PCMP.getNode(), 1));
17212 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17215 case Intrinsic::x86_sse42_pcmpistri128:
17216 case Intrinsic::x86_sse42_pcmpestri128: {
17218 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17219 Opcode = X86ISD::PCMPISTRI;
17221 Opcode = X86ISD::PCMPESTRI;
17223 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17224 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17225 return DAG.getNode(Opcode, dl, VTs, NewOps);
17228 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17229 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17230 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17231 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17232 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17233 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17234 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17235 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17236 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17237 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17238 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17239 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17240 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17241 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17242 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17243 dl, Op.getValueType(),
17247 Op.getOperand(4), Op.getOperand(1),
17253 case Intrinsic::x86_fma_vfmadd_ps:
17254 case Intrinsic::x86_fma_vfmadd_pd:
17255 case Intrinsic::x86_fma_vfmsub_ps:
17256 case Intrinsic::x86_fma_vfmsub_pd:
17257 case Intrinsic::x86_fma_vfnmadd_ps:
17258 case Intrinsic::x86_fma_vfnmadd_pd:
17259 case Intrinsic::x86_fma_vfnmsub_ps:
17260 case Intrinsic::x86_fma_vfnmsub_pd:
17261 case Intrinsic::x86_fma_vfmaddsub_ps:
17262 case Intrinsic::x86_fma_vfmaddsub_pd:
17263 case Intrinsic::x86_fma_vfmsubadd_ps:
17264 case Intrinsic::x86_fma_vfmsubadd_pd:
17265 case Intrinsic::x86_fma_vfmadd_ps_256:
17266 case Intrinsic::x86_fma_vfmadd_pd_256:
17267 case Intrinsic::x86_fma_vfmsub_ps_256:
17268 case Intrinsic::x86_fma_vfmsub_pd_256:
17269 case Intrinsic::x86_fma_vfnmadd_ps_256:
17270 case Intrinsic::x86_fma_vfnmadd_pd_256:
17271 case Intrinsic::x86_fma_vfnmsub_ps_256:
17272 case Intrinsic::x86_fma_vfnmsub_pd_256:
17273 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17274 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17275 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17276 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17277 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17278 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17282 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17283 SDValue Src, SDValue Mask, SDValue Base,
17284 SDValue Index, SDValue ScaleOp, SDValue Chain,
17285 const X86Subtarget * Subtarget) {
17287 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17288 assert(C && "Invalid scale type");
17289 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17290 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17291 Index.getSimpleValueType().getVectorNumElements());
17293 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17295 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17297 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17298 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17299 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17300 SDValue Segment = DAG.getRegister(0, MVT::i32);
17301 if (Src.getOpcode() == ISD::UNDEF)
17302 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17303 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17304 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17305 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17306 return DAG.getMergeValues(RetOps, dl);
17309 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17310 SDValue Src, SDValue Mask, SDValue Base,
17311 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17313 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17314 assert(C && "Invalid scale type");
17315 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17316 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17317 SDValue Segment = DAG.getRegister(0, MVT::i32);
17318 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17319 Index.getSimpleValueType().getVectorNumElements());
17321 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17323 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17325 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17326 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17327 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17328 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17329 return SDValue(Res, 1);
17332 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17333 SDValue Mask, SDValue Base, SDValue Index,
17334 SDValue ScaleOp, SDValue Chain) {
17336 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17337 assert(C && "Invalid scale type");
17338 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17339 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17340 SDValue Segment = DAG.getRegister(0, MVT::i32);
17342 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17344 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17346 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17348 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17349 //SDVTList VTs = DAG.getVTList(MVT::Other);
17350 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17351 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17352 return SDValue(Res, 0);
17355 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17356 // read performance monitor counters (x86_rdpmc).
17357 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17358 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17359 SmallVectorImpl<SDValue> &Results) {
17360 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17361 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17364 // The ECX register is used to select the index of the performance counter
17366 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17368 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17370 // Reads the content of a 64-bit performance counter and returns it in the
17371 // registers EDX:EAX.
17372 if (Subtarget->is64Bit()) {
17373 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17374 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17377 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17378 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17381 Chain = HI.getValue(1);
17383 if (Subtarget->is64Bit()) {
17384 // The EAX register is loaded with the low-order 32 bits. The EDX register
17385 // is loaded with the supported high-order bits of the counter.
17386 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17387 DAG.getConstant(32, MVT::i8));
17388 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17389 Results.push_back(Chain);
17393 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17394 SDValue Ops[] = { LO, HI };
17395 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17396 Results.push_back(Pair);
17397 Results.push_back(Chain);
17400 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17401 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17402 // also used to custom lower READCYCLECOUNTER nodes.
17403 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17404 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17405 SmallVectorImpl<SDValue> &Results) {
17406 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17407 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17410 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17411 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17412 // and the EAX register is loaded with the low-order 32 bits.
17413 if (Subtarget->is64Bit()) {
17414 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17415 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17418 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17419 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17422 SDValue Chain = HI.getValue(1);
17424 if (Opcode == X86ISD::RDTSCP_DAG) {
17425 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17427 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17428 // the ECX register. Add 'ecx' explicitly to the chain.
17429 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17431 // Explicitly store the content of ECX at the location passed in input
17432 // to the 'rdtscp' intrinsic.
17433 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17434 MachinePointerInfo(), false, false, 0);
17437 if (Subtarget->is64Bit()) {
17438 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17439 // the EAX register is loaded with the low-order 32 bits.
17440 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17441 DAG.getConstant(32, MVT::i8));
17442 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17443 Results.push_back(Chain);
17447 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17448 SDValue Ops[] = { LO, HI };
17449 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17450 Results.push_back(Pair);
17451 Results.push_back(Chain);
17454 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17455 SelectionDAG &DAG) {
17456 SmallVector<SDValue, 2> Results;
17458 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17460 return DAG.getMergeValues(Results, DL);
17464 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17465 SelectionDAG &DAG) {
17466 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17468 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17473 switch(IntrData->Type) {
17475 llvm_unreachable("Unknown Intrinsic Type");
17479 // Emit the node with the right value type.
17480 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17481 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17483 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17484 // Otherwise return the value from Rand, which is always 0, casted to i32.
17485 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17486 DAG.getConstant(1, Op->getValueType(1)),
17487 DAG.getConstant(X86::COND_B, MVT::i32),
17488 SDValue(Result.getNode(), 1) };
17489 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17490 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17493 // Return { result, isValid, chain }.
17494 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17495 SDValue(Result.getNode(), 2));
17498 //gather(v1, mask, index, base, scale);
17499 SDValue Chain = Op.getOperand(0);
17500 SDValue Src = Op.getOperand(2);
17501 SDValue Base = Op.getOperand(3);
17502 SDValue Index = Op.getOperand(4);
17503 SDValue Mask = Op.getOperand(5);
17504 SDValue Scale = Op.getOperand(6);
17505 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17509 //scatter(base, mask, index, v1, scale);
17510 SDValue Chain = Op.getOperand(0);
17511 SDValue Base = Op.getOperand(2);
17512 SDValue Mask = Op.getOperand(3);
17513 SDValue Index = Op.getOperand(4);
17514 SDValue Src = Op.getOperand(5);
17515 SDValue Scale = Op.getOperand(6);
17516 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17519 SDValue Hint = Op.getOperand(6);
17521 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17522 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17523 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17524 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17525 SDValue Chain = Op.getOperand(0);
17526 SDValue Mask = Op.getOperand(2);
17527 SDValue Index = Op.getOperand(3);
17528 SDValue Base = Op.getOperand(4);
17529 SDValue Scale = Op.getOperand(5);
17530 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17532 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17534 SmallVector<SDValue, 2> Results;
17535 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17536 return DAG.getMergeValues(Results, dl);
17538 // Read Performance Monitoring Counters.
17540 SmallVector<SDValue, 2> Results;
17541 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17542 return DAG.getMergeValues(Results, dl);
17544 // XTEST intrinsics.
17546 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17547 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17548 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17549 DAG.getConstant(X86::COND_NE, MVT::i8),
17551 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17552 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17553 Ret, SDValue(InTrans.getNode(), 1));
17557 SmallVector<SDValue, 2> Results;
17558 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17559 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17560 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17561 DAG.getConstant(-1, MVT::i8));
17562 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17563 Op.getOperand(4), GenCF.getValue(1));
17564 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17565 Op.getOperand(5), MachinePointerInfo(),
17567 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17568 DAG.getConstant(X86::COND_B, MVT::i8),
17570 Results.push_back(SetCC);
17571 Results.push_back(Store);
17572 return DAG.getMergeValues(Results, dl);
17577 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17578 SelectionDAG &DAG) const {
17579 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17580 MFI->setReturnAddressIsTaken(true);
17582 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17585 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17587 EVT PtrVT = getPointerTy();
17590 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17591 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17592 DAG.getSubtarget().getRegisterInfo());
17593 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17594 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17595 DAG.getNode(ISD::ADD, dl, PtrVT,
17596 FrameAddr, Offset),
17597 MachinePointerInfo(), false, false, false, 0);
17600 // Just load the return address.
17601 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17602 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17603 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17606 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17607 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17608 MFI->setFrameAddressIsTaken(true);
17610 EVT VT = Op.getValueType();
17611 SDLoc dl(Op); // FIXME probably not meaningful
17612 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17613 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17614 DAG.getSubtarget().getRegisterInfo());
17615 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17616 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17617 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17618 "Invalid Frame Register!");
17619 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17621 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17622 MachinePointerInfo(),
17623 false, false, false, 0);
17627 // FIXME? Maybe this could be a TableGen attribute on some registers and
17628 // this table could be generated automatically from RegInfo.
17629 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17631 unsigned Reg = StringSwitch<unsigned>(RegName)
17632 .Case("esp", X86::ESP)
17633 .Case("rsp", X86::RSP)
17637 report_fatal_error("Invalid register name global variable");
17640 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17641 SelectionDAG &DAG) const {
17642 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17643 DAG.getSubtarget().getRegisterInfo());
17644 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17647 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17648 SDValue Chain = Op.getOperand(0);
17649 SDValue Offset = Op.getOperand(1);
17650 SDValue Handler = Op.getOperand(2);
17653 EVT PtrVT = getPointerTy();
17654 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17655 DAG.getSubtarget().getRegisterInfo());
17656 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17657 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17658 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17659 "Invalid Frame Register!");
17660 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17661 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17663 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17664 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17665 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17666 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17668 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17670 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17671 DAG.getRegister(StoreAddrReg, PtrVT));
17674 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17675 SelectionDAG &DAG) const {
17677 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17678 DAG.getVTList(MVT::i32, MVT::Other),
17679 Op.getOperand(0), Op.getOperand(1));
17682 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17683 SelectionDAG &DAG) const {
17685 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17686 Op.getOperand(0), Op.getOperand(1));
17689 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17690 return Op.getOperand(0);
17693 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17694 SelectionDAG &DAG) const {
17695 SDValue Root = Op.getOperand(0);
17696 SDValue Trmp = Op.getOperand(1); // trampoline
17697 SDValue FPtr = Op.getOperand(2); // nested function
17698 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17701 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17702 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17704 if (Subtarget->is64Bit()) {
17705 SDValue OutChains[6];
17707 // Large code-model.
17708 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17709 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17711 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17712 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17714 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17716 // Load the pointer to the nested function into R11.
17717 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17718 SDValue Addr = Trmp;
17719 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17720 Addr, MachinePointerInfo(TrmpAddr),
17723 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17724 DAG.getConstant(2, MVT::i64));
17725 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17726 MachinePointerInfo(TrmpAddr, 2),
17729 // Load the 'nest' parameter value into R10.
17730 // R10 is specified in X86CallingConv.td
17731 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17732 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17733 DAG.getConstant(10, MVT::i64));
17734 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17735 Addr, MachinePointerInfo(TrmpAddr, 10),
17738 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17739 DAG.getConstant(12, MVT::i64));
17740 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17741 MachinePointerInfo(TrmpAddr, 12),
17744 // Jump to the nested function.
17745 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17746 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17747 DAG.getConstant(20, MVT::i64));
17748 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17749 Addr, MachinePointerInfo(TrmpAddr, 20),
17752 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17753 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17754 DAG.getConstant(22, MVT::i64));
17755 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17756 MachinePointerInfo(TrmpAddr, 22),
17759 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17761 const Function *Func =
17762 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17763 CallingConv::ID CC = Func->getCallingConv();
17768 llvm_unreachable("Unsupported calling convention");
17769 case CallingConv::C:
17770 case CallingConv::X86_StdCall: {
17771 // Pass 'nest' parameter in ECX.
17772 // Must be kept in sync with X86CallingConv.td
17773 NestReg = X86::ECX;
17775 // Check that ECX wasn't needed by an 'inreg' parameter.
17776 FunctionType *FTy = Func->getFunctionType();
17777 const AttributeSet &Attrs = Func->getAttributes();
17779 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17780 unsigned InRegCount = 0;
17783 for (FunctionType::param_iterator I = FTy->param_begin(),
17784 E = FTy->param_end(); I != E; ++I, ++Idx)
17785 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17786 // FIXME: should only count parameters that are lowered to integers.
17787 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17789 if (InRegCount > 2) {
17790 report_fatal_error("Nest register in use - reduce number of inreg"
17796 case CallingConv::X86_FastCall:
17797 case CallingConv::X86_ThisCall:
17798 case CallingConv::Fast:
17799 // Pass 'nest' parameter in EAX.
17800 // Must be kept in sync with X86CallingConv.td
17801 NestReg = X86::EAX;
17805 SDValue OutChains[4];
17806 SDValue Addr, Disp;
17808 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17809 DAG.getConstant(10, MVT::i32));
17810 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17812 // This is storing the opcode for MOV32ri.
17813 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17814 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17815 OutChains[0] = DAG.getStore(Root, dl,
17816 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17817 Trmp, MachinePointerInfo(TrmpAddr),
17820 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17821 DAG.getConstant(1, MVT::i32));
17822 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17823 MachinePointerInfo(TrmpAddr, 1),
17826 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17827 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17828 DAG.getConstant(5, MVT::i32));
17829 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17830 MachinePointerInfo(TrmpAddr, 5),
17833 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17834 DAG.getConstant(6, MVT::i32));
17835 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17836 MachinePointerInfo(TrmpAddr, 6),
17839 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17843 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17844 SelectionDAG &DAG) const {
17846 The rounding mode is in bits 11:10 of FPSR, and has the following
17848 00 Round to nearest
17853 FLT_ROUNDS, on the other hand, expects the following:
17860 To perform the conversion, we do:
17861 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17864 MachineFunction &MF = DAG.getMachineFunction();
17865 const TargetMachine &TM = MF.getTarget();
17866 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17867 unsigned StackAlignment = TFI.getStackAlignment();
17868 MVT VT = Op.getSimpleValueType();
17871 // Save FP Control Word to stack slot
17872 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17873 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17875 MachineMemOperand *MMO =
17876 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17877 MachineMemOperand::MOStore, 2, 2);
17879 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17880 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17881 DAG.getVTList(MVT::Other),
17882 Ops, MVT::i16, MMO);
17884 // Load FP Control Word from stack slot
17885 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17886 MachinePointerInfo(), false, false, false, 0);
17888 // Transform as necessary
17890 DAG.getNode(ISD::SRL, DL, MVT::i16,
17891 DAG.getNode(ISD::AND, DL, MVT::i16,
17892 CWD, DAG.getConstant(0x800, MVT::i16)),
17893 DAG.getConstant(11, MVT::i8));
17895 DAG.getNode(ISD::SRL, DL, MVT::i16,
17896 DAG.getNode(ISD::AND, DL, MVT::i16,
17897 CWD, DAG.getConstant(0x400, MVT::i16)),
17898 DAG.getConstant(9, MVT::i8));
17901 DAG.getNode(ISD::AND, DL, MVT::i16,
17902 DAG.getNode(ISD::ADD, DL, MVT::i16,
17903 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17904 DAG.getConstant(1, MVT::i16)),
17905 DAG.getConstant(3, MVT::i16));
17907 return DAG.getNode((VT.getSizeInBits() < 16 ?
17908 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17911 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17912 MVT VT = Op.getSimpleValueType();
17914 unsigned NumBits = VT.getSizeInBits();
17917 Op = Op.getOperand(0);
17918 if (VT == MVT::i8) {
17919 // Zero extend to i32 since there is not an i8 bsr.
17921 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17924 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17925 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17926 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17928 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17931 DAG.getConstant(NumBits+NumBits-1, OpVT),
17932 DAG.getConstant(X86::COND_E, MVT::i8),
17935 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17937 // Finally xor with NumBits-1.
17938 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17941 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17945 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17946 MVT VT = Op.getSimpleValueType();
17948 unsigned NumBits = VT.getSizeInBits();
17951 Op = Op.getOperand(0);
17952 if (VT == MVT::i8) {
17953 // Zero extend to i32 since there is not an i8 bsr.
17955 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17958 // Issue a bsr (scan bits in reverse).
17959 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17960 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17962 // And xor with NumBits-1.
17963 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17966 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17970 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17971 MVT VT = Op.getSimpleValueType();
17972 unsigned NumBits = VT.getSizeInBits();
17974 Op = Op.getOperand(0);
17976 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17977 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17978 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17980 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17983 DAG.getConstant(NumBits, VT),
17984 DAG.getConstant(X86::COND_E, MVT::i8),
17987 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17990 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17991 // ones, and then concatenate the result back.
17992 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17993 MVT VT = Op.getSimpleValueType();
17995 assert(VT.is256BitVector() && VT.isInteger() &&
17996 "Unsupported value type for operation");
17998 unsigned NumElems = VT.getVectorNumElements();
18001 // Extract the LHS vectors
18002 SDValue LHS = Op.getOperand(0);
18003 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18004 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18006 // Extract the RHS vectors
18007 SDValue RHS = Op.getOperand(1);
18008 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18009 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18011 MVT EltVT = VT.getVectorElementType();
18012 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18014 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18015 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18016 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18019 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18020 assert(Op.getSimpleValueType().is256BitVector() &&
18021 Op.getSimpleValueType().isInteger() &&
18022 "Only handle AVX 256-bit vector integer operation");
18023 return Lower256IntArith(Op, DAG);
18026 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18027 assert(Op.getSimpleValueType().is256BitVector() &&
18028 Op.getSimpleValueType().isInteger() &&
18029 "Only handle AVX 256-bit vector integer operation");
18030 return Lower256IntArith(Op, DAG);
18033 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18034 SelectionDAG &DAG) {
18036 MVT VT = Op.getSimpleValueType();
18038 // Decompose 256-bit ops into smaller 128-bit ops.
18039 if (VT.is256BitVector() && !Subtarget->hasInt256())
18040 return Lower256IntArith(Op, DAG);
18042 SDValue A = Op.getOperand(0);
18043 SDValue B = Op.getOperand(1);
18045 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18046 if (VT == MVT::v4i32) {
18047 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18048 "Should not custom lower when pmuldq is available!");
18050 // Extract the odd parts.
18051 static const int UnpackMask[] = { 1, -1, 3, -1 };
18052 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18053 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18055 // Multiply the even parts.
18056 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18057 // Now multiply odd parts.
18058 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18060 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18061 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18063 // Merge the two vectors back together with a shuffle. This expands into 2
18065 static const int ShufMask[] = { 0, 4, 2, 6 };
18066 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18069 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18070 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18072 // Ahi = psrlqi(a, 32);
18073 // Bhi = psrlqi(b, 32);
18075 // AloBlo = pmuludq(a, b);
18076 // AloBhi = pmuludq(a, Bhi);
18077 // AhiBlo = pmuludq(Ahi, b);
18079 // AloBhi = psllqi(AloBhi, 32);
18080 // AhiBlo = psllqi(AhiBlo, 32);
18081 // return AloBlo + AloBhi + AhiBlo;
18083 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18084 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18086 // Bit cast to 32-bit vectors for MULUDQ
18087 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18088 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18089 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18090 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18091 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18092 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18094 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18095 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18096 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18098 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18099 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18101 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18102 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18105 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18106 assert(Subtarget->isTargetWin64() && "Unexpected target");
18107 EVT VT = Op.getValueType();
18108 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18109 "Unexpected return type for lowering");
18113 switch (Op->getOpcode()) {
18114 default: llvm_unreachable("Unexpected request for libcall!");
18115 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18116 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18117 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18118 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18119 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18120 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18124 SDValue InChain = DAG.getEntryNode();
18126 TargetLowering::ArgListTy Args;
18127 TargetLowering::ArgListEntry Entry;
18128 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18129 EVT ArgVT = Op->getOperand(i).getValueType();
18130 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18131 "Unexpected argument type for lowering");
18132 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18133 Entry.Node = StackPtr;
18134 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18136 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18137 Entry.Ty = PointerType::get(ArgTy,0);
18138 Entry.isSExt = false;
18139 Entry.isZExt = false;
18140 Args.push_back(Entry);
18143 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18146 TargetLowering::CallLoweringInfo CLI(DAG);
18147 CLI.setDebugLoc(dl).setChain(InChain)
18148 .setCallee(getLibcallCallingConv(LC),
18149 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18150 Callee, std::move(Args), 0)
18151 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18153 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18154 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18157 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18158 SelectionDAG &DAG) {
18159 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18160 EVT VT = Op0.getValueType();
18163 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18164 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18166 // PMULxD operations multiply each even value (starting at 0) of LHS with
18167 // the related value of RHS and produce a widen result.
18168 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18169 // => <2 x i64> <ae|cg>
18171 // In other word, to have all the results, we need to perform two PMULxD:
18172 // 1. one with the even values.
18173 // 2. one with the odd values.
18174 // To achieve #2, with need to place the odd values at an even position.
18176 // Place the odd value at an even position (basically, shift all values 1
18177 // step to the left):
18178 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18179 // <a|b|c|d> => <b|undef|d|undef>
18180 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18181 // <e|f|g|h> => <f|undef|h|undef>
18182 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18184 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18186 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18187 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18189 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18190 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18191 // => <2 x i64> <ae|cg>
18192 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18193 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18194 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18195 // => <2 x i64> <bf|dh>
18196 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18197 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18199 // Shuffle it back into the right order.
18200 SDValue Highs, Lows;
18201 if (VT == MVT::v8i32) {
18202 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18203 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18204 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18205 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18207 const int HighMask[] = {1, 5, 3, 7};
18208 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18209 const int LowMask[] = {0, 4, 2, 6};
18210 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18213 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18214 // unsigned multiply.
18215 if (IsSigned && !Subtarget->hasSSE41()) {
18217 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18218 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18219 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18220 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18221 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18223 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18224 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18227 // The first result of MUL_LOHI is actually the low value, followed by the
18229 SDValue Ops[] = {Lows, Highs};
18230 return DAG.getMergeValues(Ops, dl);
18233 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18234 const X86Subtarget *Subtarget) {
18235 MVT VT = Op.getSimpleValueType();
18237 SDValue R = Op.getOperand(0);
18238 SDValue Amt = Op.getOperand(1);
18240 // Optimize shl/srl/sra with constant shift amount.
18241 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18242 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18243 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18245 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18246 (Subtarget->hasInt256() &&
18247 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18248 (Subtarget->hasAVX512() &&
18249 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18250 if (Op.getOpcode() == ISD::SHL)
18251 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18253 if (Op.getOpcode() == ISD::SRL)
18254 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18256 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18257 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18261 if (VT == MVT::v16i8) {
18262 if (Op.getOpcode() == ISD::SHL) {
18263 // Make a large shift.
18264 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18265 MVT::v8i16, R, ShiftAmt,
18267 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18268 // Zero out the rightmost bits.
18269 SmallVector<SDValue, 16> V(16,
18270 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18272 return DAG.getNode(ISD::AND, dl, VT, SHL,
18273 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18275 if (Op.getOpcode() == ISD::SRL) {
18276 // Make a large shift.
18277 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18278 MVT::v8i16, R, ShiftAmt,
18280 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18281 // Zero out the leftmost bits.
18282 SmallVector<SDValue, 16> V(16,
18283 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18285 return DAG.getNode(ISD::AND, dl, VT, SRL,
18286 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18288 if (Op.getOpcode() == ISD::SRA) {
18289 if (ShiftAmt == 7) {
18290 // R s>> 7 === R s< 0
18291 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18292 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18295 // R s>> a === ((R u>> a) ^ m) - m
18296 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18297 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18299 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18300 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18301 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18304 llvm_unreachable("Unknown shift opcode.");
18307 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18308 if (Op.getOpcode() == ISD::SHL) {
18309 // Make a large shift.
18310 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18311 MVT::v16i16, R, ShiftAmt,
18313 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18314 // Zero out the rightmost bits.
18315 SmallVector<SDValue, 32> V(32,
18316 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18318 return DAG.getNode(ISD::AND, dl, VT, SHL,
18319 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18321 if (Op.getOpcode() == ISD::SRL) {
18322 // Make a large shift.
18323 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18324 MVT::v16i16, R, ShiftAmt,
18326 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18327 // Zero out the leftmost bits.
18328 SmallVector<SDValue, 32> V(32,
18329 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18331 return DAG.getNode(ISD::AND, dl, VT, SRL,
18332 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18334 if (Op.getOpcode() == ISD::SRA) {
18335 if (ShiftAmt == 7) {
18336 // R s>> 7 === R s< 0
18337 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18338 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18341 // R s>> a === ((R u>> a) ^ m) - m
18342 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18343 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18345 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18346 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18347 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18350 llvm_unreachable("Unknown shift opcode.");
18355 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18356 if (!Subtarget->is64Bit() &&
18357 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18358 Amt.getOpcode() == ISD::BITCAST &&
18359 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18360 Amt = Amt.getOperand(0);
18361 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18362 VT.getVectorNumElements();
18363 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18364 uint64_t ShiftAmt = 0;
18365 for (unsigned i = 0; i != Ratio; ++i) {
18366 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18370 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18372 // Check remaining shift amounts.
18373 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18374 uint64_t ShAmt = 0;
18375 for (unsigned j = 0; j != Ratio; ++j) {
18376 ConstantSDNode *C =
18377 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18381 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18383 if (ShAmt != ShiftAmt)
18386 switch (Op.getOpcode()) {
18388 llvm_unreachable("Unknown shift opcode!");
18390 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18393 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18396 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18404 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18405 const X86Subtarget* Subtarget) {
18406 MVT VT = Op.getSimpleValueType();
18408 SDValue R = Op.getOperand(0);
18409 SDValue Amt = Op.getOperand(1);
18411 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18412 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18413 (Subtarget->hasInt256() &&
18414 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18415 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18416 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18418 EVT EltVT = VT.getVectorElementType();
18420 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18421 unsigned NumElts = VT.getVectorNumElements();
18423 for (i = 0; i != NumElts; ++i) {
18424 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18428 for (j = i; j != NumElts; ++j) {
18429 SDValue Arg = Amt.getOperand(j);
18430 if (Arg.getOpcode() == ISD::UNDEF) continue;
18431 if (Arg != Amt.getOperand(i))
18434 if (i != NumElts && j == NumElts)
18435 BaseShAmt = Amt.getOperand(i);
18437 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18438 Amt = Amt.getOperand(0);
18439 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18440 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18441 SDValue InVec = Amt.getOperand(0);
18442 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18443 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18445 for (; i != NumElts; ++i) {
18446 SDValue Arg = InVec.getOperand(i);
18447 if (Arg.getOpcode() == ISD::UNDEF) continue;
18451 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18452 if (ConstantSDNode *C =
18453 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18454 unsigned SplatIdx =
18455 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18456 if (C->getZExtValue() == SplatIdx)
18457 BaseShAmt = InVec.getOperand(1);
18460 if (!BaseShAmt.getNode())
18461 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18462 DAG.getIntPtrConstant(0));
18466 if (BaseShAmt.getNode()) {
18467 if (EltVT.bitsGT(MVT::i32))
18468 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18469 else if (EltVT.bitsLT(MVT::i32))
18470 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18472 switch (Op.getOpcode()) {
18474 llvm_unreachable("Unknown shift opcode!");
18476 switch (VT.SimpleTy) {
18477 default: return SDValue();
18486 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18489 switch (VT.SimpleTy) {
18490 default: return SDValue();
18497 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18500 switch (VT.SimpleTy) {
18501 default: return SDValue();
18510 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18516 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18517 if (!Subtarget->is64Bit() &&
18518 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18519 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18520 Amt.getOpcode() == ISD::BITCAST &&
18521 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18522 Amt = Amt.getOperand(0);
18523 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18524 VT.getVectorNumElements();
18525 std::vector<SDValue> Vals(Ratio);
18526 for (unsigned i = 0; i != Ratio; ++i)
18527 Vals[i] = Amt.getOperand(i);
18528 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18529 for (unsigned j = 0; j != Ratio; ++j)
18530 if (Vals[j] != Amt.getOperand(i + j))
18533 switch (Op.getOpcode()) {
18535 llvm_unreachable("Unknown shift opcode!");
18537 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18539 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18541 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18548 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18549 SelectionDAG &DAG) {
18550 MVT VT = Op.getSimpleValueType();
18552 SDValue R = Op.getOperand(0);
18553 SDValue Amt = Op.getOperand(1);
18556 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18557 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18559 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18563 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18567 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18569 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18570 if (Subtarget->hasInt256()) {
18571 if (Op.getOpcode() == ISD::SRL &&
18572 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18573 VT == MVT::v4i64 || VT == MVT::v8i32))
18575 if (Op.getOpcode() == ISD::SHL &&
18576 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18577 VT == MVT::v4i64 || VT == MVT::v8i32))
18579 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18583 // If possible, lower this packed shift into a vector multiply instead of
18584 // expanding it into a sequence of scalar shifts.
18585 // Do this only if the vector shift count is a constant build_vector.
18586 if (Op.getOpcode() == ISD::SHL &&
18587 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18588 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18589 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18590 SmallVector<SDValue, 8> Elts;
18591 EVT SVT = VT.getScalarType();
18592 unsigned SVTBits = SVT.getSizeInBits();
18593 const APInt &One = APInt(SVTBits, 1);
18594 unsigned NumElems = VT.getVectorNumElements();
18596 for (unsigned i=0; i !=NumElems; ++i) {
18597 SDValue Op = Amt->getOperand(i);
18598 if (Op->getOpcode() == ISD::UNDEF) {
18599 Elts.push_back(Op);
18603 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18604 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18605 uint64_t ShAmt = C.getZExtValue();
18606 if (ShAmt >= SVTBits) {
18607 Elts.push_back(DAG.getUNDEF(SVT));
18610 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18612 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18613 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18616 // Lower SHL with variable shift amount.
18617 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18618 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18620 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18621 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18622 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18623 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18626 // If possible, lower this shift as a sequence of two shifts by
18627 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18629 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18631 // Could be rewritten as:
18632 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18634 // The advantage is that the two shifts from the example would be
18635 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18636 // the vector shift into four scalar shifts plus four pairs of vector
18638 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18639 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18640 unsigned TargetOpcode = X86ISD::MOVSS;
18641 bool CanBeSimplified;
18642 // The splat value for the first packed shift (the 'X' from the example).
18643 SDValue Amt1 = Amt->getOperand(0);
18644 // The splat value for the second packed shift (the 'Y' from the example).
18645 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18646 Amt->getOperand(2);
18648 // See if it is possible to replace this node with a sequence of
18649 // two shifts followed by a MOVSS/MOVSD
18650 if (VT == MVT::v4i32) {
18651 // Check if it is legal to use a MOVSS.
18652 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18653 Amt2 == Amt->getOperand(3);
18654 if (!CanBeSimplified) {
18655 // Otherwise, check if we can still simplify this node using a MOVSD.
18656 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18657 Amt->getOperand(2) == Amt->getOperand(3);
18658 TargetOpcode = X86ISD::MOVSD;
18659 Amt2 = Amt->getOperand(2);
18662 // Do similar checks for the case where the machine value type
18664 CanBeSimplified = Amt1 == Amt->getOperand(1);
18665 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18666 CanBeSimplified = Amt2 == Amt->getOperand(i);
18668 if (!CanBeSimplified) {
18669 TargetOpcode = X86ISD::MOVSD;
18670 CanBeSimplified = true;
18671 Amt2 = Amt->getOperand(4);
18672 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18673 CanBeSimplified = Amt1 == Amt->getOperand(i);
18674 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18675 CanBeSimplified = Amt2 == Amt->getOperand(j);
18679 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18680 isa<ConstantSDNode>(Amt2)) {
18681 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18682 EVT CastVT = MVT::v4i32;
18684 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18685 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18687 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18688 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18689 if (TargetOpcode == X86ISD::MOVSD)
18690 CastVT = MVT::v2i64;
18691 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18692 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18693 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18695 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18699 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18700 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18703 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18704 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18706 // Turn 'a' into a mask suitable for VSELECT
18707 SDValue VSelM = DAG.getConstant(0x80, VT);
18708 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18709 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18711 SDValue CM1 = DAG.getConstant(0x0f, VT);
18712 SDValue CM2 = DAG.getConstant(0x3f, VT);
18714 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18715 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18716 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18717 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18718 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18721 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18722 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18723 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18725 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18726 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18727 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18728 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18729 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18732 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18733 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18734 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18736 // return VSELECT(r, r+r, a);
18737 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18738 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18742 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18743 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18744 // solution better.
18745 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18746 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18748 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18749 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18750 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18751 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18752 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18755 // Decompose 256-bit shifts into smaller 128-bit shifts.
18756 if (VT.is256BitVector()) {
18757 unsigned NumElems = VT.getVectorNumElements();
18758 MVT EltVT = VT.getVectorElementType();
18759 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18761 // Extract the two vectors
18762 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18763 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18765 // Recreate the shift amount vectors
18766 SDValue Amt1, Amt2;
18767 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18768 // Constant shift amount
18769 SmallVector<SDValue, 4> Amt1Csts;
18770 SmallVector<SDValue, 4> Amt2Csts;
18771 for (unsigned i = 0; i != NumElems/2; ++i)
18772 Amt1Csts.push_back(Amt->getOperand(i));
18773 for (unsigned i = NumElems/2; i != NumElems; ++i)
18774 Amt2Csts.push_back(Amt->getOperand(i));
18776 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18777 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18779 // Variable shift amount
18780 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18781 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18784 // Issue new vector shifts for the smaller types
18785 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18786 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18788 // Concatenate the result back
18789 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18795 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18796 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18797 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18798 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18799 // has only one use.
18800 SDNode *N = Op.getNode();
18801 SDValue LHS = N->getOperand(0);
18802 SDValue RHS = N->getOperand(1);
18803 unsigned BaseOp = 0;
18806 switch (Op.getOpcode()) {
18807 default: llvm_unreachable("Unknown ovf instruction!");
18809 // A subtract of one will be selected as a INC. Note that INC doesn't
18810 // set CF, so we can't do this for UADDO.
18811 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18813 BaseOp = X86ISD::INC;
18814 Cond = X86::COND_O;
18817 BaseOp = X86ISD::ADD;
18818 Cond = X86::COND_O;
18821 BaseOp = X86ISD::ADD;
18822 Cond = X86::COND_B;
18825 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18826 // set CF, so we can't do this for USUBO.
18827 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18829 BaseOp = X86ISD::DEC;
18830 Cond = X86::COND_O;
18833 BaseOp = X86ISD::SUB;
18834 Cond = X86::COND_O;
18837 BaseOp = X86ISD::SUB;
18838 Cond = X86::COND_B;
18841 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18842 Cond = X86::COND_O;
18844 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18845 if (N->getValueType(0) == MVT::i8) {
18846 BaseOp = X86ISD::UMUL8;
18847 Cond = X86::COND_O;
18850 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18852 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18855 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18856 DAG.getConstant(X86::COND_O, MVT::i32),
18857 SDValue(Sum.getNode(), 2));
18859 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18863 // Also sets EFLAGS.
18864 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18865 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18868 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18869 DAG.getConstant(Cond, MVT::i32),
18870 SDValue(Sum.getNode(), 1));
18872 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18875 // Sign extension of the low part of vector elements. This may be used either
18876 // when sign extend instructions are not available or if the vector element
18877 // sizes already match the sign-extended size. If the vector elements are in
18878 // their pre-extended size and sign extend instructions are available, that will
18879 // be handled by LowerSIGN_EXTEND.
18880 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18881 SelectionDAG &DAG) const {
18883 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18884 MVT VT = Op.getSimpleValueType();
18886 if (!Subtarget->hasSSE2() || !VT.isVector())
18889 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18890 ExtraVT.getScalarType().getSizeInBits();
18892 switch (VT.SimpleTy) {
18893 default: return SDValue();
18896 if (!Subtarget->hasFp256())
18898 if (!Subtarget->hasInt256()) {
18899 // needs to be split
18900 unsigned NumElems = VT.getVectorNumElements();
18902 // Extract the LHS vectors
18903 SDValue LHS = Op.getOperand(0);
18904 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18905 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18907 MVT EltVT = VT.getVectorElementType();
18908 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18910 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18911 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18912 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18914 SDValue Extra = DAG.getValueType(ExtraVT);
18916 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18917 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18919 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18924 SDValue Op0 = Op.getOperand(0);
18926 // This is a sign extension of some low part of vector elements without
18927 // changing the size of the vector elements themselves:
18928 // Shift-Left + Shift-Right-Algebraic.
18929 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18931 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18937 /// Returns true if the operand type is exactly twice the native width, and
18938 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18939 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18940 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18941 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18942 const X86Subtarget &Subtarget =
18943 getTargetMachine().getSubtarget<X86Subtarget>();
18944 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18947 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18948 else if (OpWidth == 128)
18949 return Subtarget.hasCmpxchg16b();
18954 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18955 return needsCmpXchgNb(SI->getValueOperand()->getType());
18958 // Note: this turns large loads into lock cmpxchg8b/16b.
18959 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18960 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18961 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18962 return needsCmpXchgNb(PTy->getElementType());
18965 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18966 const X86Subtarget &Subtarget =
18967 getTargetMachine().getSubtarget<X86Subtarget>();
18968 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18969 const Type *MemType = AI->getType();
18971 // If the operand is too big, we must see if cmpxchg8/16b is available
18972 // and default to library calls otherwise.
18973 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18974 return needsCmpXchgNb(MemType);
18976 AtomicRMWInst::BinOp Op = AI->getOperation();
18979 llvm_unreachable("Unknown atomic operation");
18980 case AtomicRMWInst::Xchg:
18981 case AtomicRMWInst::Add:
18982 case AtomicRMWInst::Sub:
18983 // It's better to use xadd, xsub or xchg for these in all cases.
18985 case AtomicRMWInst::Or:
18986 case AtomicRMWInst::And:
18987 case AtomicRMWInst::Xor:
18988 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18989 // prefix to a normal instruction for these operations.
18990 return !AI->use_empty();
18991 case AtomicRMWInst::Nand:
18992 case AtomicRMWInst::Max:
18993 case AtomicRMWInst::Min:
18994 case AtomicRMWInst::UMax:
18995 case AtomicRMWInst::UMin:
18996 // These always require a non-trivial set of data operations on x86. We must
18997 // use a cmpxchg loop.
19002 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19003 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19004 // no-sse2). There isn't any reason to disable it if the target processor
19006 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19010 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19011 const X86Subtarget &Subtarget =
19012 getTargetMachine().getSubtarget<X86Subtarget>();
19013 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19014 const Type *MemType = AI->getType();
19015 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19016 // there is no benefit in turning such RMWs into loads, and it is actually
19017 // harmful as it introduces a mfence.
19018 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19021 auto Builder = IRBuilder<>(AI);
19022 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19023 auto SynchScope = AI->getSynchScope();
19024 // We must restrict the ordering to avoid generating loads with Release or
19025 // ReleaseAcquire orderings.
19026 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19027 auto Ptr = AI->getPointerOperand();
19029 // Before the load we need a fence. Here is an example lifted from
19030 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19033 // x.store(1, relaxed);
19034 // r1 = y.fetch_add(0, release);
19036 // y.fetch_add(42, acquire);
19037 // r2 = x.load(relaxed);
19038 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19039 // lowered to just a load without a fence. A mfence flushes the store buffer,
19040 // making the optimization clearly correct.
19041 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19042 // otherwise, we might be able to be more agressive on relaxed idempotent
19043 // rmw. In practice, they do not look useful, so we don't try to be
19044 // especially clever.
19045 if (SynchScope == SingleThread) {
19046 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19047 // the IR level, so we must wrap it in an intrinsic.
19049 } else if (hasMFENCE(Subtarget)) {
19050 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19051 Intrinsic::x86_sse2_mfence);
19052 Builder.CreateCall(MFence);
19054 // FIXME: it might make sense to use a locked operation here but on a
19055 // different cache-line to prevent cache-line bouncing. In practice it
19056 // is probably a small win, and x86 processors without mfence are rare
19057 // enough that we do not bother.
19061 // Finally we can emit the atomic load.
19062 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19063 AI->getType()->getPrimitiveSizeInBits());
19064 Loaded->setAtomic(Order, SynchScope);
19065 AI->replaceAllUsesWith(Loaded);
19066 AI->eraseFromParent();
19070 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19071 SelectionDAG &DAG) {
19073 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19074 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19075 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19076 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19078 // The only fence that needs an instruction is a sequentially-consistent
19079 // cross-thread fence.
19080 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19081 if (hasMFENCE(*Subtarget))
19082 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19084 SDValue Chain = Op.getOperand(0);
19085 SDValue Zero = DAG.getConstant(0, MVT::i32);
19087 DAG.getRegister(X86::ESP, MVT::i32), // Base
19088 DAG.getTargetConstant(1, MVT::i8), // Scale
19089 DAG.getRegister(0, MVT::i32), // Index
19090 DAG.getTargetConstant(0, MVT::i32), // Disp
19091 DAG.getRegister(0, MVT::i32), // Segment.
19095 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19096 return SDValue(Res, 0);
19099 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19100 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19103 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19104 SelectionDAG &DAG) {
19105 MVT T = Op.getSimpleValueType();
19109 switch(T.SimpleTy) {
19110 default: llvm_unreachable("Invalid value type!");
19111 case MVT::i8: Reg = X86::AL; size = 1; break;
19112 case MVT::i16: Reg = X86::AX; size = 2; break;
19113 case MVT::i32: Reg = X86::EAX; size = 4; break;
19115 assert(Subtarget->is64Bit() && "Node not type legal!");
19116 Reg = X86::RAX; size = 8;
19119 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19120 Op.getOperand(2), SDValue());
19121 SDValue Ops[] = { cpIn.getValue(0),
19124 DAG.getTargetConstant(size, MVT::i8),
19125 cpIn.getValue(1) };
19126 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19127 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19128 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19132 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19133 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19134 MVT::i32, cpOut.getValue(2));
19135 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19136 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19138 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19139 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19140 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19144 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19145 SelectionDAG &DAG) {
19146 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19147 MVT DstVT = Op.getSimpleValueType();
19149 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19150 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19151 if (DstVT != MVT::f64)
19152 // This conversion needs to be expanded.
19155 SDValue InVec = Op->getOperand(0);
19157 unsigned NumElts = SrcVT.getVectorNumElements();
19158 EVT SVT = SrcVT.getVectorElementType();
19160 // Widen the vector in input in the case of MVT::v2i32.
19161 // Example: from MVT::v2i32 to MVT::v4i32.
19162 SmallVector<SDValue, 16> Elts;
19163 for (unsigned i = 0, e = NumElts; i != e; ++i)
19164 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19165 DAG.getIntPtrConstant(i)));
19167 // Explicitly mark the extra elements as Undef.
19168 SDValue Undef = DAG.getUNDEF(SVT);
19169 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19170 Elts.push_back(Undef);
19172 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19173 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19174 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19175 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19176 DAG.getIntPtrConstant(0));
19179 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19180 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19181 assert((DstVT == MVT::i64 ||
19182 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19183 "Unexpected custom BITCAST");
19184 // i64 <=> MMX conversions are Legal.
19185 if (SrcVT==MVT::i64 && DstVT.isVector())
19187 if (DstVT==MVT::i64 && SrcVT.isVector())
19189 // MMX <=> MMX conversions are Legal.
19190 if (SrcVT.isVector() && DstVT.isVector())
19192 // All other conversions need to be expanded.
19196 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19197 SDNode *Node = Op.getNode();
19199 EVT T = Node->getValueType(0);
19200 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19201 DAG.getConstant(0, T), Node->getOperand(2));
19202 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19203 cast<AtomicSDNode>(Node)->getMemoryVT(),
19204 Node->getOperand(0),
19205 Node->getOperand(1), negOp,
19206 cast<AtomicSDNode>(Node)->getMemOperand(),
19207 cast<AtomicSDNode>(Node)->getOrdering(),
19208 cast<AtomicSDNode>(Node)->getSynchScope());
19211 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19212 SDNode *Node = Op.getNode();
19214 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19216 // Convert seq_cst store -> xchg
19217 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19218 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19219 // (The only way to get a 16-byte store is cmpxchg16b)
19220 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19221 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19222 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19223 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19224 cast<AtomicSDNode>(Node)->getMemoryVT(),
19225 Node->getOperand(0),
19226 Node->getOperand(1), Node->getOperand(2),
19227 cast<AtomicSDNode>(Node)->getMemOperand(),
19228 cast<AtomicSDNode>(Node)->getOrdering(),
19229 cast<AtomicSDNode>(Node)->getSynchScope());
19230 return Swap.getValue(1);
19232 // Other atomic stores have a simple pattern.
19236 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19237 EVT VT = Op.getNode()->getSimpleValueType(0);
19239 // Let legalize expand this if it isn't a legal type yet.
19240 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19243 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19246 bool ExtraOp = false;
19247 switch (Op.getOpcode()) {
19248 default: llvm_unreachable("Invalid code");
19249 case ISD::ADDC: Opc = X86ISD::ADD; break;
19250 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19251 case ISD::SUBC: Opc = X86ISD::SUB; break;
19252 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19256 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19258 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19259 Op.getOperand(1), Op.getOperand(2));
19262 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19263 SelectionDAG &DAG) {
19264 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19266 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19267 // which returns the values as { float, float } (in XMM0) or
19268 // { double, double } (which is returned in XMM0, XMM1).
19270 SDValue Arg = Op.getOperand(0);
19271 EVT ArgVT = Arg.getValueType();
19272 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19274 TargetLowering::ArgListTy Args;
19275 TargetLowering::ArgListEntry Entry;
19279 Entry.isSExt = false;
19280 Entry.isZExt = false;
19281 Args.push_back(Entry);
19283 bool isF64 = ArgVT == MVT::f64;
19284 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19285 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19286 // the results are returned via SRet in memory.
19287 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19288 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19289 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19291 Type *RetTy = isF64
19292 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19293 : (Type*)VectorType::get(ArgTy, 4);
19295 TargetLowering::CallLoweringInfo CLI(DAG);
19296 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19297 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19299 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19302 // Returned in xmm0 and xmm1.
19303 return CallResult.first;
19305 // Returned in bits 0:31 and 32:64 xmm0.
19306 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19307 CallResult.first, DAG.getIntPtrConstant(0));
19308 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19309 CallResult.first, DAG.getIntPtrConstant(1));
19310 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19311 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19314 /// LowerOperation - Provide custom lowering hooks for some operations.
19316 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19317 switch (Op.getOpcode()) {
19318 default: llvm_unreachable("Should not custom lower this!");
19319 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19320 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19321 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19322 return LowerCMP_SWAP(Op, Subtarget, DAG);
19323 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19324 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19325 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19326 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19327 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19328 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19329 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19330 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19331 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19332 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19333 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19334 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19335 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19336 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19337 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19338 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19339 case ISD::SHL_PARTS:
19340 case ISD::SRA_PARTS:
19341 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19342 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19343 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19344 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19345 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19346 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19347 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19348 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19349 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19350 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19351 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19353 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19354 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19355 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19356 case ISD::SETCC: return LowerSETCC(Op, DAG);
19357 case ISD::SELECT: return LowerSELECT(Op, DAG);
19358 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19359 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19360 case ISD::VASTART: return LowerVASTART(Op, DAG);
19361 case ISD::VAARG: return LowerVAARG(Op, DAG);
19362 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19363 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19364 case ISD::INTRINSIC_VOID:
19365 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19366 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19367 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19368 case ISD::FRAME_TO_ARGS_OFFSET:
19369 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19370 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19371 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19372 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19373 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19374 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19375 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19376 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19377 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19378 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19379 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19380 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19381 case ISD::UMUL_LOHI:
19382 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19385 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19391 case ISD::UMULO: return LowerXALUO(Op, DAG);
19392 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19393 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19397 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19398 case ISD::ADD: return LowerADD(Op, DAG);
19399 case ISD::SUB: return LowerSUB(Op, DAG);
19400 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19404 /// ReplaceNodeResults - Replace a node with an illegal result type
19405 /// with a new node built out of custom code.
19406 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19407 SmallVectorImpl<SDValue>&Results,
19408 SelectionDAG &DAG) const {
19410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19411 switch (N->getOpcode()) {
19413 llvm_unreachable("Do not know how to custom type legalize this operation!");
19414 case ISD::SIGN_EXTEND_INREG:
19419 // We don't want to expand or promote these.
19426 case ISD::UDIVREM: {
19427 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19428 Results.push_back(V);
19431 case ISD::FP_TO_SINT:
19432 case ISD::FP_TO_UINT: {
19433 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19435 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19438 std::pair<SDValue,SDValue> Vals =
19439 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19440 SDValue FIST = Vals.first, StackSlot = Vals.second;
19441 if (FIST.getNode()) {
19442 EVT VT = N->getValueType(0);
19443 // Return a load from the stack slot.
19444 if (StackSlot.getNode())
19445 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19446 MachinePointerInfo(),
19447 false, false, false, 0));
19449 Results.push_back(FIST);
19453 case ISD::UINT_TO_FP: {
19454 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19455 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19456 N->getValueType(0) != MVT::v2f32)
19458 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19460 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19462 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19463 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19464 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19465 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19466 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19467 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19470 case ISD::FP_ROUND: {
19471 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19473 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19474 Results.push_back(V);
19477 case ISD::INTRINSIC_W_CHAIN: {
19478 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19480 default : llvm_unreachable("Do not know how to custom type "
19481 "legalize this intrinsic operation!");
19482 case Intrinsic::x86_rdtsc:
19483 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19485 case Intrinsic::x86_rdtscp:
19486 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19488 case Intrinsic::x86_rdpmc:
19489 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19492 case ISD::READCYCLECOUNTER: {
19493 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19496 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19497 EVT T = N->getValueType(0);
19498 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19499 bool Regs64bit = T == MVT::i128;
19500 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19501 SDValue cpInL, cpInH;
19502 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19503 DAG.getConstant(0, HalfT));
19504 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19505 DAG.getConstant(1, HalfT));
19506 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19507 Regs64bit ? X86::RAX : X86::EAX,
19509 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19510 Regs64bit ? X86::RDX : X86::EDX,
19511 cpInH, cpInL.getValue(1));
19512 SDValue swapInL, swapInH;
19513 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19514 DAG.getConstant(0, HalfT));
19515 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19516 DAG.getConstant(1, HalfT));
19517 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19518 Regs64bit ? X86::RBX : X86::EBX,
19519 swapInL, cpInH.getValue(1));
19520 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19521 Regs64bit ? X86::RCX : X86::ECX,
19522 swapInH, swapInL.getValue(1));
19523 SDValue Ops[] = { swapInH.getValue(0),
19525 swapInH.getValue(1) };
19526 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19527 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19528 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19529 X86ISD::LCMPXCHG8_DAG;
19530 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19531 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19532 Regs64bit ? X86::RAX : X86::EAX,
19533 HalfT, Result.getValue(1));
19534 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19535 Regs64bit ? X86::RDX : X86::EDX,
19536 HalfT, cpOutL.getValue(2));
19537 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19539 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19540 MVT::i32, cpOutH.getValue(2));
19542 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19543 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19544 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19546 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19547 Results.push_back(Success);
19548 Results.push_back(EFLAGS.getValue(1));
19551 case ISD::ATOMIC_SWAP:
19552 case ISD::ATOMIC_LOAD_ADD:
19553 case ISD::ATOMIC_LOAD_SUB:
19554 case ISD::ATOMIC_LOAD_AND:
19555 case ISD::ATOMIC_LOAD_OR:
19556 case ISD::ATOMIC_LOAD_XOR:
19557 case ISD::ATOMIC_LOAD_NAND:
19558 case ISD::ATOMIC_LOAD_MIN:
19559 case ISD::ATOMIC_LOAD_MAX:
19560 case ISD::ATOMIC_LOAD_UMIN:
19561 case ISD::ATOMIC_LOAD_UMAX:
19562 case ISD::ATOMIC_LOAD: {
19563 // Delegate to generic TypeLegalization. Situations we can really handle
19564 // should have already been dealt with by AtomicExpandPass.cpp.
19567 case ISD::BITCAST: {
19568 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19569 EVT DstVT = N->getValueType(0);
19570 EVT SrcVT = N->getOperand(0)->getValueType(0);
19572 if (SrcVT != MVT::f64 ||
19573 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19576 unsigned NumElts = DstVT.getVectorNumElements();
19577 EVT SVT = DstVT.getVectorElementType();
19578 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19579 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19580 MVT::v2f64, N->getOperand(0));
19581 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19583 if (ExperimentalVectorWideningLegalization) {
19584 // If we are legalizing vectors by widening, we already have the desired
19585 // legal vector type, just return it.
19586 Results.push_back(ToVecInt);
19590 SmallVector<SDValue, 8> Elts;
19591 for (unsigned i = 0, e = NumElts; i != e; ++i)
19592 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19593 ToVecInt, DAG.getIntPtrConstant(i)));
19595 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19600 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19602 default: return nullptr;
19603 case X86ISD::BSF: return "X86ISD::BSF";
19604 case X86ISD::BSR: return "X86ISD::BSR";
19605 case X86ISD::SHLD: return "X86ISD::SHLD";
19606 case X86ISD::SHRD: return "X86ISD::SHRD";
19607 case X86ISD::FAND: return "X86ISD::FAND";
19608 case X86ISD::FANDN: return "X86ISD::FANDN";
19609 case X86ISD::FOR: return "X86ISD::FOR";
19610 case X86ISD::FXOR: return "X86ISD::FXOR";
19611 case X86ISD::FSRL: return "X86ISD::FSRL";
19612 case X86ISD::FILD: return "X86ISD::FILD";
19613 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19614 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19615 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19616 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19617 case X86ISD::FLD: return "X86ISD::FLD";
19618 case X86ISD::FST: return "X86ISD::FST";
19619 case X86ISD::CALL: return "X86ISD::CALL";
19620 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19621 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19622 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19623 case X86ISD::BT: return "X86ISD::BT";
19624 case X86ISD::CMP: return "X86ISD::CMP";
19625 case X86ISD::COMI: return "X86ISD::COMI";
19626 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19627 case X86ISD::CMPM: return "X86ISD::CMPM";
19628 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19629 case X86ISD::SETCC: return "X86ISD::SETCC";
19630 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19631 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19632 case X86ISD::CMOV: return "X86ISD::CMOV";
19633 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19634 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19635 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19636 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19637 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19638 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19639 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19640 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19641 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19642 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19643 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19644 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19645 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19646 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19647 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19648 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19649 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19650 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19651 case X86ISD::HADD: return "X86ISD::HADD";
19652 case X86ISD::HSUB: return "X86ISD::HSUB";
19653 case X86ISD::FHADD: return "X86ISD::FHADD";
19654 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19655 case X86ISD::UMAX: return "X86ISD::UMAX";
19656 case X86ISD::UMIN: return "X86ISD::UMIN";
19657 case X86ISD::SMAX: return "X86ISD::SMAX";
19658 case X86ISD::SMIN: return "X86ISD::SMIN";
19659 case X86ISD::FMAX: return "X86ISD::FMAX";
19660 case X86ISD::FMIN: return "X86ISD::FMIN";
19661 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19662 case X86ISD::FMINC: return "X86ISD::FMINC";
19663 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19664 case X86ISD::FRCP: return "X86ISD::FRCP";
19665 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19666 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19667 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19668 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19669 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19670 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19671 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19672 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19673 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19674 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19675 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19676 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19677 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19678 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19679 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19680 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19681 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19682 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19683 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19684 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19685 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19686 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19687 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19688 case X86ISD::VSHL: return "X86ISD::VSHL";
19689 case X86ISD::VSRL: return "X86ISD::VSRL";
19690 case X86ISD::VSRA: return "X86ISD::VSRA";
19691 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19692 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19693 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19694 case X86ISD::CMPP: return "X86ISD::CMPP";
19695 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19696 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19697 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19698 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19699 case X86ISD::ADD: return "X86ISD::ADD";
19700 case X86ISD::SUB: return "X86ISD::SUB";
19701 case X86ISD::ADC: return "X86ISD::ADC";
19702 case X86ISD::SBB: return "X86ISD::SBB";
19703 case X86ISD::SMUL: return "X86ISD::SMUL";
19704 case X86ISD::UMUL: return "X86ISD::UMUL";
19705 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19706 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19707 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19708 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19709 case X86ISD::INC: return "X86ISD::INC";
19710 case X86ISD::DEC: return "X86ISD::DEC";
19711 case X86ISD::OR: return "X86ISD::OR";
19712 case X86ISD::XOR: return "X86ISD::XOR";
19713 case X86ISD::AND: return "X86ISD::AND";
19714 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19715 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19716 case X86ISD::PTEST: return "X86ISD::PTEST";
19717 case X86ISD::TESTP: return "X86ISD::TESTP";
19718 case X86ISD::TESTM: return "X86ISD::TESTM";
19719 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19720 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19721 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19722 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19723 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19724 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19725 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19726 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19727 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19728 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19729 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19730 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19731 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19732 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19733 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19734 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19735 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19736 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19737 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19738 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19739 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19740 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19741 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19742 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19743 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19744 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19745 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19746 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19747 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19748 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19749 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19750 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19751 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19752 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19753 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19754 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19755 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19756 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19757 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19758 case X86ISD::SAHF: return "X86ISD::SAHF";
19759 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19760 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19761 case X86ISD::FMADD: return "X86ISD::FMADD";
19762 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19763 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19764 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19765 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19766 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19767 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19768 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19769 case X86ISD::XTEST: return "X86ISD::XTEST";
19773 // isLegalAddressingMode - Return true if the addressing mode represented
19774 // by AM is legal for this target, for a load/store of the specified type.
19775 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19777 // X86 supports extremely general addressing modes.
19778 CodeModel::Model M = getTargetMachine().getCodeModel();
19779 Reloc::Model R = getTargetMachine().getRelocationModel();
19781 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19782 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19787 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19789 // If a reference to this global requires an extra load, we can't fold it.
19790 if (isGlobalStubReference(GVFlags))
19793 // If BaseGV requires a register for the PIC base, we cannot also have a
19794 // BaseReg specified.
19795 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19798 // If lower 4G is not available, then we must use rip-relative addressing.
19799 if ((M != CodeModel::Small || R != Reloc::Static) &&
19800 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19804 switch (AM.Scale) {
19810 // These scales always work.
19815 // These scales are formed with basereg+scalereg. Only accept if there is
19820 default: // Other stuff never works.
19827 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19828 unsigned Bits = Ty->getScalarSizeInBits();
19830 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19831 // particularly cheaper than those without.
19835 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19836 // variable shifts just as cheap as scalar ones.
19837 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19840 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19841 // fully general vector.
19845 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19846 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19848 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19849 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19850 return NumBits1 > NumBits2;
19853 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19854 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19857 if (!isTypeLegal(EVT::getEVT(Ty1)))
19860 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19862 // Assuming the caller doesn't have a zeroext or signext return parameter,
19863 // truncation all the way down to i1 is valid.
19867 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19868 return isInt<32>(Imm);
19871 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19872 // Can also use sub to handle negated immediates.
19873 return isInt<32>(Imm);
19876 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19877 if (!VT1.isInteger() || !VT2.isInteger())
19879 unsigned NumBits1 = VT1.getSizeInBits();
19880 unsigned NumBits2 = VT2.getSizeInBits();
19881 return NumBits1 > NumBits2;
19884 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19885 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19886 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19889 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19890 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19891 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19894 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19895 EVT VT1 = Val.getValueType();
19896 if (isZExtFree(VT1, VT2))
19899 if (Val.getOpcode() != ISD::LOAD)
19902 if (!VT1.isSimple() || !VT1.isInteger() ||
19903 !VT2.isSimple() || !VT2.isInteger())
19906 switch (VT1.getSimpleVT().SimpleTy) {
19911 // X86 has 8, 16, and 32-bit zero-extending loads.
19919 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19920 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19923 VT = VT.getScalarType();
19925 if (!VT.isSimple())
19928 switch (VT.getSimpleVT().SimpleTy) {
19939 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19940 // i16 instructions are longer (0x66 prefix) and potentially slower.
19941 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19944 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19945 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19946 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19947 /// are assumed to be legal.
19949 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19951 if (!VT.isSimple())
19954 MVT SVT = VT.getSimpleVT();
19956 // Very little shuffling can be done for 64-bit vectors right now.
19957 if (VT.getSizeInBits() == 64)
19960 // If this is a single-input shuffle with no 128 bit lane crossings we can
19961 // lower it into pshufb.
19962 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19963 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19964 bool isLegal = true;
19965 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19966 if (M[I] >= (int)SVT.getVectorNumElements() ||
19967 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19976 // FIXME: blends, shifts.
19977 return (SVT.getVectorNumElements() == 2 ||
19978 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19979 isMOVLMask(M, SVT) ||
19980 isMOVHLPSMask(M, SVT) ||
19981 isSHUFPMask(M, SVT) ||
19982 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19983 isPSHUFDMask(M, SVT) ||
19984 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19985 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19986 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19987 isPALIGNRMask(M, SVT, Subtarget) ||
19988 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19989 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19990 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19991 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19992 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19993 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19997 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19999 if (!VT.isSimple())
20002 MVT SVT = VT.getSimpleVT();
20003 unsigned NumElts = SVT.getVectorNumElements();
20004 // FIXME: This collection of masks seems suspect.
20007 if (NumElts == 4 && SVT.is128BitVector()) {
20008 return (isMOVLMask(Mask, SVT) ||
20009 isCommutedMOVLMask(Mask, SVT, true) ||
20010 isSHUFPMask(Mask, SVT) ||
20011 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20012 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20013 Subtarget->hasInt256()));
20018 //===----------------------------------------------------------------------===//
20019 // X86 Scheduler Hooks
20020 //===----------------------------------------------------------------------===//
20022 /// Utility function to emit xbegin specifying the start of an RTM region.
20023 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20024 const TargetInstrInfo *TII) {
20025 DebugLoc DL = MI->getDebugLoc();
20027 const BasicBlock *BB = MBB->getBasicBlock();
20028 MachineFunction::iterator I = MBB;
20031 // For the v = xbegin(), we generate
20042 MachineBasicBlock *thisMBB = MBB;
20043 MachineFunction *MF = MBB->getParent();
20044 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20045 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20046 MF->insert(I, mainMBB);
20047 MF->insert(I, sinkMBB);
20049 // Transfer the remainder of BB and its successor edges to sinkMBB.
20050 sinkMBB->splice(sinkMBB->begin(), MBB,
20051 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20052 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20056 // # fallthrough to mainMBB
20057 // # abortion to sinkMBB
20058 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20059 thisMBB->addSuccessor(mainMBB);
20060 thisMBB->addSuccessor(sinkMBB);
20064 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20065 mainMBB->addSuccessor(sinkMBB);
20068 // EAX is live into the sinkMBB
20069 sinkMBB->addLiveIn(X86::EAX);
20070 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20071 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20074 MI->eraseFromParent();
20078 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20079 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20080 // in the .td file.
20081 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20082 const TargetInstrInfo *TII) {
20084 switch (MI->getOpcode()) {
20085 default: llvm_unreachable("illegal opcode!");
20086 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20087 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20088 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20089 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20090 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20091 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20092 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20093 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20096 DebugLoc dl = MI->getDebugLoc();
20097 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20099 unsigned NumArgs = MI->getNumOperands();
20100 for (unsigned i = 1; i < NumArgs; ++i) {
20101 MachineOperand &Op = MI->getOperand(i);
20102 if (!(Op.isReg() && Op.isImplicit()))
20103 MIB.addOperand(Op);
20105 if (MI->hasOneMemOperand())
20106 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20108 BuildMI(*BB, MI, dl,
20109 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20110 .addReg(X86::XMM0);
20112 MI->eraseFromParent();
20116 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20117 // defs in an instruction pattern
20118 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20119 const TargetInstrInfo *TII) {
20121 switch (MI->getOpcode()) {
20122 default: llvm_unreachable("illegal opcode!");
20123 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20124 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20125 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20126 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20127 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20128 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20129 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20130 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20133 DebugLoc dl = MI->getDebugLoc();
20134 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20136 unsigned NumArgs = MI->getNumOperands(); // remove the results
20137 for (unsigned i = 1; i < NumArgs; ++i) {
20138 MachineOperand &Op = MI->getOperand(i);
20139 if (!(Op.isReg() && Op.isImplicit()))
20140 MIB.addOperand(Op);
20142 if (MI->hasOneMemOperand())
20143 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20145 BuildMI(*BB, MI, dl,
20146 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20149 MI->eraseFromParent();
20153 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20154 const TargetInstrInfo *TII,
20155 const X86Subtarget* Subtarget) {
20156 DebugLoc dl = MI->getDebugLoc();
20158 // Address into RAX/EAX, other two args into ECX, EDX.
20159 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20160 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20161 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20162 for (int i = 0; i < X86::AddrNumOperands; ++i)
20163 MIB.addOperand(MI->getOperand(i));
20165 unsigned ValOps = X86::AddrNumOperands;
20166 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20167 .addReg(MI->getOperand(ValOps).getReg());
20168 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20169 .addReg(MI->getOperand(ValOps+1).getReg());
20171 // The instruction doesn't actually take any operands though.
20172 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20174 MI->eraseFromParent(); // The pseudo is gone now.
20178 MachineBasicBlock *
20179 X86TargetLowering::EmitVAARG64WithCustomInserter(
20181 MachineBasicBlock *MBB) const {
20182 // Emit va_arg instruction on X86-64.
20184 // Operands to this pseudo-instruction:
20185 // 0 ) Output : destination address (reg)
20186 // 1-5) Input : va_list address (addr, i64mem)
20187 // 6 ) ArgSize : Size (in bytes) of vararg type
20188 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20189 // 8 ) Align : Alignment of type
20190 // 9 ) EFLAGS (implicit-def)
20192 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20193 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20195 unsigned DestReg = MI->getOperand(0).getReg();
20196 MachineOperand &Base = MI->getOperand(1);
20197 MachineOperand &Scale = MI->getOperand(2);
20198 MachineOperand &Index = MI->getOperand(3);
20199 MachineOperand &Disp = MI->getOperand(4);
20200 MachineOperand &Segment = MI->getOperand(5);
20201 unsigned ArgSize = MI->getOperand(6).getImm();
20202 unsigned ArgMode = MI->getOperand(7).getImm();
20203 unsigned Align = MI->getOperand(8).getImm();
20205 // Memory Reference
20206 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20207 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20208 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20210 // Machine Information
20211 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20212 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20213 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20214 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20215 DebugLoc DL = MI->getDebugLoc();
20217 // struct va_list {
20220 // i64 overflow_area (address)
20221 // i64 reg_save_area (address)
20223 // sizeof(va_list) = 24
20224 // alignment(va_list) = 8
20226 unsigned TotalNumIntRegs = 6;
20227 unsigned TotalNumXMMRegs = 8;
20228 bool UseGPOffset = (ArgMode == 1);
20229 bool UseFPOffset = (ArgMode == 2);
20230 unsigned MaxOffset = TotalNumIntRegs * 8 +
20231 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20233 /* Align ArgSize to a multiple of 8 */
20234 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20235 bool NeedsAlign = (Align > 8);
20237 MachineBasicBlock *thisMBB = MBB;
20238 MachineBasicBlock *overflowMBB;
20239 MachineBasicBlock *offsetMBB;
20240 MachineBasicBlock *endMBB;
20242 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20243 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20244 unsigned OffsetReg = 0;
20246 if (!UseGPOffset && !UseFPOffset) {
20247 // If we only pull from the overflow region, we don't create a branch.
20248 // We don't need to alter control flow.
20249 OffsetDestReg = 0; // unused
20250 OverflowDestReg = DestReg;
20252 offsetMBB = nullptr;
20253 overflowMBB = thisMBB;
20256 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20257 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20258 // If not, pull from overflow_area. (branch to overflowMBB)
20263 // offsetMBB overflowMBB
20268 // Registers for the PHI in endMBB
20269 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20270 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20272 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20273 MachineFunction *MF = MBB->getParent();
20274 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20275 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20276 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20278 MachineFunction::iterator MBBIter = MBB;
20281 // Insert the new basic blocks
20282 MF->insert(MBBIter, offsetMBB);
20283 MF->insert(MBBIter, overflowMBB);
20284 MF->insert(MBBIter, endMBB);
20286 // Transfer the remainder of MBB and its successor edges to endMBB.
20287 endMBB->splice(endMBB->begin(), thisMBB,
20288 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20289 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20291 // Make offsetMBB and overflowMBB successors of thisMBB
20292 thisMBB->addSuccessor(offsetMBB);
20293 thisMBB->addSuccessor(overflowMBB);
20295 // endMBB is a successor of both offsetMBB and overflowMBB
20296 offsetMBB->addSuccessor(endMBB);
20297 overflowMBB->addSuccessor(endMBB);
20299 // Load the offset value into a register
20300 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20301 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20305 .addDisp(Disp, UseFPOffset ? 4 : 0)
20306 .addOperand(Segment)
20307 .setMemRefs(MMOBegin, MMOEnd);
20309 // Check if there is enough room left to pull this argument.
20310 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20312 .addImm(MaxOffset + 8 - ArgSizeA8);
20314 // Branch to "overflowMBB" if offset >= max
20315 // Fall through to "offsetMBB" otherwise
20316 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20317 .addMBB(overflowMBB);
20320 // In offsetMBB, emit code to use the reg_save_area.
20322 assert(OffsetReg != 0);
20324 // Read the reg_save_area address.
20325 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20326 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20331 .addOperand(Segment)
20332 .setMemRefs(MMOBegin, MMOEnd);
20334 // Zero-extend the offset
20335 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20336 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20339 .addImm(X86::sub_32bit);
20341 // Add the offset to the reg_save_area to get the final address.
20342 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20343 .addReg(OffsetReg64)
20344 .addReg(RegSaveReg);
20346 // Compute the offset for the next argument
20347 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20348 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20350 .addImm(UseFPOffset ? 16 : 8);
20352 // Store it back into the va_list.
20353 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20357 .addDisp(Disp, UseFPOffset ? 4 : 0)
20358 .addOperand(Segment)
20359 .addReg(NextOffsetReg)
20360 .setMemRefs(MMOBegin, MMOEnd);
20363 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20368 // Emit code to use overflow area
20371 // Load the overflow_area address into a register.
20372 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20373 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20378 .addOperand(Segment)
20379 .setMemRefs(MMOBegin, MMOEnd);
20381 // If we need to align it, do so. Otherwise, just copy the address
20382 // to OverflowDestReg.
20384 // Align the overflow address
20385 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20386 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20388 // aligned_addr = (addr + (align-1)) & ~(align-1)
20389 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20390 .addReg(OverflowAddrReg)
20393 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20395 .addImm(~(uint64_t)(Align-1));
20397 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20398 .addReg(OverflowAddrReg);
20401 // Compute the next overflow address after this argument.
20402 // (the overflow address should be kept 8-byte aligned)
20403 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20404 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20405 .addReg(OverflowDestReg)
20406 .addImm(ArgSizeA8);
20408 // Store the new overflow address.
20409 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20414 .addOperand(Segment)
20415 .addReg(NextAddrReg)
20416 .setMemRefs(MMOBegin, MMOEnd);
20418 // If we branched, emit the PHI to the front of endMBB.
20420 BuildMI(*endMBB, endMBB->begin(), DL,
20421 TII->get(X86::PHI), DestReg)
20422 .addReg(OffsetDestReg).addMBB(offsetMBB)
20423 .addReg(OverflowDestReg).addMBB(overflowMBB);
20426 // Erase the pseudo instruction
20427 MI->eraseFromParent();
20432 MachineBasicBlock *
20433 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20435 MachineBasicBlock *MBB) const {
20436 // Emit code to save XMM registers to the stack. The ABI says that the
20437 // number of registers to save is given in %al, so it's theoretically
20438 // possible to do an indirect jump trick to avoid saving all of them,
20439 // however this code takes a simpler approach and just executes all
20440 // of the stores if %al is non-zero. It's less code, and it's probably
20441 // easier on the hardware branch predictor, and stores aren't all that
20442 // expensive anyway.
20444 // Create the new basic blocks. One block contains all the XMM stores,
20445 // and one block is the final destination regardless of whether any
20446 // stores were performed.
20447 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20448 MachineFunction *F = MBB->getParent();
20449 MachineFunction::iterator MBBIter = MBB;
20451 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20452 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20453 F->insert(MBBIter, XMMSaveMBB);
20454 F->insert(MBBIter, EndMBB);
20456 // Transfer the remainder of MBB and its successor edges to EndMBB.
20457 EndMBB->splice(EndMBB->begin(), MBB,
20458 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20459 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20461 // The original block will now fall through to the XMM save block.
20462 MBB->addSuccessor(XMMSaveMBB);
20463 // The XMMSaveMBB will fall through to the end block.
20464 XMMSaveMBB->addSuccessor(EndMBB);
20466 // Now add the instructions.
20467 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20468 DebugLoc DL = MI->getDebugLoc();
20470 unsigned CountReg = MI->getOperand(0).getReg();
20471 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20472 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20474 if (!Subtarget->isTargetWin64()) {
20475 // If %al is 0, branch around the XMM save block.
20476 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20477 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20478 MBB->addSuccessor(EndMBB);
20481 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20482 // that was just emitted, but clearly shouldn't be "saved".
20483 assert((MI->getNumOperands() <= 3 ||
20484 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20485 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20486 && "Expected last argument to be EFLAGS");
20487 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20488 // In the XMM save block, save all the XMM argument registers.
20489 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20490 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20491 MachineMemOperand *MMO =
20492 F->getMachineMemOperand(
20493 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20494 MachineMemOperand::MOStore,
20495 /*Size=*/16, /*Align=*/16);
20496 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20497 .addFrameIndex(RegSaveFrameIndex)
20498 .addImm(/*Scale=*/1)
20499 .addReg(/*IndexReg=*/0)
20500 .addImm(/*Disp=*/Offset)
20501 .addReg(/*Segment=*/0)
20502 .addReg(MI->getOperand(i).getReg())
20503 .addMemOperand(MMO);
20506 MI->eraseFromParent(); // The pseudo instruction is gone now.
20511 // The EFLAGS operand of SelectItr might be missing a kill marker
20512 // because there were multiple uses of EFLAGS, and ISel didn't know
20513 // which to mark. Figure out whether SelectItr should have had a
20514 // kill marker, and set it if it should. Returns the correct kill
20516 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20517 MachineBasicBlock* BB,
20518 const TargetRegisterInfo* TRI) {
20519 // Scan forward through BB for a use/def of EFLAGS.
20520 MachineBasicBlock::iterator miI(std::next(SelectItr));
20521 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20522 const MachineInstr& mi = *miI;
20523 if (mi.readsRegister(X86::EFLAGS))
20525 if (mi.definesRegister(X86::EFLAGS))
20526 break; // Should have kill-flag - update below.
20529 // If we hit the end of the block, check whether EFLAGS is live into a
20531 if (miI == BB->end()) {
20532 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20533 sEnd = BB->succ_end();
20534 sItr != sEnd; ++sItr) {
20535 MachineBasicBlock* succ = *sItr;
20536 if (succ->isLiveIn(X86::EFLAGS))
20541 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20542 // out. SelectMI should have a kill flag on EFLAGS.
20543 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20547 MachineBasicBlock *
20548 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20549 MachineBasicBlock *BB) const {
20550 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20551 DebugLoc DL = MI->getDebugLoc();
20553 // To "insert" a SELECT_CC instruction, we actually have to insert the
20554 // diamond control-flow pattern. The incoming instruction knows the
20555 // destination vreg to set, the condition code register to branch on, the
20556 // true/false values to select between, and a branch opcode to use.
20557 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20558 MachineFunction::iterator It = BB;
20564 // cmpTY ccX, r1, r2
20566 // fallthrough --> copy0MBB
20567 MachineBasicBlock *thisMBB = BB;
20568 MachineFunction *F = BB->getParent();
20569 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20570 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20571 F->insert(It, copy0MBB);
20572 F->insert(It, sinkMBB);
20574 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20575 // live into the sink and copy blocks.
20576 const TargetRegisterInfo *TRI =
20577 BB->getParent()->getSubtarget().getRegisterInfo();
20578 if (!MI->killsRegister(X86::EFLAGS) &&
20579 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20580 copy0MBB->addLiveIn(X86::EFLAGS);
20581 sinkMBB->addLiveIn(X86::EFLAGS);
20584 // Transfer the remainder of BB and its successor edges to sinkMBB.
20585 sinkMBB->splice(sinkMBB->begin(), BB,
20586 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20587 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20589 // Add the true and fallthrough blocks as its successors.
20590 BB->addSuccessor(copy0MBB);
20591 BB->addSuccessor(sinkMBB);
20593 // Create the conditional branch instruction.
20595 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20596 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20599 // %FalseValue = ...
20600 // # fallthrough to sinkMBB
20601 copy0MBB->addSuccessor(sinkMBB);
20604 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20606 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20607 TII->get(X86::PHI), MI->getOperand(0).getReg())
20608 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20609 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20611 MI->eraseFromParent(); // The pseudo instruction is gone now.
20615 MachineBasicBlock *
20616 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20617 MachineBasicBlock *BB) const {
20618 MachineFunction *MF = BB->getParent();
20619 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20620 DebugLoc DL = MI->getDebugLoc();
20621 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20623 assert(MF->shouldSplitStack());
20625 const bool Is64Bit = Subtarget->is64Bit();
20626 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20628 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20629 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20632 // ... [Till the alloca]
20633 // If stacklet is not large enough, jump to mallocMBB
20636 // Allocate by subtracting from RSP
20637 // Jump to continueMBB
20640 // Allocate by call to runtime
20644 // [rest of original BB]
20647 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20648 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20649 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20651 MachineRegisterInfo &MRI = MF->getRegInfo();
20652 const TargetRegisterClass *AddrRegClass =
20653 getRegClassFor(getPointerTy());
20655 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20656 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20657 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20658 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20659 sizeVReg = MI->getOperand(1).getReg(),
20660 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20662 MachineFunction::iterator MBBIter = BB;
20665 MF->insert(MBBIter, bumpMBB);
20666 MF->insert(MBBIter, mallocMBB);
20667 MF->insert(MBBIter, continueMBB);
20669 continueMBB->splice(continueMBB->begin(), BB,
20670 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20671 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20673 // Add code to the main basic block to check if the stack limit has been hit,
20674 // and if so, jump to mallocMBB otherwise to bumpMBB.
20675 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20676 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20677 .addReg(tmpSPVReg).addReg(sizeVReg);
20678 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20679 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20680 .addReg(SPLimitVReg);
20681 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20683 // bumpMBB simply decreases the stack pointer, since we know the current
20684 // stacklet has enough space.
20685 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20686 .addReg(SPLimitVReg);
20687 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20688 .addReg(SPLimitVReg);
20689 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20691 // Calls into a routine in libgcc to allocate more space from the heap.
20692 const uint32_t *RegMask = MF->getTarget()
20693 .getSubtargetImpl()
20694 ->getRegisterInfo()
20695 ->getCallPreservedMask(CallingConv::C);
20697 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20699 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20700 .addExternalSymbol("__morestack_allocate_stack_space")
20701 .addRegMask(RegMask)
20702 .addReg(X86::RDI, RegState::Implicit)
20703 .addReg(X86::RAX, RegState::ImplicitDefine);
20704 } else if (Is64Bit) {
20705 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20707 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20708 .addExternalSymbol("__morestack_allocate_stack_space")
20709 .addRegMask(RegMask)
20710 .addReg(X86::EDI, RegState::Implicit)
20711 .addReg(X86::EAX, RegState::ImplicitDefine);
20713 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20715 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20716 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20717 .addExternalSymbol("__morestack_allocate_stack_space")
20718 .addRegMask(RegMask)
20719 .addReg(X86::EAX, RegState::ImplicitDefine);
20723 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20726 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20727 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20728 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20730 // Set up the CFG correctly.
20731 BB->addSuccessor(bumpMBB);
20732 BB->addSuccessor(mallocMBB);
20733 mallocMBB->addSuccessor(continueMBB);
20734 bumpMBB->addSuccessor(continueMBB);
20736 // Take care of the PHI nodes.
20737 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20738 MI->getOperand(0).getReg())
20739 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20740 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20742 // Delete the original pseudo instruction.
20743 MI->eraseFromParent();
20746 return continueMBB;
20749 MachineBasicBlock *
20750 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20751 MachineBasicBlock *BB) const {
20752 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20753 DebugLoc DL = MI->getDebugLoc();
20755 assert(!Subtarget->isTargetMacho());
20757 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20758 // non-trivial part is impdef of ESP.
20760 if (Subtarget->isTargetWin64()) {
20761 if (Subtarget->isTargetCygMing()) {
20762 // ___chkstk(Mingw64):
20763 // Clobbers R10, R11, RAX and EFLAGS.
20765 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20766 .addExternalSymbol("___chkstk")
20767 .addReg(X86::RAX, RegState::Implicit)
20768 .addReg(X86::RSP, RegState::Implicit)
20769 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20770 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20771 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20773 // __chkstk(MSVCRT): does not update stack pointer.
20774 // Clobbers R10, R11 and EFLAGS.
20775 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20776 .addExternalSymbol("__chkstk")
20777 .addReg(X86::RAX, RegState::Implicit)
20778 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20779 // RAX has the offset to be subtracted from RSP.
20780 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20785 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20786 Subtarget->isTargetWindowsItanium())
20790 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20791 .addExternalSymbol(StackProbeSymbol)
20792 .addReg(X86::EAX, RegState::Implicit)
20793 .addReg(X86::ESP, RegState::Implicit)
20794 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20795 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20796 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20799 MI->eraseFromParent(); // The pseudo instruction is gone now.
20803 MachineBasicBlock *
20804 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20805 MachineBasicBlock *BB) const {
20806 // This is pretty easy. We're taking the value that we received from
20807 // our load from the relocation, sticking it in either RDI (x86-64)
20808 // or EAX and doing an indirect call. The return value will then
20809 // be in the normal return register.
20810 MachineFunction *F = BB->getParent();
20811 const X86InstrInfo *TII =
20812 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20813 DebugLoc DL = MI->getDebugLoc();
20815 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20816 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20818 // Get a register mask for the lowered call.
20819 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20820 // proper register mask.
20821 const uint32_t *RegMask = F->getTarget()
20822 .getSubtargetImpl()
20823 ->getRegisterInfo()
20824 ->getCallPreservedMask(CallingConv::C);
20825 if (Subtarget->is64Bit()) {
20826 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20827 TII->get(X86::MOV64rm), X86::RDI)
20829 .addImm(0).addReg(0)
20830 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20831 MI->getOperand(3).getTargetFlags())
20833 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20834 addDirectMem(MIB, X86::RDI);
20835 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20836 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20837 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20838 TII->get(X86::MOV32rm), X86::EAX)
20840 .addImm(0).addReg(0)
20841 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20842 MI->getOperand(3).getTargetFlags())
20844 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20845 addDirectMem(MIB, X86::EAX);
20846 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20848 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20849 TII->get(X86::MOV32rm), X86::EAX)
20850 .addReg(TII->getGlobalBaseReg(F))
20851 .addImm(0).addReg(0)
20852 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20853 MI->getOperand(3).getTargetFlags())
20855 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20856 addDirectMem(MIB, X86::EAX);
20857 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20860 MI->eraseFromParent(); // The pseudo instruction is gone now.
20864 MachineBasicBlock *
20865 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20866 MachineBasicBlock *MBB) const {
20867 DebugLoc DL = MI->getDebugLoc();
20868 MachineFunction *MF = MBB->getParent();
20869 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20870 MachineRegisterInfo &MRI = MF->getRegInfo();
20872 const BasicBlock *BB = MBB->getBasicBlock();
20873 MachineFunction::iterator I = MBB;
20876 // Memory Reference
20877 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20878 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20881 unsigned MemOpndSlot = 0;
20883 unsigned CurOp = 0;
20885 DstReg = MI->getOperand(CurOp++).getReg();
20886 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20887 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20888 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20889 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20891 MemOpndSlot = CurOp;
20893 MVT PVT = getPointerTy();
20894 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20895 "Invalid Pointer Size!");
20897 // For v = setjmp(buf), we generate
20900 // buf[LabelOffset] = restoreMBB
20901 // SjLjSetup restoreMBB
20907 // v = phi(main, restore)
20912 MachineBasicBlock *thisMBB = MBB;
20913 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20914 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20915 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20916 MF->insert(I, mainMBB);
20917 MF->insert(I, sinkMBB);
20918 MF->push_back(restoreMBB);
20920 MachineInstrBuilder MIB;
20922 // Transfer the remainder of BB and its successor edges to sinkMBB.
20923 sinkMBB->splice(sinkMBB->begin(), MBB,
20924 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20925 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20928 unsigned PtrStoreOpc = 0;
20929 unsigned LabelReg = 0;
20930 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20931 Reloc::Model RM = MF->getTarget().getRelocationModel();
20932 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20933 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20935 // Prepare IP either in reg or imm.
20936 if (!UseImmLabel) {
20937 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20938 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20939 LabelReg = MRI.createVirtualRegister(PtrRC);
20940 if (Subtarget->is64Bit()) {
20941 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20945 .addMBB(restoreMBB)
20948 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20949 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20950 .addReg(XII->getGlobalBaseReg(MF))
20953 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20957 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20959 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20960 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20961 if (i == X86::AddrDisp)
20962 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20964 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20967 MIB.addReg(LabelReg);
20969 MIB.addMBB(restoreMBB);
20970 MIB.setMemRefs(MMOBegin, MMOEnd);
20972 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20973 .addMBB(restoreMBB);
20975 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20976 MF->getSubtarget().getRegisterInfo());
20977 MIB.addRegMask(RegInfo->getNoPreservedMask());
20978 thisMBB->addSuccessor(mainMBB);
20979 thisMBB->addSuccessor(restoreMBB);
20983 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20984 mainMBB->addSuccessor(sinkMBB);
20987 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20988 TII->get(X86::PHI), DstReg)
20989 .addReg(mainDstReg).addMBB(mainMBB)
20990 .addReg(restoreDstReg).addMBB(restoreMBB);
20993 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20994 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20995 restoreMBB->addSuccessor(sinkMBB);
20997 MI->eraseFromParent();
21001 MachineBasicBlock *
21002 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21003 MachineBasicBlock *MBB) const {
21004 DebugLoc DL = MI->getDebugLoc();
21005 MachineFunction *MF = MBB->getParent();
21006 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21007 MachineRegisterInfo &MRI = MF->getRegInfo();
21009 // Memory Reference
21010 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21011 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21013 MVT PVT = getPointerTy();
21014 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21015 "Invalid Pointer Size!");
21017 const TargetRegisterClass *RC =
21018 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21019 unsigned Tmp = MRI.createVirtualRegister(RC);
21020 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21021 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21022 MF->getSubtarget().getRegisterInfo());
21023 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21024 unsigned SP = RegInfo->getStackRegister();
21026 MachineInstrBuilder MIB;
21028 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21029 const int64_t SPOffset = 2 * PVT.getStoreSize();
21031 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21032 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21035 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21036 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21037 MIB.addOperand(MI->getOperand(i));
21038 MIB.setMemRefs(MMOBegin, MMOEnd);
21040 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21041 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21042 if (i == X86::AddrDisp)
21043 MIB.addDisp(MI->getOperand(i), LabelOffset);
21045 MIB.addOperand(MI->getOperand(i));
21047 MIB.setMemRefs(MMOBegin, MMOEnd);
21049 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21050 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21051 if (i == X86::AddrDisp)
21052 MIB.addDisp(MI->getOperand(i), SPOffset);
21054 MIB.addOperand(MI->getOperand(i));
21056 MIB.setMemRefs(MMOBegin, MMOEnd);
21058 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21060 MI->eraseFromParent();
21064 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21065 // accumulator loops. Writing back to the accumulator allows the coalescer
21066 // to remove extra copies in the loop.
21067 MachineBasicBlock *
21068 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21069 MachineBasicBlock *MBB) const {
21070 MachineOperand &AddendOp = MI->getOperand(3);
21072 // Bail out early if the addend isn't a register - we can't switch these.
21073 if (!AddendOp.isReg())
21076 MachineFunction &MF = *MBB->getParent();
21077 MachineRegisterInfo &MRI = MF.getRegInfo();
21079 // Check whether the addend is defined by a PHI:
21080 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21081 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21082 if (!AddendDef.isPHI())
21085 // Look for the following pattern:
21087 // %addend = phi [%entry, 0], [%loop, %result]
21089 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21093 // %addend = phi [%entry, 0], [%loop, %result]
21095 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21097 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21098 assert(AddendDef.getOperand(i).isReg());
21099 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21100 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21101 if (&PHISrcInst == MI) {
21102 // Found a matching instruction.
21103 unsigned NewFMAOpc = 0;
21104 switch (MI->getOpcode()) {
21105 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21106 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21107 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21108 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21109 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21110 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21111 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21112 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21113 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21114 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21115 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21116 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21117 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21118 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21119 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21120 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21121 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21122 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21123 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21124 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21126 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21127 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21128 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21129 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21130 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21131 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21132 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21133 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21134 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21135 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21136 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21137 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21138 default: llvm_unreachable("Unrecognized FMA variant.");
21141 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21142 MachineInstrBuilder MIB =
21143 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21144 .addOperand(MI->getOperand(0))
21145 .addOperand(MI->getOperand(3))
21146 .addOperand(MI->getOperand(2))
21147 .addOperand(MI->getOperand(1));
21148 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21149 MI->eraseFromParent();
21156 MachineBasicBlock *
21157 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21158 MachineBasicBlock *BB) const {
21159 switch (MI->getOpcode()) {
21160 default: llvm_unreachable("Unexpected instr type to insert");
21161 case X86::TAILJMPd64:
21162 case X86::TAILJMPr64:
21163 case X86::TAILJMPm64:
21164 llvm_unreachable("TAILJMP64 would not be touched here.");
21165 case X86::TCRETURNdi64:
21166 case X86::TCRETURNri64:
21167 case X86::TCRETURNmi64:
21169 case X86::WIN_ALLOCA:
21170 return EmitLoweredWinAlloca(MI, BB);
21171 case X86::SEG_ALLOCA_32:
21172 case X86::SEG_ALLOCA_64:
21173 return EmitLoweredSegAlloca(MI, BB);
21174 case X86::TLSCall_32:
21175 case X86::TLSCall_64:
21176 return EmitLoweredTLSCall(MI, BB);
21177 case X86::CMOV_GR8:
21178 case X86::CMOV_FR32:
21179 case X86::CMOV_FR64:
21180 case X86::CMOV_V4F32:
21181 case X86::CMOV_V2F64:
21182 case X86::CMOV_V2I64:
21183 case X86::CMOV_V8F32:
21184 case X86::CMOV_V4F64:
21185 case X86::CMOV_V4I64:
21186 case X86::CMOV_V16F32:
21187 case X86::CMOV_V8F64:
21188 case X86::CMOV_V8I64:
21189 case X86::CMOV_GR16:
21190 case X86::CMOV_GR32:
21191 case X86::CMOV_RFP32:
21192 case X86::CMOV_RFP64:
21193 case X86::CMOV_RFP80:
21194 return EmitLoweredSelect(MI, BB);
21196 case X86::FP32_TO_INT16_IN_MEM:
21197 case X86::FP32_TO_INT32_IN_MEM:
21198 case X86::FP32_TO_INT64_IN_MEM:
21199 case X86::FP64_TO_INT16_IN_MEM:
21200 case X86::FP64_TO_INT32_IN_MEM:
21201 case X86::FP64_TO_INT64_IN_MEM:
21202 case X86::FP80_TO_INT16_IN_MEM:
21203 case X86::FP80_TO_INT32_IN_MEM:
21204 case X86::FP80_TO_INT64_IN_MEM: {
21205 MachineFunction *F = BB->getParent();
21206 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21207 DebugLoc DL = MI->getDebugLoc();
21209 // Change the floating point control register to use "round towards zero"
21210 // mode when truncating to an integer value.
21211 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21212 addFrameReference(BuildMI(*BB, MI, DL,
21213 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21215 // Load the old value of the high byte of the control word...
21217 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21218 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21221 // Set the high part to be round to zero...
21222 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21225 // Reload the modified control word now...
21226 addFrameReference(BuildMI(*BB, MI, DL,
21227 TII->get(X86::FLDCW16m)), CWFrameIdx);
21229 // Restore the memory image of control word to original value
21230 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21233 // Get the X86 opcode to use.
21235 switch (MI->getOpcode()) {
21236 default: llvm_unreachable("illegal opcode!");
21237 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21238 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21239 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21240 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21241 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21242 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21243 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21244 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21245 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21249 MachineOperand &Op = MI->getOperand(0);
21251 AM.BaseType = X86AddressMode::RegBase;
21252 AM.Base.Reg = Op.getReg();
21254 AM.BaseType = X86AddressMode::FrameIndexBase;
21255 AM.Base.FrameIndex = Op.getIndex();
21257 Op = MI->getOperand(1);
21259 AM.Scale = Op.getImm();
21260 Op = MI->getOperand(2);
21262 AM.IndexReg = Op.getImm();
21263 Op = MI->getOperand(3);
21264 if (Op.isGlobal()) {
21265 AM.GV = Op.getGlobal();
21267 AM.Disp = Op.getImm();
21269 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21270 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21272 // Reload the original control word now.
21273 addFrameReference(BuildMI(*BB, MI, DL,
21274 TII->get(X86::FLDCW16m)), CWFrameIdx);
21276 MI->eraseFromParent(); // The pseudo instruction is gone now.
21279 // String/text processing lowering.
21280 case X86::PCMPISTRM128REG:
21281 case X86::VPCMPISTRM128REG:
21282 case X86::PCMPISTRM128MEM:
21283 case X86::VPCMPISTRM128MEM:
21284 case X86::PCMPESTRM128REG:
21285 case X86::VPCMPESTRM128REG:
21286 case X86::PCMPESTRM128MEM:
21287 case X86::VPCMPESTRM128MEM:
21288 assert(Subtarget->hasSSE42() &&
21289 "Target must have SSE4.2 or AVX features enabled");
21290 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21292 // String/text processing lowering.
21293 case X86::PCMPISTRIREG:
21294 case X86::VPCMPISTRIREG:
21295 case X86::PCMPISTRIMEM:
21296 case X86::VPCMPISTRIMEM:
21297 case X86::PCMPESTRIREG:
21298 case X86::VPCMPESTRIREG:
21299 case X86::PCMPESTRIMEM:
21300 case X86::VPCMPESTRIMEM:
21301 assert(Subtarget->hasSSE42() &&
21302 "Target must have SSE4.2 or AVX features enabled");
21303 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21305 // Thread synchronization.
21307 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21312 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21314 case X86::VASTART_SAVE_XMM_REGS:
21315 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21317 case X86::VAARG_64:
21318 return EmitVAARG64WithCustomInserter(MI, BB);
21320 case X86::EH_SjLj_SetJmp32:
21321 case X86::EH_SjLj_SetJmp64:
21322 return emitEHSjLjSetJmp(MI, BB);
21324 case X86::EH_SjLj_LongJmp32:
21325 case X86::EH_SjLj_LongJmp64:
21326 return emitEHSjLjLongJmp(MI, BB);
21328 case TargetOpcode::STACKMAP:
21329 case TargetOpcode::PATCHPOINT:
21330 return emitPatchPoint(MI, BB);
21332 case X86::VFMADDPDr213r:
21333 case X86::VFMADDPSr213r:
21334 case X86::VFMADDSDr213r:
21335 case X86::VFMADDSSr213r:
21336 case X86::VFMSUBPDr213r:
21337 case X86::VFMSUBPSr213r:
21338 case X86::VFMSUBSDr213r:
21339 case X86::VFMSUBSSr213r:
21340 case X86::VFNMADDPDr213r:
21341 case X86::VFNMADDPSr213r:
21342 case X86::VFNMADDSDr213r:
21343 case X86::VFNMADDSSr213r:
21344 case X86::VFNMSUBPDr213r:
21345 case X86::VFNMSUBPSr213r:
21346 case X86::VFNMSUBSDr213r:
21347 case X86::VFNMSUBSSr213r:
21348 case X86::VFMADDSUBPDr213r:
21349 case X86::VFMADDSUBPSr213r:
21350 case X86::VFMSUBADDPDr213r:
21351 case X86::VFMSUBADDPSr213r:
21352 case X86::VFMADDPDr213rY:
21353 case X86::VFMADDPSr213rY:
21354 case X86::VFMSUBPDr213rY:
21355 case X86::VFMSUBPSr213rY:
21356 case X86::VFNMADDPDr213rY:
21357 case X86::VFNMADDPSr213rY:
21358 case X86::VFNMSUBPDr213rY:
21359 case X86::VFNMSUBPSr213rY:
21360 case X86::VFMADDSUBPDr213rY:
21361 case X86::VFMADDSUBPSr213rY:
21362 case X86::VFMSUBADDPDr213rY:
21363 case X86::VFMSUBADDPSr213rY:
21364 return emitFMA3Instr(MI, BB);
21368 //===----------------------------------------------------------------------===//
21369 // X86 Optimization Hooks
21370 //===----------------------------------------------------------------------===//
21372 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21375 const SelectionDAG &DAG,
21376 unsigned Depth) const {
21377 unsigned BitWidth = KnownZero.getBitWidth();
21378 unsigned Opc = Op.getOpcode();
21379 assert((Opc >= ISD::BUILTIN_OP_END ||
21380 Opc == ISD::INTRINSIC_WO_CHAIN ||
21381 Opc == ISD::INTRINSIC_W_CHAIN ||
21382 Opc == ISD::INTRINSIC_VOID) &&
21383 "Should use MaskedValueIsZero if you don't know whether Op"
21384 " is a target node!");
21386 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21400 // These nodes' second result is a boolean.
21401 if (Op.getResNo() == 0)
21404 case X86ISD::SETCC:
21405 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21407 case ISD::INTRINSIC_WO_CHAIN: {
21408 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21409 unsigned NumLoBits = 0;
21412 case Intrinsic::x86_sse_movmsk_ps:
21413 case Intrinsic::x86_avx_movmsk_ps_256:
21414 case Intrinsic::x86_sse2_movmsk_pd:
21415 case Intrinsic::x86_avx_movmsk_pd_256:
21416 case Intrinsic::x86_mmx_pmovmskb:
21417 case Intrinsic::x86_sse2_pmovmskb_128:
21418 case Intrinsic::x86_avx2_pmovmskb: {
21419 // High bits of movmskp{s|d}, pmovmskb are known zero.
21421 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21422 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21423 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21424 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21425 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21426 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21427 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21428 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21430 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21439 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21441 const SelectionDAG &,
21442 unsigned Depth) const {
21443 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21444 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21445 return Op.getValueType().getScalarType().getSizeInBits();
21451 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21452 /// node is a GlobalAddress + offset.
21453 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21454 const GlobalValue* &GA,
21455 int64_t &Offset) const {
21456 if (N->getOpcode() == X86ISD::Wrapper) {
21457 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21458 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21459 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21463 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21466 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21467 /// same as extracting the high 128-bit part of 256-bit vector and then
21468 /// inserting the result into the low part of a new 256-bit vector
21469 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21470 EVT VT = SVOp->getValueType(0);
21471 unsigned NumElems = VT.getVectorNumElements();
21473 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21474 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21475 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21476 SVOp->getMaskElt(j) >= 0)
21482 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21483 /// same as extracting the low 128-bit part of 256-bit vector and then
21484 /// inserting the result into the high part of a new 256-bit vector
21485 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21486 EVT VT = SVOp->getValueType(0);
21487 unsigned NumElems = VT.getVectorNumElements();
21489 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21490 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21491 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21492 SVOp->getMaskElt(j) >= 0)
21498 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21499 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21500 TargetLowering::DAGCombinerInfo &DCI,
21501 const X86Subtarget* Subtarget) {
21503 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21504 SDValue V1 = SVOp->getOperand(0);
21505 SDValue V2 = SVOp->getOperand(1);
21506 EVT VT = SVOp->getValueType(0);
21507 unsigned NumElems = VT.getVectorNumElements();
21509 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21510 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21514 // V UNDEF BUILD_VECTOR UNDEF
21516 // CONCAT_VECTOR CONCAT_VECTOR
21519 // RESULT: V + zero extended
21521 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21522 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21523 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21526 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21529 // To match the shuffle mask, the first half of the mask should
21530 // be exactly the first vector, and all the rest a splat with the
21531 // first element of the second one.
21532 for (unsigned i = 0; i != NumElems/2; ++i)
21533 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21534 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21537 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21538 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21539 if (Ld->hasNUsesOfValue(1, 0)) {
21540 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21541 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21543 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21545 Ld->getPointerInfo(),
21546 Ld->getAlignment(),
21547 false/*isVolatile*/, true/*ReadMem*/,
21548 false/*WriteMem*/);
21550 // Make sure the newly-created LOAD is in the same position as Ld in
21551 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21552 // and update uses of Ld's output chain to use the TokenFactor.
21553 if (Ld->hasAnyUseOfValue(1)) {
21554 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21555 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21556 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21557 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21558 SDValue(ResNode.getNode(), 1));
21561 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21565 // Emit a zeroed vector and insert the desired subvector on its
21567 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21568 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21569 return DCI.CombineTo(N, InsV);
21572 //===--------------------------------------------------------------------===//
21573 // Combine some shuffles into subvector extracts and inserts:
21576 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21577 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21578 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21579 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21580 return DCI.CombineTo(N, InsV);
21583 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21584 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21585 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21586 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21587 return DCI.CombineTo(N, InsV);
21593 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21596 /// This is the leaf of the recursive combinine below. When we have found some
21597 /// chain of single-use x86 shuffle instructions and accumulated the combined
21598 /// shuffle mask represented by them, this will try to pattern match that mask
21599 /// into either a single instruction if there is a special purpose instruction
21600 /// for this operation, or into a PSHUFB instruction which is a fully general
21601 /// instruction but should only be used to replace chains over a certain depth.
21602 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21603 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21604 TargetLowering::DAGCombinerInfo &DCI,
21605 const X86Subtarget *Subtarget) {
21606 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21608 // Find the operand that enters the chain. Note that multiple uses are OK
21609 // here, we're not going to remove the operand we find.
21610 SDValue Input = Op.getOperand(0);
21611 while (Input.getOpcode() == ISD::BITCAST)
21612 Input = Input.getOperand(0);
21614 MVT VT = Input.getSimpleValueType();
21615 MVT RootVT = Root.getSimpleValueType();
21618 // Just remove no-op shuffle masks.
21619 if (Mask.size() == 1) {
21620 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21625 // Use the float domain if the operand type is a floating point type.
21626 bool FloatDomain = VT.isFloatingPoint();
21628 // For floating point shuffles, we don't have free copies in the shuffle
21629 // instructions or the ability to load as part of the instruction, so
21630 // canonicalize their shuffles to UNPCK or MOV variants.
21632 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21633 // vectors because it can have a load folded into it that UNPCK cannot. This
21634 // doesn't preclude something switching to the shorter encoding post-RA.
21636 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21637 bool Lo = Mask.equals(0, 0);
21640 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21641 // is no slower than UNPCKLPD but has the option to fold the input operand
21642 // into even an unaligned memory load.
21643 if (Lo && Subtarget->hasSSE3()) {
21644 Shuffle = X86ISD::MOVDDUP;
21645 ShuffleVT = MVT::v2f64;
21647 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21648 // than the UNPCK variants.
21649 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21650 ShuffleVT = MVT::v4f32;
21652 if (Depth == 1 && Root->getOpcode() == Shuffle)
21653 return false; // Nothing to do!
21654 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21655 DCI.AddToWorklist(Op.getNode());
21656 if (Shuffle == X86ISD::MOVDDUP)
21657 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21659 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21660 DCI.AddToWorklist(Op.getNode());
21661 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21665 if (Subtarget->hasSSE3() &&
21666 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21667 bool Lo = Mask.equals(0, 0, 2, 2);
21668 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21669 MVT ShuffleVT = MVT::v4f32;
21670 if (Depth == 1 && Root->getOpcode() == Shuffle)
21671 return false; // Nothing to do!
21672 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21673 DCI.AddToWorklist(Op.getNode());
21674 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21675 DCI.AddToWorklist(Op.getNode());
21676 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21680 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21681 bool Lo = Mask.equals(0, 0, 1, 1);
21682 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21683 MVT ShuffleVT = MVT::v4f32;
21684 if (Depth == 1 && Root->getOpcode() == Shuffle)
21685 return false; // Nothing to do!
21686 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21687 DCI.AddToWorklist(Op.getNode());
21688 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21689 DCI.AddToWorklist(Op.getNode());
21690 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21696 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21697 // variants as none of these have single-instruction variants that are
21698 // superior to the UNPCK formulation.
21699 if (!FloatDomain &&
21700 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21701 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21702 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21703 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21705 bool Lo = Mask[0] == 0;
21706 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21707 if (Depth == 1 && Root->getOpcode() == Shuffle)
21708 return false; // Nothing to do!
21710 switch (Mask.size()) {
21712 ShuffleVT = MVT::v8i16;
21715 ShuffleVT = MVT::v16i8;
21718 llvm_unreachable("Impossible mask size!");
21720 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21721 DCI.AddToWorklist(Op.getNode());
21722 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21723 DCI.AddToWorklist(Op.getNode());
21724 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21729 // Don't try to re-form single instruction chains under any circumstances now
21730 // that we've done encoding canonicalization for them.
21734 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21735 // can replace them with a single PSHUFB instruction profitably. Intel's
21736 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21737 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21738 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21739 SmallVector<SDValue, 16> PSHUFBMask;
21740 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21741 int Ratio = 16 / Mask.size();
21742 for (unsigned i = 0; i < 16; ++i) {
21743 if (Mask[i / Ratio] == SM_SentinelUndef) {
21744 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21747 int M = Mask[i / Ratio] != SM_SentinelZero
21748 ? Ratio * Mask[i / Ratio] + i % Ratio
21750 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21752 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21753 DCI.AddToWorklist(Op.getNode());
21754 SDValue PSHUFBMaskOp =
21755 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21756 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21757 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21758 DCI.AddToWorklist(Op.getNode());
21759 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21764 // Failed to find any combines.
21768 /// \brief Fully generic combining of x86 shuffle instructions.
21770 /// This should be the last combine run over the x86 shuffle instructions. Once
21771 /// they have been fully optimized, this will recursively consider all chains
21772 /// of single-use shuffle instructions, build a generic model of the cumulative
21773 /// shuffle operation, and check for simpler instructions which implement this
21774 /// operation. We use this primarily for two purposes:
21776 /// 1) Collapse generic shuffles to specialized single instructions when
21777 /// equivalent. In most cases, this is just an encoding size win, but
21778 /// sometimes we will collapse multiple generic shuffles into a single
21779 /// special-purpose shuffle.
21780 /// 2) Look for sequences of shuffle instructions with 3 or more total
21781 /// instructions, and replace them with the slightly more expensive SSSE3
21782 /// PSHUFB instruction if available. We do this as the last combining step
21783 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21784 /// a suitable short sequence of other instructions. The PHUFB will either
21785 /// use a register or have to read from memory and so is slightly (but only
21786 /// slightly) more expensive than the other shuffle instructions.
21788 /// Because this is inherently a quadratic operation (for each shuffle in
21789 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21790 /// This should never be an issue in practice as the shuffle lowering doesn't
21791 /// produce sequences of more than 8 instructions.
21793 /// FIXME: We will currently miss some cases where the redundant shuffling
21794 /// would simplify under the threshold for PSHUFB formation because of
21795 /// combine-ordering. To fix this, we should do the redundant instruction
21796 /// combining in this recursive walk.
21797 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21798 ArrayRef<int> RootMask,
21799 int Depth, bool HasPSHUFB,
21801 TargetLowering::DAGCombinerInfo &DCI,
21802 const X86Subtarget *Subtarget) {
21803 // Bound the depth of our recursive combine because this is ultimately
21804 // quadratic in nature.
21808 // Directly rip through bitcasts to find the underlying operand.
21809 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21810 Op = Op.getOperand(0);
21812 MVT VT = Op.getSimpleValueType();
21813 if (!VT.isVector())
21814 return false; // Bail if we hit a non-vector.
21815 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21816 // version should be added.
21817 if (VT.getSizeInBits() != 128)
21820 assert(Root.getSimpleValueType().isVector() &&
21821 "Shuffles operate on vector types!");
21822 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21823 "Can only combine shuffles of the same vector register size.");
21825 if (!isTargetShuffle(Op.getOpcode()))
21827 SmallVector<int, 16> OpMask;
21829 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21830 // We only can combine unary shuffles which we can decode the mask for.
21831 if (!HaveMask || !IsUnary)
21834 assert(VT.getVectorNumElements() == OpMask.size() &&
21835 "Different mask size from vector size!");
21836 assert(((RootMask.size() > OpMask.size() &&
21837 RootMask.size() % OpMask.size() == 0) ||
21838 (OpMask.size() > RootMask.size() &&
21839 OpMask.size() % RootMask.size() == 0) ||
21840 OpMask.size() == RootMask.size()) &&
21841 "The smaller number of elements must divide the larger.");
21842 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21843 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21844 assert(((RootRatio == 1 && OpRatio == 1) ||
21845 (RootRatio == 1) != (OpRatio == 1)) &&
21846 "Must not have a ratio for both incoming and op masks!");
21848 SmallVector<int, 16> Mask;
21849 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21851 // Merge this shuffle operation's mask into our accumulated mask. Note that
21852 // this shuffle's mask will be the first applied to the input, followed by the
21853 // root mask to get us all the way to the root value arrangement. The reason
21854 // for this order is that we are recursing up the operation chain.
21855 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21856 int RootIdx = i / RootRatio;
21857 if (RootMask[RootIdx] < 0) {
21858 // This is a zero or undef lane, we're done.
21859 Mask.push_back(RootMask[RootIdx]);
21863 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21864 int OpIdx = RootMaskedIdx / OpRatio;
21865 if (OpMask[OpIdx] < 0) {
21866 // The incoming lanes are zero or undef, it doesn't matter which ones we
21868 Mask.push_back(OpMask[OpIdx]);
21872 // Ok, we have non-zero lanes, map them through.
21873 Mask.push_back(OpMask[OpIdx] * OpRatio +
21874 RootMaskedIdx % OpRatio);
21877 // See if we can recurse into the operand to combine more things.
21878 switch (Op.getOpcode()) {
21879 case X86ISD::PSHUFB:
21881 case X86ISD::PSHUFD:
21882 case X86ISD::PSHUFHW:
21883 case X86ISD::PSHUFLW:
21884 if (Op.getOperand(0).hasOneUse() &&
21885 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21886 HasPSHUFB, DAG, DCI, Subtarget))
21890 case X86ISD::UNPCKL:
21891 case X86ISD::UNPCKH:
21892 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21893 // We can't check for single use, we have to check that this shuffle is the only user.
21894 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21895 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21896 HasPSHUFB, DAG, DCI, Subtarget))
21901 // Minor canonicalization of the accumulated shuffle mask to make it easier
21902 // to match below. All this does is detect masks with squential pairs of
21903 // elements, and shrink them to the half-width mask. It does this in a loop
21904 // so it will reduce the size of the mask to the minimal width mask which
21905 // performs an equivalent shuffle.
21906 SmallVector<int, 16> WidenedMask;
21907 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21908 Mask = std::move(WidenedMask);
21909 WidenedMask.clear();
21912 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21916 /// \brief Get the PSHUF-style mask from PSHUF node.
21918 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21919 /// PSHUF-style masks that can be reused with such instructions.
21920 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21921 SmallVector<int, 4> Mask;
21923 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21927 switch (N.getOpcode()) {
21928 case X86ISD::PSHUFD:
21930 case X86ISD::PSHUFLW:
21933 case X86ISD::PSHUFHW:
21934 Mask.erase(Mask.begin(), Mask.begin() + 4);
21935 for (int &M : Mask)
21939 llvm_unreachable("No valid shuffle instruction found!");
21943 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21945 /// We walk up the chain and look for a combinable shuffle, skipping over
21946 /// shuffles that we could hoist this shuffle's transformation past without
21947 /// altering anything.
21949 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21951 TargetLowering::DAGCombinerInfo &DCI) {
21952 assert(N.getOpcode() == X86ISD::PSHUFD &&
21953 "Called with something other than an x86 128-bit half shuffle!");
21956 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21957 // of the shuffles in the chain so that we can form a fresh chain to replace
21959 SmallVector<SDValue, 8> Chain;
21960 SDValue V = N.getOperand(0);
21961 for (; V.hasOneUse(); V = V.getOperand(0)) {
21962 switch (V.getOpcode()) {
21964 return SDValue(); // Nothing combined!
21967 // Skip bitcasts as we always know the type for the target specific
21971 case X86ISD::PSHUFD:
21972 // Found another dword shuffle.
21975 case X86ISD::PSHUFLW:
21976 // Check that the low words (being shuffled) are the identity in the
21977 // dword shuffle, and the high words are self-contained.
21978 if (Mask[0] != 0 || Mask[1] != 1 ||
21979 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21982 Chain.push_back(V);
21985 case X86ISD::PSHUFHW:
21986 // Check that the high words (being shuffled) are the identity in the
21987 // dword shuffle, and the low words are self-contained.
21988 if (Mask[2] != 2 || Mask[3] != 3 ||
21989 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21992 Chain.push_back(V);
21995 case X86ISD::UNPCKL:
21996 case X86ISD::UNPCKH:
21997 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21998 // shuffle into a preceding word shuffle.
21999 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22002 // Search for a half-shuffle which we can combine with.
22003 unsigned CombineOp =
22004 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22005 if (V.getOperand(0) != V.getOperand(1) ||
22006 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22008 Chain.push_back(V);
22009 V = V.getOperand(0);
22011 switch (V.getOpcode()) {
22013 return SDValue(); // Nothing to combine.
22015 case X86ISD::PSHUFLW:
22016 case X86ISD::PSHUFHW:
22017 if (V.getOpcode() == CombineOp)
22020 Chain.push_back(V);
22024 V = V.getOperand(0);
22028 } while (V.hasOneUse());
22031 // Break out of the loop if we break out of the switch.
22035 if (!V.hasOneUse())
22036 // We fell out of the loop without finding a viable combining instruction.
22039 // Merge this node's mask and our incoming mask.
22040 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22041 for (int &M : Mask)
22043 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22044 getV4X86ShuffleImm8ForMask(Mask, DAG));
22046 // Rebuild the chain around this new shuffle.
22047 while (!Chain.empty()) {
22048 SDValue W = Chain.pop_back_val();
22050 if (V.getValueType() != W.getOperand(0).getValueType())
22051 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22053 switch (W.getOpcode()) {
22055 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22057 case X86ISD::UNPCKL:
22058 case X86ISD::UNPCKH:
22059 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22062 case X86ISD::PSHUFD:
22063 case X86ISD::PSHUFLW:
22064 case X86ISD::PSHUFHW:
22065 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22069 if (V.getValueType() != N.getValueType())
22070 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22072 // Return the new chain to replace N.
22076 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22078 /// We walk up the chain, skipping shuffles of the other half and looking
22079 /// through shuffles which switch halves trying to find a shuffle of the same
22080 /// pair of dwords.
22081 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22083 TargetLowering::DAGCombinerInfo &DCI) {
22085 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22086 "Called with something other than an x86 128-bit half shuffle!");
22088 unsigned CombineOpcode = N.getOpcode();
22090 // Walk up a single-use chain looking for a combinable shuffle.
22091 SDValue V = N.getOperand(0);
22092 for (; V.hasOneUse(); V = V.getOperand(0)) {
22093 switch (V.getOpcode()) {
22095 return false; // Nothing combined!
22098 // Skip bitcasts as we always know the type for the target specific
22102 case X86ISD::PSHUFLW:
22103 case X86ISD::PSHUFHW:
22104 if (V.getOpcode() == CombineOpcode)
22107 // Other-half shuffles are no-ops.
22110 // Break out of the loop if we break out of the switch.
22114 if (!V.hasOneUse())
22115 // We fell out of the loop without finding a viable combining instruction.
22118 // Combine away the bottom node as its shuffle will be accumulated into
22119 // a preceding shuffle.
22120 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22122 // Record the old value.
22125 // Merge this node's mask and our incoming mask (adjusted to account for all
22126 // the pshufd instructions encountered).
22127 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22128 for (int &M : Mask)
22130 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22131 getV4X86ShuffleImm8ForMask(Mask, DAG));
22133 // Check that the shuffles didn't cancel each other out. If not, we need to
22134 // combine to the new one.
22136 // Replace the combinable shuffle with the combined one, updating all users
22137 // so that we re-evaluate the chain here.
22138 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22143 /// \brief Try to combine x86 target specific shuffles.
22144 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22145 TargetLowering::DAGCombinerInfo &DCI,
22146 const X86Subtarget *Subtarget) {
22148 MVT VT = N.getSimpleValueType();
22149 SmallVector<int, 4> Mask;
22151 switch (N.getOpcode()) {
22152 case X86ISD::PSHUFD:
22153 case X86ISD::PSHUFLW:
22154 case X86ISD::PSHUFHW:
22155 Mask = getPSHUFShuffleMask(N);
22156 assert(Mask.size() == 4);
22162 // Nuke no-op shuffles that show up after combining.
22163 if (isNoopShuffleMask(Mask))
22164 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22166 // Look for simplifications involving one or two shuffle instructions.
22167 SDValue V = N.getOperand(0);
22168 switch (N.getOpcode()) {
22171 case X86ISD::PSHUFLW:
22172 case X86ISD::PSHUFHW:
22173 assert(VT == MVT::v8i16);
22176 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22177 return SDValue(); // We combined away this shuffle, so we're done.
22179 // See if this reduces to a PSHUFD which is no more expensive and can
22180 // combine with more operations. Note that it has to at least flip the
22181 // dwords as otherwise it would have been removed as a no-op.
22182 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22183 int DMask[] = {0, 1, 2, 3};
22184 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22185 DMask[DOffset + 0] = DOffset + 1;
22186 DMask[DOffset + 1] = DOffset + 0;
22187 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22188 DCI.AddToWorklist(V.getNode());
22189 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22190 getV4X86ShuffleImm8ForMask(DMask, DAG));
22191 DCI.AddToWorklist(V.getNode());
22192 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22195 // Look for shuffle patterns which can be implemented as a single unpack.
22196 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22197 // only works when we have a PSHUFD followed by two half-shuffles.
22198 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22199 (V.getOpcode() == X86ISD::PSHUFLW ||
22200 V.getOpcode() == X86ISD::PSHUFHW) &&
22201 V.getOpcode() != N.getOpcode() &&
22203 SDValue D = V.getOperand(0);
22204 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22205 D = D.getOperand(0);
22206 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22207 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22208 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22209 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22210 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22212 for (int i = 0; i < 4; ++i) {
22213 WordMask[i + NOffset] = Mask[i] + NOffset;
22214 WordMask[i + VOffset] = VMask[i] + VOffset;
22216 // Map the word mask through the DWord mask.
22218 for (int i = 0; i < 8; ++i)
22219 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22220 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22221 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22222 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22223 std::begin(UnpackLoMask)) ||
22224 std::equal(std::begin(MappedMask), std::end(MappedMask),
22225 std::begin(UnpackHiMask))) {
22226 // We can replace all three shuffles with an unpack.
22227 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22228 DCI.AddToWorklist(V.getNode());
22229 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22231 DL, MVT::v8i16, V, V);
22238 case X86ISD::PSHUFD:
22239 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22248 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22250 /// We combine this directly on the abstract vector shuffle nodes so it is
22251 /// easier to generically match. We also insert dummy vector shuffle nodes for
22252 /// the operands which explicitly discard the lanes which are unused by this
22253 /// operation to try to flow through the rest of the combiner the fact that
22254 /// they're unused.
22255 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22257 EVT VT = N->getValueType(0);
22259 // We only handle target-independent shuffles.
22260 // FIXME: It would be easy and harmless to use the target shuffle mask
22261 // extraction tool to support more.
22262 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22265 auto *SVN = cast<ShuffleVectorSDNode>(N);
22266 ArrayRef<int> Mask = SVN->getMask();
22267 SDValue V1 = N->getOperand(0);
22268 SDValue V2 = N->getOperand(1);
22270 // We require the first shuffle operand to be the SUB node, and the second to
22271 // be the ADD node.
22272 // FIXME: We should support the commuted patterns.
22273 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22276 // If there are other uses of these operations we can't fold them.
22277 if (!V1->hasOneUse() || !V2->hasOneUse())
22280 // Ensure that both operations have the same operands. Note that we can
22281 // commute the FADD operands.
22282 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22283 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22284 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22287 // We're looking for blends between FADD and FSUB nodes. We insist on these
22288 // nodes being lined up in a specific expected pattern.
22289 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22290 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22291 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22294 // Only specific types are legal at this point, assert so we notice if and
22295 // when these change.
22296 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22297 VT == MVT::v4f64) &&
22298 "Unknown vector type encountered!");
22300 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22303 /// PerformShuffleCombine - Performs several different shuffle combines.
22304 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22305 TargetLowering::DAGCombinerInfo &DCI,
22306 const X86Subtarget *Subtarget) {
22308 SDValue N0 = N->getOperand(0);
22309 SDValue N1 = N->getOperand(1);
22310 EVT VT = N->getValueType(0);
22312 // Don't create instructions with illegal types after legalize types has run.
22313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22314 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22317 // If we have legalized the vector types, look for blends of FADD and FSUB
22318 // nodes that we can fuse into an ADDSUB node.
22319 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22320 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22323 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22324 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22325 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22326 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22328 // During Type Legalization, when promoting illegal vector types,
22329 // the backend might introduce new shuffle dag nodes and bitcasts.
22331 // This code performs the following transformation:
22332 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22333 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22335 // We do this only if both the bitcast and the BINOP dag nodes have
22336 // one use. Also, perform this transformation only if the new binary
22337 // operation is legal. This is to avoid introducing dag nodes that
22338 // potentially need to be further expanded (or custom lowered) into a
22339 // less optimal sequence of dag nodes.
22340 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22341 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22342 N0.getOpcode() == ISD::BITCAST) {
22343 SDValue BC0 = N0.getOperand(0);
22344 EVT SVT = BC0.getValueType();
22345 unsigned Opcode = BC0.getOpcode();
22346 unsigned NumElts = VT.getVectorNumElements();
22348 if (BC0.hasOneUse() && SVT.isVector() &&
22349 SVT.getVectorNumElements() * 2 == NumElts &&
22350 TLI.isOperationLegal(Opcode, VT)) {
22351 bool CanFold = false;
22363 unsigned SVTNumElts = SVT.getVectorNumElements();
22364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22365 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22366 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22367 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22368 CanFold = SVOp->getMaskElt(i) < 0;
22371 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22372 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22373 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22374 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22379 // Only handle 128 wide vector from here on.
22380 if (!VT.is128BitVector())
22383 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22384 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22385 // consecutive, non-overlapping, and in the right order.
22386 SmallVector<SDValue, 16> Elts;
22387 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22388 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22390 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22394 if (isTargetShuffle(N->getOpcode())) {
22396 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22397 if (Shuffle.getNode())
22400 // Try recursively combining arbitrary sequences of x86 shuffle
22401 // instructions into higher-order shuffles. We do this after combining
22402 // specific PSHUF instruction sequences into their minimal form so that we
22403 // can evaluate how many specialized shuffle instructions are involved in
22404 // a particular chain.
22405 SmallVector<int, 1> NonceMask; // Just a placeholder.
22406 NonceMask.push_back(0);
22407 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22408 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22410 return SDValue(); // This routine will use CombineTo to replace N.
22416 /// PerformTruncateCombine - Converts truncate operation to
22417 /// a sequence of vector shuffle operations.
22418 /// It is possible when we truncate 256-bit vector to 128-bit vector
22419 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22420 TargetLowering::DAGCombinerInfo &DCI,
22421 const X86Subtarget *Subtarget) {
22425 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22426 /// specific shuffle of a load can be folded into a single element load.
22427 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22428 /// shuffles have been custom lowered so we need to handle those here.
22429 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22430 TargetLowering::DAGCombinerInfo &DCI) {
22431 if (DCI.isBeforeLegalizeOps())
22434 SDValue InVec = N->getOperand(0);
22435 SDValue EltNo = N->getOperand(1);
22437 if (!isa<ConstantSDNode>(EltNo))
22440 EVT OriginalVT = InVec.getValueType();
22442 if (InVec.getOpcode() == ISD::BITCAST) {
22443 // Don't duplicate a load with other uses.
22444 if (!InVec.hasOneUse())
22446 EVT BCVT = InVec.getOperand(0).getValueType();
22447 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22449 InVec = InVec.getOperand(0);
22452 EVT CurrentVT = InVec.getValueType();
22454 if (!isTargetShuffle(InVec.getOpcode()))
22457 // Don't duplicate a load with other uses.
22458 if (!InVec.hasOneUse())
22461 SmallVector<int, 16> ShuffleMask;
22463 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22464 ShuffleMask, UnaryShuffle))
22467 // Select the input vector, guarding against out of range extract vector.
22468 unsigned NumElems = CurrentVT.getVectorNumElements();
22469 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22470 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22471 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22472 : InVec.getOperand(1);
22474 // If inputs to shuffle are the same for both ops, then allow 2 uses
22475 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22477 if (LdNode.getOpcode() == ISD::BITCAST) {
22478 // Don't duplicate a load with other uses.
22479 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22482 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22483 LdNode = LdNode.getOperand(0);
22486 if (!ISD::isNormalLoad(LdNode.getNode()))
22489 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22491 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22494 EVT EltVT = N->getValueType(0);
22495 // If there's a bitcast before the shuffle, check if the load type and
22496 // alignment is valid.
22497 unsigned Align = LN0->getAlignment();
22498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22499 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22500 EltVT.getTypeForEVT(*DAG.getContext()));
22502 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22505 // All checks match so transform back to vector_shuffle so that DAG combiner
22506 // can finish the job
22509 // Create shuffle node taking into account the case that its a unary shuffle
22510 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22511 : InVec.getOperand(1);
22512 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22513 InVec.getOperand(0), Shuffle,
22515 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22516 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22520 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22521 /// generation and convert it from being a bunch of shuffles and extracts
22522 /// to a simple store and scalar loads to extract the elements.
22523 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22524 TargetLowering::DAGCombinerInfo &DCI) {
22525 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22526 if (NewOp.getNode())
22529 SDValue InputVector = N->getOperand(0);
22531 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22532 // from mmx to v2i32 has a single usage.
22533 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22534 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22535 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22536 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22537 N->getValueType(0),
22538 InputVector.getNode()->getOperand(0));
22540 // Only operate on vectors of 4 elements, where the alternative shuffling
22541 // gets to be more expensive.
22542 if (InputVector.getValueType() != MVT::v4i32)
22545 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22546 // single use which is a sign-extend or zero-extend, and all elements are
22548 SmallVector<SDNode *, 4> Uses;
22549 unsigned ExtractedElements = 0;
22550 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22551 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22552 if (UI.getUse().getResNo() != InputVector.getResNo())
22555 SDNode *Extract = *UI;
22556 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22559 if (Extract->getValueType(0) != MVT::i32)
22561 if (!Extract->hasOneUse())
22563 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22564 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22566 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22569 // Record which element was extracted.
22570 ExtractedElements |=
22571 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22573 Uses.push_back(Extract);
22576 // If not all the elements were used, this may not be worthwhile.
22577 if (ExtractedElements != 15)
22580 // Ok, we've now decided to do the transformation.
22581 SDLoc dl(InputVector);
22583 // Store the value to a temporary stack slot.
22584 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22585 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22586 MachinePointerInfo(), false, false, 0);
22588 // Replace each use (extract) with a load of the appropriate element.
22589 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22590 UE = Uses.end(); UI != UE; ++UI) {
22591 SDNode *Extract = *UI;
22593 // cOMpute the element's address.
22594 SDValue Idx = Extract->getOperand(1);
22596 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22597 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22598 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22599 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22601 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22602 StackPtr, OffsetVal);
22604 // Load the scalar.
22605 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22606 ScalarAddr, MachinePointerInfo(),
22607 false, false, false, 0);
22609 // Replace the exact with the load.
22610 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22613 // The replacement was made in place; don't return anything.
22617 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22618 static std::pair<unsigned, bool>
22619 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22620 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22621 if (!VT.isVector())
22622 return std::make_pair(0, false);
22624 bool NeedSplit = false;
22625 switch (VT.getSimpleVT().SimpleTy) {
22626 default: return std::make_pair(0, false);
22630 if (!Subtarget->hasAVX2())
22632 if (!Subtarget->hasAVX())
22633 return std::make_pair(0, false);
22638 if (!Subtarget->hasSSE2())
22639 return std::make_pair(0, false);
22642 // SSE2 has only a small subset of the operations.
22643 bool hasUnsigned = Subtarget->hasSSE41() ||
22644 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22645 bool hasSigned = Subtarget->hasSSE41() ||
22646 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22648 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22651 // Check for x CC y ? x : y.
22652 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22653 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22658 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22661 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22664 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22667 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22669 // Check for x CC y ? y : x -- a min/max with reversed arms.
22670 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22671 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22676 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22679 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22682 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22685 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22689 return std::make_pair(Opc, NeedSplit);
22693 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22694 const X86Subtarget *Subtarget) {
22696 SDValue Cond = N->getOperand(0);
22697 SDValue LHS = N->getOperand(1);
22698 SDValue RHS = N->getOperand(2);
22700 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22701 SDValue CondSrc = Cond->getOperand(0);
22702 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22703 Cond = CondSrc->getOperand(0);
22706 MVT VT = N->getSimpleValueType(0);
22707 MVT EltVT = VT.getVectorElementType();
22708 unsigned NumElems = VT.getVectorNumElements();
22709 // There is no blend with immediate in AVX-512.
22710 if (VT.is512BitVector())
22713 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22715 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22718 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22721 // A vselect where all conditions and data are constants can be optimized into
22722 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22723 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22724 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22727 unsigned MaskValue = 0;
22728 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22731 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22732 for (unsigned i = 0; i < NumElems; ++i) {
22733 // Be sure we emit undef where we can.
22734 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22735 ShuffleMask[i] = -1;
22737 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22740 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22743 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22745 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22746 TargetLowering::DAGCombinerInfo &DCI,
22747 const X86Subtarget *Subtarget) {
22749 SDValue Cond = N->getOperand(0);
22750 // Get the LHS/RHS of the select.
22751 SDValue LHS = N->getOperand(1);
22752 SDValue RHS = N->getOperand(2);
22753 EVT VT = LHS.getValueType();
22754 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22756 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22757 // instructions match the semantics of the common C idiom x<y?x:y but not
22758 // x<=y?x:y, because of how they handle negative zero (which can be
22759 // ignored in unsafe-math mode).
22760 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22761 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22762 (Subtarget->hasSSE2() ||
22763 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22764 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22766 unsigned Opcode = 0;
22767 // Check for x CC y ? x : y.
22768 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22769 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22773 // Converting this to a min would handle NaNs incorrectly, and swapping
22774 // the operands would cause it to handle comparisons between positive
22775 // and negative zero incorrectly.
22776 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22777 if (!DAG.getTarget().Options.UnsafeFPMath &&
22778 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22780 std::swap(LHS, RHS);
22782 Opcode = X86ISD::FMIN;
22785 // Converting this to a min would handle comparisons between positive
22786 // and negative zero incorrectly.
22787 if (!DAG.getTarget().Options.UnsafeFPMath &&
22788 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22790 Opcode = X86ISD::FMIN;
22793 // Converting this to a min would handle both negative zeros and NaNs
22794 // incorrectly, but we can swap the operands to fix both.
22795 std::swap(LHS, RHS);
22799 Opcode = X86ISD::FMIN;
22803 // Converting this to a max would handle comparisons between positive
22804 // and negative zero incorrectly.
22805 if (!DAG.getTarget().Options.UnsafeFPMath &&
22806 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22808 Opcode = X86ISD::FMAX;
22811 // Converting this to a max would handle NaNs incorrectly, and swapping
22812 // the operands would cause it to handle comparisons between positive
22813 // and negative zero incorrectly.
22814 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22815 if (!DAG.getTarget().Options.UnsafeFPMath &&
22816 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22818 std::swap(LHS, RHS);
22820 Opcode = X86ISD::FMAX;
22823 // Converting this to a max would handle both negative zeros and NaNs
22824 // incorrectly, but we can swap the operands to fix both.
22825 std::swap(LHS, RHS);
22829 Opcode = X86ISD::FMAX;
22832 // Check for x CC y ? y : x -- a min/max with reversed arms.
22833 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22834 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22838 // Converting this to a min would handle comparisons between positive
22839 // and negative zero incorrectly, and swapping the operands would
22840 // cause it to handle NaNs incorrectly.
22841 if (!DAG.getTarget().Options.UnsafeFPMath &&
22842 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22843 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22845 std::swap(LHS, RHS);
22847 Opcode = X86ISD::FMIN;
22850 // Converting this to a min would handle NaNs incorrectly.
22851 if (!DAG.getTarget().Options.UnsafeFPMath &&
22852 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22854 Opcode = X86ISD::FMIN;
22857 // Converting this to a min would handle both negative zeros and NaNs
22858 // incorrectly, but we can swap the operands to fix both.
22859 std::swap(LHS, RHS);
22863 Opcode = X86ISD::FMIN;
22867 // Converting this to a max would handle NaNs incorrectly.
22868 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22870 Opcode = X86ISD::FMAX;
22873 // Converting this to a max would handle comparisons between positive
22874 // and negative zero incorrectly, and swapping the operands would
22875 // cause it to handle NaNs incorrectly.
22876 if (!DAG.getTarget().Options.UnsafeFPMath &&
22877 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22878 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22880 std::swap(LHS, RHS);
22882 Opcode = X86ISD::FMAX;
22885 // Converting this to a max would handle both negative zeros and NaNs
22886 // incorrectly, but we can swap the operands to fix both.
22887 std::swap(LHS, RHS);
22891 Opcode = X86ISD::FMAX;
22897 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22900 EVT CondVT = Cond.getValueType();
22901 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22902 CondVT.getVectorElementType() == MVT::i1) {
22903 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22904 // lowering on KNL. In this case we convert it to
22905 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22906 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22907 // Since SKX these selects have a proper lowering.
22908 EVT OpVT = LHS.getValueType();
22909 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22910 (OpVT.getVectorElementType() == MVT::i8 ||
22911 OpVT.getVectorElementType() == MVT::i16) &&
22912 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22913 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22914 DCI.AddToWorklist(Cond.getNode());
22915 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22918 // If this is a select between two integer constants, try to do some
22920 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22921 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22922 // Don't do this for crazy integer types.
22923 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22924 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22925 // so that TrueC (the true value) is larger than FalseC.
22926 bool NeedsCondInvert = false;
22928 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22929 // Efficiently invertible.
22930 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22931 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22932 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22933 NeedsCondInvert = true;
22934 std::swap(TrueC, FalseC);
22937 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22938 if (FalseC->getAPIntValue() == 0 &&
22939 TrueC->getAPIntValue().isPowerOf2()) {
22940 if (NeedsCondInvert) // Invert the condition if needed.
22941 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22942 DAG.getConstant(1, Cond.getValueType()));
22944 // Zero extend the condition if needed.
22945 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22947 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22948 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22949 DAG.getConstant(ShAmt, MVT::i8));
22952 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22953 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22954 if (NeedsCondInvert) // Invert the condition if needed.
22955 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22956 DAG.getConstant(1, Cond.getValueType()));
22958 // Zero extend the condition if needed.
22959 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22960 FalseC->getValueType(0), Cond);
22961 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22962 SDValue(FalseC, 0));
22965 // Optimize cases that will turn into an LEA instruction. This requires
22966 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22967 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22968 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22969 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22971 bool isFastMultiplier = false;
22973 switch ((unsigned char)Diff) {
22975 case 1: // result = add base, cond
22976 case 2: // result = lea base( , cond*2)
22977 case 3: // result = lea base(cond, cond*2)
22978 case 4: // result = lea base( , cond*4)
22979 case 5: // result = lea base(cond, cond*4)
22980 case 8: // result = lea base( , cond*8)
22981 case 9: // result = lea base(cond, cond*8)
22982 isFastMultiplier = true;
22987 if (isFastMultiplier) {
22988 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22989 if (NeedsCondInvert) // Invert the condition if needed.
22990 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22991 DAG.getConstant(1, Cond.getValueType()));
22993 // Zero extend the condition if needed.
22994 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22996 // Scale the condition by the difference.
22998 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22999 DAG.getConstant(Diff, Cond.getValueType()));
23001 // Add the base if non-zero.
23002 if (FalseC->getAPIntValue() != 0)
23003 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23004 SDValue(FalseC, 0));
23011 // Canonicalize max and min:
23012 // (x > y) ? x : y -> (x >= y) ? x : y
23013 // (x < y) ? x : y -> (x <= y) ? x : y
23014 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23015 // the need for an extra compare
23016 // against zero. e.g.
23017 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23019 // testl %edi, %edi
23021 // cmovgl %edi, %eax
23025 // cmovsl %eax, %edi
23026 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23027 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23028 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23029 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23034 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23035 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23036 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23037 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23042 // Early exit check
23043 if (!TLI.isTypeLegal(VT))
23046 // Match VSELECTs into subs with unsigned saturation.
23047 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23048 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23049 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23050 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23051 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23053 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23054 // left side invert the predicate to simplify logic below.
23056 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23058 CC = ISD::getSetCCInverse(CC, true);
23059 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23063 if (Other.getNode() && Other->getNumOperands() == 2 &&
23064 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23065 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23066 SDValue CondRHS = Cond->getOperand(1);
23068 // Look for a general sub with unsigned saturation first.
23069 // x >= y ? x-y : 0 --> subus x, y
23070 // x > y ? x-y : 0 --> subus x, y
23071 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23072 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23073 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23075 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23076 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23077 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23078 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23079 // If the RHS is a constant we have to reverse the const
23080 // canonicalization.
23081 // x > C-1 ? x+-C : 0 --> subus x, C
23082 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23083 CondRHSConst->getAPIntValue() ==
23084 (-OpRHSConst->getAPIntValue() - 1))
23085 return DAG.getNode(
23086 X86ISD::SUBUS, DL, VT, OpLHS,
23087 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23089 // Another special case: If C was a sign bit, the sub has been
23090 // canonicalized into a xor.
23091 // FIXME: Would it be better to use computeKnownBits to determine
23092 // whether it's safe to decanonicalize the xor?
23093 // x s< 0 ? x^C : 0 --> subus x, C
23094 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23095 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23096 OpRHSConst->getAPIntValue().isSignBit())
23097 // Note that we have to rebuild the RHS constant here to ensure we
23098 // don't rely on particular values of undef lanes.
23099 return DAG.getNode(
23100 X86ISD::SUBUS, DL, VT, OpLHS,
23101 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23106 // Try to match a min/max vector operation.
23107 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23108 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23109 unsigned Opc = ret.first;
23110 bool NeedSplit = ret.second;
23112 if (Opc && NeedSplit) {
23113 unsigned NumElems = VT.getVectorNumElements();
23114 // Extract the LHS vectors
23115 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23116 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23118 // Extract the RHS vectors
23119 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23120 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23122 // Create min/max for each subvector
23123 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23124 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23126 // Merge the result
23127 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23129 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23132 // Simplify vector selection if condition value type matches vselect
23134 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23135 assert(Cond.getValueType().isVector() &&
23136 "vector select expects a vector selector!");
23138 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23139 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23141 // Try invert the condition if true value is not all 1s and false value
23143 if (!TValIsAllOnes && !FValIsAllZeros &&
23144 // Check if the selector will be produced by CMPP*/PCMP*
23145 Cond.getOpcode() == ISD::SETCC &&
23146 // Check if SETCC has already been promoted
23147 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23148 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23149 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23151 if (TValIsAllZeros || FValIsAllOnes) {
23152 SDValue CC = Cond.getOperand(2);
23153 ISD::CondCode NewCC =
23154 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23155 Cond.getOperand(0).getValueType().isInteger());
23156 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23157 std::swap(LHS, RHS);
23158 TValIsAllOnes = FValIsAllOnes;
23159 FValIsAllZeros = TValIsAllZeros;
23163 if (TValIsAllOnes || FValIsAllZeros) {
23166 if (TValIsAllOnes && FValIsAllZeros)
23168 else if (TValIsAllOnes)
23169 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23170 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23171 else if (FValIsAllZeros)
23172 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23173 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23175 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23179 // Try to fold this VSELECT into a MOVSS/MOVSD
23180 if (N->getOpcode() == ISD::VSELECT &&
23181 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
23182 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
23183 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
23184 bool CanFold = false;
23185 unsigned NumElems = Cond.getNumOperands();
23189 if (isZero(Cond.getOperand(0))) {
23192 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
23193 // fold (vselect <0,-1> -> (movsd A, B)
23194 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23195 CanFold = isAllOnes(Cond.getOperand(i));
23196 } else if (isAllOnes(Cond.getOperand(0))) {
23200 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
23201 // fold (vselect <-1,0> -> (movsd B, A)
23202 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23203 CanFold = isZero(Cond.getOperand(i));
23207 if (VT == MVT::v4i32 || VT == MVT::v4f32)
23208 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
23209 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
23212 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
23213 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
23214 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
23215 // (v2i64 (bitcast B)))))
23217 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
23218 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
23219 // (v2f64 (bitcast B)))))
23221 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
23222 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
23223 // (v2i64 (bitcast A)))))
23225 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
23226 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
23227 // (v2f64 (bitcast A)))))
23229 CanFold = (isZero(Cond.getOperand(0)) &&
23230 isZero(Cond.getOperand(1)) &&
23231 isAllOnes(Cond.getOperand(2)) &&
23232 isAllOnes(Cond.getOperand(3)));
23234 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
23235 isAllOnes(Cond.getOperand(1)) &&
23236 isZero(Cond.getOperand(2)) &&
23237 isZero(Cond.getOperand(3))) {
23239 std::swap(LHS, RHS);
23243 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
23244 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
23245 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
23246 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
23248 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
23254 // If we know that this node is legal then we know that it is going to be
23255 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23256 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23257 // to simplify previous instructions.
23258 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23259 !DCI.isBeforeLegalize() &&
23260 // We explicitly check against v8i16 and v16i16 because, although
23261 // they're marked as Custom, they might only be legal when Cond is a
23262 // build_vector of constants. This will be taken care in a later
23264 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23265 VT != MVT::v8i16) &&
23266 // Don't optimize vector of constants. Those are handled by
23267 // the generic code and all the bits must be properly set for
23268 // the generic optimizer.
23269 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23270 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23272 // Don't optimize vector selects that map to mask-registers.
23276 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23277 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23279 APInt KnownZero, KnownOne;
23280 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23281 DCI.isBeforeLegalizeOps());
23282 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23283 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23285 // If we changed the computation somewhere in the DAG, this change
23286 // will affect all users of Cond.
23287 // Make sure it is fine and update all the nodes so that we do not
23288 // use the generic VSELECT anymore. Otherwise, we may perform
23289 // wrong optimizations as we messed up with the actual expectation
23290 // for the vector boolean values.
23291 if (Cond != TLO.Old) {
23292 // Check all uses of that condition operand to check whether it will be
23293 // consumed by non-BLEND instructions, which may depend on all bits are
23295 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23297 if (I->getOpcode() != ISD::VSELECT)
23298 // TODO: Add other opcodes eventually lowered into BLEND.
23301 // Update all the users of the condition, before committing the change,
23302 // so that the VSELECT optimizations that expect the correct vector
23303 // boolean value will not be triggered.
23304 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23306 DAG.ReplaceAllUsesOfValueWith(
23308 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23309 Cond, I->getOperand(1), I->getOperand(2)));
23310 DCI.CommitTargetLoweringOpt(TLO);
23313 // At this point, only Cond is changed. Change the condition
23314 // just for N to keep the opportunity to optimize all other
23315 // users their own way.
23316 DAG.ReplaceAllUsesOfValueWith(
23318 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23319 TLO.New, N->getOperand(1), N->getOperand(2)));
23324 // We should generate an X86ISD::BLENDI from a vselect if its argument
23325 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23326 // constants. This specific pattern gets generated when we split a
23327 // selector for a 512 bit vector in a machine without AVX512 (but with
23328 // 256-bit vectors), during legalization:
23330 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23332 // Iff we find this pattern and the build_vectors are built from
23333 // constants, we translate the vselect into a shuffle_vector that we
23334 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23335 if ((N->getOpcode() == ISD::VSELECT ||
23336 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23337 !DCI.isBeforeLegalize()) {
23338 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23339 if (Shuffle.getNode())
23346 // Check whether a boolean test is testing a boolean value generated by
23347 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23350 // Simplify the following patterns:
23351 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23352 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23353 // to (Op EFLAGS Cond)
23355 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23356 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23357 // to (Op EFLAGS !Cond)
23359 // where Op could be BRCOND or CMOV.
23361 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23362 // Quit if not CMP and SUB with its value result used.
23363 if (Cmp.getOpcode() != X86ISD::CMP &&
23364 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23367 // Quit if not used as a boolean value.
23368 if (CC != X86::COND_E && CC != X86::COND_NE)
23371 // Check CMP operands. One of them should be 0 or 1 and the other should be
23372 // an SetCC or extended from it.
23373 SDValue Op1 = Cmp.getOperand(0);
23374 SDValue Op2 = Cmp.getOperand(1);
23377 const ConstantSDNode* C = nullptr;
23378 bool needOppositeCond = (CC == X86::COND_E);
23379 bool checkAgainstTrue = false; // Is it a comparison against 1?
23381 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23383 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23385 else // Quit if all operands are not constants.
23388 if (C->getZExtValue() == 1) {
23389 needOppositeCond = !needOppositeCond;
23390 checkAgainstTrue = true;
23391 } else if (C->getZExtValue() != 0)
23392 // Quit if the constant is neither 0 or 1.
23395 bool truncatedToBoolWithAnd = false;
23396 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23397 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23398 SetCC.getOpcode() == ISD::TRUNCATE ||
23399 SetCC.getOpcode() == ISD::AND) {
23400 if (SetCC.getOpcode() == ISD::AND) {
23402 ConstantSDNode *CS;
23403 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23404 CS->getZExtValue() == 1)
23406 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23407 CS->getZExtValue() == 1)
23411 SetCC = SetCC.getOperand(OpIdx);
23412 truncatedToBoolWithAnd = true;
23414 SetCC = SetCC.getOperand(0);
23417 switch (SetCC.getOpcode()) {
23418 case X86ISD::SETCC_CARRY:
23419 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23420 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23421 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23422 // truncated to i1 using 'and'.
23423 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23425 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23426 "Invalid use of SETCC_CARRY!");
23428 case X86ISD::SETCC:
23429 // Set the condition code or opposite one if necessary.
23430 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23431 if (needOppositeCond)
23432 CC = X86::GetOppositeBranchCondition(CC);
23433 return SetCC.getOperand(1);
23434 case X86ISD::CMOV: {
23435 // Check whether false/true value has canonical one, i.e. 0 or 1.
23436 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23437 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23438 // Quit if true value is not a constant.
23441 // Quit if false value is not a constant.
23443 SDValue Op = SetCC.getOperand(0);
23444 // Skip 'zext' or 'trunc' node.
23445 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23446 Op.getOpcode() == ISD::TRUNCATE)
23447 Op = Op.getOperand(0);
23448 // A special case for rdrand/rdseed, where 0 is set if false cond is
23450 if ((Op.getOpcode() != X86ISD::RDRAND &&
23451 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23454 // Quit if false value is not the constant 0 or 1.
23455 bool FValIsFalse = true;
23456 if (FVal && FVal->getZExtValue() != 0) {
23457 if (FVal->getZExtValue() != 1)
23459 // If FVal is 1, opposite cond is needed.
23460 needOppositeCond = !needOppositeCond;
23461 FValIsFalse = false;
23463 // Quit if TVal is not the constant opposite of FVal.
23464 if (FValIsFalse && TVal->getZExtValue() != 1)
23466 if (!FValIsFalse && TVal->getZExtValue() != 0)
23468 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23469 if (needOppositeCond)
23470 CC = X86::GetOppositeBranchCondition(CC);
23471 return SetCC.getOperand(3);
23478 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23479 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23480 TargetLowering::DAGCombinerInfo &DCI,
23481 const X86Subtarget *Subtarget) {
23484 // If the flag operand isn't dead, don't touch this CMOV.
23485 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23488 SDValue FalseOp = N->getOperand(0);
23489 SDValue TrueOp = N->getOperand(1);
23490 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23491 SDValue Cond = N->getOperand(3);
23493 if (CC == X86::COND_E || CC == X86::COND_NE) {
23494 switch (Cond.getOpcode()) {
23498 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23499 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23500 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23506 Flags = checkBoolTestSetCCCombine(Cond, CC);
23507 if (Flags.getNode() &&
23508 // Extra check as FCMOV only supports a subset of X86 cond.
23509 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23510 SDValue Ops[] = { FalseOp, TrueOp,
23511 DAG.getConstant(CC, MVT::i8), Flags };
23512 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23515 // If this is a select between two integer constants, try to do some
23516 // optimizations. Note that the operands are ordered the opposite of SELECT
23518 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23519 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23520 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23521 // larger than FalseC (the false value).
23522 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23523 CC = X86::GetOppositeBranchCondition(CC);
23524 std::swap(TrueC, FalseC);
23525 std::swap(TrueOp, FalseOp);
23528 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23529 // This is efficient for any integer data type (including i8/i16) and
23531 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23532 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23533 DAG.getConstant(CC, MVT::i8), Cond);
23535 // Zero extend the condition if needed.
23536 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23538 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23539 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23540 DAG.getConstant(ShAmt, MVT::i8));
23541 if (N->getNumValues() == 2) // Dead flag value?
23542 return DCI.CombineTo(N, Cond, SDValue());
23546 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23547 // for any integer data type, including i8/i16.
23548 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23549 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23550 DAG.getConstant(CC, MVT::i8), Cond);
23552 // Zero extend the condition if needed.
23553 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23554 FalseC->getValueType(0), Cond);
23555 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23556 SDValue(FalseC, 0));
23558 if (N->getNumValues() == 2) // Dead flag value?
23559 return DCI.CombineTo(N, Cond, SDValue());
23563 // Optimize cases that will turn into an LEA instruction. This requires
23564 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23565 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23566 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23567 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23569 bool isFastMultiplier = false;
23571 switch ((unsigned char)Diff) {
23573 case 1: // result = add base, cond
23574 case 2: // result = lea base( , cond*2)
23575 case 3: // result = lea base(cond, cond*2)
23576 case 4: // result = lea base( , cond*4)
23577 case 5: // result = lea base(cond, cond*4)
23578 case 8: // result = lea base( , cond*8)
23579 case 9: // result = lea base(cond, cond*8)
23580 isFastMultiplier = true;
23585 if (isFastMultiplier) {
23586 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23587 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23588 DAG.getConstant(CC, MVT::i8), Cond);
23589 // Zero extend the condition if needed.
23590 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23592 // Scale the condition by the difference.
23594 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23595 DAG.getConstant(Diff, Cond.getValueType()));
23597 // Add the base if non-zero.
23598 if (FalseC->getAPIntValue() != 0)
23599 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23600 SDValue(FalseC, 0));
23601 if (N->getNumValues() == 2) // Dead flag value?
23602 return DCI.CombineTo(N, Cond, SDValue());
23609 // Handle these cases:
23610 // (select (x != c), e, c) -> select (x != c), e, x),
23611 // (select (x == c), c, e) -> select (x == c), x, e)
23612 // where the c is an integer constant, and the "select" is the combination
23613 // of CMOV and CMP.
23615 // The rationale for this change is that the conditional-move from a constant
23616 // needs two instructions, however, conditional-move from a register needs
23617 // only one instruction.
23619 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23620 // some instruction-combining opportunities. This opt needs to be
23621 // postponed as late as possible.
23623 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23624 // the DCI.xxxx conditions are provided to postpone the optimization as
23625 // late as possible.
23627 ConstantSDNode *CmpAgainst = nullptr;
23628 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23629 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23630 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23632 if (CC == X86::COND_NE &&
23633 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23634 CC = X86::GetOppositeBranchCondition(CC);
23635 std::swap(TrueOp, FalseOp);
23638 if (CC == X86::COND_E &&
23639 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23640 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23641 DAG.getConstant(CC, MVT::i8), Cond };
23642 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23650 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23651 const X86Subtarget *Subtarget) {
23652 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23654 default: return SDValue();
23655 // SSE/AVX/AVX2 blend intrinsics.
23656 case Intrinsic::x86_avx2_pblendvb:
23657 case Intrinsic::x86_avx2_pblendw:
23658 case Intrinsic::x86_avx2_pblendd_128:
23659 case Intrinsic::x86_avx2_pblendd_256:
23660 // Don't try to simplify this intrinsic if we don't have AVX2.
23661 if (!Subtarget->hasAVX2())
23664 case Intrinsic::x86_avx_blend_pd_256:
23665 case Intrinsic::x86_avx_blend_ps_256:
23666 case Intrinsic::x86_avx_blendv_pd_256:
23667 case Intrinsic::x86_avx_blendv_ps_256:
23668 // Don't try to simplify this intrinsic if we don't have AVX.
23669 if (!Subtarget->hasAVX())
23672 case Intrinsic::x86_sse41_pblendw:
23673 case Intrinsic::x86_sse41_blendpd:
23674 case Intrinsic::x86_sse41_blendps:
23675 case Intrinsic::x86_sse41_blendvps:
23676 case Intrinsic::x86_sse41_blendvpd:
23677 case Intrinsic::x86_sse41_pblendvb: {
23678 SDValue Op0 = N->getOperand(1);
23679 SDValue Op1 = N->getOperand(2);
23680 SDValue Mask = N->getOperand(3);
23682 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23683 if (!Subtarget->hasSSE41())
23686 // fold (blend A, A, Mask) -> A
23689 // fold (blend A, B, allZeros) -> A
23690 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23692 // fold (blend A, B, allOnes) -> B
23693 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23696 // Simplify the case where the mask is a constant i32 value.
23697 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23698 if (C->isNullValue())
23700 if (C->isAllOnesValue())
23707 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23708 case Intrinsic::x86_sse2_psrai_w:
23709 case Intrinsic::x86_sse2_psrai_d:
23710 case Intrinsic::x86_avx2_psrai_w:
23711 case Intrinsic::x86_avx2_psrai_d:
23712 case Intrinsic::x86_sse2_psra_w:
23713 case Intrinsic::x86_sse2_psra_d:
23714 case Intrinsic::x86_avx2_psra_w:
23715 case Intrinsic::x86_avx2_psra_d: {
23716 SDValue Op0 = N->getOperand(1);
23717 SDValue Op1 = N->getOperand(2);
23718 EVT VT = Op0.getValueType();
23719 assert(VT.isVector() && "Expected a vector type!");
23721 if (isa<BuildVectorSDNode>(Op1))
23722 Op1 = Op1.getOperand(0);
23724 if (!isa<ConstantSDNode>(Op1))
23727 EVT SVT = VT.getVectorElementType();
23728 unsigned SVTBits = SVT.getSizeInBits();
23730 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23731 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23732 uint64_t ShAmt = C.getZExtValue();
23734 // Don't try to convert this shift into a ISD::SRA if the shift
23735 // count is bigger than or equal to the element size.
23736 if (ShAmt >= SVTBits)
23739 // Trivial case: if the shift count is zero, then fold this
23740 // into the first operand.
23744 // Replace this packed shift intrinsic with a target independent
23746 SDValue Splat = DAG.getConstant(C, VT);
23747 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23752 /// PerformMulCombine - Optimize a single multiply with constant into two
23753 /// in order to implement it with two cheaper instructions, e.g.
23754 /// LEA + SHL, LEA + LEA.
23755 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23756 TargetLowering::DAGCombinerInfo &DCI) {
23757 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23760 EVT VT = N->getValueType(0);
23761 if (VT != MVT::i64)
23764 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23767 uint64_t MulAmt = C->getZExtValue();
23768 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23771 uint64_t MulAmt1 = 0;
23772 uint64_t MulAmt2 = 0;
23773 if ((MulAmt % 9) == 0) {
23775 MulAmt2 = MulAmt / 9;
23776 } else if ((MulAmt % 5) == 0) {
23778 MulAmt2 = MulAmt / 5;
23779 } else if ((MulAmt % 3) == 0) {
23781 MulAmt2 = MulAmt / 3;
23784 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23787 if (isPowerOf2_64(MulAmt2) &&
23788 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23789 // If second multiplifer is pow2, issue it first. We want the multiply by
23790 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23792 std::swap(MulAmt1, MulAmt2);
23795 if (isPowerOf2_64(MulAmt1))
23796 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23797 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23799 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23800 DAG.getConstant(MulAmt1, VT));
23802 if (isPowerOf2_64(MulAmt2))
23803 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23804 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23806 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23807 DAG.getConstant(MulAmt2, VT));
23809 // Do not add new nodes to DAG combiner worklist.
23810 DCI.CombineTo(N, NewMul, false);
23815 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23816 SDValue N0 = N->getOperand(0);
23817 SDValue N1 = N->getOperand(1);
23818 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23819 EVT VT = N0.getValueType();
23821 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23822 // since the result of setcc_c is all zero's or all ones.
23823 if (VT.isInteger() && !VT.isVector() &&
23824 N1C && N0.getOpcode() == ISD::AND &&
23825 N0.getOperand(1).getOpcode() == ISD::Constant) {
23826 SDValue N00 = N0.getOperand(0);
23827 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23828 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23829 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23830 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23831 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23832 APInt ShAmt = N1C->getAPIntValue();
23833 Mask = Mask.shl(ShAmt);
23835 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23836 N00, DAG.getConstant(Mask, VT));
23840 // Hardware support for vector shifts is sparse which makes us scalarize the
23841 // vector operations in many cases. Also, on sandybridge ADD is faster than
23843 // (shl V, 1) -> add V,V
23844 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23845 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23846 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23847 // We shift all of the values by one. In many cases we do not have
23848 // hardware support for this operation. This is better expressed as an ADD
23850 if (N1SplatC->getZExtValue() == 1)
23851 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23857 /// \brief Returns a vector of 0s if the node in input is a vector logical
23858 /// shift by a constant amount which is known to be bigger than or equal
23859 /// to the vector element size in bits.
23860 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23861 const X86Subtarget *Subtarget) {
23862 EVT VT = N->getValueType(0);
23864 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23865 (!Subtarget->hasInt256() ||
23866 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23869 SDValue Amt = N->getOperand(1);
23871 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23872 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23873 APInt ShiftAmt = AmtSplat->getAPIntValue();
23874 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23876 // SSE2/AVX2 logical shifts always return a vector of 0s
23877 // if the shift amount is bigger than or equal to
23878 // the element size. The constant shift amount will be
23879 // encoded as a 8-bit immediate.
23880 if (ShiftAmt.trunc(8).uge(MaxAmount))
23881 return getZeroVector(VT, Subtarget, DAG, DL);
23887 /// PerformShiftCombine - Combine shifts.
23888 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23889 TargetLowering::DAGCombinerInfo &DCI,
23890 const X86Subtarget *Subtarget) {
23891 if (N->getOpcode() == ISD::SHL) {
23892 SDValue V = PerformSHLCombine(N, DAG);
23893 if (V.getNode()) return V;
23896 if (N->getOpcode() != ISD::SRA) {
23897 // Try to fold this logical shift into a zero vector.
23898 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23899 if (V.getNode()) return V;
23905 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23906 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23907 // and friends. Likewise for OR -> CMPNEQSS.
23908 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23909 TargetLowering::DAGCombinerInfo &DCI,
23910 const X86Subtarget *Subtarget) {
23913 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23914 // we're requiring SSE2 for both.
23915 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23916 SDValue N0 = N->getOperand(0);
23917 SDValue N1 = N->getOperand(1);
23918 SDValue CMP0 = N0->getOperand(1);
23919 SDValue CMP1 = N1->getOperand(1);
23922 // The SETCCs should both refer to the same CMP.
23923 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23926 SDValue CMP00 = CMP0->getOperand(0);
23927 SDValue CMP01 = CMP0->getOperand(1);
23928 EVT VT = CMP00.getValueType();
23930 if (VT == MVT::f32 || VT == MVT::f64) {
23931 bool ExpectingFlags = false;
23932 // Check for any users that want flags:
23933 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23934 !ExpectingFlags && UI != UE; ++UI)
23935 switch (UI->getOpcode()) {
23940 ExpectingFlags = true;
23942 case ISD::CopyToReg:
23943 case ISD::SIGN_EXTEND:
23944 case ISD::ZERO_EXTEND:
23945 case ISD::ANY_EXTEND:
23949 if (!ExpectingFlags) {
23950 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23951 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23953 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23954 X86::CondCode tmp = cc0;
23959 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23960 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23961 // FIXME: need symbolic constants for these magic numbers.
23962 // See X86ATTInstPrinter.cpp:printSSECC().
23963 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23964 if (Subtarget->hasAVX512()) {
23965 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23966 CMP01, DAG.getConstant(x86cc, MVT::i8));
23967 if (N->getValueType(0) != MVT::i1)
23968 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23972 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23973 CMP00.getValueType(), CMP00, CMP01,
23974 DAG.getConstant(x86cc, MVT::i8));
23976 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23977 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23979 if (is64BitFP && !Subtarget->is64Bit()) {
23980 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23981 // 64-bit integer, since that's not a legal type. Since
23982 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23983 // bits, but can do this little dance to extract the lowest 32 bits
23984 // and work with those going forward.
23985 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23987 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23989 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23990 Vector32, DAG.getIntPtrConstant(0));
23994 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23995 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23996 DAG.getConstant(1, IntVT));
23997 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23998 return OneBitOfTruth;
24006 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24007 /// so it can be folded inside ANDNP.
24008 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24009 EVT VT = N->getValueType(0);
24011 // Match direct AllOnes for 128 and 256-bit vectors
24012 if (ISD::isBuildVectorAllOnes(N))
24015 // Look through a bit convert.
24016 if (N->getOpcode() == ISD::BITCAST)
24017 N = N->getOperand(0).getNode();
24019 // Sometimes the operand may come from a insert_subvector building a 256-bit
24021 if (VT.is256BitVector() &&
24022 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24023 SDValue V1 = N->getOperand(0);
24024 SDValue V2 = N->getOperand(1);
24026 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24027 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24028 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24029 ISD::isBuildVectorAllOnes(V2.getNode()))
24036 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24037 // register. In most cases we actually compare or select YMM-sized registers
24038 // and mixing the two types creates horrible code. This method optimizes
24039 // some of the transition sequences.
24040 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24041 TargetLowering::DAGCombinerInfo &DCI,
24042 const X86Subtarget *Subtarget) {
24043 EVT VT = N->getValueType(0);
24044 if (!VT.is256BitVector())
24047 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24048 N->getOpcode() == ISD::ZERO_EXTEND ||
24049 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24051 SDValue Narrow = N->getOperand(0);
24052 EVT NarrowVT = Narrow->getValueType(0);
24053 if (!NarrowVT.is128BitVector())
24056 if (Narrow->getOpcode() != ISD::XOR &&
24057 Narrow->getOpcode() != ISD::AND &&
24058 Narrow->getOpcode() != ISD::OR)
24061 SDValue N0 = Narrow->getOperand(0);
24062 SDValue N1 = Narrow->getOperand(1);
24065 // The Left side has to be a trunc.
24066 if (N0.getOpcode() != ISD::TRUNCATE)
24069 // The type of the truncated inputs.
24070 EVT WideVT = N0->getOperand(0)->getValueType(0);
24074 // The right side has to be a 'trunc' or a constant vector.
24075 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24076 ConstantSDNode *RHSConstSplat = nullptr;
24077 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24078 RHSConstSplat = RHSBV->getConstantSplatNode();
24079 if (!RHSTrunc && !RHSConstSplat)
24082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24084 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24087 // Set N0 and N1 to hold the inputs to the new wide operation.
24088 N0 = N0->getOperand(0);
24089 if (RHSConstSplat) {
24090 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24091 SDValue(RHSConstSplat, 0));
24092 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24093 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24094 } else if (RHSTrunc) {
24095 N1 = N1->getOperand(0);
24098 // Generate the wide operation.
24099 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24100 unsigned Opcode = N->getOpcode();
24102 case ISD::ANY_EXTEND:
24104 case ISD::ZERO_EXTEND: {
24105 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24106 APInt Mask = APInt::getAllOnesValue(InBits);
24107 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24108 return DAG.getNode(ISD::AND, DL, VT,
24109 Op, DAG.getConstant(Mask, VT));
24111 case ISD::SIGN_EXTEND:
24112 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24113 Op, DAG.getValueType(NarrowVT));
24115 llvm_unreachable("Unexpected opcode");
24119 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24120 TargetLowering::DAGCombinerInfo &DCI,
24121 const X86Subtarget *Subtarget) {
24122 EVT VT = N->getValueType(0);
24123 if (DCI.isBeforeLegalizeOps())
24126 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24130 // Create BEXTR instructions
24131 // BEXTR is ((X >> imm) & (2**size-1))
24132 if (VT == MVT::i32 || VT == MVT::i64) {
24133 SDValue N0 = N->getOperand(0);
24134 SDValue N1 = N->getOperand(1);
24137 // Check for BEXTR.
24138 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24139 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24140 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24141 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24142 if (MaskNode && ShiftNode) {
24143 uint64_t Mask = MaskNode->getZExtValue();
24144 uint64_t Shift = ShiftNode->getZExtValue();
24145 if (isMask_64(Mask)) {
24146 uint64_t MaskSize = CountPopulation_64(Mask);
24147 if (Shift + MaskSize <= VT.getSizeInBits())
24148 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24149 DAG.getConstant(Shift | (MaskSize << 8), VT));
24157 // Want to form ANDNP nodes:
24158 // 1) In the hopes of then easily combining them with OR and AND nodes
24159 // to form PBLEND/PSIGN.
24160 // 2) To match ANDN packed intrinsics
24161 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24164 SDValue N0 = N->getOperand(0);
24165 SDValue N1 = N->getOperand(1);
24168 // Check LHS for vnot
24169 if (N0.getOpcode() == ISD::XOR &&
24170 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24171 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24172 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24174 // Check RHS for vnot
24175 if (N1.getOpcode() == ISD::XOR &&
24176 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24177 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24178 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24183 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24184 TargetLowering::DAGCombinerInfo &DCI,
24185 const X86Subtarget *Subtarget) {
24186 if (DCI.isBeforeLegalizeOps())
24189 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24193 SDValue N0 = N->getOperand(0);
24194 SDValue N1 = N->getOperand(1);
24195 EVT VT = N->getValueType(0);
24197 // look for psign/blend
24198 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24199 if (!Subtarget->hasSSSE3() ||
24200 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24203 // Canonicalize pandn to RHS
24204 if (N0.getOpcode() == X86ISD::ANDNP)
24206 // or (and (m, y), (pandn m, x))
24207 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24208 SDValue Mask = N1.getOperand(0);
24209 SDValue X = N1.getOperand(1);
24211 if (N0.getOperand(0) == Mask)
24212 Y = N0.getOperand(1);
24213 if (N0.getOperand(1) == Mask)
24214 Y = N0.getOperand(0);
24216 // Check to see if the mask appeared in both the AND and ANDNP and
24220 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24221 // Look through mask bitcast.
24222 if (Mask.getOpcode() == ISD::BITCAST)
24223 Mask = Mask.getOperand(0);
24224 if (X.getOpcode() == ISD::BITCAST)
24225 X = X.getOperand(0);
24226 if (Y.getOpcode() == ISD::BITCAST)
24227 Y = Y.getOperand(0);
24229 EVT MaskVT = Mask.getValueType();
24231 // Validate that the Mask operand is a vector sra node.
24232 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24233 // there is no psrai.b
24234 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24235 unsigned SraAmt = ~0;
24236 if (Mask.getOpcode() == ISD::SRA) {
24237 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24238 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24239 SraAmt = AmtConst->getZExtValue();
24240 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24241 SDValue SraC = Mask.getOperand(1);
24242 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24244 if ((SraAmt + 1) != EltBits)
24249 // Now we know we at least have a plendvb with the mask val. See if
24250 // we can form a psignb/w/d.
24251 // psign = x.type == y.type == mask.type && y = sub(0, x);
24252 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24253 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24254 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24255 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24256 "Unsupported VT for PSIGN");
24257 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24258 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24260 // PBLENDVB only available on SSE 4.1
24261 if (!Subtarget->hasSSE41())
24264 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24266 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24267 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24268 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24269 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24270 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24274 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24277 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24278 MachineFunction &MF = DAG.getMachineFunction();
24279 bool OptForSize = MF.getFunction()->getAttributes().
24280 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24282 // SHLD/SHRD instructions have lower register pressure, but on some
24283 // platforms they have higher latency than the equivalent
24284 // series of shifts/or that would otherwise be generated.
24285 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24286 // have higher latencies and we are not optimizing for size.
24287 if (!OptForSize && Subtarget->isSHLDSlow())
24290 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24292 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24294 if (!N0.hasOneUse() || !N1.hasOneUse())
24297 SDValue ShAmt0 = N0.getOperand(1);
24298 if (ShAmt0.getValueType() != MVT::i8)
24300 SDValue ShAmt1 = N1.getOperand(1);
24301 if (ShAmt1.getValueType() != MVT::i8)
24303 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24304 ShAmt0 = ShAmt0.getOperand(0);
24305 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24306 ShAmt1 = ShAmt1.getOperand(0);
24309 unsigned Opc = X86ISD::SHLD;
24310 SDValue Op0 = N0.getOperand(0);
24311 SDValue Op1 = N1.getOperand(0);
24312 if (ShAmt0.getOpcode() == ISD::SUB) {
24313 Opc = X86ISD::SHRD;
24314 std::swap(Op0, Op1);
24315 std::swap(ShAmt0, ShAmt1);
24318 unsigned Bits = VT.getSizeInBits();
24319 if (ShAmt1.getOpcode() == ISD::SUB) {
24320 SDValue Sum = ShAmt1.getOperand(0);
24321 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24322 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24323 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24324 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24325 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24326 return DAG.getNode(Opc, DL, VT,
24328 DAG.getNode(ISD::TRUNCATE, DL,
24331 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24332 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24334 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24335 return DAG.getNode(Opc, DL, VT,
24336 N0.getOperand(0), N1.getOperand(0),
24337 DAG.getNode(ISD::TRUNCATE, DL,
24344 // Generate NEG and CMOV for integer abs.
24345 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24346 EVT VT = N->getValueType(0);
24348 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24349 // 8-bit integer abs to NEG and CMOV.
24350 if (VT.isInteger() && VT.getSizeInBits() == 8)
24353 SDValue N0 = N->getOperand(0);
24354 SDValue N1 = N->getOperand(1);
24357 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24358 // and change it to SUB and CMOV.
24359 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24360 N0.getOpcode() == ISD::ADD &&
24361 N0.getOperand(1) == N1 &&
24362 N1.getOpcode() == ISD::SRA &&
24363 N1.getOperand(0) == N0.getOperand(0))
24364 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24365 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24366 // Generate SUB & CMOV.
24367 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24368 DAG.getConstant(0, VT), N0.getOperand(0));
24370 SDValue Ops[] = { N0.getOperand(0), Neg,
24371 DAG.getConstant(X86::COND_GE, MVT::i8),
24372 SDValue(Neg.getNode(), 1) };
24373 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24378 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24379 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24380 TargetLowering::DAGCombinerInfo &DCI,
24381 const X86Subtarget *Subtarget) {
24382 if (DCI.isBeforeLegalizeOps())
24385 if (Subtarget->hasCMov()) {
24386 SDValue RV = performIntegerAbsCombine(N, DAG);
24394 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24395 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24396 TargetLowering::DAGCombinerInfo &DCI,
24397 const X86Subtarget *Subtarget) {
24398 LoadSDNode *Ld = cast<LoadSDNode>(N);
24399 EVT RegVT = Ld->getValueType(0);
24400 EVT MemVT = Ld->getMemoryVT();
24402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24404 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24405 // into two 16-byte operations.
24406 ISD::LoadExtType Ext = Ld->getExtensionType();
24407 unsigned Alignment = Ld->getAlignment();
24408 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24409 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24410 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24411 unsigned NumElems = RegVT.getVectorNumElements();
24415 SDValue Ptr = Ld->getBasePtr();
24416 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24418 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24420 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24421 Ld->getPointerInfo(), Ld->isVolatile(),
24422 Ld->isNonTemporal(), Ld->isInvariant(),
24424 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24425 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24426 Ld->getPointerInfo(), Ld->isVolatile(),
24427 Ld->isNonTemporal(), Ld->isInvariant(),
24428 std::min(16U, Alignment));
24429 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24431 Load2.getValue(1));
24433 SDValue NewVec = DAG.getUNDEF(RegVT);
24434 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24435 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24436 return DCI.CombineTo(N, NewVec, TF, true);
24442 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24443 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24444 const X86Subtarget *Subtarget) {
24445 StoreSDNode *St = cast<StoreSDNode>(N);
24446 EVT VT = St->getValue().getValueType();
24447 EVT StVT = St->getMemoryVT();
24449 SDValue StoredVal = St->getOperand(1);
24450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24452 // If we are saving a concatenation of two XMM registers and 32-byte stores
24453 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24454 unsigned Alignment = St->getAlignment();
24455 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24456 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24457 StVT == VT && !IsAligned) {
24458 unsigned NumElems = VT.getVectorNumElements();
24462 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24463 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24465 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24466 SDValue Ptr0 = St->getBasePtr();
24467 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24469 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24470 St->getPointerInfo(), St->isVolatile(),
24471 St->isNonTemporal(), Alignment);
24472 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24473 St->getPointerInfo(), St->isVolatile(),
24474 St->isNonTemporal(),
24475 std::min(16U, Alignment));
24476 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24479 // Optimize trunc store (of multiple scalars) to shuffle and store.
24480 // First, pack all of the elements in one place. Next, store to memory
24481 // in fewer chunks.
24482 if (St->isTruncatingStore() && VT.isVector()) {
24483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24484 unsigned NumElems = VT.getVectorNumElements();
24485 assert(StVT != VT && "Cannot truncate to the same type");
24486 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24487 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24489 // From, To sizes and ElemCount must be pow of two
24490 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24491 // We are going to use the original vector elt for storing.
24492 // Accumulated smaller vector elements must be a multiple of the store size.
24493 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24495 unsigned SizeRatio = FromSz / ToSz;
24497 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24499 // Create a type on which we perform the shuffle
24500 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24501 StVT.getScalarType(), NumElems*SizeRatio);
24503 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24505 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24506 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24507 for (unsigned i = 0; i != NumElems; ++i)
24508 ShuffleVec[i] = i * SizeRatio;
24510 // Can't shuffle using an illegal type.
24511 if (!TLI.isTypeLegal(WideVecVT))
24514 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24515 DAG.getUNDEF(WideVecVT),
24517 // At this point all of the data is stored at the bottom of the
24518 // register. We now need to save it to mem.
24520 // Find the largest store unit
24521 MVT StoreType = MVT::i8;
24522 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24523 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24524 MVT Tp = (MVT::SimpleValueType)tp;
24525 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24529 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24530 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24531 (64 <= NumElems * ToSz))
24532 StoreType = MVT::f64;
24534 // Bitcast the original vector into a vector of store-size units
24535 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24536 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24537 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24538 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24539 SmallVector<SDValue, 8> Chains;
24540 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24541 TLI.getPointerTy());
24542 SDValue Ptr = St->getBasePtr();
24544 // Perform one or more big stores into memory.
24545 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24546 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24547 StoreType, ShuffWide,
24548 DAG.getIntPtrConstant(i));
24549 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24550 St->getPointerInfo(), St->isVolatile(),
24551 St->isNonTemporal(), St->getAlignment());
24552 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24553 Chains.push_back(Ch);
24556 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24559 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24560 // the FP state in cases where an emms may be missing.
24561 // A preferable solution to the general problem is to figure out the right
24562 // places to insert EMMS. This qualifies as a quick hack.
24564 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24565 if (VT.getSizeInBits() != 64)
24568 const Function *F = DAG.getMachineFunction().getFunction();
24569 bool NoImplicitFloatOps = F->getAttributes().
24570 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24571 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24572 && Subtarget->hasSSE2();
24573 if ((VT.isVector() ||
24574 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24575 isa<LoadSDNode>(St->getValue()) &&
24576 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24577 St->getChain().hasOneUse() && !St->isVolatile()) {
24578 SDNode* LdVal = St->getValue().getNode();
24579 LoadSDNode *Ld = nullptr;
24580 int TokenFactorIndex = -1;
24581 SmallVector<SDValue, 8> Ops;
24582 SDNode* ChainVal = St->getChain().getNode();
24583 // Must be a store of a load. We currently handle two cases: the load
24584 // is a direct child, and it's under an intervening TokenFactor. It is
24585 // possible to dig deeper under nested TokenFactors.
24586 if (ChainVal == LdVal)
24587 Ld = cast<LoadSDNode>(St->getChain());
24588 else if (St->getValue().hasOneUse() &&
24589 ChainVal->getOpcode() == ISD::TokenFactor) {
24590 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24591 if (ChainVal->getOperand(i).getNode() == LdVal) {
24592 TokenFactorIndex = i;
24593 Ld = cast<LoadSDNode>(St->getValue());
24595 Ops.push_back(ChainVal->getOperand(i));
24599 if (!Ld || !ISD::isNormalLoad(Ld))
24602 // If this is not the MMX case, i.e. we are just turning i64 load/store
24603 // into f64 load/store, avoid the transformation if there are multiple
24604 // uses of the loaded value.
24605 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24610 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24611 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24613 if (Subtarget->is64Bit() || F64IsLegal) {
24614 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24615 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24616 Ld->getPointerInfo(), Ld->isVolatile(),
24617 Ld->isNonTemporal(), Ld->isInvariant(),
24618 Ld->getAlignment());
24619 SDValue NewChain = NewLd.getValue(1);
24620 if (TokenFactorIndex != -1) {
24621 Ops.push_back(NewChain);
24622 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24624 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24625 St->getPointerInfo(),
24626 St->isVolatile(), St->isNonTemporal(),
24627 St->getAlignment());
24630 // Otherwise, lower to two pairs of 32-bit loads / stores.
24631 SDValue LoAddr = Ld->getBasePtr();
24632 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24633 DAG.getConstant(4, MVT::i32));
24635 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24636 Ld->getPointerInfo(),
24637 Ld->isVolatile(), Ld->isNonTemporal(),
24638 Ld->isInvariant(), Ld->getAlignment());
24639 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24640 Ld->getPointerInfo().getWithOffset(4),
24641 Ld->isVolatile(), Ld->isNonTemporal(),
24643 MinAlign(Ld->getAlignment(), 4));
24645 SDValue NewChain = LoLd.getValue(1);
24646 if (TokenFactorIndex != -1) {
24647 Ops.push_back(LoLd);
24648 Ops.push_back(HiLd);
24649 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24652 LoAddr = St->getBasePtr();
24653 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24654 DAG.getConstant(4, MVT::i32));
24656 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24657 St->getPointerInfo(),
24658 St->isVolatile(), St->isNonTemporal(),
24659 St->getAlignment());
24660 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24661 St->getPointerInfo().getWithOffset(4),
24663 St->isNonTemporal(),
24664 MinAlign(St->getAlignment(), 4));
24665 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24670 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24671 /// and return the operands for the horizontal operation in LHS and RHS. A
24672 /// horizontal operation performs the binary operation on successive elements
24673 /// of its first operand, then on successive elements of its second operand,
24674 /// returning the resulting values in a vector. For example, if
24675 /// A = < float a0, float a1, float a2, float a3 >
24677 /// B = < float b0, float b1, float b2, float b3 >
24678 /// then the result of doing a horizontal operation on A and B is
24679 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24680 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24681 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24682 /// set to A, RHS to B, and the routine returns 'true'.
24683 /// Note that the binary operation should have the property that if one of the
24684 /// operands is UNDEF then the result is UNDEF.
24685 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24686 // Look for the following pattern: if
24687 // A = < float a0, float a1, float a2, float a3 >
24688 // B = < float b0, float b1, float b2, float b3 >
24690 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24691 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24692 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24693 // which is A horizontal-op B.
24695 // At least one of the operands should be a vector shuffle.
24696 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24697 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24700 MVT VT = LHS.getSimpleValueType();
24702 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24703 "Unsupported vector type for horizontal add/sub");
24705 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24706 // operate independently on 128-bit lanes.
24707 unsigned NumElts = VT.getVectorNumElements();
24708 unsigned NumLanes = VT.getSizeInBits()/128;
24709 unsigned NumLaneElts = NumElts / NumLanes;
24710 assert((NumLaneElts % 2 == 0) &&
24711 "Vector type should have an even number of elements in each lane");
24712 unsigned HalfLaneElts = NumLaneElts/2;
24714 // View LHS in the form
24715 // LHS = VECTOR_SHUFFLE A, B, LMask
24716 // If LHS is not a shuffle then pretend it is the shuffle
24717 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24718 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24721 SmallVector<int, 16> LMask(NumElts);
24722 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24723 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24724 A = LHS.getOperand(0);
24725 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24726 B = LHS.getOperand(1);
24727 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24728 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24730 if (LHS.getOpcode() != ISD::UNDEF)
24732 for (unsigned i = 0; i != NumElts; ++i)
24736 // Likewise, view RHS in the form
24737 // RHS = VECTOR_SHUFFLE C, D, RMask
24739 SmallVector<int, 16> RMask(NumElts);
24740 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24741 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24742 C = RHS.getOperand(0);
24743 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24744 D = RHS.getOperand(1);
24745 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24746 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24748 if (RHS.getOpcode() != ISD::UNDEF)
24750 for (unsigned i = 0; i != NumElts; ++i)
24754 // Check that the shuffles are both shuffling the same vectors.
24755 if (!(A == C && B == D) && !(A == D && B == C))
24758 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24759 if (!A.getNode() && !B.getNode())
24762 // If A and B occur in reverse order in RHS, then "swap" them (which means
24763 // rewriting the mask).
24765 CommuteVectorShuffleMask(RMask, NumElts);
24767 // At this point LHS and RHS are equivalent to
24768 // LHS = VECTOR_SHUFFLE A, B, LMask
24769 // RHS = VECTOR_SHUFFLE A, B, RMask
24770 // Check that the masks correspond to performing a horizontal operation.
24771 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24772 for (unsigned i = 0; i != NumLaneElts; ++i) {
24773 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24775 // Ignore any UNDEF components.
24776 if (LIdx < 0 || RIdx < 0 ||
24777 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24778 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24781 // Check that successive elements are being operated on. If not, this is
24782 // not a horizontal operation.
24783 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24784 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24785 if (!(LIdx == Index && RIdx == Index + 1) &&
24786 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24791 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24792 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24796 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24797 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24798 const X86Subtarget *Subtarget) {
24799 EVT VT = N->getValueType(0);
24800 SDValue LHS = N->getOperand(0);
24801 SDValue RHS = N->getOperand(1);
24803 // Try to synthesize horizontal adds from adds of shuffles.
24804 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24805 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24806 isHorizontalBinOp(LHS, RHS, true))
24807 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24811 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24812 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24813 const X86Subtarget *Subtarget) {
24814 EVT VT = N->getValueType(0);
24815 SDValue LHS = N->getOperand(0);
24816 SDValue RHS = N->getOperand(1);
24818 // Try to synthesize horizontal subs from subs of shuffles.
24819 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24820 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24821 isHorizontalBinOp(LHS, RHS, false))
24822 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24826 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24827 /// X86ISD::FXOR nodes.
24828 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24829 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24830 // F[X]OR(0.0, x) -> x
24831 // F[X]OR(x, 0.0) -> x
24832 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24833 if (C->getValueAPF().isPosZero())
24834 return N->getOperand(1);
24835 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24836 if (C->getValueAPF().isPosZero())
24837 return N->getOperand(0);
24841 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24842 /// X86ISD::FMAX nodes.
24843 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24844 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24846 // Only perform optimizations if UnsafeMath is used.
24847 if (!DAG.getTarget().Options.UnsafeFPMath)
24850 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24851 // into FMINC and FMAXC, which are Commutative operations.
24852 unsigned NewOp = 0;
24853 switch (N->getOpcode()) {
24854 default: llvm_unreachable("unknown opcode");
24855 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24856 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24859 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24860 N->getOperand(0), N->getOperand(1));
24863 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24864 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24865 // FAND(0.0, x) -> 0.0
24866 // FAND(x, 0.0) -> 0.0
24867 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24868 if (C->getValueAPF().isPosZero())
24869 return N->getOperand(0);
24870 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24871 if (C->getValueAPF().isPosZero())
24872 return N->getOperand(1);
24876 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24877 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24878 // FANDN(x, 0.0) -> 0.0
24879 // FANDN(0.0, x) -> x
24880 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24881 if (C->getValueAPF().isPosZero())
24882 return N->getOperand(1);
24883 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24884 if (C->getValueAPF().isPosZero())
24885 return N->getOperand(1);
24889 static SDValue PerformBTCombine(SDNode *N,
24891 TargetLowering::DAGCombinerInfo &DCI) {
24892 // BT ignores high bits in the bit index operand.
24893 SDValue Op1 = N->getOperand(1);
24894 if (Op1.hasOneUse()) {
24895 unsigned BitWidth = Op1.getValueSizeInBits();
24896 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24897 APInt KnownZero, KnownOne;
24898 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24899 !DCI.isBeforeLegalizeOps());
24900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24901 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24902 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24903 DCI.CommitTargetLoweringOpt(TLO);
24908 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24909 SDValue Op = N->getOperand(0);
24910 if (Op.getOpcode() == ISD::BITCAST)
24911 Op = Op.getOperand(0);
24912 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24913 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24914 VT.getVectorElementType().getSizeInBits() ==
24915 OpVT.getVectorElementType().getSizeInBits()) {
24916 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24921 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24922 const X86Subtarget *Subtarget) {
24923 EVT VT = N->getValueType(0);
24924 if (!VT.isVector())
24927 SDValue N0 = N->getOperand(0);
24928 SDValue N1 = N->getOperand(1);
24929 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24932 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24933 // both SSE and AVX2 since there is no sign-extended shift right
24934 // operation on a vector with 64-bit elements.
24935 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24936 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24937 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24938 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24939 SDValue N00 = N0.getOperand(0);
24941 // EXTLOAD has a better solution on AVX2,
24942 // it may be replaced with X86ISD::VSEXT node.
24943 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24944 if (!ISD::isNormalLoad(N00.getNode()))
24947 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24948 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24950 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24956 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24957 TargetLowering::DAGCombinerInfo &DCI,
24958 const X86Subtarget *Subtarget) {
24959 SDValue N0 = N->getOperand(0);
24960 EVT VT = N->getValueType(0);
24962 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24963 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24964 // This exposes the sext to the sdivrem lowering, so that it directly extends
24965 // from AH (which we otherwise need to do contortions to access).
24966 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24967 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24969 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24970 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24971 N0.getOperand(0), N0.getOperand(1));
24972 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24973 return R.getValue(1);
24976 if (!DCI.isBeforeLegalizeOps())
24979 if (!Subtarget->hasFp256())
24982 if (VT.isVector() && VT.getSizeInBits() == 256) {
24983 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24991 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24992 const X86Subtarget* Subtarget) {
24994 EVT VT = N->getValueType(0);
24996 // Let legalize expand this if it isn't a legal type yet.
24997 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25000 EVT ScalarVT = VT.getScalarType();
25001 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25002 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25005 SDValue A = N->getOperand(0);
25006 SDValue B = N->getOperand(1);
25007 SDValue C = N->getOperand(2);
25009 bool NegA = (A.getOpcode() == ISD::FNEG);
25010 bool NegB = (B.getOpcode() == ISD::FNEG);
25011 bool NegC = (C.getOpcode() == ISD::FNEG);
25013 // Negative multiplication when NegA xor NegB
25014 bool NegMul = (NegA != NegB);
25016 A = A.getOperand(0);
25018 B = B.getOperand(0);
25020 C = C.getOperand(0);
25024 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25026 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25028 return DAG.getNode(Opcode, dl, VT, A, B, C);
25031 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25032 TargetLowering::DAGCombinerInfo &DCI,
25033 const X86Subtarget *Subtarget) {
25034 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25035 // (and (i32 x86isd::setcc_carry), 1)
25036 // This eliminates the zext. This transformation is necessary because
25037 // ISD::SETCC is always legalized to i8.
25039 SDValue N0 = N->getOperand(0);
25040 EVT VT = N->getValueType(0);
25042 if (N0.getOpcode() == ISD::AND &&
25044 N0.getOperand(0).hasOneUse()) {
25045 SDValue N00 = N0.getOperand(0);
25046 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25047 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25048 if (!C || C->getZExtValue() != 1)
25050 return DAG.getNode(ISD::AND, dl, VT,
25051 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25052 N00.getOperand(0), N00.getOperand(1)),
25053 DAG.getConstant(1, VT));
25057 if (N0.getOpcode() == ISD::TRUNCATE &&
25059 N0.getOperand(0).hasOneUse()) {
25060 SDValue N00 = N0.getOperand(0);
25061 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25062 return DAG.getNode(ISD::AND, dl, VT,
25063 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25064 N00.getOperand(0), N00.getOperand(1)),
25065 DAG.getConstant(1, VT));
25068 if (VT.is256BitVector()) {
25069 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25074 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25075 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25076 // This exposes the zext to the udivrem lowering, so that it directly extends
25077 // from AH (which we otherwise need to do contortions to access).
25078 if (N0.getOpcode() == ISD::UDIVREM &&
25079 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25080 (VT == MVT::i32 || VT == MVT::i64)) {
25081 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25082 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25083 N0.getOperand(0), N0.getOperand(1));
25084 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25085 return R.getValue(1);
25091 // Optimize x == -y --> x+y == 0
25092 // x != -y --> x+y != 0
25093 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25094 const X86Subtarget* Subtarget) {
25095 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25096 SDValue LHS = N->getOperand(0);
25097 SDValue RHS = N->getOperand(1);
25098 EVT VT = N->getValueType(0);
25101 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25103 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25104 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25105 LHS.getValueType(), RHS, LHS.getOperand(1));
25106 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25107 addV, DAG.getConstant(0, addV.getValueType()), CC);
25109 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25111 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25112 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25113 RHS.getValueType(), LHS, RHS.getOperand(1));
25114 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25115 addV, DAG.getConstant(0, addV.getValueType()), CC);
25118 if (VT.getScalarType() == MVT::i1) {
25119 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25120 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25121 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25122 if (!IsSEXT0 && !IsVZero0)
25124 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25125 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25126 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25128 if (!IsSEXT1 && !IsVZero1)
25131 if (IsSEXT0 && IsVZero1) {
25132 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25133 if (CC == ISD::SETEQ)
25134 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25135 return LHS.getOperand(0);
25137 if (IsSEXT1 && IsVZero0) {
25138 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25139 if (CC == ISD::SETEQ)
25140 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25141 return RHS.getOperand(0);
25148 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25149 const X86Subtarget *Subtarget) {
25151 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25152 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25153 "X86insertps is only defined for v4x32");
25155 SDValue Ld = N->getOperand(1);
25156 if (MayFoldLoad(Ld)) {
25157 // Extract the countS bits from the immediate so we can get the proper
25158 // address when narrowing the vector load to a specific element.
25159 // When the second source op is a memory address, interps doesn't use
25160 // countS and just gets an f32 from that address.
25161 unsigned DestIndex =
25162 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25163 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25167 // Create this as a scalar to vector to match the instruction pattern.
25168 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25169 // countS bits are ignored when loading from memory on insertps, which
25170 // means we don't need to explicitly set them to 0.
25171 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25172 LoadScalarToVector, N->getOperand(2));
25175 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25176 // as "sbb reg,reg", since it can be extended without zext and produces
25177 // an all-ones bit which is more useful than 0/1 in some cases.
25178 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25181 return DAG.getNode(ISD::AND, DL, VT,
25182 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25183 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25184 DAG.getConstant(1, VT));
25185 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25186 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25187 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25188 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25191 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25192 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25193 TargetLowering::DAGCombinerInfo &DCI,
25194 const X86Subtarget *Subtarget) {
25196 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25197 SDValue EFLAGS = N->getOperand(1);
25199 if (CC == X86::COND_A) {
25200 // Try to convert COND_A into COND_B in an attempt to facilitate
25201 // materializing "setb reg".
25203 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25204 // cannot take an immediate as its first operand.
25206 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25207 EFLAGS.getValueType().isInteger() &&
25208 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25209 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25210 EFLAGS.getNode()->getVTList(),
25211 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25212 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25213 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25217 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25218 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25220 if (CC == X86::COND_B)
25221 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25225 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25226 if (Flags.getNode()) {
25227 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25228 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25234 // Optimize branch condition evaluation.
25236 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25237 TargetLowering::DAGCombinerInfo &DCI,
25238 const X86Subtarget *Subtarget) {
25240 SDValue Chain = N->getOperand(0);
25241 SDValue Dest = N->getOperand(1);
25242 SDValue EFLAGS = N->getOperand(3);
25243 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25247 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25248 if (Flags.getNode()) {
25249 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25250 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25257 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25258 SelectionDAG &DAG) {
25259 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25260 // optimize away operation when it's from a constant.
25262 // The general transformation is:
25263 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25264 // AND(VECTOR_CMP(x,y), constant2)
25265 // constant2 = UNARYOP(constant)
25267 // Early exit if this isn't a vector operation, the operand of the
25268 // unary operation isn't a bitwise AND, or if the sizes of the operations
25269 // aren't the same.
25270 EVT VT = N->getValueType(0);
25271 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25272 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25273 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25276 // Now check that the other operand of the AND is a constant. We could
25277 // make the transformation for non-constant splats as well, but it's unclear
25278 // that would be a benefit as it would not eliminate any operations, just
25279 // perform one more step in scalar code before moving to the vector unit.
25280 if (BuildVectorSDNode *BV =
25281 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25282 // Bail out if the vector isn't a constant.
25283 if (!BV->isConstant())
25286 // Everything checks out. Build up the new and improved node.
25288 EVT IntVT = BV->getValueType(0);
25289 // Create a new constant of the appropriate type for the transformed
25291 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25292 // The AND node needs bitcasts to/from an integer vector type around it.
25293 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25294 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25295 N->getOperand(0)->getOperand(0), MaskConst);
25296 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25303 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25304 const X86TargetLowering *XTLI) {
25305 // First try to optimize away the conversion entirely when it's
25306 // conditionally from a constant. Vectors only.
25307 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25308 if (Res != SDValue())
25311 // Now move on to more general possibilities.
25312 SDValue Op0 = N->getOperand(0);
25313 EVT InVT = Op0->getValueType(0);
25315 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25316 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25318 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25319 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25320 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25323 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25324 // a 32-bit target where SSE doesn't support i64->FP operations.
25325 if (Op0.getOpcode() == ISD::LOAD) {
25326 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25327 EVT VT = Ld->getValueType(0);
25328 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25329 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25330 !XTLI->getSubtarget()->is64Bit() &&
25332 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25333 Ld->getChain(), Op0, DAG);
25334 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25341 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25342 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25343 X86TargetLowering::DAGCombinerInfo &DCI) {
25344 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25345 // the result is either zero or one (depending on the input carry bit).
25346 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25347 if (X86::isZeroNode(N->getOperand(0)) &&
25348 X86::isZeroNode(N->getOperand(1)) &&
25349 // We don't have a good way to replace an EFLAGS use, so only do this when
25351 SDValue(N, 1).use_empty()) {
25353 EVT VT = N->getValueType(0);
25354 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25355 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25356 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25357 DAG.getConstant(X86::COND_B,MVT::i8),
25359 DAG.getConstant(1, VT));
25360 return DCI.CombineTo(N, Res1, CarryOut);
25366 // fold (add Y, (sete X, 0)) -> adc 0, Y
25367 // (add Y, (setne X, 0)) -> sbb -1, Y
25368 // (sub (sete X, 0), Y) -> sbb 0, Y
25369 // (sub (setne X, 0), Y) -> adc -1, Y
25370 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25373 // Look through ZExts.
25374 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25375 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25378 SDValue SetCC = Ext.getOperand(0);
25379 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25382 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25383 if (CC != X86::COND_E && CC != X86::COND_NE)
25386 SDValue Cmp = SetCC.getOperand(1);
25387 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25388 !X86::isZeroNode(Cmp.getOperand(1)) ||
25389 !Cmp.getOperand(0).getValueType().isInteger())
25392 SDValue CmpOp0 = Cmp.getOperand(0);
25393 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25394 DAG.getConstant(1, CmpOp0.getValueType()));
25396 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25397 if (CC == X86::COND_NE)
25398 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25399 DL, OtherVal.getValueType(), OtherVal,
25400 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25401 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25402 DL, OtherVal.getValueType(), OtherVal,
25403 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25406 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25407 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25408 const X86Subtarget *Subtarget) {
25409 EVT VT = N->getValueType(0);
25410 SDValue Op0 = N->getOperand(0);
25411 SDValue Op1 = N->getOperand(1);
25413 // Try to synthesize horizontal adds from adds of shuffles.
25414 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25415 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25416 isHorizontalBinOp(Op0, Op1, true))
25417 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25419 return OptimizeConditionalInDecrement(N, DAG);
25422 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25423 const X86Subtarget *Subtarget) {
25424 SDValue Op0 = N->getOperand(0);
25425 SDValue Op1 = N->getOperand(1);
25427 // X86 can't encode an immediate LHS of a sub. See if we can push the
25428 // negation into a preceding instruction.
25429 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25430 // If the RHS of the sub is a XOR with one use and a constant, invert the
25431 // immediate. Then add one to the LHS of the sub so we can turn
25432 // X-Y -> X+~Y+1, saving one register.
25433 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25434 isa<ConstantSDNode>(Op1.getOperand(1))) {
25435 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25436 EVT VT = Op0.getValueType();
25437 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25439 DAG.getConstant(~XorC, VT));
25440 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25441 DAG.getConstant(C->getAPIntValue()+1, VT));
25445 // Try to synthesize horizontal adds from adds of shuffles.
25446 EVT VT = N->getValueType(0);
25447 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25448 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25449 isHorizontalBinOp(Op0, Op1, true))
25450 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25452 return OptimizeConditionalInDecrement(N, DAG);
25455 /// performVZEXTCombine - Performs build vector combines
25456 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25457 TargetLowering::DAGCombinerInfo &DCI,
25458 const X86Subtarget *Subtarget) {
25460 MVT VT = N->getSimpleValueType(0);
25461 SDValue Op = N->getOperand(0);
25462 MVT OpVT = Op.getSimpleValueType();
25463 MVT OpEltVT = OpVT.getVectorElementType();
25464 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25466 // (vzext (bitcast (vzext (x)) -> (vzext x)
25468 while (V.getOpcode() == ISD::BITCAST)
25469 V = V.getOperand(0);
25471 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25472 MVT InnerVT = V.getSimpleValueType();
25473 MVT InnerEltVT = InnerVT.getVectorElementType();
25475 // If the element sizes match exactly, we can just do one larger vzext. This
25476 // is always an exact type match as vzext operates on integer types.
25477 if (OpEltVT == InnerEltVT) {
25478 assert(OpVT == InnerVT && "Types must match for vzext!");
25479 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25482 // The only other way we can combine them is if only a single element of the
25483 // inner vzext is used in the input to the outer vzext.
25484 if (InnerEltVT.getSizeInBits() < InputBits)
25487 // In this case, the inner vzext is completely dead because we're going to
25488 // only look at bits inside of the low element. Just do the outer vzext on
25489 // a bitcast of the input to the inner.
25490 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25491 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25494 // Check if we can bypass extracting and re-inserting an element of an input
25495 // vector. Essentialy:
25496 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25497 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25498 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25499 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25500 SDValue ExtractedV = V.getOperand(0);
25501 SDValue OrigV = ExtractedV.getOperand(0);
25502 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25503 if (ExtractIdx->getZExtValue() == 0) {
25504 MVT OrigVT = OrigV.getSimpleValueType();
25505 // Extract a subvector if necessary...
25506 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25507 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25508 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25509 OrigVT.getVectorNumElements() / Ratio);
25510 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25511 DAG.getIntPtrConstant(0));
25513 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25514 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25521 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25522 DAGCombinerInfo &DCI) const {
25523 SelectionDAG &DAG = DCI.DAG;
25524 switch (N->getOpcode()) {
25526 case ISD::EXTRACT_VECTOR_ELT:
25527 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25530 case X86ISD::SHRUNKBLEND:
25531 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25532 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25533 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25534 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25535 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25536 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25539 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25540 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25541 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25542 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25543 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25544 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25545 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25546 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25547 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25549 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25551 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25552 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25553 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25554 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25555 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25556 case ISD::ANY_EXTEND:
25557 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25558 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25559 case ISD::SIGN_EXTEND_INREG:
25560 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25561 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25562 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25563 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25564 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25565 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25566 case X86ISD::SHUFP: // Handle all target specific shuffles
25567 case X86ISD::PALIGNR:
25568 case X86ISD::UNPCKH:
25569 case X86ISD::UNPCKL:
25570 case X86ISD::MOVHLPS:
25571 case X86ISD::MOVLHPS:
25572 case X86ISD::PSHUFB:
25573 case X86ISD::PSHUFD:
25574 case X86ISD::PSHUFHW:
25575 case X86ISD::PSHUFLW:
25576 case X86ISD::MOVSS:
25577 case X86ISD::MOVSD:
25578 case X86ISD::VPERMILPI:
25579 case X86ISD::VPERM2X128:
25580 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25581 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25582 case ISD::INTRINSIC_WO_CHAIN:
25583 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25584 case X86ISD::INSERTPS:
25585 return PerformINSERTPSCombine(N, DAG, Subtarget);
25586 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25592 /// isTypeDesirableForOp - Return true if the target has native support for
25593 /// the specified value type and it is 'desirable' to use the type for the
25594 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25595 /// instruction encodings are longer and some i16 instructions are slow.
25596 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25597 if (!isTypeLegal(VT))
25599 if (VT != MVT::i16)
25606 case ISD::SIGN_EXTEND:
25607 case ISD::ZERO_EXTEND:
25608 case ISD::ANY_EXTEND:
25621 /// IsDesirableToPromoteOp - This method query the target whether it is
25622 /// beneficial for dag combiner to promote the specified node. If true, it
25623 /// should return the desired promotion type by reference.
25624 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25625 EVT VT = Op.getValueType();
25626 if (VT != MVT::i16)
25629 bool Promote = false;
25630 bool Commute = false;
25631 switch (Op.getOpcode()) {
25634 LoadSDNode *LD = cast<LoadSDNode>(Op);
25635 // If the non-extending load has a single use and it's not live out, then it
25636 // might be folded.
25637 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25638 Op.hasOneUse()*/) {
25639 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25640 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25641 // The only case where we'd want to promote LOAD (rather then it being
25642 // promoted as an operand is when it's only use is liveout.
25643 if (UI->getOpcode() != ISD::CopyToReg)
25650 case ISD::SIGN_EXTEND:
25651 case ISD::ZERO_EXTEND:
25652 case ISD::ANY_EXTEND:
25657 SDValue N0 = Op.getOperand(0);
25658 // Look out for (store (shl (load), x)).
25659 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25672 SDValue N0 = Op.getOperand(0);
25673 SDValue N1 = Op.getOperand(1);
25674 if (!Commute && MayFoldLoad(N1))
25676 // Avoid disabling potential load folding opportunities.
25677 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25679 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25689 //===----------------------------------------------------------------------===//
25690 // X86 Inline Assembly Support
25691 //===----------------------------------------------------------------------===//
25694 // Helper to match a string separated by whitespace.
25695 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25696 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25698 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25699 StringRef piece(*args[i]);
25700 if (!s.startswith(piece)) // Check if the piece matches.
25703 s = s.substr(piece.size());
25704 StringRef::size_type pos = s.find_first_not_of(" \t");
25705 if (pos == 0) // We matched a prefix.
25713 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25716 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25718 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25719 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25720 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25721 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25723 if (AsmPieces.size() == 3)
25725 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25732 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25733 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25735 std::string AsmStr = IA->getAsmString();
25737 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25738 if (!Ty || Ty->getBitWidth() % 16 != 0)
25741 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25742 SmallVector<StringRef, 4> AsmPieces;
25743 SplitString(AsmStr, AsmPieces, ";\n");
25745 switch (AsmPieces.size()) {
25746 default: return false;
25748 // FIXME: this should verify that we are targeting a 486 or better. If not,
25749 // we will turn this bswap into something that will be lowered to logical
25750 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25751 // lower so don't worry about this.
25753 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25754 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25755 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25756 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25757 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25758 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25759 // No need to check constraints, nothing other than the equivalent of
25760 // "=r,0" would be valid here.
25761 return IntrinsicLowering::LowerToByteSwap(CI);
25764 // rorw $$8, ${0:w} --> llvm.bswap.i16
25765 if (CI->getType()->isIntegerTy(16) &&
25766 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25767 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25768 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25770 const std::string &ConstraintsStr = IA->getConstraintString();
25771 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25772 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25773 if (clobbersFlagRegisters(AsmPieces))
25774 return IntrinsicLowering::LowerToByteSwap(CI);
25778 if (CI->getType()->isIntegerTy(32) &&
25779 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25780 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25781 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25782 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25784 const std::string &ConstraintsStr = IA->getConstraintString();
25785 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25786 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25787 if (clobbersFlagRegisters(AsmPieces))
25788 return IntrinsicLowering::LowerToByteSwap(CI);
25791 if (CI->getType()->isIntegerTy(64)) {
25792 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25793 if (Constraints.size() >= 2 &&
25794 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25795 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25796 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25797 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25798 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25799 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25800 return IntrinsicLowering::LowerToByteSwap(CI);
25808 /// getConstraintType - Given a constraint letter, return the type of
25809 /// constraint it is for this target.
25810 X86TargetLowering::ConstraintType
25811 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25812 if (Constraint.size() == 1) {
25813 switch (Constraint[0]) {
25824 return C_RegisterClass;
25848 return TargetLowering::getConstraintType(Constraint);
25851 /// Examine constraint type and operand type and determine a weight value.
25852 /// This object must already have been set up with the operand type
25853 /// and the current alternative constraint selected.
25854 TargetLowering::ConstraintWeight
25855 X86TargetLowering::getSingleConstraintMatchWeight(
25856 AsmOperandInfo &info, const char *constraint) const {
25857 ConstraintWeight weight = CW_Invalid;
25858 Value *CallOperandVal = info.CallOperandVal;
25859 // If we don't have a value, we can't do a match,
25860 // but allow it at the lowest weight.
25861 if (!CallOperandVal)
25863 Type *type = CallOperandVal->getType();
25864 // Look at the constraint type.
25865 switch (*constraint) {
25867 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25878 if (CallOperandVal->getType()->isIntegerTy())
25879 weight = CW_SpecificReg;
25884 if (type->isFloatingPointTy())
25885 weight = CW_SpecificReg;
25888 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25889 weight = CW_SpecificReg;
25893 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25894 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25895 weight = CW_Register;
25898 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25899 if (C->getZExtValue() <= 31)
25900 weight = CW_Constant;
25904 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25905 if (C->getZExtValue() <= 63)
25906 weight = CW_Constant;
25910 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25911 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25912 weight = CW_Constant;
25916 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25917 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25918 weight = CW_Constant;
25922 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25923 if (C->getZExtValue() <= 3)
25924 weight = CW_Constant;
25928 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25929 if (C->getZExtValue() <= 0xff)
25930 weight = CW_Constant;
25935 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25936 weight = CW_Constant;
25940 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25941 if ((C->getSExtValue() >= -0x80000000LL) &&
25942 (C->getSExtValue() <= 0x7fffffffLL))
25943 weight = CW_Constant;
25947 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25948 if (C->getZExtValue() <= 0xffffffff)
25949 weight = CW_Constant;
25956 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25957 /// with another that has more specific requirements based on the type of the
25958 /// corresponding operand.
25959 const char *X86TargetLowering::
25960 LowerXConstraint(EVT ConstraintVT) const {
25961 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25962 // 'f' like normal targets.
25963 if (ConstraintVT.isFloatingPoint()) {
25964 if (Subtarget->hasSSE2())
25966 if (Subtarget->hasSSE1())
25970 return TargetLowering::LowerXConstraint(ConstraintVT);
25973 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25974 /// vector. If it is invalid, don't add anything to Ops.
25975 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25976 std::string &Constraint,
25977 std::vector<SDValue>&Ops,
25978 SelectionDAG &DAG) const {
25981 // Only support length 1 constraints for now.
25982 if (Constraint.length() > 1) return;
25984 char ConstraintLetter = Constraint[0];
25985 switch (ConstraintLetter) {
25988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25989 if (C->getZExtValue() <= 31) {
25990 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25997 if (C->getZExtValue() <= 63) {
25998 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26005 if (isInt<8>(C->getSExtValue())) {
26006 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26013 if (C->getZExtValue() <= 255) {
26014 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26020 // 32-bit signed value
26021 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26022 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26023 C->getSExtValue())) {
26024 // Widen to 64 bits here to get it sign extended.
26025 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26028 // FIXME gcc accepts some relocatable values here too, but only in certain
26029 // memory models; it's complicated.
26034 // 32-bit unsigned value
26035 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26036 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26037 C->getZExtValue())) {
26038 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26042 // FIXME gcc accepts some relocatable values here too, but only in certain
26043 // memory models; it's complicated.
26047 // Literal immediates are always ok.
26048 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26049 // Widen to 64 bits here to get it sign extended.
26050 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26054 // In any sort of PIC mode addresses need to be computed at runtime by
26055 // adding in a register or some sort of table lookup. These can't
26056 // be used as immediates.
26057 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26060 // If we are in non-pic codegen mode, we allow the address of a global (with
26061 // an optional displacement) to be used with 'i'.
26062 GlobalAddressSDNode *GA = nullptr;
26063 int64_t Offset = 0;
26065 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26067 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26068 Offset += GA->getOffset();
26070 } else if (Op.getOpcode() == ISD::ADD) {
26071 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26072 Offset += C->getZExtValue();
26073 Op = Op.getOperand(0);
26076 } else if (Op.getOpcode() == ISD::SUB) {
26077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26078 Offset += -C->getZExtValue();
26079 Op = Op.getOperand(0);
26084 // Otherwise, this isn't something we can handle, reject it.
26088 const GlobalValue *GV = GA->getGlobal();
26089 // If we require an extra load to get this address, as in PIC mode, we
26090 // can't accept it.
26091 if (isGlobalStubReference(
26092 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26095 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26096 GA->getValueType(0), Offset);
26101 if (Result.getNode()) {
26102 Ops.push_back(Result);
26105 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26108 std::pair<unsigned, const TargetRegisterClass*>
26109 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26111 // First, see if this is a constraint that directly corresponds to an LLVM
26113 if (Constraint.size() == 1) {
26114 // GCC Constraint Letters
26115 switch (Constraint[0]) {
26117 // TODO: Slight differences here in allocation order and leaving
26118 // RIP in the class. Do they matter any more here than they do
26119 // in the normal allocation?
26120 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26121 if (Subtarget->is64Bit()) {
26122 if (VT == MVT::i32 || VT == MVT::f32)
26123 return std::make_pair(0U, &X86::GR32RegClass);
26124 if (VT == MVT::i16)
26125 return std::make_pair(0U, &X86::GR16RegClass);
26126 if (VT == MVT::i8 || VT == MVT::i1)
26127 return std::make_pair(0U, &X86::GR8RegClass);
26128 if (VT == MVT::i64 || VT == MVT::f64)
26129 return std::make_pair(0U, &X86::GR64RegClass);
26132 // 32-bit fallthrough
26133 case 'Q': // Q_REGS
26134 if (VT == MVT::i32 || VT == MVT::f32)
26135 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26136 if (VT == MVT::i16)
26137 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26138 if (VT == MVT::i8 || VT == MVT::i1)
26139 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26140 if (VT == MVT::i64)
26141 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26143 case 'r': // GENERAL_REGS
26144 case 'l': // INDEX_REGS
26145 if (VT == MVT::i8 || VT == MVT::i1)
26146 return std::make_pair(0U, &X86::GR8RegClass);
26147 if (VT == MVT::i16)
26148 return std::make_pair(0U, &X86::GR16RegClass);
26149 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26150 return std::make_pair(0U, &X86::GR32RegClass);
26151 return std::make_pair(0U, &X86::GR64RegClass);
26152 case 'R': // LEGACY_REGS
26153 if (VT == MVT::i8 || VT == MVT::i1)
26154 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26155 if (VT == MVT::i16)
26156 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26157 if (VT == MVT::i32 || !Subtarget->is64Bit())
26158 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26159 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26160 case 'f': // FP Stack registers.
26161 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26162 // value to the correct fpstack register class.
26163 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26164 return std::make_pair(0U, &X86::RFP32RegClass);
26165 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26166 return std::make_pair(0U, &X86::RFP64RegClass);
26167 return std::make_pair(0U, &X86::RFP80RegClass);
26168 case 'y': // MMX_REGS if MMX allowed.
26169 if (!Subtarget->hasMMX()) break;
26170 return std::make_pair(0U, &X86::VR64RegClass);
26171 case 'Y': // SSE_REGS if SSE2 allowed
26172 if (!Subtarget->hasSSE2()) break;
26174 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26175 if (!Subtarget->hasSSE1()) break;
26177 switch (VT.SimpleTy) {
26179 // Scalar SSE types.
26182 return std::make_pair(0U, &X86::FR32RegClass);
26185 return std::make_pair(0U, &X86::FR64RegClass);
26193 return std::make_pair(0U, &X86::VR128RegClass);
26201 return std::make_pair(0U, &X86::VR256RegClass);
26206 return std::make_pair(0U, &X86::VR512RegClass);
26212 // Use the default implementation in TargetLowering to convert the register
26213 // constraint into a member of a register class.
26214 std::pair<unsigned, const TargetRegisterClass*> Res;
26215 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26217 // Not found as a standard register?
26219 // Map st(0) -> st(7) -> ST0
26220 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26221 tolower(Constraint[1]) == 's' &&
26222 tolower(Constraint[2]) == 't' &&
26223 Constraint[3] == '(' &&
26224 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26225 Constraint[5] == ')' &&
26226 Constraint[6] == '}') {
26228 Res.first = X86::FP0+Constraint[4]-'0';
26229 Res.second = &X86::RFP80RegClass;
26233 // GCC allows "st(0)" to be called just plain "st".
26234 if (StringRef("{st}").equals_lower(Constraint)) {
26235 Res.first = X86::FP0;
26236 Res.second = &X86::RFP80RegClass;
26241 if (StringRef("{flags}").equals_lower(Constraint)) {
26242 Res.first = X86::EFLAGS;
26243 Res.second = &X86::CCRRegClass;
26247 // 'A' means EAX + EDX.
26248 if (Constraint == "A") {
26249 Res.first = X86::EAX;
26250 Res.second = &X86::GR32_ADRegClass;
26256 // Otherwise, check to see if this is a register class of the wrong value
26257 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26258 // turn into {ax},{dx}.
26259 if (Res.second->hasType(VT))
26260 return Res; // Correct type already, nothing to do.
26262 // All of the single-register GCC register classes map their values onto
26263 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26264 // really want an 8-bit or 32-bit register, map to the appropriate register
26265 // class and return the appropriate register.
26266 if (Res.second == &X86::GR16RegClass) {
26267 if (VT == MVT::i8 || VT == MVT::i1) {
26268 unsigned DestReg = 0;
26269 switch (Res.first) {
26271 case X86::AX: DestReg = X86::AL; break;
26272 case X86::DX: DestReg = X86::DL; break;
26273 case X86::CX: DestReg = X86::CL; break;
26274 case X86::BX: DestReg = X86::BL; break;
26277 Res.first = DestReg;
26278 Res.second = &X86::GR8RegClass;
26280 } else if (VT == MVT::i32 || VT == MVT::f32) {
26281 unsigned DestReg = 0;
26282 switch (Res.first) {
26284 case X86::AX: DestReg = X86::EAX; break;
26285 case X86::DX: DestReg = X86::EDX; break;
26286 case X86::CX: DestReg = X86::ECX; break;
26287 case X86::BX: DestReg = X86::EBX; break;
26288 case X86::SI: DestReg = X86::ESI; break;
26289 case X86::DI: DestReg = X86::EDI; break;
26290 case X86::BP: DestReg = X86::EBP; break;
26291 case X86::SP: DestReg = X86::ESP; break;
26294 Res.first = DestReg;
26295 Res.second = &X86::GR32RegClass;
26297 } else if (VT == MVT::i64 || VT == MVT::f64) {
26298 unsigned DestReg = 0;
26299 switch (Res.first) {
26301 case X86::AX: DestReg = X86::RAX; break;
26302 case X86::DX: DestReg = X86::RDX; break;
26303 case X86::CX: DestReg = X86::RCX; break;
26304 case X86::BX: DestReg = X86::RBX; break;
26305 case X86::SI: DestReg = X86::RSI; break;
26306 case X86::DI: DestReg = X86::RDI; break;
26307 case X86::BP: DestReg = X86::RBP; break;
26308 case X86::SP: DestReg = X86::RSP; break;
26311 Res.first = DestReg;
26312 Res.second = &X86::GR64RegClass;
26315 } else if (Res.second == &X86::FR32RegClass ||
26316 Res.second == &X86::FR64RegClass ||
26317 Res.second == &X86::VR128RegClass ||
26318 Res.second == &X86::VR256RegClass ||
26319 Res.second == &X86::FR32XRegClass ||
26320 Res.second == &X86::FR64XRegClass ||
26321 Res.second == &X86::VR128XRegClass ||
26322 Res.second == &X86::VR256XRegClass ||
26323 Res.second == &X86::VR512RegClass) {
26324 // Handle references to XMM physical registers that got mapped into the
26325 // wrong class. This can happen with constraints like {xmm0} where the
26326 // target independent register mapper will just pick the first match it can
26327 // find, ignoring the required type.
26329 if (VT == MVT::f32 || VT == MVT::i32)
26330 Res.second = &X86::FR32RegClass;
26331 else if (VT == MVT::f64 || VT == MVT::i64)
26332 Res.second = &X86::FR64RegClass;
26333 else if (X86::VR128RegClass.hasType(VT))
26334 Res.second = &X86::VR128RegClass;
26335 else if (X86::VR256RegClass.hasType(VT))
26336 Res.second = &X86::VR256RegClass;
26337 else if (X86::VR512RegClass.hasType(VT))
26338 Res.second = &X86::VR512RegClass;
26344 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26346 // Scaling factors are not free at all.
26347 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26348 // will take 2 allocations in the out of order engine instead of 1
26349 // for plain addressing mode, i.e. inst (reg1).
26351 // vaddps (%rsi,%drx), %ymm0, %ymm1
26352 // Requires two allocations (one for the load, one for the computation)
26354 // vaddps (%rsi), %ymm0, %ymm1
26355 // Requires just 1 allocation, i.e., freeing allocations for other operations
26356 // and having less micro operations to execute.
26358 // For some X86 architectures, this is even worse because for instance for
26359 // stores, the complex addressing mode forces the instruction to use the
26360 // "load" ports instead of the dedicated "store" port.
26361 // E.g., on Haswell:
26362 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26363 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26364 if (isLegalAddressingMode(AM, Ty))
26365 // Scale represents reg2 * scale, thus account for 1
26366 // as soon as we use a second register.
26367 return AM.Scale != 0;
26371 bool X86TargetLowering::isTargetFTOL() const {
26372 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();