1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!Subtarget->useSoftFloat()) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!Subtarget->useSoftFloat()) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!Subtarget->useSoftFloat()) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
835 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
836 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
837 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
845 // Only provide customized ctpop vector bit twiddling for vector types we
846 // know to perform better than using the popcnt instructions on each vector
847 // element. If popcnt isn't supported, always provide the custom version.
848 if (!Subtarget->hasPOPCNT()) {
849 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
853 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
854 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
855 MVT VT = (MVT::SimpleValueType)i;
856 // Do not attempt to custom lower non-power-of-2 vectors
857 if (!isPowerOf2_32(VT.getVectorNumElements()))
859 // Do not attempt to custom lower non-128-bit vectors
860 if (!VT.is128BitVector())
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::VSELECT, VT, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
868 // We support custom legalizing of sext and anyext loads for specific
869 // memory vector types which we can load as a scalar (or sequence of
870 // scalars) and extend in-register to a legal 128-bit vector type. For sext
871 // loads these must work with a single scalar load.
872 for (MVT VT : MVT::integer_vector_valuetypes()) {
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
889 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to promote non-128-bit vectors
903 if (!VT.is128BitVector())
906 setOperationAction(ISD::AND, VT, Promote);
907 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
908 setOperationAction(ISD::OR, VT, Promote);
909 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
910 setOperationAction(ISD::XOR, VT, Promote);
911 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
912 setOperationAction(ISD::LOAD, VT, Promote);
913 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
914 setOperationAction(ISD::SELECT, VT, Promote);
915 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
918 // Custom lower v2i64 and v2f64 selects.
919 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
920 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
921 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
922 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
924 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 // FIXME: Do we need to handle scalar-to-vector here?
955 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
957 // We directly match byte blends in the backend as they match the VSELECT
959 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
961 // SSE41 brings specific instructions for doing vector sign extend even in
962 // cases where we don't have SRA.
963 for (MVT VT : MVT::integer_vector_valuetypes()) {
964 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
965 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
966 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
969 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
970 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
971 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
972 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
973 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
974 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
977 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
978 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
979 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
980 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
981 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
984 // i8 and i16 vectors are custom because the source register and source
985 // source memory operand types are not the same width. f32 vectors are
986 // custom since the immediate controlling the insert encodes additional
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
994 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
998 // FIXME: these should be Legal, but that's only for the case where
999 // the index is constant. For now custom expand to deal with that.
1000 if (Subtarget->is64Bit()) {
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1006 if (Subtarget->hasSSE2()) {
1007 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1008 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1010 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1011 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1013 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1014 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1016 // In the customized shift lowering, the legal cases in AVX2 will be
1018 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1019 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1021 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1022 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1024 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1027 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1028 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1029 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1030 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1031 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1032 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1033 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1035 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1036 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1037 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1039 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1047 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1049 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1050 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1052 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1058 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1060 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1061 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1062 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1063 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1065 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1066 // even though v8i16 is a legal type.
1067 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1068 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1071 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1072 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1073 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1075 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1076 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1078 for (MVT VT : MVT::fp_vector_valuetypes())
1079 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1081 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1084 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1085 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1087 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1088 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1090 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1091 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1092 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1093 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1095 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1096 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1097 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1099 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1100 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1101 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1103 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1104 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1105 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1106 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1107 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1108 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1109 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1110 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1112 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1113 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1114 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1115 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1116 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FMA, MVT::f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::f64, Legal);
1121 if (Subtarget->hasInt256()) {
1122 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1123 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1124 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1125 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1127 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1128 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1129 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1130 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1132 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1133 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1134 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1135 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1137 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1139 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1140 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1142 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1143 // when we have a 256bit-wide blend with immediate.
1144 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1146 // Only provide customized ctpop vector bit twiddling for vector types we
1147 // know to perform better than using the popcnt instructions on each
1148 // vector element. If popcnt isn't supported, always provide the custom
1150 if (!Subtarget->hasPOPCNT())
1151 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1153 // Custom CTPOP always performs better on natively supported v8i32
1154 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1156 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1157 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1158 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1159 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1160 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1161 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1162 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1164 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1165 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1166 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1167 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1168 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1169 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1171 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1172 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1173 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1174 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1177 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1181 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1182 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1183 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1184 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1187 // In the customized shift lowering, the legal cases in AVX2 will be
1189 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1190 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1192 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1195 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1197 // Custom lower several nodes for 256-bit types.
1198 for (MVT VT : MVT::vector_valuetypes()) {
1199 if (VT.getScalarSizeInBits() >= 32) {
1200 setOperationAction(ISD::MLOAD, VT, Legal);
1201 setOperationAction(ISD::MSTORE, VT, Legal);
1203 // Extract subvector is special because the value type
1204 // (result) is 128-bit but the source is 256-bit wide.
1205 if (VT.is128BitVector()) {
1206 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1208 // Do not attempt to custom lower other non-256-bit vectors
1209 if (!VT.is256BitVector())
1212 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1213 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1214 setOperationAction(ISD::VSELECT, VT, Custom);
1215 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1216 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1217 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1218 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1219 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1222 if (Subtarget->hasInt256())
1223 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1226 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1227 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1228 MVT VT = (MVT::SimpleValueType)i;
1230 // Do not attempt to promote non-256-bit vectors
1231 if (!VT.is256BitVector())
1234 setOperationAction(ISD::AND, VT, Promote);
1235 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1236 setOperationAction(ISD::OR, VT, Promote);
1237 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1238 setOperationAction(ISD::XOR, VT, Promote);
1239 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1240 setOperationAction(ISD::LOAD, VT, Promote);
1241 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1242 setOperationAction(ISD::SELECT, VT, Promote);
1243 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1247 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1248 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1249 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1250 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1251 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1253 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1254 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1255 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1257 for (MVT VT : MVT::fp_vector_valuetypes())
1258 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1260 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1261 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1262 setOperationAction(ISD::XOR, MVT::i1, Legal);
1263 setOperationAction(ISD::OR, MVT::i1, Legal);
1264 setOperationAction(ISD::AND, MVT::i1, Legal);
1265 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1266 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1267 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1268 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1269 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1271 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1272 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1273 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1274 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1275 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1276 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1278 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1279 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1280 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1281 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1282 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1283 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1284 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1285 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1287 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1288 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1289 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1290 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1291 if (Subtarget->is64Bit()) {
1292 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1293 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1294 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1295 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1297 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1298 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1299 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1300 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1301 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1302 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1303 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1304 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1305 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1306 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1307 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1308 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1309 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1310 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1311 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1312 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1314 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1315 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1316 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1317 if (Subtarget->hasDQI()) {
1318 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1319 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1321 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1322 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1323 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1324 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1325 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1326 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1327 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1328 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1329 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1330 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1331 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1332 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1333 if (Subtarget->hasDQI()) {
1334 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1335 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1337 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1339 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1341 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1343 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1348 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1349 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1350 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1351 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1352 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1354 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1355 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1357 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1359 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1360 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1361 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1362 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1363 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1364 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1365 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1366 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1367 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1368 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1371 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1372 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1374 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1375 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1377 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1379 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1380 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1382 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1383 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1385 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1386 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1388 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1389 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1390 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1391 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1392 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1393 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1395 if (Subtarget->hasCDI()) {
1396 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1397 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1401 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1402 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1404 // Custom lower several nodes.
1405 for (MVT VT : MVT::vector_valuetypes()) {
1406 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1408 setOperationAction(ISD::AND, VT, Legal);
1409 setOperationAction(ISD::OR, VT, Legal);
1410 setOperationAction(ISD::XOR, VT, Legal);
1412 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1413 setOperationAction(ISD::MGATHER, VT, Custom);
1414 setOperationAction(ISD::MSCATTER, VT, Custom);
1416 // Extract subvector is special because the value type
1417 // (result) is 256/128-bit but the source is 512-bit wide.
1418 if (VT.is128BitVector() || VT.is256BitVector()) {
1419 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1421 if (VT.getVectorElementType() == MVT::i1)
1422 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1424 // Do not attempt to custom lower other non-512-bit vectors
1425 if (!VT.is512BitVector())
1428 if (EltSize >= 32) {
1429 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1430 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1431 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1432 setOperationAction(ISD::VSELECT, VT, Legal);
1433 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1434 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1435 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1436 setOperationAction(ISD::MLOAD, VT, Legal);
1437 setOperationAction(ISD::MSTORE, VT, Legal);
1440 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1441 MVT VT = (MVT::SimpleValueType)i;
1443 // Do not attempt to promote non-512-bit vectors.
1444 if (!VT.is512BitVector())
1447 setOperationAction(ISD::SELECT, VT, Promote);
1448 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1452 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1453 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1454 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1456 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1457 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1459 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1460 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1463 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1464 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1465 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1466 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1467 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1468 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1470 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1471 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1475 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1476 const MVT VT = (MVT::SimpleValueType)i;
1478 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1480 // Do not attempt to promote non-512-bit vectors.
1481 if (!VT.is512BitVector())
1485 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1486 setOperationAction(ISD::VSELECT, VT, Legal);
1491 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1492 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1493 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1495 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1496 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1497 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1498 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1499 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1500 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1501 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1502 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1507 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1510 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1511 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1514 // We want to custom lower some of our intrinsics.
1515 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1516 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1517 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1518 if (!Subtarget->is64Bit())
1519 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1521 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1522 // handle type legalization for these operations here.
1524 // FIXME: We really should do custom legalization for addition and
1525 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1526 // than generic legalization for 64-bit multiplication-with-overflow, though.
1527 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1528 // Add/Sub/Mul with overflow operations are custom lowered.
1530 setOperationAction(ISD::SADDO, VT, Custom);
1531 setOperationAction(ISD::UADDO, VT, Custom);
1532 setOperationAction(ISD::SSUBO, VT, Custom);
1533 setOperationAction(ISD::USUBO, VT, Custom);
1534 setOperationAction(ISD::SMULO, VT, Custom);
1535 setOperationAction(ISD::UMULO, VT, Custom);
1539 if (!Subtarget->is64Bit()) {
1540 // These libcalls are not available in 32-bit.
1541 setLibcallName(RTLIB::SHL_I128, nullptr);
1542 setLibcallName(RTLIB::SRL_I128, nullptr);
1543 setLibcallName(RTLIB::SRA_I128, nullptr);
1546 // Combine sin / cos into one node or libcall if possible.
1547 if (Subtarget->hasSinCos()) {
1548 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1549 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1550 if (Subtarget->isTargetDarwin()) {
1551 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1552 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1553 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1554 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1558 if (Subtarget->isTargetWin64()) {
1559 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1560 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1561 setOperationAction(ISD::SREM, MVT::i128, Custom);
1562 setOperationAction(ISD::UREM, MVT::i128, Custom);
1563 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1564 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1567 // We have target-specific dag combine patterns for the following nodes:
1568 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1569 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1570 setTargetDAGCombine(ISD::BITCAST);
1571 setTargetDAGCombine(ISD::VSELECT);
1572 setTargetDAGCombine(ISD::SELECT);
1573 setTargetDAGCombine(ISD::SHL);
1574 setTargetDAGCombine(ISD::SRA);
1575 setTargetDAGCombine(ISD::SRL);
1576 setTargetDAGCombine(ISD::OR);
1577 setTargetDAGCombine(ISD::AND);
1578 setTargetDAGCombine(ISD::ADD);
1579 setTargetDAGCombine(ISD::FADD);
1580 setTargetDAGCombine(ISD::FSUB);
1581 setTargetDAGCombine(ISD::FMA);
1582 setTargetDAGCombine(ISD::SUB);
1583 setTargetDAGCombine(ISD::LOAD);
1584 setTargetDAGCombine(ISD::MLOAD);
1585 setTargetDAGCombine(ISD::STORE);
1586 setTargetDAGCombine(ISD::MSTORE);
1587 setTargetDAGCombine(ISD::ZERO_EXTEND);
1588 setTargetDAGCombine(ISD::ANY_EXTEND);
1589 setTargetDAGCombine(ISD::SIGN_EXTEND);
1590 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1591 setTargetDAGCombine(ISD::SINT_TO_FP);
1592 setTargetDAGCombine(ISD::SETCC);
1593 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1594 setTargetDAGCombine(ISD::BUILD_VECTOR);
1595 setTargetDAGCombine(ISD::MUL);
1596 setTargetDAGCombine(ISD::XOR);
1598 computeRegisterProperties(Subtarget->getRegisterInfo());
1600 // On Darwin, -Os means optimize for size without hurting performance,
1601 // do not reduce the limit.
1602 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1603 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1604 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1605 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1606 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1607 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1608 setPrefLoopAlignment(4); // 2^4 bytes.
1610 // Predictable cmov don't hurt on atom because it's in-order.
1611 PredictableSelectIsExpensive = !Subtarget->isAtom();
1612 EnableExtLdPromotion = true;
1613 setPrefFunctionAlignment(4); // 2^4 bytes.
1615 verifyIntrinsicTables();
1618 // This has so far only been implemented for 64-bit MachO.
1619 bool X86TargetLowering::useLoadStackGuardNode() const {
1620 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1623 TargetLoweringBase::LegalizeTypeAction
1624 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1625 if (ExperimentalVectorWideningLegalization &&
1626 VT.getVectorNumElements() != 1 &&
1627 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1628 return TypeWidenVector;
1630 return TargetLoweringBase::getPreferredVectorAction(VT);
1633 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1635 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1637 const unsigned NumElts = VT.getVectorNumElements();
1638 const EVT EltVT = VT.getVectorElementType();
1639 if (VT.is512BitVector()) {
1640 if (Subtarget->hasAVX512())
1641 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1642 EltVT == MVT::f32 || EltVT == MVT::f64)
1644 case 8: return MVT::v8i1;
1645 case 16: return MVT::v16i1;
1647 if (Subtarget->hasBWI())
1648 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1650 case 32: return MVT::v32i1;
1651 case 64: return MVT::v64i1;
1655 if (VT.is256BitVector() || VT.is128BitVector()) {
1656 if (Subtarget->hasVLX())
1657 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1658 EltVT == MVT::f32 || EltVT == MVT::f64)
1660 case 2: return MVT::v2i1;
1661 case 4: return MVT::v4i1;
1662 case 8: return MVT::v8i1;
1664 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1665 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1667 case 8: return MVT::v8i1;
1668 case 16: return MVT::v16i1;
1669 case 32: return MVT::v32i1;
1673 return VT.changeVectorElementTypeToInteger();
1676 /// Helper for getByValTypeAlignment to determine
1677 /// the desired ByVal argument alignment.
1678 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1681 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1682 if (VTy->getBitWidth() == 128)
1684 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1685 unsigned EltAlign = 0;
1686 getMaxByValAlign(ATy->getElementType(), EltAlign);
1687 if (EltAlign > MaxAlign)
1688 MaxAlign = EltAlign;
1689 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1690 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1691 unsigned EltAlign = 0;
1692 getMaxByValAlign(STy->getElementType(i), EltAlign);
1693 if (EltAlign > MaxAlign)
1694 MaxAlign = EltAlign;
1701 /// Return the desired alignment for ByVal aggregate
1702 /// function arguments in the caller parameter area. For X86, aggregates
1703 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1704 /// are at 4-byte boundaries.
1705 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1706 if (Subtarget->is64Bit()) {
1707 // Max of 8 and alignment of type.
1708 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1715 if (Subtarget->hasSSE1())
1716 getMaxByValAlign(Ty, Align);
1720 /// Returns the target specific optimal type for load
1721 /// and store operations as a result of memset, memcpy, and memmove
1722 /// lowering. If DstAlign is zero that means it's safe to destination
1723 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1724 /// means there isn't a need to check it against alignment requirement,
1725 /// probably because the source does not need to be loaded. If 'IsMemset' is
1726 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1727 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1728 /// source is constant so it does not need to be loaded.
1729 /// It returns EVT::Other if the type should be determined using generic
1730 /// target-independent logic.
1732 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1733 unsigned DstAlign, unsigned SrcAlign,
1734 bool IsMemset, bool ZeroMemset,
1736 MachineFunction &MF) const {
1737 const Function *F = MF.getFunction();
1738 if ((!IsMemset || ZeroMemset) &&
1739 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1741 (Subtarget->isUnalignedMemAccessFast() ||
1742 ((DstAlign == 0 || DstAlign >= 16) &&
1743 (SrcAlign == 0 || SrcAlign >= 16)))) {
1745 if (Subtarget->hasInt256())
1747 if (Subtarget->hasFp256())
1750 if (Subtarget->hasSSE2())
1752 if (Subtarget->hasSSE1())
1754 } else if (!MemcpyStrSrc && Size >= 8 &&
1755 !Subtarget->is64Bit() &&
1756 Subtarget->hasSSE2()) {
1757 // Do not use f64 to lower memcpy if source is string constant. It's
1758 // better to use i32 to avoid the loads.
1762 if (Subtarget->is64Bit() && Size >= 8)
1767 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1769 return X86ScalarSSEf32;
1770 else if (VT == MVT::f64)
1771 return X86ScalarSSEf64;
1776 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1781 *Fast = Subtarget->isUnalignedMemAccessFast();
1785 /// Return the entry encoding for a jump table in the
1786 /// current function. The returned value is a member of the
1787 /// MachineJumpTableInfo::JTEntryKind enum.
1788 unsigned X86TargetLowering::getJumpTableEncoding() const {
1789 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1791 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1792 Subtarget->isPICStyleGOT())
1793 return MachineJumpTableInfo::EK_Custom32;
1795 // Otherwise, use the normal jump table encoding heuristics.
1796 return TargetLowering::getJumpTableEncoding();
1799 bool X86TargetLowering::useSoftFloat() const {
1800 return Subtarget->useSoftFloat();
1804 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1805 const MachineBasicBlock *MBB,
1806 unsigned uid,MCContext &Ctx) const{
1807 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1808 Subtarget->isPICStyleGOT());
1809 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1811 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1812 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1815 /// Returns relocation base for the given PIC jumptable.
1816 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1817 SelectionDAG &DAG) const {
1818 if (!Subtarget->is64Bit())
1819 // This doesn't have SDLoc associated with it, but is not really the
1820 // same as a Register.
1821 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1825 /// This returns the relocation base for the given PIC jumptable,
1826 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1827 const MCExpr *X86TargetLowering::
1828 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1829 MCContext &Ctx) const {
1830 // X86-64 uses RIP relative addressing based on the jump table label.
1831 if (Subtarget->isPICStyleRIPRel())
1832 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1834 // Otherwise, the reference is relative to the PIC base.
1835 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1838 std::pair<const TargetRegisterClass *, uint8_t>
1839 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1841 const TargetRegisterClass *RRC = nullptr;
1843 switch (VT.SimpleTy) {
1845 return TargetLowering::findRepresentativeClass(TRI, VT);
1846 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1847 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1850 RRC = &X86::VR64RegClass;
1852 case MVT::f32: case MVT::f64:
1853 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1854 case MVT::v4f32: case MVT::v2f64:
1855 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1857 RRC = &X86::VR128RegClass;
1860 return std::make_pair(RRC, Cost);
1863 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1864 unsigned &Offset) const {
1865 if (!Subtarget->isTargetLinux())
1868 if (Subtarget->is64Bit()) {
1869 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1871 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1883 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1884 unsigned DestAS) const {
1885 assert(SrcAS != DestAS && "Expected different address spaces!");
1887 return SrcAS < 256 && DestAS < 256;
1890 //===----------------------------------------------------------------------===//
1891 // Return Value Calling Convention Implementation
1892 //===----------------------------------------------------------------------===//
1894 #include "X86GenCallingConv.inc"
1897 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1898 MachineFunction &MF, bool isVarArg,
1899 const SmallVectorImpl<ISD::OutputArg> &Outs,
1900 LLVMContext &Context) const {
1901 SmallVector<CCValAssign, 16> RVLocs;
1902 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1903 return CCInfo.CheckReturn(Outs, RetCC_X86);
1906 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1907 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1912 X86TargetLowering::LowerReturn(SDValue Chain,
1913 CallingConv::ID CallConv, bool isVarArg,
1914 const SmallVectorImpl<ISD::OutputArg> &Outs,
1915 const SmallVectorImpl<SDValue> &OutVals,
1916 SDLoc dl, SelectionDAG &DAG) const {
1917 MachineFunction &MF = DAG.getMachineFunction();
1918 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1920 SmallVector<CCValAssign, 16> RVLocs;
1921 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1922 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1925 SmallVector<SDValue, 6> RetOps;
1926 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1927 // Operand #1 = Bytes To Pop
1928 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1931 // Copy the result values into the output registers.
1932 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1933 CCValAssign &VA = RVLocs[i];
1934 assert(VA.isRegLoc() && "Can only return in registers!");
1935 SDValue ValToCopy = OutVals[i];
1936 EVT ValVT = ValToCopy.getValueType();
1938 // Promote values to the appropriate types.
1939 if (VA.getLocInfo() == CCValAssign::SExt)
1940 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1941 else if (VA.getLocInfo() == CCValAssign::ZExt)
1942 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1943 else if (VA.getLocInfo() == CCValAssign::AExt) {
1944 if (ValVT.getScalarType() == MVT::i1)
1945 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1947 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1949 else if (VA.getLocInfo() == CCValAssign::BCvt)
1950 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1952 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1953 "Unexpected FP-extend for return value.");
1955 // If this is x86-64, and we disabled SSE, we can't return FP values,
1956 // or SSE or MMX vectors.
1957 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1958 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1959 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1960 report_fatal_error("SSE register return with SSE disabled");
1962 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1963 // llvm-gcc has never done it right and no one has noticed, so this
1964 // should be OK for now.
1965 if (ValVT == MVT::f64 &&
1966 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1967 report_fatal_error("SSE2 register return with SSE2 disabled");
1969 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1970 // the RET instruction and handled by the FP Stackifier.
1971 if (VA.getLocReg() == X86::FP0 ||
1972 VA.getLocReg() == X86::FP1) {
1973 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1974 // change the value to the FP stack register class.
1975 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1976 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1977 RetOps.push_back(ValToCopy);
1978 // Don't emit a copytoreg.
1982 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1983 // which is returned in RAX / RDX.
1984 if (Subtarget->is64Bit()) {
1985 if (ValVT == MVT::x86mmx) {
1986 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1987 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1988 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1990 // If we don't have SSE2 available, convert to v4f32 so the generated
1991 // register is legal.
1992 if (!Subtarget->hasSSE2())
1993 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1998 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1999 Flag = Chain.getValue(1);
2000 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2003 // All x86 ABIs require that for returning structs by value we copy
2004 // the sret argument into %rax/%eax (depending on ABI) for the return.
2005 // We saved the argument into a virtual register in the entry block,
2006 // so now we copy the value out and into %rax/%eax.
2008 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2009 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2010 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2011 // either case FuncInfo->setSRetReturnReg() will have been called.
2012 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2013 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2016 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2017 X86::RAX : X86::EAX;
2018 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2019 Flag = Chain.getValue(1);
2021 // RAX/EAX now acts like a return value.
2022 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2025 RetOps[0] = Chain; // Update chain.
2027 // Add the flag if we have it.
2029 RetOps.push_back(Flag);
2031 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2034 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2035 if (N->getNumValues() != 1)
2037 if (!N->hasNUsesOfValue(1, 0))
2040 SDValue TCChain = Chain;
2041 SDNode *Copy = *N->use_begin();
2042 if (Copy->getOpcode() == ISD::CopyToReg) {
2043 // If the copy has a glue operand, we conservatively assume it isn't safe to
2044 // perform a tail call.
2045 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2047 TCChain = Copy->getOperand(0);
2048 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2051 bool HasRet = false;
2052 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2054 if (UI->getOpcode() != X86ISD::RET_FLAG)
2056 // If we are returning more than one value, we can definitely
2057 // not make a tail call see PR19530
2058 if (UI->getNumOperands() > 4)
2060 if (UI->getNumOperands() == 4 &&
2061 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2074 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2075 ISD::NodeType ExtendKind) const {
2077 // TODO: Is this also valid on 32-bit?
2078 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2079 ReturnMVT = MVT::i8;
2081 ReturnMVT = MVT::i32;
2083 EVT MinVT = getRegisterType(Context, ReturnMVT);
2084 return VT.bitsLT(MinVT) ? MinVT : VT;
2087 /// Lower the result values of a call into the
2088 /// appropriate copies out of appropriate physical registers.
2091 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2092 CallingConv::ID CallConv, bool isVarArg,
2093 const SmallVectorImpl<ISD::InputArg> &Ins,
2094 SDLoc dl, SelectionDAG &DAG,
2095 SmallVectorImpl<SDValue> &InVals) const {
2097 // Assign locations to each value returned by this call.
2098 SmallVector<CCValAssign, 16> RVLocs;
2099 bool Is64Bit = Subtarget->is64Bit();
2100 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2102 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2104 // Copy all of the result registers out of their specified physreg.
2105 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2106 CCValAssign &VA = RVLocs[i];
2107 EVT CopyVT = VA.getLocVT();
2109 // If this is x86-64, and we disabled SSE, we can't return FP values
2110 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2111 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2112 report_fatal_error("SSE register return with SSE disabled");
2115 // If we prefer to use the value in xmm registers, copy it out as f80 and
2116 // use a truncate to move it from fp stack reg to xmm reg.
2117 bool RoundAfterCopy = false;
2118 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2119 isScalarFPTypeInSSEReg(VA.getValVT())) {
2121 RoundAfterCopy = (CopyVT != VA.getLocVT());
2124 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2125 CopyVT, InFlag).getValue(1);
2126 SDValue Val = Chain.getValue(0);
2129 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2130 // This truncation won't change the value.
2131 DAG.getIntPtrConstant(1, dl));
2133 InFlag = Chain.getValue(2);
2134 InVals.push_back(Val);
2140 //===----------------------------------------------------------------------===//
2141 // C & StdCall & Fast Calling Convention implementation
2142 //===----------------------------------------------------------------------===//
2143 // StdCall calling convention seems to be standard for many Windows' API
2144 // routines and around. It differs from C calling convention just a little:
2145 // callee should clean up the stack, not caller. Symbols should be also
2146 // decorated in some fancy way :) It doesn't support any vector arguments.
2147 // For info on fast calling convention see Fast Calling Convention (tail call)
2148 // implementation LowerX86_32FastCCCallTo.
2150 /// CallIsStructReturn - Determines whether a call uses struct return
2152 enum StructReturnType {
2157 static StructReturnType
2158 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2160 return NotStructReturn;
2162 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2163 if (!Flags.isSRet())
2164 return NotStructReturn;
2165 if (Flags.isInReg())
2166 return RegStructReturn;
2167 return StackStructReturn;
2170 /// Determines whether a function uses struct return semantics.
2171 static StructReturnType
2172 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2174 return NotStructReturn;
2176 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2177 if (!Flags.isSRet())
2178 return NotStructReturn;
2179 if (Flags.isInReg())
2180 return RegStructReturn;
2181 return StackStructReturn;
2184 /// Make a copy of an aggregate at address specified by "Src" to address
2185 /// "Dst" with size and alignment information specified by the specific
2186 /// parameter attribute. The copy will be passed as a byval function parameter.
2188 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2189 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2191 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2193 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2194 /*isVolatile*/false, /*AlwaysInline=*/true,
2195 /*isTailCall*/false,
2196 MachinePointerInfo(), MachinePointerInfo());
2199 /// Return true if the calling convention is one that
2200 /// supports tail call optimization.
2201 static bool IsTailCallConvention(CallingConv::ID CC) {
2202 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2203 CC == CallingConv::HiPE);
2206 /// \brief Return true if the calling convention is a C calling convention.
2207 static bool IsCCallConvention(CallingConv::ID CC) {
2208 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2209 CC == CallingConv::X86_64_SysV);
2212 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2213 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2217 CallingConv::ID CalleeCC = CS.getCallingConv();
2218 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2224 /// Return true if the function is being made into
2225 /// a tailcall target by changing its ABI.
2226 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2227 bool GuaranteedTailCallOpt) {
2228 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2232 X86TargetLowering::LowerMemArgument(SDValue Chain,
2233 CallingConv::ID CallConv,
2234 const SmallVectorImpl<ISD::InputArg> &Ins,
2235 SDLoc dl, SelectionDAG &DAG,
2236 const CCValAssign &VA,
2237 MachineFrameInfo *MFI,
2239 // Create the nodes corresponding to a load from this parameter slot.
2240 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2241 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2242 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2243 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2246 // If value is passed by pointer we have address passed instead of the value
2248 if (VA.getLocInfo() == CCValAssign::Indirect)
2249 ValVT = VA.getLocVT();
2251 ValVT = VA.getValVT();
2253 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2254 // changed with more analysis.
2255 // In case of tail call optimization mark all arguments mutable. Since they
2256 // could be overwritten by lowering of arguments in case of a tail call.
2257 if (Flags.isByVal()) {
2258 unsigned Bytes = Flags.getByValSize();
2259 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2260 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2261 return DAG.getFrameIndex(FI, getPointerTy());
2263 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2264 VA.getLocMemOffset(), isImmutable);
2265 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2266 return DAG.getLoad(ValVT, dl, Chain, FIN,
2267 MachinePointerInfo::getFixedStack(FI),
2268 false, false, false, 0);
2272 // FIXME: Get this from tablegen.
2273 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2274 const X86Subtarget *Subtarget) {
2275 assert(Subtarget->is64Bit());
2277 if (Subtarget->isCallingConvWin64(CallConv)) {
2278 static const MCPhysReg GPR64ArgRegsWin64[] = {
2279 X86::RCX, X86::RDX, X86::R8, X86::R9
2281 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2284 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2285 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2287 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2290 // FIXME: Get this from tablegen.
2291 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2292 CallingConv::ID CallConv,
2293 const X86Subtarget *Subtarget) {
2294 assert(Subtarget->is64Bit());
2295 if (Subtarget->isCallingConvWin64(CallConv)) {
2296 // The XMM registers which might contain var arg parameters are shadowed
2297 // in their paired GPR. So we only need to save the GPR to their home
2299 // TODO: __vectorcall will change this.
2303 const Function *Fn = MF.getFunction();
2304 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2305 bool isSoftFloat = Subtarget->useSoftFloat();
2306 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2307 "SSE register cannot be used when SSE is disabled!");
2308 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2309 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2313 static const MCPhysReg XMMArgRegs64Bit[] = {
2314 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2315 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2317 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2321 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2322 CallingConv::ID CallConv,
2324 const SmallVectorImpl<ISD::InputArg> &Ins,
2327 SmallVectorImpl<SDValue> &InVals)
2329 MachineFunction &MF = DAG.getMachineFunction();
2330 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2331 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2333 const Function* Fn = MF.getFunction();
2334 if (Fn->hasExternalLinkage() &&
2335 Subtarget->isTargetCygMing() &&
2336 Fn->getName() == "main")
2337 FuncInfo->setForceFramePointer(true);
2339 MachineFrameInfo *MFI = MF.getFrameInfo();
2340 bool Is64Bit = Subtarget->is64Bit();
2341 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2343 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2344 "Var args not supported with calling convention fastcc, ghc or hipe");
2346 // Assign locations to all of the incoming arguments.
2347 SmallVector<CCValAssign, 16> ArgLocs;
2348 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2350 // Allocate shadow area for Win64
2352 CCInfo.AllocateStack(32, 8);
2354 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2356 unsigned LastVal = ~0U;
2358 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2359 CCValAssign &VA = ArgLocs[i];
2360 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2362 assert(VA.getValNo() != LastVal &&
2363 "Don't support value assigned to multiple locs yet");
2365 LastVal = VA.getValNo();
2367 if (VA.isRegLoc()) {
2368 EVT RegVT = VA.getLocVT();
2369 const TargetRegisterClass *RC;
2370 if (RegVT == MVT::i32)
2371 RC = &X86::GR32RegClass;
2372 else if (Is64Bit && RegVT == MVT::i64)
2373 RC = &X86::GR64RegClass;
2374 else if (RegVT == MVT::f32)
2375 RC = &X86::FR32RegClass;
2376 else if (RegVT == MVT::f64)
2377 RC = &X86::FR64RegClass;
2378 else if (RegVT.is512BitVector())
2379 RC = &X86::VR512RegClass;
2380 else if (RegVT.is256BitVector())
2381 RC = &X86::VR256RegClass;
2382 else if (RegVT.is128BitVector())
2383 RC = &X86::VR128RegClass;
2384 else if (RegVT == MVT::x86mmx)
2385 RC = &X86::VR64RegClass;
2386 else if (RegVT == MVT::i1)
2387 RC = &X86::VK1RegClass;
2388 else if (RegVT == MVT::v8i1)
2389 RC = &X86::VK8RegClass;
2390 else if (RegVT == MVT::v16i1)
2391 RC = &X86::VK16RegClass;
2392 else if (RegVT == MVT::v32i1)
2393 RC = &X86::VK32RegClass;
2394 else if (RegVT == MVT::v64i1)
2395 RC = &X86::VK64RegClass;
2397 llvm_unreachable("Unknown argument type!");
2399 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2400 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2402 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2403 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2405 if (VA.getLocInfo() == CCValAssign::SExt)
2406 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2407 DAG.getValueType(VA.getValVT()));
2408 else if (VA.getLocInfo() == CCValAssign::ZExt)
2409 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2410 DAG.getValueType(VA.getValVT()));
2411 else if (VA.getLocInfo() == CCValAssign::BCvt)
2412 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2414 if (VA.isExtInLoc()) {
2415 // Handle MMX values passed in XMM regs.
2416 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2417 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2419 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2422 assert(VA.isMemLoc());
2423 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2426 // If value is passed via pointer - do a load.
2427 if (VA.getLocInfo() == CCValAssign::Indirect)
2428 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2429 MachinePointerInfo(), false, false, false, 0);
2431 InVals.push_back(ArgValue);
2434 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2435 // All x86 ABIs require that for returning structs by value we copy the
2436 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2437 // the argument into a virtual register so that we can access it from the
2439 if (Ins[i].Flags.isSRet()) {
2440 unsigned Reg = FuncInfo->getSRetReturnReg();
2442 MVT PtrTy = getPointerTy();
2443 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2444 FuncInfo->setSRetReturnReg(Reg);
2446 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2447 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2452 unsigned StackSize = CCInfo.getNextStackOffset();
2453 // Align stack specially for tail calls.
2454 if (FuncIsMadeTailCallSafe(CallConv,
2455 MF.getTarget().Options.GuaranteedTailCallOpt))
2456 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2458 // If the function takes variable number of arguments, make a frame index for
2459 // the start of the first vararg value... for expansion of llvm.va_start. We
2460 // can skip this if there are no va_start calls.
2461 if (MFI->hasVAStart() &&
2462 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2463 CallConv != CallingConv::X86_ThisCall))) {
2464 FuncInfo->setVarArgsFrameIndex(
2465 MFI->CreateFixedObject(1, StackSize, true));
2468 MachineModuleInfo &MMI = MF.getMMI();
2469 const Function *WinEHParent = nullptr;
2470 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2471 WinEHParent = MMI.getWinEHParent(Fn);
2472 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2473 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2475 // Figure out if XMM registers are in use.
2476 assert(!(Subtarget->useSoftFloat() &&
2477 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2478 "SSE register cannot be used when SSE is disabled!");
2480 // 64-bit calling conventions support varargs and register parameters, so we
2481 // have to do extra work to spill them in the prologue.
2482 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2483 // Find the first unallocated argument registers.
2484 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2485 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2486 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2487 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2488 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2489 "SSE register cannot be used when SSE is disabled!");
2491 // Gather all the live in physical registers.
2492 SmallVector<SDValue, 6> LiveGPRs;
2493 SmallVector<SDValue, 8> LiveXMMRegs;
2495 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2496 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2498 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2500 if (!ArgXMMs.empty()) {
2501 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2502 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2503 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2504 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2505 LiveXMMRegs.push_back(
2506 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2511 // Get to the caller-allocated home save location. Add 8 to account
2512 // for the return address.
2513 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2514 FuncInfo->setRegSaveFrameIndex(
2515 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2516 // Fixup to set vararg frame on shadow area (4 x i64).
2518 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2520 // For X86-64, if there are vararg parameters that are passed via
2521 // registers, then we must store them to their spots on the stack so
2522 // they may be loaded by deferencing the result of va_next.
2523 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2524 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2525 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2526 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2529 // Store the integer parameter registers.
2530 SmallVector<SDValue, 8> MemOps;
2531 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2533 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2534 for (SDValue Val : LiveGPRs) {
2535 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2536 DAG.getIntPtrConstant(Offset, dl));
2538 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2539 MachinePointerInfo::getFixedStack(
2540 FuncInfo->getRegSaveFrameIndex(), Offset),
2542 MemOps.push_back(Store);
2546 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2547 // Now store the XMM (fp + vector) parameter registers.
2548 SmallVector<SDValue, 12> SaveXMMOps;
2549 SaveXMMOps.push_back(Chain);
2550 SaveXMMOps.push_back(ALVal);
2551 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2552 FuncInfo->getRegSaveFrameIndex(), dl));
2553 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2554 FuncInfo->getVarArgsFPOffset(), dl));
2555 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2557 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2558 MVT::Other, SaveXMMOps));
2561 if (!MemOps.empty())
2562 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2563 } else if (IsWinEHOutlined) {
2564 // Get to the caller-allocated home save location. Add 8 to account
2565 // for the return address.
2566 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2567 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2568 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2570 MMI.getWinEHFuncInfo(Fn)
2571 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2572 FuncInfo->getRegSaveFrameIndex();
2574 // Store the second integer parameter (rdx) into rsp+16 relative to the
2575 // stack pointer at the entry of the function.
2577 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2578 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2579 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2580 Chain = DAG.getStore(
2581 Val.getValue(1), dl, Val, RSFIN,
2582 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2583 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2586 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2587 // Find the largest legal vector type.
2588 MVT VecVT = MVT::Other;
2589 // FIXME: Only some x86_32 calling conventions support AVX512.
2590 if (Subtarget->hasAVX512() &&
2591 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2592 CallConv == CallingConv::Intel_OCL_BI)))
2593 VecVT = MVT::v16f32;
2594 else if (Subtarget->hasAVX())
2596 else if (Subtarget->hasSSE2())
2599 // We forward some GPRs and some vector types.
2600 SmallVector<MVT, 2> RegParmTypes;
2601 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2602 RegParmTypes.push_back(IntVT);
2603 if (VecVT != MVT::Other)
2604 RegParmTypes.push_back(VecVT);
2606 // Compute the set of forwarded registers. The rest are scratch.
2607 SmallVectorImpl<ForwardedRegister> &Forwards =
2608 FuncInfo->getForwardedMustTailRegParms();
2609 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2611 // Conservatively forward AL on x86_64, since it might be used for varargs.
2612 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2613 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2614 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2617 // Copy all forwards from physical to virtual registers.
2618 for (ForwardedRegister &F : Forwards) {
2619 // FIXME: Can we use a less constrained schedule?
2620 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2621 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2622 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2626 // Some CCs need callee pop.
2627 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2628 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2629 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2631 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2632 // If this is an sret function, the return should pop the hidden pointer.
2633 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2634 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2635 argsAreStructReturn(Ins) == StackStructReturn)
2636 FuncInfo->setBytesToPopOnReturn(4);
2640 // RegSaveFrameIndex is X86-64 only.
2641 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2642 if (CallConv == CallingConv::X86_FastCall ||
2643 CallConv == CallingConv::X86_ThisCall)
2644 // fastcc functions can't have varargs.
2645 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2648 FuncInfo->setArgumentStackSize(StackSize);
2650 if (IsWinEHParent) {
2651 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2652 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2653 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2654 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2655 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2656 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2657 /*isVolatile=*/true,
2658 /*isNonTemporal=*/false, /*Alignment=*/0);
2665 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2666 SDValue StackPtr, SDValue Arg,
2667 SDLoc dl, SelectionDAG &DAG,
2668 const CCValAssign &VA,
2669 ISD::ArgFlagsTy Flags) const {
2670 unsigned LocMemOffset = VA.getLocMemOffset();
2671 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2672 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2673 if (Flags.isByVal())
2674 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2676 return DAG.getStore(Chain, dl, Arg, PtrOff,
2677 MachinePointerInfo::getStack(LocMemOffset),
2681 /// Emit a load of return address if tail call
2682 /// optimization is performed and it is required.
2684 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2685 SDValue &OutRetAddr, SDValue Chain,
2686 bool IsTailCall, bool Is64Bit,
2687 int FPDiff, SDLoc dl) const {
2688 // Adjust the Return address stack slot.
2689 EVT VT = getPointerTy();
2690 OutRetAddr = getReturnAddressFrameIndex(DAG);
2692 // Load the "old" Return address.
2693 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2694 false, false, false, 0);
2695 return SDValue(OutRetAddr.getNode(), 1);
2698 /// Emit a store of the return address if tail call
2699 /// optimization is performed and it is required (FPDiff!=0).
2700 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2701 SDValue Chain, SDValue RetAddrFrIdx,
2702 EVT PtrVT, unsigned SlotSize,
2703 int FPDiff, SDLoc dl) {
2704 // Store the return address to the appropriate stack slot.
2705 if (!FPDiff) return Chain;
2706 // Calculate the new stack slot for the return address.
2707 int NewReturnAddrFI =
2708 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2710 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2711 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2712 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2718 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2719 SmallVectorImpl<SDValue> &InVals) const {
2720 SelectionDAG &DAG = CLI.DAG;
2722 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2723 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2724 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2725 SDValue Chain = CLI.Chain;
2726 SDValue Callee = CLI.Callee;
2727 CallingConv::ID CallConv = CLI.CallConv;
2728 bool &isTailCall = CLI.IsTailCall;
2729 bool isVarArg = CLI.IsVarArg;
2731 MachineFunction &MF = DAG.getMachineFunction();
2732 bool Is64Bit = Subtarget->is64Bit();
2733 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2734 StructReturnType SR = callIsStructReturn(Outs);
2735 bool IsSibcall = false;
2736 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2738 if (MF.getTarget().Options.DisableTailCalls)
2741 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2743 // Force this to be a tail call. The verifier rules are enough to ensure
2744 // that we can lower this successfully without moving the return address
2747 } else if (isTailCall) {
2748 // Check if it's really possible to do a tail call.
2749 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2750 isVarArg, SR != NotStructReturn,
2751 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2752 Outs, OutVals, Ins, DAG);
2754 // Sibcalls are automatically detected tailcalls which do not require
2756 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2763 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2764 "Var args not supported with calling convention fastcc, ghc or hipe");
2766 // Analyze operands of the call, assigning locations to each operand.
2767 SmallVector<CCValAssign, 16> ArgLocs;
2768 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2770 // Allocate shadow area for Win64
2772 CCInfo.AllocateStack(32, 8);
2774 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2776 // Get a count of how many bytes are to be pushed on the stack.
2777 unsigned NumBytes = CCInfo.getNextStackOffset();
2779 // This is a sibcall. The memory operands are available in caller's
2780 // own caller's stack.
2782 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2783 IsTailCallConvention(CallConv))
2784 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2787 if (isTailCall && !IsSibcall && !IsMustTail) {
2788 // Lower arguments at fp - stackoffset + fpdiff.
2789 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2791 FPDiff = NumBytesCallerPushed - NumBytes;
2793 // Set the delta of movement of the returnaddr stackslot.
2794 // But only set if delta is greater than previous delta.
2795 if (FPDiff < X86Info->getTCReturnAddrDelta())
2796 X86Info->setTCReturnAddrDelta(FPDiff);
2799 unsigned NumBytesToPush = NumBytes;
2800 unsigned NumBytesToPop = NumBytes;
2802 // If we have an inalloca argument, all stack space has already been allocated
2803 // for us and be right at the top of the stack. We don't support multiple
2804 // arguments passed in memory when using inalloca.
2805 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2807 if (!ArgLocs.back().isMemLoc())
2808 report_fatal_error("cannot use inalloca attribute on a register "
2810 if (ArgLocs.back().getLocMemOffset() != 0)
2811 report_fatal_error("any parameter with the inalloca attribute must be "
2812 "the only memory argument");
2816 Chain = DAG.getCALLSEQ_START(
2817 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2819 SDValue RetAddrFrIdx;
2820 // Load return address for tail calls.
2821 if (isTailCall && FPDiff)
2822 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2823 Is64Bit, FPDiff, dl);
2825 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2826 SmallVector<SDValue, 8> MemOpChains;
2829 // Walk the register/memloc assignments, inserting copies/loads. In the case
2830 // of tail call optimization arguments are handle later.
2831 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2833 // Skip inalloca arguments, they have already been written.
2834 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2835 if (Flags.isInAlloca())
2838 CCValAssign &VA = ArgLocs[i];
2839 EVT RegVT = VA.getLocVT();
2840 SDValue Arg = OutVals[i];
2841 bool isByVal = Flags.isByVal();
2843 // Promote the value if needed.
2844 switch (VA.getLocInfo()) {
2845 default: llvm_unreachable("Unknown loc info!");
2846 case CCValAssign::Full: break;
2847 case CCValAssign::SExt:
2848 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2850 case CCValAssign::ZExt:
2851 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2853 case CCValAssign::AExt:
2854 if (Arg.getValueType().getScalarType() == MVT::i1)
2855 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2856 else if (RegVT.is128BitVector()) {
2857 // Special case: passing MMX values in XMM registers.
2858 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2859 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2860 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2862 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::BCvt:
2865 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2867 case CCValAssign::Indirect: {
2868 // Store the argument.
2869 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2870 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2871 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2872 MachinePointerInfo::getFixedStack(FI),
2879 if (VA.isRegLoc()) {
2880 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2881 if (isVarArg && IsWin64) {
2882 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2883 // shadow reg if callee is a varargs function.
2884 unsigned ShadowReg = 0;
2885 switch (VA.getLocReg()) {
2886 case X86::XMM0: ShadowReg = X86::RCX; break;
2887 case X86::XMM1: ShadowReg = X86::RDX; break;
2888 case X86::XMM2: ShadowReg = X86::R8; break;
2889 case X86::XMM3: ShadowReg = X86::R9; break;
2892 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2894 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2895 assert(VA.isMemLoc());
2896 if (!StackPtr.getNode())
2897 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2899 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2900 dl, DAG, VA, Flags));
2904 if (!MemOpChains.empty())
2905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2907 if (Subtarget->isPICStyleGOT()) {
2908 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2911 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2912 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2914 // If we are tail calling and generating PIC/GOT style code load the
2915 // address of the callee into ECX. The value in ecx is used as target of
2916 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2917 // for tail calls on PIC/GOT architectures. Normally we would just put the
2918 // address of GOT into ebx and then call target@PLT. But for tail calls
2919 // ebx would be restored (since ebx is callee saved) before jumping to the
2922 // Note: The actual moving to ECX is done further down.
2923 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2924 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2925 !G->getGlobal()->hasProtectedVisibility())
2926 Callee = LowerGlobalAddress(Callee, DAG);
2927 else if (isa<ExternalSymbolSDNode>(Callee))
2928 Callee = LowerExternalSymbol(Callee, DAG);
2932 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2933 // From AMD64 ABI document:
2934 // For calls that may call functions that use varargs or stdargs
2935 // (prototype-less calls or calls to functions containing ellipsis (...) in
2936 // the declaration) %al is used as hidden argument to specify the number
2937 // of SSE registers used. The contents of %al do not need to match exactly
2938 // the number of registers, but must be an ubound on the number of SSE
2939 // registers used and is in the range 0 - 8 inclusive.
2941 // Count the number of XMM registers allocated.
2942 static const MCPhysReg XMMArgRegs[] = {
2943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2946 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2947 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2948 && "SSE registers cannot be used when SSE is disabled");
2950 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2951 DAG.getConstant(NumXMMRegs, dl,
2955 if (isVarArg && IsMustTail) {
2956 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2957 for (const auto &F : Forwards) {
2958 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2959 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2963 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2964 // don't need this because the eligibility check rejects calls that require
2965 // shuffling arguments passed in memory.
2966 if (!IsSibcall && isTailCall) {
2967 // Force all the incoming stack arguments to be loaded from the stack
2968 // before any new outgoing arguments are stored to the stack, because the
2969 // outgoing stack slots may alias the incoming argument stack slots, and
2970 // the alias isn't otherwise explicit. This is slightly more conservative
2971 // than necessary, because it means that each store effectively depends
2972 // on every argument instead of just those arguments it would clobber.
2973 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2975 SmallVector<SDValue, 8> MemOpChains2;
2978 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2979 CCValAssign &VA = ArgLocs[i];
2982 assert(VA.isMemLoc());
2983 SDValue Arg = OutVals[i];
2984 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2985 // Skip inalloca arguments. They don't require any work.
2986 if (Flags.isInAlloca())
2988 // Create frame index.
2989 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2990 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2991 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2992 FIN = DAG.getFrameIndex(FI, getPointerTy());
2994 if (Flags.isByVal()) {
2995 // Copy relative to framepointer.
2996 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
2997 if (!StackPtr.getNode())
2998 StackPtr = DAG.getCopyFromReg(Chain, dl,
2999 RegInfo->getStackRegister(),
3001 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3003 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3007 // Store relative to framepointer.
3008 MemOpChains2.push_back(
3009 DAG.getStore(ArgChain, dl, Arg, FIN,
3010 MachinePointerInfo::getFixedStack(FI),
3015 if (!MemOpChains2.empty())
3016 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3018 // Store the return address to the appropriate stack slot.
3019 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3020 getPointerTy(), RegInfo->getSlotSize(),
3024 // Build a sequence of copy-to-reg nodes chained together with token chain
3025 // and flag operands which copy the outgoing args into registers.
3027 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3028 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3029 RegsToPass[i].second, InFlag);
3030 InFlag = Chain.getValue(1);
3033 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3034 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3035 // In the 64-bit large code model, we have to make all calls
3036 // through a register, since the call instruction's 32-bit
3037 // pc-relative offset may not be large enough to hold the whole
3039 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3040 // If the callee is a GlobalAddress node (quite common, every direct call
3041 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3043 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3045 // We should use extra load for direct calls to dllimported functions in
3047 const GlobalValue *GV = G->getGlobal();
3048 if (!GV->hasDLLImportStorageClass()) {
3049 unsigned char OpFlags = 0;
3050 bool ExtraLoad = false;
3051 unsigned WrapperKind = ISD::DELETED_NODE;
3053 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3054 // external symbols most go through the PLT in PIC mode. If the symbol
3055 // has hidden or protected visibility, or if it is static or local, then
3056 // we don't need to use the PLT - we can directly call it.
3057 if (Subtarget->isTargetELF() &&
3058 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3059 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3060 OpFlags = X86II::MO_PLT;
3061 } else if (Subtarget->isPICStyleStubAny() &&
3062 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3063 (!Subtarget->getTargetTriple().isMacOSX() ||
3064 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3065 // PC-relative references to external symbols should go through $stub,
3066 // unless we're building with the leopard linker or later, which
3067 // automatically synthesizes these stubs.
3068 OpFlags = X86II::MO_DARWIN_STUB;
3069 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3070 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3071 // If the function is marked as non-lazy, generate an indirect call
3072 // which loads from the GOT directly. This avoids runtime overhead
3073 // at the cost of eager binding (and one extra byte of encoding).
3074 OpFlags = X86II::MO_GOTPCREL;
3075 WrapperKind = X86ISD::WrapperRIP;
3079 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3080 G->getOffset(), OpFlags);
3082 // Add a wrapper if needed.
3083 if (WrapperKind != ISD::DELETED_NODE)
3084 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3085 // Add extra indirection if needed.
3087 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3088 MachinePointerInfo::getGOT(),
3089 false, false, false, 0);
3091 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3092 unsigned char OpFlags = 0;
3094 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3095 // external symbols should go through the PLT.
3096 if (Subtarget->isTargetELF() &&
3097 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3098 OpFlags = X86II::MO_PLT;
3099 } else if (Subtarget->isPICStyleStubAny() &&
3100 (!Subtarget->getTargetTriple().isMacOSX() ||
3101 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3102 // PC-relative references to external symbols should go through $stub,
3103 // unless we're building with the leopard linker or later, which
3104 // automatically synthesizes these stubs.
3105 OpFlags = X86II::MO_DARWIN_STUB;
3108 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3110 } else if (Subtarget->isTarget64BitILP32() &&
3111 Callee->getValueType(0) == MVT::i32) {
3112 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3113 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3116 // Returns a chain & a flag for retval copy to use.
3117 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3118 SmallVector<SDValue, 8> Ops;
3120 if (!IsSibcall && isTailCall) {
3121 Chain = DAG.getCALLSEQ_END(Chain,
3122 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3123 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3124 InFlag = Chain.getValue(1);
3127 Ops.push_back(Chain);
3128 Ops.push_back(Callee);
3131 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3133 // Add argument registers to the end of the list so that they are known live
3135 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3136 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3137 RegsToPass[i].second.getValueType()));
3139 // Add a register mask operand representing the call-preserved registers.
3140 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3141 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3142 assert(Mask && "Missing call preserved mask for calling convention");
3143 Ops.push_back(DAG.getRegisterMask(Mask));
3145 if (InFlag.getNode())
3146 Ops.push_back(InFlag);
3150 //// If this is the first return lowered for this function, add the regs
3151 //// to the liveout set for the function.
3152 // This isn't right, although it's probably harmless on x86; liveouts
3153 // should be computed from returns not tail calls. Consider a void
3154 // function making a tail call to a function returning int.
3155 MF.getFrameInfo()->setHasTailCall();
3156 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3159 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3160 InFlag = Chain.getValue(1);
3162 // Create the CALLSEQ_END node.
3163 unsigned NumBytesForCalleeToPop;
3164 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3165 DAG.getTarget().Options.GuaranteedTailCallOpt))
3166 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3167 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3168 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3169 SR == StackStructReturn)
3170 // If this is a call to a struct-return function, the callee
3171 // pops the hidden struct pointer, so we have to push it back.
3172 // This is common for Darwin/X86, Linux & Mingw32 targets.
3173 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3174 NumBytesForCalleeToPop = 4;
3176 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3178 // Returns a flag for retval copy to use.
3180 Chain = DAG.getCALLSEQ_END(Chain,
3181 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3182 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3185 InFlag = Chain.getValue(1);
3188 // Handle result values, copying them out of physregs into vregs that we
3190 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3191 Ins, dl, DAG, InVals);
3194 //===----------------------------------------------------------------------===//
3195 // Fast Calling Convention (tail call) implementation
3196 //===----------------------------------------------------------------------===//
3198 // Like std call, callee cleans arguments, convention except that ECX is
3199 // reserved for storing the tail called function address. Only 2 registers are
3200 // free for argument passing (inreg). Tail call optimization is performed
3202 // * tailcallopt is enabled
3203 // * caller/callee are fastcc
3204 // On X86_64 architecture with GOT-style position independent code only local
3205 // (within module) calls are supported at the moment.
3206 // To keep the stack aligned according to platform abi the function
3207 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3208 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3209 // If a tail called function callee has more arguments than the caller the
3210 // caller needs to make sure that there is room to move the RETADDR to. This is
3211 // achieved by reserving an area the size of the argument delta right after the
3212 // original RETADDR, but before the saved framepointer or the spilled registers
3213 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3225 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3226 /// for a 16 byte align requirement.
3228 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3229 SelectionDAG& DAG) const {
3230 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3231 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3232 unsigned StackAlignment = TFI.getStackAlignment();
3233 uint64_t AlignMask = StackAlignment - 1;
3234 int64_t Offset = StackSize;
3235 unsigned SlotSize = RegInfo->getSlotSize();
3236 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3237 // Number smaller than 12 so just add the difference.
3238 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3240 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3241 Offset = ((~AlignMask) & Offset) + StackAlignment +
3242 (StackAlignment-SlotSize);
3247 /// MatchingStackOffset - Return true if the given stack call argument is
3248 /// already available in the same position (relatively) of the caller's
3249 /// incoming argument stack.
3251 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3252 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3253 const X86InstrInfo *TII) {
3254 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3256 if (Arg.getOpcode() == ISD::CopyFromReg) {
3257 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3258 if (!TargetRegisterInfo::isVirtualRegister(VR))
3260 MachineInstr *Def = MRI->getVRegDef(VR);
3263 if (!Flags.isByVal()) {
3264 if (!TII->isLoadFromStackSlot(Def, FI))
3267 unsigned Opcode = Def->getOpcode();
3268 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3269 Opcode == X86::LEA64_32r) &&
3270 Def->getOperand(1).isFI()) {
3271 FI = Def->getOperand(1).getIndex();
3272 Bytes = Flags.getByValSize();
3276 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3277 if (Flags.isByVal())
3278 // ByVal argument is passed in as a pointer but it's now being
3279 // dereferenced. e.g.
3280 // define @foo(%struct.X* %A) {
3281 // tail call @bar(%struct.X* byval %A)
3284 SDValue Ptr = Ld->getBasePtr();
3285 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3288 FI = FINode->getIndex();
3289 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3290 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3291 FI = FINode->getIndex();
3292 Bytes = Flags.getByValSize();
3296 assert(FI != INT_MAX);
3297 if (!MFI->isFixedObjectIndex(FI))
3299 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3302 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3303 /// for tail call optimization. Targets which want to do tail call
3304 /// optimization should implement this function.
3306 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3307 CallingConv::ID CalleeCC,
3309 bool isCalleeStructRet,
3310 bool isCallerStructRet,
3312 const SmallVectorImpl<ISD::OutputArg> &Outs,
3313 const SmallVectorImpl<SDValue> &OutVals,
3314 const SmallVectorImpl<ISD::InputArg> &Ins,
3315 SelectionDAG &DAG) const {
3316 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3319 // If -tailcallopt is specified, make fastcc functions tail-callable.
3320 const MachineFunction &MF = DAG.getMachineFunction();
3321 const Function *CallerF = MF.getFunction();
3323 // If the function return type is x86_fp80 and the callee return type is not,
3324 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3325 // perform a tailcall optimization here.
3326 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3329 CallingConv::ID CallerCC = CallerF->getCallingConv();
3330 bool CCMatch = CallerCC == CalleeCC;
3331 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3332 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3334 // Win64 functions have extra shadow space for argument homing. Don't do the
3335 // sibcall if the caller and callee have mismatched expectations for this
3337 if (IsCalleeWin64 != IsCallerWin64)
3340 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3341 if (IsTailCallConvention(CalleeCC) && CCMatch)
3346 // Look for obvious safe cases to perform tail call optimization that do not
3347 // require ABI changes. This is what gcc calls sibcall.
3349 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3350 // emit a special epilogue.
3351 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3352 if (RegInfo->needsStackRealignment(MF))
3355 // Also avoid sibcall optimization if either caller or callee uses struct
3356 // return semantics.
3357 if (isCalleeStructRet || isCallerStructRet)
3360 // An stdcall/thiscall caller is expected to clean up its arguments; the
3361 // callee isn't going to do that.
3362 // FIXME: this is more restrictive than needed. We could produce a tailcall
3363 // when the stack adjustment matches. For example, with a thiscall that takes
3364 // only one argument.
3365 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3366 CallerCC == CallingConv::X86_ThisCall))
3369 // Do not sibcall optimize vararg calls unless all arguments are passed via
3371 if (isVarArg && !Outs.empty()) {
3373 // Optimizing for varargs on Win64 is unlikely to be safe without
3374 // additional testing.
3375 if (IsCalleeWin64 || IsCallerWin64)
3378 SmallVector<CCValAssign, 16> ArgLocs;
3379 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3382 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3383 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3384 if (!ArgLocs[i].isRegLoc())
3388 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3389 // stack. Therefore, if it's not used by the call it is not safe to optimize
3390 // this into a sibcall.
3391 bool Unused = false;
3392 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3399 SmallVector<CCValAssign, 16> RVLocs;
3400 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3402 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3403 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3404 CCValAssign &VA = RVLocs[i];
3405 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3410 // If the calling conventions do not match, then we'd better make sure the
3411 // results are returned in the same way as what the caller expects.
3413 SmallVector<CCValAssign, 16> RVLocs1;
3414 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3416 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3418 SmallVector<CCValAssign, 16> RVLocs2;
3419 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3421 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3423 if (RVLocs1.size() != RVLocs2.size())
3425 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3426 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3428 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3430 if (RVLocs1[i].isRegLoc()) {
3431 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3434 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3440 // If the callee takes no arguments then go on to check the results of the
3442 if (!Outs.empty()) {
3443 // Check if stack adjustment is needed. For now, do not do this if any
3444 // argument is passed on the stack.
3445 SmallVector<CCValAssign, 16> ArgLocs;
3446 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3449 // Allocate shadow area for Win64
3451 CCInfo.AllocateStack(32, 8);
3453 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3454 if (CCInfo.getNextStackOffset()) {
3455 MachineFunction &MF = DAG.getMachineFunction();
3456 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3459 // Check if the arguments are already laid out in the right way as
3460 // the caller's fixed stack objects.
3461 MachineFrameInfo *MFI = MF.getFrameInfo();
3462 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3463 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3464 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3465 CCValAssign &VA = ArgLocs[i];
3466 SDValue Arg = OutVals[i];
3467 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3468 if (VA.getLocInfo() == CCValAssign::Indirect)
3470 if (!VA.isRegLoc()) {
3471 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3478 // If the tailcall address may be in a register, then make sure it's
3479 // possible to register allocate for it. In 32-bit, the call address can
3480 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3481 // callee-saved registers are restored. These happen to be the same
3482 // registers used to pass 'inreg' arguments so watch out for those.
3483 if (!Subtarget->is64Bit() &&
3484 ((!isa<GlobalAddressSDNode>(Callee) &&
3485 !isa<ExternalSymbolSDNode>(Callee)) ||
3486 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3487 unsigned NumInRegs = 0;
3488 // In PIC we need an extra register to formulate the address computation
3490 unsigned MaxInRegs =
3491 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3494 CCValAssign &VA = ArgLocs[i];
3497 unsigned Reg = VA.getLocReg();
3500 case X86::EAX: case X86::EDX: case X86::ECX:
3501 if (++NumInRegs == MaxInRegs)
3513 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3514 const TargetLibraryInfo *libInfo) const {
3515 return X86::createFastISel(funcInfo, libInfo);
3518 //===----------------------------------------------------------------------===//
3519 // Other Lowering Hooks
3520 //===----------------------------------------------------------------------===//
3522 static bool MayFoldLoad(SDValue Op) {
3523 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3526 static bool MayFoldIntoStore(SDValue Op) {
3527 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3530 static bool isTargetShuffle(unsigned Opcode) {
3532 default: return false;
3533 case X86ISD::BLENDI:
3534 case X86ISD::PSHUFB:
3535 case X86ISD::PSHUFD:
3536 case X86ISD::PSHUFHW:
3537 case X86ISD::PSHUFLW:
3539 case X86ISD::PALIGNR:
3540 case X86ISD::MOVLHPS:
3541 case X86ISD::MOVLHPD:
3542 case X86ISD::MOVHLPS:
3543 case X86ISD::MOVLPS:
3544 case X86ISD::MOVLPD:
3545 case X86ISD::MOVSHDUP:
3546 case X86ISD::MOVSLDUP:
3547 case X86ISD::MOVDDUP:
3550 case X86ISD::UNPCKL:
3551 case X86ISD::UNPCKH:
3552 case X86ISD::VPERMILPI:
3553 case X86ISD::VPERM2X128:
3554 case X86ISD::VPERMI:
3559 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3560 SDValue V1, unsigned TargetMask,
3561 SelectionDAG &DAG) {
3563 default: llvm_unreachable("Unknown x86 shuffle node");
3564 case X86ISD::PSHUFD:
3565 case X86ISD::PSHUFHW:
3566 case X86ISD::PSHUFLW:
3567 case X86ISD::VPERMILPI:
3568 case X86ISD::VPERMI:
3569 return DAG.getNode(Opc, dl, VT, V1,
3570 DAG.getConstant(TargetMask, dl, MVT::i8));
3574 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3575 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3577 default: llvm_unreachable("Unknown x86 shuffle node");
3578 case X86ISD::MOVLHPS:
3579 case X86ISD::MOVLHPD:
3580 case X86ISD::MOVHLPS:
3581 case X86ISD::MOVLPS:
3582 case X86ISD::MOVLPD:
3585 case X86ISD::UNPCKL:
3586 case X86ISD::UNPCKH:
3587 return DAG.getNode(Opc, dl, VT, V1, V2);
3591 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3592 MachineFunction &MF = DAG.getMachineFunction();
3593 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3594 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3595 int ReturnAddrIndex = FuncInfo->getRAIndex();
3597 if (ReturnAddrIndex == 0) {
3598 // Set up a frame object for the return address.
3599 unsigned SlotSize = RegInfo->getSlotSize();
3600 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3603 FuncInfo->setRAIndex(ReturnAddrIndex);
3606 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3609 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3610 bool hasSymbolicDisplacement) {
3611 // Offset should fit into 32 bit immediate field.
3612 if (!isInt<32>(Offset))
3615 // If we don't have a symbolic displacement - we don't have any extra
3617 if (!hasSymbolicDisplacement)
3620 // FIXME: Some tweaks might be needed for medium code model.
3621 if (M != CodeModel::Small && M != CodeModel::Kernel)
3624 // For small code model we assume that latest object is 16MB before end of 31
3625 // bits boundary. We may also accept pretty large negative constants knowing
3626 // that all objects are in the positive half of address space.
3627 if (M == CodeModel::Small && Offset < 16*1024*1024)
3630 // For kernel code model we know that all object resist in the negative half
3631 // of 32bits address space. We may not accept negative offsets, since they may
3632 // be just off and we may accept pretty large positive ones.
3633 if (M == CodeModel::Kernel && Offset >= 0)
3639 /// isCalleePop - Determines whether the callee is required to pop its
3640 /// own arguments. Callee pop is necessary to support tail calls.
3641 bool X86::isCalleePop(CallingConv::ID CallingConv,
3642 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3643 switch (CallingConv) {
3646 case CallingConv::X86_StdCall:
3647 case CallingConv::X86_FastCall:
3648 case CallingConv::X86_ThisCall:
3650 case CallingConv::Fast:
3651 case CallingConv::GHC:
3652 case CallingConv::HiPE:
3659 /// \brief Return true if the condition is an unsigned comparison operation.
3660 static bool isX86CCUnsigned(unsigned X86CC) {
3662 default: llvm_unreachable("Invalid integer condition!");
3663 case X86::COND_E: return true;
3664 case X86::COND_G: return false;
3665 case X86::COND_GE: return false;
3666 case X86::COND_L: return false;
3667 case X86::COND_LE: return false;
3668 case X86::COND_NE: return true;
3669 case X86::COND_B: return true;
3670 case X86::COND_A: return true;
3671 case X86::COND_BE: return true;
3672 case X86::COND_AE: return true;
3674 llvm_unreachable("covered switch fell through?!");
3677 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3678 /// specific condition code, returning the condition code and the LHS/RHS of the
3679 /// comparison to make.
3680 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3681 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3683 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3684 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3685 // X > -1 -> X == 0, jump !sign.
3686 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3687 return X86::COND_NS;
3689 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3690 // X < 0 -> X == 0, jump on sign.
3693 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3695 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3696 return X86::COND_LE;
3700 switch (SetCCOpcode) {
3701 default: llvm_unreachable("Invalid integer condition!");
3702 case ISD::SETEQ: return X86::COND_E;
3703 case ISD::SETGT: return X86::COND_G;
3704 case ISD::SETGE: return X86::COND_GE;
3705 case ISD::SETLT: return X86::COND_L;
3706 case ISD::SETLE: return X86::COND_LE;
3707 case ISD::SETNE: return X86::COND_NE;
3708 case ISD::SETULT: return X86::COND_B;
3709 case ISD::SETUGT: return X86::COND_A;
3710 case ISD::SETULE: return X86::COND_BE;
3711 case ISD::SETUGE: return X86::COND_AE;
3715 // First determine if it is required or is profitable to flip the operands.
3717 // If LHS is a foldable load, but RHS is not, flip the condition.
3718 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3719 !ISD::isNON_EXTLoad(RHS.getNode())) {
3720 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3721 std::swap(LHS, RHS);
3724 switch (SetCCOpcode) {
3730 std::swap(LHS, RHS);
3734 // On a floating point condition, the flags are set as follows:
3736 // 0 | 0 | 0 | X > Y
3737 // 0 | 0 | 1 | X < Y
3738 // 1 | 0 | 0 | X == Y
3739 // 1 | 1 | 1 | unordered
3740 switch (SetCCOpcode) {
3741 default: llvm_unreachable("Condcode should be pre-legalized away");
3743 case ISD::SETEQ: return X86::COND_E;
3744 case ISD::SETOLT: // flipped
3746 case ISD::SETGT: return X86::COND_A;
3747 case ISD::SETOLE: // flipped
3749 case ISD::SETGE: return X86::COND_AE;
3750 case ISD::SETUGT: // flipped
3752 case ISD::SETLT: return X86::COND_B;
3753 case ISD::SETUGE: // flipped
3755 case ISD::SETLE: return X86::COND_BE;
3757 case ISD::SETNE: return X86::COND_NE;
3758 case ISD::SETUO: return X86::COND_P;
3759 case ISD::SETO: return X86::COND_NP;
3761 case ISD::SETUNE: return X86::COND_INVALID;
3765 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3766 /// code. Current x86 isa includes the following FP cmov instructions:
3767 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3768 static bool hasFPCMov(unsigned X86CC) {
3784 /// isFPImmLegal - Returns true if the target can instruction select the
3785 /// specified FP immediate natively. If false, the legalizer will
3786 /// materialize the FP immediate as a load from a constant pool.
3787 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3788 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3789 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3795 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3796 ISD::LoadExtType ExtTy,
3798 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3799 // relocation target a movq or addq instruction: don't let the load shrink.
3800 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3801 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3802 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3803 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3807 /// \brief Returns true if it is beneficial to convert a load of a constant
3808 /// to just the constant itself.
3809 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3811 assert(Ty->isIntegerTy());
3813 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3814 if (BitSize == 0 || BitSize > 64)
3819 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3820 unsigned Index) const {
3821 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3824 return (Index == 0 || Index == ResVT.getVectorNumElements());
3827 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3828 // Speculate cttz only if we can directly use TZCNT.
3829 return Subtarget->hasBMI();
3832 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3833 // Speculate ctlz only if we can directly use LZCNT.
3834 return Subtarget->hasLZCNT();
3837 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3838 /// the specified range (L, H].
3839 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3840 return (Val < 0) || (Val >= Low && Val < Hi);
3843 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3844 /// specified value.
3845 static bool isUndefOrEqual(int Val, int CmpVal) {
3846 return (Val < 0 || Val == CmpVal);
3849 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3850 /// from position Pos and ending in Pos+Size, falls within the specified
3851 /// sequential range (Low, Low+Size]. or is undef.
3852 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3853 unsigned Pos, unsigned Size, int Low) {
3854 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3855 if (!isUndefOrEqual(Mask[i], Low))
3860 /// isVEXTRACTIndex - Return true if the specified
3861 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3862 /// suitable for instruction that extract 128 or 256 bit vectors
3863 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3864 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3865 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3868 // The index should be aligned on a vecWidth-bit boundary.
3870 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3872 MVT VT = N->getSimpleValueType(0);
3873 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3874 bool Result = (Index * ElSize) % vecWidth == 0;
3879 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3880 /// operand specifies a subvector insert that is suitable for input to
3881 /// insertion of 128 or 256-bit subvectors
3882 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3883 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3884 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3886 // The index should be aligned on a vecWidth-bit boundary.
3888 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3890 MVT VT = N->getSimpleValueType(0);
3891 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3892 bool Result = (Index * ElSize) % vecWidth == 0;
3897 bool X86::isVINSERT128Index(SDNode *N) {
3898 return isVINSERTIndex(N, 128);
3901 bool X86::isVINSERT256Index(SDNode *N) {
3902 return isVINSERTIndex(N, 256);
3905 bool X86::isVEXTRACT128Index(SDNode *N) {
3906 return isVEXTRACTIndex(N, 128);
3909 bool X86::isVEXTRACT256Index(SDNode *N) {
3910 return isVEXTRACTIndex(N, 256);
3913 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3914 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3915 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3916 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3919 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3921 MVT VecVT = N->getOperand(0).getSimpleValueType();
3922 MVT ElVT = VecVT.getVectorElementType();
3924 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3925 return Index / NumElemsPerChunk;
3928 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3929 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3930 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3931 llvm_unreachable("Illegal insert subvector for VINSERT");
3934 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3936 MVT VecVT = N->getSimpleValueType(0);
3937 MVT ElVT = VecVT.getVectorElementType();
3939 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3940 return Index / NumElemsPerChunk;
3943 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3944 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3945 /// and VINSERTI128 instructions.
3946 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3947 return getExtractVEXTRACTImmediate(N, 128);
3950 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3951 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3952 /// and VINSERTI64x4 instructions.
3953 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3954 return getExtractVEXTRACTImmediate(N, 256);
3957 /// getInsertVINSERT128Immediate - Return the appropriate immediate
3958 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3959 /// and VINSERTI128 instructions.
3960 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
3961 return getInsertVINSERTImmediate(N, 128);
3964 /// getInsertVINSERT256Immediate - Return the appropriate immediate
3965 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
3966 /// and VINSERTI64x4 instructions.
3967 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
3968 return getInsertVINSERTImmediate(N, 256);
3971 /// isZero - Returns true if Elt is a constant integer zero
3972 static bool isZero(SDValue V) {
3973 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
3974 return C && C->isNullValue();
3977 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3979 bool X86::isZeroNode(SDValue Elt) {
3982 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
3983 return CFP->getValueAPF().isPosZero();
3987 /// getZeroVector - Returns a vector of specified type with all zero elements.
3989 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
3990 SelectionDAG &DAG, SDLoc dl) {
3991 assert(VT.isVector() && "Expected a vector type");
3993 // Always build SSE zero vectors as <4 x i32> bitcasted
3994 // to their dest type. This ensures they get CSE'd.
3996 if (VT.is128BitVector()) { // SSE
3997 if (Subtarget->hasSSE2()) { // SSE2
3998 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
3999 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4001 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4002 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4004 } else if (VT.is256BitVector()) { // AVX
4005 if (Subtarget->hasInt256()) { // AVX2
4006 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4007 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4008 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4010 // 256-bit logic and arithmetic instructions in AVX are all
4011 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4012 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4013 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4014 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4016 } else if (VT.is512BitVector()) { // AVX-512
4017 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4018 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4019 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4020 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4021 } else if (VT.getScalarType() == MVT::i1) {
4023 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4024 && "Unexpected vector type");
4025 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4026 && "Unexpected vector type");
4027 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4028 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4029 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4031 llvm_unreachable("Unexpected vector type");
4033 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4036 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4037 SelectionDAG &DAG, SDLoc dl,
4038 unsigned vectorWidth) {
4039 assert((vectorWidth == 128 || vectorWidth == 256) &&
4040 "Unsupported vector width");
4041 EVT VT = Vec.getValueType();
4042 EVT ElVT = VT.getVectorElementType();
4043 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4044 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4045 VT.getVectorNumElements()/Factor);
4047 // Extract from UNDEF is UNDEF.
4048 if (Vec.getOpcode() == ISD::UNDEF)
4049 return DAG.getUNDEF(ResultVT);
4051 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4052 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4054 // This is the index of the first element of the vectorWidth-bit chunk
4056 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4059 // If the input is a buildvector just emit a smaller one.
4060 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4061 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4062 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4065 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4066 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4069 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4070 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4071 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4072 /// instructions or a simple subregister reference. Idx is an index in the
4073 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4074 /// lowering EXTRACT_VECTOR_ELT operations easier.
4075 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4076 SelectionDAG &DAG, SDLoc dl) {
4077 assert((Vec.getValueType().is256BitVector() ||
4078 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4079 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4082 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4083 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4084 SelectionDAG &DAG, SDLoc dl) {
4085 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4086 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4089 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4090 unsigned IdxVal, SelectionDAG &DAG,
4091 SDLoc dl, unsigned vectorWidth) {
4092 assert((vectorWidth == 128 || vectorWidth == 256) &&
4093 "Unsupported vector width");
4094 // Inserting UNDEF is Result
4095 if (Vec.getOpcode() == ISD::UNDEF)
4097 EVT VT = Vec.getValueType();
4098 EVT ElVT = VT.getVectorElementType();
4099 EVT ResultVT = Result.getValueType();
4101 // Insert the relevant vectorWidth bits.
4102 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4104 // This is the index of the first element of the vectorWidth-bit chunk
4106 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4109 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4110 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4113 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4114 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4115 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4116 /// simple superregister reference. Idx is an index in the 128 bits
4117 /// we want. It need not be aligned to a 128-bit boundary. That makes
4118 /// lowering INSERT_VECTOR_ELT operations easier.
4119 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4120 SelectionDAG &DAG, SDLoc dl) {
4121 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4123 // For insertion into the zero index (low half) of a 256-bit vector, it is
4124 // more efficient to generate a blend with immediate instead of an insert*128.
4125 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4126 // extend the subvector to the size of the result vector. Make sure that
4127 // we are not recursing on that node by checking for undef here.
4128 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4129 Result.getOpcode() != ISD::UNDEF) {
4130 EVT ResultVT = Result.getValueType();
4131 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4132 SDValue Undef = DAG.getUNDEF(ResultVT);
4133 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4136 // The blend instruction, and therefore its mask, depend on the data type.
4137 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4138 if (ScalarType.isFloatingPoint()) {
4139 // Choose either vblendps (float) or vblendpd (double).
4140 unsigned ScalarSize = ScalarType.getSizeInBits();
4141 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4142 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4143 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4144 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4147 const X86Subtarget &Subtarget =
4148 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4150 // AVX2 is needed for 256-bit integer blend support.
4151 // Integers must be cast to 32-bit because there is only vpblendd;
4152 // vpblendw can't be used for this because it has a handicapped mask.
4154 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4155 // is still more efficient than using the wrong domain vinsertf128 that
4156 // will be created by InsertSubVector().
4157 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4159 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4160 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4161 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4162 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4165 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4168 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4169 SelectionDAG &DAG, SDLoc dl) {
4170 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4171 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4174 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4175 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4176 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4177 /// large BUILD_VECTORS.
4178 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4179 unsigned NumElems, SelectionDAG &DAG,
4181 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4182 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4185 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4186 unsigned NumElems, SelectionDAG &DAG,
4188 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4189 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4192 /// getOnesVector - Returns a vector of specified type with all bits set.
4193 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4194 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4195 /// Then bitcast to their original type, ensuring they get CSE'd.
4196 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4198 assert(VT.isVector() && "Expected a vector type");
4200 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4202 if (VT.is256BitVector()) {
4203 if (HasInt256) { // AVX2
4204 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4205 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4207 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4208 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4210 } else if (VT.is128BitVector()) {
4211 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4213 llvm_unreachable("Unexpected vector type");
4215 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4218 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4219 /// operation of specified width.
4220 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4222 unsigned NumElems = VT.getVectorNumElements();
4223 SmallVector<int, 8> Mask;
4224 Mask.push_back(NumElems);
4225 for (unsigned i = 1; i != NumElems; ++i)
4227 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4230 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4231 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4233 unsigned NumElems = VT.getVectorNumElements();
4234 SmallVector<int, 8> Mask;
4235 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4237 Mask.push_back(i + NumElems);
4239 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4242 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4243 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4245 unsigned NumElems = VT.getVectorNumElements();
4246 SmallVector<int, 8> Mask;
4247 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4248 Mask.push_back(i + Half);
4249 Mask.push_back(i + NumElems + Half);
4251 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4254 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4255 /// vector of zero or undef vector. This produces a shuffle where the low
4256 /// element of V2 is swizzled into the zero/undef vector, landing at element
4257 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4258 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4260 const X86Subtarget *Subtarget,
4261 SelectionDAG &DAG) {
4262 MVT VT = V2.getSimpleValueType();
4264 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4265 unsigned NumElems = VT.getVectorNumElements();
4266 SmallVector<int, 16> MaskVec;
4267 for (unsigned i = 0; i != NumElems; ++i)
4268 // If this is the insertion idx, put the low elt of V2 here.
4269 MaskVec.push_back(i == Idx ? NumElems : i);
4270 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4273 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4274 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4275 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4276 /// shuffles which use a single input multiple times, and in those cases it will
4277 /// adjust the mask to only have indices within that single input.
4278 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4279 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4280 unsigned NumElems = VT.getVectorNumElements();
4284 bool IsFakeUnary = false;
4285 switch(N->getOpcode()) {
4286 case X86ISD::BLENDI:
4287 ImmN = N->getOperand(N->getNumOperands()-1);
4288 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4291 ImmN = N->getOperand(N->getNumOperands()-1);
4292 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4293 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4295 case X86ISD::UNPCKH:
4296 DecodeUNPCKHMask(VT, Mask);
4297 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4299 case X86ISD::UNPCKL:
4300 DecodeUNPCKLMask(VT, Mask);
4301 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4303 case X86ISD::MOVHLPS:
4304 DecodeMOVHLPSMask(NumElems, Mask);
4305 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4307 case X86ISD::MOVLHPS:
4308 DecodeMOVLHPSMask(NumElems, Mask);
4309 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4311 case X86ISD::PALIGNR:
4312 ImmN = N->getOperand(N->getNumOperands()-1);
4313 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4315 case X86ISD::PSHUFD:
4316 case X86ISD::VPERMILPI:
4317 ImmN = N->getOperand(N->getNumOperands()-1);
4318 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4321 case X86ISD::PSHUFHW:
4322 ImmN = N->getOperand(N->getNumOperands()-1);
4323 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4326 case X86ISD::PSHUFLW:
4327 ImmN = N->getOperand(N->getNumOperands()-1);
4328 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4331 case X86ISD::PSHUFB: {
4333 SDValue MaskNode = N->getOperand(1);
4334 while (MaskNode->getOpcode() == ISD::BITCAST)
4335 MaskNode = MaskNode->getOperand(0);
4337 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4338 // If we have a build-vector, then things are easy.
4339 EVT VT = MaskNode.getValueType();
4340 assert(VT.isVector() &&
4341 "Can't produce a non-vector with a build_vector!");
4342 if (!VT.isInteger())
4345 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4347 SmallVector<uint64_t, 32> RawMask;
4348 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4349 SDValue Op = MaskNode->getOperand(i);
4350 if (Op->getOpcode() == ISD::UNDEF) {
4351 RawMask.push_back((uint64_t)SM_SentinelUndef);
4354 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4357 APInt MaskElement = CN->getAPIntValue();
4359 // We now have to decode the element which could be any integer size and
4360 // extract each byte of it.
4361 for (int j = 0; j < NumBytesPerElement; ++j) {
4362 // Note that this is x86 and so always little endian: the low byte is
4363 // the first byte of the mask.
4364 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4365 MaskElement = MaskElement.lshr(8);
4368 DecodePSHUFBMask(RawMask, Mask);
4372 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4376 SDValue Ptr = MaskLoad->getBasePtr();
4377 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4378 Ptr->getOpcode() == X86ISD::WrapperRIP)
4379 Ptr = Ptr->getOperand(0);
4381 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4382 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4385 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4386 DecodePSHUFBMask(C, Mask);
4394 case X86ISD::VPERMI:
4395 ImmN = N->getOperand(N->getNumOperands()-1);
4396 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4401 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4403 case X86ISD::VPERM2X128:
4404 ImmN = N->getOperand(N->getNumOperands()-1);
4405 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4406 if (Mask.empty()) return false;
4408 case X86ISD::MOVSLDUP:
4409 DecodeMOVSLDUPMask(VT, Mask);
4412 case X86ISD::MOVSHDUP:
4413 DecodeMOVSHDUPMask(VT, Mask);
4416 case X86ISD::MOVDDUP:
4417 DecodeMOVDDUPMask(VT, Mask);
4420 case X86ISD::MOVLHPD:
4421 case X86ISD::MOVLPD:
4422 case X86ISD::MOVLPS:
4423 // Not yet implemented
4425 default: llvm_unreachable("unknown target shuffle node");
4428 // If we have a fake unary shuffle, the shuffle mask is spread across two
4429 // inputs that are actually the same node. Re-map the mask to always point
4430 // into the first input.
4433 if (M >= (int)Mask.size())
4439 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4440 /// element of the result of the vector shuffle.
4441 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4444 return SDValue(); // Limit search depth.
4446 SDValue V = SDValue(N, 0);
4447 EVT VT = V.getValueType();
4448 unsigned Opcode = V.getOpcode();
4450 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4451 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4452 int Elt = SV->getMaskElt(Index);
4455 return DAG.getUNDEF(VT.getVectorElementType());
4457 unsigned NumElems = VT.getVectorNumElements();
4458 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4459 : SV->getOperand(1);
4460 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4463 // Recurse into target specific vector shuffles to find scalars.
4464 if (isTargetShuffle(Opcode)) {
4465 MVT ShufVT = V.getSimpleValueType();
4466 unsigned NumElems = ShufVT.getVectorNumElements();
4467 SmallVector<int, 16> ShuffleMask;
4470 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4473 int Elt = ShuffleMask[Index];
4475 return DAG.getUNDEF(ShufVT.getVectorElementType());
4477 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4479 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4483 // Actual nodes that may contain scalar elements
4484 if (Opcode == ISD::BITCAST) {
4485 V = V.getOperand(0);
4486 EVT SrcVT = V.getValueType();
4487 unsigned NumElems = VT.getVectorNumElements();
4489 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4493 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4494 return (Index == 0) ? V.getOperand(0)
4495 : DAG.getUNDEF(VT.getVectorElementType());
4497 if (V.getOpcode() == ISD::BUILD_VECTOR)
4498 return V.getOperand(Index);
4503 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4505 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4506 unsigned NumNonZero, unsigned NumZero,
4508 const X86Subtarget* Subtarget,
4509 const TargetLowering &TLI) {
4517 // SSE4.1 - use PINSRB to insert each byte directly.
4518 if (Subtarget->hasSSE41()) {
4519 for (unsigned i = 0; i < 16; ++i) {
4520 bool isNonZero = (NonZeros & (1 << i)) != 0;
4524 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4526 V = DAG.getUNDEF(MVT::v16i8);
4529 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4530 MVT::v16i8, V, Op.getOperand(i),
4531 DAG.getIntPtrConstant(i, dl));
4538 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4539 for (unsigned i = 0; i < 16; ++i) {
4540 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4541 if (ThisIsNonZero && First) {
4543 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4545 V = DAG.getUNDEF(MVT::v8i16);
4550 SDValue ThisElt, LastElt;
4551 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4552 if (LastIsNonZero) {
4553 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4554 MVT::i16, Op.getOperand(i-1));
4556 if (ThisIsNonZero) {
4557 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4558 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4559 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4561 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4565 if (ThisElt.getNode())
4566 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4567 DAG.getIntPtrConstant(i/2, dl));
4571 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4574 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4576 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4577 unsigned NumNonZero, unsigned NumZero,
4579 const X86Subtarget* Subtarget,
4580 const TargetLowering &TLI) {
4587 for (unsigned i = 0; i < 8; ++i) {
4588 bool isNonZero = (NonZeros & (1 << i)) != 0;
4592 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4594 V = DAG.getUNDEF(MVT::v8i16);
4597 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4598 MVT::v8i16, V, Op.getOperand(i),
4599 DAG.getIntPtrConstant(i, dl));
4606 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4607 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4608 const X86Subtarget *Subtarget,
4609 const TargetLowering &TLI) {
4610 // Find all zeroable elements.
4611 std::bitset<4> Zeroable;
4612 for (int i=0; i < 4; ++i) {
4613 SDValue Elt = Op->getOperand(i);
4614 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4616 assert(Zeroable.size() - Zeroable.count() > 1 &&
4617 "We expect at least two non-zero elements!");
4619 // We only know how to deal with build_vector nodes where elements are either
4620 // zeroable or extract_vector_elt with constant index.
4621 SDValue FirstNonZero;
4622 unsigned FirstNonZeroIdx;
4623 for (unsigned i=0; i < 4; ++i) {
4626 SDValue Elt = Op->getOperand(i);
4627 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4628 !isa<ConstantSDNode>(Elt.getOperand(1)))
4630 // Make sure that this node is extracting from a 128-bit vector.
4631 MVT VT = Elt.getOperand(0).getSimpleValueType();
4632 if (!VT.is128BitVector())
4634 if (!FirstNonZero.getNode()) {
4636 FirstNonZeroIdx = i;
4640 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4641 SDValue V1 = FirstNonZero.getOperand(0);
4642 MVT VT = V1.getSimpleValueType();
4644 // See if this build_vector can be lowered as a blend with zero.
4646 unsigned EltMaskIdx, EltIdx;
4648 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4649 if (Zeroable[EltIdx]) {
4650 // The zero vector will be on the right hand side.
4651 Mask[EltIdx] = EltIdx+4;
4655 Elt = Op->getOperand(EltIdx);
4656 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4657 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4658 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4660 Mask[EltIdx] = EltIdx;
4664 // Let the shuffle legalizer deal with blend operations.
4665 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4666 if (V1.getSimpleValueType() != VT)
4667 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4668 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4671 // See if we can lower this build_vector to a INSERTPS.
4672 if (!Subtarget->hasSSE41())
4675 SDValue V2 = Elt.getOperand(0);
4676 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4679 bool CanFold = true;
4680 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4684 SDValue Current = Op->getOperand(i);
4685 SDValue SrcVector = Current->getOperand(0);
4688 CanFold = SrcVector == V1 &&
4689 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4695 assert(V1.getNode() && "Expected at least two non-zero elements!");
4696 if (V1.getSimpleValueType() != MVT::v4f32)
4697 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4698 if (V2.getSimpleValueType() != MVT::v4f32)
4699 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4701 // Ok, we can emit an INSERTPS instruction.
4702 unsigned ZMask = Zeroable.to_ulong();
4704 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4705 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4707 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4708 DAG.getIntPtrConstant(InsertPSMask, DL));
4709 return DAG.getNode(ISD::BITCAST, DL, VT, Result);
4712 /// Return a vector logical shift node.
4713 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4714 unsigned NumBits, SelectionDAG &DAG,
4715 const TargetLowering &TLI, SDLoc dl) {
4716 assert(VT.is128BitVector() && "Unknown type for VShift");
4717 MVT ShVT = MVT::v2i64;
4718 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4719 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4720 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4721 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4722 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4723 return DAG.getNode(ISD::BITCAST, dl, VT,
4724 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4728 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4730 // Check if the scalar load can be widened into a vector load. And if
4731 // the address is "base + cst" see if the cst can be "absorbed" into
4732 // the shuffle mask.
4733 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4734 SDValue Ptr = LD->getBasePtr();
4735 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4737 EVT PVT = LD->getValueType(0);
4738 if (PVT != MVT::i32 && PVT != MVT::f32)
4743 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4744 FI = FINode->getIndex();
4746 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4747 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4748 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4749 Offset = Ptr.getConstantOperandVal(1);
4750 Ptr = Ptr.getOperand(0);
4755 // FIXME: 256-bit vector instructions don't require a strict alignment,
4756 // improve this code to support it better.
4757 unsigned RequiredAlign = VT.getSizeInBits()/8;
4758 SDValue Chain = LD->getChain();
4759 // Make sure the stack object alignment is at least 16 or 32.
4760 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4761 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4762 if (MFI->isFixedObjectIndex(FI)) {
4763 // Can't change the alignment. FIXME: It's possible to compute
4764 // the exact stack offset and reference FI + adjust offset instead.
4765 // If someone *really* cares about this. That's the way to implement it.
4768 MFI->setObjectAlignment(FI, RequiredAlign);
4772 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4773 // Ptr + (Offset & ~15).
4776 if ((Offset % RequiredAlign) & 3)
4778 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4781 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4782 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4785 int EltNo = (Offset - StartOffset) >> 2;
4786 unsigned NumElems = VT.getVectorNumElements();
4788 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4789 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4790 LD->getPointerInfo().getWithOffset(StartOffset),
4791 false, false, false, 0);
4793 SmallVector<int, 8> Mask(NumElems, EltNo);
4795 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4801 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4802 /// elements can be replaced by a single large load which has the same value as
4803 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4805 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4807 /// FIXME: we'd also like to handle the case where the last elements are zero
4808 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4809 /// There's even a handy isZeroNode for that purpose.
4810 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4811 SDLoc &DL, SelectionDAG &DAG,
4812 bool isAfterLegalize) {
4813 unsigned NumElems = Elts.size();
4815 LoadSDNode *LDBase = nullptr;
4816 unsigned LastLoadedElt = -1U;
4818 // For each element in the initializer, see if we've found a load or an undef.
4819 // If we don't find an initial load element, or later load elements are
4820 // non-consecutive, bail out.
4821 for (unsigned i = 0; i < NumElems; ++i) {
4822 SDValue Elt = Elts[i];
4823 // Look through a bitcast.
4824 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4825 Elt = Elt.getOperand(0);
4826 if (!Elt.getNode() ||
4827 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4830 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4832 LDBase = cast<LoadSDNode>(Elt.getNode());
4836 if (Elt.getOpcode() == ISD::UNDEF)
4839 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4840 EVT LdVT = Elt.getValueType();
4841 // Each loaded element must be the correct fractional portion of the
4842 // requested vector load.
4843 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4845 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4850 // If we have found an entire vector of loads and undefs, then return a large
4851 // load of the entire vector width starting at the base pointer. If we found
4852 // consecutive loads for the low half, generate a vzext_load node.
4853 if (LastLoadedElt == NumElems - 1) {
4854 assert(LDBase && "Did not find base load for merging consecutive loads");
4855 EVT EltVT = LDBase->getValueType(0);
4856 // Ensure that the input vector size for the merged loads matches the
4857 // cumulative size of the input elements.
4858 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4861 if (isAfterLegalize &&
4862 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4865 SDValue NewLd = SDValue();
4867 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4868 LDBase->getPointerInfo(), LDBase->isVolatile(),
4869 LDBase->isNonTemporal(), LDBase->isInvariant(),
4870 LDBase->getAlignment());
4872 if (LDBase->hasAnyUseOfValue(1)) {
4873 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4875 SDValue(NewLd.getNode(), 1));
4876 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4877 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4878 SDValue(NewLd.getNode(), 1));
4884 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4885 //of a v4i32 / v4f32. It's probably worth generalizing.
4886 EVT EltVT = VT.getVectorElementType();
4887 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4888 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4889 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4890 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4892 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4893 LDBase->getPointerInfo(),
4894 LDBase->getAlignment(),
4895 false/*isVolatile*/, true/*ReadMem*/,
4898 // Make sure the newly-created LOAD is in the same position as LDBase in
4899 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4900 // update uses of LDBase's output chain to use the TokenFactor.
4901 if (LDBase->hasAnyUseOfValue(1)) {
4902 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4903 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4904 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4905 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4906 SDValue(ResNode.getNode(), 1));
4909 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4914 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4915 /// to generate a splat value for the following cases:
4916 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4917 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4918 /// a scalar load, or a constant.
4919 /// The VBROADCAST node is returned when a pattern is found,
4920 /// or SDValue() otherwise.
4921 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4922 SelectionDAG &DAG) {
4923 // VBROADCAST requires AVX.
4924 // TODO: Splats could be generated for non-AVX CPUs using SSE
4925 // instructions, but there's less potential gain for only 128-bit vectors.
4926 if (!Subtarget->hasAVX())
4929 MVT VT = Op.getSimpleValueType();
4932 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4933 "Unsupported vector type for broadcast.");
4938 switch (Op.getOpcode()) {
4940 // Unknown pattern found.
4943 case ISD::BUILD_VECTOR: {
4944 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4945 BitVector UndefElements;
4946 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4948 // We need a splat of a single value to use broadcast, and it doesn't
4949 // make any sense if the value is only in one element of the vector.
4950 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4954 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4955 Ld.getOpcode() == ISD::ConstantFP);
4957 // Make sure that all of the users of a non-constant load are from the
4958 // BUILD_VECTOR node.
4959 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4964 case ISD::VECTOR_SHUFFLE: {
4965 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4967 // Shuffles must have a splat mask where the first element is
4969 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4972 SDValue Sc = Op.getOperand(0);
4973 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4974 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4976 if (!Subtarget->hasInt256())
4979 // Use the register form of the broadcast instruction available on AVX2.
4980 if (VT.getSizeInBits() >= 256)
4981 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4982 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4985 Ld = Sc.getOperand(0);
4986 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4987 Ld.getOpcode() == ISD::ConstantFP);
4989 // The scalar_to_vector node and the suspected
4990 // load node must have exactly one user.
4991 // Constants may have multiple users.
4993 // AVX-512 has register version of the broadcast
4994 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
4995 Ld.getValueType().getSizeInBits() >= 32;
4996 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5003 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5004 bool IsGE256 = (VT.getSizeInBits() >= 256);
5006 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5007 // instruction to save 8 or more bytes of constant pool data.
5008 // TODO: If multiple splats are generated to load the same constant,
5009 // it may be detrimental to overall size. There needs to be a way to detect
5010 // that condition to know if this is truly a size win.
5011 const Function *F = DAG.getMachineFunction().getFunction();
5012 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5014 // Handle broadcasting a single constant scalar from the constant pool
5016 // On Sandybridge (no AVX2), it is still better to load a constant vector
5017 // from the constant pool and not to broadcast it from a scalar.
5018 // But override that restriction when optimizing for size.
5019 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5020 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5021 EVT CVT = Ld.getValueType();
5022 assert(!CVT.isVector() && "Must not broadcast a vector type");
5024 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5025 // For size optimization, also splat v2f64 and v2i64, and for size opt
5026 // with AVX2, also splat i8 and i16.
5027 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5028 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5029 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5030 const Constant *C = nullptr;
5031 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5032 C = CI->getConstantIntValue();
5033 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5034 C = CF->getConstantFPValue();
5036 assert(C && "Invalid constant type");
5038 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5039 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5040 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5041 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5042 MachinePointerInfo::getConstantPool(),
5043 false, false, false, Alignment);
5045 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5049 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5051 // Handle AVX2 in-register broadcasts.
5052 if (!IsLoad && Subtarget->hasInt256() &&
5053 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5054 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5056 // The scalar source must be a normal load.
5060 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5061 (Subtarget->hasVLX() && ScalarSize == 64))
5062 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5064 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5065 // double since there is no vbroadcastsd xmm
5066 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5067 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5071 // Unsupported broadcast.
5075 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5076 /// underlying vector and index.
5078 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5080 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5082 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5083 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5086 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5088 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5090 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5091 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5094 // In this case the vector is the extract_subvector expression and the index
5095 // is 2, as specified by the shuffle.
5096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5097 SDValue ShuffleVec = SVOp->getOperand(0);
5098 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5099 assert(ShuffleVecVT.getVectorElementType() ==
5100 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5102 int ShuffleIdx = SVOp->getMaskElt(Idx);
5103 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5104 ExtractedFromVec = ShuffleVec;
5110 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5111 MVT VT = Op.getSimpleValueType();
5113 // Skip if insert_vec_elt is not supported.
5114 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5115 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5119 unsigned NumElems = Op.getNumOperands();
5123 SmallVector<unsigned, 4> InsertIndices;
5124 SmallVector<int, 8> Mask(NumElems, -1);
5126 for (unsigned i = 0; i != NumElems; ++i) {
5127 unsigned Opc = Op.getOperand(i).getOpcode();
5129 if (Opc == ISD::UNDEF)
5132 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5133 // Quit if more than 1 elements need inserting.
5134 if (InsertIndices.size() > 1)
5137 InsertIndices.push_back(i);
5141 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5142 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5143 // Quit if non-constant index.
5144 if (!isa<ConstantSDNode>(ExtIdx))
5146 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5148 // Quit if extracted from vector of different type.
5149 if (ExtractedFromVec.getValueType() != VT)
5152 if (!VecIn1.getNode())
5153 VecIn1 = ExtractedFromVec;
5154 else if (VecIn1 != ExtractedFromVec) {
5155 if (!VecIn2.getNode())
5156 VecIn2 = ExtractedFromVec;
5157 else if (VecIn2 != ExtractedFromVec)
5158 // Quit if more than 2 vectors to shuffle
5162 if (ExtractedFromVec == VecIn1)
5164 else if (ExtractedFromVec == VecIn2)
5165 Mask[i] = Idx + NumElems;
5168 if (!VecIn1.getNode())
5171 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5172 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5173 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5174 unsigned Idx = InsertIndices[i];
5175 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5176 DAG.getIntPtrConstant(Idx, DL));
5182 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5184 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5186 MVT VT = Op.getSimpleValueType();
5187 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5188 "Unexpected type in LowerBUILD_VECTORvXi1!");
5191 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5192 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5193 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5194 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5197 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5198 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5199 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5200 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5203 bool AllContants = true;
5204 uint64_t Immediate = 0;
5205 int NonConstIdx = -1;
5206 bool IsSplat = true;
5207 unsigned NumNonConsts = 0;
5208 unsigned NumConsts = 0;
5209 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5210 SDValue In = Op.getOperand(idx);
5211 if (In.getOpcode() == ISD::UNDEF)
5213 if (!isa<ConstantSDNode>(In)) {
5214 AllContants = false;
5219 if (cast<ConstantSDNode>(In)->getZExtValue())
5220 Immediate |= (1ULL << idx);
5222 if (In != Op.getOperand(0))
5227 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5228 DAG.getConstant(Immediate, dl, MVT::i16));
5229 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5230 DAG.getIntPtrConstant(0, dl));
5233 if (NumNonConsts == 1 && NonConstIdx != 0) {
5236 SDValue VecAsImm = DAG.getConstant(Immediate, dl,
5237 MVT::getIntegerVT(VT.getSizeInBits()));
5238 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5241 DstVec = DAG.getUNDEF(VT);
5242 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5243 Op.getOperand(NonConstIdx),
5244 DAG.getIntPtrConstant(NonConstIdx, dl));
5246 if (!IsSplat && (NonConstIdx != 0))
5247 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5248 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5251 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5252 DAG.getConstant(-1, dl, SelectVT),
5253 DAG.getConstant(0, dl, SelectVT));
5255 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5256 DAG.getConstant((Immediate | 1), dl, SelectVT),
5257 DAG.getConstant(Immediate, dl, SelectVT));
5258 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5261 /// \brief Return true if \p N implements a horizontal binop and return the
5262 /// operands for the horizontal binop into V0 and V1.
5264 /// This is a helper function of LowerToHorizontalOp().
5265 /// This function checks that the build_vector \p N in input implements a
5266 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5267 /// operation to match.
5268 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5269 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5270 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5273 /// This function only analyzes elements of \p N whose indices are
5274 /// in range [BaseIdx, LastIdx).
5275 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5277 unsigned BaseIdx, unsigned LastIdx,
5278 SDValue &V0, SDValue &V1) {
5279 EVT VT = N->getValueType(0);
5281 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5282 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5283 "Invalid Vector in input!");
5285 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5286 bool CanFold = true;
5287 unsigned ExpectedVExtractIdx = BaseIdx;
5288 unsigned NumElts = LastIdx - BaseIdx;
5289 V0 = DAG.getUNDEF(VT);
5290 V1 = DAG.getUNDEF(VT);
5292 // Check if N implements a horizontal binop.
5293 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5294 SDValue Op = N->getOperand(i + BaseIdx);
5297 if (Op->getOpcode() == ISD::UNDEF) {
5298 // Update the expected vector extract index.
5299 if (i * 2 == NumElts)
5300 ExpectedVExtractIdx = BaseIdx;
5301 ExpectedVExtractIdx += 2;
5305 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5310 SDValue Op0 = Op.getOperand(0);
5311 SDValue Op1 = Op.getOperand(1);
5313 // Try to match the following pattern:
5314 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5315 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5316 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5317 Op0.getOperand(0) == Op1.getOperand(0) &&
5318 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5319 isa<ConstantSDNode>(Op1.getOperand(1)));
5323 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5324 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5326 if (i * 2 < NumElts) {
5327 if (V0.getOpcode() == ISD::UNDEF) {
5328 V0 = Op0.getOperand(0);
5329 if (V0.getValueType() != VT)
5333 if (V1.getOpcode() == ISD::UNDEF) {
5334 V1 = Op0.getOperand(0);
5335 if (V1.getValueType() != VT)
5338 if (i * 2 == NumElts)
5339 ExpectedVExtractIdx = BaseIdx;
5342 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5343 if (I0 == ExpectedVExtractIdx)
5344 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5345 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5346 // Try to match the following dag sequence:
5347 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5348 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5352 ExpectedVExtractIdx += 2;
5358 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5359 /// a concat_vector.
5361 /// This is a helper function of LowerToHorizontalOp().
5362 /// This function expects two 256-bit vectors called V0 and V1.
5363 /// At first, each vector is split into two separate 128-bit vectors.
5364 /// Then, the resulting 128-bit vectors are used to implement two
5365 /// horizontal binary operations.
5367 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5369 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5370 /// the two new horizontal binop.
5371 /// When Mode is set, the first horizontal binop dag node would take as input
5372 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5373 /// horizontal binop dag node would take as input the lower 128-bit of V1
5374 /// and the upper 128-bit of V1.
5376 /// HADD V0_LO, V0_HI
5377 /// HADD V1_LO, V1_HI
5379 /// Otherwise, the first horizontal binop dag node takes as input the lower
5380 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5381 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5383 /// HADD V0_LO, V1_LO
5384 /// HADD V0_HI, V1_HI
5386 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5387 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5388 /// the upper 128-bits of the result.
5389 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5390 SDLoc DL, SelectionDAG &DAG,
5391 unsigned X86Opcode, bool Mode,
5392 bool isUndefLO, bool isUndefHI) {
5393 EVT VT = V0.getValueType();
5394 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5395 "Invalid nodes in input!");
5397 unsigned NumElts = VT.getVectorNumElements();
5398 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5399 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5400 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5401 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5402 EVT NewVT = V0_LO.getValueType();
5404 SDValue LO = DAG.getUNDEF(NewVT);
5405 SDValue HI = DAG.getUNDEF(NewVT);
5408 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5409 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5410 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5411 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5412 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5414 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5415 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5416 V1_LO->getOpcode() != ISD::UNDEF))
5417 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5419 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5420 V1_HI->getOpcode() != ISD::UNDEF))
5421 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5424 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5427 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5429 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5430 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5431 EVT VT = BV->getValueType(0);
5432 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5433 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5437 unsigned NumElts = VT.getVectorNumElements();
5438 SDValue InVec0 = DAG.getUNDEF(VT);
5439 SDValue InVec1 = DAG.getUNDEF(VT);
5441 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5442 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5444 // Odd-numbered elements in the input build vector are obtained from
5445 // adding two integer/float elements.
5446 // Even-numbered elements in the input build vector are obtained from
5447 // subtracting two integer/float elements.
5448 unsigned ExpectedOpcode = ISD::FSUB;
5449 unsigned NextExpectedOpcode = ISD::FADD;
5450 bool AddFound = false;
5451 bool SubFound = false;
5453 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5454 SDValue Op = BV->getOperand(i);
5456 // Skip 'undef' values.
5457 unsigned Opcode = Op.getOpcode();
5458 if (Opcode == ISD::UNDEF) {
5459 std::swap(ExpectedOpcode, NextExpectedOpcode);
5463 // Early exit if we found an unexpected opcode.
5464 if (Opcode != ExpectedOpcode)
5467 SDValue Op0 = Op.getOperand(0);
5468 SDValue Op1 = Op.getOperand(1);
5470 // Try to match the following pattern:
5471 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5472 // Early exit if we cannot match that sequence.
5473 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5474 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5475 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5476 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5477 Op0.getOperand(1) != Op1.getOperand(1))
5480 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5484 // We found a valid add/sub node. Update the information accordingly.
5490 // Update InVec0 and InVec1.
5491 if (InVec0.getOpcode() == ISD::UNDEF) {
5492 InVec0 = Op0.getOperand(0);
5493 if (InVec0.getValueType() != VT)
5496 if (InVec1.getOpcode() == ISD::UNDEF) {
5497 InVec1 = Op1.getOperand(0);
5498 if (InVec1.getValueType() != VT)
5502 // Make sure that operands in input to each add/sub node always
5503 // come from a same pair of vectors.
5504 if (InVec0 != Op0.getOperand(0)) {
5505 if (ExpectedOpcode == ISD::FSUB)
5508 // FADD is commutable. Try to commute the operands
5509 // and then test again.
5510 std::swap(Op0, Op1);
5511 if (InVec0 != Op0.getOperand(0))
5515 if (InVec1 != Op1.getOperand(0))
5518 // Update the pair of expected opcodes.
5519 std::swap(ExpectedOpcode, NextExpectedOpcode);
5522 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5523 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5524 InVec1.getOpcode() != ISD::UNDEF)
5525 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5530 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5531 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5532 const X86Subtarget *Subtarget,
5533 SelectionDAG &DAG) {
5534 EVT VT = BV->getValueType(0);
5535 unsigned NumElts = VT.getVectorNumElements();
5536 unsigned NumUndefsLO = 0;
5537 unsigned NumUndefsHI = 0;
5538 unsigned Half = NumElts/2;
5540 // Count the number of UNDEF operands in the build_vector in input.
5541 for (unsigned i = 0, e = Half; i != e; ++i)
5542 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5545 for (unsigned i = Half, e = NumElts; i != e; ++i)
5546 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5549 // Early exit if this is either a build_vector of all UNDEFs or all the
5550 // operands but one are UNDEF.
5551 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5555 SDValue InVec0, InVec1;
5556 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5557 // Try to match an SSE3 float HADD/HSUB.
5558 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5559 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5561 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5562 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5563 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5564 // Try to match an SSSE3 integer HADD/HSUB.
5565 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5566 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5568 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5569 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5572 if (!Subtarget->hasAVX())
5575 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5576 // Try to match an AVX horizontal add/sub of packed single/double
5577 // precision floating point values from 256-bit vectors.
5578 SDValue InVec2, InVec3;
5579 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5580 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5581 ((InVec0.getOpcode() == ISD::UNDEF ||
5582 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5583 ((InVec1.getOpcode() == ISD::UNDEF ||
5584 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5585 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5587 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5588 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5589 ((InVec0.getOpcode() == ISD::UNDEF ||
5590 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5591 ((InVec1.getOpcode() == ISD::UNDEF ||
5592 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5593 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5594 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5595 // Try to match an AVX2 horizontal add/sub of signed integers.
5596 SDValue InVec2, InVec3;
5598 bool CanFold = true;
5600 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5601 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5602 ((InVec0.getOpcode() == ISD::UNDEF ||
5603 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5604 ((InVec1.getOpcode() == ISD::UNDEF ||
5605 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5606 X86Opcode = X86ISD::HADD;
5607 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5608 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5609 ((InVec0.getOpcode() == ISD::UNDEF ||
5610 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5611 ((InVec1.getOpcode() == ISD::UNDEF ||
5612 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5613 X86Opcode = X86ISD::HSUB;
5618 // Fold this build_vector into a single horizontal add/sub.
5619 // Do this only if the target has AVX2.
5620 if (Subtarget->hasAVX2())
5621 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5623 // Do not try to expand this build_vector into a pair of horizontal
5624 // add/sub if we can emit a pair of scalar add/sub.
5625 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5628 // Convert this build_vector into a pair of horizontal binop followed by
5630 bool isUndefLO = NumUndefsLO == Half;
5631 bool isUndefHI = NumUndefsHI == Half;
5632 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5633 isUndefLO, isUndefHI);
5637 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5638 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5640 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5641 X86Opcode = X86ISD::HADD;
5642 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5643 X86Opcode = X86ISD::HSUB;
5644 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5645 X86Opcode = X86ISD::FHADD;
5646 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5647 X86Opcode = X86ISD::FHSUB;
5651 // Don't try to expand this build_vector into a pair of horizontal add/sub
5652 // if we can simply emit a pair of scalar add/sub.
5653 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5656 // Convert this build_vector into two horizontal add/sub followed by
5658 bool isUndefLO = NumUndefsLO == Half;
5659 bool isUndefHI = NumUndefsHI == Half;
5660 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5661 isUndefLO, isUndefHI);
5668 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5671 MVT VT = Op.getSimpleValueType();
5672 MVT ExtVT = VT.getVectorElementType();
5673 unsigned NumElems = Op.getNumOperands();
5675 // Generate vectors for predicate vectors.
5676 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5677 return LowerBUILD_VECTORvXi1(Op, DAG);
5679 // Vectors containing all zeros can be matched by pxor and xorps later
5680 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5681 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5682 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5683 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5686 return getZeroVector(VT, Subtarget, DAG, dl);
5689 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5690 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5691 // vpcmpeqd on 256-bit vectors.
5692 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5693 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5696 if (!VT.is512BitVector())
5697 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5700 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5701 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5703 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5704 return HorizontalOp;
5705 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5708 unsigned EVTBits = ExtVT.getSizeInBits();
5710 unsigned NumZero = 0;
5711 unsigned NumNonZero = 0;
5712 unsigned NonZeros = 0;
5713 bool IsAllConstants = true;
5714 SmallSet<SDValue, 8> Values;
5715 for (unsigned i = 0; i < NumElems; ++i) {
5716 SDValue Elt = Op.getOperand(i);
5717 if (Elt.getOpcode() == ISD::UNDEF)
5720 if (Elt.getOpcode() != ISD::Constant &&
5721 Elt.getOpcode() != ISD::ConstantFP)
5722 IsAllConstants = false;
5723 if (X86::isZeroNode(Elt))
5726 NonZeros |= (1 << i);
5731 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5732 if (NumNonZero == 0)
5733 return DAG.getUNDEF(VT);
5735 // Special case for single non-zero, non-undef, element.
5736 if (NumNonZero == 1) {
5737 unsigned Idx = countTrailingZeros(NonZeros);
5738 SDValue Item = Op.getOperand(Idx);
5740 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5741 // the value are obviously zero, truncate the value to i32 and do the
5742 // insertion that way. Only do this if the value is non-constant or if the
5743 // value is a constant being inserted into element 0. It is cheaper to do
5744 // a constant pool load than it is to do a movd + shuffle.
5745 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5746 (!IsAllConstants || Idx == 0)) {
5747 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5749 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5750 EVT VecVT = MVT::v4i32;
5752 // Truncate the value (which may itself be a constant) to i32, and
5753 // convert it to a vector with movd (S2V+shuffle to zero extend).
5754 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5755 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5757 ISD::BITCAST, dl, VT,
5758 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5762 // If we have a constant or non-constant insertion into the low element of
5763 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5764 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5765 // depending on what the source datatype is.
5768 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5770 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5771 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5772 if (VT.is512BitVector()) {
5773 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5774 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5775 Item, DAG.getIntPtrConstant(0, dl));
5777 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5778 "Expected an SSE value type!");
5779 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5780 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5781 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5784 // We can't directly insert an i8 or i16 into a vector, so zero extend
5786 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5787 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5788 if (VT.is256BitVector()) {
5789 if (Subtarget->hasAVX()) {
5790 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5791 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5793 // Without AVX, we need to extend to a 128-bit vector and then
5794 // insert into the 256-bit vector.
5795 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5796 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5797 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5800 assert(VT.is128BitVector() && "Expected an SSE value type!");
5801 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5802 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5804 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5808 // Is it a vector logical left shift?
5809 if (NumElems == 2 && Idx == 1 &&
5810 X86::isZeroNode(Op.getOperand(0)) &&
5811 !X86::isZeroNode(Op.getOperand(1))) {
5812 unsigned NumBits = VT.getSizeInBits();
5813 return getVShift(true, VT,
5814 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5815 VT, Op.getOperand(1)),
5816 NumBits/2, DAG, *this, dl);
5819 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5822 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5823 // is a non-constant being inserted into an element other than the low one,
5824 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5825 // movd/movss) to move this into the low element, then shuffle it into
5827 if (EVTBits == 32) {
5828 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5829 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5833 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5834 if (Values.size() == 1) {
5835 if (EVTBits == 32) {
5836 // Instead of a shuffle like this:
5837 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5838 // Check if it's possible to issue this instead.
5839 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5840 unsigned Idx = countTrailingZeros(NonZeros);
5841 SDValue Item = Op.getOperand(Idx);
5842 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5843 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5848 // A vector full of immediates; various special cases are already
5849 // handled, so this is best done with a single constant-pool load.
5853 // For AVX-length vectors, see if we can use a vector load to get all of the
5854 // elements, otherwise build the individual 128-bit pieces and use
5855 // shuffles to put them in place.
5856 if (VT.is256BitVector() || VT.is512BitVector()) {
5857 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5859 // Check for a build vector of consecutive loads.
5860 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5863 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5865 // Build both the lower and upper subvector.
5866 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5867 makeArrayRef(&V[0], NumElems/2));
5868 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5869 makeArrayRef(&V[NumElems / 2], NumElems/2));
5871 // Recreate the wider vector with the lower and upper part.
5872 if (VT.is256BitVector())
5873 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5874 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5877 // Let legalizer expand 2-wide build_vectors.
5878 if (EVTBits == 64) {
5879 if (NumNonZero == 1) {
5880 // One half is zero or undef.
5881 unsigned Idx = countTrailingZeros(NonZeros);
5882 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5883 Op.getOperand(Idx));
5884 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5889 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5890 if (EVTBits == 8 && NumElems == 16)
5891 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5895 if (EVTBits == 16 && NumElems == 8)
5896 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5900 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5901 if (EVTBits == 32 && NumElems == 4)
5902 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5905 // If element VT is == 32 bits, turn it into a number of shuffles.
5906 SmallVector<SDValue, 8> V(NumElems);
5907 if (NumElems == 4 && NumZero > 0) {
5908 for (unsigned i = 0; i < 4; ++i) {
5909 bool isZero = !(NonZeros & (1 << i));
5911 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5913 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5916 for (unsigned i = 0; i < 2; ++i) {
5917 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5920 V[i] = V[i*2]; // Must be a zero vector.
5923 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5926 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5929 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5934 bool Reverse1 = (NonZeros & 0x3) == 2;
5935 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5939 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5940 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5942 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5945 if (Values.size() > 1 && VT.is128BitVector()) {
5946 // Check for a build vector of consecutive loads.
5947 for (unsigned i = 0; i < NumElems; ++i)
5948 V[i] = Op.getOperand(i);
5950 // Check for elements which are consecutive loads.
5951 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5954 // Check for a build vector from mostly shuffle plus few inserting.
5955 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
5958 // For SSE 4.1, use insertps to put the high elements into the low element.
5959 if (Subtarget->hasSSE41()) {
5961 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5962 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5964 Result = DAG.getUNDEF(VT);
5966 for (unsigned i = 1; i < NumElems; ++i) {
5967 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5968 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5969 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
5974 // Otherwise, expand into a number of unpckl*, start by extending each of
5975 // our (non-undef) elements to the full vector width with the element in the
5976 // bottom slot of the vector (which generates no code for SSE).
5977 for (unsigned i = 0; i < NumElems; ++i) {
5978 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5979 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5981 V[i] = DAG.getUNDEF(VT);
5984 // Next, we iteratively mix elements, e.g. for v4f32:
5985 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5986 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5987 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5988 unsigned EltStride = NumElems >> 1;
5989 while (EltStride != 0) {
5990 for (unsigned i = 0; i < EltStride; ++i) {
5991 // If V[i+EltStride] is undef and this is the first round of mixing,
5992 // then it is safe to just drop this shuffle: V[i] is already in the
5993 // right place, the one element (since it's the first round) being
5994 // inserted as undef can be dropped. This isn't safe for successive
5995 // rounds because they will permute elements within both vectors.
5996 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5997 EltStride == NumElems/2)
6000 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6009 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6010 // to create 256-bit vectors from two other 128-bit ones.
6011 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6013 MVT ResVT = Op.getSimpleValueType();
6015 assert((ResVT.is256BitVector() ||
6016 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6018 SDValue V1 = Op.getOperand(0);
6019 SDValue V2 = Op.getOperand(1);
6020 unsigned NumElems = ResVT.getVectorNumElements();
6021 if (ResVT.is256BitVector())
6022 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6024 if (Op.getNumOperands() == 4) {
6025 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6026 ResVT.getVectorNumElements()/2);
6027 SDValue V3 = Op.getOperand(2);
6028 SDValue V4 = Op.getOperand(3);
6029 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6030 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6032 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6035 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6036 const X86Subtarget *Subtarget,
6037 SelectionDAG & DAG) {
6039 MVT ResVT = Op.getSimpleValueType();
6040 unsigned NumOfOperands = Op.getNumOperands();
6042 assert(isPowerOf2_32(NumOfOperands) &&
6043 "Unexpected number of operands in CONCAT_VECTORS");
6045 if (NumOfOperands > 2) {
6046 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6047 ResVT.getVectorNumElements()/2);
6048 SmallVector<SDValue, 2> Ops;
6049 for (unsigned i = 0; i < NumOfOperands/2; i++)
6050 Ops.push_back(Op.getOperand(i));
6051 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6053 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6054 Ops.push_back(Op.getOperand(i));
6055 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6056 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6059 SDValue V1 = Op.getOperand(0);
6060 SDValue V2 = Op.getOperand(1);
6061 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6062 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6064 if (IsZeroV1 && IsZeroV2)
6065 return getZeroVector(ResVT, Subtarget, DAG, dl);
6067 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6068 SDValue Undef = DAG.getUNDEF(ResVT);
6069 unsigned NumElems = ResVT.getVectorNumElements();
6070 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6072 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6073 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6077 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6078 // Zero the upper bits of V1
6079 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6080 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6083 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6086 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6087 const X86Subtarget *Subtarget,
6088 SelectionDAG &DAG) {
6089 MVT VT = Op.getSimpleValueType();
6090 if (VT.getVectorElementType() == MVT::i1)
6091 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6093 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6094 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6095 Op.getNumOperands() == 4)));
6097 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6098 // from two other 128-bit ones.
6100 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6101 return LowerAVXCONCAT_VECTORS(Op, DAG);
6105 //===----------------------------------------------------------------------===//
6106 // Vector shuffle lowering
6108 // This is an experimental code path for lowering vector shuffles on x86. It is
6109 // designed to handle arbitrary vector shuffles and blends, gracefully
6110 // degrading performance as necessary. It works hard to recognize idiomatic
6111 // shuffles and lower them to optimal instruction patterns without leaving
6112 // a framework that allows reasonably efficient handling of all vector shuffle
6114 //===----------------------------------------------------------------------===//
6116 /// \brief Tiny helper function to identify a no-op mask.
6118 /// This is a somewhat boring predicate function. It checks whether the mask
6119 /// array input, which is assumed to be a single-input shuffle mask of the kind
6120 /// used by the X86 shuffle instructions (not a fully general
6121 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6122 /// in-place shuffle are 'no-op's.
6123 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6124 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6125 if (Mask[i] != -1 && Mask[i] != i)
6130 /// \brief Helper function to classify a mask as a single-input mask.
6132 /// This isn't a generic single-input test because in the vector shuffle
6133 /// lowering we canonicalize single inputs to be the first input operand. This
6134 /// means we can more quickly test for a single input by only checking whether
6135 /// an input from the second operand exists. We also assume that the size of
6136 /// mask corresponds to the size of the input vectors which isn't true in the
6137 /// fully general case.
6138 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6140 if (M >= (int)Mask.size())
6145 /// \brief Test whether there are elements crossing 128-bit lanes in this
6148 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6149 /// and we routinely test for these.
6150 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6151 int LaneSize = 128 / VT.getScalarSizeInBits();
6152 int Size = Mask.size();
6153 for (int i = 0; i < Size; ++i)
6154 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6159 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6161 /// This checks a shuffle mask to see if it is performing the same
6162 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6163 /// that it is also not lane-crossing. It may however involve a blend from the
6164 /// same lane of a second vector.
6166 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6167 /// non-trivial to compute in the face of undef lanes. The representation is
6168 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6169 /// entries from both V1 and V2 inputs to the wider mask.
6171 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6172 SmallVectorImpl<int> &RepeatedMask) {
6173 int LaneSize = 128 / VT.getScalarSizeInBits();
6174 RepeatedMask.resize(LaneSize, -1);
6175 int Size = Mask.size();
6176 for (int i = 0; i < Size; ++i) {
6179 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6180 // This entry crosses lanes, so there is no way to model this shuffle.
6183 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6184 if (RepeatedMask[i % LaneSize] == -1)
6185 // This is the first non-undef entry in this slot of a 128-bit lane.
6186 RepeatedMask[i % LaneSize] =
6187 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6188 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6189 // Found a mismatch with the repeated mask.
6195 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6198 /// This is a fast way to test a shuffle mask against a fixed pattern:
6200 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6202 /// It returns true if the mask is exactly as wide as the argument list, and
6203 /// each element of the mask is either -1 (signifying undef) or the value given
6204 /// in the argument.
6205 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6206 ArrayRef<int> ExpectedMask) {
6207 if (Mask.size() != ExpectedMask.size())
6210 int Size = Mask.size();
6212 // If the values are build vectors, we can look through them to find
6213 // equivalent inputs that make the shuffles equivalent.
6214 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6215 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6217 for (int i = 0; i < Size; ++i)
6218 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6219 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6220 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6221 if (!MaskBV || !ExpectedBV ||
6222 MaskBV->getOperand(Mask[i] % Size) !=
6223 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6230 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6232 /// This helper function produces an 8-bit shuffle immediate corresponding to
6233 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6234 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6237 /// NB: We rely heavily on "undef" masks preserving the input lane.
6238 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6239 SelectionDAG &DAG) {
6240 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6241 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6242 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6243 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6244 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6247 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6248 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6249 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6250 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6251 return DAG.getConstant(Imm, DL, MVT::i8);
6254 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6256 /// This is used as a fallback approach when first class blend instructions are
6257 /// unavailable. Currently it is only suitable for integer vectors, but could
6258 /// be generalized for floating point vectors if desirable.
6259 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6260 SDValue V2, ArrayRef<int> Mask,
6261 SelectionDAG &DAG) {
6262 assert(VT.isInteger() && "Only supports integer vector types!");
6263 MVT EltVT = VT.getScalarType();
6264 int NumEltBits = EltVT.getSizeInBits();
6265 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6266 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6268 SmallVector<SDValue, 16> MaskOps;
6269 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6270 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6271 return SDValue(); // Shuffled input!
6272 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6275 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6276 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6277 // We have to cast V2 around.
6278 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6279 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6280 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6281 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6282 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6283 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6286 /// \brief Try to emit a blend instruction for a shuffle.
6288 /// This doesn't do any checks for the availability of instructions for blending
6289 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6290 /// be matched in the backend with the type given. What it does check for is
6291 /// that the shuffle mask is in fact a blend.
6292 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6293 SDValue V2, ArrayRef<int> Mask,
6294 const X86Subtarget *Subtarget,
6295 SelectionDAG &DAG) {
6296 unsigned BlendMask = 0;
6297 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6298 if (Mask[i] >= Size) {
6299 if (Mask[i] != i + Size)
6300 return SDValue(); // Shuffled V2 input!
6301 BlendMask |= 1u << i;
6304 if (Mask[i] >= 0 && Mask[i] != i)
6305 return SDValue(); // Shuffled V1 input!
6307 switch (VT.SimpleTy) {
6312 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6313 DAG.getConstant(BlendMask, DL, MVT::i8));
6317 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6321 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6322 // that instruction.
6323 if (Subtarget->hasAVX2()) {
6324 // Scale the blend by the number of 32-bit dwords per element.
6325 int Scale = VT.getScalarSizeInBits() / 32;
6327 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6328 if (Mask[i] >= Size)
6329 for (int j = 0; j < Scale; ++j)
6330 BlendMask |= 1u << (i * Scale + j);
6332 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6333 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6334 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6335 return DAG.getNode(ISD::BITCAST, DL, VT,
6336 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6337 DAG.getConstant(BlendMask, DL, MVT::i8)));
6341 // For integer shuffles we need to expand the mask and cast the inputs to
6342 // v8i16s prior to blending.
6343 int Scale = 8 / VT.getVectorNumElements();
6345 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6346 if (Mask[i] >= Size)
6347 for (int j = 0; j < Scale; ++j)
6348 BlendMask |= 1u << (i * Scale + j);
6350 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6351 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6352 return DAG.getNode(ISD::BITCAST, DL, VT,
6353 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6354 DAG.getConstant(BlendMask, DL, MVT::i8)));
6358 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6359 SmallVector<int, 8> RepeatedMask;
6360 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6361 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6362 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6364 for (int i = 0; i < 8; ++i)
6365 if (RepeatedMask[i] >= 16)
6366 BlendMask |= 1u << i;
6367 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6368 DAG.getConstant(BlendMask, DL, MVT::i8));
6374 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6375 "256-bit byte-blends require AVX2 support!");
6377 // Scale the blend by the number of bytes per element.
6378 int Scale = VT.getScalarSizeInBits() / 8;
6380 // This form of blend is always done on bytes. Compute the byte vector
6382 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6384 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6385 // mix of LLVM's code generator and the x86 backend. We tell the code
6386 // generator that boolean values in the elements of an x86 vector register
6387 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6388 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6389 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6390 // of the element (the remaining are ignored) and 0 in that high bit would
6391 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6392 // the LLVM model for boolean values in vector elements gets the relevant
6393 // bit set, it is set backwards and over constrained relative to x86's
6395 SmallVector<SDValue, 32> VSELECTMask;
6396 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6397 for (int j = 0; j < Scale; ++j)
6398 VSELECTMask.push_back(
6399 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6400 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6403 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6404 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6406 ISD::BITCAST, DL, VT,
6407 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6408 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6413 llvm_unreachable("Not a supported integer vector type!");
6417 /// \brief Try to lower as a blend of elements from two inputs followed by
6418 /// a single-input permutation.
6420 /// This matches the pattern where we can blend elements from two inputs and
6421 /// then reduce the shuffle to a single-input permutation.
6422 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6425 SelectionDAG &DAG) {
6426 // We build up the blend mask while checking whether a blend is a viable way
6427 // to reduce the shuffle.
6428 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6429 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6431 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6435 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6437 if (BlendMask[Mask[i] % Size] == -1)
6438 BlendMask[Mask[i] % Size] = Mask[i];
6439 else if (BlendMask[Mask[i] % Size] != Mask[i])
6440 return SDValue(); // Can't blend in the needed input!
6442 PermuteMask[i] = Mask[i] % Size;
6445 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6446 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6449 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6450 /// blends and permutes.
6452 /// This matches the extremely common pattern for handling combined
6453 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6454 /// operations. It will try to pick the best arrangement of shuffles and
6456 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6460 SelectionDAG &DAG) {
6461 // Shuffle the input elements into the desired positions in V1 and V2 and
6462 // blend them together.
6463 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6464 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6465 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6466 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6467 if (Mask[i] >= 0 && Mask[i] < Size) {
6468 V1Mask[i] = Mask[i];
6470 } else if (Mask[i] >= Size) {
6471 V2Mask[i] = Mask[i] - Size;
6472 BlendMask[i] = i + Size;
6475 // Try to lower with the simpler initial blend strategy unless one of the
6476 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6477 // shuffle may be able to fold with a load or other benefit. However, when
6478 // we'll have to do 2x as many shuffles in order to achieve this, blending
6479 // first is a better strategy.
6480 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6481 if (SDValue BlendPerm =
6482 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6485 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6486 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6487 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6490 /// \brief Try to lower a vector shuffle as a byte rotation.
6492 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6493 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6494 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6495 /// try to generically lower a vector shuffle through such an pattern. It
6496 /// does not check for the profitability of lowering either as PALIGNR or
6497 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6498 /// This matches shuffle vectors that look like:
6500 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6502 /// Essentially it concatenates V1 and V2, shifts right by some number of
6503 /// elements, and takes the low elements as the result. Note that while this is
6504 /// specified as a *right shift* because x86 is little-endian, it is a *left
6505 /// rotate* of the vector lanes.
6506 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6509 const X86Subtarget *Subtarget,
6510 SelectionDAG &DAG) {
6511 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6513 int NumElts = Mask.size();
6514 int NumLanes = VT.getSizeInBits() / 128;
6515 int NumLaneElts = NumElts / NumLanes;
6517 // We need to detect various ways of spelling a rotation:
6518 // [11, 12, 13, 14, 15, 0, 1, 2]
6519 // [-1, 12, 13, 14, -1, -1, 1, -1]
6520 // [-1, -1, -1, -1, -1, -1, 1, 2]
6521 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6522 // [-1, 4, 5, 6, -1, -1, 9, -1]
6523 // [-1, 4, 5, 6, -1, -1, -1, -1]
6526 for (int l = 0; l < NumElts; l += NumLaneElts) {
6527 for (int i = 0; i < NumLaneElts; ++i) {
6528 if (Mask[l + i] == -1)
6530 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6532 // Get the mod-Size index and lane correct it.
6533 int LaneIdx = (Mask[l + i] % NumElts) - l;
6534 // Make sure it was in this lane.
6535 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6538 // Determine where a rotated vector would have started.
6539 int StartIdx = i - LaneIdx;
6541 // The identity rotation isn't interesting, stop.
6544 // If we found the tail of a vector the rotation must be the missing
6545 // front. If we found the head of a vector, it must be how much of the
6547 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6550 Rotation = CandidateRotation;
6551 else if (Rotation != CandidateRotation)
6552 // The rotations don't match, so we can't match this mask.
6555 // Compute which value this mask is pointing at.
6556 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6558 // Compute which of the two target values this index should be assigned
6559 // to. This reflects whether the high elements are remaining or the low
6560 // elements are remaining.
6561 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6563 // Either set up this value if we've not encountered it before, or check
6564 // that it remains consistent.
6567 else if (TargetV != MaskV)
6568 // This may be a rotation, but it pulls from the inputs in some
6569 // unsupported interleaving.
6574 // Check that we successfully analyzed the mask, and normalize the results.
6575 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6576 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6582 // The actual rotate instruction rotates bytes, so we need to scale the
6583 // rotation based on how many bytes are in the vector lane.
6584 int Scale = 16 / NumLaneElts;
6586 // SSSE3 targets can use the palignr instruction.
6587 if (Subtarget->hasSSSE3()) {
6588 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6589 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6590 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6591 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6593 return DAG.getNode(ISD::BITCAST, DL, VT,
6594 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6595 DAG.getConstant(Rotation * Scale, DL,
6599 assert(VT.getSizeInBits() == 128 &&
6600 "Rotate-based lowering only supports 128-bit lowering!");
6601 assert(Mask.size() <= 16 &&
6602 "Can shuffle at most 16 bytes in a 128-bit vector!");
6604 // Default SSE2 implementation
6605 int LoByteShift = 16 - Rotation * Scale;
6606 int HiByteShift = Rotation * Scale;
6608 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6609 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6610 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6612 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6613 DAG.getConstant(LoByteShift, DL, MVT::i8));
6614 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6615 DAG.getConstant(HiByteShift, DL, MVT::i8));
6616 return DAG.getNode(ISD::BITCAST, DL, VT,
6617 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6620 /// \brief Compute whether each element of a shuffle is zeroable.
6622 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6623 /// Either it is an undef element in the shuffle mask, the element of the input
6624 /// referenced is undef, or the element of the input referenced is known to be
6625 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6626 /// as many lanes with this technique as possible to simplify the remaining
6628 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6629 SDValue V1, SDValue V2) {
6630 SmallBitVector Zeroable(Mask.size(), false);
6632 while (V1.getOpcode() == ISD::BITCAST)
6633 V1 = V1->getOperand(0);
6634 while (V2.getOpcode() == ISD::BITCAST)
6635 V2 = V2->getOperand(0);
6637 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6638 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6640 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6642 // Handle the easy cases.
6643 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6648 // If this is an index into a build_vector node (which has the same number
6649 // of elements), dig out the input value and use it.
6650 SDValue V = M < Size ? V1 : V2;
6651 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6654 SDValue Input = V.getOperand(M % Size);
6655 // The UNDEF opcode check really should be dead code here, but not quite
6656 // worth asserting on (it isn't invalid, just unexpected).
6657 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6664 /// \brief Try to emit a bitmask instruction for a shuffle.
6666 /// This handles cases where we can model a blend exactly as a bitmask due to
6667 /// one of the inputs being zeroable.
6668 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6669 SDValue V2, ArrayRef<int> Mask,
6670 SelectionDAG &DAG) {
6671 MVT EltVT = VT.getScalarType();
6672 int NumEltBits = EltVT.getSizeInBits();
6673 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6674 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6675 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6677 if (EltVT.isFloatingPoint()) {
6678 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6679 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6681 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6682 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6684 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6687 if (Mask[i] % Size != i)
6688 return SDValue(); // Not a blend.
6690 V = Mask[i] < Size ? V1 : V2;
6691 else if (V != (Mask[i] < Size ? V1 : V2))
6692 return SDValue(); // Can only let one input through the mask.
6694 VMaskOps[i] = AllOnes;
6697 return SDValue(); // No non-zeroable elements!
6699 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6700 V = DAG.getNode(VT.isFloatingPoint()
6701 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6706 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6708 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6709 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6710 /// matches elements from one of the input vectors shuffled to the left or
6711 /// right with zeroable elements 'shifted in'. It handles both the strictly
6712 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6715 /// PSHL : (little-endian) left bit shift.
6716 /// [ zz, 0, zz, 2 ]
6717 /// [ -1, 4, zz, -1 ]
6718 /// PSRL : (little-endian) right bit shift.
6720 /// [ -1, -1, 7, zz]
6721 /// PSLLDQ : (little-endian) left byte shift
6722 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6723 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6724 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6725 /// PSRLDQ : (little-endian) right byte shift
6726 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6727 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6728 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6729 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6730 SDValue V2, ArrayRef<int> Mask,
6731 SelectionDAG &DAG) {
6732 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6734 int Size = Mask.size();
6735 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6737 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6738 for (int i = 0; i < Size; i += Scale)
6739 for (int j = 0; j < Shift; ++j)
6740 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6746 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6747 for (int i = 0; i != Size; i += Scale) {
6748 unsigned Pos = Left ? i + Shift : i;
6749 unsigned Low = Left ? i : i + Shift;
6750 unsigned Len = Scale - Shift;
6751 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6752 Low + (V == V1 ? 0 : Size)))
6756 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6757 bool ByteShift = ShiftEltBits > 64;
6758 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6759 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6760 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6762 // Normalize the scale for byte shifts to still produce an i64 element
6764 Scale = ByteShift ? Scale / 2 : Scale;
6766 // We need to round trip through the appropriate type for the shift.
6767 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6768 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6769 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6770 "Illegal integer vector type");
6771 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6773 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6774 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6775 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6778 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6779 // keep doubling the size of the integer elements up to that. We can
6780 // then shift the elements of the integer vector by whole multiples of
6781 // their width within the elements of the larger integer vector. Test each
6782 // multiple to see if we can find a match with the moved element indices
6783 // and that the shifted in elements are all zeroable.
6784 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6785 for (int Shift = 1; Shift != Scale; ++Shift)
6786 for (bool Left : {true, false})
6787 if (CheckZeros(Shift, Scale, Left))
6788 for (SDValue V : {V1, V2})
6789 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6796 /// \brief Lower a vector shuffle as a zero or any extension.
6798 /// Given a specific number of elements, element bit width, and extension
6799 /// stride, produce either a zero or any extension based on the available
6800 /// features of the subtarget.
6801 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6802 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6803 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6804 assert(Scale > 1 && "Need a scale to extend.");
6805 int NumElements = VT.getVectorNumElements();
6806 int EltBits = VT.getScalarSizeInBits();
6807 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6808 "Only 8, 16, and 32 bit elements can be extended.");
6809 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6811 // Found a valid zext mask! Try various lowering strategies based on the
6812 // input type and available ISA extensions.
6813 if (Subtarget->hasSSE41()) {
6814 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6815 NumElements / Scale);
6816 return DAG.getNode(ISD::BITCAST, DL, VT,
6817 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6820 // For any extends we can cheat for larger element sizes and use shuffle
6821 // instructions that can fold with a load and/or copy.
6822 if (AnyExt && EltBits == 32) {
6823 int PSHUFDMask[4] = {0, -1, 1, -1};
6825 ISD::BITCAST, DL, VT,
6826 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6827 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6828 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6830 if (AnyExt && EltBits == 16 && Scale > 2) {
6831 int PSHUFDMask[4] = {0, -1, 0, -1};
6832 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6833 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6834 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6835 int PSHUFHWMask[4] = {1, -1, -1, -1};
6837 ISD::BITCAST, DL, VT,
6838 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6839 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6840 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6843 // If this would require more than 2 unpack instructions to expand, use
6844 // pshufb when available. We can only use more than 2 unpack instructions
6845 // when zero extending i8 elements which also makes it easier to use pshufb.
6846 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6847 assert(NumElements == 16 && "Unexpected byte vector width!");
6848 SDValue PSHUFBMask[16];
6849 for (int i = 0; i < 16; ++i)
6851 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6852 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6853 return DAG.getNode(ISD::BITCAST, DL, VT,
6854 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6855 DAG.getNode(ISD::BUILD_VECTOR, DL,
6856 MVT::v16i8, PSHUFBMask)));
6859 // Otherwise emit a sequence of unpacks.
6861 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6862 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6863 : getZeroVector(InputVT, Subtarget, DAG, DL);
6864 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6865 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6869 } while (Scale > 1);
6870 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6873 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6875 /// This routine will try to do everything in its power to cleverly lower
6876 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6877 /// check for the profitability of this lowering, it tries to aggressively
6878 /// match this pattern. It will use all of the micro-architectural details it
6879 /// can to emit an efficient lowering. It handles both blends with all-zero
6880 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6881 /// masking out later).
6883 /// The reason we have dedicated lowering for zext-style shuffles is that they
6884 /// are both incredibly common and often quite performance sensitive.
6885 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6886 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6887 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6888 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6890 int Bits = VT.getSizeInBits();
6891 int NumElements = VT.getVectorNumElements();
6892 assert(VT.getScalarSizeInBits() <= 32 &&
6893 "Exceeds 32-bit integer zero extension limit");
6894 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6896 // Define a helper function to check a particular ext-scale and lower to it if
6898 auto Lower = [&](int Scale) -> SDValue {
6901 for (int i = 0; i < NumElements; ++i) {
6903 continue; // Valid anywhere but doesn't tell us anything.
6904 if (i % Scale != 0) {
6905 // Each of the extended elements need to be zeroable.
6909 // We no longer are in the anyext case.
6914 // Each of the base elements needs to be consecutive indices into the
6915 // same input vector.
6916 SDValue V = Mask[i] < NumElements ? V1 : V2;
6919 else if (InputV != V)
6920 return SDValue(); // Flip-flopping inputs.
6922 if (Mask[i] % NumElements != i / Scale)
6923 return SDValue(); // Non-consecutive strided elements.
6926 // If we fail to find an input, we have a zero-shuffle which should always
6927 // have already been handled.
6928 // FIXME: Maybe handle this here in case during blending we end up with one?
6932 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6933 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6936 // The widest scale possible for extending is to a 64-bit integer.
6937 assert(Bits % 64 == 0 &&
6938 "The number of bits in a vector must be divisible by 64 on x86!");
6939 int NumExtElements = Bits / 64;
6941 // Each iteration, try extending the elements half as much, but into twice as
6943 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6944 assert(NumElements % NumExtElements == 0 &&
6945 "The input vector size must be divisible by the extended size.");
6946 if (SDValue V = Lower(NumElements / NumExtElements))
6950 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6954 // Returns one of the source operands if the shuffle can be reduced to a
6955 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6956 auto CanZExtLowHalf = [&]() {
6957 for (int i = NumElements / 2; i != NumElements; ++i)
6960 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6962 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6967 if (SDValue V = CanZExtLowHalf()) {
6968 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6969 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6970 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6973 // No viable ext lowering found.
6977 /// \brief Try to get a scalar value for a specific element of a vector.
6979 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6980 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6981 SelectionDAG &DAG) {
6982 MVT VT = V.getSimpleValueType();
6983 MVT EltVT = VT.getVectorElementType();
6984 while (V.getOpcode() == ISD::BITCAST)
6985 V = V.getOperand(0);
6986 // If the bitcasts shift the element size, we can't extract an equivalent
6988 MVT NewVT = V.getSimpleValueType();
6989 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
6992 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6993 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
6994 // Ensure the scalar operand is the same size as the destination.
6995 // FIXME: Add support for scalar truncation where possible.
6996 SDValue S = V.getOperand(Idx);
6997 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
6998 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7004 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7006 /// This is particularly important because the set of instructions varies
7007 /// significantly based on whether the operand is a load or not.
7008 static bool isShuffleFoldableLoad(SDValue V) {
7009 while (V.getOpcode() == ISD::BITCAST)
7010 V = V.getOperand(0);
7012 return ISD::isNON_EXTLoad(V.getNode());
7015 /// \brief Try to lower insertion of a single element into a zero vector.
7017 /// This is a common pattern that we have especially efficient patterns to lower
7018 /// across all subtarget feature sets.
7019 static SDValue lowerVectorShuffleAsElementInsertion(
7020 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7021 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7022 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7024 MVT EltVT = VT.getVectorElementType();
7026 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7027 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7029 bool IsV1Zeroable = true;
7030 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7031 if (i != V2Index && !Zeroable[i]) {
7032 IsV1Zeroable = false;
7036 // Check for a single input from a SCALAR_TO_VECTOR node.
7037 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7038 // all the smarts here sunk into that routine. However, the current
7039 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7040 // vector shuffle lowering is dead.
7041 if (SDValue V2S = getScalarValueForVectorElement(
7042 V2, Mask[V2Index] - Mask.size(), DAG)) {
7043 // We need to zext the scalar if it is smaller than an i32.
7044 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7045 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7046 // Using zext to expand a narrow element won't work for non-zero
7051 // Zero-extend directly to i32.
7053 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7055 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7056 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7057 EltVT == MVT::i16) {
7058 // Either not inserting from the low element of the input or the input
7059 // element size is too small to use VZEXT_MOVL to clear the high bits.
7063 if (!IsV1Zeroable) {
7064 // If V1 can't be treated as a zero vector we have fewer options to lower
7065 // this. We can't support integer vectors or non-zero targets cheaply, and
7066 // the V1 elements can't be permuted in any way.
7067 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7068 if (!VT.isFloatingPoint() || V2Index != 0)
7070 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7071 V1Mask[V2Index] = -1;
7072 if (!isNoopShuffleMask(V1Mask))
7074 // This is essentially a special case blend operation, but if we have
7075 // general purpose blend operations, they are always faster. Bail and let
7076 // the rest of the lowering handle these as blends.
7077 if (Subtarget->hasSSE41())
7080 // Otherwise, use MOVSD or MOVSS.
7081 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7082 "Only two types of floating point element types to handle!");
7083 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7087 // This lowering only works for the low element with floating point vectors.
7088 if (VT.isFloatingPoint() && V2Index != 0)
7091 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7093 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7096 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7097 // the desired position. Otherwise it is more efficient to do a vector
7098 // shift left. We know that we can do a vector shift left because all
7099 // the inputs are zero.
7100 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7101 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7102 V2Shuffle[V2Index] = 0;
7103 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7105 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7107 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7109 V2Index * EltVT.getSizeInBits()/8, DL,
7110 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7111 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7117 /// \brief Try to lower broadcast of a single element.
7119 /// For convenience, this code also bundles all of the subtarget feature set
7120 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7121 /// a convenient way to factor it out.
7122 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7124 const X86Subtarget *Subtarget,
7125 SelectionDAG &DAG) {
7126 if (!Subtarget->hasAVX())
7128 if (VT.isInteger() && !Subtarget->hasAVX2())
7131 // Check that the mask is a broadcast.
7132 int BroadcastIdx = -1;
7134 if (M >= 0 && BroadcastIdx == -1)
7136 else if (M >= 0 && M != BroadcastIdx)
7139 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7140 "a sorted mask where the broadcast "
7143 // Go up the chain of (vector) values to find a scalar load that we can
7144 // combine with the broadcast.
7146 switch (V.getOpcode()) {
7147 case ISD::CONCAT_VECTORS: {
7148 int OperandSize = Mask.size() / V.getNumOperands();
7149 V = V.getOperand(BroadcastIdx / OperandSize);
7150 BroadcastIdx %= OperandSize;
7154 case ISD::INSERT_SUBVECTOR: {
7155 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7156 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7160 int BeginIdx = (int)ConstantIdx->getZExtValue();
7162 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7163 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7164 BroadcastIdx -= BeginIdx;
7175 // Check if this is a broadcast of a scalar. We special case lowering
7176 // for scalars so that we can more effectively fold with loads.
7177 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7178 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7179 V = V.getOperand(BroadcastIdx);
7181 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7182 // Only AVX2 has register broadcasts.
7183 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7185 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7186 // We can't broadcast from a vector register without AVX2, and we can only
7187 // broadcast from the zero-element of a vector register.
7191 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7194 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7195 // INSERTPS when the V1 elements are already in the correct locations
7196 // because otherwise we can just always use two SHUFPS instructions which
7197 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7198 // perform INSERTPS if a single V1 element is out of place and all V2
7199 // elements are zeroable.
7200 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7202 SelectionDAG &DAG) {
7203 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7204 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7205 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7206 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7208 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7211 int V1DstIndex = -1;
7212 int V2DstIndex = -1;
7213 bool V1UsedInPlace = false;
7215 for (int i = 0; i < 4; ++i) {
7216 // Synthesize a zero mask from the zeroable elements (includes undefs).
7222 // Flag if we use any V1 inputs in place.
7224 V1UsedInPlace = true;
7228 // We can only insert a single non-zeroable element.
7229 if (V1DstIndex != -1 || V2DstIndex != -1)
7233 // V1 input out of place for insertion.
7236 // V2 input for insertion.
7241 // Don't bother if we have no (non-zeroable) element for insertion.
7242 if (V1DstIndex == -1 && V2DstIndex == -1)
7245 // Determine element insertion src/dst indices. The src index is from the
7246 // start of the inserted vector, not the start of the concatenated vector.
7247 unsigned V2SrcIndex = 0;
7248 if (V1DstIndex != -1) {
7249 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7250 // and don't use the original V2 at all.
7251 V2SrcIndex = Mask[V1DstIndex];
7252 V2DstIndex = V1DstIndex;
7255 V2SrcIndex = Mask[V2DstIndex] - 4;
7258 // If no V1 inputs are used in place, then the result is created only from
7259 // the zero mask and the V2 insertion - so remove V1 dependency.
7261 V1 = DAG.getUNDEF(MVT::v4f32);
7263 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7264 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7266 // Insert the V2 element into the desired position.
7268 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7269 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7272 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7273 /// UNPCK instruction.
7275 /// This specifically targets cases where we end up with alternating between
7276 /// the two inputs, and so can permute them into something that feeds a single
7277 /// UNPCK instruction. Note that this routine only targets integer vectors
7278 /// because for floating point vectors we have a generalized SHUFPS lowering
7279 /// strategy that handles everything that doesn't *exactly* match an unpack,
7280 /// making this clever lowering unnecessary.
7281 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7282 SDValue V2, ArrayRef<int> Mask,
7283 SelectionDAG &DAG) {
7284 assert(!VT.isFloatingPoint() &&
7285 "This routine only supports integer vectors.");
7286 assert(!isSingleInputShuffleMask(Mask) &&
7287 "This routine should only be used when blending two inputs.");
7288 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7290 int Size = Mask.size();
7292 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7293 return M >= 0 && M % Size < Size / 2;
7295 int NumHiInputs = std::count_if(
7296 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7298 bool UnpackLo = NumLoInputs >= NumHiInputs;
7300 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7301 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7302 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7304 for (int i = 0; i < Size; ++i) {
7308 // Each element of the unpack contains Scale elements from this mask.
7309 int UnpackIdx = i / Scale;
7311 // We only handle the case where V1 feeds the first slots of the unpack.
7312 // We rely on canonicalization to ensure this is the case.
7313 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7316 // Setup the mask for this input. The indexing is tricky as we have to
7317 // handle the unpack stride.
7318 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7319 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7323 // If we will have to shuffle both inputs to use the unpack, check whether
7324 // we can just unpack first and shuffle the result. If so, skip this unpack.
7325 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7326 !isNoopShuffleMask(V2Mask))
7329 // Shuffle the inputs into place.
7330 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7331 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7333 // Cast the inputs to the type we will use to unpack them.
7334 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7335 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7337 // Unpack the inputs and cast the result back to the desired type.
7338 return DAG.getNode(ISD::BITCAST, DL, VT,
7339 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7340 DL, UnpackVT, V1, V2));
7343 // We try each unpack from the largest to the smallest to try and find one
7344 // that fits this mask.
7345 int OrigNumElements = VT.getVectorNumElements();
7346 int OrigScalarSize = VT.getScalarSizeInBits();
7347 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7348 int Scale = ScalarSize / OrigScalarSize;
7349 int NumElements = OrigNumElements / Scale;
7350 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7351 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7355 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7357 if (NumLoInputs == 0 || NumHiInputs == 0) {
7358 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7359 "We have to have *some* inputs!");
7360 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7362 // FIXME: We could consider the total complexity of the permute of each
7363 // possible unpacking. Or at the least we should consider how many
7364 // half-crossings are created.
7365 // FIXME: We could consider commuting the unpacks.
7367 SmallVector<int, 32> PermMask;
7368 PermMask.assign(Size, -1);
7369 for (int i = 0; i < Size; ++i) {
7373 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7376 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7378 return DAG.getVectorShuffle(
7379 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7381 DAG.getUNDEF(VT), PermMask);
7387 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7389 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7390 /// support for floating point shuffles but not integer shuffles. These
7391 /// instructions will incur a domain crossing penalty on some chips though so
7392 /// it is better to avoid lowering through this for integer vectors where
7394 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7395 const X86Subtarget *Subtarget,
7396 SelectionDAG &DAG) {
7398 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7399 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7400 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7401 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7402 ArrayRef<int> Mask = SVOp->getMask();
7403 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7405 if (isSingleInputShuffleMask(Mask)) {
7406 // Use low duplicate instructions for masks that match their pattern.
7407 if (Subtarget->hasSSE3())
7408 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7409 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7411 // Straight shuffle of a single input vector. Simulate this by using the
7412 // single input as both of the "inputs" to this instruction..
7413 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7415 if (Subtarget->hasAVX()) {
7416 // If we have AVX, we can use VPERMILPS which will allow folding a load
7417 // into the shuffle.
7418 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7419 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7422 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7423 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7425 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7426 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7428 // If we have a single input, insert that into V1 if we can do so cheaply.
7429 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7430 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7431 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7433 // Try inverting the insertion since for v2 masks it is easy to do and we
7434 // can't reliably sort the mask one way or the other.
7435 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7436 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7437 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7438 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7442 // Try to use one of the special instruction patterns to handle two common
7443 // blend patterns if a zero-blend above didn't work.
7444 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7445 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7446 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7447 // We can either use a special instruction to load over the low double or
7448 // to move just the low double.
7450 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7452 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7454 if (Subtarget->hasSSE41())
7455 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7459 // Use dedicated unpack instructions for masks that match their pattern.
7460 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7461 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7462 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7463 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7465 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7466 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7467 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7470 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7472 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7473 /// the integer unit to minimize domain crossing penalties. However, for blends
7474 /// it falls back to the floating point shuffle operation with appropriate bit
7476 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7477 const X86Subtarget *Subtarget,
7478 SelectionDAG &DAG) {
7480 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7481 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7482 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7483 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7484 ArrayRef<int> Mask = SVOp->getMask();
7485 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7487 if (isSingleInputShuffleMask(Mask)) {
7488 // Check for being able to broadcast a single element.
7489 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7490 Mask, Subtarget, DAG))
7493 // Straight shuffle of a single input vector. For everything from SSE2
7494 // onward this has a single fast instruction with no scary immediates.
7495 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7496 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7497 int WidenedMask[4] = {
7498 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7499 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7501 ISD::BITCAST, DL, MVT::v2i64,
7502 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7503 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7505 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7506 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7507 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7508 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7510 // If we have a blend of two PACKUS operations an the blend aligns with the
7511 // low and half halves, we can just merge the PACKUS operations. This is
7512 // particularly important as it lets us merge shuffles that this routine itself
7514 auto GetPackNode = [](SDValue V) {
7515 while (V.getOpcode() == ISD::BITCAST)
7516 V = V.getOperand(0);
7518 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7520 if (SDValue V1Pack = GetPackNode(V1))
7521 if (SDValue V2Pack = GetPackNode(V2))
7522 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7523 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7524 Mask[0] == 0 ? V1Pack.getOperand(0)
7525 : V1Pack.getOperand(1),
7526 Mask[1] == 2 ? V2Pack.getOperand(0)
7527 : V2Pack.getOperand(1)));
7529 // Try to use shift instructions.
7531 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7534 // When loading a scalar and then shuffling it into a vector we can often do
7535 // the insertion cheaply.
7536 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7537 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7539 // Try inverting the insertion since for v2 masks it is easy to do and we
7540 // can't reliably sort the mask one way or the other.
7541 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7542 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7543 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7546 // We have different paths for blend lowering, but they all must use the
7547 // *exact* same predicate.
7548 bool IsBlendSupported = Subtarget->hasSSE41();
7549 if (IsBlendSupported)
7550 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7554 // Use dedicated unpack instructions for masks that match their pattern.
7555 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7556 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7557 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7558 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7560 // Try to use byte rotation instructions.
7561 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7562 if (Subtarget->hasSSSE3())
7563 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7564 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7567 // If we have direct support for blends, we should lower by decomposing into
7568 // a permute. That will be faster than the domain cross.
7569 if (IsBlendSupported)
7570 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7573 // We implement this with SHUFPD which is pretty lame because it will likely
7574 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7575 // However, all the alternatives are still more cycles and newer chips don't
7576 // have this problem. It would be really nice if x86 had better shuffles here.
7577 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7578 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7579 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7580 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7583 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7585 /// This is used to disable more specialized lowerings when the shufps lowering
7586 /// will happen to be efficient.
7587 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7588 // This routine only handles 128-bit shufps.
7589 assert(Mask.size() == 4 && "Unsupported mask size!");
7591 // To lower with a single SHUFPS we need to have the low half and high half
7592 // each requiring a single input.
7593 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7595 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7601 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7603 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7604 /// It makes no assumptions about whether this is the *best* lowering, it simply
7606 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7607 ArrayRef<int> Mask, SDValue V1,
7608 SDValue V2, SelectionDAG &DAG) {
7609 SDValue LowV = V1, HighV = V2;
7610 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7613 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7615 if (NumV2Elements == 1) {
7617 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7620 // Compute the index adjacent to V2Index and in the same half by toggling
7622 int V2AdjIndex = V2Index ^ 1;
7624 if (Mask[V2AdjIndex] == -1) {
7625 // Handles all the cases where we have a single V2 element and an undef.
7626 // This will only ever happen in the high lanes because we commute the
7627 // vector otherwise.
7629 std::swap(LowV, HighV);
7630 NewMask[V2Index] -= 4;
7632 // Handle the case where the V2 element ends up adjacent to a V1 element.
7633 // To make this work, blend them together as the first step.
7634 int V1Index = V2AdjIndex;
7635 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7636 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7637 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7639 // Now proceed to reconstruct the final blend as we have the necessary
7640 // high or low half formed.
7647 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7648 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7650 } else if (NumV2Elements == 2) {
7651 if (Mask[0] < 4 && Mask[1] < 4) {
7652 // Handle the easy case where we have V1 in the low lanes and V2 in the
7656 } else if (Mask[2] < 4 && Mask[3] < 4) {
7657 // We also handle the reversed case because this utility may get called
7658 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7659 // arrange things in the right direction.
7665 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7666 // trying to place elements directly, just blend them and set up the final
7667 // shuffle to place them.
7669 // The first two blend mask elements are for V1, the second two are for
7671 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7672 Mask[2] < 4 ? Mask[2] : Mask[3],
7673 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7674 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7675 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7676 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7678 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7681 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7682 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7683 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7684 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7687 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7688 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7691 /// \brief Lower 4-lane 32-bit floating point shuffles.
7693 /// Uses instructions exclusively from the floating point unit to minimize
7694 /// domain crossing penalties, as these are sufficient to implement all v4f32
7696 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7697 const X86Subtarget *Subtarget,
7698 SelectionDAG &DAG) {
7700 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7701 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7702 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7704 ArrayRef<int> Mask = SVOp->getMask();
7705 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7708 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7710 if (NumV2Elements == 0) {
7711 // Check for being able to broadcast a single element.
7712 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7713 Mask, Subtarget, DAG))
7716 // Use even/odd duplicate instructions for masks that match their pattern.
7717 if (Subtarget->hasSSE3()) {
7718 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7719 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7720 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7721 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7724 if (Subtarget->hasAVX()) {
7725 // If we have AVX, we can use VPERMILPS which will allow folding a load
7726 // into the shuffle.
7727 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7728 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7731 // Otherwise, use a straight shuffle of a single input vector. We pass the
7732 // input vector to both operands to simulate this with a SHUFPS.
7733 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7734 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7737 // There are special ways we can lower some single-element blends. However, we
7738 // have custom ways we can lower more complex single-element blends below that
7739 // we defer to if both this and BLENDPS fail to match, so restrict this to
7740 // when the V2 input is targeting element 0 of the mask -- that is the fast
7742 if (NumV2Elements == 1 && Mask[0] >= 4)
7743 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7744 Mask, Subtarget, DAG))
7747 if (Subtarget->hasSSE41()) {
7748 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7752 // Use INSERTPS if we can complete the shuffle efficiently.
7753 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7756 if (!isSingleSHUFPSMask(Mask))
7757 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7758 DL, MVT::v4f32, V1, V2, Mask, DAG))
7762 // Use dedicated unpack instructions for masks that match their pattern.
7763 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7764 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7765 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7766 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7767 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7768 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7769 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7770 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7772 // Otherwise fall back to a SHUFPS lowering strategy.
7773 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7776 /// \brief Lower 4-lane i32 vector shuffles.
7778 /// We try to handle these with integer-domain shuffles where we can, but for
7779 /// blends we use the floating point domain blend instructions.
7780 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7781 const X86Subtarget *Subtarget,
7782 SelectionDAG &DAG) {
7784 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7785 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7786 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7787 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7788 ArrayRef<int> Mask = SVOp->getMask();
7789 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7791 // Whenever we can lower this as a zext, that instruction is strictly faster
7792 // than any alternative. It also allows us to fold memory operands into the
7793 // shuffle in many cases.
7794 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7795 Mask, Subtarget, DAG))
7799 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7801 if (NumV2Elements == 0) {
7802 // Check for being able to broadcast a single element.
7803 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7804 Mask, Subtarget, DAG))
7807 // Straight shuffle of a single input vector. For everything from SSE2
7808 // onward this has a single fast instruction with no scary immediates.
7809 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7810 // but we aren't actually going to use the UNPCK instruction because doing
7811 // so prevents folding a load into this instruction or making a copy.
7812 const int UnpackLoMask[] = {0, 0, 1, 1};
7813 const int UnpackHiMask[] = {2, 2, 3, 3};
7814 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7815 Mask = UnpackLoMask;
7816 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7817 Mask = UnpackHiMask;
7819 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7820 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7823 // Try to use shift instructions.
7825 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7828 // There are special ways we can lower some single-element blends.
7829 if (NumV2Elements == 1)
7830 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7831 Mask, Subtarget, DAG))
7834 // We have different paths for blend lowering, but they all must use the
7835 // *exact* same predicate.
7836 bool IsBlendSupported = Subtarget->hasSSE41();
7837 if (IsBlendSupported)
7838 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7842 if (SDValue Masked =
7843 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7846 // Use dedicated unpack instructions for masks that match their pattern.
7847 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7848 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7849 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7850 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7851 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7852 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7853 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7854 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7856 // Try to use byte rotation instructions.
7857 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7858 if (Subtarget->hasSSSE3())
7859 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7860 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7863 // If we have direct support for blends, we should lower by decomposing into
7864 // a permute. That will be faster than the domain cross.
7865 if (IsBlendSupported)
7866 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7869 // Try to lower by permuting the inputs into an unpack instruction.
7870 if (SDValue Unpack =
7871 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7874 // We implement this with SHUFPS because it can blend from two vectors.
7875 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7876 // up the inputs, bypassing domain shift penalties that we would encur if we
7877 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7879 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7880 DAG.getVectorShuffle(
7882 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7883 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7886 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7887 /// shuffle lowering, and the most complex part.
7889 /// The lowering strategy is to try to form pairs of input lanes which are
7890 /// targeted at the same half of the final vector, and then use a dword shuffle
7891 /// to place them onto the right half, and finally unpack the paired lanes into
7892 /// their final position.
7894 /// The exact breakdown of how to form these dword pairs and align them on the
7895 /// correct sides is really tricky. See the comments within the function for
7896 /// more of the details.
7898 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7899 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7900 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7901 /// vector, form the analogous 128-bit 8-element Mask.
7902 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7903 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7904 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7905 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7906 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7908 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7909 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7910 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7912 SmallVector<int, 4> LoInputs;
7913 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7914 [](int M) { return M >= 0; });
7915 std::sort(LoInputs.begin(), LoInputs.end());
7916 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7917 SmallVector<int, 4> HiInputs;
7918 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7919 [](int M) { return M >= 0; });
7920 std::sort(HiInputs.begin(), HiInputs.end());
7921 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7923 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7924 int NumHToL = LoInputs.size() - NumLToL;
7926 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7927 int NumHToH = HiInputs.size() - NumLToH;
7928 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7929 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7930 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7931 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7933 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7934 // such inputs we can swap two of the dwords across the half mark and end up
7935 // with <=2 inputs to each half in each half. Once there, we can fall through
7936 // to the generic code below. For example:
7938 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7939 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7941 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7942 // and an existing 2-into-2 on the other half. In this case we may have to
7943 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7944 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7945 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7946 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7947 // half than the one we target for fixing) will be fixed when we re-enter this
7948 // path. We will also combine away any sequence of PSHUFD instructions that
7949 // result into a single instruction. Here is an example of the tricky case:
7951 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7952 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7954 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7956 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7957 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7959 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7960 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7962 // The result is fine to be handled by the generic logic.
7963 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7964 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7965 int AOffset, int BOffset) {
7966 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7967 "Must call this with A having 3 or 1 inputs from the A half.");
7968 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7969 "Must call this with B having 1 or 3 inputs from the B half.");
7970 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7971 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7973 // Compute the index of dword with only one word among the three inputs in
7974 // a half by taking the sum of the half with three inputs and subtracting
7975 // the sum of the actual three inputs. The difference is the remaining
7978 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7979 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7980 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7981 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7982 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7983 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7984 int TripleNonInputIdx =
7985 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7986 TripleDWord = TripleNonInputIdx / 2;
7988 // We use xor with one to compute the adjacent DWord to whichever one the
7990 OneInputDWord = (OneInput / 2) ^ 1;
7992 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7993 // and BToA inputs. If there is also such a problem with the BToB and AToB
7994 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7995 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7996 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7997 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7998 // Compute how many inputs will be flipped by swapping these DWords. We
8000 // to balance this to ensure we don't form a 3-1 shuffle in the other
8002 int NumFlippedAToBInputs =
8003 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8004 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8005 int NumFlippedBToBInputs =
8006 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8007 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8008 if ((NumFlippedAToBInputs == 1 &&
8009 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8010 (NumFlippedBToBInputs == 1 &&
8011 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8012 // We choose whether to fix the A half or B half based on whether that
8013 // half has zero flipped inputs. At zero, we may not be able to fix it
8014 // with that half. We also bias towards fixing the B half because that
8015 // will more commonly be the high half, and we have to bias one way.
8016 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8017 ArrayRef<int> Inputs) {
8018 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8019 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8020 PinnedIdx ^ 1) != Inputs.end();
8021 // Determine whether the free index is in the flipped dword or the
8022 // unflipped dword based on where the pinned index is. We use this bit
8023 // in an xor to conditionally select the adjacent dword.
8024 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8025 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8026 FixFreeIdx) != Inputs.end();
8027 if (IsFixIdxInput == IsFixFreeIdxInput)
8029 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8030 FixFreeIdx) != Inputs.end();
8031 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8032 "We need to be changing the number of flipped inputs!");
8033 int PSHUFHalfMask[] = {0, 1, 2, 3};
8034 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8035 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8037 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8040 if (M != -1 && M == FixIdx)
8042 else if (M != -1 && M == FixFreeIdx)
8045 if (NumFlippedBToBInputs != 0) {
8047 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8048 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8050 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8052 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8053 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8058 int PSHUFDMask[] = {0, 1, 2, 3};
8059 PSHUFDMask[ADWord] = BDWord;
8060 PSHUFDMask[BDWord] = ADWord;
8061 V = DAG.getNode(ISD::BITCAST, DL, VT,
8062 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8063 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8064 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8067 // Adjust the mask to match the new locations of A and B.
8069 if (M != -1 && M/2 == ADWord)
8070 M = 2 * BDWord + M % 2;
8071 else if (M != -1 && M/2 == BDWord)
8072 M = 2 * ADWord + M % 2;
8074 // Recurse back into this routine to re-compute state now that this isn't
8075 // a 3 and 1 problem.
8076 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8079 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8080 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8081 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8082 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8084 // At this point there are at most two inputs to the low and high halves from
8085 // each half. That means the inputs can always be grouped into dwords and
8086 // those dwords can then be moved to the correct half with a dword shuffle.
8087 // We use at most one low and one high word shuffle to collect these paired
8088 // inputs into dwords, and finally a dword shuffle to place them.
8089 int PSHUFLMask[4] = {-1, -1, -1, -1};
8090 int PSHUFHMask[4] = {-1, -1, -1, -1};
8091 int PSHUFDMask[4] = {-1, -1, -1, -1};
8093 // First fix the masks for all the inputs that are staying in their
8094 // original halves. This will then dictate the targets of the cross-half
8096 auto fixInPlaceInputs =
8097 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8098 MutableArrayRef<int> SourceHalfMask,
8099 MutableArrayRef<int> HalfMask, int HalfOffset) {
8100 if (InPlaceInputs.empty())
8102 if (InPlaceInputs.size() == 1) {
8103 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8104 InPlaceInputs[0] - HalfOffset;
8105 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8108 if (IncomingInputs.empty()) {
8109 // Just fix all of the in place inputs.
8110 for (int Input : InPlaceInputs) {
8111 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8112 PSHUFDMask[Input / 2] = Input / 2;
8117 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8118 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8119 InPlaceInputs[0] - HalfOffset;
8120 // Put the second input next to the first so that they are packed into
8121 // a dword. We find the adjacent index by toggling the low bit.
8122 int AdjIndex = InPlaceInputs[0] ^ 1;
8123 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8124 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8125 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8127 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8128 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8130 // Now gather the cross-half inputs and place them into a free dword of
8131 // their target half.
8132 // FIXME: This operation could almost certainly be simplified dramatically to
8133 // look more like the 3-1 fixing operation.
8134 auto moveInputsToRightHalf = [&PSHUFDMask](
8135 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8136 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8137 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8139 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8140 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8142 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8144 int LowWord = Word & ~1;
8145 int HighWord = Word | 1;
8146 return isWordClobbered(SourceHalfMask, LowWord) ||
8147 isWordClobbered(SourceHalfMask, HighWord);
8150 if (IncomingInputs.empty())
8153 if (ExistingInputs.empty()) {
8154 // Map any dwords with inputs from them into the right half.
8155 for (int Input : IncomingInputs) {
8156 // If the source half mask maps over the inputs, turn those into
8157 // swaps and use the swapped lane.
8158 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8159 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8160 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8161 Input - SourceOffset;
8162 // We have to swap the uses in our half mask in one sweep.
8163 for (int &M : HalfMask)
8164 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8166 else if (M == Input)
8167 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8169 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8170 Input - SourceOffset &&
8171 "Previous placement doesn't match!");
8173 // Note that this correctly re-maps both when we do a swap and when
8174 // we observe the other side of the swap above. We rely on that to
8175 // avoid swapping the members of the input list directly.
8176 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8179 // Map the input's dword into the correct half.
8180 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8181 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8183 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8185 "Previous placement doesn't match!");
8188 // And just directly shift any other-half mask elements to be same-half
8189 // as we will have mirrored the dword containing the element into the
8190 // same position within that half.
8191 for (int &M : HalfMask)
8192 if (M >= SourceOffset && M < SourceOffset + 4) {
8193 M = M - SourceOffset + DestOffset;
8194 assert(M >= 0 && "This should never wrap below zero!");
8199 // Ensure we have the input in a viable dword of its current half. This
8200 // is particularly tricky because the original position may be clobbered
8201 // by inputs being moved and *staying* in that half.
8202 if (IncomingInputs.size() == 1) {
8203 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8204 int InputFixed = std::find(std::begin(SourceHalfMask),
8205 std::end(SourceHalfMask), -1) -
8206 std::begin(SourceHalfMask) + SourceOffset;
8207 SourceHalfMask[InputFixed - SourceOffset] =
8208 IncomingInputs[0] - SourceOffset;
8209 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8211 IncomingInputs[0] = InputFixed;
8213 } else if (IncomingInputs.size() == 2) {
8214 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8215 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8216 // We have two non-adjacent or clobbered inputs we need to extract from
8217 // the source half. To do this, we need to map them into some adjacent
8218 // dword slot in the source mask.
8219 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8220 IncomingInputs[1] - SourceOffset};
8222 // If there is a free slot in the source half mask adjacent to one of
8223 // the inputs, place the other input in it. We use (Index XOR 1) to
8224 // compute an adjacent index.
8225 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8226 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8227 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8228 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8229 InputsFixed[1] = InputsFixed[0] ^ 1;
8230 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8231 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8232 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8233 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8234 InputsFixed[0] = InputsFixed[1] ^ 1;
8235 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8236 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8237 // The two inputs are in the same DWord but it is clobbered and the
8238 // adjacent DWord isn't used at all. Move both inputs to the free
8240 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8241 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8242 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8243 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8245 // The only way we hit this point is if there is no clobbering
8246 // (because there are no off-half inputs to this half) and there is no
8247 // free slot adjacent to one of the inputs. In this case, we have to
8248 // swap an input with a non-input.
8249 for (int i = 0; i < 4; ++i)
8250 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8251 "We can't handle any clobbers here!");
8252 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8253 "Cannot have adjacent inputs here!");
8255 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8256 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8258 // We also have to update the final source mask in this case because
8259 // it may need to undo the above swap.
8260 for (int &M : FinalSourceHalfMask)
8261 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8262 M = InputsFixed[1] + SourceOffset;
8263 else if (M == InputsFixed[1] + SourceOffset)
8264 M = (InputsFixed[0] ^ 1) + SourceOffset;
8266 InputsFixed[1] = InputsFixed[0] ^ 1;
8269 // Point everything at the fixed inputs.
8270 for (int &M : HalfMask)
8271 if (M == IncomingInputs[0])
8272 M = InputsFixed[0] + SourceOffset;
8273 else if (M == IncomingInputs[1])
8274 M = InputsFixed[1] + SourceOffset;
8276 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8277 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8280 llvm_unreachable("Unhandled input size!");
8283 // Now hoist the DWord down to the right half.
8284 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8285 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8286 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8287 for (int &M : HalfMask)
8288 for (int Input : IncomingInputs)
8290 M = FreeDWord * 2 + Input % 2;
8292 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8293 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8294 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8295 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8297 // Now enact all the shuffles we've computed to move the inputs into their
8299 if (!isNoopShuffleMask(PSHUFLMask))
8300 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8301 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8302 if (!isNoopShuffleMask(PSHUFHMask))
8303 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8304 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8305 if (!isNoopShuffleMask(PSHUFDMask))
8306 V = DAG.getNode(ISD::BITCAST, DL, VT,
8307 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8308 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8309 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8312 // At this point, each half should contain all its inputs, and we can then
8313 // just shuffle them into their final position.
8314 assert(std::count_if(LoMask.begin(), LoMask.end(),
8315 [](int M) { return M >= 4; }) == 0 &&
8316 "Failed to lift all the high half inputs to the low mask!");
8317 assert(std::count_if(HiMask.begin(), HiMask.end(),
8318 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8319 "Failed to lift all the low half inputs to the high mask!");
8321 // Do a half shuffle for the low mask.
8322 if (!isNoopShuffleMask(LoMask))
8323 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8324 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8326 // Do a half shuffle with the high mask after shifting its values down.
8327 for (int &M : HiMask)
8330 if (!isNoopShuffleMask(HiMask))
8331 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8332 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8337 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8338 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8339 SDValue V2, ArrayRef<int> Mask,
8340 SelectionDAG &DAG, bool &V1InUse,
8342 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8348 int Size = Mask.size();
8349 int Scale = 16 / Size;
8350 for (int i = 0; i < 16; ++i) {
8351 if (Mask[i / Scale] == -1) {
8352 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8354 const int ZeroMask = 0x80;
8355 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8357 int V2Idx = Mask[i / Scale] < Size
8359 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8360 if (Zeroable[i / Scale])
8361 V1Idx = V2Idx = ZeroMask;
8362 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8363 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8364 V1InUse |= (ZeroMask != V1Idx);
8365 V2InUse |= (ZeroMask != V2Idx);
8370 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8371 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8372 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8374 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8375 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8376 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8378 // If we need shuffled inputs from both, blend the two.
8380 if (V1InUse && V2InUse)
8381 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8383 V = V1InUse ? V1 : V2;
8385 // Cast the result back to the correct type.
8386 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8389 /// \brief Generic lowering of 8-lane i16 shuffles.
8391 /// This handles both single-input shuffles and combined shuffle/blends with
8392 /// two inputs. The single input shuffles are immediately delegated to
8393 /// a dedicated lowering routine.
8395 /// The blends are lowered in one of three fundamental ways. If there are few
8396 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8397 /// of the input is significantly cheaper when lowered as an interleaving of
8398 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8399 /// halves of the inputs separately (making them have relatively few inputs)
8400 /// and then concatenate them.
8401 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8402 const X86Subtarget *Subtarget,
8403 SelectionDAG &DAG) {
8405 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8406 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8407 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8408 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8409 ArrayRef<int> OrigMask = SVOp->getMask();
8410 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8411 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8412 MutableArrayRef<int> Mask(MaskStorage);
8414 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8416 // Whenever we can lower this as a zext, that instruction is strictly faster
8417 // than any alternative.
8418 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8419 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8422 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8424 auto isV2 = [](int M) { return M >= 8; };
8426 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8428 if (NumV2Inputs == 0) {
8429 // Check for being able to broadcast a single element.
8430 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8431 Mask, Subtarget, DAG))
8434 // Try to use shift instructions.
8436 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8439 // Use dedicated unpack instructions for masks that match their pattern.
8440 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8441 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8442 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8443 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8445 // Try to use byte rotation instructions.
8446 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8447 Mask, Subtarget, DAG))
8450 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8454 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8455 "All single-input shuffles should be canonicalized to be V1-input "
8458 // Try to use shift instructions.
8460 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8463 // There are special ways we can lower some single-element blends.
8464 if (NumV2Inputs == 1)
8465 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8466 Mask, Subtarget, DAG))
8469 // We have different paths for blend lowering, but they all must use the
8470 // *exact* same predicate.
8471 bool IsBlendSupported = Subtarget->hasSSE41();
8472 if (IsBlendSupported)
8473 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8477 if (SDValue Masked =
8478 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8481 // Use dedicated unpack instructions for masks that match their pattern.
8482 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8483 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8484 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8485 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8487 // Try to use byte rotation instructions.
8488 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8489 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8492 if (SDValue BitBlend =
8493 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8496 if (SDValue Unpack =
8497 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8500 // If we can't directly blend but can use PSHUFB, that will be better as it
8501 // can both shuffle and set up the inefficient blend.
8502 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8503 bool V1InUse, V2InUse;
8504 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8508 // We can always bit-blend if we have to so the fallback strategy is to
8509 // decompose into single-input permutes and blends.
8510 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8514 /// \brief Check whether a compaction lowering can be done by dropping even
8515 /// elements and compute how many times even elements must be dropped.
8517 /// This handles shuffles which take every Nth element where N is a power of
8518 /// two. Example shuffle masks:
8520 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8521 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8522 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8523 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8524 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8525 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8527 /// Any of these lanes can of course be undef.
8529 /// This routine only supports N <= 3.
8530 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8533 /// \returns N above, or the number of times even elements must be dropped if
8534 /// there is such a number. Otherwise returns zero.
8535 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8536 // Figure out whether we're looping over two inputs or just one.
8537 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8539 // The modulus for the shuffle vector entries is based on whether this is
8540 // a single input or not.
8541 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8542 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8543 "We should only be called with masks with a power-of-2 size!");
8545 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8547 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8548 // and 2^3 simultaneously. This is because we may have ambiguity with
8549 // partially undef inputs.
8550 bool ViableForN[3] = {true, true, true};
8552 for (int i = 0, e = Mask.size(); i < e; ++i) {
8553 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8558 bool IsAnyViable = false;
8559 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8560 if (ViableForN[j]) {
8563 // The shuffle mask must be equal to (i * 2^N) % M.
8564 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8567 ViableForN[j] = false;
8569 // Early exit if we exhaust the possible powers of two.
8574 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8578 // Return 0 as there is no viable power of two.
8582 /// \brief Generic lowering of v16i8 shuffles.
8584 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8585 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8586 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8587 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8589 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8590 const X86Subtarget *Subtarget,
8591 SelectionDAG &DAG) {
8593 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8594 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8595 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8596 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8597 ArrayRef<int> Mask = SVOp->getMask();
8598 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8600 // Try to use shift instructions.
8602 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8605 // Try to use byte rotation instructions.
8606 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8607 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8610 // Try to use a zext lowering.
8611 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8612 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8616 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8618 // For single-input shuffles, there are some nicer lowering tricks we can use.
8619 if (NumV2Elements == 0) {
8620 // Check for being able to broadcast a single element.
8621 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8622 Mask, Subtarget, DAG))
8625 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8626 // Notably, this handles splat and partial-splat shuffles more efficiently.
8627 // However, it only makes sense if the pre-duplication shuffle simplifies
8628 // things significantly. Currently, this means we need to be able to
8629 // express the pre-duplication shuffle as an i16 shuffle.
8631 // FIXME: We should check for other patterns which can be widened into an
8632 // i16 shuffle as well.
8633 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8634 for (int i = 0; i < 16; i += 2)
8635 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8640 auto tryToWidenViaDuplication = [&]() -> SDValue {
8641 if (!canWidenViaDuplication(Mask))
8643 SmallVector<int, 4> LoInputs;
8644 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8645 [](int M) { return M >= 0 && M < 8; });
8646 std::sort(LoInputs.begin(), LoInputs.end());
8647 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8649 SmallVector<int, 4> HiInputs;
8650 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8651 [](int M) { return M >= 8; });
8652 std::sort(HiInputs.begin(), HiInputs.end());
8653 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8656 bool TargetLo = LoInputs.size() >= HiInputs.size();
8657 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8658 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8660 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8661 SmallDenseMap<int, int, 8> LaneMap;
8662 for (int I : InPlaceInputs) {
8663 PreDupI16Shuffle[I/2] = I/2;
8666 int j = TargetLo ? 0 : 4, je = j + 4;
8667 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8668 // Check if j is already a shuffle of this input. This happens when
8669 // there are two adjacent bytes after we move the low one.
8670 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8671 // If we haven't yet mapped the input, search for a slot into which
8673 while (j < je && PreDupI16Shuffle[j] != -1)
8677 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8680 // Map this input with the i16 shuffle.
8681 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8684 // Update the lane map based on the mapping we ended up with.
8685 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8688 ISD::BITCAST, DL, MVT::v16i8,
8689 DAG.getVectorShuffle(MVT::v8i16, DL,
8690 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8691 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8693 // Unpack the bytes to form the i16s that will be shuffled into place.
8694 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8695 MVT::v16i8, V1, V1);
8697 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8698 for (int i = 0; i < 16; ++i)
8699 if (Mask[i] != -1) {
8700 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8701 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8702 if (PostDupI16Shuffle[i / 2] == -1)
8703 PostDupI16Shuffle[i / 2] = MappedMask;
8705 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8706 "Conflicting entrties in the original shuffle!");
8709 ISD::BITCAST, DL, MVT::v16i8,
8710 DAG.getVectorShuffle(MVT::v8i16, DL,
8711 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8712 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8714 if (SDValue V = tryToWidenViaDuplication())
8718 // Use dedicated unpack instructions for masks that match their pattern.
8719 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8720 0, 16, 1, 17, 2, 18, 3, 19,
8722 4, 20, 5, 21, 6, 22, 7, 23}))
8723 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8724 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8725 8, 24, 9, 25, 10, 26, 11, 27,
8727 12, 28, 13, 29, 14, 30, 15, 31}))
8728 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8730 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8731 // with PSHUFB. It is important to do this before we attempt to generate any
8732 // blends but after all of the single-input lowerings. If the single input
8733 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8734 // want to preserve that and we can DAG combine any longer sequences into
8735 // a PSHUFB in the end. But once we start blending from multiple inputs,
8736 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8737 // and there are *very* few patterns that would actually be faster than the
8738 // PSHUFB approach because of its ability to zero lanes.
8740 // FIXME: The only exceptions to the above are blends which are exact
8741 // interleavings with direct instructions supporting them. We currently don't
8742 // handle those well here.
8743 if (Subtarget->hasSSSE3()) {
8744 bool V1InUse = false;
8745 bool V2InUse = false;
8747 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8748 DAG, V1InUse, V2InUse);
8750 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8751 // do so. This avoids using them to handle blends-with-zero which is
8752 // important as a single pshufb is significantly faster for that.
8753 if (V1InUse && V2InUse) {
8754 if (Subtarget->hasSSE41())
8755 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8756 Mask, Subtarget, DAG))
8759 // We can use an unpack to do the blending rather than an or in some
8760 // cases. Even though the or may be (very minorly) more efficient, we
8761 // preference this lowering because there are common cases where part of
8762 // the complexity of the shuffles goes away when we do the final blend as
8764 // FIXME: It might be worth trying to detect if the unpack-feeding
8765 // shuffles will both be pshufb, in which case we shouldn't bother with
8767 if (SDValue Unpack =
8768 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8775 // There are special ways we can lower some single-element blends.
8776 if (NumV2Elements == 1)
8777 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8778 Mask, Subtarget, DAG))
8781 if (SDValue BitBlend =
8782 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8785 // Check whether a compaction lowering can be done. This handles shuffles
8786 // which take every Nth element for some even N. See the helper function for
8789 // We special case these as they can be particularly efficiently handled with
8790 // the PACKUSB instruction on x86 and they show up in common patterns of
8791 // rearranging bytes to truncate wide elements.
8792 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8793 // NumEvenDrops is the power of two stride of the elements. Another way of
8794 // thinking about it is that we need to drop the even elements this many
8795 // times to get the original input.
8796 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8798 // First we need to zero all the dropped bytes.
8799 assert(NumEvenDrops <= 3 &&
8800 "No support for dropping even elements more than 3 times.");
8801 // We use the mask type to pick which bytes are preserved based on how many
8802 // elements are dropped.
8803 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8804 SDValue ByteClearMask =
8805 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8806 DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8807 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8809 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8811 // Now pack things back together.
8812 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8813 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8814 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8815 for (int i = 1; i < NumEvenDrops; ++i) {
8816 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8817 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8823 // Handle multi-input cases by blending single-input shuffles.
8824 if (NumV2Elements > 0)
8825 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8828 // The fallback path for single-input shuffles widens this into two v8i16
8829 // vectors with unpacks, shuffles those, and then pulls them back together
8833 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8834 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8835 for (int i = 0; i < 16; ++i)
8837 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8839 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8841 SDValue VLoHalf, VHiHalf;
8842 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8843 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8845 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8846 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8847 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8848 [](int M) { return M >= 0 && M % 2 == 1; })) {
8849 // Use a mask to drop the high bytes.
8850 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8851 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8852 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8854 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8855 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8857 // Squash the masks to point directly into VLoHalf.
8858 for (int &M : LoBlendMask)
8861 for (int &M : HiBlendMask)
8865 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8866 // VHiHalf so that we can blend them as i16s.
8867 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8868 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8869 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8870 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8873 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8874 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8876 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8879 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8881 /// This routine breaks down the specific type of 128-bit shuffle and
8882 /// dispatches to the lowering routines accordingly.
8883 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8884 MVT VT, const X86Subtarget *Subtarget,
8885 SelectionDAG &DAG) {
8886 switch (VT.SimpleTy) {
8888 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8890 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8892 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8894 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8896 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8898 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8901 llvm_unreachable("Unimplemented!");
8905 /// \brief Helper function to test whether a shuffle mask could be
8906 /// simplified by widening the elements being shuffled.
8908 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8909 /// leaves it in an unspecified state.
8911 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8912 /// shuffle masks. The latter have the special property of a '-2' representing
8913 /// a zero-ed lane of a vector.
8914 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8915 SmallVectorImpl<int> &WidenedMask) {
8916 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8917 // If both elements are undef, its trivial.
8918 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8919 WidenedMask.push_back(SM_SentinelUndef);
8923 // Check for an undef mask and a mask value properly aligned to fit with
8924 // a pair of values. If we find such a case, use the non-undef mask's value.
8925 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8926 WidenedMask.push_back(Mask[i + 1] / 2);
8929 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8930 WidenedMask.push_back(Mask[i] / 2);
8934 // When zeroing, we need to spread the zeroing across both lanes to widen.
8935 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8936 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8937 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8938 WidenedMask.push_back(SM_SentinelZero);
8944 // Finally check if the two mask values are adjacent and aligned with
8946 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8947 WidenedMask.push_back(Mask[i] / 2);
8951 // Otherwise we can't safely widen the elements used in this shuffle.
8954 assert(WidenedMask.size() == Mask.size() / 2 &&
8955 "Incorrect size of mask after widening the elements!");
8960 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8962 /// This routine just extracts two subvectors, shuffles them independently, and
8963 /// then concatenates them back together. This should work effectively with all
8964 /// AVX vector shuffle types.
8965 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8966 SDValue V2, ArrayRef<int> Mask,
8967 SelectionDAG &DAG) {
8968 assert(VT.getSizeInBits() >= 256 &&
8969 "Only for 256-bit or wider vector shuffles!");
8970 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8971 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8973 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8974 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8976 int NumElements = VT.getVectorNumElements();
8977 int SplitNumElements = NumElements / 2;
8978 MVT ScalarVT = VT.getScalarType();
8979 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8981 // Rather than splitting build-vectors, just build two narrower build
8982 // vectors. This helps shuffling with splats and zeros.
8983 auto SplitVector = [&](SDValue V) {
8984 while (V.getOpcode() == ISD::BITCAST)
8985 V = V->getOperand(0);
8987 MVT OrigVT = V.getSimpleValueType();
8988 int OrigNumElements = OrigVT.getVectorNumElements();
8989 int OrigSplitNumElements = OrigNumElements / 2;
8990 MVT OrigScalarVT = OrigVT.getScalarType();
8991 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
8995 auto *BV = dyn_cast<BuildVectorSDNode>(V);
8997 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8998 DAG.getIntPtrConstant(0, DL));
8999 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9000 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9003 SmallVector<SDValue, 16> LoOps, HiOps;
9004 for (int i = 0; i < OrigSplitNumElements; ++i) {
9005 LoOps.push_back(BV->getOperand(i));
9006 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9008 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9009 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9011 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
9012 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
9015 SDValue LoV1, HiV1, LoV2, HiV2;
9016 std::tie(LoV1, HiV1) = SplitVector(V1);
9017 std::tie(LoV2, HiV2) = SplitVector(V2);
9019 // Now create two 4-way blends of these half-width vectors.
9020 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9021 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9022 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9023 for (int i = 0; i < SplitNumElements; ++i) {
9024 int M = HalfMask[i];
9025 if (M >= NumElements) {
9026 if (M >= NumElements + SplitNumElements)
9030 V2BlendMask.push_back(M - NumElements);
9031 V1BlendMask.push_back(-1);
9032 BlendMask.push_back(SplitNumElements + i);
9033 } else if (M >= 0) {
9034 if (M >= SplitNumElements)
9038 V2BlendMask.push_back(-1);
9039 V1BlendMask.push_back(M);
9040 BlendMask.push_back(i);
9042 V2BlendMask.push_back(-1);
9043 V1BlendMask.push_back(-1);
9044 BlendMask.push_back(-1);
9048 // Because the lowering happens after all combining takes place, we need to
9049 // manually combine these blend masks as much as possible so that we create
9050 // a minimal number of high-level vector shuffle nodes.
9052 // First try just blending the halves of V1 or V2.
9053 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9054 return DAG.getUNDEF(SplitVT);
9055 if (!UseLoV2 && !UseHiV2)
9056 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9057 if (!UseLoV1 && !UseHiV1)
9058 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9060 SDValue V1Blend, V2Blend;
9061 if (UseLoV1 && UseHiV1) {
9063 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9065 // We only use half of V1 so map the usage down into the final blend mask.
9066 V1Blend = UseLoV1 ? LoV1 : HiV1;
9067 for (int i = 0; i < SplitNumElements; ++i)
9068 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9069 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9071 if (UseLoV2 && UseHiV2) {
9073 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9075 // We only use half of V2 so map the usage down into the final blend mask.
9076 V2Blend = UseLoV2 ? LoV2 : HiV2;
9077 for (int i = 0; i < SplitNumElements; ++i)
9078 if (BlendMask[i] >= SplitNumElements)
9079 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9081 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9083 SDValue Lo = HalfBlend(LoMask);
9084 SDValue Hi = HalfBlend(HiMask);
9085 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9088 /// \brief Either split a vector in halves or decompose the shuffles and the
9091 /// This is provided as a good fallback for many lowerings of non-single-input
9092 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9093 /// between splitting the shuffle into 128-bit components and stitching those
9094 /// back together vs. extracting the single-input shuffles and blending those
9096 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9097 SDValue V2, ArrayRef<int> Mask,
9098 SelectionDAG &DAG) {
9099 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9100 "lower single-input shuffles as it "
9101 "could then recurse on itself.");
9102 int Size = Mask.size();
9104 // If this can be modeled as a broadcast of two elements followed by a blend,
9105 // prefer that lowering. This is especially important because broadcasts can
9106 // often fold with memory operands.
9107 auto DoBothBroadcast = [&] {
9108 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9111 if (V2BroadcastIdx == -1)
9112 V2BroadcastIdx = M - Size;
9113 else if (M - Size != V2BroadcastIdx)
9115 } else if (M >= 0) {
9116 if (V1BroadcastIdx == -1)
9118 else if (M != V1BroadcastIdx)
9123 if (DoBothBroadcast())
9124 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9127 // If the inputs all stem from a single 128-bit lane of each input, then we
9128 // split them rather than blending because the split will decompose to
9129 // unusually few instructions.
9130 int LaneCount = VT.getSizeInBits() / 128;
9131 int LaneSize = Size / LaneCount;
9132 SmallBitVector LaneInputs[2];
9133 LaneInputs[0].resize(LaneCount, false);
9134 LaneInputs[1].resize(LaneCount, false);
9135 for (int i = 0; i < Size; ++i)
9137 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9138 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9139 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9141 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9142 // that the decomposed single-input shuffles don't end up here.
9143 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9146 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9147 /// a permutation and blend of those lanes.
9149 /// This essentially blends the out-of-lane inputs to each lane into the lane
9150 /// from a permuted copy of the vector. This lowering strategy results in four
9151 /// instructions in the worst case for a single-input cross lane shuffle which
9152 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9153 /// of. Special cases for each particular shuffle pattern should be handled
9154 /// prior to trying this lowering.
9155 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9156 SDValue V1, SDValue V2,
9158 SelectionDAG &DAG) {
9159 // FIXME: This should probably be generalized for 512-bit vectors as well.
9160 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9161 int LaneSize = Mask.size() / 2;
9163 // If there are only inputs from one 128-bit lane, splitting will in fact be
9164 // less expensive. The flags track whether the given lane contains an element
9165 // that crosses to another lane.
9166 bool LaneCrossing[2] = {false, false};
9167 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9168 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9169 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9170 if (!LaneCrossing[0] || !LaneCrossing[1])
9171 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9173 if (isSingleInputShuffleMask(Mask)) {
9174 SmallVector<int, 32> FlippedBlendMask;
9175 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9176 FlippedBlendMask.push_back(
9177 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9179 : Mask[i] % LaneSize +
9180 (i / LaneSize) * LaneSize + Size));
9182 // Flip the vector, and blend the results which should now be in-lane. The
9183 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9184 // 5 for the high source. The value 3 selects the high half of source 2 and
9185 // the value 2 selects the low half of source 2. We only use source 2 to
9186 // allow folding it into a memory operand.
9187 unsigned PERMMask = 3 | 2 << 4;
9188 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9189 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9190 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9193 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9194 // will be handled by the above logic and a blend of the results, much like
9195 // other patterns in AVX.
9196 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9199 /// \brief Handle lowering 2-lane 128-bit shuffles.
9200 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9201 SDValue V2, ArrayRef<int> Mask,
9202 const X86Subtarget *Subtarget,
9203 SelectionDAG &DAG) {
9204 // TODO: If minimizing size and one of the inputs is a zero vector and the
9205 // the zero vector has only one use, we could use a VPERM2X128 to save the
9206 // instruction bytes needed to explicitly generate the zero vector.
9208 // Blends are faster and handle all the non-lane-crossing cases.
9209 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9213 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9214 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9216 // If either input operand is a zero vector, use VPERM2X128 because its mask
9217 // allows us to replace the zero input with an implicit zero.
9218 if (!IsV1Zero && !IsV2Zero) {
9219 // Check for patterns which can be matched with a single insert of a 128-bit
9221 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9222 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9223 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9224 VT.getVectorNumElements() / 2);
9225 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9226 DAG.getIntPtrConstant(0, DL));
9227 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9228 OnlyUsesV1 ? V1 : V2,
9229 DAG.getIntPtrConstant(0, DL));
9230 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9234 // Otherwise form a 128-bit permutation. After accounting for undefs,
9235 // convert the 64-bit shuffle mask selection values into 128-bit
9236 // selection bits by dividing the indexes by 2 and shifting into positions
9237 // defined by a vperm2*128 instruction's immediate control byte.
9239 // The immediate permute control byte looks like this:
9240 // [1:0] - select 128 bits from sources for low half of destination
9242 // [3] - zero low half of destination
9243 // [5:4] - select 128 bits from sources for high half of destination
9245 // [7] - zero high half of destination
9247 int MaskLO = Mask[0];
9248 if (MaskLO == SM_SentinelUndef)
9249 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9251 int MaskHI = Mask[2];
9252 if (MaskHI == SM_SentinelUndef)
9253 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9255 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9257 // If either input is a zero vector, replace it with an undef input.
9258 // Shuffle mask values < 4 are selecting elements of V1.
9259 // Shuffle mask values >= 4 are selecting elements of V2.
9260 // Adjust each half of the permute mask by clearing the half that was
9261 // selecting the zero vector and setting the zero mask bit.
9263 V1 = DAG.getUNDEF(VT);
9265 PermMask = (PermMask & 0xf0) | 0x08;
9267 PermMask = (PermMask & 0x0f) | 0x80;
9270 V2 = DAG.getUNDEF(VT);
9272 PermMask = (PermMask & 0xf0) | 0x08;
9274 PermMask = (PermMask & 0x0f) | 0x80;
9277 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9278 DAG.getConstant(PermMask, DL, MVT::i8));
9281 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9282 /// shuffling each lane.
9284 /// This will only succeed when the result of fixing the 128-bit lanes results
9285 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9286 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9287 /// the lane crosses early and then use simpler shuffles within each lane.
9289 /// FIXME: It might be worthwhile at some point to support this without
9290 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9291 /// in x86 only floating point has interesting non-repeating shuffles, and even
9292 /// those are still *marginally* more expensive.
9293 static SDValue lowerVectorShuffleByMerging128BitLanes(
9294 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9295 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9296 assert(!isSingleInputShuffleMask(Mask) &&
9297 "This is only useful with multiple inputs.");
9299 int Size = Mask.size();
9300 int LaneSize = 128 / VT.getScalarSizeInBits();
9301 int NumLanes = Size / LaneSize;
9302 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9304 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9305 // check whether the in-128-bit lane shuffles share a repeating pattern.
9306 SmallVector<int, 4> Lanes;
9307 Lanes.resize(NumLanes, -1);
9308 SmallVector<int, 4> InLaneMask;
9309 InLaneMask.resize(LaneSize, -1);
9310 for (int i = 0; i < Size; ++i) {
9314 int j = i / LaneSize;
9317 // First entry we've seen for this lane.
9318 Lanes[j] = Mask[i] / LaneSize;
9319 } else if (Lanes[j] != Mask[i] / LaneSize) {
9320 // This doesn't match the lane selected previously!
9324 // Check that within each lane we have a consistent shuffle mask.
9325 int k = i % LaneSize;
9326 if (InLaneMask[k] < 0) {
9327 InLaneMask[k] = Mask[i] % LaneSize;
9328 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9329 // This doesn't fit a repeating in-lane mask.
9334 // First shuffle the lanes into place.
9335 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9336 VT.getSizeInBits() / 64);
9337 SmallVector<int, 8> LaneMask;
9338 LaneMask.resize(NumLanes * 2, -1);
9339 for (int i = 0; i < NumLanes; ++i)
9340 if (Lanes[i] >= 0) {
9341 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9342 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9345 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9346 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9347 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9349 // Cast it back to the type we actually want.
9350 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9352 // Now do a simple shuffle that isn't lane crossing.
9353 SmallVector<int, 8> NewMask;
9354 NewMask.resize(Size, -1);
9355 for (int i = 0; i < Size; ++i)
9357 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9358 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9359 "Must not introduce lane crosses at this point!");
9361 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9364 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9367 /// This returns true if the elements from a particular input are already in the
9368 /// slot required by the given mask and require no permutation.
9369 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9370 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9371 int Size = Mask.size();
9372 for (int i = 0; i < Size; ++i)
9373 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9379 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9381 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9382 /// isn't available.
9383 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9384 const X86Subtarget *Subtarget,
9385 SelectionDAG &DAG) {
9387 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9388 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9389 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9390 ArrayRef<int> Mask = SVOp->getMask();
9391 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9393 SmallVector<int, 4> WidenedMask;
9394 if (canWidenShuffleElements(Mask, WidenedMask))
9395 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9398 if (isSingleInputShuffleMask(Mask)) {
9399 // Check for being able to broadcast a single element.
9400 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9401 Mask, Subtarget, DAG))
9404 // Use low duplicate instructions for masks that match their pattern.
9405 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9406 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9408 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9409 // Non-half-crossing single input shuffles can be lowerid with an
9410 // interleaved permutation.
9411 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9412 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9413 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9414 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9417 // With AVX2 we have direct support for this permutation.
9418 if (Subtarget->hasAVX2())
9419 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9420 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9422 // Otherwise, fall back.
9423 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9427 // X86 has dedicated unpack instructions that can handle specific blend
9428 // operations: UNPCKH and UNPCKL.
9429 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9430 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9431 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9432 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9433 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9434 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9435 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9436 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9438 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9442 // Check if the blend happens to exactly fit that of SHUFPD.
9443 if ((Mask[0] == -1 || Mask[0] < 2) &&
9444 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9445 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9446 (Mask[3] == -1 || Mask[3] >= 6)) {
9447 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9448 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9449 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9450 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9452 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9453 (Mask[1] == -1 || Mask[1] < 2) &&
9454 (Mask[2] == -1 || Mask[2] >= 6) &&
9455 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9456 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9457 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9458 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9459 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9462 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9463 // shuffle. However, if we have AVX2 and either inputs are already in place,
9464 // we will be able to shuffle even across lanes the other input in a single
9465 // instruction so skip this pattern.
9466 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9467 isShuffleMaskInputInPlace(1, Mask))))
9468 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9469 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9472 // If we have AVX2 then we always want to lower with a blend because an v4 we
9473 // can fully permute the elements.
9474 if (Subtarget->hasAVX2())
9475 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9478 // Otherwise fall back on generic lowering.
9479 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9482 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9484 /// This routine is only called when we have AVX2 and thus a reasonable
9485 /// instruction set for v4i64 shuffling..
9486 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9487 const X86Subtarget *Subtarget,
9488 SelectionDAG &DAG) {
9490 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9491 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9493 ArrayRef<int> Mask = SVOp->getMask();
9494 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9495 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9497 SmallVector<int, 4> WidenedMask;
9498 if (canWidenShuffleElements(Mask, WidenedMask))
9499 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9502 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9506 // Check for being able to broadcast a single element.
9507 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9508 Mask, Subtarget, DAG))
9511 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9512 // use lower latency instructions that will operate on both 128-bit lanes.
9513 SmallVector<int, 2> RepeatedMask;
9514 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9515 if (isSingleInputShuffleMask(Mask)) {
9516 int PSHUFDMask[] = {-1, -1, -1, -1};
9517 for (int i = 0; i < 2; ++i)
9518 if (RepeatedMask[i] >= 0) {
9519 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9520 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9523 ISD::BITCAST, DL, MVT::v4i64,
9524 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9525 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9526 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9530 // AVX2 provides a direct instruction for permuting a single input across
9532 if (isSingleInputShuffleMask(Mask))
9533 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9534 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9536 // Try to use shift instructions.
9538 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9541 // Use dedicated unpack instructions for masks that match their pattern.
9542 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9543 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9544 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9545 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9546 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9547 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9548 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9549 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9551 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9552 // shuffle. However, if we have AVX2 and either inputs are already in place,
9553 // we will be able to shuffle even across lanes the other input in a single
9554 // instruction so skip this pattern.
9555 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9556 isShuffleMaskInputInPlace(1, Mask))))
9557 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9558 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9561 // Otherwise fall back on generic blend lowering.
9562 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9566 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9568 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9569 /// isn't available.
9570 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9571 const X86Subtarget *Subtarget,
9572 SelectionDAG &DAG) {
9574 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9575 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9576 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9577 ArrayRef<int> Mask = SVOp->getMask();
9578 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9580 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9584 // Check for being able to broadcast a single element.
9585 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9586 Mask, Subtarget, DAG))
9589 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9590 // options to efficiently lower the shuffle.
9591 SmallVector<int, 4> RepeatedMask;
9592 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9593 assert(RepeatedMask.size() == 4 &&
9594 "Repeated masks must be half the mask width!");
9596 // Use even/odd duplicate instructions for masks that match their pattern.
9597 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9598 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9599 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9600 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9602 if (isSingleInputShuffleMask(Mask))
9603 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9604 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9606 // Use dedicated unpack instructions for masks that match their pattern.
9607 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9608 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9609 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9610 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9611 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9612 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9613 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9614 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9616 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9617 // have already handled any direct blends. We also need to squash the
9618 // repeated mask into a simulated v4f32 mask.
9619 for (int i = 0; i < 4; ++i)
9620 if (RepeatedMask[i] >= 8)
9621 RepeatedMask[i] -= 4;
9622 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9625 // If we have a single input shuffle with different shuffle patterns in the
9626 // two 128-bit lanes use the variable mask to VPERMILPS.
9627 if (isSingleInputShuffleMask(Mask)) {
9628 SDValue VPermMask[8];
9629 for (int i = 0; i < 8; ++i)
9630 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9631 : DAG.getConstant(Mask[i], DL, MVT::i32);
9632 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9634 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9635 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9637 if (Subtarget->hasAVX2())
9638 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9639 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9640 DAG.getNode(ISD::BUILD_VECTOR, DL,
9641 MVT::v8i32, VPermMask)),
9644 // Otherwise, fall back.
9645 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9649 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9651 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9652 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9655 // If we have AVX2 then we always want to lower with a blend because at v8 we
9656 // can fully permute the elements.
9657 if (Subtarget->hasAVX2())
9658 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9661 // Otherwise fall back on generic lowering.
9662 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9665 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9667 /// This routine is only called when we have AVX2 and thus a reasonable
9668 /// instruction set for v8i32 shuffling..
9669 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9670 const X86Subtarget *Subtarget,
9671 SelectionDAG &DAG) {
9673 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9674 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9675 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9676 ArrayRef<int> Mask = SVOp->getMask();
9677 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9678 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9680 // Whenever we can lower this as a zext, that instruction is strictly faster
9681 // than any alternative. It also allows us to fold memory operands into the
9682 // shuffle in many cases.
9683 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9684 Mask, Subtarget, DAG))
9687 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9691 // Check for being able to broadcast a single element.
9692 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9693 Mask, Subtarget, DAG))
9696 // If the shuffle mask is repeated in each 128-bit lane we can use more
9697 // efficient instructions that mirror the shuffles across the two 128-bit
9699 SmallVector<int, 4> RepeatedMask;
9700 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9701 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9702 if (isSingleInputShuffleMask(Mask))
9703 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9704 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9706 // Use dedicated unpack instructions for masks that match their pattern.
9707 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9708 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9709 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9710 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9711 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9712 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9713 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9714 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9717 // Try to use shift instructions.
9719 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9722 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9723 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9726 // If the shuffle patterns aren't repeated but it is a single input, directly
9727 // generate a cross-lane VPERMD instruction.
9728 if (isSingleInputShuffleMask(Mask)) {
9729 SDValue VPermMask[8];
9730 for (int i = 0; i < 8; ++i)
9731 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9732 : DAG.getConstant(Mask[i], DL, MVT::i32);
9734 X86ISD::VPERMV, DL, MVT::v8i32,
9735 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9738 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9740 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9741 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9744 // Otherwise fall back on generic blend lowering.
9745 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9749 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9751 /// This routine is only called when we have AVX2 and thus a reasonable
9752 /// instruction set for v16i16 shuffling..
9753 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9754 const X86Subtarget *Subtarget,
9755 SelectionDAG &DAG) {
9757 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9758 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9759 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9760 ArrayRef<int> Mask = SVOp->getMask();
9761 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9762 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9764 // Whenever we can lower this as a zext, that instruction is strictly faster
9765 // than any alternative. It also allows us to fold memory operands into the
9766 // shuffle in many cases.
9767 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9768 Mask, Subtarget, DAG))
9771 // Check for being able to broadcast a single element.
9772 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9773 Mask, Subtarget, DAG))
9776 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9780 // Use dedicated unpack instructions for masks that match their pattern.
9781 if (isShuffleEquivalent(V1, V2, Mask,
9782 {// First 128-bit lane:
9783 0, 16, 1, 17, 2, 18, 3, 19,
9784 // Second 128-bit lane:
9785 8, 24, 9, 25, 10, 26, 11, 27}))
9786 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9787 if (isShuffleEquivalent(V1, V2, Mask,
9788 {// First 128-bit lane:
9789 4, 20, 5, 21, 6, 22, 7, 23,
9790 // Second 128-bit lane:
9791 12, 28, 13, 29, 14, 30, 15, 31}))
9792 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9794 // Try to use shift instructions.
9796 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9799 // Try to use byte rotation instructions.
9800 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9801 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9804 if (isSingleInputShuffleMask(Mask)) {
9805 // There are no generalized cross-lane shuffle operations available on i16
9807 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9808 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9811 SmallVector<int, 8> RepeatedMask;
9812 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9813 // As this is a single-input shuffle, the repeated mask should be
9814 // a strictly valid v8i16 mask that we can pass through to the v8i16
9815 // lowering to handle even the v16 case.
9816 return lowerV8I16GeneralSingleInputVectorShuffle(
9817 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9820 SDValue PSHUFBMask[32];
9821 for (int i = 0; i < 16; ++i) {
9822 if (Mask[i] == -1) {
9823 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9827 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9828 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9829 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9830 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9833 ISD::BITCAST, DL, MVT::v16i16,
9835 X86ISD::PSHUFB, DL, MVT::v32i8,
9836 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9837 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9840 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9842 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9843 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9846 // Otherwise fall back on generic lowering.
9847 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9850 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9852 /// This routine is only called when we have AVX2 and thus a reasonable
9853 /// instruction set for v32i8 shuffling..
9854 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9855 const X86Subtarget *Subtarget,
9856 SelectionDAG &DAG) {
9858 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9859 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9860 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9861 ArrayRef<int> Mask = SVOp->getMask();
9862 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9863 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9865 // Whenever we can lower this as a zext, that instruction is strictly faster
9866 // than any alternative. It also allows us to fold memory operands into the
9867 // shuffle in many cases.
9868 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9869 Mask, Subtarget, DAG))
9872 // Check for being able to broadcast a single element.
9873 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9874 Mask, Subtarget, DAG))
9877 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9881 // Use dedicated unpack instructions for masks that match their pattern.
9882 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9884 if (isShuffleEquivalent(
9886 {// First 128-bit lane:
9887 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9888 // Second 128-bit lane:
9889 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9890 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9891 if (isShuffleEquivalent(
9893 {// First 128-bit lane:
9894 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9895 // Second 128-bit lane:
9896 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9897 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9899 // Try to use shift instructions.
9901 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9904 // Try to use byte rotation instructions.
9905 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9906 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9909 if (isSingleInputShuffleMask(Mask)) {
9910 // There are no generalized cross-lane shuffle operations available on i8
9912 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9913 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9916 SDValue PSHUFBMask[32];
9917 for (int i = 0; i < 32; ++i)
9920 ? DAG.getUNDEF(MVT::i8)
9921 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
9925 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9926 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9929 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9931 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9932 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9935 // Otherwise fall back on generic lowering.
9936 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9939 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9941 /// This routine either breaks down the specific type of a 256-bit x86 vector
9942 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9943 /// together based on the available instructions.
9944 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9945 MVT VT, const X86Subtarget *Subtarget,
9946 SelectionDAG &DAG) {
9948 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9949 ArrayRef<int> Mask = SVOp->getMask();
9951 // If we have a single input to the zero element, insert that into V1 if we
9952 // can do so cheaply.
9953 int NumElts = VT.getVectorNumElements();
9954 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
9955 return M >= NumElts;
9958 if (NumV2Elements == 1 && Mask[0] >= NumElts)
9959 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9960 DL, VT, V1, V2, Mask, Subtarget, DAG))
9963 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9964 // check for those subtargets here and avoid much of the subtarget querying in
9965 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9966 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9967 // floating point types there eventually, just immediately cast everything to
9968 // a float and operate entirely in that domain.
9969 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9970 int ElementBits = VT.getScalarSizeInBits();
9971 if (ElementBits < 32)
9972 // No floating point type available, decompose into 128-bit vectors.
9973 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9975 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9976 VT.getVectorNumElements());
9977 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9978 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9979 return DAG.getNode(ISD::BITCAST, DL, VT,
9980 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9983 switch (VT.SimpleTy) {
9985 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9987 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9989 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9991 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9993 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9995 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9998 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10002 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10003 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10004 const X86Subtarget *Subtarget,
10005 SelectionDAG &DAG) {
10007 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10008 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10009 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10010 ArrayRef<int> Mask = SVOp->getMask();
10011 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10013 // X86 has dedicated unpack instructions that can handle specific blend
10014 // operations: UNPCKH and UNPCKL.
10015 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10016 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10017 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10018 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10020 // FIXME: Implement direct support for this type!
10021 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10024 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10025 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10026 const X86Subtarget *Subtarget,
10027 SelectionDAG &DAG) {
10029 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10030 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10031 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10032 ArrayRef<int> Mask = SVOp->getMask();
10033 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10035 // Use dedicated unpack instructions for masks that match their pattern.
10036 if (isShuffleEquivalent(V1, V2, Mask,
10037 {// First 128-bit lane.
10038 0, 16, 1, 17, 4, 20, 5, 21,
10039 // Second 128-bit lane.
10040 8, 24, 9, 25, 12, 28, 13, 29}))
10041 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10042 if (isShuffleEquivalent(V1, V2, Mask,
10043 {// First 128-bit lane.
10044 2, 18, 3, 19, 6, 22, 7, 23,
10045 // Second 128-bit lane.
10046 10, 26, 11, 27, 14, 30, 15, 31}))
10047 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10049 // FIXME: Implement direct support for this type!
10050 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10053 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10054 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10055 const X86Subtarget *Subtarget,
10056 SelectionDAG &DAG) {
10058 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10059 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10060 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10061 ArrayRef<int> Mask = SVOp->getMask();
10062 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10064 // X86 has dedicated unpack instructions that can handle specific blend
10065 // operations: UNPCKH and UNPCKL.
10066 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10067 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10068 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10069 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10071 // FIXME: Implement direct support for this type!
10072 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10075 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10076 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10077 const X86Subtarget *Subtarget,
10078 SelectionDAG &DAG) {
10080 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10081 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10082 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10083 ArrayRef<int> Mask = SVOp->getMask();
10084 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10086 // Use dedicated unpack instructions for masks that match their pattern.
10087 if (isShuffleEquivalent(V1, V2, Mask,
10088 {// First 128-bit lane.
10089 0, 16, 1, 17, 4, 20, 5, 21,
10090 // Second 128-bit lane.
10091 8, 24, 9, 25, 12, 28, 13, 29}))
10092 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10093 if (isShuffleEquivalent(V1, V2, Mask,
10094 {// First 128-bit lane.
10095 2, 18, 3, 19, 6, 22, 7, 23,
10096 // Second 128-bit lane.
10097 10, 26, 11, 27, 14, 30, 15, 31}))
10098 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10100 // FIXME: Implement direct support for this type!
10101 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10104 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10105 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10106 const X86Subtarget *Subtarget,
10107 SelectionDAG &DAG) {
10109 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10110 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10111 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10112 ArrayRef<int> Mask = SVOp->getMask();
10113 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10114 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10116 // FIXME: Implement direct support for this type!
10117 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10120 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10121 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10122 const X86Subtarget *Subtarget,
10123 SelectionDAG &DAG) {
10125 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10126 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10127 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10128 ArrayRef<int> Mask = SVOp->getMask();
10129 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10130 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10132 // FIXME: Implement direct support for this type!
10133 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10136 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10138 /// This routine either breaks down the specific type of a 512-bit x86 vector
10139 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10140 /// together based on the available instructions.
10141 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10142 MVT VT, const X86Subtarget *Subtarget,
10143 SelectionDAG &DAG) {
10145 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10146 ArrayRef<int> Mask = SVOp->getMask();
10147 assert(Subtarget->hasAVX512() &&
10148 "Cannot lower 512-bit vectors w/ basic ISA!");
10150 // Check for being able to broadcast a single element.
10151 if (SDValue Broadcast =
10152 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10155 // Dispatch to each element type for lowering. If we don't have supprot for
10156 // specific element type shuffles at 512 bits, immediately split them and
10157 // lower them. Each lowering routine of a given type is allowed to assume that
10158 // the requisite ISA extensions for that element type are available.
10159 switch (VT.SimpleTy) {
10161 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10163 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10165 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10167 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10169 if (Subtarget->hasBWI())
10170 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10173 if (Subtarget->hasBWI())
10174 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10178 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10181 // Otherwise fall back on splitting.
10182 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10185 /// \brief Top-level lowering for x86 vector shuffles.
10187 /// This handles decomposition, canonicalization, and lowering of all x86
10188 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10189 /// above in helper routines. The canonicalization attempts to widen shuffles
10190 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10191 /// s.t. only one of the two inputs needs to be tested, etc.
10192 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10193 SelectionDAG &DAG) {
10194 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10195 ArrayRef<int> Mask = SVOp->getMask();
10196 SDValue V1 = Op.getOperand(0);
10197 SDValue V2 = Op.getOperand(1);
10198 MVT VT = Op.getSimpleValueType();
10199 int NumElements = VT.getVectorNumElements();
10202 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10204 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10205 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10206 if (V1IsUndef && V2IsUndef)
10207 return DAG.getUNDEF(VT);
10209 // When we create a shuffle node we put the UNDEF node to second operand,
10210 // but in some cases the first operand may be transformed to UNDEF.
10211 // In this case we should just commute the node.
10213 return DAG.getCommutedVectorShuffle(*SVOp);
10215 // Check for non-undef masks pointing at an undef vector and make the masks
10216 // undef as well. This makes it easier to match the shuffle based solely on
10220 if (M >= NumElements) {
10221 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10222 for (int &M : NewMask)
10223 if (M >= NumElements)
10225 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10228 // We actually see shuffles that are entirely re-arrangements of a set of
10229 // zero inputs. This mostly happens while decomposing complex shuffles into
10230 // simple ones. Directly lower these as a buildvector of zeros.
10231 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10232 if (Zeroable.all())
10233 return getZeroVector(VT, Subtarget, DAG, dl);
10235 // Try to collapse shuffles into using a vector type with fewer elements but
10236 // wider element types. We cap this to not form integers or floating point
10237 // elements wider than 64 bits, but it might be interesting to form i128
10238 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10239 SmallVector<int, 16> WidenedMask;
10240 if (VT.getScalarSizeInBits() < 64 &&
10241 canWidenShuffleElements(Mask, WidenedMask)) {
10242 MVT NewEltVT = VT.isFloatingPoint()
10243 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10244 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10245 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10246 // Make sure that the new vector type is legal. For example, v2f64 isn't
10248 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10249 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10250 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10251 return DAG.getNode(ISD::BITCAST, dl, VT,
10252 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10256 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10257 for (int M : SVOp->getMask())
10259 ++NumUndefElements;
10260 else if (M < NumElements)
10265 // Commute the shuffle as needed such that more elements come from V1 than
10266 // V2. This allows us to match the shuffle pattern strictly on how many
10267 // elements come from V1 without handling the symmetric cases.
10268 if (NumV2Elements > NumV1Elements)
10269 return DAG.getCommutedVectorShuffle(*SVOp);
10271 // When the number of V1 and V2 elements are the same, try to minimize the
10272 // number of uses of V2 in the low half of the vector. When that is tied,
10273 // ensure that the sum of indices for V1 is equal to or lower than the sum
10274 // indices for V2. When those are equal, try to ensure that the number of odd
10275 // indices for V1 is lower than the number of odd indices for V2.
10276 if (NumV1Elements == NumV2Elements) {
10277 int LowV1Elements = 0, LowV2Elements = 0;
10278 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10279 if (M >= NumElements)
10283 if (LowV2Elements > LowV1Elements) {
10284 return DAG.getCommutedVectorShuffle(*SVOp);
10285 } else if (LowV2Elements == LowV1Elements) {
10286 int SumV1Indices = 0, SumV2Indices = 0;
10287 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10288 if (SVOp->getMask()[i] >= NumElements)
10290 else if (SVOp->getMask()[i] >= 0)
10292 if (SumV2Indices < SumV1Indices) {
10293 return DAG.getCommutedVectorShuffle(*SVOp);
10294 } else if (SumV2Indices == SumV1Indices) {
10295 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10296 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10297 if (SVOp->getMask()[i] >= NumElements)
10298 NumV2OddIndices += i % 2;
10299 else if (SVOp->getMask()[i] >= 0)
10300 NumV1OddIndices += i % 2;
10301 if (NumV2OddIndices < NumV1OddIndices)
10302 return DAG.getCommutedVectorShuffle(*SVOp);
10307 // For each vector width, delegate to a specialized lowering routine.
10308 if (VT.getSizeInBits() == 128)
10309 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10311 if (VT.getSizeInBits() == 256)
10312 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10314 // Force AVX-512 vectors to be scalarized for now.
10315 // FIXME: Implement AVX-512 support!
10316 if (VT.getSizeInBits() == 512)
10317 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10319 llvm_unreachable("Unimplemented!");
10322 // This function assumes its argument is a BUILD_VECTOR of constants or
10323 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10325 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10326 unsigned &MaskValue) {
10328 unsigned NumElems = BuildVector->getNumOperands();
10329 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10330 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10331 unsigned NumElemsInLane = NumElems / NumLanes;
10333 // Blend for v16i16 should be symetric for the both lanes.
10334 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10335 SDValue EltCond = BuildVector->getOperand(i);
10336 SDValue SndLaneEltCond =
10337 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10339 int Lane1Cond = -1, Lane2Cond = -1;
10340 if (isa<ConstantSDNode>(EltCond))
10341 Lane1Cond = !isZero(EltCond);
10342 if (isa<ConstantSDNode>(SndLaneEltCond))
10343 Lane2Cond = !isZero(SndLaneEltCond);
10345 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10346 // Lane1Cond != 0, means we want the first argument.
10347 // Lane1Cond == 0, means we want the second argument.
10348 // The encoding of this argument is 0 for the first argument, 1
10349 // for the second. Therefore, invert the condition.
10350 MaskValue |= !Lane1Cond << i;
10351 else if (Lane1Cond < 0)
10352 MaskValue |= !Lane2Cond << i;
10359 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10360 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10361 const X86Subtarget *Subtarget,
10362 SelectionDAG &DAG) {
10363 SDValue Cond = Op.getOperand(0);
10364 SDValue LHS = Op.getOperand(1);
10365 SDValue RHS = Op.getOperand(2);
10367 MVT VT = Op.getSimpleValueType();
10369 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10371 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10373 // Only non-legal VSELECTs reach this lowering, convert those into generic
10374 // shuffles and re-use the shuffle lowering path for blends.
10375 SmallVector<int, 32> Mask;
10376 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10377 SDValue CondElt = CondBV->getOperand(i);
10379 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10381 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10384 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10385 // A vselect where all conditions and data are constants can be optimized into
10386 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10387 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10388 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10389 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10392 // Try to lower this to a blend-style vector shuffle. This can handle all
10393 // constant condition cases.
10394 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10397 // Variable blends are only legal from SSE4.1 onward.
10398 if (!Subtarget->hasSSE41())
10401 // Only some types will be legal on some subtargets. If we can emit a legal
10402 // VSELECT-matching blend, return Op, and but if we need to expand, return
10404 switch (Op.getSimpleValueType().SimpleTy) {
10406 // Most of the vector types have blends past SSE4.1.
10410 // The byte blends for AVX vectors were introduced only in AVX2.
10411 if (Subtarget->hasAVX2())
10418 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10419 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10422 // FIXME: We should custom lower this by fixing the condition and using i8
10428 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10429 MVT VT = Op.getSimpleValueType();
10432 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10435 if (VT.getSizeInBits() == 8) {
10436 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10437 Op.getOperand(0), Op.getOperand(1));
10438 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10439 DAG.getValueType(VT));
10440 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10443 if (VT.getSizeInBits() == 16) {
10444 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10445 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10447 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10448 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10449 DAG.getNode(ISD::BITCAST, dl,
10452 Op.getOperand(1)));
10453 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10454 Op.getOperand(0), Op.getOperand(1));
10455 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10456 DAG.getValueType(VT));
10457 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10460 if (VT == MVT::f32) {
10461 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10462 // the result back to FR32 register. It's only worth matching if the
10463 // result has a single use which is a store or a bitcast to i32. And in
10464 // the case of a store, it's not worth it if the index is a constant 0,
10465 // because a MOVSSmr can be used instead, which is smaller and faster.
10466 if (!Op.hasOneUse())
10468 SDNode *User = *Op.getNode()->use_begin();
10469 if ((User->getOpcode() != ISD::STORE ||
10470 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10471 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10472 (User->getOpcode() != ISD::BITCAST ||
10473 User->getValueType(0) != MVT::i32))
10475 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10476 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10479 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10482 if (VT == MVT::i32 || VT == MVT::i64) {
10483 // ExtractPS/pextrq works with constant index.
10484 if (isa<ConstantSDNode>(Op.getOperand(1)))
10490 /// Extract one bit from mask vector, like v16i1 or v8i1.
10491 /// AVX-512 feature.
10493 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10494 SDValue Vec = Op.getOperand(0);
10496 MVT VecVT = Vec.getSimpleValueType();
10497 SDValue Idx = Op.getOperand(1);
10498 MVT EltVT = Op.getSimpleValueType();
10500 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10501 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10502 "Unexpected vector type in ExtractBitFromMaskVector");
10504 // variable index can't be handled in mask registers,
10505 // extend vector to VR512
10506 if (!isa<ConstantSDNode>(Idx)) {
10507 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10508 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10509 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10510 ExtVT.getVectorElementType(), Ext, Idx);
10511 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10514 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10515 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10516 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10517 rc = getRegClassFor(MVT::v16i1);
10518 unsigned MaxSift = rc->getSize()*8 - 1;
10519 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10520 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10521 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10522 DAG.getConstant(MaxSift, dl, MVT::i8));
10523 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10524 DAG.getIntPtrConstant(0, dl));
10528 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10529 SelectionDAG &DAG) const {
10531 SDValue Vec = Op.getOperand(0);
10532 MVT VecVT = Vec.getSimpleValueType();
10533 SDValue Idx = Op.getOperand(1);
10535 if (Op.getSimpleValueType() == MVT::i1)
10536 return ExtractBitFromMaskVector(Op, DAG);
10538 if (!isa<ConstantSDNode>(Idx)) {
10539 if (VecVT.is512BitVector() ||
10540 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10541 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10544 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10545 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10546 MaskEltVT.getSizeInBits());
10548 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10549 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10550 getZeroVector(MaskVT, Subtarget, DAG, dl),
10551 Idx, DAG.getConstant(0, dl, getPointerTy()));
10552 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10553 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10554 Perm, DAG.getConstant(0, dl, getPointerTy()));
10559 // If this is a 256-bit vector result, first extract the 128-bit vector and
10560 // then extract the element from the 128-bit vector.
10561 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10563 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10564 // Get the 128-bit vector.
10565 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10566 MVT EltVT = VecVT.getVectorElementType();
10568 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10570 //if (IdxVal >= NumElems/2)
10571 // IdxVal -= NumElems/2;
10572 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10573 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10574 DAG.getConstant(IdxVal, dl, MVT::i32));
10577 assert(VecVT.is128BitVector() && "Unexpected vector length");
10579 if (Subtarget->hasSSE41()) {
10580 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10585 MVT VT = Op.getSimpleValueType();
10586 // TODO: handle v16i8.
10587 if (VT.getSizeInBits() == 16) {
10588 SDValue Vec = Op.getOperand(0);
10589 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10591 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10592 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10593 DAG.getNode(ISD::BITCAST, dl,
10595 Op.getOperand(1)));
10596 // Transform it so it match pextrw which produces a 32-bit result.
10597 MVT EltVT = MVT::i32;
10598 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10599 Op.getOperand(0), Op.getOperand(1));
10600 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10601 DAG.getValueType(VT));
10602 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10605 if (VT.getSizeInBits() == 32) {
10606 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10610 // SHUFPS the element to the lowest double word, then movss.
10611 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10612 MVT VVT = Op.getOperand(0).getSimpleValueType();
10613 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10614 DAG.getUNDEF(VVT), Mask);
10615 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10616 DAG.getIntPtrConstant(0, dl));
10619 if (VT.getSizeInBits() == 64) {
10620 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10621 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10622 // to match extract_elt for f64.
10623 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10627 // UNPCKHPD the element to the lowest double word, then movsd.
10628 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10629 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10630 int Mask[2] = { 1, -1 };
10631 MVT VVT = Op.getOperand(0).getSimpleValueType();
10632 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10633 DAG.getUNDEF(VVT), Mask);
10634 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10635 DAG.getIntPtrConstant(0, dl));
10641 /// Insert one bit to mask vector, like v16i1 or v8i1.
10642 /// AVX-512 feature.
10644 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10646 SDValue Vec = Op.getOperand(0);
10647 SDValue Elt = Op.getOperand(1);
10648 SDValue Idx = Op.getOperand(2);
10649 MVT VecVT = Vec.getSimpleValueType();
10651 if (!isa<ConstantSDNode>(Idx)) {
10652 // Non constant index. Extend source and destination,
10653 // insert element and then truncate the result.
10654 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10655 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10656 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10657 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10658 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10659 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10662 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10663 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10664 if (Vec.getOpcode() == ISD::UNDEF)
10665 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10666 DAG.getConstant(IdxVal, dl, MVT::i8));
10667 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10668 unsigned MaxSift = rc->getSize()*8 - 1;
10669 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10670 DAG.getConstant(MaxSift, dl, MVT::i8));
10671 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10672 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10673 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10676 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10677 SelectionDAG &DAG) const {
10678 MVT VT = Op.getSimpleValueType();
10679 MVT EltVT = VT.getVectorElementType();
10681 if (EltVT == MVT::i1)
10682 return InsertBitToMaskVector(Op, DAG);
10685 SDValue N0 = Op.getOperand(0);
10686 SDValue N1 = Op.getOperand(1);
10687 SDValue N2 = Op.getOperand(2);
10688 if (!isa<ConstantSDNode>(N2))
10690 auto *N2C = cast<ConstantSDNode>(N2);
10691 unsigned IdxVal = N2C->getZExtValue();
10693 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10694 // into that, and then insert the subvector back into the result.
10695 if (VT.is256BitVector() || VT.is512BitVector()) {
10696 // With a 256-bit vector, we can insert into the zero element efficiently
10697 // using a blend if we have AVX or AVX2 and the right data type.
10698 if (VT.is256BitVector() && IdxVal == 0) {
10699 // TODO: It is worthwhile to cast integer to floating point and back
10700 // and incur a domain crossing penalty if that's what we'll end up
10701 // doing anyway after extracting to a 128-bit vector.
10702 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10703 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10704 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10705 N2 = DAG.getIntPtrConstant(1, dl);
10706 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10710 // Get the desired 128-bit vector chunk.
10711 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10713 // Insert the element into the desired chunk.
10714 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10715 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10718 DAG.getConstant(IdxIn128, dl, MVT::i32));
10720 // Insert the changed part back into the bigger vector
10721 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10723 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10725 if (Subtarget->hasSSE41()) {
10726 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10728 if (VT == MVT::v8i16) {
10729 Opc = X86ISD::PINSRW;
10731 assert(VT == MVT::v16i8);
10732 Opc = X86ISD::PINSRB;
10735 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10737 if (N1.getValueType() != MVT::i32)
10738 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10739 if (N2.getValueType() != MVT::i32)
10740 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10741 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10744 if (EltVT == MVT::f32) {
10745 // Bits [7:6] of the constant are the source select. This will always be
10746 // zero here. The DAG Combiner may combine an extract_elt index into
10747 // these bits. For example (insert (extract, 3), 2) could be matched by
10748 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10749 // Bits [5:4] of the constant are the destination select. This is the
10750 // value of the incoming immediate.
10751 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10752 // combine either bitwise AND or insert of float 0.0 to set these bits.
10754 const Function *F = DAG.getMachineFunction().getFunction();
10755 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10756 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10757 // If this is an insertion of 32-bits into the low 32-bits of
10758 // a vector, we prefer to generate a blend with immediate rather
10759 // than an insertps. Blends are simpler operations in hardware and so
10760 // will always have equal or better performance than insertps.
10761 // But if optimizing for size and there's a load folding opportunity,
10762 // generate insertps because blendps does not have a 32-bit memory
10764 N2 = DAG.getIntPtrConstant(1, dl);
10765 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10766 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10768 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10769 // Create this as a scalar to vector..
10770 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10771 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10774 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10775 // PINSR* works with constant index.
10780 if (EltVT == MVT::i8)
10783 if (EltVT.getSizeInBits() == 16) {
10784 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10785 // as its second argument.
10786 if (N1.getValueType() != MVT::i32)
10787 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10788 if (N2.getValueType() != MVT::i32)
10789 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10790 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10795 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10797 MVT OpVT = Op.getSimpleValueType();
10799 // If this is a 256-bit vector result, first insert into a 128-bit
10800 // vector and then insert into the 256-bit vector.
10801 if (!OpVT.is128BitVector()) {
10802 // Insert into a 128-bit vector.
10803 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10804 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10805 OpVT.getVectorNumElements() / SizeFactor);
10807 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10809 // Insert the 128-bit vector.
10810 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10813 if (OpVT == MVT::v1i64 &&
10814 Op.getOperand(0).getValueType() == MVT::i64)
10815 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10817 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10818 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10819 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10820 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10823 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10824 // a simple subregister reference or explicit instructions to grab
10825 // upper bits of a vector.
10826 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10827 SelectionDAG &DAG) {
10829 SDValue In = Op.getOperand(0);
10830 SDValue Idx = Op.getOperand(1);
10831 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10832 MVT ResVT = Op.getSimpleValueType();
10833 MVT InVT = In.getSimpleValueType();
10835 if (Subtarget->hasFp256()) {
10836 if (ResVT.is128BitVector() &&
10837 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10838 isa<ConstantSDNode>(Idx)) {
10839 return Extract128BitVector(In, IdxVal, DAG, dl);
10841 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10842 isa<ConstantSDNode>(Idx)) {
10843 return Extract256BitVector(In, IdxVal, DAG, dl);
10849 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10850 // simple superregister reference or explicit instructions to insert
10851 // the upper bits of a vector.
10852 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10853 SelectionDAG &DAG) {
10854 if (!Subtarget->hasAVX())
10858 SDValue Vec = Op.getOperand(0);
10859 SDValue SubVec = Op.getOperand(1);
10860 SDValue Idx = Op.getOperand(2);
10862 if (!isa<ConstantSDNode>(Idx))
10865 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10866 MVT OpVT = Op.getSimpleValueType();
10867 MVT SubVecVT = SubVec.getSimpleValueType();
10869 // Fold two 16-byte subvector loads into one 32-byte load:
10870 // (insert_subvector (insert_subvector undef, (load addr), 0),
10871 // (load addr + 16), Elts/2)
10873 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10874 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10875 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10876 !Subtarget->isUnalignedMem32Slow()) {
10877 SDValue SubVec2 = Vec.getOperand(1);
10878 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10879 if (Idx2->getZExtValue() == 0) {
10880 SDValue Ops[] = { SubVec2, SubVec };
10881 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10888 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10889 SubVecVT.is128BitVector())
10890 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10892 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10893 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10895 if (OpVT.getVectorElementType() == MVT::i1) {
10896 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10898 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10899 SDValue Undef = DAG.getUNDEF(OpVT);
10900 unsigned NumElems = OpVT.getVectorNumElements();
10901 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10903 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10904 // Zero upper bits of the Vec
10905 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10906 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10908 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10910 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10911 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10914 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10916 // Zero upper bits of the Vec2
10917 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10918 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10919 // Zero lower bits of the Vec
10920 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10921 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10922 // Merge them together
10923 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10929 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10930 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10931 // one of the above mentioned nodes. It has to be wrapped because otherwise
10932 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10933 // be used to form addressing mode. These wrapped nodes will be selected
10936 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10937 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10939 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10940 // global base reg.
10941 unsigned char OpFlag = 0;
10942 unsigned WrapperKind = X86ISD::Wrapper;
10943 CodeModel::Model M = DAG.getTarget().getCodeModel();
10945 if (Subtarget->isPICStyleRIPRel() &&
10946 (M == CodeModel::Small || M == CodeModel::Kernel))
10947 WrapperKind = X86ISD::WrapperRIP;
10948 else if (Subtarget->isPICStyleGOT())
10949 OpFlag = X86II::MO_GOTOFF;
10950 else if (Subtarget->isPICStyleStubPIC())
10951 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10953 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10954 CP->getAlignment(),
10955 CP->getOffset(), OpFlag);
10957 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10958 // With PIC, the address is actually $g + Offset.
10960 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10961 DAG.getNode(X86ISD::GlobalBaseReg,
10962 SDLoc(), getPointerTy()),
10969 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10970 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10972 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10973 // global base reg.
10974 unsigned char OpFlag = 0;
10975 unsigned WrapperKind = X86ISD::Wrapper;
10976 CodeModel::Model M = DAG.getTarget().getCodeModel();
10978 if (Subtarget->isPICStyleRIPRel() &&
10979 (M == CodeModel::Small || M == CodeModel::Kernel))
10980 WrapperKind = X86ISD::WrapperRIP;
10981 else if (Subtarget->isPICStyleGOT())
10982 OpFlag = X86II::MO_GOTOFF;
10983 else if (Subtarget->isPICStyleStubPIC())
10984 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10986 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10989 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10991 // With PIC, the address is actually $g + Offset.
10993 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10994 DAG.getNode(X86ISD::GlobalBaseReg,
10995 SDLoc(), getPointerTy()),
11002 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11003 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11005 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11006 // global base reg.
11007 unsigned char OpFlag = 0;
11008 unsigned WrapperKind = X86ISD::Wrapper;
11009 CodeModel::Model M = DAG.getTarget().getCodeModel();
11011 if (Subtarget->isPICStyleRIPRel() &&
11012 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11013 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11014 OpFlag = X86II::MO_GOTPCREL;
11015 WrapperKind = X86ISD::WrapperRIP;
11016 } else if (Subtarget->isPICStyleGOT()) {
11017 OpFlag = X86II::MO_GOT;
11018 } else if (Subtarget->isPICStyleStubPIC()) {
11019 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11020 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11021 OpFlag = X86II::MO_DARWIN_NONLAZY;
11024 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11027 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11029 // With PIC, the address is actually $g + Offset.
11030 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11031 !Subtarget->is64Bit()) {
11032 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11033 DAG.getNode(X86ISD::GlobalBaseReg,
11034 SDLoc(), getPointerTy()),
11038 // For symbols that require a load from a stub to get the address, emit the
11040 if (isGlobalStubReference(OpFlag))
11041 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11042 MachinePointerInfo::getGOT(), false, false, false, 0);
11048 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11049 // Create the TargetBlockAddressAddress node.
11050 unsigned char OpFlags =
11051 Subtarget->ClassifyBlockAddressReference();
11052 CodeModel::Model M = DAG.getTarget().getCodeModel();
11053 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11054 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11056 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11059 if (Subtarget->isPICStyleRIPRel() &&
11060 (M == CodeModel::Small || M == CodeModel::Kernel))
11061 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11063 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11065 // With PIC, the address is actually $g + Offset.
11066 if (isGlobalRelativeToPICBase(OpFlags)) {
11067 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11068 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11076 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11077 int64_t Offset, SelectionDAG &DAG) const {
11078 // Create the TargetGlobalAddress node, folding in the constant
11079 // offset if it is legal.
11080 unsigned char OpFlags =
11081 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11082 CodeModel::Model M = DAG.getTarget().getCodeModel();
11084 if (OpFlags == X86II::MO_NO_FLAG &&
11085 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11086 // A direct static reference to a global.
11087 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11090 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11093 if (Subtarget->isPICStyleRIPRel() &&
11094 (M == CodeModel::Small || M == CodeModel::Kernel))
11095 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11097 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11099 // With PIC, the address is actually $g + Offset.
11100 if (isGlobalRelativeToPICBase(OpFlags)) {
11101 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11102 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11106 // For globals that require a load from a stub to get the address, emit the
11108 if (isGlobalStubReference(OpFlags))
11109 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11110 MachinePointerInfo::getGOT(), false, false, false, 0);
11112 // If there was a non-zero offset that we didn't fold, create an explicit
11113 // addition for it.
11115 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11116 DAG.getConstant(Offset, dl, getPointerTy()));
11122 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11123 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11124 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11125 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11129 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11130 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11131 unsigned char OperandFlags, bool LocalDynamic = false) {
11132 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11133 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11135 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11136 GA->getValueType(0),
11140 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11144 SDValue Ops[] = { Chain, TGA, *InFlag };
11145 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11147 SDValue Ops[] = { Chain, TGA };
11148 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11151 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11152 MFI->setAdjustsStack(true);
11153 MFI->setHasCalls(true);
11155 SDValue Flag = Chain.getValue(1);
11156 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11159 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11161 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11164 SDLoc dl(GA); // ? function entry point might be better
11165 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11166 DAG.getNode(X86ISD::GlobalBaseReg,
11167 SDLoc(), PtrVT), InFlag);
11168 InFlag = Chain.getValue(1);
11170 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11173 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11175 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11177 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11178 X86::RAX, X86II::MO_TLSGD);
11181 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11187 // Get the start address of the TLS block for this module.
11188 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11189 .getInfo<X86MachineFunctionInfo>();
11190 MFI->incNumLocalDynamicTLSAccesses();
11194 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11195 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11198 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11199 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11200 InFlag = Chain.getValue(1);
11201 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11202 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11205 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11209 unsigned char OperandFlags = X86II::MO_DTPOFF;
11210 unsigned WrapperKind = X86ISD::Wrapper;
11211 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11212 GA->getValueType(0),
11213 GA->getOffset(), OperandFlags);
11214 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11216 // Add x@dtpoff with the base.
11217 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11220 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11221 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11222 const EVT PtrVT, TLSModel::Model model,
11223 bool is64Bit, bool isPIC) {
11226 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11227 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11228 is64Bit ? 257 : 256));
11230 SDValue ThreadPointer =
11231 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11232 MachinePointerInfo(Ptr), false, false, false, 0);
11234 unsigned char OperandFlags = 0;
11235 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11237 unsigned WrapperKind = X86ISD::Wrapper;
11238 if (model == TLSModel::LocalExec) {
11239 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11240 } else if (model == TLSModel::InitialExec) {
11242 OperandFlags = X86II::MO_GOTTPOFF;
11243 WrapperKind = X86ISD::WrapperRIP;
11245 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11248 llvm_unreachable("Unexpected model");
11251 // emit "addl x@ntpoff,%eax" (local exec)
11252 // or "addl x@indntpoff,%eax" (initial exec)
11253 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11255 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11256 GA->getOffset(), OperandFlags);
11257 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11259 if (model == TLSModel::InitialExec) {
11260 if (isPIC && !is64Bit) {
11261 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11262 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11266 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11267 MachinePointerInfo::getGOT(), false, false, false, 0);
11270 // The address of the thread local variable is the add of the thread
11271 // pointer with the offset of the variable.
11272 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11276 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11278 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11279 const GlobalValue *GV = GA->getGlobal();
11281 if (Subtarget->isTargetELF()) {
11282 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11285 case TLSModel::GeneralDynamic:
11286 if (Subtarget->is64Bit())
11287 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11288 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11289 case TLSModel::LocalDynamic:
11290 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11291 Subtarget->is64Bit());
11292 case TLSModel::InitialExec:
11293 case TLSModel::LocalExec:
11294 return LowerToTLSExecModel(
11295 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11296 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11298 llvm_unreachable("Unknown TLS model.");
11301 if (Subtarget->isTargetDarwin()) {
11302 // Darwin only has one model of TLS. Lower to that.
11303 unsigned char OpFlag = 0;
11304 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11305 X86ISD::WrapperRIP : X86ISD::Wrapper;
11307 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11308 // global base reg.
11309 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11310 !Subtarget->is64Bit();
11312 OpFlag = X86II::MO_TLVP_PIC_BASE;
11314 OpFlag = X86II::MO_TLVP;
11316 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11317 GA->getValueType(0),
11318 GA->getOffset(), OpFlag);
11319 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11321 // With PIC32, the address is actually $g + Offset.
11323 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11324 DAG.getNode(X86ISD::GlobalBaseReg,
11325 SDLoc(), getPointerTy()),
11328 // Lowering the machine isd will make sure everything is in the right
11330 SDValue Chain = DAG.getEntryNode();
11331 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11332 SDValue Args[] = { Chain, Offset };
11333 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11335 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11336 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11337 MFI->setAdjustsStack(true);
11339 // And our return value (tls address) is in the standard call return value
11341 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11342 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11343 Chain.getValue(1));
11346 if (Subtarget->isTargetKnownWindowsMSVC() ||
11347 Subtarget->isTargetWindowsGNU()) {
11348 // Just use the implicit TLS architecture
11349 // Need to generate someting similar to:
11350 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11352 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11353 // mov rcx, qword [rdx+rcx*8]
11354 // mov eax, .tls$:tlsvar
11355 // [rax+rcx] contains the address
11356 // Windows 64bit: gs:0x58
11357 // Windows 32bit: fs:__tls_array
11360 SDValue Chain = DAG.getEntryNode();
11362 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11363 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11364 // use its literal value of 0x2C.
11365 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11366 ? Type::getInt8PtrTy(*DAG.getContext(),
11368 : Type::getInt32PtrTy(*DAG.getContext(),
11372 Subtarget->is64Bit()
11373 ? DAG.getIntPtrConstant(0x58, dl)
11374 : (Subtarget->isTargetWindowsGNU()
11375 ? DAG.getIntPtrConstant(0x2C, dl)
11376 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11378 SDValue ThreadPointer =
11379 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11380 MachinePointerInfo(Ptr), false, false, false, 0);
11382 // Load the _tls_index variable
11383 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11384 if (Subtarget->is64Bit())
11385 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11386 IDX, MachinePointerInfo(), MVT::i32,
11387 false, false, false, 0);
11389 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11390 false, false, false, 0);
11392 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11394 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11396 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11397 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11398 false, false, false, 0);
11400 // Get the offset of start of .tls section
11401 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11402 GA->getValueType(0),
11403 GA->getOffset(), X86II::MO_SECREL);
11404 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11406 // The address of the thread local variable is the add of the thread
11407 // pointer with the offset of the variable.
11408 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11411 llvm_unreachable("TLS not implemented for this target.");
11414 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11415 /// and take a 2 x i32 value to shift plus a shift amount.
11416 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11417 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11418 MVT VT = Op.getSimpleValueType();
11419 unsigned VTBits = VT.getSizeInBits();
11421 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11422 SDValue ShOpLo = Op.getOperand(0);
11423 SDValue ShOpHi = Op.getOperand(1);
11424 SDValue ShAmt = Op.getOperand(2);
11425 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11426 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11428 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11429 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11430 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11431 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11432 : DAG.getConstant(0, dl, VT);
11434 SDValue Tmp2, Tmp3;
11435 if (Op.getOpcode() == ISD::SHL_PARTS) {
11436 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11437 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11439 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11440 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11443 // If the shift amount is larger or equal than the width of a part we can't
11444 // rely on the results of shld/shrd. Insert a test and select the appropriate
11445 // values for large shift amounts.
11446 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11447 DAG.getConstant(VTBits, dl, MVT::i8));
11448 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11449 AndNode, DAG.getConstant(0, dl, MVT::i8));
11452 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11453 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11454 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11456 if (Op.getOpcode() == ISD::SHL_PARTS) {
11457 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11458 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11460 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11461 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11464 SDValue Ops[2] = { Lo, Hi };
11465 return DAG.getMergeValues(Ops, dl);
11468 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11469 SelectionDAG &DAG) const {
11470 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11473 if (SrcVT.isVector()) {
11474 if (SrcVT.getVectorElementType() == MVT::i1) {
11475 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11476 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11477 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11478 Op.getOperand(0)));
11483 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11484 "Unknown SINT_TO_FP to lower!");
11486 // These are really Legal; return the operand so the caller accepts it as
11488 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11490 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11491 Subtarget->is64Bit()) {
11495 unsigned Size = SrcVT.getSizeInBits()/8;
11496 MachineFunction &MF = DAG.getMachineFunction();
11497 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11498 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11499 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11501 MachinePointerInfo::getFixedStack(SSFI),
11503 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11506 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11508 SelectionDAG &DAG) const {
11512 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11514 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11516 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11518 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11520 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11521 MachineMemOperand *MMO;
11523 int SSFI = FI->getIndex();
11525 DAG.getMachineFunction()
11526 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11527 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11529 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11530 StackSlot = StackSlot.getOperand(1);
11532 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11533 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11535 Tys, Ops, SrcVT, MMO);
11538 Chain = Result.getValue(1);
11539 SDValue InFlag = Result.getValue(2);
11541 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11542 // shouldn't be necessary except that RFP cannot be live across
11543 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11544 MachineFunction &MF = DAG.getMachineFunction();
11545 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11546 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11547 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11548 Tys = DAG.getVTList(MVT::Other);
11550 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11552 MachineMemOperand *MMO =
11553 DAG.getMachineFunction()
11554 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11555 MachineMemOperand::MOStore, SSFISize, SSFISize);
11557 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11558 Ops, Op.getValueType(), MMO);
11559 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11560 MachinePointerInfo::getFixedStack(SSFI),
11561 false, false, false, 0);
11567 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11568 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11569 SelectionDAG &DAG) const {
11570 // This algorithm is not obvious. Here it is what we're trying to output:
11573 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11574 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11576 haddpd %xmm0, %xmm0
11578 pshufd $0x4e, %xmm0, %xmm1
11584 LLVMContext *Context = DAG.getContext();
11586 // Build some magic constants.
11587 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11588 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11589 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11591 SmallVector<Constant*,2> CV1;
11593 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11594 APInt(64, 0x4330000000000000ULL))));
11596 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11597 APInt(64, 0x4530000000000000ULL))));
11598 Constant *C1 = ConstantVector::get(CV1);
11599 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11601 // Load the 64-bit value into an XMM register.
11602 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11604 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11605 MachinePointerInfo::getConstantPool(),
11606 false, false, false, 16);
11607 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11608 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11611 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11612 MachinePointerInfo::getConstantPool(),
11613 false, false, false, 16);
11614 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11615 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11618 if (Subtarget->hasSSE3()) {
11619 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11620 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11622 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11623 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11625 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11626 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11630 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11631 DAG.getIntPtrConstant(0, dl));
11634 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11635 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11636 SelectionDAG &DAG) const {
11638 // FP constant to bias correct the final result.
11639 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11642 // Load the 32-bit value into an XMM register.
11643 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11646 // Zero out the upper parts of the register.
11647 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11649 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11650 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11651 DAG.getIntPtrConstant(0, dl));
11653 // Or the load with the bias.
11654 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11655 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11656 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11657 MVT::v2f64, Load)),
11658 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11659 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11660 MVT::v2f64, Bias)));
11661 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11662 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11663 DAG.getIntPtrConstant(0, dl));
11665 // Subtract the bias.
11666 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11668 // Handle final rounding.
11669 EVT DestVT = Op.getValueType();
11671 if (DestVT.bitsLT(MVT::f64))
11672 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11673 DAG.getIntPtrConstant(0, dl));
11674 if (DestVT.bitsGT(MVT::f64))
11675 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11677 // Handle final rounding.
11681 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11682 const X86Subtarget &Subtarget) {
11683 // The algorithm is the following:
11684 // #ifdef __SSE4_1__
11685 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11686 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11687 // (uint4) 0x53000000, 0xaa);
11689 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11690 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11692 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11693 // return (float4) lo + fhi;
11696 SDValue V = Op->getOperand(0);
11697 EVT VecIntVT = V.getValueType();
11698 bool Is128 = VecIntVT == MVT::v4i32;
11699 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11700 // If we convert to something else than the supported type, e.g., to v4f64,
11702 if (VecFloatVT != Op->getValueType(0))
11705 unsigned NumElts = VecIntVT.getVectorNumElements();
11706 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11707 "Unsupported custom type");
11708 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11710 // In the #idef/#else code, we have in common:
11711 // - The vector of constants:
11717 // Create the splat vector for 0x4b000000.
11718 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11719 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11720 CstLow, CstLow, CstLow, CstLow};
11721 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11722 makeArrayRef(&CstLowArray[0], NumElts));
11723 // Create the splat vector for 0x53000000.
11724 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11725 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11726 CstHigh, CstHigh, CstHigh, CstHigh};
11727 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11728 makeArrayRef(&CstHighArray[0], NumElts));
11730 // Create the right shift.
11731 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11732 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11733 CstShift, CstShift, CstShift, CstShift};
11734 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11735 makeArrayRef(&CstShiftArray[0], NumElts));
11736 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11739 if (Subtarget.hasSSE41()) {
11740 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11741 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11742 SDValue VecCstLowBitcast =
11743 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11744 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11745 // Low will be bitcasted right away, so do not bother bitcasting back to its
11747 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11748 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11749 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11750 // (uint4) 0x53000000, 0xaa);
11751 SDValue VecCstHighBitcast =
11752 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11753 SDValue VecShiftBitcast =
11754 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11755 // High will be bitcasted right away, so do not bother bitcasting back to
11756 // its original type.
11757 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11758 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11760 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11761 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11762 CstMask, CstMask, CstMask);
11763 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11764 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11765 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11767 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11768 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11771 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11772 SDValue CstFAdd = DAG.getConstantFP(
11773 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11774 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11775 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11776 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11777 makeArrayRef(&CstFAddArray[0], NumElts));
11779 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11780 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11782 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11783 // return (float4) lo + fhi;
11784 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11785 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11788 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11789 SelectionDAG &DAG) const {
11790 SDValue N0 = Op.getOperand(0);
11791 MVT SVT = N0.getSimpleValueType();
11794 switch (SVT.SimpleTy) {
11796 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11801 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11802 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11803 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11807 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11810 if (Subtarget->hasAVX512())
11811 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11812 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11814 llvm_unreachable(nullptr);
11817 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11818 SelectionDAG &DAG) const {
11819 SDValue N0 = Op.getOperand(0);
11822 if (Op.getValueType().isVector())
11823 return lowerUINT_TO_FP_vec(Op, DAG);
11825 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11826 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11827 // the optimization here.
11828 if (DAG.SignBitIsZero(N0))
11829 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11831 MVT SrcVT = N0.getSimpleValueType();
11832 MVT DstVT = Op.getSimpleValueType();
11833 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11834 return LowerUINT_TO_FP_i64(Op, DAG);
11835 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11836 return LowerUINT_TO_FP_i32(Op, DAG);
11837 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11840 // Make a 64-bit buffer, and use it to build an FILD.
11841 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11842 if (SrcVT == MVT::i32) {
11843 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11844 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11845 getPointerTy(), StackSlot, WordOff);
11846 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11847 StackSlot, MachinePointerInfo(),
11849 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11850 OffsetSlot, MachinePointerInfo(),
11852 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11856 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11857 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11858 StackSlot, MachinePointerInfo(),
11860 // For i64 source, we need to add the appropriate power of 2 if the input
11861 // was negative. This is the same as the optimization in
11862 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11863 // we must be careful to do the computation in x87 extended precision, not
11864 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11865 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11866 MachineMemOperand *MMO =
11867 DAG.getMachineFunction()
11868 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11869 MachineMemOperand::MOLoad, 8, 8);
11871 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11872 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11873 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11876 APInt FF(32, 0x5F800000ULL);
11878 // Check whether the sign bit is set.
11879 SDValue SignSet = DAG.getSetCC(dl,
11880 getSetCCResultType(*DAG.getContext(), MVT::i64),
11882 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11884 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11885 SDValue FudgePtr = DAG.getConstantPool(
11886 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11889 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11890 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11891 SDValue Four = DAG.getIntPtrConstant(4, dl);
11892 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11894 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11896 // Load the value out, extending it from f32 to f80.
11897 // FIXME: Avoid the extend by constructing the right constant pool?
11898 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11899 FudgePtr, MachinePointerInfo::getConstantPool(),
11900 MVT::f32, false, false, false, 4);
11901 // Extend everything to 80 bits to force it to be done on x87.
11902 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11903 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11904 DAG.getIntPtrConstant(0, dl));
11907 std::pair<SDValue,SDValue>
11908 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11909 bool IsSigned, bool IsReplace) const {
11912 EVT DstTy = Op.getValueType();
11914 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11915 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11919 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11920 DstTy.getSimpleVT() >= MVT::i16 &&
11921 "Unknown FP_TO_INT to lower!");
11923 // These are really Legal.
11924 if (DstTy == MVT::i32 &&
11925 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11926 return std::make_pair(SDValue(), SDValue());
11927 if (Subtarget->is64Bit() &&
11928 DstTy == MVT::i64 &&
11929 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11930 return std::make_pair(SDValue(), SDValue());
11932 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11933 // stack slot, or into the FTOL runtime function.
11934 MachineFunction &MF = DAG.getMachineFunction();
11935 unsigned MemSize = DstTy.getSizeInBits()/8;
11936 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11937 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11940 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11941 Opc = X86ISD::WIN_FTOL;
11943 switch (DstTy.getSimpleVT().SimpleTy) {
11944 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11945 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11946 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11947 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11950 SDValue Chain = DAG.getEntryNode();
11951 SDValue Value = Op.getOperand(0);
11952 EVT TheVT = Op.getOperand(0).getValueType();
11953 // FIXME This causes a redundant load/store if the SSE-class value is already
11954 // in memory, such as if it is on the callstack.
11955 if (isScalarFPTypeInSSEReg(TheVT)) {
11956 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11957 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11958 MachinePointerInfo::getFixedStack(SSFI),
11960 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11962 Chain, StackSlot, DAG.getValueType(TheVT)
11965 MachineMemOperand *MMO =
11966 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11967 MachineMemOperand::MOLoad, MemSize, MemSize);
11968 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11969 Chain = Value.getValue(1);
11970 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11971 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11974 MachineMemOperand *MMO =
11975 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11976 MachineMemOperand::MOStore, MemSize, MemSize);
11978 if (Opc != X86ISD::WIN_FTOL) {
11979 // Build the FP_TO_INT*_IN_MEM
11980 SDValue Ops[] = { Chain, Value, StackSlot };
11981 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11983 return std::make_pair(FIST, StackSlot);
11985 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11986 DAG.getVTList(MVT::Other, MVT::Glue),
11988 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11989 MVT::i32, ftol.getValue(1));
11990 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11991 MVT::i32, eax.getValue(2));
11992 SDValue Ops[] = { eax, edx };
11993 SDValue pair = IsReplace
11994 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11995 : DAG.getMergeValues(Ops, DL);
11996 return std::make_pair(pair, SDValue());
12000 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12001 const X86Subtarget *Subtarget) {
12002 MVT VT = Op->getSimpleValueType(0);
12003 SDValue In = Op->getOperand(0);
12004 MVT InVT = In.getSimpleValueType();
12007 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12008 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12010 // Optimize vectors in AVX mode:
12013 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12014 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12015 // Concat upper and lower parts.
12018 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12019 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12020 // Concat upper and lower parts.
12023 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12024 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12025 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12028 if (Subtarget->hasInt256())
12029 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12031 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12032 SDValue Undef = DAG.getUNDEF(InVT);
12033 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12034 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12035 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12037 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12038 VT.getVectorNumElements()/2);
12040 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12041 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12043 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12046 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12047 SelectionDAG &DAG) {
12048 MVT VT = Op->getSimpleValueType(0);
12049 SDValue In = Op->getOperand(0);
12050 MVT InVT = In.getSimpleValueType();
12052 unsigned int NumElts = VT.getVectorNumElements();
12053 if (NumElts != 8 && NumElts != 16)
12056 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12057 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12059 assert(InVT.getVectorElementType() == MVT::i1);
12060 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12062 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12064 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12066 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12067 if (VT.is512BitVector())
12069 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12072 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12073 SelectionDAG &DAG) {
12074 if (Subtarget->hasFp256()) {
12075 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12083 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12084 SelectionDAG &DAG) {
12086 MVT VT = Op.getSimpleValueType();
12087 SDValue In = Op.getOperand(0);
12088 MVT SVT = In.getSimpleValueType();
12090 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12091 return LowerZERO_EXTEND_AVX512(Op, DAG);
12093 if (Subtarget->hasFp256()) {
12094 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12099 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12100 VT.getVectorNumElements() != SVT.getVectorNumElements());
12104 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12106 MVT VT = Op.getSimpleValueType();
12107 SDValue In = Op.getOperand(0);
12108 MVT InVT = In.getSimpleValueType();
12110 if (VT == MVT::i1) {
12111 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12112 "Invalid scalar TRUNCATE operation");
12113 if (InVT.getSizeInBits() >= 32)
12115 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12116 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12118 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12119 "Invalid TRUNCATE operation");
12121 // move vector to mask - truncate solution for SKX
12122 if (VT.getVectorElementType() == MVT::i1) {
12123 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12124 Subtarget->hasBWI())
12125 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12126 if ((InVT.is256BitVector() || InVT.is128BitVector())
12127 && InVT.getScalarSizeInBits() <= 16 &&
12128 Subtarget->hasBWI() && Subtarget->hasVLX())
12129 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12130 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12131 Subtarget->hasDQI())
12132 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12133 if ((InVT.is256BitVector() || InVT.is128BitVector())
12134 && InVT.getScalarSizeInBits() >= 32 &&
12135 Subtarget->hasDQI() && Subtarget->hasVLX())
12136 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12138 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12139 if (VT.getVectorElementType().getSizeInBits() >=8)
12140 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12142 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12143 unsigned NumElts = InVT.getVectorNumElements();
12144 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12145 if (InVT.getSizeInBits() < 512) {
12146 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12147 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12152 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12153 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12154 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12157 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12158 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12159 if (Subtarget->hasInt256()) {
12160 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12161 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12162 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12164 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12165 DAG.getIntPtrConstant(0, DL));
12168 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12169 DAG.getIntPtrConstant(0, DL));
12170 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12171 DAG.getIntPtrConstant(2, DL));
12172 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12173 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12174 static const int ShufMask[] = {0, 2, 4, 6};
12175 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12178 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12179 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12180 if (Subtarget->hasInt256()) {
12181 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12183 SmallVector<SDValue,32> pshufbMask;
12184 for (unsigned i = 0; i < 2; ++i) {
12185 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12186 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12187 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12188 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12189 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12190 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12191 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12192 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12193 for (unsigned j = 0; j < 8; ++j)
12194 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12196 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12197 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12198 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12200 static const int ShufMask[] = {0, 2, -1, -1};
12201 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12203 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12204 DAG.getIntPtrConstant(0, DL));
12205 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12208 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12209 DAG.getIntPtrConstant(0, DL));
12211 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12212 DAG.getIntPtrConstant(4, DL));
12214 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12215 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12217 // The PSHUFB mask:
12218 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12219 -1, -1, -1, -1, -1, -1, -1, -1};
12221 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12222 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12223 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12225 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12226 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12228 // The MOVLHPS Mask:
12229 static const int ShufMask2[] = {0, 1, 4, 5};
12230 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12231 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12234 // Handle truncation of V256 to V128 using shuffles.
12235 if (!VT.is128BitVector() || !InVT.is256BitVector())
12238 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12240 unsigned NumElems = VT.getVectorNumElements();
12241 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12243 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12244 // Prepare truncation shuffle mask
12245 for (unsigned i = 0; i != NumElems; ++i)
12246 MaskVec[i] = i * 2;
12247 SDValue V = DAG.getVectorShuffle(NVT, DL,
12248 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12249 DAG.getUNDEF(NVT), &MaskVec[0]);
12250 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12251 DAG.getIntPtrConstant(0, DL));
12254 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12255 SelectionDAG &DAG) const {
12256 assert(!Op.getSimpleValueType().isVector());
12258 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12259 /*IsSigned=*/ true, /*IsReplace=*/ false);
12260 SDValue FIST = Vals.first, StackSlot = Vals.second;
12261 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12262 if (!FIST.getNode()) return Op;
12264 if (StackSlot.getNode())
12265 // Load the result.
12266 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12267 FIST, StackSlot, MachinePointerInfo(),
12268 false, false, false, 0);
12270 // The node is the result.
12274 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12275 SelectionDAG &DAG) const {
12276 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12277 /*IsSigned=*/ false, /*IsReplace=*/ false);
12278 SDValue FIST = Vals.first, StackSlot = Vals.second;
12279 assert(FIST.getNode() && "Unexpected failure");
12281 if (StackSlot.getNode())
12282 // Load the result.
12283 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12284 FIST, StackSlot, MachinePointerInfo(),
12285 false, false, false, 0);
12287 // The node is the result.
12291 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12293 MVT VT = Op.getSimpleValueType();
12294 SDValue In = Op.getOperand(0);
12295 MVT SVT = In.getSimpleValueType();
12297 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12299 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12300 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12301 In, DAG.getUNDEF(SVT)));
12304 /// The only differences between FABS and FNEG are the mask and the logic op.
12305 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12306 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12307 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12308 "Wrong opcode for lowering FABS or FNEG.");
12310 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12312 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12313 // into an FNABS. We'll lower the FABS after that if it is still in use.
12315 for (SDNode *User : Op->uses())
12316 if (User->getOpcode() == ISD::FNEG)
12319 SDValue Op0 = Op.getOperand(0);
12320 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12323 MVT VT = Op.getSimpleValueType();
12324 // Assume scalar op for initialization; update for vector if needed.
12325 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12326 // generate a 16-byte vector constant and logic op even for the scalar case.
12327 // Using a 16-byte mask allows folding the load of the mask with
12328 // the logic op, so it can save (~4 bytes) on code size.
12330 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12331 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12332 // decide if we should generate a 16-byte constant mask when we only need 4 or
12333 // 8 bytes for the scalar case.
12334 if (VT.isVector()) {
12335 EltVT = VT.getVectorElementType();
12336 NumElts = VT.getVectorNumElements();
12339 unsigned EltBits = EltVT.getSizeInBits();
12340 LLVMContext *Context = DAG.getContext();
12341 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12343 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12344 Constant *C = ConstantInt::get(*Context, MaskElt);
12345 C = ConstantVector::getSplat(NumElts, C);
12346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12347 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12348 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12349 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12350 MachinePointerInfo::getConstantPool(),
12351 false, false, false, Alignment);
12353 if (VT.isVector()) {
12354 // For a vector, cast operands to a vector type, perform the logic op,
12355 // and cast the result back to the original value type.
12356 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12357 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12358 SDValue Operand = IsFNABS ?
12359 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12360 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12361 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12362 return DAG.getNode(ISD::BITCAST, dl, VT,
12363 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12366 // If not vector, then scalar.
12367 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12368 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12369 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12372 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12373 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12374 LLVMContext *Context = DAG.getContext();
12375 SDValue Op0 = Op.getOperand(0);
12376 SDValue Op1 = Op.getOperand(1);
12378 MVT VT = Op.getSimpleValueType();
12379 MVT SrcVT = Op1.getSimpleValueType();
12381 // If second operand is smaller, extend it first.
12382 if (SrcVT.bitsLT(VT)) {
12383 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12386 // And if it is bigger, shrink it first.
12387 if (SrcVT.bitsGT(VT)) {
12388 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12392 // At this point the operands and the result should have the same
12393 // type, and that won't be f80 since that is not custom lowered.
12395 const fltSemantics &Sem =
12396 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12397 const unsigned SizeInBits = VT.getSizeInBits();
12399 SmallVector<Constant *, 4> CV(
12400 VT == MVT::f64 ? 2 : 4,
12401 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12403 // First, clear all bits but the sign bit from the second operand (sign).
12404 CV[0] = ConstantFP::get(*Context,
12405 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12406 Constant *C = ConstantVector::get(CV);
12407 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12408 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12409 MachinePointerInfo::getConstantPool(),
12410 false, false, false, 16);
12411 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12413 // Next, clear the sign bit from the first operand (magnitude).
12414 // If it's a constant, we can clear it here.
12415 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12416 APFloat APF = Op0CN->getValueAPF();
12417 // If the magnitude is a positive zero, the sign bit alone is enough.
12418 if (APF.isPosZero())
12421 CV[0] = ConstantFP::get(*Context, APF);
12423 CV[0] = ConstantFP::get(
12425 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12427 C = ConstantVector::get(CV);
12428 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12429 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12430 MachinePointerInfo::getConstantPool(),
12431 false, false, false, 16);
12432 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12433 if (!isa<ConstantFPSDNode>(Op0))
12434 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12436 // OR the magnitude value with the sign bit.
12437 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12440 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12441 SDValue N0 = Op.getOperand(0);
12443 MVT VT = Op.getSimpleValueType();
12445 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12446 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12447 DAG.getConstant(1, dl, VT));
12448 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12451 // Check whether an OR'd tree is PTEST-able.
12452 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12453 SelectionDAG &DAG) {
12454 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12456 if (!Subtarget->hasSSE41())
12459 if (!Op->hasOneUse())
12462 SDNode *N = Op.getNode();
12465 SmallVector<SDValue, 8> Opnds;
12466 DenseMap<SDValue, unsigned> VecInMap;
12467 SmallVector<SDValue, 8> VecIns;
12468 EVT VT = MVT::Other;
12470 // Recognize a special case where a vector is casted into wide integer to
12472 Opnds.push_back(N->getOperand(0));
12473 Opnds.push_back(N->getOperand(1));
12475 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12476 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12477 // BFS traverse all OR'd operands.
12478 if (I->getOpcode() == ISD::OR) {
12479 Opnds.push_back(I->getOperand(0));
12480 Opnds.push_back(I->getOperand(1));
12481 // Re-evaluate the number of nodes to be traversed.
12482 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12486 // Quit if a non-EXTRACT_VECTOR_ELT
12487 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12490 // Quit if without a constant index.
12491 SDValue Idx = I->getOperand(1);
12492 if (!isa<ConstantSDNode>(Idx))
12495 SDValue ExtractedFromVec = I->getOperand(0);
12496 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12497 if (M == VecInMap.end()) {
12498 VT = ExtractedFromVec.getValueType();
12499 // Quit if not 128/256-bit vector.
12500 if (!VT.is128BitVector() && !VT.is256BitVector())
12502 // Quit if not the same type.
12503 if (VecInMap.begin() != VecInMap.end() &&
12504 VT != VecInMap.begin()->first.getValueType())
12506 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12507 VecIns.push_back(ExtractedFromVec);
12509 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12512 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12513 "Not extracted from 128-/256-bit vector.");
12515 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12517 for (DenseMap<SDValue, unsigned>::const_iterator
12518 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12519 // Quit if not all elements are used.
12520 if (I->second != FullMask)
12524 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12526 // Cast all vectors into TestVT for PTEST.
12527 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12528 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12530 // If more than one full vectors are evaluated, OR them first before PTEST.
12531 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12532 // Each iteration will OR 2 nodes and append the result until there is only
12533 // 1 node left, i.e. the final OR'd value of all vectors.
12534 SDValue LHS = VecIns[Slot];
12535 SDValue RHS = VecIns[Slot + 1];
12536 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12539 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12540 VecIns.back(), VecIns.back());
12543 /// \brief return true if \c Op has a use that doesn't just read flags.
12544 static bool hasNonFlagsUse(SDValue Op) {
12545 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12547 SDNode *User = *UI;
12548 unsigned UOpNo = UI.getOperandNo();
12549 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12550 // Look pass truncate.
12551 UOpNo = User->use_begin().getOperandNo();
12552 User = *User->use_begin();
12555 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12556 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12562 /// Emit nodes that will be selected as "test Op0,Op0", or something
12564 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12565 SelectionDAG &DAG) const {
12566 if (Op.getValueType() == MVT::i1) {
12567 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12568 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12569 DAG.getConstant(0, dl, MVT::i8));
12571 // CF and OF aren't always set the way we want. Determine which
12572 // of these we need.
12573 bool NeedCF = false;
12574 bool NeedOF = false;
12577 case X86::COND_A: case X86::COND_AE:
12578 case X86::COND_B: case X86::COND_BE:
12581 case X86::COND_G: case X86::COND_GE:
12582 case X86::COND_L: case X86::COND_LE:
12583 case X86::COND_O: case X86::COND_NO: {
12584 // Check if we really need to set the
12585 // Overflow flag. If NoSignedWrap is present
12586 // that is not actually needed.
12587 switch (Op->getOpcode()) {
12592 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12593 if (BinNode->Flags.hasNoSignedWrap())
12603 // See if we can use the EFLAGS value from the operand instead of
12604 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12605 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12606 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12607 // Emit a CMP with 0, which is the TEST pattern.
12608 //if (Op.getValueType() == MVT::i1)
12609 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12610 // DAG.getConstant(0, MVT::i1));
12611 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12612 DAG.getConstant(0, dl, Op.getValueType()));
12614 unsigned Opcode = 0;
12615 unsigned NumOperands = 0;
12617 // Truncate operations may prevent the merge of the SETCC instruction
12618 // and the arithmetic instruction before it. Attempt to truncate the operands
12619 // of the arithmetic instruction and use a reduced bit-width instruction.
12620 bool NeedTruncation = false;
12621 SDValue ArithOp = Op;
12622 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12623 SDValue Arith = Op->getOperand(0);
12624 // Both the trunc and the arithmetic op need to have one user each.
12625 if (Arith->hasOneUse())
12626 switch (Arith.getOpcode()) {
12633 NeedTruncation = true;
12639 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12640 // which may be the result of a CAST. We use the variable 'Op', which is the
12641 // non-casted variable when we check for possible users.
12642 switch (ArithOp.getOpcode()) {
12644 // Due to an isel shortcoming, be conservative if this add is likely to be
12645 // selected as part of a load-modify-store instruction. When the root node
12646 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12647 // uses of other nodes in the match, such as the ADD in this case. This
12648 // leads to the ADD being left around and reselected, with the result being
12649 // two adds in the output. Alas, even if none our users are stores, that
12650 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12651 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12652 // climbing the DAG back to the root, and it doesn't seem to be worth the
12654 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12655 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12656 if (UI->getOpcode() != ISD::CopyToReg &&
12657 UI->getOpcode() != ISD::SETCC &&
12658 UI->getOpcode() != ISD::STORE)
12661 if (ConstantSDNode *C =
12662 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12663 // An add of one will be selected as an INC.
12664 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12665 Opcode = X86ISD::INC;
12670 // An add of negative one (subtract of one) will be selected as a DEC.
12671 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12672 Opcode = X86ISD::DEC;
12678 // Otherwise use a regular EFLAGS-setting add.
12679 Opcode = X86ISD::ADD;
12684 // If we have a constant logical shift that's only used in a comparison
12685 // against zero turn it into an equivalent AND. This allows turning it into
12686 // a TEST instruction later.
12687 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12688 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12689 EVT VT = Op.getValueType();
12690 unsigned BitWidth = VT.getSizeInBits();
12691 unsigned ShAmt = Op->getConstantOperandVal(1);
12692 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12694 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12695 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12696 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12697 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12699 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12700 DAG.getConstant(Mask, dl, VT));
12701 DAG.ReplaceAllUsesWith(Op, New);
12707 // If the primary and result isn't used, don't bother using X86ISD::AND,
12708 // because a TEST instruction will be better.
12709 if (!hasNonFlagsUse(Op))
12715 // Due to the ISEL shortcoming noted above, be conservative if this op is
12716 // likely to be selected as part of a load-modify-store instruction.
12717 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12718 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12719 if (UI->getOpcode() == ISD::STORE)
12722 // Otherwise use a regular EFLAGS-setting instruction.
12723 switch (ArithOp.getOpcode()) {
12724 default: llvm_unreachable("unexpected operator!");
12725 case ISD::SUB: Opcode = X86ISD::SUB; break;
12726 case ISD::XOR: Opcode = X86ISD::XOR; break;
12727 case ISD::AND: Opcode = X86ISD::AND; break;
12729 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12730 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12731 if (EFLAGS.getNode())
12734 Opcode = X86ISD::OR;
12748 return SDValue(Op.getNode(), 1);
12754 // If we found that truncation is beneficial, perform the truncation and
12756 if (NeedTruncation) {
12757 EVT VT = Op.getValueType();
12758 SDValue WideVal = Op->getOperand(0);
12759 EVT WideVT = WideVal.getValueType();
12760 unsigned ConvertedOp = 0;
12761 // Use a target machine opcode to prevent further DAGCombine
12762 // optimizations that may separate the arithmetic operations
12763 // from the setcc node.
12764 switch (WideVal.getOpcode()) {
12766 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12767 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12768 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12769 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12770 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12775 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12776 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12777 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12778 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12784 // Emit a CMP with 0, which is the TEST pattern.
12785 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12786 DAG.getConstant(0, dl, Op.getValueType()));
12788 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12789 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12791 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12792 DAG.ReplaceAllUsesWith(Op, New);
12793 return SDValue(New.getNode(), 1);
12796 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12798 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12799 SDLoc dl, SelectionDAG &DAG) const {
12800 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12801 if (C->getAPIntValue() == 0)
12802 return EmitTest(Op0, X86CC, dl, DAG);
12804 if (Op0.getValueType() == MVT::i1)
12805 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12808 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12809 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12810 // Do the comparison at i32 if it's smaller, besides the Atom case.
12811 // This avoids subregister aliasing issues. Keep the smaller reference
12812 // if we're optimizing for size, however, as that'll allow better folding
12813 // of memory operations.
12814 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12815 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12816 Attribute::MinSize) &&
12817 !Subtarget->isAtom()) {
12818 unsigned ExtendOp =
12819 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12820 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12821 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12823 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12824 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12825 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12827 return SDValue(Sub.getNode(), 1);
12829 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12832 /// Convert a comparison if required by the subtarget.
12833 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12834 SelectionDAG &DAG) const {
12835 // If the subtarget does not support the FUCOMI instruction, floating-point
12836 // comparisons have to be converted.
12837 if (Subtarget->hasCMov() ||
12838 Cmp.getOpcode() != X86ISD::CMP ||
12839 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12840 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12843 // The instruction selector will select an FUCOM instruction instead of
12844 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12845 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12846 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12848 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12849 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12850 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12851 DAG.getConstant(8, dl, MVT::i8));
12852 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12853 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12856 /// The minimum architected relative accuracy is 2^-12. We need one
12857 /// Newton-Raphson step to have a good float result (24 bits of precision).
12858 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12859 DAGCombinerInfo &DCI,
12860 unsigned &RefinementSteps,
12861 bool &UseOneConstNR) const {
12862 // FIXME: We should use instruction latency models to calculate the cost of
12863 // each potential sequence, but this is very hard to do reliably because
12864 // at least Intel's Core* chips have variable timing based on the number of
12865 // significant digits in the divisor and/or sqrt operand.
12866 if (!Subtarget->useSqrtEst())
12869 EVT VT = Op.getValueType();
12871 // SSE1 has rsqrtss and rsqrtps.
12872 // TODO: Add support for AVX512 (v16f32).
12873 // It is likely not profitable to do this for f64 because a double-precision
12874 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12875 // instructions: convert to single, rsqrtss, convert back to double, refine
12876 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12877 // along with FMA, this could be a throughput win.
12878 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12879 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12880 RefinementSteps = 1;
12881 UseOneConstNR = false;
12882 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12887 /// The minimum architected relative accuracy is 2^-12. We need one
12888 /// Newton-Raphson step to have a good float result (24 bits of precision).
12889 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12890 DAGCombinerInfo &DCI,
12891 unsigned &RefinementSteps) const {
12892 // FIXME: We should use instruction latency models to calculate the cost of
12893 // each potential sequence, but this is very hard to do reliably because
12894 // at least Intel's Core* chips have variable timing based on the number of
12895 // significant digits in the divisor.
12896 if (!Subtarget->useReciprocalEst())
12899 EVT VT = Op.getValueType();
12901 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12902 // TODO: Add support for AVX512 (v16f32).
12903 // It is likely not profitable to do this for f64 because a double-precision
12904 // reciprocal estimate with refinement on x86 prior to FMA requires
12905 // 15 instructions: convert to single, rcpss, convert back to double, refine
12906 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12907 // along with FMA, this could be a throughput win.
12908 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12909 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12910 RefinementSteps = ReciprocalEstimateRefinementSteps;
12911 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12916 /// If we have at least two divisions that use the same divisor, convert to
12917 /// multplication by a reciprocal. This may need to be adjusted for a given
12918 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12919 /// This is because we still need one division to calculate the reciprocal and
12920 /// then we need two multiplies by that reciprocal as replacements for the
12921 /// original divisions.
12922 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12923 return NumUsers > 1;
12926 static bool isAllOnes(SDValue V) {
12927 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12928 return C && C->isAllOnesValue();
12931 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12932 /// if it's possible.
12933 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12934 SDLoc dl, SelectionDAG &DAG) const {
12935 SDValue Op0 = And.getOperand(0);
12936 SDValue Op1 = And.getOperand(1);
12937 if (Op0.getOpcode() == ISD::TRUNCATE)
12938 Op0 = Op0.getOperand(0);
12939 if (Op1.getOpcode() == ISD::TRUNCATE)
12940 Op1 = Op1.getOperand(0);
12943 if (Op1.getOpcode() == ISD::SHL)
12944 std::swap(Op0, Op1);
12945 if (Op0.getOpcode() == ISD::SHL) {
12946 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12947 if (And00C->getZExtValue() == 1) {
12948 // If we looked past a truncate, check that it's only truncating away
12950 unsigned BitWidth = Op0.getValueSizeInBits();
12951 unsigned AndBitWidth = And.getValueSizeInBits();
12952 if (BitWidth > AndBitWidth) {
12954 DAG.computeKnownBits(Op0, Zeros, Ones);
12955 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12959 RHS = Op0.getOperand(1);
12961 } else if (Op1.getOpcode() == ISD::Constant) {
12962 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12963 uint64_t AndRHSVal = AndRHS->getZExtValue();
12964 SDValue AndLHS = Op0;
12966 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12967 LHS = AndLHS.getOperand(0);
12968 RHS = AndLHS.getOperand(1);
12971 // Use BT if the immediate can't be encoded in a TEST instruction.
12972 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12974 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
12978 if (LHS.getNode()) {
12979 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12980 // instruction. Since the shift amount is in-range-or-undefined, we know
12981 // that doing a bittest on the i32 value is ok. We extend to i32 because
12982 // the encoding for the i16 version is larger than the i32 version.
12983 // Also promote i16 to i32 for performance / code size reason.
12984 if (LHS.getValueType() == MVT::i8 ||
12985 LHS.getValueType() == MVT::i16)
12986 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12988 // If the operand types disagree, extend the shift amount to match. Since
12989 // BT ignores high bits (like shifts) we can use anyextend.
12990 if (LHS.getValueType() != RHS.getValueType())
12991 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12993 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12994 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12995 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12996 DAG.getConstant(Cond, dl, MVT::i8), BT);
13002 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13004 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13009 // SSE Condition code mapping:
13018 switch (SetCCOpcode) {
13019 default: llvm_unreachable("Unexpected SETCC condition");
13021 case ISD::SETEQ: SSECC = 0; break;
13023 case ISD::SETGT: Swap = true; // Fallthrough
13025 case ISD::SETOLT: SSECC = 1; break;
13027 case ISD::SETGE: Swap = true; // Fallthrough
13029 case ISD::SETOLE: SSECC = 2; break;
13030 case ISD::SETUO: SSECC = 3; break;
13032 case ISD::SETNE: SSECC = 4; break;
13033 case ISD::SETULE: Swap = true; // Fallthrough
13034 case ISD::SETUGE: SSECC = 5; break;
13035 case ISD::SETULT: Swap = true; // Fallthrough
13036 case ISD::SETUGT: SSECC = 6; break;
13037 case ISD::SETO: SSECC = 7; break;
13039 case ISD::SETONE: SSECC = 8; break;
13042 std::swap(Op0, Op1);
13047 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13048 // ones, and then concatenate the result back.
13049 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13050 MVT VT = Op.getSimpleValueType();
13052 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13053 "Unsupported value type for operation");
13055 unsigned NumElems = VT.getVectorNumElements();
13057 SDValue CC = Op.getOperand(2);
13059 // Extract the LHS vectors
13060 SDValue LHS = Op.getOperand(0);
13061 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13062 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13064 // Extract the RHS vectors
13065 SDValue RHS = Op.getOperand(1);
13066 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13067 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13069 // Issue the operation on the smaller types and concatenate the result back
13070 MVT EltVT = VT.getVectorElementType();
13071 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13072 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13073 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13074 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13077 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13078 SDValue Op0 = Op.getOperand(0);
13079 SDValue Op1 = Op.getOperand(1);
13080 SDValue CC = Op.getOperand(2);
13081 MVT VT = Op.getSimpleValueType();
13084 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13085 "Unexpected type for boolean compare operation");
13086 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13087 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13088 DAG.getConstant(-1, dl, VT));
13089 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13090 DAG.getConstant(-1, dl, VT));
13091 switch (SetCCOpcode) {
13092 default: llvm_unreachable("Unexpected SETCC condition");
13094 // (x != y) -> ~(x ^ y)
13095 return DAG.getNode(ISD::XOR, dl, VT,
13096 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13097 DAG.getConstant(-1, dl, VT));
13099 // (x == y) -> (x ^ y)
13100 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13103 // (x > y) -> (x & ~y)
13104 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13107 // (x < y) -> (~x & y)
13108 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13111 // (x <= y) -> (~x | y)
13112 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13115 // (x >=y) -> (x | ~y)
13116 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13120 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13121 const X86Subtarget *Subtarget) {
13122 SDValue Op0 = Op.getOperand(0);
13123 SDValue Op1 = Op.getOperand(1);
13124 SDValue CC = Op.getOperand(2);
13125 MVT VT = Op.getSimpleValueType();
13128 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13129 Op.getValueType().getScalarType() == MVT::i1 &&
13130 "Cannot set masked compare for this operation");
13132 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13134 bool Unsigned = false;
13137 switch (SetCCOpcode) {
13138 default: llvm_unreachable("Unexpected SETCC condition");
13139 case ISD::SETNE: SSECC = 4; break;
13140 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13141 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13142 case ISD::SETLT: Swap = true; //fall-through
13143 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13144 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13145 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13146 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13147 case ISD::SETULE: Unsigned = true; //fall-through
13148 case ISD::SETLE: SSECC = 2; break;
13152 std::swap(Op0, Op1);
13154 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13155 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13156 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13157 DAG.getConstant(SSECC, dl, MVT::i8));
13160 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13161 /// operand \p Op1. If non-trivial (for example because it's not constant)
13162 /// return an empty value.
13163 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13165 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13169 MVT VT = Op1.getSimpleValueType();
13170 MVT EVT = VT.getVectorElementType();
13171 unsigned n = VT.getVectorNumElements();
13172 SmallVector<SDValue, 8> ULTOp1;
13174 for (unsigned i = 0; i < n; ++i) {
13175 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13176 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13179 // Avoid underflow.
13180 APInt Val = Elt->getAPIntValue();
13184 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13187 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13190 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13191 SelectionDAG &DAG) {
13192 SDValue Op0 = Op.getOperand(0);
13193 SDValue Op1 = Op.getOperand(1);
13194 SDValue CC = Op.getOperand(2);
13195 MVT VT = Op.getSimpleValueType();
13196 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13197 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13202 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13203 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13206 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13207 unsigned Opc = X86ISD::CMPP;
13208 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13209 assert(VT.getVectorNumElements() <= 16);
13210 Opc = X86ISD::CMPM;
13212 // In the two special cases we can't handle, emit two comparisons.
13215 unsigned CombineOpc;
13216 if (SetCCOpcode == ISD::SETUEQ) {
13217 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13219 assert(SetCCOpcode == ISD::SETONE);
13220 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13223 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13224 DAG.getConstant(CC0, dl, MVT::i8));
13225 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13226 DAG.getConstant(CC1, dl, MVT::i8));
13227 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13229 // Handle all other FP comparisons here.
13230 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13231 DAG.getConstant(SSECC, dl, MVT::i8));
13234 // Break 256-bit integer vector compare into smaller ones.
13235 if (VT.is256BitVector() && !Subtarget->hasInt256())
13236 return Lower256IntVSETCC(Op, DAG);
13238 EVT OpVT = Op1.getValueType();
13239 if (OpVT.getVectorElementType() == MVT::i1)
13240 return LowerBoolVSETCC_AVX512(Op, DAG);
13242 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13243 if (Subtarget->hasAVX512()) {
13244 if (Op1.getValueType().is512BitVector() ||
13245 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13246 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13247 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13249 // In AVX-512 architecture setcc returns mask with i1 elements,
13250 // But there is no compare instruction for i8 and i16 elements in KNL.
13251 // We are not talking about 512-bit operands in this case, these
13252 // types are illegal.
13254 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13255 OpVT.getVectorElementType().getSizeInBits() >= 8))
13256 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13257 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13260 // We are handling one of the integer comparisons here. Since SSE only has
13261 // GT and EQ comparisons for integer, swapping operands and multiple
13262 // operations may be required for some comparisons.
13264 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13265 bool Subus = false;
13267 switch (SetCCOpcode) {
13268 default: llvm_unreachable("Unexpected SETCC condition");
13269 case ISD::SETNE: Invert = true;
13270 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13271 case ISD::SETLT: Swap = true;
13272 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13273 case ISD::SETGE: Swap = true;
13274 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13275 Invert = true; break;
13276 case ISD::SETULT: Swap = true;
13277 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13278 FlipSigns = true; break;
13279 case ISD::SETUGE: Swap = true;
13280 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13281 FlipSigns = true; Invert = true; break;
13284 // Special case: Use min/max operations for SETULE/SETUGE
13285 MVT VET = VT.getVectorElementType();
13287 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13288 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13291 switch (SetCCOpcode) {
13293 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13294 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13297 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13300 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13301 if (!MinMax && hasSubus) {
13302 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13304 // t = psubus Op0, Op1
13305 // pcmpeq t, <0..0>
13306 switch (SetCCOpcode) {
13308 case ISD::SETULT: {
13309 // If the comparison is against a constant we can turn this into a
13310 // setule. With psubus, setule does not require a swap. This is
13311 // beneficial because the constant in the register is no longer
13312 // destructed as the destination so it can be hoisted out of a loop.
13313 // Only do this pre-AVX since vpcmp* is no longer destructive.
13314 if (Subtarget->hasAVX())
13316 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13317 if (ULEOp1.getNode()) {
13319 Subus = true; Invert = false; Swap = false;
13323 // Psubus is better than flip-sign because it requires no inversion.
13324 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13325 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13329 Opc = X86ISD::SUBUS;
13335 std::swap(Op0, Op1);
13337 // Check that the operation in question is available (most are plain SSE2,
13338 // but PCMPGTQ and PCMPEQQ have different requirements).
13339 if (VT == MVT::v2i64) {
13340 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13341 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13343 // First cast everything to the right type.
13344 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13345 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13347 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13348 // bits of the inputs before performing those operations. The lower
13349 // compare is always unsigned.
13352 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13354 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13355 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13356 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13357 Sign, Zero, Sign, Zero);
13359 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13360 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13362 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13363 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13364 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13366 // Create masks for only the low parts/high parts of the 64 bit integers.
13367 static const int MaskHi[] = { 1, 1, 3, 3 };
13368 static const int MaskLo[] = { 0, 0, 2, 2 };
13369 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13370 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13371 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13373 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13374 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13377 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13379 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13382 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13383 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13384 // pcmpeqd + pshufd + pand.
13385 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13387 // First cast everything to the right type.
13388 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13389 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13392 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13394 // Make sure the lower and upper halves are both all-ones.
13395 static const int Mask[] = { 1, 0, 3, 2 };
13396 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13397 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13400 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13402 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13406 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13407 // bits of the inputs before performing those operations.
13409 EVT EltVT = VT.getVectorElementType();
13410 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13412 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13413 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13416 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13418 // If the logical-not of the result is required, perform that now.
13420 Result = DAG.getNOT(dl, Result, VT);
13423 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13426 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13427 getZeroVector(VT, Subtarget, DAG, dl));
13432 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13434 MVT VT = Op.getSimpleValueType();
13436 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13438 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13439 && "SetCC type must be 8-bit or 1-bit integer");
13440 SDValue Op0 = Op.getOperand(0);
13441 SDValue Op1 = Op.getOperand(1);
13443 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13445 // Optimize to BT if possible.
13446 // Lower (X & (1 << N)) == 0 to BT(X, N).
13447 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13448 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13449 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13450 Op1.getOpcode() == ISD::Constant &&
13451 cast<ConstantSDNode>(Op1)->isNullValue() &&
13452 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13453 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13454 if (NewSetCC.getNode()) {
13456 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13461 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13463 if (Op1.getOpcode() == ISD::Constant &&
13464 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13465 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13466 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13468 // If the input is a setcc, then reuse the input setcc or use a new one with
13469 // the inverted condition.
13470 if (Op0.getOpcode() == X86ISD::SETCC) {
13471 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13472 bool Invert = (CC == ISD::SETNE) ^
13473 cast<ConstantSDNode>(Op1)->isNullValue();
13477 CCode = X86::GetOppositeBranchCondition(CCode);
13478 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13479 DAG.getConstant(CCode, dl, MVT::i8),
13480 Op0.getOperand(1));
13482 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13486 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13487 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13488 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13490 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13491 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13494 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13495 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13496 if (X86CC == X86::COND_INVALID)
13499 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13500 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13501 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13502 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13504 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13508 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13509 static bool isX86LogicalCmp(SDValue Op) {
13510 unsigned Opc = Op.getNode()->getOpcode();
13511 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13512 Opc == X86ISD::SAHF)
13514 if (Op.getResNo() == 1 &&
13515 (Opc == X86ISD::ADD ||
13516 Opc == X86ISD::SUB ||
13517 Opc == X86ISD::ADC ||
13518 Opc == X86ISD::SBB ||
13519 Opc == X86ISD::SMUL ||
13520 Opc == X86ISD::UMUL ||
13521 Opc == X86ISD::INC ||
13522 Opc == X86ISD::DEC ||
13523 Opc == X86ISD::OR ||
13524 Opc == X86ISD::XOR ||
13525 Opc == X86ISD::AND))
13528 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13534 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13535 if (V.getOpcode() != ISD::TRUNCATE)
13538 SDValue VOp0 = V.getOperand(0);
13539 unsigned InBits = VOp0.getValueSizeInBits();
13540 unsigned Bits = V.getValueSizeInBits();
13541 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13544 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13545 bool addTest = true;
13546 SDValue Cond = Op.getOperand(0);
13547 SDValue Op1 = Op.getOperand(1);
13548 SDValue Op2 = Op.getOperand(2);
13550 EVT VT = Op1.getValueType();
13553 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13554 // are available or VBLENDV if AVX is available.
13555 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13556 if (Cond.getOpcode() == ISD::SETCC &&
13557 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13558 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13559 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13560 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13561 int SSECC = translateX86FSETCC(
13562 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13565 if (Subtarget->hasAVX512()) {
13566 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13567 DAG.getConstant(SSECC, DL, MVT::i8));
13568 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13571 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13572 DAG.getConstant(SSECC, DL, MVT::i8));
13574 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13575 // of 3 logic instructions for size savings and potentially speed.
13576 // Unfortunately, there is no scalar form of VBLENDV.
13578 // If either operand is a constant, don't try this. We can expect to
13579 // optimize away at least one of the logic instructions later in that
13580 // case, so that sequence would be faster than a variable blend.
13582 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13583 // uses XMM0 as the selection register. That may need just as many
13584 // instructions as the AND/ANDN/OR sequence due to register moves, so
13587 if (Subtarget->hasAVX() &&
13588 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13590 // Convert to vectors, do a VSELECT, and convert back to scalar.
13591 // All of the conversions should be optimized away.
13593 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13594 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13595 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13596 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13598 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13599 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13601 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13603 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13604 VSel, DAG.getIntPtrConstant(0, DL));
13606 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13607 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13608 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13612 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13613 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13614 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13615 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13616 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13617 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13618 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13620 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13623 if (Cond.getOpcode() == ISD::SETCC) {
13624 SDValue NewCond = LowerSETCC(Cond, DAG);
13625 if (NewCond.getNode())
13629 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13630 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13631 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13632 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13633 if (Cond.getOpcode() == X86ISD::SETCC &&
13634 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13635 isZero(Cond.getOperand(1).getOperand(1))) {
13636 SDValue Cmp = Cond.getOperand(1);
13638 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13640 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13641 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13642 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13644 SDValue CmpOp0 = Cmp.getOperand(0);
13645 // Apply further optimizations for special cases
13646 // (select (x != 0), -1, 0) -> neg & sbb
13647 // (select (x == 0), 0, -1) -> neg & sbb
13648 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13649 if (YC->isNullValue() &&
13650 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13651 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13652 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13653 DAG.getConstant(0, DL,
13654 CmpOp0.getValueType()),
13656 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13657 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13658 SDValue(Neg.getNode(), 1));
13662 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13663 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13664 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13666 SDValue Res = // Res = 0 or -1.
13667 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13668 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13670 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13671 Res = DAG.getNOT(DL, Res, Res.getValueType());
13673 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13674 if (!N2C || !N2C->isNullValue())
13675 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13680 // Look past (and (setcc_carry (cmp ...)), 1).
13681 if (Cond.getOpcode() == ISD::AND &&
13682 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13683 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13684 if (C && C->getAPIntValue() == 1)
13685 Cond = Cond.getOperand(0);
13688 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13689 // setting operand in place of the X86ISD::SETCC.
13690 unsigned CondOpcode = Cond.getOpcode();
13691 if (CondOpcode == X86ISD::SETCC ||
13692 CondOpcode == X86ISD::SETCC_CARRY) {
13693 CC = Cond.getOperand(0);
13695 SDValue Cmp = Cond.getOperand(1);
13696 unsigned Opc = Cmp.getOpcode();
13697 MVT VT = Op.getSimpleValueType();
13699 bool IllegalFPCMov = false;
13700 if (VT.isFloatingPoint() && !VT.isVector() &&
13701 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13702 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13704 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13705 Opc == X86ISD::BT) { // FIXME
13709 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13710 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13711 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13712 Cond.getOperand(0).getValueType() != MVT::i8)) {
13713 SDValue LHS = Cond.getOperand(0);
13714 SDValue RHS = Cond.getOperand(1);
13715 unsigned X86Opcode;
13718 switch (CondOpcode) {
13719 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13720 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13721 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13722 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13723 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13724 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13725 default: llvm_unreachable("unexpected overflowing operator");
13727 if (CondOpcode == ISD::UMULO)
13728 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13731 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13733 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13735 if (CondOpcode == ISD::UMULO)
13736 Cond = X86Op.getValue(2);
13738 Cond = X86Op.getValue(1);
13740 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13745 // Look pass the truncate if the high bits are known zero.
13746 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13747 Cond = Cond.getOperand(0);
13749 // We know the result of AND is compared against zero. Try to match
13751 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13752 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13753 if (NewSetCC.getNode()) {
13754 CC = NewSetCC.getOperand(0);
13755 Cond = NewSetCC.getOperand(1);
13762 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13763 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13766 // a < b ? -1 : 0 -> RES = ~setcc_carry
13767 // a < b ? 0 : -1 -> RES = setcc_carry
13768 // a >= b ? -1 : 0 -> RES = setcc_carry
13769 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13770 if (Cond.getOpcode() == X86ISD::SUB) {
13771 Cond = ConvertCmpIfNecessary(Cond, DAG);
13772 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13774 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13775 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13776 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13777 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13779 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13780 return DAG.getNOT(DL, Res, Res.getValueType());
13785 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13786 // widen the cmov and push the truncate through. This avoids introducing a new
13787 // branch during isel and doesn't add any extensions.
13788 if (Op.getValueType() == MVT::i8 &&
13789 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13790 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13791 if (T1.getValueType() == T2.getValueType() &&
13792 // Blacklist CopyFromReg to avoid partial register stalls.
13793 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13794 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13795 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13796 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13800 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13801 // condition is true.
13802 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13803 SDValue Ops[] = { Op2, Op1, CC, Cond };
13804 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13807 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13808 SelectionDAG &DAG) {
13809 MVT VT = Op->getSimpleValueType(0);
13810 SDValue In = Op->getOperand(0);
13811 MVT InVT = In.getSimpleValueType();
13812 MVT VTElt = VT.getVectorElementType();
13813 MVT InVTElt = InVT.getVectorElementType();
13817 if ((InVTElt == MVT::i1) &&
13818 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13819 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13821 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13822 VTElt.getSizeInBits() <= 16)) ||
13824 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13825 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13827 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13828 VTElt.getSizeInBits() >= 32))))
13829 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13831 unsigned int NumElts = VT.getVectorNumElements();
13833 if (NumElts != 8 && NumElts != 16)
13836 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13837 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13838 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13839 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13842 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13843 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13845 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
13848 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
13850 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
13851 if (VT.is512BitVector())
13853 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
13856 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13857 SelectionDAG &DAG) {
13858 MVT VT = Op->getSimpleValueType(0);
13859 SDValue In = Op->getOperand(0);
13860 MVT InVT = In.getSimpleValueType();
13863 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13864 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13866 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13867 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13868 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13871 if (Subtarget->hasInt256())
13872 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13874 // Optimize vectors in AVX mode
13875 // Sign extend v8i16 to v8i32 and
13878 // Divide input vector into two parts
13879 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13880 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13881 // concat the vectors to original VT
13883 unsigned NumElems = InVT.getVectorNumElements();
13884 SDValue Undef = DAG.getUNDEF(InVT);
13886 SmallVector<int,8> ShufMask1(NumElems, -1);
13887 for (unsigned i = 0; i != NumElems/2; ++i)
13890 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13892 SmallVector<int,8> ShufMask2(NumElems, -1);
13893 for (unsigned i = 0; i != NumElems/2; ++i)
13894 ShufMask2[i] = i + NumElems/2;
13896 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13898 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13899 VT.getVectorNumElements()/2);
13901 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13902 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13904 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13907 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13908 // may emit an illegal shuffle but the expansion is still better than scalar
13909 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13910 // we'll emit a shuffle and a arithmetic shift.
13911 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13912 // TODO: It is possible to support ZExt by zeroing the undef values during
13913 // the shuffle phase or after the shuffle.
13914 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13915 SelectionDAG &DAG) {
13916 MVT RegVT = Op.getSimpleValueType();
13917 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13918 assert(RegVT.isInteger() &&
13919 "We only custom lower integer vector sext loads.");
13921 // Nothing useful we can do without SSE2 shuffles.
13922 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13924 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13926 EVT MemVT = Ld->getMemoryVT();
13927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13928 unsigned RegSz = RegVT.getSizeInBits();
13930 ISD::LoadExtType Ext = Ld->getExtensionType();
13932 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13933 && "Only anyext and sext are currently implemented.");
13934 assert(MemVT != RegVT && "Cannot extend to the same type");
13935 assert(MemVT.isVector() && "Must load a vector from memory");
13937 unsigned NumElems = RegVT.getVectorNumElements();
13938 unsigned MemSz = MemVT.getSizeInBits();
13939 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13941 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13942 // The only way in which we have a legal 256-bit vector result but not the
13943 // integer 256-bit operations needed to directly lower a sextload is if we
13944 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13945 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13946 // correctly legalized. We do this late to allow the canonical form of
13947 // sextload to persist throughout the rest of the DAG combiner -- it wants
13948 // to fold together any extensions it can, and so will fuse a sign_extend
13949 // of an sextload into a sextload targeting a wider value.
13951 if (MemSz == 128) {
13952 // Just switch this to a normal load.
13953 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13954 "it must be a legal 128-bit vector "
13956 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13957 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13958 Ld->isInvariant(), Ld->getAlignment());
13960 assert(MemSz < 128 &&
13961 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13962 // Do an sext load to a 128-bit vector type. We want to use the same
13963 // number of elements, but elements half as wide. This will end up being
13964 // recursively lowered by this routine, but will succeed as we definitely
13965 // have all the necessary features if we're using AVX1.
13967 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13968 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13970 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13971 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13972 Ld->isNonTemporal(), Ld->isInvariant(),
13973 Ld->getAlignment());
13976 // Replace chain users with the new chain.
13977 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13978 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13980 // Finally, do a normal sign-extend to the desired register.
13981 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13984 // All sizes must be a power of two.
13985 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13986 "Non-power-of-two elements are not custom lowered!");
13988 // Attempt to load the original value using scalar loads.
13989 // Find the largest scalar type that divides the total loaded size.
13990 MVT SclrLoadTy = MVT::i8;
13991 for (MVT Tp : MVT::integer_valuetypes()) {
13992 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13997 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13998 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14000 SclrLoadTy = MVT::f64;
14002 // Calculate the number of scalar loads that we need to perform
14003 // in order to load our vector from memory.
14004 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14006 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14007 "Can only lower sext loads with a single scalar load!");
14009 unsigned loadRegZize = RegSz;
14010 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14013 // Represent our vector as a sequence of elements which are the
14014 // largest scalar that we can load.
14015 EVT LoadUnitVecVT = EVT::getVectorVT(
14016 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14018 // Represent the data using the same element type that is stored in
14019 // memory. In practice, we ''widen'' MemVT.
14021 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14022 loadRegZize / MemVT.getScalarType().getSizeInBits());
14024 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14025 "Invalid vector type");
14027 // We can't shuffle using an illegal type.
14028 assert(TLI.isTypeLegal(WideVecVT) &&
14029 "We only lower types that form legal widened vector types");
14031 SmallVector<SDValue, 8> Chains;
14032 SDValue Ptr = Ld->getBasePtr();
14033 SDValue Increment =
14034 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14035 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14037 for (unsigned i = 0; i < NumLoads; ++i) {
14038 // Perform a single load.
14039 SDValue ScalarLoad =
14040 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14041 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14042 Ld->getAlignment());
14043 Chains.push_back(ScalarLoad.getValue(1));
14044 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14045 // another round of DAGCombining.
14047 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14049 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14050 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14052 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14055 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14057 // Bitcast the loaded value to a vector of the original element type, in
14058 // the size of the target vector type.
14059 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14060 unsigned SizeRatio = RegSz / MemSz;
14062 if (Ext == ISD::SEXTLOAD) {
14063 // If we have SSE4.1, we can directly emit a VSEXT node.
14064 if (Subtarget->hasSSE41()) {
14065 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14066 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14070 // Otherwise we'll shuffle the small elements in the high bits of the
14071 // larger type and perform an arithmetic shift. If the shift is not legal
14072 // it's better to scalarize.
14073 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14074 "We can't implement a sext load without an arithmetic right shift!");
14076 // Redistribute the loaded elements into the different locations.
14077 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14078 for (unsigned i = 0; i != NumElems; ++i)
14079 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14081 SDValue Shuff = DAG.getVectorShuffle(
14082 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14084 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14086 // Build the arithmetic shift.
14087 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14088 MemVT.getVectorElementType().getSizeInBits();
14090 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14091 DAG.getConstant(Amt, dl, RegVT));
14093 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14097 // Redistribute the loaded elements into the different locations.
14098 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14099 for (unsigned i = 0; i != NumElems; ++i)
14100 ShuffleVec[i * SizeRatio] = i;
14102 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14103 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14105 // Bitcast to the requested type.
14106 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14107 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14111 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14112 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14113 // from the AND / OR.
14114 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14115 Opc = Op.getOpcode();
14116 if (Opc != ISD::OR && Opc != ISD::AND)
14118 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14119 Op.getOperand(0).hasOneUse() &&
14120 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14121 Op.getOperand(1).hasOneUse());
14124 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14125 // 1 and that the SETCC node has a single use.
14126 static bool isXor1OfSetCC(SDValue Op) {
14127 if (Op.getOpcode() != ISD::XOR)
14129 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14130 if (N1C && N1C->getAPIntValue() == 1) {
14131 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14132 Op.getOperand(0).hasOneUse();
14137 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14138 bool addTest = true;
14139 SDValue Chain = Op.getOperand(0);
14140 SDValue Cond = Op.getOperand(1);
14141 SDValue Dest = Op.getOperand(2);
14144 bool Inverted = false;
14146 if (Cond.getOpcode() == ISD::SETCC) {
14147 // Check for setcc([su]{add,sub,mul}o == 0).
14148 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14149 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14150 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14151 Cond.getOperand(0).getResNo() == 1 &&
14152 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14153 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14154 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14155 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14156 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14157 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14159 Cond = Cond.getOperand(0);
14161 SDValue NewCond = LowerSETCC(Cond, DAG);
14162 if (NewCond.getNode())
14167 // FIXME: LowerXALUO doesn't handle these!!
14168 else if (Cond.getOpcode() == X86ISD::ADD ||
14169 Cond.getOpcode() == X86ISD::SUB ||
14170 Cond.getOpcode() == X86ISD::SMUL ||
14171 Cond.getOpcode() == X86ISD::UMUL)
14172 Cond = LowerXALUO(Cond, DAG);
14175 // Look pass (and (setcc_carry (cmp ...)), 1).
14176 if (Cond.getOpcode() == ISD::AND &&
14177 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14178 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14179 if (C && C->getAPIntValue() == 1)
14180 Cond = Cond.getOperand(0);
14183 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14184 // setting operand in place of the X86ISD::SETCC.
14185 unsigned CondOpcode = Cond.getOpcode();
14186 if (CondOpcode == X86ISD::SETCC ||
14187 CondOpcode == X86ISD::SETCC_CARRY) {
14188 CC = Cond.getOperand(0);
14190 SDValue Cmp = Cond.getOperand(1);
14191 unsigned Opc = Cmp.getOpcode();
14192 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14193 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14197 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14201 // These can only come from an arithmetic instruction with overflow,
14202 // e.g. SADDO, UADDO.
14203 Cond = Cond.getNode()->getOperand(1);
14209 CondOpcode = Cond.getOpcode();
14210 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14211 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14212 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14213 Cond.getOperand(0).getValueType() != MVT::i8)) {
14214 SDValue LHS = Cond.getOperand(0);
14215 SDValue RHS = Cond.getOperand(1);
14216 unsigned X86Opcode;
14219 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14220 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14222 switch (CondOpcode) {
14223 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14225 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14227 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14230 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14231 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14233 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14235 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14238 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14239 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14240 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14241 default: llvm_unreachable("unexpected overflowing operator");
14244 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14245 if (CondOpcode == ISD::UMULO)
14246 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14249 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14251 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14253 if (CondOpcode == ISD::UMULO)
14254 Cond = X86Op.getValue(2);
14256 Cond = X86Op.getValue(1);
14258 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14262 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14263 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14264 if (CondOpc == ISD::OR) {
14265 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14266 // two branches instead of an explicit OR instruction with a
14268 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14269 isX86LogicalCmp(Cmp)) {
14270 CC = Cond.getOperand(0).getOperand(0);
14271 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14272 Chain, Dest, CC, Cmp);
14273 CC = Cond.getOperand(1).getOperand(0);
14277 } else { // ISD::AND
14278 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14279 // two branches instead of an explicit AND instruction with a
14280 // separate test. However, we only do this if this block doesn't
14281 // have a fall-through edge, because this requires an explicit
14282 // jmp when the condition is false.
14283 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14284 isX86LogicalCmp(Cmp) &&
14285 Op.getNode()->hasOneUse()) {
14286 X86::CondCode CCode =
14287 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14288 CCode = X86::GetOppositeBranchCondition(CCode);
14289 CC = DAG.getConstant(CCode, dl, MVT::i8);
14290 SDNode *User = *Op.getNode()->use_begin();
14291 // Look for an unconditional branch following this conditional branch.
14292 // We need this because we need to reverse the successors in order
14293 // to implement FCMP_OEQ.
14294 if (User->getOpcode() == ISD::BR) {
14295 SDValue FalseBB = User->getOperand(1);
14297 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14298 assert(NewBR == User);
14302 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14303 Chain, Dest, CC, Cmp);
14304 X86::CondCode CCode =
14305 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14306 CCode = X86::GetOppositeBranchCondition(CCode);
14307 CC = DAG.getConstant(CCode, dl, MVT::i8);
14313 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14314 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14315 // It should be transformed during dag combiner except when the condition
14316 // is set by a arithmetics with overflow node.
14317 X86::CondCode CCode =
14318 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14319 CCode = X86::GetOppositeBranchCondition(CCode);
14320 CC = DAG.getConstant(CCode, dl, MVT::i8);
14321 Cond = Cond.getOperand(0).getOperand(1);
14323 } else if (Cond.getOpcode() == ISD::SETCC &&
14324 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14325 // For FCMP_OEQ, we can emit
14326 // two branches instead of an explicit AND instruction with a
14327 // separate test. However, we only do this if this block doesn't
14328 // have a fall-through edge, because this requires an explicit
14329 // jmp when the condition is false.
14330 if (Op.getNode()->hasOneUse()) {
14331 SDNode *User = *Op.getNode()->use_begin();
14332 // Look for an unconditional branch following this conditional branch.
14333 // We need this because we need to reverse the successors in order
14334 // to implement FCMP_OEQ.
14335 if (User->getOpcode() == ISD::BR) {
14336 SDValue FalseBB = User->getOperand(1);
14338 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14339 assert(NewBR == User);
14343 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14344 Cond.getOperand(0), Cond.getOperand(1));
14345 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14346 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14347 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14348 Chain, Dest, CC, Cmp);
14349 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14354 } else if (Cond.getOpcode() == ISD::SETCC &&
14355 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14356 // For FCMP_UNE, we can emit
14357 // two branches instead of an explicit AND instruction with a
14358 // separate test. However, we only do this if this block doesn't
14359 // have a fall-through edge, because this requires an explicit
14360 // jmp when the condition is false.
14361 if (Op.getNode()->hasOneUse()) {
14362 SDNode *User = *Op.getNode()->use_begin();
14363 // Look for an unconditional branch following this conditional branch.
14364 // We need this because we need to reverse the successors in order
14365 // to implement FCMP_UNE.
14366 if (User->getOpcode() == ISD::BR) {
14367 SDValue FalseBB = User->getOperand(1);
14369 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14370 assert(NewBR == User);
14373 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14374 Cond.getOperand(0), Cond.getOperand(1));
14375 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14376 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14377 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14378 Chain, Dest, CC, Cmp);
14379 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14389 // Look pass the truncate if the high bits are known zero.
14390 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14391 Cond = Cond.getOperand(0);
14393 // We know the result of AND is compared against zero. Try to match
14395 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14396 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14397 if (NewSetCC.getNode()) {
14398 CC = NewSetCC.getOperand(0);
14399 Cond = NewSetCC.getOperand(1);
14406 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14407 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14408 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14410 Cond = ConvertCmpIfNecessary(Cond, DAG);
14411 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14412 Chain, Dest, CC, Cond);
14415 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14416 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14417 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14418 // that the guard pages used by the OS virtual memory manager are allocated in
14419 // correct sequence.
14421 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14422 SelectionDAG &DAG) const {
14423 MachineFunction &MF = DAG.getMachineFunction();
14424 bool SplitStack = MF.shouldSplitStack();
14425 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14430 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14431 SDNode* Node = Op.getNode();
14433 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14434 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14435 " not tell us which reg is the stack pointer!");
14436 EVT VT = Node->getValueType(0);
14437 SDValue Tmp1 = SDValue(Node, 0);
14438 SDValue Tmp2 = SDValue(Node, 1);
14439 SDValue Tmp3 = Node->getOperand(2);
14440 SDValue Chain = Tmp1.getOperand(0);
14442 // Chain the dynamic stack allocation so that it doesn't modify the stack
14443 // pointer when other instructions are using the stack.
14444 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14447 SDValue Size = Tmp2.getOperand(1);
14448 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14449 Chain = SP.getValue(1);
14450 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14451 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14452 unsigned StackAlign = TFI.getStackAlignment();
14453 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14454 if (Align > StackAlign)
14455 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14456 DAG.getConstant(-(uint64_t)Align, dl, VT));
14457 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14459 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14460 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14463 SDValue Ops[2] = { Tmp1, Tmp2 };
14464 return DAG.getMergeValues(Ops, dl);
14468 SDValue Chain = Op.getOperand(0);
14469 SDValue Size = Op.getOperand(1);
14470 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14471 EVT VT = Op.getNode()->getValueType(0);
14473 bool Is64Bit = Subtarget->is64Bit();
14474 EVT SPTy = getPointerTy();
14477 MachineRegisterInfo &MRI = MF.getRegInfo();
14480 // The 64 bit implementation of segmented stacks needs to clobber both r10
14481 // r11. This makes it impossible to use it along with nested parameters.
14482 const Function *F = MF.getFunction();
14484 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14486 if (I->hasNestAttr())
14487 report_fatal_error("Cannot use segmented stacks with functions that "
14488 "have nested arguments.");
14491 const TargetRegisterClass *AddrRegClass =
14492 getRegClassFor(getPointerTy());
14493 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14494 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14495 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14496 DAG.getRegister(Vreg, SPTy));
14497 SDValue Ops1[2] = { Value, Chain };
14498 return DAG.getMergeValues(Ops1, dl);
14501 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14503 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14504 Flag = Chain.getValue(1);
14505 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14507 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14509 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14510 unsigned SPReg = RegInfo->getStackRegister();
14511 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14512 Chain = SP.getValue(1);
14515 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14516 DAG.getConstant(-(uint64_t)Align, dl, VT));
14517 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14520 SDValue Ops1[2] = { SP, Chain };
14521 return DAG.getMergeValues(Ops1, dl);
14525 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14526 MachineFunction &MF = DAG.getMachineFunction();
14527 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14529 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14532 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14533 // vastart just stores the address of the VarArgsFrameIndex slot into the
14534 // memory location argument.
14535 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14537 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14538 MachinePointerInfo(SV), false, false, 0);
14542 // gp_offset (0 - 6 * 8)
14543 // fp_offset (48 - 48 + 8 * 16)
14544 // overflow_arg_area (point to parameters coming in memory).
14546 SmallVector<SDValue, 8> MemOps;
14547 SDValue FIN = Op.getOperand(1);
14549 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14550 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14552 FIN, MachinePointerInfo(SV), false, false, 0);
14553 MemOps.push_back(Store);
14556 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14557 FIN, DAG.getIntPtrConstant(4, DL));
14558 Store = DAG.getStore(Op.getOperand(0), DL,
14559 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14561 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14562 MemOps.push_back(Store);
14564 // Store ptr to overflow_arg_area
14565 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14566 FIN, DAG.getIntPtrConstant(4, DL));
14567 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14569 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14570 MachinePointerInfo(SV, 8),
14572 MemOps.push_back(Store);
14574 // Store ptr to reg_save_area.
14575 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14576 FIN, DAG.getIntPtrConstant(8, DL));
14577 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14579 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14580 MachinePointerInfo(SV, 16), false, false, 0);
14581 MemOps.push_back(Store);
14582 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14585 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14586 assert(Subtarget->is64Bit() &&
14587 "LowerVAARG only handles 64-bit va_arg!");
14588 assert((Subtarget->isTargetLinux() ||
14589 Subtarget->isTargetDarwin()) &&
14590 "Unhandled target in LowerVAARG");
14591 assert(Op.getNode()->getNumOperands() == 4);
14592 SDValue Chain = Op.getOperand(0);
14593 SDValue SrcPtr = Op.getOperand(1);
14594 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14595 unsigned Align = Op.getConstantOperandVal(3);
14598 EVT ArgVT = Op.getNode()->getValueType(0);
14599 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14600 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14603 // Decide which area this value should be read from.
14604 // TODO: Implement the AMD64 ABI in its entirety. This simple
14605 // selection mechanism works only for the basic types.
14606 if (ArgVT == MVT::f80) {
14607 llvm_unreachable("va_arg for f80 not yet implemented");
14608 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14609 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14610 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14611 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14613 llvm_unreachable("Unhandled argument type in LowerVAARG");
14616 if (ArgMode == 2) {
14617 // Sanity Check: Make sure using fp_offset makes sense.
14618 assert(!Subtarget->useSoftFloat() &&
14619 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14620 Attribute::NoImplicitFloat)) &&
14621 Subtarget->hasSSE1());
14624 // Insert VAARG_64 node into the DAG
14625 // VAARG_64 returns two values: Variable Argument Address, Chain
14626 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14627 DAG.getConstant(ArgMode, dl, MVT::i8),
14628 DAG.getConstant(Align, dl, MVT::i32)};
14629 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14630 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14631 VTs, InstOps, MVT::i64,
14632 MachinePointerInfo(SV),
14634 /*Volatile=*/false,
14636 /*WriteMem=*/true);
14637 Chain = VAARG.getValue(1);
14639 // Load the next argument and return it
14640 return DAG.getLoad(ArgVT, dl,
14643 MachinePointerInfo(),
14644 false, false, false, 0);
14647 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14648 SelectionDAG &DAG) {
14649 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14650 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14651 SDValue Chain = Op.getOperand(0);
14652 SDValue DstPtr = Op.getOperand(1);
14653 SDValue SrcPtr = Op.getOperand(2);
14654 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14655 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14658 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14659 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14661 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14664 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14665 // amount is a constant. Takes immediate version of shift as input.
14666 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14667 SDValue SrcOp, uint64_t ShiftAmt,
14668 SelectionDAG &DAG) {
14669 MVT ElementType = VT.getVectorElementType();
14671 // Fold this packed shift into its first operand if ShiftAmt is 0.
14675 // Check for ShiftAmt >= element width
14676 if (ShiftAmt >= ElementType.getSizeInBits()) {
14677 if (Opc == X86ISD::VSRAI)
14678 ShiftAmt = ElementType.getSizeInBits() - 1;
14680 return DAG.getConstant(0, dl, VT);
14683 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14684 && "Unknown target vector shift-by-constant node");
14686 // Fold this packed vector shift into a build vector if SrcOp is a
14687 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14688 if (VT == SrcOp.getSimpleValueType() &&
14689 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14690 SmallVector<SDValue, 8> Elts;
14691 unsigned NumElts = SrcOp->getNumOperands();
14692 ConstantSDNode *ND;
14695 default: llvm_unreachable(nullptr);
14696 case X86ISD::VSHLI:
14697 for (unsigned i=0; i!=NumElts; ++i) {
14698 SDValue CurrentOp = SrcOp->getOperand(i);
14699 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14700 Elts.push_back(CurrentOp);
14703 ND = cast<ConstantSDNode>(CurrentOp);
14704 const APInt &C = ND->getAPIntValue();
14705 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14708 case X86ISD::VSRLI:
14709 for (unsigned i=0; i!=NumElts; ++i) {
14710 SDValue CurrentOp = SrcOp->getOperand(i);
14711 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14712 Elts.push_back(CurrentOp);
14715 ND = cast<ConstantSDNode>(CurrentOp);
14716 const APInt &C = ND->getAPIntValue();
14717 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14720 case X86ISD::VSRAI:
14721 for (unsigned i=0; i!=NumElts; ++i) {
14722 SDValue CurrentOp = SrcOp->getOperand(i);
14723 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14724 Elts.push_back(CurrentOp);
14727 ND = cast<ConstantSDNode>(CurrentOp);
14728 const APInt &C = ND->getAPIntValue();
14729 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14734 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14737 return DAG.getNode(Opc, dl, VT, SrcOp,
14738 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14741 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14742 // may or may not be a constant. Takes immediate version of shift as input.
14743 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14744 SDValue SrcOp, SDValue ShAmt,
14745 SelectionDAG &DAG) {
14746 MVT SVT = ShAmt.getSimpleValueType();
14747 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14749 // Catch shift-by-constant.
14750 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14751 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14752 CShAmt->getZExtValue(), DAG);
14754 // Change opcode to non-immediate version
14756 default: llvm_unreachable("Unknown target vector shift node");
14757 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14758 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14759 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14762 const X86Subtarget &Subtarget =
14763 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14764 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14765 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14766 // Let the shuffle legalizer expand this shift amount node.
14767 SDValue Op0 = ShAmt.getOperand(0);
14768 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14769 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14771 // Need to build a vector containing shift amount.
14772 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14773 SmallVector<SDValue, 4> ShOps;
14774 ShOps.push_back(ShAmt);
14775 if (SVT == MVT::i32) {
14776 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14777 ShOps.push_back(DAG.getUNDEF(SVT));
14779 ShOps.push_back(DAG.getUNDEF(SVT));
14781 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14782 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14785 // The return type has to be a 128-bit type with the same element
14786 // type as the input type.
14787 MVT EltVT = VT.getVectorElementType();
14788 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14790 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14791 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14794 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14795 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14796 /// necessary casting for \p Mask when lowering masking intrinsics.
14797 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14798 SDValue PreservedSrc,
14799 const X86Subtarget *Subtarget,
14800 SelectionDAG &DAG) {
14801 EVT VT = Op.getValueType();
14802 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14803 MVT::i1, VT.getVectorNumElements());
14804 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14805 Mask.getValueType().getSizeInBits());
14808 assert(MaskVT.isSimple() && "invalid mask type");
14810 if (isAllOnes(Mask))
14813 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14814 // are extracted by EXTRACT_SUBVECTOR.
14815 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14816 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14817 DAG.getIntPtrConstant(0, dl));
14819 switch (Op.getOpcode()) {
14821 case X86ISD::PCMPEQM:
14822 case X86ISD::PCMPGTM:
14824 case X86ISD::CMPMU:
14825 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14827 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14828 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14829 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14832 /// \brief Creates an SDNode for a predicated scalar operation.
14833 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14834 /// The mask is comming as MVT::i8 and it should be truncated
14835 /// to MVT::i1 while lowering masking intrinsics.
14836 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14837 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14838 /// a scalar instruction.
14839 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14840 SDValue PreservedSrc,
14841 const X86Subtarget *Subtarget,
14842 SelectionDAG &DAG) {
14843 if (isAllOnes(Mask))
14846 EVT VT = Op.getValueType();
14848 // The mask should be of type MVT::i1
14849 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14851 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14852 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14853 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14856 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14857 SelectionDAG &DAG) {
14859 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14860 EVT VT = Op.getValueType();
14861 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14863 switch(IntrData->Type) {
14864 case INTR_TYPE_1OP:
14865 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14866 case INTR_TYPE_2OP:
14867 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14869 case INTR_TYPE_3OP:
14870 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14871 Op.getOperand(2), Op.getOperand(3));
14872 case INTR_TYPE_1OP_MASK_RM: {
14873 SDValue Src = Op.getOperand(1);
14874 SDValue Src0 = Op.getOperand(2);
14875 SDValue Mask = Op.getOperand(3);
14876 SDValue RoundingMode = Op.getOperand(4);
14877 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14879 Mask, Src0, Subtarget, DAG);
14881 case INTR_TYPE_SCALAR_MASK_RM: {
14882 SDValue Src1 = Op.getOperand(1);
14883 SDValue Src2 = Op.getOperand(2);
14884 SDValue Src0 = Op.getOperand(3);
14885 SDValue Mask = Op.getOperand(4);
14886 // There are 2 kinds of intrinsics in this group:
14887 // (1) With supress-all-exceptions (sae) - 6 operands
14888 // (2) With rounding mode and sae - 7 operands.
14889 if (Op.getNumOperands() == 6) {
14890 SDValue Sae = Op.getOperand(5);
14891 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14893 Mask, Src0, Subtarget, DAG);
14895 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
14896 SDValue RoundingMode = Op.getOperand(5);
14897 SDValue Sae = Op.getOperand(6);
14898 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14899 RoundingMode, Sae),
14900 Mask, Src0, Subtarget, DAG);
14902 case INTR_TYPE_2OP_MASK: {
14903 SDValue Src1 = Op.getOperand(1);
14904 SDValue Src2 = Op.getOperand(2);
14905 SDValue PassThru = Op.getOperand(3);
14906 SDValue Mask = Op.getOperand(4);
14907 // We specify 2 possible opcodes for intrinsics with rounding modes.
14908 // First, we check if the intrinsic may have non-default rounding mode,
14909 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14910 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14911 if (IntrWithRoundingModeOpcode != 0) {
14912 SDValue Rnd = Op.getOperand(5);
14913 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14914 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14915 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14916 dl, Op.getValueType(),
14918 Mask, PassThru, Subtarget, DAG);
14921 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14923 Mask, PassThru, Subtarget, DAG);
14925 case FMA_OP_MASK: {
14926 SDValue Src1 = Op.getOperand(1);
14927 SDValue Src2 = Op.getOperand(2);
14928 SDValue Src3 = Op.getOperand(3);
14929 SDValue Mask = Op.getOperand(4);
14930 // We specify 2 possible opcodes for intrinsics with rounding modes.
14931 // First, we check if the intrinsic may have non-default rounding mode,
14932 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14933 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14934 if (IntrWithRoundingModeOpcode != 0) {
14935 SDValue Rnd = Op.getOperand(5);
14936 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14937 X86::STATIC_ROUNDING::CUR_DIRECTION)
14938 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14939 dl, Op.getValueType(),
14940 Src1, Src2, Src3, Rnd),
14941 Mask, Src1, Subtarget, DAG);
14943 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14944 dl, Op.getValueType(),
14946 Mask, Src1, Subtarget, DAG);
14949 case CMP_MASK_CC: {
14950 // Comparison intrinsics with masks.
14951 // Example of transformation:
14952 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14953 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14955 // (v8i1 (insert_subvector undef,
14956 // (v2i1 (and (PCMPEQM %a, %b),
14957 // (extract_subvector
14958 // (v8i1 (bitcast %mask)), 0))), 0))))
14959 EVT VT = Op.getOperand(1).getValueType();
14960 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14961 VT.getVectorNumElements());
14962 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14963 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14964 Mask.getValueType().getSizeInBits());
14966 if (IntrData->Type == CMP_MASK_CC) {
14967 SDValue CC = Op.getOperand(3);
14968 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
14969 // We specify 2 possible opcodes for intrinsics with rounding modes.
14970 // First, we check if the intrinsic may have non-default rounding mode,
14971 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14972 if (IntrData->Opc1 != 0) {
14973 SDValue Rnd = Op.getOperand(5);
14974 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14975 X86::STATIC_ROUNDING::CUR_DIRECTION)
14976 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
14977 Op.getOperand(2), CC, Rnd);
14979 //default rounding mode
14981 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14982 Op.getOperand(2), CC);
14985 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14986 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14989 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
14990 DAG.getTargetConstant(0, dl,
14993 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
14994 DAG.getUNDEF(BitcastVT), CmpMask,
14995 DAG.getIntPtrConstant(0, dl));
14996 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
14998 case COMI: { // Comparison intrinsics
14999 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15000 SDValue LHS = Op.getOperand(1);
15001 SDValue RHS = Op.getOperand(2);
15002 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15003 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15004 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15005 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15006 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15007 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15010 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15011 Op.getOperand(1), Op.getOperand(2), DAG);
15013 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15014 Op.getSimpleValueType(),
15016 Op.getOperand(2), DAG),
15017 Op.getOperand(4), Op.getOperand(3), Subtarget,
15019 case COMPRESS_EXPAND_IN_REG: {
15020 SDValue Mask = Op.getOperand(3);
15021 SDValue DataToCompress = Op.getOperand(1);
15022 SDValue PassThru = Op.getOperand(2);
15023 if (isAllOnes(Mask)) // return data as is
15024 return Op.getOperand(1);
15025 EVT VT = Op.getValueType();
15026 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15027 VT.getVectorNumElements());
15028 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15029 Mask.getValueType().getSizeInBits());
15031 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15032 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15033 DAG.getIntPtrConstant(0, dl));
15035 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15039 SDValue Mask = Op.getOperand(3);
15040 EVT VT = Op.getValueType();
15041 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15042 VT.getVectorNumElements());
15043 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15044 Mask.getValueType().getSizeInBits());
15046 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15047 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15048 DAG.getIntPtrConstant(0, dl));
15049 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15058 default: return SDValue(); // Don't custom lower most intrinsics.
15060 case Intrinsic::x86_avx2_permd:
15061 case Intrinsic::x86_avx2_permps:
15062 // Operands intentionally swapped. Mask is last operand to intrinsic,
15063 // but second operand for node/instruction.
15064 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15065 Op.getOperand(2), Op.getOperand(1));
15067 case Intrinsic::x86_avx512_mask_valign_q_512:
15068 case Intrinsic::x86_avx512_mask_valign_d_512:
15069 // Vector source operands are swapped.
15070 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15071 Op.getValueType(), Op.getOperand(2),
15074 Op.getOperand(5), Op.getOperand(4),
15077 // ptest and testp intrinsics. The intrinsic these come from are designed to
15078 // return an integer value, not just an instruction so lower it to the ptest
15079 // or testp pattern and a setcc for the result.
15080 case Intrinsic::x86_sse41_ptestz:
15081 case Intrinsic::x86_sse41_ptestc:
15082 case Intrinsic::x86_sse41_ptestnzc:
15083 case Intrinsic::x86_avx_ptestz_256:
15084 case Intrinsic::x86_avx_ptestc_256:
15085 case Intrinsic::x86_avx_ptestnzc_256:
15086 case Intrinsic::x86_avx_vtestz_ps:
15087 case Intrinsic::x86_avx_vtestc_ps:
15088 case Intrinsic::x86_avx_vtestnzc_ps:
15089 case Intrinsic::x86_avx_vtestz_pd:
15090 case Intrinsic::x86_avx_vtestc_pd:
15091 case Intrinsic::x86_avx_vtestnzc_pd:
15092 case Intrinsic::x86_avx_vtestz_ps_256:
15093 case Intrinsic::x86_avx_vtestc_ps_256:
15094 case Intrinsic::x86_avx_vtestnzc_ps_256:
15095 case Intrinsic::x86_avx_vtestz_pd_256:
15096 case Intrinsic::x86_avx_vtestc_pd_256:
15097 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15098 bool IsTestPacked = false;
15101 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15102 case Intrinsic::x86_avx_vtestz_ps:
15103 case Intrinsic::x86_avx_vtestz_pd:
15104 case Intrinsic::x86_avx_vtestz_ps_256:
15105 case Intrinsic::x86_avx_vtestz_pd_256:
15106 IsTestPacked = true; // Fallthrough
15107 case Intrinsic::x86_sse41_ptestz:
15108 case Intrinsic::x86_avx_ptestz_256:
15110 X86CC = X86::COND_E;
15112 case Intrinsic::x86_avx_vtestc_ps:
15113 case Intrinsic::x86_avx_vtestc_pd:
15114 case Intrinsic::x86_avx_vtestc_ps_256:
15115 case Intrinsic::x86_avx_vtestc_pd_256:
15116 IsTestPacked = true; // Fallthrough
15117 case Intrinsic::x86_sse41_ptestc:
15118 case Intrinsic::x86_avx_ptestc_256:
15120 X86CC = X86::COND_B;
15122 case Intrinsic::x86_avx_vtestnzc_ps:
15123 case Intrinsic::x86_avx_vtestnzc_pd:
15124 case Intrinsic::x86_avx_vtestnzc_ps_256:
15125 case Intrinsic::x86_avx_vtestnzc_pd_256:
15126 IsTestPacked = true; // Fallthrough
15127 case Intrinsic::x86_sse41_ptestnzc:
15128 case Intrinsic::x86_avx_ptestnzc_256:
15130 X86CC = X86::COND_A;
15134 SDValue LHS = Op.getOperand(1);
15135 SDValue RHS = Op.getOperand(2);
15136 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15137 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15138 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15139 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15140 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15142 case Intrinsic::x86_avx512_kortestz_w:
15143 case Intrinsic::x86_avx512_kortestc_w: {
15144 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15145 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15146 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15147 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15148 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15149 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15150 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15153 case Intrinsic::x86_sse42_pcmpistria128:
15154 case Intrinsic::x86_sse42_pcmpestria128:
15155 case Intrinsic::x86_sse42_pcmpistric128:
15156 case Intrinsic::x86_sse42_pcmpestric128:
15157 case Intrinsic::x86_sse42_pcmpistrio128:
15158 case Intrinsic::x86_sse42_pcmpestrio128:
15159 case Intrinsic::x86_sse42_pcmpistris128:
15160 case Intrinsic::x86_sse42_pcmpestris128:
15161 case Intrinsic::x86_sse42_pcmpistriz128:
15162 case Intrinsic::x86_sse42_pcmpestriz128: {
15166 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15167 case Intrinsic::x86_sse42_pcmpistria128:
15168 Opcode = X86ISD::PCMPISTRI;
15169 X86CC = X86::COND_A;
15171 case Intrinsic::x86_sse42_pcmpestria128:
15172 Opcode = X86ISD::PCMPESTRI;
15173 X86CC = X86::COND_A;
15175 case Intrinsic::x86_sse42_pcmpistric128:
15176 Opcode = X86ISD::PCMPISTRI;
15177 X86CC = X86::COND_B;
15179 case Intrinsic::x86_sse42_pcmpestric128:
15180 Opcode = X86ISD::PCMPESTRI;
15181 X86CC = X86::COND_B;
15183 case Intrinsic::x86_sse42_pcmpistrio128:
15184 Opcode = X86ISD::PCMPISTRI;
15185 X86CC = X86::COND_O;
15187 case Intrinsic::x86_sse42_pcmpestrio128:
15188 Opcode = X86ISD::PCMPESTRI;
15189 X86CC = X86::COND_O;
15191 case Intrinsic::x86_sse42_pcmpistris128:
15192 Opcode = X86ISD::PCMPISTRI;
15193 X86CC = X86::COND_S;
15195 case Intrinsic::x86_sse42_pcmpestris128:
15196 Opcode = X86ISD::PCMPESTRI;
15197 X86CC = X86::COND_S;
15199 case Intrinsic::x86_sse42_pcmpistriz128:
15200 Opcode = X86ISD::PCMPISTRI;
15201 X86CC = X86::COND_E;
15203 case Intrinsic::x86_sse42_pcmpestriz128:
15204 Opcode = X86ISD::PCMPESTRI;
15205 X86CC = X86::COND_E;
15208 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15209 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15210 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15211 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15212 DAG.getConstant(X86CC, dl, MVT::i8),
15213 SDValue(PCMP.getNode(), 1));
15214 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15217 case Intrinsic::x86_sse42_pcmpistri128:
15218 case Intrinsic::x86_sse42_pcmpestri128: {
15220 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15221 Opcode = X86ISD::PCMPISTRI;
15223 Opcode = X86ISD::PCMPESTRI;
15225 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15226 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15227 return DAG.getNode(Opcode, dl, VTs, NewOps);
15232 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15233 SDValue Src, SDValue Mask, SDValue Base,
15234 SDValue Index, SDValue ScaleOp, SDValue Chain,
15235 const X86Subtarget * Subtarget) {
15237 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15238 assert(C && "Invalid scale type");
15239 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15240 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15241 Index.getSimpleValueType().getVectorNumElements());
15243 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15245 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15247 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15248 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15249 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15250 SDValue Segment = DAG.getRegister(0, MVT::i32);
15251 if (Src.getOpcode() == ISD::UNDEF)
15252 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15253 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15254 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15255 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15256 return DAG.getMergeValues(RetOps, dl);
15259 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15260 SDValue Src, SDValue Mask, SDValue Base,
15261 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15263 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15264 assert(C && "Invalid scale type");
15265 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15266 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15267 SDValue Segment = DAG.getRegister(0, MVT::i32);
15268 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15269 Index.getSimpleValueType().getVectorNumElements());
15271 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15273 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15275 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15276 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15277 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15278 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15279 return SDValue(Res, 1);
15282 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15283 SDValue Mask, SDValue Base, SDValue Index,
15284 SDValue ScaleOp, SDValue Chain) {
15286 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15287 assert(C && "Invalid scale type");
15288 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15289 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15290 SDValue Segment = DAG.getRegister(0, MVT::i32);
15292 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15294 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15296 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15298 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15299 //SDVTList VTs = DAG.getVTList(MVT::Other);
15300 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15301 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15302 return SDValue(Res, 0);
15305 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15306 // read performance monitor counters (x86_rdpmc).
15307 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15308 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15309 SmallVectorImpl<SDValue> &Results) {
15310 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15311 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15314 // The ECX register is used to select the index of the performance counter
15316 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15318 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15320 // Reads the content of a 64-bit performance counter and returns it in the
15321 // registers EDX:EAX.
15322 if (Subtarget->is64Bit()) {
15323 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15324 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15327 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15328 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15331 Chain = HI.getValue(1);
15333 if (Subtarget->is64Bit()) {
15334 // The EAX register is loaded with the low-order 32 bits. The EDX register
15335 // is loaded with the supported high-order bits of the counter.
15336 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15337 DAG.getConstant(32, DL, MVT::i8));
15338 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15339 Results.push_back(Chain);
15343 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15344 SDValue Ops[] = { LO, HI };
15345 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15346 Results.push_back(Pair);
15347 Results.push_back(Chain);
15350 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15351 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15352 // also used to custom lower READCYCLECOUNTER nodes.
15353 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15354 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15355 SmallVectorImpl<SDValue> &Results) {
15356 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15357 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15360 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15361 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15362 // and the EAX register is loaded with the low-order 32 bits.
15363 if (Subtarget->is64Bit()) {
15364 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15365 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15368 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15369 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15372 SDValue Chain = HI.getValue(1);
15374 if (Opcode == X86ISD::RDTSCP_DAG) {
15375 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15377 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15378 // the ECX register. Add 'ecx' explicitly to the chain.
15379 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15381 // Explicitly store the content of ECX at the location passed in input
15382 // to the 'rdtscp' intrinsic.
15383 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15384 MachinePointerInfo(), false, false, 0);
15387 if (Subtarget->is64Bit()) {
15388 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15389 // the EAX register is loaded with the low-order 32 bits.
15390 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15391 DAG.getConstant(32, DL, MVT::i8));
15392 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15393 Results.push_back(Chain);
15397 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15398 SDValue Ops[] = { LO, HI };
15399 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15400 Results.push_back(Pair);
15401 Results.push_back(Chain);
15404 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15405 SelectionDAG &DAG) {
15406 SmallVector<SDValue, 2> Results;
15408 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15410 return DAG.getMergeValues(Results, DL);
15414 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15415 SelectionDAG &DAG) {
15416 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15418 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15423 switch(IntrData->Type) {
15425 llvm_unreachable("Unknown Intrinsic Type");
15429 // Emit the node with the right value type.
15430 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15431 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15433 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15434 // Otherwise return the value from Rand, which is always 0, casted to i32.
15435 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15436 DAG.getConstant(1, dl, Op->getValueType(1)),
15437 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15438 SDValue(Result.getNode(), 1) };
15439 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15440 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15443 // Return { result, isValid, chain }.
15444 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15445 SDValue(Result.getNode(), 2));
15448 //gather(v1, mask, index, base, scale);
15449 SDValue Chain = Op.getOperand(0);
15450 SDValue Src = Op.getOperand(2);
15451 SDValue Base = Op.getOperand(3);
15452 SDValue Index = Op.getOperand(4);
15453 SDValue Mask = Op.getOperand(5);
15454 SDValue Scale = Op.getOperand(6);
15455 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15459 //scatter(base, mask, index, v1, scale);
15460 SDValue Chain = Op.getOperand(0);
15461 SDValue Base = Op.getOperand(2);
15462 SDValue Mask = Op.getOperand(3);
15463 SDValue Index = Op.getOperand(4);
15464 SDValue Src = Op.getOperand(5);
15465 SDValue Scale = Op.getOperand(6);
15466 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15470 SDValue Hint = Op.getOperand(6);
15471 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15472 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15473 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15474 SDValue Chain = Op.getOperand(0);
15475 SDValue Mask = Op.getOperand(2);
15476 SDValue Index = Op.getOperand(3);
15477 SDValue Base = Op.getOperand(4);
15478 SDValue Scale = Op.getOperand(5);
15479 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15481 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15483 SmallVector<SDValue, 2> Results;
15484 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15486 return DAG.getMergeValues(Results, dl);
15488 // Read Performance Monitoring Counters.
15490 SmallVector<SDValue, 2> Results;
15491 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15492 return DAG.getMergeValues(Results, dl);
15494 // XTEST intrinsics.
15496 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15497 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15498 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15499 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15501 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15502 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15503 Ret, SDValue(InTrans.getNode(), 1));
15507 SmallVector<SDValue, 2> Results;
15508 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15509 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15510 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15511 DAG.getConstant(-1, dl, MVT::i8));
15512 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15513 Op.getOperand(4), GenCF.getValue(1));
15514 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15515 Op.getOperand(5), MachinePointerInfo(),
15517 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15518 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15520 Results.push_back(SetCC);
15521 Results.push_back(Store);
15522 return DAG.getMergeValues(Results, dl);
15524 case COMPRESS_TO_MEM: {
15526 SDValue Mask = Op.getOperand(4);
15527 SDValue DataToCompress = Op.getOperand(3);
15528 SDValue Addr = Op.getOperand(2);
15529 SDValue Chain = Op.getOperand(0);
15531 if (isAllOnes(Mask)) // return just a store
15532 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15533 MachinePointerInfo(), false, false, 0);
15535 EVT VT = DataToCompress.getValueType();
15536 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15537 VT.getVectorNumElements());
15538 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15539 Mask.getValueType().getSizeInBits());
15540 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15541 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15542 DAG.getIntPtrConstant(0, dl));
15544 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15545 DataToCompress, DAG.getUNDEF(VT));
15546 return DAG.getStore(Chain, dl, Compressed, Addr,
15547 MachinePointerInfo(), false, false, 0);
15549 case EXPAND_FROM_MEM: {
15551 SDValue Mask = Op.getOperand(4);
15552 SDValue PathThru = Op.getOperand(3);
15553 SDValue Addr = Op.getOperand(2);
15554 SDValue Chain = Op.getOperand(0);
15555 EVT VT = Op.getValueType();
15557 if (isAllOnes(Mask)) // return just a load
15558 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15560 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15561 VT.getVectorNumElements());
15562 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15563 Mask.getValueType().getSizeInBits());
15564 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15565 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15566 DAG.getIntPtrConstant(0, dl));
15568 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15569 false, false, false, 0);
15571 SDValue Results[] = {
15572 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15574 return DAG.getMergeValues(Results, dl);
15579 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15580 SelectionDAG &DAG) const {
15581 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15582 MFI->setReturnAddressIsTaken(true);
15584 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15587 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15589 EVT PtrVT = getPointerTy();
15592 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15593 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15594 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15595 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15596 DAG.getNode(ISD::ADD, dl, PtrVT,
15597 FrameAddr, Offset),
15598 MachinePointerInfo(), false, false, false, 0);
15601 // Just load the return address.
15602 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15603 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15604 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15607 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15608 MachineFunction &MF = DAG.getMachineFunction();
15609 MachineFrameInfo *MFI = MF.getFrameInfo();
15610 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15611 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15612 EVT VT = Op.getValueType();
15614 MFI->setFrameAddressIsTaken(true);
15616 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15617 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15618 // is not possible to crawl up the stack without looking at the unwind codes
15620 int FrameAddrIndex = FuncInfo->getFAIndex();
15621 if (!FrameAddrIndex) {
15622 // Set up a frame object for the return address.
15623 unsigned SlotSize = RegInfo->getSlotSize();
15624 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15625 SlotSize, /*Offset=*/INT64_MIN, /*IsImmutable=*/false);
15626 FuncInfo->setFAIndex(FrameAddrIndex);
15628 return DAG.getFrameIndex(FrameAddrIndex, VT);
15631 unsigned FrameReg =
15632 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15633 SDLoc dl(Op); // FIXME probably not meaningful
15634 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15635 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15636 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15637 "Invalid Frame Register!");
15638 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15640 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15641 MachinePointerInfo(),
15642 false, false, false, 0);
15646 // FIXME? Maybe this could be a TableGen attribute on some registers and
15647 // this table could be generated automatically from RegInfo.
15648 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15650 unsigned Reg = StringSwitch<unsigned>(RegName)
15651 .Case("esp", X86::ESP)
15652 .Case("rsp", X86::RSP)
15656 report_fatal_error("Invalid register name global variable");
15659 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15660 SelectionDAG &DAG) const {
15661 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15662 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15665 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15666 SDValue Chain = Op.getOperand(0);
15667 SDValue Offset = Op.getOperand(1);
15668 SDValue Handler = Op.getOperand(2);
15671 EVT PtrVT = getPointerTy();
15672 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15673 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15674 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15675 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15676 "Invalid Frame Register!");
15677 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15678 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15680 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15681 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15683 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15684 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15686 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15688 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15689 DAG.getRegister(StoreAddrReg, PtrVT));
15692 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15693 SelectionDAG &DAG) const {
15695 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15696 DAG.getVTList(MVT::i32, MVT::Other),
15697 Op.getOperand(0), Op.getOperand(1));
15700 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15701 SelectionDAG &DAG) const {
15703 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15704 Op.getOperand(0), Op.getOperand(1));
15707 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15708 return Op.getOperand(0);
15711 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15712 SelectionDAG &DAG) const {
15713 SDValue Root = Op.getOperand(0);
15714 SDValue Trmp = Op.getOperand(1); // trampoline
15715 SDValue FPtr = Op.getOperand(2); // nested function
15716 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15719 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15720 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15722 if (Subtarget->is64Bit()) {
15723 SDValue OutChains[6];
15725 // Large code-model.
15726 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15727 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15729 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15730 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15732 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15734 // Load the pointer to the nested function into R11.
15735 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15736 SDValue Addr = Trmp;
15737 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15738 Addr, MachinePointerInfo(TrmpAddr),
15741 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15742 DAG.getConstant(2, dl, MVT::i64));
15743 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15744 MachinePointerInfo(TrmpAddr, 2),
15747 // Load the 'nest' parameter value into R10.
15748 // R10 is specified in X86CallingConv.td
15749 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15750 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15751 DAG.getConstant(10, dl, MVT::i64));
15752 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15753 Addr, MachinePointerInfo(TrmpAddr, 10),
15756 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15757 DAG.getConstant(12, dl, MVT::i64));
15758 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15759 MachinePointerInfo(TrmpAddr, 12),
15762 // Jump to the nested function.
15763 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15764 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15765 DAG.getConstant(20, dl, MVT::i64));
15766 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15767 Addr, MachinePointerInfo(TrmpAddr, 20),
15770 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15771 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15772 DAG.getConstant(22, dl, MVT::i64));
15773 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
15774 Addr, MachinePointerInfo(TrmpAddr, 22),
15777 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15779 const Function *Func =
15780 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15781 CallingConv::ID CC = Func->getCallingConv();
15786 llvm_unreachable("Unsupported calling convention");
15787 case CallingConv::C:
15788 case CallingConv::X86_StdCall: {
15789 // Pass 'nest' parameter in ECX.
15790 // Must be kept in sync with X86CallingConv.td
15791 NestReg = X86::ECX;
15793 // Check that ECX wasn't needed by an 'inreg' parameter.
15794 FunctionType *FTy = Func->getFunctionType();
15795 const AttributeSet &Attrs = Func->getAttributes();
15797 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15798 unsigned InRegCount = 0;
15801 for (FunctionType::param_iterator I = FTy->param_begin(),
15802 E = FTy->param_end(); I != E; ++I, ++Idx)
15803 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15804 // FIXME: should only count parameters that are lowered to integers.
15805 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15807 if (InRegCount > 2) {
15808 report_fatal_error("Nest register in use - reduce number of inreg"
15814 case CallingConv::X86_FastCall:
15815 case CallingConv::X86_ThisCall:
15816 case CallingConv::Fast:
15817 // Pass 'nest' parameter in EAX.
15818 // Must be kept in sync with X86CallingConv.td
15819 NestReg = X86::EAX;
15823 SDValue OutChains[4];
15824 SDValue Addr, Disp;
15826 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15827 DAG.getConstant(10, dl, MVT::i32));
15828 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15830 // This is storing the opcode for MOV32ri.
15831 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15832 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15833 OutChains[0] = DAG.getStore(Root, dl,
15834 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
15835 Trmp, MachinePointerInfo(TrmpAddr),
15838 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15839 DAG.getConstant(1, dl, MVT::i32));
15840 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15841 MachinePointerInfo(TrmpAddr, 1),
15844 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15845 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15846 DAG.getConstant(5, dl, MVT::i32));
15847 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
15848 Addr, MachinePointerInfo(TrmpAddr, 5),
15851 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15852 DAG.getConstant(6, dl, MVT::i32));
15853 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15854 MachinePointerInfo(TrmpAddr, 6),
15857 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15861 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15862 SelectionDAG &DAG) const {
15864 The rounding mode is in bits 11:10 of FPSR, and has the following
15866 00 Round to nearest
15871 FLT_ROUNDS, on the other hand, expects the following:
15878 To perform the conversion, we do:
15879 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15882 MachineFunction &MF = DAG.getMachineFunction();
15883 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15884 unsigned StackAlignment = TFI.getStackAlignment();
15885 MVT VT = Op.getSimpleValueType();
15888 // Save FP Control Word to stack slot
15889 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15890 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15892 MachineMemOperand *MMO =
15893 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15894 MachineMemOperand::MOStore, 2, 2);
15896 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15897 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15898 DAG.getVTList(MVT::Other),
15899 Ops, MVT::i16, MMO);
15901 // Load FP Control Word from stack slot
15902 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15903 MachinePointerInfo(), false, false, false, 0);
15905 // Transform as necessary
15907 DAG.getNode(ISD::SRL, DL, MVT::i16,
15908 DAG.getNode(ISD::AND, DL, MVT::i16,
15909 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
15910 DAG.getConstant(11, DL, MVT::i8));
15912 DAG.getNode(ISD::SRL, DL, MVT::i16,
15913 DAG.getNode(ISD::AND, DL, MVT::i16,
15914 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
15915 DAG.getConstant(9, DL, MVT::i8));
15918 DAG.getNode(ISD::AND, DL, MVT::i16,
15919 DAG.getNode(ISD::ADD, DL, MVT::i16,
15920 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15921 DAG.getConstant(1, DL, MVT::i16)),
15922 DAG.getConstant(3, DL, MVT::i16));
15924 return DAG.getNode((VT.getSizeInBits() < 16 ?
15925 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15928 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15929 MVT VT = Op.getSimpleValueType();
15931 unsigned NumBits = VT.getSizeInBits();
15934 Op = Op.getOperand(0);
15935 if (VT == MVT::i8) {
15936 // Zero extend to i32 since there is not an i8 bsr.
15938 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15941 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15942 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15943 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15945 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15948 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
15949 DAG.getConstant(X86::COND_E, dl, MVT::i8),
15952 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15954 // Finally xor with NumBits-1.
15955 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
15956 DAG.getConstant(NumBits - 1, dl, OpVT));
15959 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15963 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15964 MVT VT = Op.getSimpleValueType();
15966 unsigned NumBits = VT.getSizeInBits();
15969 Op = Op.getOperand(0);
15970 if (VT == MVT::i8) {
15971 // Zero extend to i32 since there is not an i8 bsr.
15973 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15976 // Issue a bsr (scan bits in reverse).
15977 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15978 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15980 // And xor with NumBits-1.
15981 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
15982 DAG.getConstant(NumBits - 1, dl, OpVT));
15985 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15989 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15990 MVT VT = Op.getSimpleValueType();
15991 unsigned NumBits = VT.getSizeInBits();
15993 Op = Op.getOperand(0);
15995 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15996 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15997 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15999 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16002 DAG.getConstant(NumBits, dl, VT),
16003 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16006 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16009 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16010 // ones, and then concatenate the result back.
16011 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16012 MVT VT = Op.getSimpleValueType();
16014 assert(VT.is256BitVector() && VT.isInteger() &&
16015 "Unsupported value type for operation");
16017 unsigned NumElems = VT.getVectorNumElements();
16020 // Extract the LHS vectors
16021 SDValue LHS = Op.getOperand(0);
16022 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16023 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16025 // Extract the RHS vectors
16026 SDValue RHS = Op.getOperand(1);
16027 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16028 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16030 MVT EltVT = VT.getVectorElementType();
16031 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16033 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16034 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16035 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16038 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16039 assert(Op.getSimpleValueType().is256BitVector() &&
16040 Op.getSimpleValueType().isInteger() &&
16041 "Only handle AVX 256-bit vector integer operation");
16042 return Lower256IntArith(Op, DAG);
16045 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16046 assert(Op.getSimpleValueType().is256BitVector() &&
16047 Op.getSimpleValueType().isInteger() &&
16048 "Only handle AVX 256-bit vector integer operation");
16049 return Lower256IntArith(Op, DAG);
16052 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16053 SelectionDAG &DAG) {
16055 MVT VT = Op.getSimpleValueType();
16057 // Decompose 256-bit ops into smaller 128-bit ops.
16058 if (VT.is256BitVector() && !Subtarget->hasInt256())
16059 return Lower256IntArith(Op, DAG);
16061 SDValue A = Op.getOperand(0);
16062 SDValue B = Op.getOperand(1);
16064 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16065 // pairs, multiply and truncate.
16066 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16067 if (Subtarget->hasInt256()) {
16068 if (VT == MVT::v32i8) {
16069 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16070 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16071 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16072 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16073 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16074 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16075 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16076 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16077 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16078 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16081 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16082 return DAG.getNode(
16083 ISD::TRUNCATE, dl, VT,
16084 DAG.getNode(ISD::MUL, dl, ExVT,
16085 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16086 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16089 assert(VT == MVT::v16i8 &&
16090 "Pre-AVX2 support only supports v16i8 multiplication");
16091 MVT ExVT = MVT::v8i16;
16093 // Extract the lo parts and sign extend to i16
16095 if (Subtarget->hasSSE41()) {
16096 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16097 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16099 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16100 -1, 4, -1, 5, -1, 6, -1, 7};
16101 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16102 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16103 ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);
16104 BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);
16105 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16106 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16109 // Extract the hi parts and sign extend to i16
16111 if (Subtarget->hasSSE41()) {
16112 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16113 -1, -1, -1, -1, -1, -1, -1, -1};
16114 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16115 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16116 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16117 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16119 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16120 -1, 12, -1, 13, -1, 14, -1, 15};
16121 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16122 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16123 AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);
16124 BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);
16125 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16126 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16129 // Multiply, mask the lower 8bits of the lo/hi results and pack
16130 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16131 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16132 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16133 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16134 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16137 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16138 if (VT == MVT::v4i32) {
16139 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16140 "Should not custom lower when pmuldq is available!");
16142 // Extract the odd parts.
16143 static const int UnpackMask[] = { 1, -1, 3, -1 };
16144 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16145 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16147 // Multiply the even parts.
16148 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16149 // Now multiply odd parts.
16150 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16152 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16153 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16155 // Merge the two vectors back together with a shuffle. This expands into 2
16157 static const int ShufMask[] = { 0, 4, 2, 6 };
16158 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16161 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16162 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16164 // Ahi = psrlqi(a, 32);
16165 // Bhi = psrlqi(b, 32);
16167 // AloBlo = pmuludq(a, b);
16168 // AloBhi = pmuludq(a, Bhi);
16169 // AhiBlo = pmuludq(Ahi, b);
16171 // AloBhi = psllqi(AloBhi, 32);
16172 // AhiBlo = psllqi(AhiBlo, 32);
16173 // return AloBlo + AloBhi + AhiBlo;
16175 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16176 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16178 // Bit cast to 32-bit vectors for MULUDQ
16179 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16180 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16181 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16182 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16183 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16184 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16186 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16187 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16188 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16190 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16191 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16193 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16194 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16197 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16198 assert(Subtarget->isTargetWin64() && "Unexpected target");
16199 EVT VT = Op.getValueType();
16200 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16201 "Unexpected return type for lowering");
16205 switch (Op->getOpcode()) {
16206 default: llvm_unreachable("Unexpected request for libcall!");
16207 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16208 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16209 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16210 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16211 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16212 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16216 SDValue InChain = DAG.getEntryNode();
16218 TargetLowering::ArgListTy Args;
16219 TargetLowering::ArgListEntry Entry;
16220 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16221 EVT ArgVT = Op->getOperand(i).getValueType();
16222 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16223 "Unexpected argument type for lowering");
16224 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16225 Entry.Node = StackPtr;
16226 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16228 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16229 Entry.Ty = PointerType::get(ArgTy,0);
16230 Entry.isSExt = false;
16231 Entry.isZExt = false;
16232 Args.push_back(Entry);
16235 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16238 TargetLowering::CallLoweringInfo CLI(DAG);
16239 CLI.setDebugLoc(dl).setChain(InChain)
16240 .setCallee(getLibcallCallingConv(LC),
16241 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16242 Callee, std::move(Args), 0)
16243 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16245 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16246 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16249 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16250 SelectionDAG &DAG) {
16251 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16252 EVT VT = Op0.getValueType();
16255 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16256 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16258 // PMULxD operations multiply each even value (starting at 0) of LHS with
16259 // the related value of RHS and produce a widen result.
16260 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16261 // => <2 x i64> <ae|cg>
16263 // In other word, to have all the results, we need to perform two PMULxD:
16264 // 1. one with the even values.
16265 // 2. one with the odd values.
16266 // To achieve #2, with need to place the odd values at an even position.
16268 // Place the odd value at an even position (basically, shift all values 1
16269 // step to the left):
16270 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16271 // <a|b|c|d> => <b|undef|d|undef>
16272 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16273 // <e|f|g|h> => <f|undef|h|undef>
16274 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16276 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16278 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16279 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16281 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16282 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16283 // => <2 x i64> <ae|cg>
16284 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16285 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16286 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16287 // => <2 x i64> <bf|dh>
16288 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16289 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16291 // Shuffle it back into the right order.
16292 SDValue Highs, Lows;
16293 if (VT == MVT::v8i32) {
16294 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16295 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16296 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16297 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16299 const int HighMask[] = {1, 5, 3, 7};
16300 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16301 const int LowMask[] = {0, 4, 2, 6};
16302 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16305 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16306 // unsigned multiply.
16307 if (IsSigned && !Subtarget->hasSSE41()) {
16309 DAG.getConstant(31, dl,
16310 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16311 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16312 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16313 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16314 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16316 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16317 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16320 // The first result of MUL_LOHI is actually the low value, followed by the
16322 SDValue Ops[] = {Lows, Highs};
16323 return DAG.getMergeValues(Ops, dl);
16326 // Return true if the requred (according to Opcode) shift-imm form is natively
16327 // supported by the Subtarget
16328 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16330 if (VT.getScalarSizeInBits() < 16)
16333 if (VT.is512BitVector() &&
16334 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16337 bool LShift = VT.is128BitVector() ||
16338 (VT.is256BitVector() && Subtarget->hasInt256());
16340 bool AShift = LShift && (Subtarget->hasVLX() ||
16341 (VT != MVT::v2i64 && VT != MVT::v4i64));
16342 return (Opcode == ISD::SRA) ? AShift : LShift;
16345 // The shift amount is a variable, but it is the same for all vector lanes.
16346 // These instrcutions are defined together with shift-immediate.
16348 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16350 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16353 // Return true if the requred (according to Opcode) variable-shift form is
16354 // natively supported by the Subtarget
16355 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16358 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16361 // vXi16 supported only on AVX-512, BWI
16362 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16365 if (VT.is512BitVector() || Subtarget->hasVLX())
16368 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16369 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16370 return (Opcode == ISD::SRA) ? AShift : LShift;
16373 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16374 const X86Subtarget *Subtarget) {
16375 MVT VT = Op.getSimpleValueType();
16377 SDValue R = Op.getOperand(0);
16378 SDValue Amt = Op.getOperand(1);
16380 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16381 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16383 // Optimize shl/srl/sra with constant shift amount.
16384 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16385 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16386 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16388 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16389 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16391 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16392 unsigned NumElts = VT.getVectorNumElements();
16393 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16395 if (Op.getOpcode() == ISD::SHL) {
16396 // Make a large shift.
16397 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16399 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16400 // Zero out the rightmost bits.
16401 SmallVector<SDValue, 32> V(
16402 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16403 return DAG.getNode(ISD::AND, dl, VT, SHL,
16404 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16406 if (Op.getOpcode() == ISD::SRL) {
16407 // Make a large shift.
16408 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16410 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16411 // Zero out the leftmost bits.
16412 SmallVector<SDValue, 32> V(
16413 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16414 return DAG.getNode(ISD::AND, dl, VT, SRL,
16415 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16417 if (Op.getOpcode() == ISD::SRA) {
16418 if (ShiftAmt == 7) {
16419 // R s>> 7 === R s< 0
16420 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16421 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16424 // R s>> a === ((R u>> a) ^ m) - m
16425 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16426 SmallVector<SDValue, 32> V(NumElts,
16427 DAG.getConstant(128 >> ShiftAmt, dl,
16429 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16430 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16431 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16434 llvm_unreachable("Unknown shift opcode.");
16439 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16440 if (!Subtarget->is64Bit() &&
16441 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16442 Amt.getOpcode() == ISD::BITCAST &&
16443 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16444 Amt = Amt.getOperand(0);
16445 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16446 VT.getVectorNumElements();
16447 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16448 uint64_t ShiftAmt = 0;
16449 for (unsigned i = 0; i != Ratio; ++i) {
16450 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16454 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16456 // Check remaining shift amounts.
16457 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16458 uint64_t ShAmt = 0;
16459 for (unsigned j = 0; j != Ratio; ++j) {
16460 ConstantSDNode *C =
16461 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16465 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16467 if (ShAmt != ShiftAmt)
16470 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16476 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16477 const X86Subtarget* Subtarget) {
16478 MVT VT = Op.getSimpleValueType();
16480 SDValue R = Op.getOperand(0);
16481 SDValue Amt = Op.getOperand(1);
16483 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16484 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16486 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16487 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16489 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16491 EVT EltVT = VT.getVectorElementType();
16493 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16494 // Check if this build_vector node is doing a splat.
16495 // If so, then set BaseShAmt equal to the splat value.
16496 BaseShAmt = BV->getSplatValue();
16497 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16498 BaseShAmt = SDValue();
16500 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16501 Amt = Amt.getOperand(0);
16503 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16504 if (SVN && SVN->isSplat()) {
16505 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16506 SDValue InVec = Amt.getOperand(0);
16507 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16508 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16509 "Unexpected shuffle index found!");
16510 BaseShAmt = InVec.getOperand(SplatIdx);
16511 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16512 if (ConstantSDNode *C =
16513 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16514 if (C->getZExtValue() == SplatIdx)
16515 BaseShAmt = InVec.getOperand(1);
16520 // Avoid introducing an extract element from a shuffle.
16521 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16522 DAG.getIntPtrConstant(SplatIdx, dl));
16526 if (BaseShAmt.getNode()) {
16527 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16528 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16529 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16530 else if (EltVT.bitsLT(MVT::i32))
16531 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16533 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16537 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16538 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16539 Amt.getOpcode() == ISD::BITCAST &&
16540 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16541 Amt = Amt.getOperand(0);
16542 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16543 VT.getVectorNumElements();
16544 std::vector<SDValue> Vals(Ratio);
16545 for (unsigned i = 0; i != Ratio; ++i)
16546 Vals[i] = Amt.getOperand(i);
16547 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16548 for (unsigned j = 0; j != Ratio; ++j)
16549 if (Vals[j] != Amt.getOperand(i + j))
16552 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16557 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16558 SelectionDAG &DAG) {
16559 MVT VT = Op.getSimpleValueType();
16561 SDValue R = Op.getOperand(0);
16562 SDValue Amt = Op.getOperand(1);
16564 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16565 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16567 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16570 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16573 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16576 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16577 // shifts per-lane and then shuffle the partial results back together.
16578 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16579 // Splat the shift amounts so the scalar shifts above will catch it.
16580 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16581 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16582 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16583 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16584 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16587 // If possible, lower this packed shift into a vector multiply instead of
16588 // expanding it into a sequence of scalar shifts.
16589 // Do this only if the vector shift count is a constant build_vector.
16590 if (Op.getOpcode() == ISD::SHL &&
16591 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16592 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16593 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16594 SmallVector<SDValue, 8> Elts;
16595 EVT SVT = VT.getScalarType();
16596 unsigned SVTBits = SVT.getSizeInBits();
16597 const APInt &One = APInt(SVTBits, 1);
16598 unsigned NumElems = VT.getVectorNumElements();
16600 for (unsigned i=0; i !=NumElems; ++i) {
16601 SDValue Op = Amt->getOperand(i);
16602 if (Op->getOpcode() == ISD::UNDEF) {
16603 Elts.push_back(Op);
16607 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16608 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16609 uint64_t ShAmt = C.getZExtValue();
16610 if (ShAmt >= SVTBits) {
16611 Elts.push_back(DAG.getUNDEF(SVT));
16614 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16616 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16617 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16620 // Lower SHL with variable shift amount.
16621 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16622 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16624 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16625 DAG.getConstant(0x3f800000U, dl, VT));
16626 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16627 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16628 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16631 // If possible, lower this shift as a sequence of two shifts by
16632 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16634 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16636 // Could be rewritten as:
16637 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16639 // The advantage is that the two shifts from the example would be
16640 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16641 // the vector shift into four scalar shifts plus four pairs of vector
16643 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16644 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16645 unsigned TargetOpcode = X86ISD::MOVSS;
16646 bool CanBeSimplified;
16647 // The splat value for the first packed shift (the 'X' from the example).
16648 SDValue Amt1 = Amt->getOperand(0);
16649 // The splat value for the second packed shift (the 'Y' from the example).
16650 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16651 Amt->getOperand(2);
16653 // See if it is possible to replace this node with a sequence of
16654 // two shifts followed by a MOVSS/MOVSD
16655 if (VT == MVT::v4i32) {
16656 // Check if it is legal to use a MOVSS.
16657 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16658 Amt2 == Amt->getOperand(3);
16659 if (!CanBeSimplified) {
16660 // Otherwise, check if we can still simplify this node using a MOVSD.
16661 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16662 Amt->getOperand(2) == Amt->getOperand(3);
16663 TargetOpcode = X86ISD::MOVSD;
16664 Amt2 = Amt->getOperand(2);
16667 // Do similar checks for the case where the machine value type
16669 CanBeSimplified = Amt1 == Amt->getOperand(1);
16670 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16671 CanBeSimplified = Amt2 == Amt->getOperand(i);
16673 if (!CanBeSimplified) {
16674 TargetOpcode = X86ISD::MOVSD;
16675 CanBeSimplified = true;
16676 Amt2 = Amt->getOperand(4);
16677 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16678 CanBeSimplified = Amt1 == Amt->getOperand(i);
16679 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16680 CanBeSimplified = Amt2 == Amt->getOperand(j);
16684 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16685 isa<ConstantSDNode>(Amt2)) {
16686 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16687 EVT CastVT = MVT::v4i32;
16689 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16690 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16692 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16693 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16694 if (TargetOpcode == X86ISD::MOVSD)
16695 CastVT = MVT::v2i64;
16696 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16697 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16698 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16700 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16704 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16705 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
16706 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
16708 SDValue VSelM = DAG.getConstant(0x80, dl, VT);
16709 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16710 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16712 // r = VSELECT(r, shl(r, 4), a);
16713 SDValue M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(4, dl, VT));
16714 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16717 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16718 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16719 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16721 // r = VSELECT(r, shl(r, 2), a);
16722 M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(2, dl, VT));
16723 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16726 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16727 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16728 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16730 // return VSELECT(r, r+r, a);
16731 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16732 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16736 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16737 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16738 // solution better.
16739 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16740 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16742 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16743 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16744 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16745 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16746 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16749 // Decompose 256-bit shifts into smaller 128-bit shifts.
16750 if (VT.is256BitVector()) {
16751 unsigned NumElems = VT.getVectorNumElements();
16752 MVT EltVT = VT.getVectorElementType();
16753 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16755 // Extract the two vectors
16756 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16757 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16759 // Recreate the shift amount vectors
16760 SDValue Amt1, Amt2;
16761 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16762 // Constant shift amount
16763 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16764 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16765 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16767 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16768 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16770 // Variable shift amount
16771 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16772 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16775 // Issue new vector shifts for the smaller types
16776 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16777 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16779 // Concatenate the result back
16780 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16786 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16787 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16788 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16789 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16790 // has only one use.
16791 SDNode *N = Op.getNode();
16792 SDValue LHS = N->getOperand(0);
16793 SDValue RHS = N->getOperand(1);
16794 unsigned BaseOp = 0;
16797 switch (Op.getOpcode()) {
16798 default: llvm_unreachable("Unknown ovf instruction!");
16800 // A subtract of one will be selected as a INC. Note that INC doesn't
16801 // set CF, so we can't do this for UADDO.
16802 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16804 BaseOp = X86ISD::INC;
16805 Cond = X86::COND_O;
16808 BaseOp = X86ISD::ADD;
16809 Cond = X86::COND_O;
16812 BaseOp = X86ISD::ADD;
16813 Cond = X86::COND_B;
16816 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16817 // set CF, so we can't do this for USUBO.
16818 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16820 BaseOp = X86ISD::DEC;
16821 Cond = X86::COND_O;
16824 BaseOp = X86ISD::SUB;
16825 Cond = X86::COND_O;
16828 BaseOp = X86ISD::SUB;
16829 Cond = X86::COND_B;
16832 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16833 Cond = X86::COND_O;
16835 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16836 if (N->getValueType(0) == MVT::i8) {
16837 BaseOp = X86ISD::UMUL8;
16838 Cond = X86::COND_O;
16841 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16843 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16846 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16847 DAG.getConstant(X86::COND_O, DL, MVT::i32),
16848 SDValue(Sum.getNode(), 2));
16850 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16854 // Also sets EFLAGS.
16855 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16856 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16859 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16860 DAG.getConstant(Cond, DL, MVT::i32),
16861 SDValue(Sum.getNode(), 1));
16863 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16866 /// Returns true if the operand type is exactly twice the native width, and
16867 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16868 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16869 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16870 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16871 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16874 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16875 else if (OpWidth == 128)
16876 return Subtarget->hasCmpxchg16b();
16881 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16882 return needsCmpXchgNb(SI->getValueOperand()->getType());
16885 // Note: this turns large loads into lock cmpxchg8b/16b.
16886 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16887 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16888 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16889 return needsCmpXchgNb(PTy->getElementType());
16892 TargetLoweringBase::AtomicRMWExpansionKind
16893 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16894 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16895 const Type *MemType = AI->getType();
16897 // If the operand is too big, we must see if cmpxchg8/16b is available
16898 // and default to library calls otherwise.
16899 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
16900 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
16901 : AtomicRMWExpansionKind::None;
16904 AtomicRMWInst::BinOp Op = AI->getOperation();
16907 llvm_unreachable("Unknown atomic operation");
16908 case AtomicRMWInst::Xchg:
16909 case AtomicRMWInst::Add:
16910 case AtomicRMWInst::Sub:
16911 // It's better to use xadd, xsub or xchg for these in all cases.
16912 return AtomicRMWExpansionKind::None;
16913 case AtomicRMWInst::Or:
16914 case AtomicRMWInst::And:
16915 case AtomicRMWInst::Xor:
16916 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16917 // prefix to a normal instruction for these operations.
16918 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
16919 : AtomicRMWExpansionKind::None;
16920 case AtomicRMWInst::Nand:
16921 case AtomicRMWInst::Max:
16922 case AtomicRMWInst::Min:
16923 case AtomicRMWInst::UMax:
16924 case AtomicRMWInst::UMin:
16925 // These always require a non-trivial set of data operations on x86. We must
16926 // use a cmpxchg loop.
16927 return AtomicRMWExpansionKind::CmpXChg;
16931 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16932 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16933 // no-sse2). There isn't any reason to disable it if the target processor
16935 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16939 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16940 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16941 const Type *MemType = AI->getType();
16942 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16943 // there is no benefit in turning such RMWs into loads, and it is actually
16944 // harmful as it introduces a mfence.
16945 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16948 auto Builder = IRBuilder<>(AI);
16949 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16950 auto SynchScope = AI->getSynchScope();
16951 // We must restrict the ordering to avoid generating loads with Release or
16952 // ReleaseAcquire orderings.
16953 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16954 auto Ptr = AI->getPointerOperand();
16956 // Before the load we need a fence. Here is an example lifted from
16957 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16960 // x.store(1, relaxed);
16961 // r1 = y.fetch_add(0, release);
16963 // y.fetch_add(42, acquire);
16964 // r2 = x.load(relaxed);
16965 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16966 // lowered to just a load without a fence. A mfence flushes the store buffer,
16967 // making the optimization clearly correct.
16968 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16969 // otherwise, we might be able to be more agressive on relaxed idempotent
16970 // rmw. In practice, they do not look useful, so we don't try to be
16971 // especially clever.
16972 if (SynchScope == SingleThread) {
16973 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16974 // the IR level, so we must wrap it in an intrinsic.
16976 } else if (hasMFENCE(*Subtarget)) {
16977 Function *MFence = llvm::Intrinsic::getDeclaration(M,
16978 Intrinsic::x86_sse2_mfence);
16979 Builder.CreateCall(MFence);
16981 // FIXME: it might make sense to use a locked operation here but on a
16982 // different cache-line to prevent cache-line bouncing. In practice it
16983 // is probably a small win, and x86 processors without mfence are rare
16984 // enough that we do not bother.
16988 // Finally we can emit the atomic load.
16989 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
16990 AI->getType()->getPrimitiveSizeInBits());
16991 Loaded->setAtomic(Order, SynchScope);
16992 AI->replaceAllUsesWith(Loaded);
16993 AI->eraseFromParent();
16997 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16998 SelectionDAG &DAG) {
17000 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17001 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17002 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17003 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17005 // The only fence that needs an instruction is a sequentially-consistent
17006 // cross-thread fence.
17007 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17008 if (hasMFENCE(*Subtarget))
17009 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17011 SDValue Chain = Op.getOperand(0);
17012 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17014 DAG.getRegister(X86::ESP, MVT::i32), // Base
17015 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17016 DAG.getRegister(0, MVT::i32), // Index
17017 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17018 DAG.getRegister(0, MVT::i32), // Segment.
17022 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17023 return SDValue(Res, 0);
17026 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17027 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17030 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17031 SelectionDAG &DAG) {
17032 MVT T = Op.getSimpleValueType();
17036 switch(T.SimpleTy) {
17037 default: llvm_unreachable("Invalid value type!");
17038 case MVT::i8: Reg = X86::AL; size = 1; break;
17039 case MVT::i16: Reg = X86::AX; size = 2; break;
17040 case MVT::i32: Reg = X86::EAX; size = 4; break;
17042 assert(Subtarget->is64Bit() && "Node not type legal!");
17043 Reg = X86::RAX; size = 8;
17046 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17047 Op.getOperand(2), SDValue());
17048 SDValue Ops[] = { cpIn.getValue(0),
17051 DAG.getTargetConstant(size, DL, MVT::i8),
17052 cpIn.getValue(1) };
17053 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17054 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17055 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17059 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17060 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17061 MVT::i32, cpOut.getValue(2));
17062 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17063 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17066 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17067 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17068 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17072 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17073 SelectionDAG &DAG) {
17074 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17075 MVT DstVT = Op.getSimpleValueType();
17077 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17078 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17079 if (DstVT != MVT::f64)
17080 // This conversion needs to be expanded.
17083 SDValue InVec = Op->getOperand(0);
17085 unsigned NumElts = SrcVT.getVectorNumElements();
17086 EVT SVT = SrcVT.getVectorElementType();
17088 // Widen the vector in input in the case of MVT::v2i32.
17089 // Example: from MVT::v2i32 to MVT::v4i32.
17090 SmallVector<SDValue, 16> Elts;
17091 for (unsigned i = 0, e = NumElts; i != e; ++i)
17092 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17093 DAG.getIntPtrConstant(i, dl)));
17095 // Explicitly mark the extra elements as Undef.
17096 Elts.append(NumElts, DAG.getUNDEF(SVT));
17098 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17099 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17100 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17101 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17102 DAG.getIntPtrConstant(0, dl));
17105 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17106 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17107 assert((DstVT == MVT::i64 ||
17108 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17109 "Unexpected custom BITCAST");
17110 // i64 <=> MMX conversions are Legal.
17111 if (SrcVT==MVT::i64 && DstVT.isVector())
17113 if (DstVT==MVT::i64 && SrcVT.isVector())
17115 // MMX <=> MMX conversions are Legal.
17116 if (SrcVT.isVector() && DstVT.isVector())
17118 // All other conversions need to be expanded.
17122 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17123 SelectionDAG &DAG) {
17124 SDNode *Node = Op.getNode();
17127 Op = Op.getOperand(0);
17128 EVT VT = Op.getValueType();
17129 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17130 "CTPOP lowering only implemented for 128/256-bit wide vector types");
17132 unsigned NumElts = VT.getVectorNumElements();
17133 EVT EltVT = VT.getVectorElementType();
17134 unsigned Len = EltVT.getSizeInBits();
17136 // This is the vectorized version of the "best" algorithm from
17137 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17138 // with a minor tweak to use a series of adds + shifts instead of vector
17139 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
17141 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
17142 // v8i32 => Always profitable
17144 // FIXME: There a couple of possible improvements:
17146 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
17147 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
17149 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
17150 "CTPOP not implemented for this vector element type.");
17152 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
17153 // extra legalization.
17154 bool NeedsBitcast = EltVT == MVT::i32;
17155 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
17157 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl,
17159 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl,
17161 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl,
17164 // v = v - ((v >> 1) & 0x55555555...)
17165 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, dl, EltVT));
17166 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
17167 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
17169 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17171 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
17172 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
17174 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
17176 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
17177 if (VT != And.getValueType())
17178 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17179 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
17181 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17182 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
17183 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
17184 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, dl, EltVT));
17185 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
17187 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
17188 if (NeedsBitcast) {
17189 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17190 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
17191 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
17194 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
17195 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
17196 if (VT != AndRHS.getValueType()) {
17197 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
17198 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
17200 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
17202 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17203 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, dl, EltVT));
17204 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
17205 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
17206 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17208 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
17209 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
17210 if (NeedsBitcast) {
17211 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17212 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
17214 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
17215 if (VT != And.getValueType())
17216 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17218 // The algorithm mentioned above uses:
17219 // v = (v * 0x01010101...) >> (Len - 8)
17221 // Change it to use vector adds + vector shifts which yield faster results on
17222 // Haswell than using vector integer multiplication.
17224 // For i32 elements:
17225 // v = v + (v >> 8)
17226 // v = v + (v >> 16)
17228 // For i64 elements:
17229 // v = v + (v >> 8)
17230 // v = v + (v >> 16)
17231 // v = v + (v >> 32)
17234 SmallVector<SDValue, 8> Csts;
17235 for (unsigned i = 8; i <= Len/2; i *= 2) {
17236 Csts.assign(NumElts, DAG.getConstant(i, dl, EltVT));
17237 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
17238 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
17239 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17243 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
17244 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), dl,
17246 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
17247 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
17248 if (NeedsBitcast) {
17249 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17250 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
17252 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
17253 if (VT != And.getValueType())
17254 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17259 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17260 SDNode *Node = Op.getNode();
17262 EVT T = Node->getValueType(0);
17263 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17264 DAG.getConstant(0, dl, T), Node->getOperand(2));
17265 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17266 cast<AtomicSDNode>(Node)->getMemoryVT(),
17267 Node->getOperand(0),
17268 Node->getOperand(1), negOp,
17269 cast<AtomicSDNode>(Node)->getMemOperand(),
17270 cast<AtomicSDNode>(Node)->getOrdering(),
17271 cast<AtomicSDNode>(Node)->getSynchScope());
17274 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17275 SDNode *Node = Op.getNode();
17277 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17279 // Convert seq_cst store -> xchg
17280 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17281 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17282 // (The only way to get a 16-byte store is cmpxchg16b)
17283 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17284 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17285 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17286 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17287 cast<AtomicSDNode>(Node)->getMemoryVT(),
17288 Node->getOperand(0),
17289 Node->getOperand(1), Node->getOperand(2),
17290 cast<AtomicSDNode>(Node)->getMemOperand(),
17291 cast<AtomicSDNode>(Node)->getOrdering(),
17292 cast<AtomicSDNode>(Node)->getSynchScope());
17293 return Swap.getValue(1);
17295 // Other atomic stores have a simple pattern.
17299 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17300 EVT VT = Op.getNode()->getSimpleValueType(0);
17302 // Let legalize expand this if it isn't a legal type yet.
17303 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17306 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17309 bool ExtraOp = false;
17310 switch (Op.getOpcode()) {
17311 default: llvm_unreachable("Invalid code");
17312 case ISD::ADDC: Opc = X86ISD::ADD; break;
17313 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17314 case ISD::SUBC: Opc = X86ISD::SUB; break;
17315 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17319 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17321 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17322 Op.getOperand(1), Op.getOperand(2));
17325 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17326 SelectionDAG &DAG) {
17327 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17329 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17330 // which returns the values as { float, float } (in XMM0) or
17331 // { double, double } (which is returned in XMM0, XMM1).
17333 SDValue Arg = Op.getOperand(0);
17334 EVT ArgVT = Arg.getValueType();
17335 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17337 TargetLowering::ArgListTy Args;
17338 TargetLowering::ArgListEntry Entry;
17342 Entry.isSExt = false;
17343 Entry.isZExt = false;
17344 Args.push_back(Entry);
17346 bool isF64 = ArgVT == MVT::f64;
17347 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17348 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17349 // the results are returned via SRet in memory.
17350 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17352 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17354 Type *RetTy = isF64
17355 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17356 : (Type*)VectorType::get(ArgTy, 4);
17358 TargetLowering::CallLoweringInfo CLI(DAG);
17359 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17360 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17362 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17365 // Returned in xmm0 and xmm1.
17366 return CallResult.first;
17368 // Returned in bits 0:31 and 32:64 xmm0.
17369 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17370 CallResult.first, DAG.getIntPtrConstant(0, dl));
17371 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17372 CallResult.first, DAG.getIntPtrConstant(1, dl));
17373 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17374 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17377 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17378 SelectionDAG &DAG) {
17379 assert(Subtarget->hasAVX512() &&
17380 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17382 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17383 EVT VT = N->getValue().getValueType();
17384 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17387 // X86 scatter kills mask register, so its type should be added to
17388 // the list of return values
17389 if (N->getNumValues() == 1) {
17390 SDValue Index = N->getIndex();
17391 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17392 !Index.getValueType().is512BitVector())
17393 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17395 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17396 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17397 N->getOperand(3), Index };
17399 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17400 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17401 return SDValue(NewScatter.getNode(), 0);
17406 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17407 SelectionDAG &DAG) {
17408 assert(Subtarget->hasAVX512() &&
17409 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17411 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17412 EVT VT = Op.getValueType();
17413 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17416 SDValue Index = N->getIndex();
17417 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17418 !Index.getValueType().is512BitVector()) {
17419 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17420 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17421 N->getOperand(3), Index };
17422 DAG.UpdateNodeOperands(N, Ops);
17427 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
17428 SelectionDAG &DAG) const {
17429 // TODO: Eventually, the lowering of these nodes should be informed by or
17430 // deferred to the GC strategy for the function in which they appear. For
17431 // now, however, they must be lowered to something. Since they are logically
17432 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17433 // require special handling for these nodes), lower them as literal NOOPs for
17435 SmallVector<SDValue, 2> Ops;
17437 Ops.push_back(Op.getOperand(0));
17438 if (Op->getGluedNode())
17439 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17442 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17443 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17448 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
17449 SelectionDAG &DAG) const {
17450 // TODO: Eventually, the lowering of these nodes should be informed by or
17451 // deferred to the GC strategy for the function in which they appear. For
17452 // now, however, they must be lowered to something. Since they are logically
17453 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17454 // require special handling for these nodes), lower them as literal NOOPs for
17456 SmallVector<SDValue, 2> Ops;
17458 Ops.push_back(Op.getOperand(0));
17459 if (Op->getGluedNode())
17460 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17463 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17464 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17469 /// LowerOperation - Provide custom lowering hooks for some operations.
17471 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17472 switch (Op.getOpcode()) {
17473 default: llvm_unreachable("Should not custom lower this!");
17474 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17475 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17476 return LowerCMP_SWAP(Op, Subtarget, DAG);
17477 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17478 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17479 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17480 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17481 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17482 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17483 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17484 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17485 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17486 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17487 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17488 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17489 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17490 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17491 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17492 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17493 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17494 case ISD::SHL_PARTS:
17495 case ISD::SRA_PARTS:
17496 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17497 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17498 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17499 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17500 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17501 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17502 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17503 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17504 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17505 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17506 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17508 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17509 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17510 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17511 case ISD::SETCC: return LowerSETCC(Op, DAG);
17512 case ISD::SELECT: return LowerSELECT(Op, DAG);
17513 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17514 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17515 case ISD::VASTART: return LowerVASTART(Op, DAG);
17516 case ISD::VAARG: return LowerVAARG(Op, DAG);
17517 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17518 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17519 case ISD::INTRINSIC_VOID:
17520 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17521 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17522 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17523 case ISD::FRAME_TO_ARGS_OFFSET:
17524 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17525 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17526 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17527 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17528 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17529 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17530 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17531 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17532 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17533 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17534 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17535 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17536 case ISD::UMUL_LOHI:
17537 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17540 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17546 case ISD::UMULO: return LowerXALUO(Op, DAG);
17547 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17548 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17552 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17553 case ISD::ADD: return LowerADD(Op, DAG);
17554 case ISD::SUB: return LowerSUB(Op, DAG);
17555 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17556 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
17557 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
17558 case ISD::GC_TRANSITION_START:
17559 return LowerGC_TRANSITION_START(Op, DAG);
17560 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
17564 /// ReplaceNodeResults - Replace a node with an illegal result type
17565 /// with a new node built out of custom code.
17566 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17567 SmallVectorImpl<SDValue>&Results,
17568 SelectionDAG &DAG) const {
17570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17571 switch (N->getOpcode()) {
17573 llvm_unreachable("Do not know how to custom type legalize this operation!");
17574 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17575 case X86ISD::FMINC:
17577 case X86ISD::FMAXC:
17578 case X86ISD::FMAX: {
17579 EVT VT = N->getValueType(0);
17580 if (VT != MVT::v2f32)
17581 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17582 SDValue UNDEF = DAG.getUNDEF(VT);
17583 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17584 N->getOperand(0), UNDEF);
17585 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17586 N->getOperand(1), UNDEF);
17587 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17590 case ISD::SIGN_EXTEND_INREG:
17595 // We don't want to expand or promote these.
17602 case ISD::UDIVREM: {
17603 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17604 Results.push_back(V);
17607 case ISD::FP_TO_SINT:
17608 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
17609 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
17610 if (N->getOperand(0).getValueType() == MVT::f16)
17613 case ISD::FP_TO_UINT: {
17614 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17616 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17619 std::pair<SDValue,SDValue> Vals =
17620 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17621 SDValue FIST = Vals.first, StackSlot = Vals.second;
17622 if (FIST.getNode()) {
17623 EVT VT = N->getValueType(0);
17624 // Return a load from the stack slot.
17625 if (StackSlot.getNode())
17626 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17627 MachinePointerInfo(),
17628 false, false, false, 0));
17630 Results.push_back(FIST);
17634 case ISD::UINT_TO_FP: {
17635 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17636 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17637 N->getValueType(0) != MVT::v2f32)
17639 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17641 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
17643 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17644 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17645 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17646 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17647 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17648 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17651 case ISD::FP_ROUND: {
17652 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17654 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17655 Results.push_back(V);
17658 case ISD::FP_EXTEND: {
17659 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
17660 // No other ValueType for FP_EXTEND should reach this point.
17661 assert(N->getValueType(0) == MVT::v2f32 &&
17662 "Do not know how to legalize this Node");
17665 case ISD::INTRINSIC_W_CHAIN: {
17666 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17668 default : llvm_unreachable("Do not know how to custom type "
17669 "legalize this intrinsic operation!");
17670 case Intrinsic::x86_rdtsc:
17671 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17673 case Intrinsic::x86_rdtscp:
17674 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17676 case Intrinsic::x86_rdpmc:
17677 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17680 case ISD::READCYCLECOUNTER: {
17681 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17684 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17685 EVT T = N->getValueType(0);
17686 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17687 bool Regs64bit = T == MVT::i128;
17688 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17689 SDValue cpInL, cpInH;
17690 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17691 DAG.getConstant(0, dl, HalfT));
17692 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17693 DAG.getConstant(1, dl, HalfT));
17694 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17695 Regs64bit ? X86::RAX : X86::EAX,
17697 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17698 Regs64bit ? X86::RDX : X86::EDX,
17699 cpInH, cpInL.getValue(1));
17700 SDValue swapInL, swapInH;
17701 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17702 DAG.getConstant(0, dl, HalfT));
17703 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17704 DAG.getConstant(1, dl, HalfT));
17705 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17706 Regs64bit ? X86::RBX : X86::EBX,
17707 swapInL, cpInH.getValue(1));
17708 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17709 Regs64bit ? X86::RCX : X86::ECX,
17710 swapInH, swapInL.getValue(1));
17711 SDValue Ops[] = { swapInH.getValue(0),
17713 swapInH.getValue(1) };
17714 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17715 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17716 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17717 X86ISD::LCMPXCHG8_DAG;
17718 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17719 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17720 Regs64bit ? X86::RAX : X86::EAX,
17721 HalfT, Result.getValue(1));
17722 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17723 Regs64bit ? X86::RDX : X86::EDX,
17724 HalfT, cpOutL.getValue(2));
17725 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17727 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17728 MVT::i32, cpOutH.getValue(2));
17730 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17731 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
17732 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17734 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17735 Results.push_back(Success);
17736 Results.push_back(EFLAGS.getValue(1));
17739 case ISD::ATOMIC_SWAP:
17740 case ISD::ATOMIC_LOAD_ADD:
17741 case ISD::ATOMIC_LOAD_SUB:
17742 case ISD::ATOMIC_LOAD_AND:
17743 case ISD::ATOMIC_LOAD_OR:
17744 case ISD::ATOMIC_LOAD_XOR:
17745 case ISD::ATOMIC_LOAD_NAND:
17746 case ISD::ATOMIC_LOAD_MIN:
17747 case ISD::ATOMIC_LOAD_MAX:
17748 case ISD::ATOMIC_LOAD_UMIN:
17749 case ISD::ATOMIC_LOAD_UMAX:
17750 case ISD::ATOMIC_LOAD: {
17751 // Delegate to generic TypeLegalization. Situations we can really handle
17752 // should have already been dealt with by AtomicExpandPass.cpp.
17755 case ISD::BITCAST: {
17756 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17757 EVT DstVT = N->getValueType(0);
17758 EVT SrcVT = N->getOperand(0)->getValueType(0);
17760 if (SrcVT != MVT::f64 ||
17761 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17764 unsigned NumElts = DstVT.getVectorNumElements();
17765 EVT SVT = DstVT.getVectorElementType();
17766 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17767 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17768 MVT::v2f64, N->getOperand(0));
17769 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17771 if (ExperimentalVectorWideningLegalization) {
17772 // If we are legalizing vectors by widening, we already have the desired
17773 // legal vector type, just return it.
17774 Results.push_back(ToVecInt);
17778 SmallVector<SDValue, 8> Elts;
17779 for (unsigned i = 0, e = NumElts; i != e; ++i)
17780 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17781 ToVecInt, DAG.getIntPtrConstant(i, dl)));
17783 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17788 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17789 switch ((X86ISD::NodeType)Opcode) {
17790 case X86ISD::FIRST_NUMBER: break;
17791 case X86ISD::BSF: return "X86ISD::BSF";
17792 case X86ISD::BSR: return "X86ISD::BSR";
17793 case X86ISD::SHLD: return "X86ISD::SHLD";
17794 case X86ISD::SHRD: return "X86ISD::SHRD";
17795 case X86ISD::FAND: return "X86ISD::FAND";
17796 case X86ISD::FANDN: return "X86ISD::FANDN";
17797 case X86ISD::FOR: return "X86ISD::FOR";
17798 case X86ISD::FXOR: return "X86ISD::FXOR";
17799 case X86ISD::FSRL: return "X86ISD::FSRL";
17800 case X86ISD::FILD: return "X86ISD::FILD";
17801 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17802 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17803 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17804 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17805 case X86ISD::FLD: return "X86ISD::FLD";
17806 case X86ISD::FST: return "X86ISD::FST";
17807 case X86ISD::CALL: return "X86ISD::CALL";
17808 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17809 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17810 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17811 case X86ISD::BT: return "X86ISD::BT";
17812 case X86ISD::CMP: return "X86ISD::CMP";
17813 case X86ISD::COMI: return "X86ISD::COMI";
17814 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17815 case X86ISD::CMPM: return "X86ISD::CMPM";
17816 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17817 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
17818 case X86ISD::SETCC: return "X86ISD::SETCC";
17819 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17820 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17821 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
17822 case X86ISD::CMOV: return "X86ISD::CMOV";
17823 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17824 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17825 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17826 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17827 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17828 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17829 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17830 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
17831 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
17832 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
17833 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17834 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17835 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17836 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17837 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17838 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
17839 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17840 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17841 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17842 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17843 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17844 case X86ISD::ADDUS: return "X86ISD::ADDUS";
17845 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17846 case X86ISD::HADD: return "X86ISD::HADD";
17847 case X86ISD::HSUB: return "X86ISD::HSUB";
17848 case X86ISD::FHADD: return "X86ISD::FHADD";
17849 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17850 case X86ISD::UMAX: return "X86ISD::UMAX";
17851 case X86ISD::UMIN: return "X86ISD::UMIN";
17852 case X86ISD::SMAX: return "X86ISD::SMAX";
17853 case X86ISD::SMIN: return "X86ISD::SMIN";
17854 case X86ISD::FMAX: return "X86ISD::FMAX";
17855 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
17856 case X86ISD::FMIN: return "X86ISD::FMIN";
17857 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
17858 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17859 case X86ISD::FMINC: return "X86ISD::FMINC";
17860 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17861 case X86ISD::FRCP: return "X86ISD::FRCP";
17862 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17863 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17864 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17865 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17866 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17867 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17868 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17869 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17870 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17871 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17872 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17873 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17874 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17875 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17876 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17877 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17878 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17879 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17880 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17881 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17882 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17883 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17884 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17885 case X86ISD::VSHL: return "X86ISD::VSHL";
17886 case X86ISD::VSRL: return "X86ISD::VSRL";
17887 case X86ISD::VSRA: return "X86ISD::VSRA";
17888 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17889 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17890 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17891 case X86ISD::CMPP: return "X86ISD::CMPP";
17892 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17893 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17894 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17895 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17896 case X86ISD::ADD: return "X86ISD::ADD";
17897 case X86ISD::SUB: return "X86ISD::SUB";
17898 case X86ISD::ADC: return "X86ISD::ADC";
17899 case X86ISD::SBB: return "X86ISD::SBB";
17900 case X86ISD::SMUL: return "X86ISD::SMUL";
17901 case X86ISD::UMUL: return "X86ISD::UMUL";
17902 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17903 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17904 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17905 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17906 case X86ISD::INC: return "X86ISD::INC";
17907 case X86ISD::DEC: return "X86ISD::DEC";
17908 case X86ISD::OR: return "X86ISD::OR";
17909 case X86ISD::XOR: return "X86ISD::XOR";
17910 case X86ISD::AND: return "X86ISD::AND";
17911 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17912 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17913 case X86ISD::PTEST: return "X86ISD::PTEST";
17914 case X86ISD::TESTP: return "X86ISD::TESTP";
17915 case X86ISD::TESTM: return "X86ISD::TESTM";
17916 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17917 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17918 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17919 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17920 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17921 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17922 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17923 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17924 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17925 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17926 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17927 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17928 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17929 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17930 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17931 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17932 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17933 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17934 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17935 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17936 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17937 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17938 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17939 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17940 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
17941 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17942 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17943 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17944 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17945 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17946 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17947 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17948 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17949 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17950 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17951 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17952 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17953 case X86ISD::MFENCE: return "X86ISD::MFENCE";
17954 case X86ISD::SFENCE: return "X86ISD::SFENCE";
17955 case X86ISD::LFENCE: return "X86ISD::LFENCE";
17956 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17957 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17958 case X86ISD::SAHF: return "X86ISD::SAHF";
17959 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17960 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17961 case X86ISD::FMADD: return "X86ISD::FMADD";
17962 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17963 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17964 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17965 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17966 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17967 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
17968 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
17969 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
17970 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
17971 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
17972 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
17973 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
17974 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17975 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17976 case X86ISD::XTEST: return "X86ISD::XTEST";
17977 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17978 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17979 case X86ISD::SELECT: return "X86ISD::SELECT";
17980 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17981 case X86ISD::RCP28: return "X86ISD::RCP28";
17982 case X86ISD::EXP2: return "X86ISD::EXP2";
17983 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17984 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17985 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17986 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17987 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17988 case X86ISD::ADDS: return "X86ISD::ADDS";
17989 case X86ISD::SUBS: return "X86ISD::SUBS";
17994 // isLegalAddressingMode - Return true if the addressing mode represented
17995 // by AM is legal for this target, for a load/store of the specified type.
17996 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17998 // X86 supports extremely general addressing modes.
17999 CodeModel::Model M = getTargetMachine().getCodeModel();
18000 Reloc::Model R = getTargetMachine().getRelocationModel();
18002 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18003 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18008 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18010 // If a reference to this global requires an extra load, we can't fold it.
18011 if (isGlobalStubReference(GVFlags))
18014 // If BaseGV requires a register for the PIC base, we cannot also have a
18015 // BaseReg specified.
18016 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18019 // If lower 4G is not available, then we must use rip-relative addressing.
18020 if ((M != CodeModel::Small || R != Reloc::Static) &&
18021 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18025 switch (AM.Scale) {
18031 // These scales always work.
18036 // These scales are formed with basereg+scalereg. Only accept if there is
18041 default: // Other stuff never works.
18048 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18049 unsigned Bits = Ty->getScalarSizeInBits();
18051 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18052 // particularly cheaper than those without.
18056 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18057 // variable shifts just as cheap as scalar ones.
18058 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18061 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18062 // fully general vector.
18066 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18067 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18069 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18070 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18071 return NumBits1 > NumBits2;
18074 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18075 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18078 if (!isTypeLegal(EVT::getEVT(Ty1)))
18081 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18083 // Assuming the caller doesn't have a zeroext or signext return parameter,
18084 // truncation all the way down to i1 is valid.
18088 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18089 return isInt<32>(Imm);
18092 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18093 // Can also use sub to handle negated immediates.
18094 return isInt<32>(Imm);
18097 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18098 if (!VT1.isInteger() || !VT2.isInteger())
18100 unsigned NumBits1 = VT1.getSizeInBits();
18101 unsigned NumBits2 = VT2.getSizeInBits();
18102 return NumBits1 > NumBits2;
18105 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18106 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18107 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18110 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18111 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18112 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18115 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18116 EVT VT1 = Val.getValueType();
18117 if (isZExtFree(VT1, VT2))
18120 if (Val.getOpcode() != ISD::LOAD)
18123 if (!VT1.isSimple() || !VT1.isInteger() ||
18124 !VT2.isSimple() || !VT2.isInteger())
18127 switch (VT1.getSimpleVT().SimpleTy) {
18132 // X86 has 8, 16, and 32-bit zero-extending loads.
18139 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18142 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18143 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18146 VT = VT.getScalarType();
18148 if (!VT.isSimple())
18151 switch (VT.getSimpleVT().SimpleTy) {
18162 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18163 // i16 instructions are longer (0x66 prefix) and potentially slower.
18164 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18167 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18168 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18169 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18170 /// are assumed to be legal.
18172 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18174 if (!VT.isSimple())
18177 // Not for i1 vectors
18178 if (VT.getScalarType() == MVT::i1)
18181 // Very little shuffling can be done for 64-bit vectors right now.
18182 if (VT.getSizeInBits() == 64)
18185 // We only care that the types being shuffled are legal. The lowering can
18186 // handle any possible shuffle mask that results.
18187 return isTypeLegal(VT.getSimpleVT());
18191 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18193 // Just delegate to the generic legality, clear masks aren't special.
18194 return isShuffleMaskLegal(Mask, VT);
18197 //===----------------------------------------------------------------------===//
18198 // X86 Scheduler Hooks
18199 //===----------------------------------------------------------------------===//
18201 /// Utility function to emit xbegin specifying the start of an RTM region.
18202 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18203 const TargetInstrInfo *TII) {
18204 DebugLoc DL = MI->getDebugLoc();
18206 const BasicBlock *BB = MBB->getBasicBlock();
18207 MachineFunction::iterator I = MBB;
18210 // For the v = xbegin(), we generate
18221 MachineBasicBlock *thisMBB = MBB;
18222 MachineFunction *MF = MBB->getParent();
18223 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18224 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18225 MF->insert(I, mainMBB);
18226 MF->insert(I, sinkMBB);
18228 // Transfer the remainder of BB and its successor edges to sinkMBB.
18229 sinkMBB->splice(sinkMBB->begin(), MBB,
18230 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18231 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18235 // # fallthrough to mainMBB
18236 // # abortion to sinkMBB
18237 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18238 thisMBB->addSuccessor(mainMBB);
18239 thisMBB->addSuccessor(sinkMBB);
18243 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18244 mainMBB->addSuccessor(sinkMBB);
18247 // EAX is live into the sinkMBB
18248 sinkMBB->addLiveIn(X86::EAX);
18249 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18250 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18253 MI->eraseFromParent();
18257 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18258 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18259 // in the .td file.
18260 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18261 const TargetInstrInfo *TII) {
18263 switch (MI->getOpcode()) {
18264 default: llvm_unreachable("illegal opcode!");
18265 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18266 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18267 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18268 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18269 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18270 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18271 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18272 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18275 DebugLoc dl = MI->getDebugLoc();
18276 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18278 unsigned NumArgs = MI->getNumOperands();
18279 for (unsigned i = 1; i < NumArgs; ++i) {
18280 MachineOperand &Op = MI->getOperand(i);
18281 if (!(Op.isReg() && Op.isImplicit()))
18282 MIB.addOperand(Op);
18284 if (MI->hasOneMemOperand())
18285 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18287 BuildMI(*BB, MI, dl,
18288 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18289 .addReg(X86::XMM0);
18291 MI->eraseFromParent();
18295 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18296 // defs in an instruction pattern
18297 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18298 const TargetInstrInfo *TII) {
18300 switch (MI->getOpcode()) {
18301 default: llvm_unreachable("illegal opcode!");
18302 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18303 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18304 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18305 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18306 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18307 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18308 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18309 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18312 DebugLoc dl = MI->getDebugLoc();
18313 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18315 unsigned NumArgs = MI->getNumOperands(); // remove the results
18316 for (unsigned i = 1; i < NumArgs; ++i) {
18317 MachineOperand &Op = MI->getOperand(i);
18318 if (!(Op.isReg() && Op.isImplicit()))
18319 MIB.addOperand(Op);
18321 if (MI->hasOneMemOperand())
18322 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18324 BuildMI(*BB, MI, dl,
18325 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18328 MI->eraseFromParent();
18332 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18333 const X86Subtarget *Subtarget) {
18334 DebugLoc dl = MI->getDebugLoc();
18335 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18336 // Address into RAX/EAX, other two args into ECX, EDX.
18337 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18338 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18339 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18340 for (int i = 0; i < X86::AddrNumOperands; ++i)
18341 MIB.addOperand(MI->getOperand(i));
18343 unsigned ValOps = X86::AddrNumOperands;
18344 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18345 .addReg(MI->getOperand(ValOps).getReg());
18346 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18347 .addReg(MI->getOperand(ValOps+1).getReg());
18349 // The instruction doesn't actually take any operands though.
18350 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18352 MI->eraseFromParent(); // The pseudo is gone now.
18356 MachineBasicBlock *
18357 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18358 MachineBasicBlock *MBB) const {
18359 // Emit va_arg instruction on X86-64.
18361 // Operands to this pseudo-instruction:
18362 // 0 ) Output : destination address (reg)
18363 // 1-5) Input : va_list address (addr, i64mem)
18364 // 6 ) ArgSize : Size (in bytes) of vararg type
18365 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18366 // 8 ) Align : Alignment of type
18367 // 9 ) EFLAGS (implicit-def)
18369 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18370 static_assert(X86::AddrNumOperands == 5,
18371 "VAARG_64 assumes 5 address operands");
18373 unsigned DestReg = MI->getOperand(0).getReg();
18374 MachineOperand &Base = MI->getOperand(1);
18375 MachineOperand &Scale = MI->getOperand(2);
18376 MachineOperand &Index = MI->getOperand(3);
18377 MachineOperand &Disp = MI->getOperand(4);
18378 MachineOperand &Segment = MI->getOperand(5);
18379 unsigned ArgSize = MI->getOperand(6).getImm();
18380 unsigned ArgMode = MI->getOperand(7).getImm();
18381 unsigned Align = MI->getOperand(8).getImm();
18383 // Memory Reference
18384 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18385 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18386 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18388 // Machine Information
18389 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18390 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18391 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18392 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18393 DebugLoc DL = MI->getDebugLoc();
18395 // struct va_list {
18398 // i64 overflow_area (address)
18399 // i64 reg_save_area (address)
18401 // sizeof(va_list) = 24
18402 // alignment(va_list) = 8
18404 unsigned TotalNumIntRegs = 6;
18405 unsigned TotalNumXMMRegs = 8;
18406 bool UseGPOffset = (ArgMode == 1);
18407 bool UseFPOffset = (ArgMode == 2);
18408 unsigned MaxOffset = TotalNumIntRegs * 8 +
18409 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18411 /* Align ArgSize to a multiple of 8 */
18412 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18413 bool NeedsAlign = (Align > 8);
18415 MachineBasicBlock *thisMBB = MBB;
18416 MachineBasicBlock *overflowMBB;
18417 MachineBasicBlock *offsetMBB;
18418 MachineBasicBlock *endMBB;
18420 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18421 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18422 unsigned OffsetReg = 0;
18424 if (!UseGPOffset && !UseFPOffset) {
18425 // If we only pull from the overflow region, we don't create a branch.
18426 // We don't need to alter control flow.
18427 OffsetDestReg = 0; // unused
18428 OverflowDestReg = DestReg;
18430 offsetMBB = nullptr;
18431 overflowMBB = thisMBB;
18434 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18435 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18436 // If not, pull from overflow_area. (branch to overflowMBB)
18441 // offsetMBB overflowMBB
18446 // Registers for the PHI in endMBB
18447 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18448 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18450 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18451 MachineFunction *MF = MBB->getParent();
18452 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18453 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18454 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18456 MachineFunction::iterator MBBIter = MBB;
18459 // Insert the new basic blocks
18460 MF->insert(MBBIter, offsetMBB);
18461 MF->insert(MBBIter, overflowMBB);
18462 MF->insert(MBBIter, endMBB);
18464 // Transfer the remainder of MBB and its successor edges to endMBB.
18465 endMBB->splice(endMBB->begin(), thisMBB,
18466 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18467 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18469 // Make offsetMBB and overflowMBB successors of thisMBB
18470 thisMBB->addSuccessor(offsetMBB);
18471 thisMBB->addSuccessor(overflowMBB);
18473 // endMBB is a successor of both offsetMBB and overflowMBB
18474 offsetMBB->addSuccessor(endMBB);
18475 overflowMBB->addSuccessor(endMBB);
18477 // Load the offset value into a register
18478 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18479 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18483 .addDisp(Disp, UseFPOffset ? 4 : 0)
18484 .addOperand(Segment)
18485 .setMemRefs(MMOBegin, MMOEnd);
18487 // Check if there is enough room left to pull this argument.
18488 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18490 .addImm(MaxOffset + 8 - ArgSizeA8);
18492 // Branch to "overflowMBB" if offset >= max
18493 // Fall through to "offsetMBB" otherwise
18494 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18495 .addMBB(overflowMBB);
18498 // In offsetMBB, emit code to use the reg_save_area.
18500 assert(OffsetReg != 0);
18502 // Read the reg_save_area address.
18503 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18504 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18509 .addOperand(Segment)
18510 .setMemRefs(MMOBegin, MMOEnd);
18512 // Zero-extend the offset
18513 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18514 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18517 .addImm(X86::sub_32bit);
18519 // Add the offset to the reg_save_area to get the final address.
18520 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18521 .addReg(OffsetReg64)
18522 .addReg(RegSaveReg);
18524 // Compute the offset for the next argument
18525 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18526 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18528 .addImm(UseFPOffset ? 16 : 8);
18530 // Store it back into the va_list.
18531 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18535 .addDisp(Disp, UseFPOffset ? 4 : 0)
18536 .addOperand(Segment)
18537 .addReg(NextOffsetReg)
18538 .setMemRefs(MMOBegin, MMOEnd);
18541 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18546 // Emit code to use overflow area
18549 // Load the overflow_area address into a register.
18550 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18551 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18556 .addOperand(Segment)
18557 .setMemRefs(MMOBegin, MMOEnd);
18559 // If we need to align it, do so. Otherwise, just copy the address
18560 // to OverflowDestReg.
18562 // Align the overflow address
18563 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18564 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18566 // aligned_addr = (addr + (align-1)) & ~(align-1)
18567 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18568 .addReg(OverflowAddrReg)
18571 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18573 .addImm(~(uint64_t)(Align-1));
18575 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18576 .addReg(OverflowAddrReg);
18579 // Compute the next overflow address after this argument.
18580 // (the overflow address should be kept 8-byte aligned)
18581 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18582 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18583 .addReg(OverflowDestReg)
18584 .addImm(ArgSizeA8);
18586 // Store the new overflow address.
18587 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18592 .addOperand(Segment)
18593 .addReg(NextAddrReg)
18594 .setMemRefs(MMOBegin, MMOEnd);
18596 // If we branched, emit the PHI to the front of endMBB.
18598 BuildMI(*endMBB, endMBB->begin(), DL,
18599 TII->get(X86::PHI), DestReg)
18600 .addReg(OffsetDestReg).addMBB(offsetMBB)
18601 .addReg(OverflowDestReg).addMBB(overflowMBB);
18604 // Erase the pseudo instruction
18605 MI->eraseFromParent();
18610 MachineBasicBlock *
18611 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18613 MachineBasicBlock *MBB) const {
18614 // Emit code to save XMM registers to the stack. The ABI says that the
18615 // number of registers to save is given in %al, so it's theoretically
18616 // possible to do an indirect jump trick to avoid saving all of them,
18617 // however this code takes a simpler approach and just executes all
18618 // of the stores if %al is non-zero. It's less code, and it's probably
18619 // easier on the hardware branch predictor, and stores aren't all that
18620 // expensive anyway.
18622 // Create the new basic blocks. One block contains all the XMM stores,
18623 // and one block is the final destination regardless of whether any
18624 // stores were performed.
18625 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18626 MachineFunction *F = MBB->getParent();
18627 MachineFunction::iterator MBBIter = MBB;
18629 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18630 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18631 F->insert(MBBIter, XMMSaveMBB);
18632 F->insert(MBBIter, EndMBB);
18634 // Transfer the remainder of MBB and its successor edges to EndMBB.
18635 EndMBB->splice(EndMBB->begin(), MBB,
18636 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18637 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18639 // The original block will now fall through to the XMM save block.
18640 MBB->addSuccessor(XMMSaveMBB);
18641 // The XMMSaveMBB will fall through to the end block.
18642 XMMSaveMBB->addSuccessor(EndMBB);
18644 // Now add the instructions.
18645 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18646 DebugLoc DL = MI->getDebugLoc();
18648 unsigned CountReg = MI->getOperand(0).getReg();
18649 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18650 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18652 if (!Subtarget->isTargetWin64()) {
18653 // If %al is 0, branch around the XMM save block.
18654 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18655 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18656 MBB->addSuccessor(EndMBB);
18659 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18660 // that was just emitted, but clearly shouldn't be "saved".
18661 assert((MI->getNumOperands() <= 3 ||
18662 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18663 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18664 && "Expected last argument to be EFLAGS");
18665 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18666 // In the XMM save block, save all the XMM argument registers.
18667 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18668 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18669 MachineMemOperand *MMO =
18670 F->getMachineMemOperand(
18671 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18672 MachineMemOperand::MOStore,
18673 /*Size=*/16, /*Align=*/16);
18674 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18675 .addFrameIndex(RegSaveFrameIndex)
18676 .addImm(/*Scale=*/1)
18677 .addReg(/*IndexReg=*/0)
18678 .addImm(/*Disp=*/Offset)
18679 .addReg(/*Segment=*/0)
18680 .addReg(MI->getOperand(i).getReg())
18681 .addMemOperand(MMO);
18684 MI->eraseFromParent(); // The pseudo instruction is gone now.
18689 // The EFLAGS operand of SelectItr might be missing a kill marker
18690 // because there were multiple uses of EFLAGS, and ISel didn't know
18691 // which to mark. Figure out whether SelectItr should have had a
18692 // kill marker, and set it if it should. Returns the correct kill
18694 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18695 MachineBasicBlock* BB,
18696 const TargetRegisterInfo* TRI) {
18697 // Scan forward through BB for a use/def of EFLAGS.
18698 MachineBasicBlock::iterator miI(std::next(SelectItr));
18699 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18700 const MachineInstr& mi = *miI;
18701 if (mi.readsRegister(X86::EFLAGS))
18703 if (mi.definesRegister(X86::EFLAGS))
18704 break; // Should have kill-flag - update below.
18707 // If we hit the end of the block, check whether EFLAGS is live into a
18709 if (miI == BB->end()) {
18710 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18711 sEnd = BB->succ_end();
18712 sItr != sEnd; ++sItr) {
18713 MachineBasicBlock* succ = *sItr;
18714 if (succ->isLiveIn(X86::EFLAGS))
18719 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18720 // out. SelectMI should have a kill flag on EFLAGS.
18721 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18725 MachineBasicBlock *
18726 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18727 MachineBasicBlock *BB) const {
18728 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18729 DebugLoc DL = MI->getDebugLoc();
18731 // To "insert" a SELECT_CC instruction, we actually have to insert the
18732 // diamond control-flow pattern. The incoming instruction knows the
18733 // destination vreg to set, the condition code register to branch on, the
18734 // true/false values to select between, and a branch opcode to use.
18735 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18736 MachineFunction::iterator It = BB;
18742 // cmpTY ccX, r1, r2
18744 // fallthrough --> copy0MBB
18745 MachineBasicBlock *thisMBB = BB;
18746 MachineFunction *F = BB->getParent();
18748 // We also lower double CMOVs:
18749 // (CMOV (CMOV F, T, cc1), T, cc2)
18750 // to two successives branches. For that, we look for another CMOV as the
18751 // following instruction.
18753 // Without this, we would add a PHI between the two jumps, which ends up
18754 // creating a few copies all around. For instance, for
18756 // (sitofp (zext (fcmp une)))
18758 // we would generate:
18760 // ucomiss %xmm1, %xmm0
18761 // movss <1.0f>, %xmm0
18762 // movaps %xmm0, %xmm1
18764 // xorps %xmm1, %xmm1
18767 // movaps %xmm1, %xmm0
18771 // because this custom-inserter would have generated:
18783 // A: X = ...; Y = ...
18785 // C: Z = PHI [X, A], [Y, B]
18787 // E: PHI [X, C], [Z, D]
18789 // If we lower both CMOVs in a single step, we can instead generate:
18801 // A: X = ...; Y = ...
18803 // E: PHI [X, A], [X, C], [Y, D]
18805 // Which, in our sitofp/fcmp example, gives us something like:
18807 // ucomiss %xmm1, %xmm0
18808 // movss <1.0f>, %xmm0
18811 // xorps %xmm0, %xmm0
18815 MachineInstr *NextCMOV = nullptr;
18816 MachineBasicBlock::iterator NextMIIt =
18817 std::next(MachineBasicBlock::iterator(MI));
18818 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
18819 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
18820 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
18821 NextCMOV = &*NextMIIt;
18823 MachineBasicBlock *jcc1MBB = nullptr;
18825 // If we have a double CMOV, we lower it to two successive branches to
18826 // the same block. EFLAGS is used by both, so mark it as live in the second.
18828 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
18829 F->insert(It, jcc1MBB);
18830 jcc1MBB->addLiveIn(X86::EFLAGS);
18833 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18834 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18835 F->insert(It, copy0MBB);
18836 F->insert(It, sinkMBB);
18838 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18839 // live into the sink and copy blocks.
18840 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18842 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
18843 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
18844 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
18845 copy0MBB->addLiveIn(X86::EFLAGS);
18846 sinkMBB->addLiveIn(X86::EFLAGS);
18849 // Transfer the remainder of BB and its successor edges to sinkMBB.
18850 sinkMBB->splice(sinkMBB->begin(), BB,
18851 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18852 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18854 // Add the true and fallthrough blocks as its successors.
18856 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
18857 BB->addSuccessor(jcc1MBB);
18859 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
18860 // jump to the sinkMBB.
18861 jcc1MBB->addSuccessor(copy0MBB);
18862 jcc1MBB->addSuccessor(sinkMBB);
18864 BB->addSuccessor(copy0MBB);
18867 // The true block target of the first (or only) branch is always sinkMBB.
18868 BB->addSuccessor(sinkMBB);
18870 // Create the conditional branch instruction.
18872 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18873 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18876 unsigned Opc2 = X86::GetCondBranchFromCond(
18877 (X86::CondCode)NextCMOV->getOperand(3).getImm());
18878 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
18882 // %FalseValue = ...
18883 // # fallthrough to sinkMBB
18884 copy0MBB->addSuccessor(sinkMBB);
18887 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18889 MachineInstrBuilder MIB =
18890 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
18891 MI->getOperand(0).getReg())
18892 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18893 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18895 // If we have a double CMOV, the second Jcc provides the same incoming
18896 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
18898 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
18899 // Copy the PHI result to the register defined by the second CMOV.
18900 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
18901 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
18902 .addReg(MI->getOperand(0).getReg());
18903 NextCMOV->eraseFromParent();
18906 MI->eraseFromParent(); // The pseudo instruction is gone now.
18910 MachineBasicBlock *
18911 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18912 MachineBasicBlock *BB) const {
18913 MachineFunction *MF = BB->getParent();
18914 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18915 DebugLoc DL = MI->getDebugLoc();
18916 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18918 assert(MF->shouldSplitStack());
18920 const bool Is64Bit = Subtarget->is64Bit();
18921 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18923 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18924 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18927 // ... [Till the alloca]
18928 // If stacklet is not large enough, jump to mallocMBB
18931 // Allocate by subtracting from RSP
18932 // Jump to continueMBB
18935 // Allocate by call to runtime
18939 // [rest of original BB]
18942 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18943 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18944 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18946 MachineRegisterInfo &MRI = MF->getRegInfo();
18947 const TargetRegisterClass *AddrRegClass =
18948 getRegClassFor(getPointerTy());
18950 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18951 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18952 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18953 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18954 sizeVReg = MI->getOperand(1).getReg(),
18955 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18957 MachineFunction::iterator MBBIter = BB;
18960 MF->insert(MBBIter, bumpMBB);
18961 MF->insert(MBBIter, mallocMBB);
18962 MF->insert(MBBIter, continueMBB);
18964 continueMBB->splice(continueMBB->begin(), BB,
18965 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18966 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18968 // Add code to the main basic block to check if the stack limit has been hit,
18969 // and if so, jump to mallocMBB otherwise to bumpMBB.
18970 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18971 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18972 .addReg(tmpSPVReg).addReg(sizeVReg);
18973 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18974 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18975 .addReg(SPLimitVReg);
18976 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18978 // bumpMBB simply decreases the stack pointer, since we know the current
18979 // stacklet has enough space.
18980 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18981 .addReg(SPLimitVReg);
18982 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18983 .addReg(SPLimitVReg);
18984 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18986 // Calls into a routine in libgcc to allocate more space from the heap.
18987 const uint32_t *RegMask =
18988 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
18990 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18992 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18993 .addExternalSymbol("__morestack_allocate_stack_space")
18994 .addRegMask(RegMask)
18995 .addReg(X86::RDI, RegState::Implicit)
18996 .addReg(X86::RAX, RegState::ImplicitDefine);
18997 } else if (Is64Bit) {
18998 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19000 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19001 .addExternalSymbol("__morestack_allocate_stack_space")
19002 .addRegMask(RegMask)
19003 .addReg(X86::EDI, RegState::Implicit)
19004 .addReg(X86::EAX, RegState::ImplicitDefine);
19006 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19008 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19009 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19010 .addExternalSymbol("__morestack_allocate_stack_space")
19011 .addRegMask(RegMask)
19012 .addReg(X86::EAX, RegState::ImplicitDefine);
19016 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19019 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19020 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19021 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19023 // Set up the CFG correctly.
19024 BB->addSuccessor(bumpMBB);
19025 BB->addSuccessor(mallocMBB);
19026 mallocMBB->addSuccessor(continueMBB);
19027 bumpMBB->addSuccessor(continueMBB);
19029 // Take care of the PHI nodes.
19030 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19031 MI->getOperand(0).getReg())
19032 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19033 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19035 // Delete the original pseudo instruction.
19036 MI->eraseFromParent();
19039 return continueMBB;
19042 MachineBasicBlock *
19043 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19044 MachineBasicBlock *BB) const {
19045 DebugLoc DL = MI->getDebugLoc();
19047 assert(!Subtarget->isTargetMachO());
19049 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19051 MI->eraseFromParent(); // The pseudo instruction is gone now.
19055 MachineBasicBlock *
19056 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19057 MachineBasicBlock *BB) const {
19058 // This is pretty easy. We're taking the value that we received from
19059 // our load from the relocation, sticking it in either RDI (x86-64)
19060 // or EAX and doing an indirect call. The return value will then
19061 // be in the normal return register.
19062 MachineFunction *F = BB->getParent();
19063 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19064 DebugLoc DL = MI->getDebugLoc();
19066 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19067 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19069 // Get a register mask for the lowered call.
19070 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19071 // proper register mask.
19072 const uint32_t *RegMask =
19073 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19074 if (Subtarget->is64Bit()) {
19075 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19076 TII->get(X86::MOV64rm), X86::RDI)
19078 .addImm(0).addReg(0)
19079 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19080 MI->getOperand(3).getTargetFlags())
19082 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19083 addDirectMem(MIB, X86::RDI);
19084 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19085 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19086 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19087 TII->get(X86::MOV32rm), X86::EAX)
19089 .addImm(0).addReg(0)
19090 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19091 MI->getOperand(3).getTargetFlags())
19093 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19094 addDirectMem(MIB, X86::EAX);
19095 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19097 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19098 TII->get(X86::MOV32rm), X86::EAX)
19099 .addReg(TII->getGlobalBaseReg(F))
19100 .addImm(0).addReg(0)
19101 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19102 MI->getOperand(3).getTargetFlags())
19104 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19105 addDirectMem(MIB, X86::EAX);
19106 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19109 MI->eraseFromParent(); // The pseudo instruction is gone now.
19113 MachineBasicBlock *
19114 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19115 MachineBasicBlock *MBB) const {
19116 DebugLoc DL = MI->getDebugLoc();
19117 MachineFunction *MF = MBB->getParent();
19118 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19119 MachineRegisterInfo &MRI = MF->getRegInfo();
19121 const BasicBlock *BB = MBB->getBasicBlock();
19122 MachineFunction::iterator I = MBB;
19125 // Memory Reference
19126 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19127 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19130 unsigned MemOpndSlot = 0;
19132 unsigned CurOp = 0;
19134 DstReg = MI->getOperand(CurOp++).getReg();
19135 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19136 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19137 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19138 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19140 MemOpndSlot = CurOp;
19142 MVT PVT = getPointerTy();
19143 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19144 "Invalid Pointer Size!");
19146 // For v = setjmp(buf), we generate
19149 // buf[LabelOffset] = restoreMBB
19150 // SjLjSetup restoreMBB
19156 // v = phi(main, restore)
19159 // if base pointer being used, load it from frame
19162 MachineBasicBlock *thisMBB = MBB;
19163 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19164 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19165 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19166 MF->insert(I, mainMBB);
19167 MF->insert(I, sinkMBB);
19168 MF->push_back(restoreMBB);
19170 MachineInstrBuilder MIB;
19172 // Transfer the remainder of BB and its successor edges to sinkMBB.
19173 sinkMBB->splice(sinkMBB->begin(), MBB,
19174 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19175 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19178 unsigned PtrStoreOpc = 0;
19179 unsigned LabelReg = 0;
19180 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19181 Reloc::Model RM = MF->getTarget().getRelocationModel();
19182 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19183 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19185 // Prepare IP either in reg or imm.
19186 if (!UseImmLabel) {
19187 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19188 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19189 LabelReg = MRI.createVirtualRegister(PtrRC);
19190 if (Subtarget->is64Bit()) {
19191 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19195 .addMBB(restoreMBB)
19198 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19199 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19200 .addReg(XII->getGlobalBaseReg(MF))
19203 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19207 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19209 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19210 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19211 if (i == X86::AddrDisp)
19212 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19214 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19217 MIB.addReg(LabelReg);
19219 MIB.addMBB(restoreMBB);
19220 MIB.setMemRefs(MMOBegin, MMOEnd);
19222 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19223 .addMBB(restoreMBB);
19225 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19226 MIB.addRegMask(RegInfo->getNoPreservedMask());
19227 thisMBB->addSuccessor(mainMBB);
19228 thisMBB->addSuccessor(restoreMBB);
19232 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19233 mainMBB->addSuccessor(sinkMBB);
19236 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19237 TII->get(X86::PHI), DstReg)
19238 .addReg(mainDstReg).addMBB(mainMBB)
19239 .addReg(restoreDstReg).addMBB(restoreMBB);
19242 if (RegInfo->hasBasePointer(*MF)) {
19243 const bool Uses64BitFramePtr =
19244 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19245 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19246 X86FI->setRestoreBasePointer(MF);
19247 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19248 unsigned BasePtr = RegInfo->getBaseRegister();
19249 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19250 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19251 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19252 .setMIFlag(MachineInstr::FrameSetup);
19254 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19255 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19256 restoreMBB->addSuccessor(sinkMBB);
19258 MI->eraseFromParent();
19262 MachineBasicBlock *
19263 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19264 MachineBasicBlock *MBB) const {
19265 DebugLoc DL = MI->getDebugLoc();
19266 MachineFunction *MF = MBB->getParent();
19267 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19268 MachineRegisterInfo &MRI = MF->getRegInfo();
19270 // Memory Reference
19271 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19272 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19274 MVT PVT = getPointerTy();
19275 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19276 "Invalid Pointer Size!");
19278 const TargetRegisterClass *RC =
19279 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19280 unsigned Tmp = MRI.createVirtualRegister(RC);
19281 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19282 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19283 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19284 unsigned SP = RegInfo->getStackRegister();
19286 MachineInstrBuilder MIB;
19288 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19289 const int64_t SPOffset = 2 * PVT.getStoreSize();
19291 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19292 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19295 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19296 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19297 MIB.addOperand(MI->getOperand(i));
19298 MIB.setMemRefs(MMOBegin, MMOEnd);
19300 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19301 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19302 if (i == X86::AddrDisp)
19303 MIB.addDisp(MI->getOperand(i), LabelOffset);
19305 MIB.addOperand(MI->getOperand(i));
19307 MIB.setMemRefs(MMOBegin, MMOEnd);
19309 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19310 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19311 if (i == X86::AddrDisp)
19312 MIB.addDisp(MI->getOperand(i), SPOffset);
19314 MIB.addOperand(MI->getOperand(i));
19316 MIB.setMemRefs(MMOBegin, MMOEnd);
19318 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19320 MI->eraseFromParent();
19324 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19325 // accumulator loops. Writing back to the accumulator allows the coalescer
19326 // to remove extra copies in the loop.
19327 MachineBasicBlock *
19328 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19329 MachineBasicBlock *MBB) const {
19330 MachineOperand &AddendOp = MI->getOperand(3);
19332 // Bail out early if the addend isn't a register - we can't switch these.
19333 if (!AddendOp.isReg())
19336 MachineFunction &MF = *MBB->getParent();
19337 MachineRegisterInfo &MRI = MF.getRegInfo();
19339 // Check whether the addend is defined by a PHI:
19340 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19341 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19342 if (!AddendDef.isPHI())
19345 // Look for the following pattern:
19347 // %addend = phi [%entry, 0], [%loop, %result]
19349 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19353 // %addend = phi [%entry, 0], [%loop, %result]
19355 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19357 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19358 assert(AddendDef.getOperand(i).isReg());
19359 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19360 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19361 if (&PHISrcInst == MI) {
19362 // Found a matching instruction.
19363 unsigned NewFMAOpc = 0;
19364 switch (MI->getOpcode()) {
19365 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19366 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19367 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19368 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19369 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19370 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19371 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19372 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19373 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19374 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19375 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19376 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19377 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19378 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19379 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19380 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19381 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19382 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19383 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19384 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19386 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19387 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19388 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19389 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19390 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19391 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19392 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19393 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19394 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19395 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19396 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19397 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19398 default: llvm_unreachable("Unrecognized FMA variant.");
19401 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19402 MachineInstrBuilder MIB =
19403 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19404 .addOperand(MI->getOperand(0))
19405 .addOperand(MI->getOperand(3))
19406 .addOperand(MI->getOperand(2))
19407 .addOperand(MI->getOperand(1));
19408 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19409 MI->eraseFromParent();
19416 MachineBasicBlock *
19417 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19418 MachineBasicBlock *BB) const {
19419 switch (MI->getOpcode()) {
19420 default: llvm_unreachable("Unexpected instr type to insert");
19421 case X86::TAILJMPd64:
19422 case X86::TAILJMPr64:
19423 case X86::TAILJMPm64:
19424 case X86::TAILJMPd64_REX:
19425 case X86::TAILJMPr64_REX:
19426 case X86::TAILJMPm64_REX:
19427 llvm_unreachable("TAILJMP64 would not be touched here.");
19428 case X86::TCRETURNdi64:
19429 case X86::TCRETURNri64:
19430 case X86::TCRETURNmi64:
19432 case X86::WIN_ALLOCA:
19433 return EmitLoweredWinAlloca(MI, BB);
19434 case X86::SEG_ALLOCA_32:
19435 case X86::SEG_ALLOCA_64:
19436 return EmitLoweredSegAlloca(MI, BB);
19437 case X86::TLSCall_32:
19438 case X86::TLSCall_64:
19439 return EmitLoweredTLSCall(MI, BB);
19440 case X86::CMOV_GR8:
19441 case X86::CMOV_FR32:
19442 case X86::CMOV_FR64:
19443 case X86::CMOV_V4F32:
19444 case X86::CMOV_V2F64:
19445 case X86::CMOV_V2I64:
19446 case X86::CMOV_V8F32:
19447 case X86::CMOV_V4F64:
19448 case X86::CMOV_V4I64:
19449 case X86::CMOV_V16F32:
19450 case X86::CMOV_V8F64:
19451 case X86::CMOV_V8I64:
19452 case X86::CMOV_GR16:
19453 case X86::CMOV_GR32:
19454 case X86::CMOV_RFP32:
19455 case X86::CMOV_RFP64:
19456 case X86::CMOV_RFP80:
19457 case X86::CMOV_V8I1:
19458 case X86::CMOV_V16I1:
19459 case X86::CMOV_V32I1:
19460 case X86::CMOV_V64I1:
19461 return EmitLoweredSelect(MI, BB);
19463 case X86::FP32_TO_INT16_IN_MEM:
19464 case X86::FP32_TO_INT32_IN_MEM:
19465 case X86::FP32_TO_INT64_IN_MEM:
19466 case X86::FP64_TO_INT16_IN_MEM:
19467 case X86::FP64_TO_INT32_IN_MEM:
19468 case X86::FP64_TO_INT64_IN_MEM:
19469 case X86::FP80_TO_INT16_IN_MEM:
19470 case X86::FP80_TO_INT32_IN_MEM:
19471 case X86::FP80_TO_INT64_IN_MEM: {
19472 MachineFunction *F = BB->getParent();
19473 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19474 DebugLoc DL = MI->getDebugLoc();
19476 // Change the floating point control register to use "round towards zero"
19477 // mode when truncating to an integer value.
19478 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19479 addFrameReference(BuildMI(*BB, MI, DL,
19480 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19482 // Load the old value of the high byte of the control word...
19484 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19485 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19488 // Set the high part to be round to zero...
19489 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19492 // Reload the modified control word now...
19493 addFrameReference(BuildMI(*BB, MI, DL,
19494 TII->get(X86::FLDCW16m)), CWFrameIdx);
19496 // Restore the memory image of control word to original value
19497 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19500 // Get the X86 opcode to use.
19502 switch (MI->getOpcode()) {
19503 default: llvm_unreachable("illegal opcode!");
19504 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19505 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19506 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19507 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19508 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19509 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19510 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19511 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19512 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19516 MachineOperand &Op = MI->getOperand(0);
19518 AM.BaseType = X86AddressMode::RegBase;
19519 AM.Base.Reg = Op.getReg();
19521 AM.BaseType = X86AddressMode::FrameIndexBase;
19522 AM.Base.FrameIndex = Op.getIndex();
19524 Op = MI->getOperand(1);
19526 AM.Scale = Op.getImm();
19527 Op = MI->getOperand(2);
19529 AM.IndexReg = Op.getImm();
19530 Op = MI->getOperand(3);
19531 if (Op.isGlobal()) {
19532 AM.GV = Op.getGlobal();
19534 AM.Disp = Op.getImm();
19536 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19537 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19539 // Reload the original control word now.
19540 addFrameReference(BuildMI(*BB, MI, DL,
19541 TII->get(X86::FLDCW16m)), CWFrameIdx);
19543 MI->eraseFromParent(); // The pseudo instruction is gone now.
19546 // String/text processing lowering.
19547 case X86::PCMPISTRM128REG:
19548 case X86::VPCMPISTRM128REG:
19549 case X86::PCMPISTRM128MEM:
19550 case X86::VPCMPISTRM128MEM:
19551 case X86::PCMPESTRM128REG:
19552 case X86::VPCMPESTRM128REG:
19553 case X86::PCMPESTRM128MEM:
19554 case X86::VPCMPESTRM128MEM:
19555 assert(Subtarget->hasSSE42() &&
19556 "Target must have SSE4.2 or AVX features enabled");
19557 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19559 // String/text processing lowering.
19560 case X86::PCMPISTRIREG:
19561 case X86::VPCMPISTRIREG:
19562 case X86::PCMPISTRIMEM:
19563 case X86::VPCMPISTRIMEM:
19564 case X86::PCMPESTRIREG:
19565 case X86::VPCMPESTRIREG:
19566 case X86::PCMPESTRIMEM:
19567 case X86::VPCMPESTRIMEM:
19568 assert(Subtarget->hasSSE42() &&
19569 "Target must have SSE4.2 or AVX features enabled");
19570 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19572 // Thread synchronization.
19574 return EmitMonitor(MI, BB, Subtarget);
19578 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19580 case X86::VASTART_SAVE_XMM_REGS:
19581 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19583 case X86::VAARG_64:
19584 return EmitVAARG64WithCustomInserter(MI, BB);
19586 case X86::EH_SjLj_SetJmp32:
19587 case X86::EH_SjLj_SetJmp64:
19588 return emitEHSjLjSetJmp(MI, BB);
19590 case X86::EH_SjLj_LongJmp32:
19591 case X86::EH_SjLj_LongJmp64:
19592 return emitEHSjLjLongJmp(MI, BB);
19594 case TargetOpcode::STATEPOINT:
19595 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19596 // this point in the process. We diverge later.
19597 return emitPatchPoint(MI, BB);
19599 case TargetOpcode::STACKMAP:
19600 case TargetOpcode::PATCHPOINT:
19601 return emitPatchPoint(MI, BB);
19603 case X86::VFMADDPDr213r:
19604 case X86::VFMADDPSr213r:
19605 case X86::VFMADDSDr213r:
19606 case X86::VFMADDSSr213r:
19607 case X86::VFMSUBPDr213r:
19608 case X86::VFMSUBPSr213r:
19609 case X86::VFMSUBSDr213r:
19610 case X86::VFMSUBSSr213r:
19611 case X86::VFNMADDPDr213r:
19612 case X86::VFNMADDPSr213r:
19613 case X86::VFNMADDSDr213r:
19614 case X86::VFNMADDSSr213r:
19615 case X86::VFNMSUBPDr213r:
19616 case X86::VFNMSUBPSr213r:
19617 case X86::VFNMSUBSDr213r:
19618 case X86::VFNMSUBSSr213r:
19619 case X86::VFMADDSUBPDr213r:
19620 case X86::VFMADDSUBPSr213r:
19621 case X86::VFMSUBADDPDr213r:
19622 case X86::VFMSUBADDPSr213r:
19623 case X86::VFMADDPDr213rY:
19624 case X86::VFMADDPSr213rY:
19625 case X86::VFMSUBPDr213rY:
19626 case X86::VFMSUBPSr213rY:
19627 case X86::VFNMADDPDr213rY:
19628 case X86::VFNMADDPSr213rY:
19629 case X86::VFNMSUBPDr213rY:
19630 case X86::VFNMSUBPSr213rY:
19631 case X86::VFMADDSUBPDr213rY:
19632 case X86::VFMADDSUBPSr213rY:
19633 case X86::VFMSUBADDPDr213rY:
19634 case X86::VFMSUBADDPSr213rY:
19635 return emitFMA3Instr(MI, BB);
19639 //===----------------------------------------------------------------------===//
19640 // X86 Optimization Hooks
19641 //===----------------------------------------------------------------------===//
19643 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19646 const SelectionDAG &DAG,
19647 unsigned Depth) const {
19648 unsigned BitWidth = KnownZero.getBitWidth();
19649 unsigned Opc = Op.getOpcode();
19650 assert((Opc >= ISD::BUILTIN_OP_END ||
19651 Opc == ISD::INTRINSIC_WO_CHAIN ||
19652 Opc == ISD::INTRINSIC_W_CHAIN ||
19653 Opc == ISD::INTRINSIC_VOID) &&
19654 "Should use MaskedValueIsZero if you don't know whether Op"
19655 " is a target node!");
19657 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19671 // These nodes' second result is a boolean.
19672 if (Op.getResNo() == 0)
19675 case X86ISD::SETCC:
19676 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19678 case ISD::INTRINSIC_WO_CHAIN: {
19679 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19680 unsigned NumLoBits = 0;
19683 case Intrinsic::x86_sse_movmsk_ps:
19684 case Intrinsic::x86_avx_movmsk_ps_256:
19685 case Intrinsic::x86_sse2_movmsk_pd:
19686 case Intrinsic::x86_avx_movmsk_pd_256:
19687 case Intrinsic::x86_mmx_pmovmskb:
19688 case Intrinsic::x86_sse2_pmovmskb_128:
19689 case Intrinsic::x86_avx2_pmovmskb: {
19690 // High bits of movmskp{s|d}, pmovmskb are known zero.
19692 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19693 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19694 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19695 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19696 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19697 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19698 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19699 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19701 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19710 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19712 const SelectionDAG &,
19713 unsigned Depth) const {
19714 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19715 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19716 return Op.getValueType().getScalarType().getSizeInBits();
19722 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19723 /// node is a GlobalAddress + offset.
19724 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19725 const GlobalValue* &GA,
19726 int64_t &Offset) const {
19727 if (N->getOpcode() == X86ISD::Wrapper) {
19728 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19729 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19730 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19734 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19737 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19738 /// same as extracting the high 128-bit part of 256-bit vector and then
19739 /// inserting the result into the low part of a new 256-bit vector
19740 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19741 EVT VT = SVOp->getValueType(0);
19742 unsigned NumElems = VT.getVectorNumElements();
19744 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19745 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19746 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19747 SVOp->getMaskElt(j) >= 0)
19753 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19754 /// same as extracting the low 128-bit part of 256-bit vector and then
19755 /// inserting the result into the high part of a new 256-bit vector
19756 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19757 EVT VT = SVOp->getValueType(0);
19758 unsigned NumElems = VT.getVectorNumElements();
19760 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19761 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19762 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19763 SVOp->getMaskElt(j) >= 0)
19769 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19770 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19771 TargetLowering::DAGCombinerInfo &DCI,
19772 const X86Subtarget* Subtarget) {
19774 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19775 SDValue V1 = SVOp->getOperand(0);
19776 SDValue V2 = SVOp->getOperand(1);
19777 EVT VT = SVOp->getValueType(0);
19778 unsigned NumElems = VT.getVectorNumElements();
19780 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19781 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19785 // V UNDEF BUILD_VECTOR UNDEF
19787 // CONCAT_VECTOR CONCAT_VECTOR
19790 // RESULT: V + zero extended
19792 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19793 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19794 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19797 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19800 // To match the shuffle mask, the first half of the mask should
19801 // be exactly the first vector, and all the rest a splat with the
19802 // first element of the second one.
19803 for (unsigned i = 0; i != NumElems/2; ++i)
19804 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19805 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19808 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19809 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19810 if (Ld->hasNUsesOfValue(1, 0)) {
19811 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19812 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19814 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19816 Ld->getPointerInfo(),
19817 Ld->getAlignment(),
19818 false/*isVolatile*/, true/*ReadMem*/,
19819 false/*WriteMem*/);
19821 // Make sure the newly-created LOAD is in the same position as Ld in
19822 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19823 // and update uses of Ld's output chain to use the TokenFactor.
19824 if (Ld->hasAnyUseOfValue(1)) {
19825 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19826 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19827 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19828 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19829 SDValue(ResNode.getNode(), 1));
19832 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19836 // Emit a zeroed vector and insert the desired subvector on its
19838 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19839 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19840 return DCI.CombineTo(N, InsV);
19843 //===--------------------------------------------------------------------===//
19844 // Combine some shuffles into subvector extracts and inserts:
19847 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19848 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19849 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19850 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19851 return DCI.CombineTo(N, InsV);
19854 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19855 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19856 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19857 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19858 return DCI.CombineTo(N, InsV);
19864 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19867 /// This is the leaf of the recursive combinine below. When we have found some
19868 /// chain of single-use x86 shuffle instructions and accumulated the combined
19869 /// shuffle mask represented by them, this will try to pattern match that mask
19870 /// into either a single instruction if there is a special purpose instruction
19871 /// for this operation, or into a PSHUFB instruction which is a fully general
19872 /// instruction but should only be used to replace chains over a certain depth.
19873 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19874 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19875 TargetLowering::DAGCombinerInfo &DCI,
19876 const X86Subtarget *Subtarget) {
19877 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19879 // Find the operand that enters the chain. Note that multiple uses are OK
19880 // here, we're not going to remove the operand we find.
19881 SDValue Input = Op.getOperand(0);
19882 while (Input.getOpcode() == ISD::BITCAST)
19883 Input = Input.getOperand(0);
19885 MVT VT = Input.getSimpleValueType();
19886 MVT RootVT = Root.getSimpleValueType();
19889 // Just remove no-op shuffle masks.
19890 if (Mask.size() == 1) {
19891 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19896 // Use the float domain if the operand type is a floating point type.
19897 bool FloatDomain = VT.isFloatingPoint();
19899 // For floating point shuffles, we don't have free copies in the shuffle
19900 // instructions or the ability to load as part of the instruction, so
19901 // canonicalize their shuffles to UNPCK or MOV variants.
19903 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19904 // vectors because it can have a load folded into it that UNPCK cannot. This
19905 // doesn't preclude something switching to the shorter encoding post-RA.
19907 // FIXME: Should teach these routines about AVX vector widths.
19908 if (FloatDomain && VT.getSizeInBits() == 128) {
19909 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
19910 bool Lo = Mask.equals({0, 0});
19913 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19914 // is no slower than UNPCKLPD but has the option to fold the input operand
19915 // into even an unaligned memory load.
19916 if (Lo && Subtarget->hasSSE3()) {
19917 Shuffle = X86ISD::MOVDDUP;
19918 ShuffleVT = MVT::v2f64;
19920 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19921 // than the UNPCK variants.
19922 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19923 ShuffleVT = MVT::v4f32;
19925 if (Depth == 1 && Root->getOpcode() == Shuffle)
19926 return false; // Nothing to do!
19927 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19928 DCI.AddToWorklist(Op.getNode());
19929 if (Shuffle == X86ISD::MOVDDUP)
19930 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19932 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19933 DCI.AddToWorklist(Op.getNode());
19934 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19938 if (Subtarget->hasSSE3() &&
19939 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
19940 bool Lo = Mask.equals({0, 0, 2, 2});
19941 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19942 MVT ShuffleVT = MVT::v4f32;
19943 if (Depth == 1 && Root->getOpcode() == Shuffle)
19944 return false; // Nothing to do!
19945 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19946 DCI.AddToWorklist(Op.getNode());
19947 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19948 DCI.AddToWorklist(Op.getNode());
19949 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19953 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
19954 bool Lo = Mask.equals({0, 0, 1, 1});
19955 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19956 MVT ShuffleVT = MVT::v4f32;
19957 if (Depth == 1 && Root->getOpcode() == Shuffle)
19958 return false; // Nothing to do!
19959 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19960 DCI.AddToWorklist(Op.getNode());
19961 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19962 DCI.AddToWorklist(Op.getNode());
19963 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19969 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19970 // variants as none of these have single-instruction variants that are
19971 // superior to the UNPCK formulation.
19972 if (!FloatDomain && VT.getSizeInBits() == 128 &&
19973 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
19974 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
19975 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
19977 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
19978 bool Lo = Mask[0] == 0;
19979 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19980 if (Depth == 1 && Root->getOpcode() == Shuffle)
19981 return false; // Nothing to do!
19983 switch (Mask.size()) {
19985 ShuffleVT = MVT::v8i16;
19988 ShuffleVT = MVT::v16i8;
19991 llvm_unreachable("Impossible mask size!");
19993 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19994 DCI.AddToWorklist(Op.getNode());
19995 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19996 DCI.AddToWorklist(Op.getNode());
19997 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20002 // Don't try to re-form single instruction chains under any circumstances now
20003 // that we've done encoding canonicalization for them.
20007 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20008 // can replace them with a single PSHUFB instruction profitably. Intel's
20009 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20010 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20011 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20012 SmallVector<SDValue, 16> PSHUFBMask;
20013 int NumBytes = VT.getSizeInBits() / 8;
20014 int Ratio = NumBytes / Mask.size();
20015 for (int i = 0; i < NumBytes; ++i) {
20016 if (Mask[i / Ratio] == SM_SentinelUndef) {
20017 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20020 int M = Mask[i / Ratio] != SM_SentinelZero
20021 ? Ratio * Mask[i / Ratio] + i % Ratio
20023 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20025 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20026 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
20027 DCI.AddToWorklist(Op.getNode());
20028 SDValue PSHUFBMaskOp =
20029 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20030 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20031 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20032 DCI.AddToWorklist(Op.getNode());
20033 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20038 // Failed to find any combines.
20042 /// \brief Fully generic combining of x86 shuffle instructions.
20044 /// This should be the last combine run over the x86 shuffle instructions. Once
20045 /// they have been fully optimized, this will recursively consider all chains
20046 /// of single-use shuffle instructions, build a generic model of the cumulative
20047 /// shuffle operation, and check for simpler instructions which implement this
20048 /// operation. We use this primarily for two purposes:
20050 /// 1) Collapse generic shuffles to specialized single instructions when
20051 /// equivalent. In most cases, this is just an encoding size win, but
20052 /// sometimes we will collapse multiple generic shuffles into a single
20053 /// special-purpose shuffle.
20054 /// 2) Look for sequences of shuffle instructions with 3 or more total
20055 /// instructions, and replace them with the slightly more expensive SSSE3
20056 /// PSHUFB instruction if available. We do this as the last combining step
20057 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20058 /// a suitable short sequence of other instructions. The PHUFB will either
20059 /// use a register or have to read from memory and so is slightly (but only
20060 /// slightly) more expensive than the other shuffle instructions.
20062 /// Because this is inherently a quadratic operation (for each shuffle in
20063 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20064 /// This should never be an issue in practice as the shuffle lowering doesn't
20065 /// produce sequences of more than 8 instructions.
20067 /// FIXME: We will currently miss some cases where the redundant shuffling
20068 /// would simplify under the threshold for PSHUFB formation because of
20069 /// combine-ordering. To fix this, we should do the redundant instruction
20070 /// combining in this recursive walk.
20071 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20072 ArrayRef<int> RootMask,
20073 int Depth, bool HasPSHUFB,
20075 TargetLowering::DAGCombinerInfo &DCI,
20076 const X86Subtarget *Subtarget) {
20077 // Bound the depth of our recursive combine because this is ultimately
20078 // quadratic in nature.
20082 // Directly rip through bitcasts to find the underlying operand.
20083 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20084 Op = Op.getOperand(0);
20086 MVT VT = Op.getSimpleValueType();
20087 if (!VT.isVector())
20088 return false; // Bail if we hit a non-vector.
20090 assert(Root.getSimpleValueType().isVector() &&
20091 "Shuffles operate on vector types!");
20092 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20093 "Can only combine shuffles of the same vector register size.");
20095 if (!isTargetShuffle(Op.getOpcode()))
20097 SmallVector<int, 16> OpMask;
20099 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20100 // We only can combine unary shuffles which we can decode the mask for.
20101 if (!HaveMask || !IsUnary)
20104 assert(VT.getVectorNumElements() == OpMask.size() &&
20105 "Different mask size from vector size!");
20106 assert(((RootMask.size() > OpMask.size() &&
20107 RootMask.size() % OpMask.size() == 0) ||
20108 (OpMask.size() > RootMask.size() &&
20109 OpMask.size() % RootMask.size() == 0) ||
20110 OpMask.size() == RootMask.size()) &&
20111 "The smaller number of elements must divide the larger.");
20112 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20113 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20114 assert(((RootRatio == 1 && OpRatio == 1) ||
20115 (RootRatio == 1) != (OpRatio == 1)) &&
20116 "Must not have a ratio for both incoming and op masks!");
20118 SmallVector<int, 16> Mask;
20119 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20121 // Merge this shuffle operation's mask into our accumulated mask. Note that
20122 // this shuffle's mask will be the first applied to the input, followed by the
20123 // root mask to get us all the way to the root value arrangement. The reason
20124 // for this order is that we are recursing up the operation chain.
20125 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20126 int RootIdx = i / RootRatio;
20127 if (RootMask[RootIdx] < 0) {
20128 // This is a zero or undef lane, we're done.
20129 Mask.push_back(RootMask[RootIdx]);
20133 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20134 int OpIdx = RootMaskedIdx / OpRatio;
20135 if (OpMask[OpIdx] < 0) {
20136 // The incoming lanes are zero or undef, it doesn't matter which ones we
20138 Mask.push_back(OpMask[OpIdx]);
20142 // Ok, we have non-zero lanes, map them through.
20143 Mask.push_back(OpMask[OpIdx] * OpRatio +
20144 RootMaskedIdx % OpRatio);
20147 // See if we can recurse into the operand to combine more things.
20148 switch (Op.getOpcode()) {
20149 case X86ISD::PSHUFB:
20151 case X86ISD::PSHUFD:
20152 case X86ISD::PSHUFHW:
20153 case X86ISD::PSHUFLW:
20154 if (Op.getOperand(0).hasOneUse() &&
20155 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20156 HasPSHUFB, DAG, DCI, Subtarget))
20160 case X86ISD::UNPCKL:
20161 case X86ISD::UNPCKH:
20162 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20163 // We can't check for single use, we have to check that this shuffle is the only user.
20164 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20165 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20166 HasPSHUFB, DAG, DCI, Subtarget))
20171 // Minor canonicalization of the accumulated shuffle mask to make it easier
20172 // to match below. All this does is detect masks with squential pairs of
20173 // elements, and shrink them to the half-width mask. It does this in a loop
20174 // so it will reduce the size of the mask to the minimal width mask which
20175 // performs an equivalent shuffle.
20176 SmallVector<int, 16> WidenedMask;
20177 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20178 Mask = std::move(WidenedMask);
20179 WidenedMask.clear();
20182 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20186 /// \brief Get the PSHUF-style mask from PSHUF node.
20188 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20189 /// PSHUF-style masks that can be reused with such instructions.
20190 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20191 MVT VT = N.getSimpleValueType();
20192 SmallVector<int, 4> Mask;
20194 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20198 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20199 // matter. Check that the upper masks are repeats and remove them.
20200 if (VT.getSizeInBits() > 128) {
20201 int LaneElts = 128 / VT.getScalarSizeInBits();
20203 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20204 for (int j = 0; j < LaneElts; ++j)
20205 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
20206 "Mask doesn't repeat in high 128-bit lanes!");
20208 Mask.resize(LaneElts);
20211 switch (N.getOpcode()) {
20212 case X86ISD::PSHUFD:
20214 case X86ISD::PSHUFLW:
20217 case X86ISD::PSHUFHW:
20218 Mask.erase(Mask.begin(), Mask.begin() + 4);
20219 for (int &M : Mask)
20223 llvm_unreachable("No valid shuffle instruction found!");
20227 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20229 /// We walk up the chain and look for a combinable shuffle, skipping over
20230 /// shuffles that we could hoist this shuffle's transformation past without
20231 /// altering anything.
20233 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20235 TargetLowering::DAGCombinerInfo &DCI) {
20236 assert(N.getOpcode() == X86ISD::PSHUFD &&
20237 "Called with something other than an x86 128-bit half shuffle!");
20240 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20241 // of the shuffles in the chain so that we can form a fresh chain to replace
20243 SmallVector<SDValue, 8> Chain;
20244 SDValue V = N.getOperand(0);
20245 for (; V.hasOneUse(); V = V.getOperand(0)) {
20246 switch (V.getOpcode()) {
20248 return SDValue(); // Nothing combined!
20251 // Skip bitcasts as we always know the type for the target specific
20255 case X86ISD::PSHUFD:
20256 // Found another dword shuffle.
20259 case X86ISD::PSHUFLW:
20260 // Check that the low words (being shuffled) are the identity in the
20261 // dword shuffle, and the high words are self-contained.
20262 if (Mask[0] != 0 || Mask[1] != 1 ||
20263 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20266 Chain.push_back(V);
20269 case X86ISD::PSHUFHW:
20270 // Check that the high words (being shuffled) are the identity in the
20271 // dword shuffle, and the low words are self-contained.
20272 if (Mask[2] != 2 || Mask[3] != 3 ||
20273 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20276 Chain.push_back(V);
20279 case X86ISD::UNPCKL:
20280 case X86ISD::UNPCKH:
20281 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20282 // shuffle into a preceding word shuffle.
20283 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20284 V.getSimpleValueType().getScalarType() != MVT::i16)
20287 // Search for a half-shuffle which we can combine with.
20288 unsigned CombineOp =
20289 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20290 if (V.getOperand(0) != V.getOperand(1) ||
20291 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20293 Chain.push_back(V);
20294 V = V.getOperand(0);
20296 switch (V.getOpcode()) {
20298 return SDValue(); // Nothing to combine.
20300 case X86ISD::PSHUFLW:
20301 case X86ISD::PSHUFHW:
20302 if (V.getOpcode() == CombineOp)
20305 Chain.push_back(V);
20309 V = V.getOperand(0);
20313 } while (V.hasOneUse());
20316 // Break out of the loop if we break out of the switch.
20320 if (!V.hasOneUse())
20321 // We fell out of the loop without finding a viable combining instruction.
20324 // Merge this node's mask and our incoming mask.
20325 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20326 for (int &M : Mask)
20328 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20329 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20331 // Rebuild the chain around this new shuffle.
20332 while (!Chain.empty()) {
20333 SDValue W = Chain.pop_back_val();
20335 if (V.getValueType() != W.getOperand(0).getValueType())
20336 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20338 switch (W.getOpcode()) {
20340 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20342 case X86ISD::UNPCKL:
20343 case X86ISD::UNPCKH:
20344 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20347 case X86ISD::PSHUFD:
20348 case X86ISD::PSHUFLW:
20349 case X86ISD::PSHUFHW:
20350 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20354 if (V.getValueType() != N.getValueType())
20355 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20357 // Return the new chain to replace N.
20361 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20363 /// We walk up the chain, skipping shuffles of the other half and looking
20364 /// through shuffles which switch halves trying to find a shuffle of the same
20365 /// pair of dwords.
20366 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20368 TargetLowering::DAGCombinerInfo &DCI) {
20370 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20371 "Called with something other than an x86 128-bit half shuffle!");
20373 unsigned CombineOpcode = N.getOpcode();
20375 // Walk up a single-use chain looking for a combinable shuffle.
20376 SDValue V = N.getOperand(0);
20377 for (; V.hasOneUse(); V = V.getOperand(0)) {
20378 switch (V.getOpcode()) {
20380 return false; // Nothing combined!
20383 // Skip bitcasts as we always know the type for the target specific
20387 case X86ISD::PSHUFLW:
20388 case X86ISD::PSHUFHW:
20389 if (V.getOpcode() == CombineOpcode)
20392 // Other-half shuffles are no-ops.
20395 // Break out of the loop if we break out of the switch.
20399 if (!V.hasOneUse())
20400 // We fell out of the loop without finding a viable combining instruction.
20403 // Combine away the bottom node as its shuffle will be accumulated into
20404 // a preceding shuffle.
20405 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20407 // Record the old value.
20410 // Merge this node's mask and our incoming mask (adjusted to account for all
20411 // the pshufd instructions encountered).
20412 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20413 for (int &M : Mask)
20415 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20416 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20418 // Check that the shuffles didn't cancel each other out. If not, we need to
20419 // combine to the new one.
20421 // Replace the combinable shuffle with the combined one, updating all users
20422 // so that we re-evaluate the chain here.
20423 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20428 /// \brief Try to combine x86 target specific shuffles.
20429 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20430 TargetLowering::DAGCombinerInfo &DCI,
20431 const X86Subtarget *Subtarget) {
20433 MVT VT = N.getSimpleValueType();
20434 SmallVector<int, 4> Mask;
20436 switch (N.getOpcode()) {
20437 case X86ISD::PSHUFD:
20438 case X86ISD::PSHUFLW:
20439 case X86ISD::PSHUFHW:
20440 Mask = getPSHUFShuffleMask(N);
20441 assert(Mask.size() == 4);
20447 // Nuke no-op shuffles that show up after combining.
20448 if (isNoopShuffleMask(Mask))
20449 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20451 // Look for simplifications involving one or two shuffle instructions.
20452 SDValue V = N.getOperand(0);
20453 switch (N.getOpcode()) {
20456 case X86ISD::PSHUFLW:
20457 case X86ISD::PSHUFHW:
20458 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20460 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20461 return SDValue(); // We combined away this shuffle, so we're done.
20463 // See if this reduces to a PSHUFD which is no more expensive and can
20464 // combine with more operations. Note that it has to at least flip the
20465 // dwords as otherwise it would have been removed as a no-op.
20466 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20467 int DMask[] = {0, 1, 2, 3};
20468 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20469 DMask[DOffset + 0] = DOffset + 1;
20470 DMask[DOffset + 1] = DOffset + 0;
20471 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20472 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20473 DCI.AddToWorklist(V.getNode());
20474 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20475 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20476 DCI.AddToWorklist(V.getNode());
20477 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20480 // Look for shuffle patterns which can be implemented as a single unpack.
20481 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20482 // only works when we have a PSHUFD followed by two half-shuffles.
20483 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20484 (V.getOpcode() == X86ISD::PSHUFLW ||
20485 V.getOpcode() == X86ISD::PSHUFHW) &&
20486 V.getOpcode() != N.getOpcode() &&
20488 SDValue D = V.getOperand(0);
20489 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20490 D = D.getOperand(0);
20491 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20492 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20493 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20494 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20495 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20497 for (int i = 0; i < 4; ++i) {
20498 WordMask[i + NOffset] = Mask[i] + NOffset;
20499 WordMask[i + VOffset] = VMask[i] + VOffset;
20501 // Map the word mask through the DWord mask.
20503 for (int i = 0; i < 8; ++i)
20504 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20505 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20506 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20507 // We can replace all three shuffles with an unpack.
20508 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20509 DCI.AddToWorklist(V.getNode());
20510 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20519 case X86ISD::PSHUFD:
20520 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20529 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20531 /// We combine this directly on the abstract vector shuffle nodes so it is
20532 /// easier to generically match. We also insert dummy vector shuffle nodes for
20533 /// the operands which explicitly discard the lanes which are unused by this
20534 /// operation to try to flow through the rest of the combiner the fact that
20535 /// they're unused.
20536 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20538 EVT VT = N->getValueType(0);
20540 // We only handle target-independent shuffles.
20541 // FIXME: It would be easy and harmless to use the target shuffle mask
20542 // extraction tool to support more.
20543 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20546 auto *SVN = cast<ShuffleVectorSDNode>(N);
20547 ArrayRef<int> Mask = SVN->getMask();
20548 SDValue V1 = N->getOperand(0);
20549 SDValue V2 = N->getOperand(1);
20551 // We require the first shuffle operand to be the SUB node, and the second to
20552 // be the ADD node.
20553 // FIXME: We should support the commuted patterns.
20554 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20557 // If there are other uses of these operations we can't fold them.
20558 if (!V1->hasOneUse() || !V2->hasOneUse())
20561 // Ensure that both operations have the same operands. Note that we can
20562 // commute the FADD operands.
20563 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20564 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20565 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20568 // We're looking for blends between FADD and FSUB nodes. We insist on these
20569 // nodes being lined up in a specific expected pattern.
20570 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20571 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20572 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20575 // Only specific types are legal at this point, assert so we notice if and
20576 // when these change.
20577 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20578 VT == MVT::v4f64) &&
20579 "Unknown vector type encountered!");
20581 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20584 /// PerformShuffleCombine - Performs several different shuffle combines.
20585 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20586 TargetLowering::DAGCombinerInfo &DCI,
20587 const X86Subtarget *Subtarget) {
20589 SDValue N0 = N->getOperand(0);
20590 SDValue N1 = N->getOperand(1);
20591 EVT VT = N->getValueType(0);
20593 // Don't create instructions with illegal types after legalize types has run.
20594 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20595 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20598 // If we have legalized the vector types, look for blends of FADD and FSUB
20599 // nodes that we can fuse into an ADDSUB node.
20600 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20601 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20604 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20605 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20606 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20607 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20609 // During Type Legalization, when promoting illegal vector types,
20610 // the backend might introduce new shuffle dag nodes and bitcasts.
20612 // This code performs the following transformation:
20613 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20614 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20616 // We do this only if both the bitcast and the BINOP dag nodes have
20617 // one use. Also, perform this transformation only if the new binary
20618 // operation is legal. This is to avoid introducing dag nodes that
20619 // potentially need to be further expanded (or custom lowered) into a
20620 // less optimal sequence of dag nodes.
20621 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20622 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20623 N0.getOpcode() == ISD::BITCAST) {
20624 SDValue BC0 = N0.getOperand(0);
20625 EVT SVT = BC0.getValueType();
20626 unsigned Opcode = BC0.getOpcode();
20627 unsigned NumElts = VT.getVectorNumElements();
20629 if (BC0.hasOneUse() && SVT.isVector() &&
20630 SVT.getVectorNumElements() * 2 == NumElts &&
20631 TLI.isOperationLegal(Opcode, VT)) {
20632 bool CanFold = false;
20644 unsigned SVTNumElts = SVT.getVectorNumElements();
20645 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20646 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20647 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20648 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20649 CanFold = SVOp->getMaskElt(i) < 0;
20652 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20653 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20654 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20655 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20660 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20661 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20662 // consecutive, non-overlapping, and in the right order.
20663 SmallVector<SDValue, 16> Elts;
20664 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20665 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20667 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20671 if (isTargetShuffle(N->getOpcode())) {
20673 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20674 if (Shuffle.getNode())
20677 // Try recursively combining arbitrary sequences of x86 shuffle
20678 // instructions into higher-order shuffles. We do this after combining
20679 // specific PSHUF instruction sequences into their minimal form so that we
20680 // can evaluate how many specialized shuffle instructions are involved in
20681 // a particular chain.
20682 SmallVector<int, 1> NonceMask; // Just a placeholder.
20683 NonceMask.push_back(0);
20684 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20685 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20687 return SDValue(); // This routine will use CombineTo to replace N.
20693 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20694 /// specific shuffle of a load can be folded into a single element load.
20695 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20696 /// shuffles have been custom lowered so we need to handle those here.
20697 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20698 TargetLowering::DAGCombinerInfo &DCI) {
20699 if (DCI.isBeforeLegalizeOps())
20702 SDValue InVec = N->getOperand(0);
20703 SDValue EltNo = N->getOperand(1);
20705 if (!isa<ConstantSDNode>(EltNo))
20708 EVT OriginalVT = InVec.getValueType();
20710 if (InVec.getOpcode() == ISD::BITCAST) {
20711 // Don't duplicate a load with other uses.
20712 if (!InVec.hasOneUse())
20714 EVT BCVT = InVec.getOperand(0).getValueType();
20715 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20717 InVec = InVec.getOperand(0);
20720 EVT CurrentVT = InVec.getValueType();
20722 if (!isTargetShuffle(InVec.getOpcode()))
20725 // Don't duplicate a load with other uses.
20726 if (!InVec.hasOneUse())
20729 SmallVector<int, 16> ShuffleMask;
20731 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20732 ShuffleMask, UnaryShuffle))
20735 // Select the input vector, guarding against out of range extract vector.
20736 unsigned NumElems = CurrentVT.getVectorNumElements();
20737 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20738 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20739 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20740 : InVec.getOperand(1);
20742 // If inputs to shuffle are the same for both ops, then allow 2 uses
20743 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20744 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20746 if (LdNode.getOpcode() == ISD::BITCAST) {
20747 // Don't duplicate a load with other uses.
20748 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20751 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20752 LdNode = LdNode.getOperand(0);
20755 if (!ISD::isNormalLoad(LdNode.getNode()))
20758 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20760 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20763 EVT EltVT = N->getValueType(0);
20764 // If there's a bitcast before the shuffle, check if the load type and
20765 // alignment is valid.
20766 unsigned Align = LN0->getAlignment();
20767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20768 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20769 EltVT.getTypeForEVT(*DAG.getContext()));
20771 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20774 // All checks match so transform back to vector_shuffle so that DAG combiner
20775 // can finish the job
20778 // Create shuffle node taking into account the case that its a unary shuffle
20779 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20780 : InVec.getOperand(1);
20781 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20782 InVec.getOperand(0), Shuffle,
20784 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20789 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20790 /// special and don't usually play with other vector types, it's better to
20791 /// handle them early to be sure we emit efficient code by avoiding
20792 /// store-load conversions.
20793 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20794 if (N->getValueType(0) != MVT::x86mmx ||
20795 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
20796 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20799 SDValue V = N->getOperand(0);
20800 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20801 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20802 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20803 N->getValueType(0), V.getOperand(0));
20808 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20809 /// generation and convert it from being a bunch of shuffles and extracts
20810 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20811 /// storing the value and loading scalars back, while for x64 we should
20812 /// use 64-bit extracts and shifts.
20813 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20814 TargetLowering::DAGCombinerInfo &DCI) {
20815 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20816 if (NewOp.getNode())
20819 SDValue InputVector = N->getOperand(0);
20821 // Detect mmx to i32 conversion through a v2i32 elt extract.
20822 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20823 N->getValueType(0) == MVT::i32 &&
20824 InputVector.getValueType() == MVT::v2i32) {
20826 // The bitcast source is a direct mmx result.
20827 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20828 if (MMXSrc.getValueType() == MVT::x86mmx)
20829 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20830 N->getValueType(0),
20831 InputVector.getNode()->getOperand(0));
20833 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20834 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20835 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20836 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20837 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20838 MMXSrcOp.getValueType() == MVT::v1i64 &&
20839 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20840 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20841 N->getValueType(0),
20842 MMXSrcOp.getOperand(0));
20845 // Only operate on vectors of 4 elements, where the alternative shuffling
20846 // gets to be more expensive.
20847 if (InputVector.getValueType() != MVT::v4i32)
20850 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20851 // single use which is a sign-extend or zero-extend, and all elements are
20853 SmallVector<SDNode *, 4> Uses;
20854 unsigned ExtractedElements = 0;
20855 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20856 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20857 if (UI.getUse().getResNo() != InputVector.getResNo())
20860 SDNode *Extract = *UI;
20861 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20864 if (Extract->getValueType(0) != MVT::i32)
20866 if (!Extract->hasOneUse())
20868 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20869 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20871 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20874 // Record which element was extracted.
20875 ExtractedElements |=
20876 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20878 Uses.push_back(Extract);
20881 // If not all the elements were used, this may not be worthwhile.
20882 if (ExtractedElements != 15)
20885 // Ok, we've now decided to do the transformation.
20886 // If 64-bit shifts are legal, use the extract-shift sequence,
20887 // otherwise bounce the vector off the cache.
20888 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20890 SDLoc dl(InputVector);
20892 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20893 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20894 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20895 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20896 DAG.getConstant(0, dl, VecIdxTy));
20897 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20898 DAG.getConstant(1, dl, VecIdxTy));
20900 SDValue ShAmt = DAG.getConstant(32, dl,
20901 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20902 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20903 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20904 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20905 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20906 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20907 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20909 // Store the value to a temporary stack slot.
20910 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20911 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20912 MachinePointerInfo(), false, false, 0);
20914 EVT ElementType = InputVector.getValueType().getVectorElementType();
20915 unsigned EltSize = ElementType.getSizeInBits() / 8;
20917 // Replace each use (extract) with a load of the appropriate element.
20918 for (unsigned i = 0; i < 4; ++i) {
20919 uint64_t Offset = EltSize * i;
20920 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
20922 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20923 StackPtr, OffsetVal);
20925 // Load the scalar.
20926 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20927 ScalarAddr, MachinePointerInfo(),
20928 false, false, false, 0);
20933 // Replace the extracts
20934 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20935 UE = Uses.end(); UI != UE; ++UI) {
20936 SDNode *Extract = *UI;
20938 SDValue Idx = Extract->getOperand(1);
20939 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20940 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20943 // The replacement was made in place; don't return anything.
20947 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20948 static std::pair<unsigned, bool>
20949 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20950 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20951 if (!VT.isVector())
20952 return std::make_pair(0, false);
20954 bool NeedSplit = false;
20955 switch (VT.getSimpleVT().SimpleTy) {
20956 default: return std::make_pair(0, false);
20959 if (!Subtarget->hasVLX())
20960 return std::make_pair(0, false);
20964 if (!Subtarget->hasBWI())
20965 return std::make_pair(0, false);
20969 if (!Subtarget->hasAVX512())
20970 return std::make_pair(0, false);
20975 if (!Subtarget->hasAVX2())
20977 if (!Subtarget->hasAVX())
20978 return std::make_pair(0, false);
20983 if (!Subtarget->hasSSE2())
20984 return std::make_pair(0, false);
20987 // SSE2 has only a small subset of the operations.
20988 bool hasUnsigned = Subtarget->hasSSE41() ||
20989 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20990 bool hasSigned = Subtarget->hasSSE41() ||
20991 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20993 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20996 // Check for x CC y ? x : y.
20997 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20998 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21003 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21006 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21009 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21012 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21014 // Check for x CC y ? y : x -- a min/max with reversed arms.
21015 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21016 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21021 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21024 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21027 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21030 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21034 return std::make_pair(Opc, NeedSplit);
21038 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21039 const X86Subtarget *Subtarget) {
21041 SDValue Cond = N->getOperand(0);
21042 SDValue LHS = N->getOperand(1);
21043 SDValue RHS = N->getOperand(2);
21045 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21046 SDValue CondSrc = Cond->getOperand(0);
21047 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21048 Cond = CondSrc->getOperand(0);
21051 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21054 // A vselect where all conditions and data are constants can be optimized into
21055 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21056 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21057 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21060 unsigned MaskValue = 0;
21061 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21064 MVT VT = N->getSimpleValueType(0);
21065 unsigned NumElems = VT.getVectorNumElements();
21066 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21067 for (unsigned i = 0; i < NumElems; ++i) {
21068 // Be sure we emit undef where we can.
21069 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21070 ShuffleMask[i] = -1;
21072 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21076 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21078 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21081 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21083 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21084 TargetLowering::DAGCombinerInfo &DCI,
21085 const X86Subtarget *Subtarget) {
21087 SDValue Cond = N->getOperand(0);
21088 // Get the LHS/RHS of the select.
21089 SDValue LHS = N->getOperand(1);
21090 SDValue RHS = N->getOperand(2);
21091 EVT VT = LHS.getValueType();
21092 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21094 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21095 // instructions match the semantics of the common C idiom x<y?x:y but not
21096 // x<=y?x:y, because of how they handle negative zero (which can be
21097 // ignored in unsafe-math mode).
21098 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21099 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21100 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21101 (Subtarget->hasSSE2() ||
21102 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21103 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21105 unsigned Opcode = 0;
21106 // Check for x CC y ? x : y.
21107 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21108 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21112 // Converting this to a min would handle NaNs incorrectly, and swapping
21113 // the operands would cause it to handle comparisons between positive
21114 // and negative zero incorrectly.
21115 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21116 if (!DAG.getTarget().Options.UnsafeFPMath &&
21117 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21119 std::swap(LHS, RHS);
21121 Opcode = X86ISD::FMIN;
21124 // Converting this to a min would handle comparisons between positive
21125 // and negative zero incorrectly.
21126 if (!DAG.getTarget().Options.UnsafeFPMath &&
21127 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21129 Opcode = X86ISD::FMIN;
21132 // Converting this to a min would handle both negative zeros and NaNs
21133 // incorrectly, but we can swap the operands to fix both.
21134 std::swap(LHS, RHS);
21138 Opcode = X86ISD::FMIN;
21142 // Converting this to a max would handle comparisons between positive
21143 // and negative zero incorrectly.
21144 if (!DAG.getTarget().Options.UnsafeFPMath &&
21145 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21147 Opcode = X86ISD::FMAX;
21150 // Converting this to a max would handle NaNs incorrectly, and swapping
21151 // the operands would cause it to handle comparisons between positive
21152 // and negative zero incorrectly.
21153 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21154 if (!DAG.getTarget().Options.UnsafeFPMath &&
21155 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21157 std::swap(LHS, RHS);
21159 Opcode = X86ISD::FMAX;
21162 // Converting this to a max would handle both negative zeros and NaNs
21163 // incorrectly, but we can swap the operands to fix both.
21164 std::swap(LHS, RHS);
21168 Opcode = X86ISD::FMAX;
21171 // Check for x CC y ? y : x -- a min/max with reversed arms.
21172 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21173 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21177 // Converting this to a min would handle comparisons between positive
21178 // and negative zero incorrectly, and swapping the operands would
21179 // cause it to handle NaNs incorrectly.
21180 if (!DAG.getTarget().Options.UnsafeFPMath &&
21181 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21182 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21184 std::swap(LHS, RHS);
21186 Opcode = X86ISD::FMIN;
21189 // Converting this to a min would handle NaNs incorrectly.
21190 if (!DAG.getTarget().Options.UnsafeFPMath &&
21191 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21193 Opcode = X86ISD::FMIN;
21196 // Converting this to a min would handle both negative zeros and NaNs
21197 // incorrectly, but we can swap the operands to fix both.
21198 std::swap(LHS, RHS);
21202 Opcode = X86ISD::FMIN;
21206 // Converting this to a max would handle NaNs incorrectly.
21207 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21209 Opcode = X86ISD::FMAX;
21212 // Converting this to a max would handle comparisons between positive
21213 // and negative zero incorrectly, and swapping the operands would
21214 // cause it to handle NaNs incorrectly.
21215 if (!DAG.getTarget().Options.UnsafeFPMath &&
21216 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21217 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21219 std::swap(LHS, RHS);
21221 Opcode = X86ISD::FMAX;
21224 // Converting this to a max would handle both negative zeros and NaNs
21225 // incorrectly, but we can swap the operands to fix both.
21226 std::swap(LHS, RHS);
21230 Opcode = X86ISD::FMAX;
21236 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21239 EVT CondVT = Cond.getValueType();
21240 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21241 CondVT.getVectorElementType() == MVT::i1) {
21242 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21243 // lowering on KNL. In this case we convert it to
21244 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21245 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21246 // Since SKX these selects have a proper lowering.
21247 EVT OpVT = LHS.getValueType();
21248 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21249 (OpVT.getVectorElementType() == MVT::i8 ||
21250 OpVT.getVectorElementType() == MVT::i16) &&
21251 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21252 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21253 DCI.AddToWorklist(Cond.getNode());
21254 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21257 // If this is a select between two integer constants, try to do some
21259 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21260 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21261 // Don't do this for crazy integer types.
21262 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21263 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21264 // so that TrueC (the true value) is larger than FalseC.
21265 bool NeedsCondInvert = false;
21267 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21268 // Efficiently invertible.
21269 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21270 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21271 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21272 NeedsCondInvert = true;
21273 std::swap(TrueC, FalseC);
21276 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21277 if (FalseC->getAPIntValue() == 0 &&
21278 TrueC->getAPIntValue().isPowerOf2()) {
21279 if (NeedsCondInvert) // Invert the condition if needed.
21280 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21281 DAG.getConstant(1, DL, Cond.getValueType()));
21283 // Zero extend the condition if needed.
21284 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21286 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21287 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21288 DAG.getConstant(ShAmt, DL, MVT::i8));
21291 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21292 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21293 if (NeedsCondInvert) // Invert the condition if needed.
21294 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21295 DAG.getConstant(1, DL, Cond.getValueType()));
21297 // Zero extend the condition if needed.
21298 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21299 FalseC->getValueType(0), Cond);
21300 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21301 SDValue(FalseC, 0));
21304 // Optimize cases that will turn into an LEA instruction. This requires
21305 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21306 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21307 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21308 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21310 bool isFastMultiplier = false;
21312 switch ((unsigned char)Diff) {
21314 case 1: // result = add base, cond
21315 case 2: // result = lea base( , cond*2)
21316 case 3: // result = lea base(cond, cond*2)
21317 case 4: // result = lea base( , cond*4)
21318 case 5: // result = lea base(cond, cond*4)
21319 case 8: // result = lea base( , cond*8)
21320 case 9: // result = lea base(cond, cond*8)
21321 isFastMultiplier = true;
21326 if (isFastMultiplier) {
21327 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21328 if (NeedsCondInvert) // Invert the condition if needed.
21329 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21330 DAG.getConstant(1, DL, Cond.getValueType()));
21332 // Zero extend the condition if needed.
21333 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21335 // Scale the condition by the difference.
21337 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21338 DAG.getConstant(Diff, DL,
21339 Cond.getValueType()));
21341 // Add the base if non-zero.
21342 if (FalseC->getAPIntValue() != 0)
21343 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21344 SDValue(FalseC, 0));
21351 // Canonicalize max and min:
21352 // (x > y) ? x : y -> (x >= y) ? x : y
21353 // (x < y) ? x : y -> (x <= y) ? x : y
21354 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21355 // the need for an extra compare
21356 // against zero. e.g.
21357 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21359 // testl %edi, %edi
21361 // cmovgl %edi, %eax
21365 // cmovsl %eax, %edi
21366 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21367 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21368 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21369 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21374 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21375 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21376 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21377 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21382 // Early exit check
21383 if (!TLI.isTypeLegal(VT))
21386 // Match VSELECTs into subs with unsigned saturation.
21387 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21388 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21389 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21390 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21391 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21393 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21394 // left side invert the predicate to simplify logic below.
21396 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21398 CC = ISD::getSetCCInverse(CC, true);
21399 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21403 if (Other.getNode() && Other->getNumOperands() == 2 &&
21404 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21405 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21406 SDValue CondRHS = Cond->getOperand(1);
21408 // Look for a general sub with unsigned saturation first.
21409 // x >= y ? x-y : 0 --> subus x, y
21410 // x > y ? x-y : 0 --> subus x, y
21411 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21412 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21413 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21415 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21416 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21417 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21418 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21419 // If the RHS is a constant we have to reverse the const
21420 // canonicalization.
21421 // x > C-1 ? x+-C : 0 --> subus x, C
21422 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21423 CondRHSConst->getAPIntValue() ==
21424 (-OpRHSConst->getAPIntValue() - 1))
21425 return DAG.getNode(
21426 X86ISD::SUBUS, DL, VT, OpLHS,
21427 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21429 // Another special case: If C was a sign bit, the sub has been
21430 // canonicalized into a xor.
21431 // FIXME: Would it be better to use computeKnownBits to determine
21432 // whether it's safe to decanonicalize the xor?
21433 // x s< 0 ? x^C : 0 --> subus x, C
21434 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21435 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21436 OpRHSConst->getAPIntValue().isSignBit())
21437 // Note that we have to rebuild the RHS constant here to ensure we
21438 // don't rely on particular values of undef lanes.
21439 return DAG.getNode(
21440 X86ISD::SUBUS, DL, VT, OpLHS,
21441 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21446 // Try to match a min/max vector operation.
21447 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21448 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21449 unsigned Opc = ret.first;
21450 bool NeedSplit = ret.second;
21452 if (Opc && NeedSplit) {
21453 unsigned NumElems = VT.getVectorNumElements();
21454 // Extract the LHS vectors
21455 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21456 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21458 // Extract the RHS vectors
21459 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21460 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21462 // Create min/max for each subvector
21463 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21464 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21466 // Merge the result
21467 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21469 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21472 // Simplify vector selection if condition value type matches vselect
21474 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21475 assert(Cond.getValueType().isVector() &&
21476 "vector select expects a vector selector!");
21478 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21479 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21481 // Try invert the condition if true value is not all 1s and false value
21483 if (!TValIsAllOnes && !FValIsAllZeros &&
21484 // Check if the selector will be produced by CMPP*/PCMP*
21485 Cond.getOpcode() == ISD::SETCC &&
21486 // Check if SETCC has already been promoted
21487 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21488 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21489 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21491 if (TValIsAllZeros || FValIsAllOnes) {
21492 SDValue CC = Cond.getOperand(2);
21493 ISD::CondCode NewCC =
21494 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21495 Cond.getOperand(0).getValueType().isInteger());
21496 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21497 std::swap(LHS, RHS);
21498 TValIsAllOnes = FValIsAllOnes;
21499 FValIsAllZeros = TValIsAllZeros;
21503 if (TValIsAllOnes || FValIsAllZeros) {
21506 if (TValIsAllOnes && FValIsAllZeros)
21508 else if (TValIsAllOnes)
21509 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21510 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21511 else if (FValIsAllZeros)
21512 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21513 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21515 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21519 // We should generate an X86ISD::BLENDI from a vselect if its argument
21520 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21521 // constants. This specific pattern gets generated when we split a
21522 // selector for a 512 bit vector in a machine without AVX512 (but with
21523 // 256-bit vectors), during legalization:
21525 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21527 // Iff we find this pattern and the build_vectors are built from
21528 // constants, we translate the vselect into a shuffle_vector that we
21529 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21530 if ((N->getOpcode() == ISD::VSELECT ||
21531 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21532 !DCI.isBeforeLegalize()) {
21533 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21534 if (Shuffle.getNode())
21538 // If this is a *dynamic* select (non-constant condition) and we can match
21539 // this node with one of the variable blend instructions, restructure the
21540 // condition so that the blends can use the high bit of each element and use
21541 // SimplifyDemandedBits to simplify the condition operand.
21542 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21543 !DCI.isBeforeLegalize() &&
21544 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21545 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21547 // Don't optimize vector selects that map to mask-registers.
21551 // We can only handle the cases where VSELECT is directly legal on the
21552 // subtarget. We custom lower VSELECT nodes with constant conditions and
21553 // this makes it hard to see whether a dynamic VSELECT will correctly
21554 // lower, so we both check the operation's status and explicitly handle the
21555 // cases where a *dynamic* blend will fail even though a constant-condition
21556 // blend could be custom lowered.
21557 // FIXME: We should find a better way to handle this class of problems.
21558 // Potentially, we should combine constant-condition vselect nodes
21559 // pre-legalization into shuffles and not mark as many types as custom
21561 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21563 // FIXME: We don't support i16-element blends currently. We could and
21564 // should support them by making *all* the bits in the condition be set
21565 // rather than just the high bit and using an i8-element blend.
21566 if (VT.getScalarType() == MVT::i16)
21568 // Dynamic blending was only available from SSE4.1 onward.
21569 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21571 // Byte blends are only available in AVX2
21572 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21573 !Subtarget->hasAVX2())
21576 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21577 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21579 APInt KnownZero, KnownOne;
21580 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21581 DCI.isBeforeLegalizeOps());
21582 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21583 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21585 // If we changed the computation somewhere in the DAG, this change
21586 // will affect all users of Cond.
21587 // Make sure it is fine and update all the nodes so that we do not
21588 // use the generic VSELECT anymore. Otherwise, we may perform
21589 // wrong optimizations as we messed up with the actual expectation
21590 // for the vector boolean values.
21591 if (Cond != TLO.Old) {
21592 // Check all uses of that condition operand to check whether it will be
21593 // consumed by non-BLEND instructions, which may depend on all bits are
21595 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21597 if (I->getOpcode() != ISD::VSELECT)
21598 // TODO: Add other opcodes eventually lowered into BLEND.
21601 // Update all the users of the condition, before committing the change,
21602 // so that the VSELECT optimizations that expect the correct vector
21603 // boolean value will not be triggered.
21604 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21606 DAG.ReplaceAllUsesOfValueWith(
21608 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21609 Cond, I->getOperand(1), I->getOperand(2)));
21610 DCI.CommitTargetLoweringOpt(TLO);
21613 // At this point, only Cond is changed. Change the condition
21614 // just for N to keep the opportunity to optimize all other
21615 // users their own way.
21616 DAG.ReplaceAllUsesOfValueWith(
21618 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21619 TLO.New, N->getOperand(1), N->getOperand(2)));
21627 // Check whether a boolean test is testing a boolean value generated by
21628 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21631 // Simplify the following patterns:
21632 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21633 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21634 // to (Op EFLAGS Cond)
21636 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21637 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21638 // to (Op EFLAGS !Cond)
21640 // where Op could be BRCOND or CMOV.
21642 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21643 // Quit if not CMP and SUB with its value result used.
21644 if (Cmp.getOpcode() != X86ISD::CMP &&
21645 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21648 // Quit if not used as a boolean value.
21649 if (CC != X86::COND_E && CC != X86::COND_NE)
21652 // Check CMP operands. One of them should be 0 or 1 and the other should be
21653 // an SetCC or extended from it.
21654 SDValue Op1 = Cmp.getOperand(0);
21655 SDValue Op2 = Cmp.getOperand(1);
21658 const ConstantSDNode* C = nullptr;
21659 bool needOppositeCond = (CC == X86::COND_E);
21660 bool checkAgainstTrue = false; // Is it a comparison against 1?
21662 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21664 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21666 else // Quit if all operands are not constants.
21669 if (C->getZExtValue() == 1) {
21670 needOppositeCond = !needOppositeCond;
21671 checkAgainstTrue = true;
21672 } else if (C->getZExtValue() != 0)
21673 // Quit if the constant is neither 0 or 1.
21676 bool truncatedToBoolWithAnd = false;
21677 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21678 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21679 SetCC.getOpcode() == ISD::TRUNCATE ||
21680 SetCC.getOpcode() == ISD::AND) {
21681 if (SetCC.getOpcode() == ISD::AND) {
21683 ConstantSDNode *CS;
21684 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21685 CS->getZExtValue() == 1)
21687 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21688 CS->getZExtValue() == 1)
21692 SetCC = SetCC.getOperand(OpIdx);
21693 truncatedToBoolWithAnd = true;
21695 SetCC = SetCC.getOperand(0);
21698 switch (SetCC.getOpcode()) {
21699 case X86ISD::SETCC_CARRY:
21700 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21701 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21702 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21703 // truncated to i1 using 'and'.
21704 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21706 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21707 "Invalid use of SETCC_CARRY!");
21709 case X86ISD::SETCC:
21710 // Set the condition code or opposite one if necessary.
21711 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21712 if (needOppositeCond)
21713 CC = X86::GetOppositeBranchCondition(CC);
21714 return SetCC.getOperand(1);
21715 case X86ISD::CMOV: {
21716 // Check whether false/true value has canonical one, i.e. 0 or 1.
21717 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21718 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21719 // Quit if true value is not a constant.
21722 // Quit if false value is not a constant.
21724 SDValue Op = SetCC.getOperand(0);
21725 // Skip 'zext' or 'trunc' node.
21726 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21727 Op.getOpcode() == ISD::TRUNCATE)
21728 Op = Op.getOperand(0);
21729 // A special case for rdrand/rdseed, where 0 is set if false cond is
21731 if ((Op.getOpcode() != X86ISD::RDRAND &&
21732 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21735 // Quit if false value is not the constant 0 or 1.
21736 bool FValIsFalse = true;
21737 if (FVal && FVal->getZExtValue() != 0) {
21738 if (FVal->getZExtValue() != 1)
21740 // If FVal is 1, opposite cond is needed.
21741 needOppositeCond = !needOppositeCond;
21742 FValIsFalse = false;
21744 // Quit if TVal is not the constant opposite of FVal.
21745 if (FValIsFalse && TVal->getZExtValue() != 1)
21747 if (!FValIsFalse && TVal->getZExtValue() != 0)
21749 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21750 if (needOppositeCond)
21751 CC = X86::GetOppositeBranchCondition(CC);
21752 return SetCC.getOperand(3);
21759 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21761 /// (X86or (X86setcc) (X86setcc))
21762 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21763 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21764 X86::CondCode &CC1, SDValue &Flags,
21766 if (Cond->getOpcode() == X86ISD::CMP) {
21767 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21768 if (!CondOp1C || !CondOp1C->isNullValue())
21771 Cond = Cond->getOperand(0);
21776 SDValue SetCC0, SetCC1;
21777 switch (Cond->getOpcode()) {
21778 default: return false;
21785 SetCC0 = Cond->getOperand(0);
21786 SetCC1 = Cond->getOperand(1);
21790 // Make sure we have SETCC nodes, using the same flags value.
21791 if (SetCC0.getOpcode() != X86ISD::SETCC ||
21792 SetCC1.getOpcode() != X86ISD::SETCC ||
21793 SetCC0->getOperand(1) != SetCC1->getOperand(1))
21796 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
21797 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
21798 Flags = SetCC0->getOperand(1);
21802 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21803 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21804 TargetLowering::DAGCombinerInfo &DCI,
21805 const X86Subtarget *Subtarget) {
21808 // If the flag operand isn't dead, don't touch this CMOV.
21809 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21812 SDValue FalseOp = N->getOperand(0);
21813 SDValue TrueOp = N->getOperand(1);
21814 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21815 SDValue Cond = N->getOperand(3);
21817 if (CC == X86::COND_E || CC == X86::COND_NE) {
21818 switch (Cond.getOpcode()) {
21822 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21823 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21824 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21830 Flags = checkBoolTestSetCCCombine(Cond, CC);
21831 if (Flags.getNode() &&
21832 // Extra check as FCMOV only supports a subset of X86 cond.
21833 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21834 SDValue Ops[] = { FalseOp, TrueOp,
21835 DAG.getConstant(CC, DL, MVT::i8), Flags };
21836 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21839 // If this is a select between two integer constants, try to do some
21840 // optimizations. Note that the operands are ordered the opposite of SELECT
21842 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21843 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21844 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21845 // larger than FalseC (the false value).
21846 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21847 CC = X86::GetOppositeBranchCondition(CC);
21848 std::swap(TrueC, FalseC);
21849 std::swap(TrueOp, FalseOp);
21852 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21853 // This is efficient for any integer data type (including i8/i16) and
21855 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21856 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21857 DAG.getConstant(CC, DL, MVT::i8), Cond);
21859 // Zero extend the condition if needed.
21860 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21862 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21863 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21864 DAG.getConstant(ShAmt, DL, MVT::i8));
21865 if (N->getNumValues() == 2) // Dead flag value?
21866 return DCI.CombineTo(N, Cond, SDValue());
21870 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21871 // for any integer data type, including i8/i16.
21872 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21873 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21874 DAG.getConstant(CC, DL, MVT::i8), Cond);
21876 // Zero extend the condition if needed.
21877 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21878 FalseC->getValueType(0), Cond);
21879 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21880 SDValue(FalseC, 0));
21882 if (N->getNumValues() == 2) // Dead flag value?
21883 return DCI.CombineTo(N, Cond, SDValue());
21887 // Optimize cases that will turn into an LEA instruction. This requires
21888 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21889 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21890 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21891 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21893 bool isFastMultiplier = false;
21895 switch ((unsigned char)Diff) {
21897 case 1: // result = add base, cond
21898 case 2: // result = lea base( , cond*2)
21899 case 3: // result = lea base(cond, cond*2)
21900 case 4: // result = lea base( , cond*4)
21901 case 5: // result = lea base(cond, cond*4)
21902 case 8: // result = lea base( , cond*8)
21903 case 9: // result = lea base(cond, cond*8)
21904 isFastMultiplier = true;
21909 if (isFastMultiplier) {
21910 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21911 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21912 DAG.getConstant(CC, DL, MVT::i8), Cond);
21913 // Zero extend the condition if needed.
21914 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21916 // Scale the condition by the difference.
21918 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21919 DAG.getConstant(Diff, DL, Cond.getValueType()));
21921 // Add the base if non-zero.
21922 if (FalseC->getAPIntValue() != 0)
21923 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21924 SDValue(FalseC, 0));
21925 if (N->getNumValues() == 2) // Dead flag value?
21926 return DCI.CombineTo(N, Cond, SDValue());
21933 // Handle these cases:
21934 // (select (x != c), e, c) -> select (x != c), e, x),
21935 // (select (x == c), c, e) -> select (x == c), x, e)
21936 // where the c is an integer constant, and the "select" is the combination
21937 // of CMOV and CMP.
21939 // The rationale for this change is that the conditional-move from a constant
21940 // needs two instructions, however, conditional-move from a register needs
21941 // only one instruction.
21943 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21944 // some instruction-combining opportunities. This opt needs to be
21945 // postponed as late as possible.
21947 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21948 // the DCI.xxxx conditions are provided to postpone the optimization as
21949 // late as possible.
21951 ConstantSDNode *CmpAgainst = nullptr;
21952 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21953 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21954 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21956 if (CC == X86::COND_NE &&
21957 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21958 CC = X86::GetOppositeBranchCondition(CC);
21959 std::swap(TrueOp, FalseOp);
21962 if (CC == X86::COND_E &&
21963 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21964 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21965 DAG.getConstant(CC, DL, MVT::i8), Cond };
21966 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21971 // Fold and/or of setcc's to double CMOV:
21972 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
21973 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
21975 // This combine lets us generate:
21976 // cmovcc1 (jcc1 if we don't have CMOV)
21982 // cmovne (jne if we don't have CMOV)
21983 // When we can't use the CMOV instruction, it might increase branch
21985 // When we can use CMOV, or when there is no mispredict, this improves
21986 // throughput and reduces register pressure.
21988 if (CC == X86::COND_NE) {
21990 X86::CondCode CC0, CC1;
21992 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
21994 std::swap(FalseOp, TrueOp);
21995 CC0 = X86::GetOppositeBranchCondition(CC0);
21996 CC1 = X86::GetOppositeBranchCondition(CC1);
21999 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22001 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22002 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22003 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22004 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22012 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22013 const X86Subtarget *Subtarget) {
22014 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22016 default: return SDValue();
22017 // SSE/AVX/AVX2 blend intrinsics.
22018 case Intrinsic::x86_avx2_pblendvb:
22019 // Don't try to simplify this intrinsic if we don't have AVX2.
22020 if (!Subtarget->hasAVX2())
22023 case Intrinsic::x86_avx_blendv_pd_256:
22024 case Intrinsic::x86_avx_blendv_ps_256:
22025 // Don't try to simplify this intrinsic if we don't have AVX.
22026 if (!Subtarget->hasAVX())
22029 case Intrinsic::x86_sse41_blendvps:
22030 case Intrinsic::x86_sse41_blendvpd:
22031 case Intrinsic::x86_sse41_pblendvb: {
22032 SDValue Op0 = N->getOperand(1);
22033 SDValue Op1 = N->getOperand(2);
22034 SDValue Mask = N->getOperand(3);
22036 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22037 if (!Subtarget->hasSSE41())
22040 // fold (blend A, A, Mask) -> A
22043 // fold (blend A, B, allZeros) -> A
22044 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22046 // fold (blend A, B, allOnes) -> B
22047 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22050 // Simplify the case where the mask is a constant i32 value.
22051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22052 if (C->isNullValue())
22054 if (C->isAllOnesValue())
22061 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22062 case Intrinsic::x86_sse2_psrai_w:
22063 case Intrinsic::x86_sse2_psrai_d:
22064 case Intrinsic::x86_avx2_psrai_w:
22065 case Intrinsic::x86_avx2_psrai_d:
22066 case Intrinsic::x86_sse2_psra_w:
22067 case Intrinsic::x86_sse2_psra_d:
22068 case Intrinsic::x86_avx2_psra_w:
22069 case Intrinsic::x86_avx2_psra_d: {
22070 SDValue Op0 = N->getOperand(1);
22071 SDValue Op1 = N->getOperand(2);
22072 EVT VT = Op0.getValueType();
22073 assert(VT.isVector() && "Expected a vector type!");
22075 if (isa<BuildVectorSDNode>(Op1))
22076 Op1 = Op1.getOperand(0);
22078 if (!isa<ConstantSDNode>(Op1))
22081 EVT SVT = VT.getVectorElementType();
22082 unsigned SVTBits = SVT.getSizeInBits();
22084 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22085 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22086 uint64_t ShAmt = C.getZExtValue();
22088 // Don't try to convert this shift into a ISD::SRA if the shift
22089 // count is bigger than or equal to the element size.
22090 if (ShAmt >= SVTBits)
22093 // Trivial case: if the shift count is zero, then fold this
22094 // into the first operand.
22098 // Replace this packed shift intrinsic with a target independent
22101 SDValue Splat = DAG.getConstant(C, DL, VT);
22102 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22107 /// PerformMulCombine - Optimize a single multiply with constant into two
22108 /// in order to implement it with two cheaper instructions, e.g.
22109 /// LEA + SHL, LEA + LEA.
22110 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22111 TargetLowering::DAGCombinerInfo &DCI) {
22112 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22115 EVT VT = N->getValueType(0);
22116 if (VT != MVT::i64 && VT != MVT::i32)
22119 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22122 uint64_t MulAmt = C->getZExtValue();
22123 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22126 uint64_t MulAmt1 = 0;
22127 uint64_t MulAmt2 = 0;
22128 if ((MulAmt % 9) == 0) {
22130 MulAmt2 = MulAmt / 9;
22131 } else if ((MulAmt % 5) == 0) {
22133 MulAmt2 = MulAmt / 5;
22134 } else if ((MulAmt % 3) == 0) {
22136 MulAmt2 = MulAmt / 3;
22139 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22142 if (isPowerOf2_64(MulAmt2) &&
22143 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22144 // If second multiplifer is pow2, issue it first. We want the multiply by
22145 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22147 std::swap(MulAmt1, MulAmt2);
22150 if (isPowerOf2_64(MulAmt1))
22151 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22152 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22154 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22155 DAG.getConstant(MulAmt1, DL, VT));
22157 if (isPowerOf2_64(MulAmt2))
22158 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22159 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22161 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22162 DAG.getConstant(MulAmt2, DL, VT));
22164 // Do not add new nodes to DAG combiner worklist.
22165 DCI.CombineTo(N, NewMul, false);
22170 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22171 SDValue N0 = N->getOperand(0);
22172 SDValue N1 = N->getOperand(1);
22173 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22174 EVT VT = N0.getValueType();
22176 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22177 // since the result of setcc_c is all zero's or all ones.
22178 if (VT.isInteger() && !VT.isVector() &&
22179 N1C && N0.getOpcode() == ISD::AND &&
22180 N0.getOperand(1).getOpcode() == ISD::Constant) {
22181 SDValue N00 = N0.getOperand(0);
22182 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22183 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22184 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22185 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22186 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22187 APInt ShAmt = N1C->getAPIntValue();
22188 Mask = Mask.shl(ShAmt);
22191 return DAG.getNode(ISD::AND, DL, VT,
22192 N00, DAG.getConstant(Mask, DL, VT));
22197 // Hardware support for vector shifts is sparse which makes us scalarize the
22198 // vector operations in many cases. Also, on sandybridge ADD is faster than
22200 // (shl V, 1) -> add V,V
22201 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22202 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22203 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22204 // We shift all of the values by one. In many cases we do not have
22205 // hardware support for this operation. This is better expressed as an ADD
22207 if (N1SplatC->getZExtValue() == 1)
22208 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22214 /// \brief Returns a vector of 0s if the node in input is a vector logical
22215 /// shift by a constant amount which is known to be bigger than or equal
22216 /// to the vector element size in bits.
22217 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22218 const X86Subtarget *Subtarget) {
22219 EVT VT = N->getValueType(0);
22221 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22222 (!Subtarget->hasInt256() ||
22223 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22226 SDValue Amt = N->getOperand(1);
22228 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22229 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22230 APInt ShiftAmt = AmtSplat->getAPIntValue();
22231 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22233 // SSE2/AVX2 logical shifts always return a vector of 0s
22234 // if the shift amount is bigger than or equal to
22235 // the element size. The constant shift amount will be
22236 // encoded as a 8-bit immediate.
22237 if (ShiftAmt.trunc(8).uge(MaxAmount))
22238 return getZeroVector(VT, Subtarget, DAG, DL);
22244 /// PerformShiftCombine - Combine shifts.
22245 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22246 TargetLowering::DAGCombinerInfo &DCI,
22247 const X86Subtarget *Subtarget) {
22248 if (N->getOpcode() == ISD::SHL) {
22249 SDValue V = PerformSHLCombine(N, DAG);
22250 if (V.getNode()) return V;
22253 if (N->getOpcode() != ISD::SRA) {
22254 // Try to fold this logical shift into a zero vector.
22255 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22256 if (V.getNode()) return V;
22262 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22263 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22264 // and friends. Likewise for OR -> CMPNEQSS.
22265 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22266 TargetLowering::DAGCombinerInfo &DCI,
22267 const X86Subtarget *Subtarget) {
22270 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22271 // we're requiring SSE2 for both.
22272 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22273 SDValue N0 = N->getOperand(0);
22274 SDValue N1 = N->getOperand(1);
22275 SDValue CMP0 = N0->getOperand(1);
22276 SDValue CMP1 = N1->getOperand(1);
22279 // The SETCCs should both refer to the same CMP.
22280 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22283 SDValue CMP00 = CMP0->getOperand(0);
22284 SDValue CMP01 = CMP0->getOperand(1);
22285 EVT VT = CMP00.getValueType();
22287 if (VT == MVT::f32 || VT == MVT::f64) {
22288 bool ExpectingFlags = false;
22289 // Check for any users that want flags:
22290 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22291 !ExpectingFlags && UI != UE; ++UI)
22292 switch (UI->getOpcode()) {
22297 ExpectingFlags = true;
22299 case ISD::CopyToReg:
22300 case ISD::SIGN_EXTEND:
22301 case ISD::ZERO_EXTEND:
22302 case ISD::ANY_EXTEND:
22306 if (!ExpectingFlags) {
22307 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22308 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22310 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22311 X86::CondCode tmp = cc0;
22316 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22317 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22318 // FIXME: need symbolic constants for these magic numbers.
22319 // See X86ATTInstPrinter.cpp:printSSECC().
22320 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22321 if (Subtarget->hasAVX512()) {
22322 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22324 DAG.getConstant(x86cc, DL, MVT::i8));
22325 if (N->getValueType(0) != MVT::i1)
22326 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22330 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22331 CMP00.getValueType(), CMP00, CMP01,
22332 DAG.getConstant(x86cc, DL,
22335 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22336 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22338 if (is64BitFP && !Subtarget->is64Bit()) {
22339 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22340 // 64-bit integer, since that's not a legal type. Since
22341 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22342 // bits, but can do this little dance to extract the lowest 32 bits
22343 // and work with those going forward.
22344 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22346 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22348 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22349 Vector32, DAG.getIntPtrConstant(0, DL));
22353 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
22355 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22356 DAG.getConstant(1, DL, IntVT));
22357 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22359 return OneBitOfTruth;
22367 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22368 /// so it can be folded inside ANDNP.
22369 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22370 EVT VT = N->getValueType(0);
22372 // Match direct AllOnes for 128 and 256-bit vectors
22373 if (ISD::isBuildVectorAllOnes(N))
22376 // Look through a bit convert.
22377 if (N->getOpcode() == ISD::BITCAST)
22378 N = N->getOperand(0).getNode();
22380 // Sometimes the operand may come from a insert_subvector building a 256-bit
22382 if (VT.is256BitVector() &&
22383 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22384 SDValue V1 = N->getOperand(0);
22385 SDValue V2 = N->getOperand(1);
22387 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22388 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22389 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22390 ISD::isBuildVectorAllOnes(V2.getNode()))
22397 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22398 // register. In most cases we actually compare or select YMM-sized registers
22399 // and mixing the two types creates horrible code. This method optimizes
22400 // some of the transition sequences.
22401 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22402 TargetLowering::DAGCombinerInfo &DCI,
22403 const X86Subtarget *Subtarget) {
22404 EVT VT = N->getValueType(0);
22405 if (!VT.is256BitVector())
22408 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22409 N->getOpcode() == ISD::ZERO_EXTEND ||
22410 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22412 SDValue Narrow = N->getOperand(0);
22413 EVT NarrowVT = Narrow->getValueType(0);
22414 if (!NarrowVT.is128BitVector())
22417 if (Narrow->getOpcode() != ISD::XOR &&
22418 Narrow->getOpcode() != ISD::AND &&
22419 Narrow->getOpcode() != ISD::OR)
22422 SDValue N0 = Narrow->getOperand(0);
22423 SDValue N1 = Narrow->getOperand(1);
22426 // The Left side has to be a trunc.
22427 if (N0.getOpcode() != ISD::TRUNCATE)
22430 // The type of the truncated inputs.
22431 EVT WideVT = N0->getOperand(0)->getValueType(0);
22435 // The right side has to be a 'trunc' or a constant vector.
22436 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22437 ConstantSDNode *RHSConstSplat = nullptr;
22438 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22439 RHSConstSplat = RHSBV->getConstantSplatNode();
22440 if (!RHSTrunc && !RHSConstSplat)
22443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22445 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22448 // Set N0 and N1 to hold the inputs to the new wide operation.
22449 N0 = N0->getOperand(0);
22450 if (RHSConstSplat) {
22451 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22452 SDValue(RHSConstSplat, 0));
22453 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22454 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22455 } else if (RHSTrunc) {
22456 N1 = N1->getOperand(0);
22459 // Generate the wide operation.
22460 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22461 unsigned Opcode = N->getOpcode();
22463 case ISD::ANY_EXTEND:
22465 case ISD::ZERO_EXTEND: {
22466 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22467 APInt Mask = APInt::getAllOnesValue(InBits);
22468 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22469 return DAG.getNode(ISD::AND, DL, VT,
22470 Op, DAG.getConstant(Mask, DL, VT));
22472 case ISD::SIGN_EXTEND:
22473 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22474 Op, DAG.getValueType(NarrowVT));
22476 llvm_unreachable("Unexpected opcode");
22480 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22481 TargetLowering::DAGCombinerInfo &DCI,
22482 const X86Subtarget *Subtarget) {
22483 SDValue N0 = N->getOperand(0);
22484 SDValue N1 = N->getOperand(1);
22487 // A vector zext_in_reg may be represented as a shuffle,
22488 // feeding into a bitcast (this represents anyext) feeding into
22489 // an and with a mask.
22490 // We'd like to try to combine that into a shuffle with zero
22491 // plus a bitcast, removing the and.
22492 if (N0.getOpcode() != ISD::BITCAST ||
22493 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22496 // The other side of the AND should be a splat of 2^C, where C
22497 // is the number of bits in the source type.
22498 if (N1.getOpcode() == ISD::BITCAST)
22499 N1 = N1.getOperand(0);
22500 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22502 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22504 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22505 EVT SrcType = Shuffle->getValueType(0);
22507 // We expect a single-source shuffle
22508 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22511 unsigned SrcSize = SrcType.getScalarSizeInBits();
22513 APInt SplatValue, SplatUndef;
22514 unsigned SplatBitSize;
22516 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22517 SplatBitSize, HasAnyUndefs))
22520 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22521 // Make sure the splat matches the mask we expect
22522 if (SplatBitSize > ResSize ||
22523 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22526 // Make sure the input and output size make sense
22527 if (SrcSize >= ResSize || ResSize % SrcSize)
22530 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22531 // The number of u's between each two values depends on the ratio between
22532 // the source and dest type.
22533 unsigned ZextRatio = ResSize / SrcSize;
22534 bool IsZext = true;
22535 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22536 if (i % ZextRatio) {
22537 if (Shuffle->getMaskElt(i) > 0) {
22543 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22544 // Expected element number
22554 // Ok, perform the transformation - replace the shuffle with
22555 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22556 // (instead of undef) where the k elements come from the zero vector.
22557 SmallVector<int, 8> Mask;
22558 unsigned NumElems = SrcType.getVectorNumElements();
22559 for (unsigned i = 0; i < NumElems; ++i)
22561 Mask.push_back(NumElems);
22563 Mask.push_back(i / ZextRatio);
22565 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22566 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
22567 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22570 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22571 TargetLowering::DAGCombinerInfo &DCI,
22572 const X86Subtarget *Subtarget) {
22573 if (DCI.isBeforeLegalizeOps())
22576 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22579 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22582 EVT VT = N->getValueType(0);
22583 SDValue N0 = N->getOperand(0);
22584 SDValue N1 = N->getOperand(1);
22587 // Create BEXTR instructions
22588 // BEXTR is ((X >> imm) & (2**size-1))
22589 if (VT == MVT::i32 || VT == MVT::i64) {
22590 // Check for BEXTR.
22591 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22592 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22593 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22594 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22595 if (MaskNode && ShiftNode) {
22596 uint64_t Mask = MaskNode->getZExtValue();
22597 uint64_t Shift = ShiftNode->getZExtValue();
22598 if (isMask_64(Mask)) {
22599 uint64_t MaskSize = countPopulation(Mask);
22600 if (Shift + MaskSize <= VT.getSizeInBits())
22601 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22602 DAG.getConstant(Shift | (MaskSize << 8), DL,
22611 // Want to form ANDNP nodes:
22612 // 1) In the hopes of then easily combining them with OR and AND nodes
22613 // to form PBLEND/PSIGN.
22614 // 2) To match ANDN packed intrinsics
22615 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22618 // Check LHS for vnot
22619 if (N0.getOpcode() == ISD::XOR &&
22620 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22621 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22622 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22624 // Check RHS for vnot
22625 if (N1.getOpcode() == ISD::XOR &&
22626 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22627 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22628 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22633 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22634 TargetLowering::DAGCombinerInfo &DCI,
22635 const X86Subtarget *Subtarget) {
22636 if (DCI.isBeforeLegalizeOps())
22639 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22643 SDValue N0 = N->getOperand(0);
22644 SDValue N1 = N->getOperand(1);
22645 EVT VT = N->getValueType(0);
22647 // look for psign/blend
22648 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22649 if (!Subtarget->hasSSSE3() ||
22650 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22653 // Canonicalize pandn to RHS
22654 if (N0.getOpcode() == X86ISD::ANDNP)
22656 // or (and (m, y), (pandn m, x))
22657 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22658 SDValue Mask = N1.getOperand(0);
22659 SDValue X = N1.getOperand(1);
22661 if (N0.getOperand(0) == Mask)
22662 Y = N0.getOperand(1);
22663 if (N0.getOperand(1) == Mask)
22664 Y = N0.getOperand(0);
22666 // Check to see if the mask appeared in both the AND and ANDNP and
22670 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22671 // Look through mask bitcast.
22672 if (Mask.getOpcode() == ISD::BITCAST)
22673 Mask = Mask.getOperand(0);
22674 if (X.getOpcode() == ISD::BITCAST)
22675 X = X.getOperand(0);
22676 if (Y.getOpcode() == ISD::BITCAST)
22677 Y = Y.getOperand(0);
22679 EVT MaskVT = Mask.getValueType();
22681 // Validate that the Mask operand is a vector sra node.
22682 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22683 // there is no psrai.b
22684 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22685 unsigned SraAmt = ~0;
22686 if (Mask.getOpcode() == ISD::SRA) {
22687 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22688 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22689 SraAmt = AmtConst->getZExtValue();
22690 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22691 SDValue SraC = Mask.getOperand(1);
22692 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22694 if ((SraAmt + 1) != EltBits)
22699 // Now we know we at least have a plendvb with the mask val. See if
22700 // we can form a psignb/w/d.
22701 // psign = x.type == y.type == mask.type && y = sub(0, x);
22702 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22703 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22704 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22705 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22706 "Unsupported VT for PSIGN");
22707 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22708 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22710 // PBLENDVB only available on SSE 4.1
22711 if (!Subtarget->hasSSE41())
22714 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22716 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22717 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22718 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22719 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22720 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22724 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22727 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22728 MachineFunction &MF = DAG.getMachineFunction();
22730 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22732 // SHLD/SHRD instructions have lower register pressure, but on some
22733 // platforms they have higher latency than the equivalent
22734 // series of shifts/or that would otherwise be generated.
22735 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22736 // have higher latencies and we are not optimizing for size.
22737 if (!OptForSize && Subtarget->isSHLDSlow())
22740 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22742 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22744 if (!N0.hasOneUse() || !N1.hasOneUse())
22747 SDValue ShAmt0 = N0.getOperand(1);
22748 if (ShAmt0.getValueType() != MVT::i8)
22750 SDValue ShAmt1 = N1.getOperand(1);
22751 if (ShAmt1.getValueType() != MVT::i8)
22753 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22754 ShAmt0 = ShAmt0.getOperand(0);
22755 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22756 ShAmt1 = ShAmt1.getOperand(0);
22759 unsigned Opc = X86ISD::SHLD;
22760 SDValue Op0 = N0.getOperand(0);
22761 SDValue Op1 = N1.getOperand(0);
22762 if (ShAmt0.getOpcode() == ISD::SUB) {
22763 Opc = X86ISD::SHRD;
22764 std::swap(Op0, Op1);
22765 std::swap(ShAmt0, ShAmt1);
22768 unsigned Bits = VT.getSizeInBits();
22769 if (ShAmt1.getOpcode() == ISD::SUB) {
22770 SDValue Sum = ShAmt1.getOperand(0);
22771 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22772 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22773 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22774 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22775 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22776 return DAG.getNode(Opc, DL, VT,
22778 DAG.getNode(ISD::TRUNCATE, DL,
22781 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22782 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22784 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22785 return DAG.getNode(Opc, DL, VT,
22786 N0.getOperand(0), N1.getOperand(0),
22787 DAG.getNode(ISD::TRUNCATE, DL,
22794 // Generate NEG and CMOV for integer abs.
22795 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22796 EVT VT = N->getValueType(0);
22798 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22799 // 8-bit integer abs to NEG and CMOV.
22800 if (VT.isInteger() && VT.getSizeInBits() == 8)
22803 SDValue N0 = N->getOperand(0);
22804 SDValue N1 = N->getOperand(1);
22807 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22808 // and change it to SUB and CMOV.
22809 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22810 N0.getOpcode() == ISD::ADD &&
22811 N0.getOperand(1) == N1 &&
22812 N1.getOpcode() == ISD::SRA &&
22813 N1.getOperand(0) == N0.getOperand(0))
22814 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22815 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22816 // Generate SUB & CMOV.
22817 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22818 DAG.getConstant(0, DL, VT), N0.getOperand(0));
22820 SDValue Ops[] = { N0.getOperand(0), Neg,
22821 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
22822 SDValue(Neg.getNode(), 1) };
22823 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22828 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22829 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22830 TargetLowering::DAGCombinerInfo &DCI,
22831 const X86Subtarget *Subtarget) {
22832 if (DCI.isBeforeLegalizeOps())
22835 if (Subtarget->hasCMov()) {
22836 SDValue RV = performIntegerAbsCombine(N, DAG);
22844 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22845 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22846 TargetLowering::DAGCombinerInfo &DCI,
22847 const X86Subtarget *Subtarget) {
22848 LoadSDNode *Ld = cast<LoadSDNode>(N);
22849 EVT RegVT = Ld->getValueType(0);
22850 EVT MemVT = Ld->getMemoryVT();
22852 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22854 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
22855 // into two 16-byte operations.
22856 ISD::LoadExtType Ext = Ld->getExtensionType();
22857 unsigned Alignment = Ld->getAlignment();
22858 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22859 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22860 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22861 unsigned NumElems = RegVT.getVectorNumElements();
22865 SDValue Ptr = Ld->getBasePtr();
22866 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
22868 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22870 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22871 Ld->getPointerInfo(), Ld->isVolatile(),
22872 Ld->isNonTemporal(), Ld->isInvariant(),
22874 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22875 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22876 Ld->getPointerInfo(), Ld->isVolatile(),
22877 Ld->isNonTemporal(), Ld->isInvariant(),
22878 std::min(16U, Alignment));
22879 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22881 Load2.getValue(1));
22883 SDValue NewVec = DAG.getUNDEF(RegVT);
22884 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22885 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22886 return DCI.CombineTo(N, NewVec, TF, true);
22892 /// PerformMLOADCombine - Resolve extending loads
22893 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22894 TargetLowering::DAGCombinerInfo &DCI,
22895 const X86Subtarget *Subtarget) {
22896 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22897 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22900 EVT VT = Mld->getValueType(0);
22901 unsigned NumElems = VT.getVectorNumElements();
22902 EVT LdVT = Mld->getMemoryVT();
22905 assert(LdVT != VT && "Cannot extend to the same type");
22906 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22907 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22908 // From, To sizes and ElemCount must be pow of two
22909 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22910 "Unexpected size for extending masked load");
22912 unsigned SizeRatio = ToSz / FromSz;
22913 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22915 // Create a type on which we perform the shuffle
22916 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22917 LdVT.getScalarType(), NumElems*SizeRatio);
22918 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22920 // Convert Src0 value
22921 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22922 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22923 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22924 for (unsigned i = 0; i != NumElems; ++i)
22925 ShuffleVec[i] = i * SizeRatio;
22927 // Can't shuffle using an illegal type.
22928 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22929 && "WideVecVT should be legal");
22930 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22931 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22933 // Prepare the new mask
22935 SDValue Mask = Mld->getMask();
22936 if (Mask.getValueType() == VT) {
22937 // Mask and original value have the same type
22938 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22939 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22940 for (unsigned i = 0; i != NumElems; ++i)
22941 ShuffleVec[i] = i * SizeRatio;
22942 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22943 ShuffleVec[i] = NumElems*SizeRatio;
22944 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22945 DAG.getConstant(0, dl, WideVecVT),
22949 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22950 unsigned WidenNumElts = NumElems*SizeRatio;
22951 unsigned MaskNumElts = VT.getVectorNumElements();
22952 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22955 unsigned NumConcat = WidenNumElts / MaskNumElts;
22956 SmallVector<SDValue, 16> Ops(NumConcat);
22957 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
22959 for (unsigned i = 1; i != NumConcat; ++i)
22962 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22965 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22966 Mld->getBasePtr(), NewMask, WideSrc0,
22967 Mld->getMemoryVT(), Mld->getMemOperand(),
22969 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22970 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22973 /// PerformMSTORECombine - Resolve truncating stores
22974 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22975 const X86Subtarget *Subtarget) {
22976 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22977 if (!Mst->isTruncatingStore())
22980 EVT VT = Mst->getValue().getValueType();
22981 unsigned NumElems = VT.getVectorNumElements();
22982 EVT StVT = Mst->getMemoryVT();
22985 assert(StVT != VT && "Cannot truncate to the same type");
22986 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22987 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22989 // From, To sizes and ElemCount must be pow of two
22990 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22991 "Unexpected size for truncating masked store");
22992 // We are going to use the original vector elt for storing.
22993 // Accumulated smaller vector elements must be a multiple of the store size.
22994 assert (((NumElems * FromSz) % ToSz) == 0 &&
22995 "Unexpected ratio for truncating masked store");
22997 unsigned SizeRatio = FromSz / ToSz;
22998 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23000 // Create a type on which we perform the shuffle
23001 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23002 StVT.getScalarType(), NumElems*SizeRatio);
23004 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23006 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
23007 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23008 for (unsigned i = 0; i != NumElems; ++i)
23009 ShuffleVec[i] = i * SizeRatio;
23011 // Can't shuffle using an illegal type.
23012 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23013 && "WideVecVT should be legal");
23015 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23016 DAG.getUNDEF(WideVecVT),
23020 SDValue Mask = Mst->getMask();
23021 if (Mask.getValueType() == VT) {
23022 // Mask and original value have the same type
23023 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
23024 for (unsigned i = 0; i != NumElems; ++i)
23025 ShuffleVec[i] = i * SizeRatio;
23026 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23027 ShuffleVec[i] = NumElems*SizeRatio;
23028 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23029 DAG.getConstant(0, dl, WideVecVT),
23033 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23034 unsigned WidenNumElts = NumElems*SizeRatio;
23035 unsigned MaskNumElts = VT.getVectorNumElements();
23036 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23039 unsigned NumConcat = WidenNumElts / MaskNumElts;
23040 SmallVector<SDValue, 16> Ops(NumConcat);
23041 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23043 for (unsigned i = 1; i != NumConcat; ++i)
23046 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23049 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23050 NewMask, StVT, Mst->getMemOperand(), false);
23052 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23053 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23054 const X86Subtarget *Subtarget) {
23055 StoreSDNode *St = cast<StoreSDNode>(N);
23056 EVT VT = St->getValue().getValueType();
23057 EVT StVT = St->getMemoryVT();
23059 SDValue StoredVal = St->getOperand(1);
23060 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23062 // If we are saving a concatenation of two XMM registers and 32-byte stores
23063 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23064 unsigned Alignment = St->getAlignment();
23065 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23066 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23067 StVT == VT && !IsAligned) {
23068 unsigned NumElems = VT.getVectorNumElements();
23072 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23073 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23075 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23076 SDValue Ptr0 = St->getBasePtr();
23077 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23079 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23080 St->getPointerInfo(), St->isVolatile(),
23081 St->isNonTemporal(), Alignment);
23082 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23083 St->getPointerInfo(), St->isVolatile(),
23084 St->isNonTemporal(),
23085 std::min(16U, Alignment));
23086 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23089 // Optimize trunc store (of multiple scalars) to shuffle and store.
23090 // First, pack all of the elements in one place. Next, store to memory
23091 // in fewer chunks.
23092 if (St->isTruncatingStore() && VT.isVector()) {
23093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23094 unsigned NumElems = VT.getVectorNumElements();
23095 assert(StVT != VT && "Cannot truncate to the same type");
23096 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23097 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23099 // From, To sizes and ElemCount must be pow of two
23100 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23101 // We are going to use the original vector elt for storing.
23102 // Accumulated smaller vector elements must be a multiple of the store size.
23103 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23105 unsigned SizeRatio = FromSz / ToSz;
23107 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23109 // Create a type on which we perform the shuffle
23110 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23111 StVT.getScalarType(), NumElems*SizeRatio);
23113 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23115 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23116 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23117 for (unsigned i = 0; i != NumElems; ++i)
23118 ShuffleVec[i] = i * SizeRatio;
23120 // Can't shuffle using an illegal type.
23121 if (!TLI.isTypeLegal(WideVecVT))
23124 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23125 DAG.getUNDEF(WideVecVT),
23127 // At this point all of the data is stored at the bottom of the
23128 // register. We now need to save it to mem.
23130 // Find the largest store unit
23131 MVT StoreType = MVT::i8;
23132 for (MVT Tp : MVT::integer_valuetypes()) {
23133 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23137 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23138 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23139 (64 <= NumElems * ToSz))
23140 StoreType = MVT::f64;
23142 // Bitcast the original vector into a vector of store-size units
23143 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23144 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23145 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23146 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23147 SmallVector<SDValue, 8> Chains;
23148 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23149 TLI.getPointerTy());
23150 SDValue Ptr = St->getBasePtr();
23152 // Perform one or more big stores into memory.
23153 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23154 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23155 StoreType, ShuffWide,
23156 DAG.getIntPtrConstant(i, dl));
23157 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23158 St->getPointerInfo(), St->isVolatile(),
23159 St->isNonTemporal(), St->getAlignment());
23160 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23161 Chains.push_back(Ch);
23164 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23167 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23168 // the FP state in cases where an emms may be missing.
23169 // A preferable solution to the general problem is to figure out the right
23170 // places to insert EMMS. This qualifies as a quick hack.
23172 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23173 if (VT.getSizeInBits() != 64)
23176 const Function *F = DAG.getMachineFunction().getFunction();
23177 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23179 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23180 if ((VT.isVector() ||
23181 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23182 isa<LoadSDNode>(St->getValue()) &&
23183 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23184 St->getChain().hasOneUse() && !St->isVolatile()) {
23185 SDNode* LdVal = St->getValue().getNode();
23186 LoadSDNode *Ld = nullptr;
23187 int TokenFactorIndex = -1;
23188 SmallVector<SDValue, 8> Ops;
23189 SDNode* ChainVal = St->getChain().getNode();
23190 // Must be a store of a load. We currently handle two cases: the load
23191 // is a direct child, and it's under an intervening TokenFactor. It is
23192 // possible to dig deeper under nested TokenFactors.
23193 if (ChainVal == LdVal)
23194 Ld = cast<LoadSDNode>(St->getChain());
23195 else if (St->getValue().hasOneUse() &&
23196 ChainVal->getOpcode() == ISD::TokenFactor) {
23197 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23198 if (ChainVal->getOperand(i).getNode() == LdVal) {
23199 TokenFactorIndex = i;
23200 Ld = cast<LoadSDNode>(St->getValue());
23202 Ops.push_back(ChainVal->getOperand(i));
23206 if (!Ld || !ISD::isNormalLoad(Ld))
23209 // If this is not the MMX case, i.e. we are just turning i64 load/store
23210 // into f64 load/store, avoid the transformation if there are multiple
23211 // uses of the loaded value.
23212 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23217 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23218 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23220 if (Subtarget->is64Bit() || F64IsLegal) {
23221 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23222 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23223 Ld->getPointerInfo(), Ld->isVolatile(),
23224 Ld->isNonTemporal(), Ld->isInvariant(),
23225 Ld->getAlignment());
23226 SDValue NewChain = NewLd.getValue(1);
23227 if (TokenFactorIndex != -1) {
23228 Ops.push_back(NewChain);
23229 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23231 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23232 St->getPointerInfo(),
23233 St->isVolatile(), St->isNonTemporal(),
23234 St->getAlignment());
23237 // Otherwise, lower to two pairs of 32-bit loads / stores.
23238 SDValue LoAddr = Ld->getBasePtr();
23239 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23240 DAG.getConstant(4, LdDL, MVT::i32));
23242 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23243 Ld->getPointerInfo(),
23244 Ld->isVolatile(), Ld->isNonTemporal(),
23245 Ld->isInvariant(), Ld->getAlignment());
23246 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23247 Ld->getPointerInfo().getWithOffset(4),
23248 Ld->isVolatile(), Ld->isNonTemporal(),
23250 MinAlign(Ld->getAlignment(), 4));
23252 SDValue NewChain = LoLd.getValue(1);
23253 if (TokenFactorIndex != -1) {
23254 Ops.push_back(LoLd);
23255 Ops.push_back(HiLd);
23256 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23259 LoAddr = St->getBasePtr();
23260 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23261 DAG.getConstant(4, StDL, MVT::i32));
23263 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23264 St->getPointerInfo(),
23265 St->isVolatile(), St->isNonTemporal(),
23266 St->getAlignment());
23267 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23268 St->getPointerInfo().getWithOffset(4),
23270 St->isNonTemporal(),
23271 MinAlign(St->getAlignment(), 4));
23272 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23275 // This is similar to the above case, but here we handle a scalar 64-bit
23276 // integer store that is extracted from a vector on a 32-bit target.
23277 // If we have SSE2, then we can treat it like a floating-point double
23278 // to get past legalization. The execution dependencies fixup pass will
23279 // choose the optimal machine instruction for the store if this really is
23280 // an integer or v2f32 rather than an f64.
23281 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23282 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23283 SDValue OldExtract = St->getOperand(1);
23284 SDValue ExtOp0 = OldExtract.getOperand(0);
23285 unsigned VecSize = ExtOp0.getValueSizeInBits();
23286 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23287 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
23288 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23289 BitCast, OldExtract.getOperand(1));
23290 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23291 St->getPointerInfo(), St->isVolatile(),
23292 St->isNonTemporal(), St->getAlignment());
23298 /// Return 'true' if this vector operation is "horizontal"
23299 /// and return the operands for the horizontal operation in LHS and RHS. A
23300 /// horizontal operation performs the binary operation on successive elements
23301 /// of its first operand, then on successive elements of its second operand,
23302 /// returning the resulting values in a vector. For example, if
23303 /// A = < float a0, float a1, float a2, float a3 >
23305 /// B = < float b0, float b1, float b2, float b3 >
23306 /// then the result of doing a horizontal operation on A and B is
23307 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23308 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23309 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23310 /// set to A, RHS to B, and the routine returns 'true'.
23311 /// Note that the binary operation should have the property that if one of the
23312 /// operands is UNDEF then the result is UNDEF.
23313 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23314 // Look for the following pattern: if
23315 // A = < float a0, float a1, float a2, float a3 >
23316 // B = < float b0, float b1, float b2, float b3 >
23318 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23319 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23320 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23321 // which is A horizontal-op B.
23323 // At least one of the operands should be a vector shuffle.
23324 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23325 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23328 MVT VT = LHS.getSimpleValueType();
23330 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23331 "Unsupported vector type for horizontal add/sub");
23333 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23334 // operate independently on 128-bit lanes.
23335 unsigned NumElts = VT.getVectorNumElements();
23336 unsigned NumLanes = VT.getSizeInBits()/128;
23337 unsigned NumLaneElts = NumElts / NumLanes;
23338 assert((NumLaneElts % 2 == 0) &&
23339 "Vector type should have an even number of elements in each lane");
23340 unsigned HalfLaneElts = NumLaneElts/2;
23342 // View LHS in the form
23343 // LHS = VECTOR_SHUFFLE A, B, LMask
23344 // If LHS is not a shuffle then pretend it is the shuffle
23345 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23346 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23349 SmallVector<int, 16> LMask(NumElts);
23350 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23351 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23352 A = LHS.getOperand(0);
23353 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23354 B = LHS.getOperand(1);
23355 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23356 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23358 if (LHS.getOpcode() != ISD::UNDEF)
23360 for (unsigned i = 0; i != NumElts; ++i)
23364 // Likewise, view RHS in the form
23365 // RHS = VECTOR_SHUFFLE C, D, RMask
23367 SmallVector<int, 16> RMask(NumElts);
23368 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23369 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23370 C = RHS.getOperand(0);
23371 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23372 D = RHS.getOperand(1);
23373 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23374 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23376 if (RHS.getOpcode() != ISD::UNDEF)
23378 for (unsigned i = 0; i != NumElts; ++i)
23382 // Check that the shuffles are both shuffling the same vectors.
23383 if (!(A == C && B == D) && !(A == D && B == C))
23386 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23387 if (!A.getNode() && !B.getNode())
23390 // If A and B occur in reverse order in RHS, then "swap" them (which means
23391 // rewriting the mask).
23393 ShuffleVectorSDNode::commuteMask(RMask);
23395 // At this point LHS and RHS are equivalent to
23396 // LHS = VECTOR_SHUFFLE A, B, LMask
23397 // RHS = VECTOR_SHUFFLE A, B, RMask
23398 // Check that the masks correspond to performing a horizontal operation.
23399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23400 for (unsigned i = 0; i != NumLaneElts; ++i) {
23401 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23403 // Ignore any UNDEF components.
23404 if (LIdx < 0 || RIdx < 0 ||
23405 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23406 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23409 // Check that successive elements are being operated on. If not, this is
23410 // not a horizontal operation.
23411 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23412 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23413 if (!(LIdx == Index && RIdx == Index + 1) &&
23414 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23419 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23420 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23424 /// Do target-specific dag combines on floating point adds.
23425 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23426 const X86Subtarget *Subtarget) {
23427 EVT VT = N->getValueType(0);
23428 SDValue LHS = N->getOperand(0);
23429 SDValue RHS = N->getOperand(1);
23431 // Try to synthesize horizontal adds from adds of shuffles.
23432 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23433 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23434 isHorizontalBinOp(LHS, RHS, true))
23435 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23439 /// Do target-specific dag combines on floating point subs.
23440 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23441 const X86Subtarget *Subtarget) {
23442 EVT VT = N->getValueType(0);
23443 SDValue LHS = N->getOperand(0);
23444 SDValue RHS = N->getOperand(1);
23446 // Try to synthesize horizontal subs from subs of shuffles.
23447 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23448 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23449 isHorizontalBinOp(LHS, RHS, false))
23450 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23454 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23455 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23456 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23458 // F[X]OR(0.0, x) -> x
23459 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23460 if (C->getValueAPF().isPosZero())
23461 return N->getOperand(1);
23463 // F[X]OR(x, 0.0) -> x
23464 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23465 if (C->getValueAPF().isPosZero())
23466 return N->getOperand(0);
23470 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23471 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23472 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23474 // Only perform optimizations if UnsafeMath is used.
23475 if (!DAG.getTarget().Options.UnsafeFPMath)
23478 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23479 // into FMINC and FMAXC, which are Commutative operations.
23480 unsigned NewOp = 0;
23481 switch (N->getOpcode()) {
23482 default: llvm_unreachable("unknown opcode");
23483 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23484 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23487 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23488 N->getOperand(0), N->getOperand(1));
23491 /// Do target-specific dag combines on X86ISD::FAND nodes.
23492 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23493 // FAND(0.0, x) -> 0.0
23494 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23495 if (C->getValueAPF().isPosZero())
23496 return N->getOperand(0);
23498 // FAND(x, 0.0) -> 0.0
23499 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23500 if (C->getValueAPF().isPosZero())
23501 return N->getOperand(1);
23506 /// Do target-specific dag combines on X86ISD::FANDN nodes
23507 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23508 // FANDN(0.0, x) -> x
23509 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23510 if (C->getValueAPF().isPosZero())
23511 return N->getOperand(1);
23513 // FANDN(x, 0.0) -> 0.0
23514 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23515 if (C->getValueAPF().isPosZero())
23516 return N->getOperand(1);
23521 static SDValue PerformBTCombine(SDNode *N,
23523 TargetLowering::DAGCombinerInfo &DCI) {
23524 // BT ignores high bits in the bit index operand.
23525 SDValue Op1 = N->getOperand(1);
23526 if (Op1.hasOneUse()) {
23527 unsigned BitWidth = Op1.getValueSizeInBits();
23528 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23529 APInt KnownZero, KnownOne;
23530 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23531 !DCI.isBeforeLegalizeOps());
23532 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23533 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23534 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23535 DCI.CommitTargetLoweringOpt(TLO);
23540 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23541 SDValue Op = N->getOperand(0);
23542 if (Op.getOpcode() == ISD::BITCAST)
23543 Op = Op.getOperand(0);
23544 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23545 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23546 VT.getVectorElementType().getSizeInBits() ==
23547 OpVT.getVectorElementType().getSizeInBits()) {
23548 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23553 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23554 const X86Subtarget *Subtarget) {
23555 EVT VT = N->getValueType(0);
23556 if (!VT.isVector())
23559 SDValue N0 = N->getOperand(0);
23560 SDValue N1 = N->getOperand(1);
23561 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23564 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23565 // both SSE and AVX2 since there is no sign-extended shift right
23566 // operation on a vector with 64-bit elements.
23567 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23568 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23569 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23570 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23571 SDValue N00 = N0.getOperand(0);
23573 // EXTLOAD has a better solution on AVX2,
23574 // it may be replaced with X86ISD::VSEXT node.
23575 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23576 if (!ISD::isNormalLoad(N00.getNode()))
23579 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23580 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23582 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23588 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23589 TargetLowering::DAGCombinerInfo &DCI,
23590 const X86Subtarget *Subtarget) {
23591 SDValue N0 = N->getOperand(0);
23592 EVT VT = N->getValueType(0);
23594 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23595 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23596 // This exposes the sext to the sdivrem lowering, so that it directly extends
23597 // from AH (which we otherwise need to do contortions to access).
23598 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23599 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
23601 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23602 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
23603 N0.getOperand(0), N0.getOperand(1));
23604 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23605 return R.getValue(1);
23608 if (!DCI.isBeforeLegalizeOps())
23611 if (!Subtarget->hasFp256())
23614 if (VT.isVector() && VT.getSizeInBits() == 256) {
23615 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23623 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23624 const X86Subtarget* Subtarget) {
23626 EVT VT = N->getValueType(0);
23628 // Let legalize expand this if it isn't a legal type yet.
23629 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23632 EVT ScalarVT = VT.getScalarType();
23633 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23634 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23637 SDValue A = N->getOperand(0);
23638 SDValue B = N->getOperand(1);
23639 SDValue C = N->getOperand(2);
23641 bool NegA = (A.getOpcode() == ISD::FNEG);
23642 bool NegB = (B.getOpcode() == ISD::FNEG);
23643 bool NegC = (C.getOpcode() == ISD::FNEG);
23645 // Negative multiplication when NegA xor NegB
23646 bool NegMul = (NegA != NegB);
23648 A = A.getOperand(0);
23650 B = B.getOperand(0);
23652 C = C.getOperand(0);
23656 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23658 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23660 return DAG.getNode(Opcode, dl, VT, A, B, C);
23663 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23664 TargetLowering::DAGCombinerInfo &DCI,
23665 const X86Subtarget *Subtarget) {
23666 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23667 // (and (i32 x86isd::setcc_carry), 1)
23668 // This eliminates the zext. This transformation is necessary because
23669 // ISD::SETCC is always legalized to i8.
23671 SDValue N0 = N->getOperand(0);
23672 EVT VT = N->getValueType(0);
23674 if (N0.getOpcode() == ISD::AND &&
23676 N0.getOperand(0).hasOneUse()) {
23677 SDValue N00 = N0.getOperand(0);
23678 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23679 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23680 if (!C || C->getZExtValue() != 1)
23682 return DAG.getNode(ISD::AND, dl, VT,
23683 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23684 N00.getOperand(0), N00.getOperand(1)),
23685 DAG.getConstant(1, dl, VT));
23689 if (N0.getOpcode() == ISD::TRUNCATE &&
23691 N0.getOperand(0).hasOneUse()) {
23692 SDValue N00 = N0.getOperand(0);
23693 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23694 return DAG.getNode(ISD::AND, dl, VT,
23695 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23696 N00.getOperand(0), N00.getOperand(1)),
23697 DAG.getConstant(1, dl, VT));
23700 if (VT.is256BitVector()) {
23701 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23706 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23707 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23708 // This exposes the zext to the udivrem lowering, so that it directly extends
23709 // from AH (which we otherwise need to do contortions to access).
23710 if (N0.getOpcode() == ISD::UDIVREM &&
23711 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23712 (VT == MVT::i32 || VT == MVT::i64)) {
23713 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23714 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23715 N0.getOperand(0), N0.getOperand(1));
23716 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23717 return R.getValue(1);
23723 // Optimize x == -y --> x+y == 0
23724 // x != -y --> x+y != 0
23725 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23726 const X86Subtarget* Subtarget) {
23727 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23728 SDValue LHS = N->getOperand(0);
23729 SDValue RHS = N->getOperand(1);
23730 EVT VT = N->getValueType(0);
23733 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23734 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23735 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23736 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
23737 LHS.getOperand(1));
23738 return DAG.getSetCC(DL, N->getValueType(0), addV,
23739 DAG.getConstant(0, DL, addV.getValueType()), CC);
23741 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23743 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23744 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
23745 RHS.getOperand(1));
23746 return DAG.getSetCC(DL, N->getValueType(0), addV,
23747 DAG.getConstant(0, DL, addV.getValueType()), CC);
23750 if (VT.getScalarType() == MVT::i1 &&
23751 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
23753 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23754 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23755 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23757 if (!IsSEXT0 || !IsVZero1) {
23758 // Swap the operands and update the condition code.
23759 std::swap(LHS, RHS);
23760 CC = ISD::getSetCCSwappedOperands(CC);
23762 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23763 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23764 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23767 if (IsSEXT0 && IsVZero1) {
23768 assert(VT == LHS.getOperand(0).getValueType() &&
23769 "Uexpected operand type");
23770 if (CC == ISD::SETGT)
23771 return DAG.getConstant(0, DL, VT);
23772 if (CC == ISD::SETLE)
23773 return DAG.getConstant(1, DL, VT);
23774 if (CC == ISD::SETEQ || CC == ISD::SETGE)
23775 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23777 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
23778 "Unexpected condition code!");
23779 return LHS.getOperand(0);
23786 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
23787 SelectionDAG &DAG) {
23789 MVT VT = Load->getSimpleValueType(0);
23790 MVT EVT = VT.getVectorElementType();
23791 SDValue Addr = Load->getOperand(1);
23792 SDValue NewAddr = DAG.getNode(
23793 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
23794 DAG.getConstant(Index * EVT.getStoreSize(), dl,
23795 Addr.getSimpleValueType()));
23798 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
23799 DAG.getMachineFunction().getMachineMemOperand(
23800 Load->getMemOperand(), 0, EVT.getStoreSize()));
23804 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23805 const X86Subtarget *Subtarget) {
23807 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23808 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23809 "X86insertps is only defined for v4x32");
23811 SDValue Ld = N->getOperand(1);
23812 if (MayFoldLoad(Ld)) {
23813 // Extract the countS bits from the immediate so we can get the proper
23814 // address when narrowing the vector load to a specific element.
23815 // When the second source op is a memory address, insertps doesn't use
23816 // countS and just gets an f32 from that address.
23817 unsigned DestIndex =
23818 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23820 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23822 // Create this as a scalar to vector to match the instruction pattern.
23823 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23824 // countS bits are ignored when loading from memory on insertps, which
23825 // means we don't need to explicitly set them to 0.
23826 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23827 LoadScalarToVector, N->getOperand(2));
23832 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
23833 SDValue V0 = N->getOperand(0);
23834 SDValue V1 = N->getOperand(1);
23836 EVT VT = N->getValueType(0);
23838 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23839 // operands and changing the mask to 1. This saves us a bunch of
23840 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23841 // x86InstrInfo knows how to commute this back after instruction selection
23842 // if it would help register allocation.
23844 // TODO: If optimizing for size or a processor that doesn't suffer from
23845 // partial register update stalls, this should be transformed into a MOVSD
23846 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23848 if (VT == MVT::v2f64)
23849 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23850 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23851 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
23852 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23858 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23859 // as "sbb reg,reg", since it can be extended without zext and produces
23860 // an all-ones bit which is more useful than 0/1 in some cases.
23861 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23864 return DAG.getNode(ISD::AND, DL, VT,
23865 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23866 DAG.getConstant(X86::COND_B, DL, MVT::i8),
23868 DAG.getConstant(1, DL, VT));
23869 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23870 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23871 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23872 DAG.getConstant(X86::COND_B, DL, MVT::i8),
23876 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23877 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23878 TargetLowering::DAGCombinerInfo &DCI,
23879 const X86Subtarget *Subtarget) {
23881 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23882 SDValue EFLAGS = N->getOperand(1);
23884 if (CC == X86::COND_A) {
23885 // Try to convert COND_A into COND_B in an attempt to facilitate
23886 // materializing "setb reg".
23888 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23889 // cannot take an immediate as its first operand.
23891 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23892 EFLAGS.getValueType().isInteger() &&
23893 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23894 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23895 EFLAGS.getNode()->getVTList(),
23896 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23897 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23898 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23902 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23903 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23905 if (CC == X86::COND_B)
23906 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23910 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23911 if (Flags.getNode()) {
23912 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
23913 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23919 // Optimize branch condition evaluation.
23921 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23922 TargetLowering::DAGCombinerInfo &DCI,
23923 const X86Subtarget *Subtarget) {
23925 SDValue Chain = N->getOperand(0);
23926 SDValue Dest = N->getOperand(1);
23927 SDValue EFLAGS = N->getOperand(3);
23928 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23932 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23933 if (Flags.getNode()) {
23934 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
23935 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23942 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23943 SelectionDAG &DAG) {
23944 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23945 // optimize away operation when it's from a constant.
23947 // The general transformation is:
23948 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23949 // AND(VECTOR_CMP(x,y), constant2)
23950 // constant2 = UNARYOP(constant)
23952 // Early exit if this isn't a vector operation, the operand of the
23953 // unary operation isn't a bitwise AND, or if the sizes of the operations
23954 // aren't the same.
23955 EVT VT = N->getValueType(0);
23956 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23957 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23958 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23961 // Now check that the other operand of the AND is a constant. We could
23962 // make the transformation for non-constant splats as well, but it's unclear
23963 // that would be a benefit as it would not eliminate any operations, just
23964 // perform one more step in scalar code before moving to the vector unit.
23965 if (BuildVectorSDNode *BV =
23966 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23967 // Bail out if the vector isn't a constant.
23968 if (!BV->isConstant())
23971 // Everything checks out. Build up the new and improved node.
23973 EVT IntVT = BV->getValueType(0);
23974 // Create a new constant of the appropriate type for the transformed
23976 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23977 // The AND node needs bitcasts to/from an integer vector type around it.
23978 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23979 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23980 N->getOperand(0)->getOperand(0), MaskConst);
23981 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23988 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23989 const X86Subtarget *Subtarget) {
23990 // First try to optimize away the conversion entirely when it's
23991 // conditionally from a constant. Vectors only.
23992 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23993 if (Res != SDValue())
23996 // Now move on to more general possibilities.
23997 SDValue Op0 = N->getOperand(0);
23998 EVT InVT = Op0->getValueType(0);
24000 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24001 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24003 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24004 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24005 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24008 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24009 // a 32-bit target where SSE doesn't support i64->FP operations.
24010 if (Op0.getOpcode() == ISD::LOAD) {
24011 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24012 EVT VT = Ld->getValueType(0);
24014 // This transformation is not supported if the result type is f16
24015 if (N->getValueType(0) == MVT::f16)
24018 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24019 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24020 !Subtarget->is64Bit() && VT == MVT::i64) {
24021 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24022 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24023 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24030 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24031 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24032 X86TargetLowering::DAGCombinerInfo &DCI) {
24033 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24034 // the result is either zero or one (depending on the input carry bit).
24035 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24036 if (X86::isZeroNode(N->getOperand(0)) &&
24037 X86::isZeroNode(N->getOperand(1)) &&
24038 // We don't have a good way to replace an EFLAGS use, so only do this when
24040 SDValue(N, 1).use_empty()) {
24042 EVT VT = N->getValueType(0);
24043 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24044 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24045 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24046 DAG.getConstant(X86::COND_B, DL,
24049 DAG.getConstant(1, DL, VT));
24050 return DCI.CombineTo(N, Res1, CarryOut);
24056 // fold (add Y, (sete X, 0)) -> adc 0, Y
24057 // (add Y, (setne X, 0)) -> sbb -1, Y
24058 // (sub (sete X, 0), Y) -> sbb 0, Y
24059 // (sub (setne X, 0), Y) -> adc -1, Y
24060 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24063 // Look through ZExts.
24064 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24065 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24068 SDValue SetCC = Ext.getOperand(0);
24069 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24072 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24073 if (CC != X86::COND_E && CC != X86::COND_NE)
24076 SDValue Cmp = SetCC.getOperand(1);
24077 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24078 !X86::isZeroNode(Cmp.getOperand(1)) ||
24079 !Cmp.getOperand(0).getValueType().isInteger())
24082 SDValue CmpOp0 = Cmp.getOperand(0);
24083 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24084 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24086 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24087 if (CC == X86::COND_NE)
24088 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24089 DL, OtherVal.getValueType(), OtherVal,
24090 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24092 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24093 DL, OtherVal.getValueType(), OtherVal,
24094 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24097 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24098 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24099 const X86Subtarget *Subtarget) {
24100 EVT VT = N->getValueType(0);
24101 SDValue Op0 = N->getOperand(0);
24102 SDValue Op1 = N->getOperand(1);
24104 // Try to synthesize horizontal adds from adds of shuffles.
24105 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24106 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24107 isHorizontalBinOp(Op0, Op1, true))
24108 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24110 return OptimizeConditionalInDecrement(N, DAG);
24113 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24114 const X86Subtarget *Subtarget) {
24115 SDValue Op0 = N->getOperand(0);
24116 SDValue Op1 = N->getOperand(1);
24118 // X86 can't encode an immediate LHS of a sub. See if we can push the
24119 // negation into a preceding instruction.
24120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24121 // If the RHS of the sub is a XOR with one use and a constant, invert the
24122 // immediate. Then add one to the LHS of the sub so we can turn
24123 // X-Y -> X+~Y+1, saving one register.
24124 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24125 isa<ConstantSDNode>(Op1.getOperand(1))) {
24126 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24127 EVT VT = Op0.getValueType();
24128 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24130 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24131 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24132 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24136 // Try to synthesize horizontal adds from adds of shuffles.
24137 EVT VT = N->getValueType(0);
24138 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24139 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24140 isHorizontalBinOp(Op0, Op1, true))
24141 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24143 return OptimizeConditionalInDecrement(N, DAG);
24146 /// performVZEXTCombine - Performs build vector combines
24147 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24148 TargetLowering::DAGCombinerInfo &DCI,
24149 const X86Subtarget *Subtarget) {
24151 MVT VT = N->getSimpleValueType(0);
24152 SDValue Op = N->getOperand(0);
24153 MVT OpVT = Op.getSimpleValueType();
24154 MVT OpEltVT = OpVT.getVectorElementType();
24155 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24157 // (vzext (bitcast (vzext (x)) -> (vzext x)
24159 while (V.getOpcode() == ISD::BITCAST)
24160 V = V.getOperand(0);
24162 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24163 MVT InnerVT = V.getSimpleValueType();
24164 MVT InnerEltVT = InnerVT.getVectorElementType();
24166 // If the element sizes match exactly, we can just do one larger vzext. This
24167 // is always an exact type match as vzext operates on integer types.
24168 if (OpEltVT == InnerEltVT) {
24169 assert(OpVT == InnerVT && "Types must match for vzext!");
24170 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24173 // The only other way we can combine them is if only a single element of the
24174 // inner vzext is used in the input to the outer vzext.
24175 if (InnerEltVT.getSizeInBits() < InputBits)
24178 // In this case, the inner vzext is completely dead because we're going to
24179 // only look at bits inside of the low element. Just do the outer vzext on
24180 // a bitcast of the input to the inner.
24181 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24182 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24185 // Check if we can bypass extracting and re-inserting an element of an input
24186 // vector. Essentialy:
24187 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24188 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24189 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24190 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24191 SDValue ExtractedV = V.getOperand(0);
24192 SDValue OrigV = ExtractedV.getOperand(0);
24193 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24194 if (ExtractIdx->getZExtValue() == 0) {
24195 MVT OrigVT = OrigV.getSimpleValueType();
24196 // Extract a subvector if necessary...
24197 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24198 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24199 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24200 OrigVT.getVectorNumElements() / Ratio);
24201 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24202 DAG.getIntPtrConstant(0, DL));
24204 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24205 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24212 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24213 DAGCombinerInfo &DCI) const {
24214 SelectionDAG &DAG = DCI.DAG;
24215 switch (N->getOpcode()) {
24217 case ISD::EXTRACT_VECTOR_ELT:
24218 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24221 case X86ISD::SHRUNKBLEND:
24222 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24223 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24224 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24225 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24226 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24227 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24228 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24231 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24232 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24233 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24234 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24235 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24236 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24237 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24238 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24239 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24240 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24241 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24243 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24245 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24246 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24247 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24248 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24249 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24250 case ISD::ANY_EXTEND:
24251 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24252 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24253 case ISD::SIGN_EXTEND_INREG:
24254 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24255 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24256 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24257 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24258 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24259 case X86ISD::SHUFP: // Handle all target specific shuffles
24260 case X86ISD::PALIGNR:
24261 case X86ISD::UNPCKH:
24262 case X86ISD::UNPCKL:
24263 case X86ISD::MOVHLPS:
24264 case X86ISD::MOVLHPS:
24265 case X86ISD::PSHUFB:
24266 case X86ISD::PSHUFD:
24267 case X86ISD::PSHUFHW:
24268 case X86ISD::PSHUFLW:
24269 case X86ISD::MOVSS:
24270 case X86ISD::MOVSD:
24271 case X86ISD::VPERMILPI:
24272 case X86ISD::VPERM2X128:
24273 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24274 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24275 case ISD::INTRINSIC_WO_CHAIN:
24276 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24277 case X86ISD::INSERTPS: {
24278 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24279 return PerformINSERTPSCombine(N, DAG, Subtarget);
24282 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24288 /// isTypeDesirableForOp - Return true if the target has native support for
24289 /// the specified value type and it is 'desirable' to use the type for the
24290 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24291 /// instruction encodings are longer and some i16 instructions are slow.
24292 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24293 if (!isTypeLegal(VT))
24295 if (VT != MVT::i16)
24302 case ISD::SIGN_EXTEND:
24303 case ISD::ZERO_EXTEND:
24304 case ISD::ANY_EXTEND:
24317 /// IsDesirableToPromoteOp - This method query the target whether it is
24318 /// beneficial for dag combiner to promote the specified node. If true, it
24319 /// should return the desired promotion type by reference.
24320 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24321 EVT VT = Op.getValueType();
24322 if (VT != MVT::i16)
24325 bool Promote = false;
24326 bool Commute = false;
24327 switch (Op.getOpcode()) {
24330 LoadSDNode *LD = cast<LoadSDNode>(Op);
24331 // If the non-extending load has a single use and it's not live out, then it
24332 // might be folded.
24333 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24334 Op.hasOneUse()*/) {
24335 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24336 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24337 // The only case where we'd want to promote LOAD (rather then it being
24338 // promoted as an operand is when it's only use is liveout.
24339 if (UI->getOpcode() != ISD::CopyToReg)
24346 case ISD::SIGN_EXTEND:
24347 case ISD::ZERO_EXTEND:
24348 case ISD::ANY_EXTEND:
24353 SDValue N0 = Op.getOperand(0);
24354 // Look out for (store (shl (load), x)).
24355 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24368 SDValue N0 = Op.getOperand(0);
24369 SDValue N1 = Op.getOperand(1);
24370 if (!Commute && MayFoldLoad(N1))
24372 // Avoid disabling potential load folding opportunities.
24373 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24375 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24385 //===----------------------------------------------------------------------===//
24386 // X86 Inline Assembly Support
24387 //===----------------------------------------------------------------------===//
24389 // Helper to match a string separated by whitespace.
24390 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24391 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24393 for (StringRef Piece : Pieces) {
24394 if (!S.startswith(Piece)) // Check if the piece matches.
24397 S = S.substr(Piece.size());
24398 StringRef::size_type Pos = S.find_first_not_of(" \t");
24399 if (Pos == 0) // We matched a prefix.
24408 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24410 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24411 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24412 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24413 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24415 if (AsmPieces.size() == 3)
24417 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24424 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24425 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24427 std::string AsmStr = IA->getAsmString();
24429 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24430 if (!Ty || Ty->getBitWidth() % 16 != 0)
24433 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24434 SmallVector<StringRef, 4> AsmPieces;
24435 SplitString(AsmStr, AsmPieces, ";\n");
24437 switch (AsmPieces.size()) {
24438 default: return false;
24440 // FIXME: this should verify that we are targeting a 486 or better. If not,
24441 // we will turn this bswap into something that will be lowered to logical
24442 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24443 // lower so don't worry about this.
24445 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24446 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24447 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24448 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24449 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24450 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24451 // No need to check constraints, nothing other than the equivalent of
24452 // "=r,0" would be valid here.
24453 return IntrinsicLowering::LowerToByteSwap(CI);
24456 // rorw $$8, ${0:w} --> llvm.bswap.i16
24457 if (CI->getType()->isIntegerTy(16) &&
24458 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24459 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24460 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24462 const std::string &ConstraintsStr = IA->getConstraintString();
24463 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24464 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24465 if (clobbersFlagRegisters(AsmPieces))
24466 return IntrinsicLowering::LowerToByteSwap(CI);
24470 if (CI->getType()->isIntegerTy(32) &&
24471 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24472 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24473 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24474 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24476 const std::string &ConstraintsStr = IA->getConstraintString();
24477 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24478 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24479 if (clobbersFlagRegisters(AsmPieces))
24480 return IntrinsicLowering::LowerToByteSwap(CI);
24483 if (CI->getType()->isIntegerTy(64)) {
24484 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24485 if (Constraints.size() >= 2 &&
24486 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24487 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24488 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24489 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24490 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24491 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24492 return IntrinsicLowering::LowerToByteSwap(CI);
24500 /// getConstraintType - Given a constraint letter, return the type of
24501 /// constraint it is for this target.
24502 X86TargetLowering::ConstraintType
24503 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24504 if (Constraint.size() == 1) {
24505 switch (Constraint[0]) {
24516 return C_RegisterClass;
24540 return TargetLowering::getConstraintType(Constraint);
24543 /// Examine constraint type and operand type and determine a weight value.
24544 /// This object must already have been set up with the operand type
24545 /// and the current alternative constraint selected.
24546 TargetLowering::ConstraintWeight
24547 X86TargetLowering::getSingleConstraintMatchWeight(
24548 AsmOperandInfo &info, const char *constraint) const {
24549 ConstraintWeight weight = CW_Invalid;
24550 Value *CallOperandVal = info.CallOperandVal;
24551 // If we don't have a value, we can't do a match,
24552 // but allow it at the lowest weight.
24553 if (!CallOperandVal)
24555 Type *type = CallOperandVal->getType();
24556 // Look at the constraint type.
24557 switch (*constraint) {
24559 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24570 if (CallOperandVal->getType()->isIntegerTy())
24571 weight = CW_SpecificReg;
24576 if (type->isFloatingPointTy())
24577 weight = CW_SpecificReg;
24580 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24581 weight = CW_SpecificReg;
24585 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24586 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24587 weight = CW_Register;
24590 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24591 if (C->getZExtValue() <= 31)
24592 weight = CW_Constant;
24596 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24597 if (C->getZExtValue() <= 63)
24598 weight = CW_Constant;
24602 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24603 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24604 weight = CW_Constant;
24608 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24609 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24610 weight = CW_Constant;
24614 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24615 if (C->getZExtValue() <= 3)
24616 weight = CW_Constant;
24620 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24621 if (C->getZExtValue() <= 0xff)
24622 weight = CW_Constant;
24627 if (isa<ConstantFP>(CallOperandVal)) {
24628 weight = CW_Constant;
24632 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24633 if ((C->getSExtValue() >= -0x80000000LL) &&
24634 (C->getSExtValue() <= 0x7fffffffLL))
24635 weight = CW_Constant;
24639 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24640 if (C->getZExtValue() <= 0xffffffff)
24641 weight = CW_Constant;
24648 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24649 /// with another that has more specific requirements based on the type of the
24650 /// corresponding operand.
24651 const char *X86TargetLowering::
24652 LowerXConstraint(EVT ConstraintVT) const {
24653 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24654 // 'f' like normal targets.
24655 if (ConstraintVT.isFloatingPoint()) {
24656 if (Subtarget->hasSSE2())
24658 if (Subtarget->hasSSE1())
24662 return TargetLowering::LowerXConstraint(ConstraintVT);
24665 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24666 /// vector. If it is invalid, don't add anything to Ops.
24667 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24668 std::string &Constraint,
24669 std::vector<SDValue>&Ops,
24670 SelectionDAG &DAG) const {
24673 // Only support length 1 constraints for now.
24674 if (Constraint.length() > 1) return;
24676 char ConstraintLetter = Constraint[0];
24677 switch (ConstraintLetter) {
24680 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24681 if (C->getZExtValue() <= 31) {
24682 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24683 Op.getValueType());
24689 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24690 if (C->getZExtValue() <= 63) {
24691 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24692 Op.getValueType());
24698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24699 if (isInt<8>(C->getSExtValue())) {
24700 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24701 Op.getValueType());
24707 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24708 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24709 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24710 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
24711 Op.getValueType());
24717 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24718 if (C->getZExtValue() <= 3) {
24719 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24720 Op.getValueType());
24726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24727 if (C->getZExtValue() <= 255) {
24728 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24729 Op.getValueType());
24735 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24736 if (C->getZExtValue() <= 127) {
24737 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24738 Op.getValueType());
24744 // 32-bit signed value
24745 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24746 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24747 C->getSExtValue())) {
24748 // Widen to 64 bits here to get it sign extended.
24749 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
24752 // FIXME gcc accepts some relocatable values here too, but only in certain
24753 // memory models; it's complicated.
24758 // 32-bit unsigned value
24759 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24760 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24761 C->getZExtValue())) {
24762 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24763 Op.getValueType());
24767 // FIXME gcc accepts some relocatable values here too, but only in certain
24768 // memory models; it's complicated.
24772 // Literal immediates are always ok.
24773 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24774 // Widen to 64 bits here to get it sign extended.
24775 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
24779 // In any sort of PIC mode addresses need to be computed at runtime by
24780 // adding in a register or some sort of table lookup. These can't
24781 // be used as immediates.
24782 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24785 // If we are in non-pic codegen mode, we allow the address of a global (with
24786 // an optional displacement) to be used with 'i'.
24787 GlobalAddressSDNode *GA = nullptr;
24788 int64_t Offset = 0;
24790 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24792 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24793 Offset += GA->getOffset();
24795 } else if (Op.getOpcode() == ISD::ADD) {
24796 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24797 Offset += C->getZExtValue();
24798 Op = Op.getOperand(0);
24801 } else if (Op.getOpcode() == ISD::SUB) {
24802 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24803 Offset += -C->getZExtValue();
24804 Op = Op.getOperand(0);
24809 // Otherwise, this isn't something we can handle, reject it.
24813 const GlobalValue *GV = GA->getGlobal();
24814 // If we require an extra load to get this address, as in PIC mode, we
24815 // can't accept it.
24816 if (isGlobalStubReference(
24817 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24820 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24821 GA->getValueType(0), Offset);
24826 if (Result.getNode()) {
24827 Ops.push_back(Result);
24830 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24833 std::pair<unsigned, const TargetRegisterClass *>
24834 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
24835 const std::string &Constraint,
24837 // First, see if this is a constraint that directly corresponds to an LLVM
24839 if (Constraint.size() == 1) {
24840 // GCC Constraint Letters
24841 switch (Constraint[0]) {
24843 // TODO: Slight differences here in allocation order and leaving
24844 // RIP in the class. Do they matter any more here than they do
24845 // in the normal allocation?
24846 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24847 if (Subtarget->is64Bit()) {
24848 if (VT == MVT::i32 || VT == MVT::f32)
24849 return std::make_pair(0U, &X86::GR32RegClass);
24850 if (VT == MVT::i16)
24851 return std::make_pair(0U, &X86::GR16RegClass);
24852 if (VT == MVT::i8 || VT == MVT::i1)
24853 return std::make_pair(0U, &X86::GR8RegClass);
24854 if (VT == MVT::i64 || VT == MVT::f64)
24855 return std::make_pair(0U, &X86::GR64RegClass);
24858 // 32-bit fallthrough
24859 case 'Q': // Q_REGS
24860 if (VT == MVT::i32 || VT == MVT::f32)
24861 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24862 if (VT == MVT::i16)
24863 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24864 if (VT == MVT::i8 || VT == MVT::i1)
24865 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24866 if (VT == MVT::i64)
24867 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24869 case 'r': // GENERAL_REGS
24870 case 'l': // INDEX_REGS
24871 if (VT == MVT::i8 || VT == MVT::i1)
24872 return std::make_pair(0U, &X86::GR8RegClass);
24873 if (VT == MVT::i16)
24874 return std::make_pair(0U, &X86::GR16RegClass);
24875 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24876 return std::make_pair(0U, &X86::GR32RegClass);
24877 return std::make_pair(0U, &X86::GR64RegClass);
24878 case 'R': // LEGACY_REGS
24879 if (VT == MVT::i8 || VT == MVT::i1)
24880 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24881 if (VT == MVT::i16)
24882 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24883 if (VT == MVT::i32 || !Subtarget->is64Bit())
24884 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24885 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24886 case 'f': // FP Stack registers.
24887 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24888 // value to the correct fpstack register class.
24889 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24890 return std::make_pair(0U, &X86::RFP32RegClass);
24891 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24892 return std::make_pair(0U, &X86::RFP64RegClass);
24893 return std::make_pair(0U, &X86::RFP80RegClass);
24894 case 'y': // MMX_REGS if MMX allowed.
24895 if (!Subtarget->hasMMX()) break;
24896 return std::make_pair(0U, &X86::VR64RegClass);
24897 case 'Y': // SSE_REGS if SSE2 allowed
24898 if (!Subtarget->hasSSE2()) break;
24900 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24901 if (!Subtarget->hasSSE1()) break;
24903 switch (VT.SimpleTy) {
24905 // Scalar SSE types.
24908 return std::make_pair(0U, &X86::FR32RegClass);
24911 return std::make_pair(0U, &X86::FR64RegClass);
24919 return std::make_pair(0U, &X86::VR128RegClass);
24927 return std::make_pair(0U, &X86::VR256RegClass);
24932 return std::make_pair(0U, &X86::VR512RegClass);
24938 // Use the default implementation in TargetLowering to convert the register
24939 // constraint into a member of a register class.
24940 std::pair<unsigned, const TargetRegisterClass*> Res;
24941 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
24943 // Not found as a standard register?
24945 // Map st(0) -> st(7) -> ST0
24946 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24947 tolower(Constraint[1]) == 's' &&
24948 tolower(Constraint[2]) == 't' &&
24949 Constraint[3] == '(' &&
24950 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24951 Constraint[5] == ')' &&
24952 Constraint[6] == '}') {
24954 Res.first = X86::FP0+Constraint[4]-'0';
24955 Res.second = &X86::RFP80RegClass;
24959 // GCC allows "st(0)" to be called just plain "st".
24960 if (StringRef("{st}").equals_lower(Constraint)) {
24961 Res.first = X86::FP0;
24962 Res.second = &X86::RFP80RegClass;
24967 if (StringRef("{flags}").equals_lower(Constraint)) {
24968 Res.first = X86::EFLAGS;
24969 Res.second = &X86::CCRRegClass;
24973 // 'A' means EAX + EDX.
24974 if (Constraint == "A") {
24975 Res.first = X86::EAX;
24976 Res.second = &X86::GR32_ADRegClass;
24982 // Otherwise, check to see if this is a register class of the wrong value
24983 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24984 // turn into {ax},{dx}.
24985 if (Res.second->hasType(VT))
24986 return Res; // Correct type already, nothing to do.
24988 // All of the single-register GCC register classes map their values onto
24989 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24990 // really want an 8-bit or 32-bit register, map to the appropriate register
24991 // class and return the appropriate register.
24992 if (Res.second == &X86::GR16RegClass) {
24993 if (VT == MVT::i8 || VT == MVT::i1) {
24994 unsigned DestReg = 0;
24995 switch (Res.first) {
24997 case X86::AX: DestReg = X86::AL; break;
24998 case X86::DX: DestReg = X86::DL; break;
24999 case X86::CX: DestReg = X86::CL; break;
25000 case X86::BX: DestReg = X86::BL; break;
25003 Res.first = DestReg;
25004 Res.second = &X86::GR8RegClass;
25006 } else if (VT == MVT::i32 || VT == MVT::f32) {
25007 unsigned DestReg = 0;
25008 switch (Res.first) {
25010 case X86::AX: DestReg = X86::EAX; break;
25011 case X86::DX: DestReg = X86::EDX; break;
25012 case X86::CX: DestReg = X86::ECX; break;
25013 case X86::BX: DestReg = X86::EBX; break;
25014 case X86::SI: DestReg = X86::ESI; break;
25015 case X86::DI: DestReg = X86::EDI; break;
25016 case X86::BP: DestReg = X86::EBP; break;
25017 case X86::SP: DestReg = X86::ESP; break;
25020 Res.first = DestReg;
25021 Res.second = &X86::GR32RegClass;
25023 } else if (VT == MVT::i64 || VT == MVT::f64) {
25024 unsigned DestReg = 0;
25025 switch (Res.first) {
25027 case X86::AX: DestReg = X86::RAX; break;
25028 case X86::DX: DestReg = X86::RDX; break;
25029 case X86::CX: DestReg = X86::RCX; break;
25030 case X86::BX: DestReg = X86::RBX; break;
25031 case X86::SI: DestReg = X86::RSI; break;
25032 case X86::DI: DestReg = X86::RDI; break;
25033 case X86::BP: DestReg = X86::RBP; break;
25034 case X86::SP: DestReg = X86::RSP; break;
25037 Res.first = DestReg;
25038 Res.second = &X86::GR64RegClass;
25041 } else if (Res.second == &X86::FR32RegClass ||
25042 Res.second == &X86::FR64RegClass ||
25043 Res.second == &X86::VR128RegClass ||
25044 Res.second == &X86::VR256RegClass ||
25045 Res.second == &X86::FR32XRegClass ||
25046 Res.second == &X86::FR64XRegClass ||
25047 Res.second == &X86::VR128XRegClass ||
25048 Res.second == &X86::VR256XRegClass ||
25049 Res.second == &X86::VR512RegClass) {
25050 // Handle references to XMM physical registers that got mapped into the
25051 // wrong class. This can happen with constraints like {xmm0} where the
25052 // target independent register mapper will just pick the first match it can
25053 // find, ignoring the required type.
25055 if (VT == MVT::f32 || VT == MVT::i32)
25056 Res.second = &X86::FR32RegClass;
25057 else if (VT == MVT::f64 || VT == MVT::i64)
25058 Res.second = &X86::FR64RegClass;
25059 else if (X86::VR128RegClass.hasType(VT))
25060 Res.second = &X86::VR128RegClass;
25061 else if (X86::VR256RegClass.hasType(VT))
25062 Res.second = &X86::VR256RegClass;
25063 else if (X86::VR512RegClass.hasType(VT))
25064 Res.second = &X86::VR512RegClass;
25070 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25072 // Scaling factors are not free at all.
25073 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25074 // will take 2 allocations in the out of order engine instead of 1
25075 // for plain addressing mode, i.e. inst (reg1).
25077 // vaddps (%rsi,%drx), %ymm0, %ymm1
25078 // Requires two allocations (one for the load, one for the computation)
25080 // vaddps (%rsi), %ymm0, %ymm1
25081 // Requires just 1 allocation, i.e., freeing allocations for other operations
25082 // and having less micro operations to execute.
25084 // For some X86 architectures, this is even worse because for instance for
25085 // stores, the complex addressing mode forces the instruction to use the
25086 // "load" ports instead of the dedicated "store" port.
25087 // E.g., on Haswell:
25088 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25089 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25090 if (isLegalAddressingMode(AM, Ty))
25091 // Scale represents reg2 * scale, thus account for 1
25092 // as soon as we use a second register.
25093 return AM.Scale != 0;
25097 bool X86TargetLowering::isTargetFTOL() const {
25098 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();