1 //===-- X86/MachineCodeEmitter.cpp - Convert X86 code to machine code -----===//
3 // This file contains the pass that transforms the X86 machine instructions into
4 // actual executable machine code.
6 //===----------------------------------------------------------------------===//
8 #include "X86TargetMachine.h"
10 #include "llvm/PassManager.h"
11 #include "llvm/CodeGen/MachineCodeEmitter.h"
12 #include "llvm/CodeGen/MachineFunction.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/Value.h"
17 class Emitter : public FunctionPass {
19 const X86InstrInfo ⅈ
20 MachineCodeEmitter &MCE;
23 Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
24 : TM(tm), II(TM.getInstrInfo()), MCE(mce) {}
26 bool runOnFunction(Function &F);
28 virtual const char *getPassName() const {
29 return "X86 Machine Code Emitter";
33 void emitBasicBlock(MachineBasicBlock &MBB);
34 void emitInstruction(MachineInstr &MI);
36 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
37 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
38 void emitConstant(unsigned Val, unsigned Size);
40 void emitMemModRMByte(const MachineInstr &MI,
41 unsigned Op, unsigned RegOpcodeField);
47 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
48 /// machine code emitted. This uses a MAchineCodeEmitter object to handle
49 /// actually outputting the machine code and resolving things like the address
50 /// of functions. This method should returns true if machine code emission is
53 bool X86TargetMachine::addPassesToEmitMachineCode(PassManager &PM,
54 MachineCodeEmitter &MCE) {
55 PM.add(new Emitter(*this, MCE));
59 bool Emitter::runOnFunction(Function &F) {
60 MachineFunction &MF = MachineFunction::get(&F);
62 MCE.startFunction(MF);
63 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
65 MCE.finishFunction(MF);
69 void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
70 MCE.startBasicBlock(MBB);
71 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
76 namespace N86 { // Native X86 Register numbers...
78 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
83 // getX86RegNum - This function maps LLVM register identifiers to their X86
84 // specific numbering, which is used in various places encoding instructions.
86 static unsigned getX86RegNum(unsigned RegNo) {
88 case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
89 case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
90 case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
91 case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
92 case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
93 case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
94 case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
95 case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
97 assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
98 "Unknown physical register!");
99 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
104 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
106 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
107 return RM | (RegOpcode << 3) | (Mod << 6);
110 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
111 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
114 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
115 // SIB byte is in the same format as the ModRMByte...
116 MCE.emitByte(ModRMByte(SS, Index, Base));
119 void Emitter::emitConstant(unsigned Val, unsigned Size) {
120 // Output the constant in little endian byte order...
121 for (unsigned i = 0; i != Size; ++i) {
122 MCE.emitByte(Val & 255);
127 static bool isDisp8(int Value) {
128 return Value == (signed char)Value;
131 void Emitter::emitMemModRMByte(const MachineInstr &MI,
132 unsigned Op, unsigned RegOpcodeField) {
133 const MachineOperand &BaseReg = MI.getOperand(Op);
134 const MachineOperand &Scale = MI.getOperand(Op+1);
135 const MachineOperand &IndexReg = MI.getOperand(Op+2);
136 const MachineOperand &Disp = MI.getOperand(Op+3);
138 // Is a SIB byte needed?
139 if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
140 if (BaseReg.getReg() == 0) { // Just a displacement?
141 // Emit special case [disp32] encoding
142 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
143 emitConstant(Disp.getImmedValue(), 4);
145 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
146 if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
147 // Emit simple indirect register encoding... [EAX] f.e.
148 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
149 } else if (isDisp8(Disp.getImmedValue())) {
150 // Emit the disp8 encoding... [REG+disp8]
151 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
152 emitConstant(Disp.getImmedValue(), 1);
154 // Emit the most general non-SIB encoding: [REG+disp32]
155 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
156 emitConstant(Disp.getImmedValue(), 4);
160 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
161 assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
163 bool ForceDisp32 = false;
164 bool ForceDisp8 = false;
165 if (BaseReg.getReg() == 0) {
166 // If there is no base register, we emit the special case SIB byte with
167 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
168 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
170 } else if (Disp.getImmedValue() == 0 && BaseReg.getReg() != X86::EBP) {
171 // Emit no displacement ModR/M byte
172 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
173 } else if (isDisp8(Disp.getImmedValue())) {
174 // Emit the disp8 encoding...
175 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
176 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
178 // Emit the normal disp32 encoding...
179 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
182 // Calculate what the SS field value should be...
183 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
184 unsigned SS = SSTable[Scale.getImmedValue()];
186 if (BaseReg.getReg() == 0) {
187 // Handle the SIB byte for the case where there is no base. The
188 // displacement has already been output.
189 assert(IndexReg.getReg() && "Index register must be specified!");
190 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
192 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
193 unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
194 emitSIBByte(SS, IndexRegNo, BaseRegNo);
197 // Do we need to output a displacement?
198 if (Disp.getImmedValue() != 0 || ForceDisp32 || ForceDisp8) {
199 if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
200 emitConstant(Disp.getImmedValue(), 1);
202 emitConstant(Disp.getImmedValue(), 4);
207 unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
208 switch (Desc.TSFlags & X86II::ArgMask) {
209 case X86II::Arg8: return 1;
210 case X86II::Arg16: return 2;
211 case X86II::Arg32: return 4;
212 case X86II::Arg64: return 8;
213 case X86II::Arg80: return 10;
214 case X86II::Arg128: return 16;
215 default: assert(0 && "Memory size not set!");
221 void Emitter::emitInstruction(MachineInstr &MI) {
222 unsigned Opcode = MI.getOpcode();
223 const MachineInstrDescriptor &Desc = II.get(Opcode);
225 // Emit instruction prefixes if neccesary
226 if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
227 if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix
229 unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode);
230 switch (Desc.TSFlags & X86II::FormMask) {
232 MCE.emitByte(BaseOpcode);
234 if (MI.getNumOperands() == 1) {
235 assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp);
236 MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue());
239 case X86II::AddRegFrm:
240 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
241 if (MI.getNumOperands() == 2 && (MI.getOperand(1).isImmediate() ||
242 MI.getOperand(1).getVRegValueOrNull())) {
243 unsigned Size = sizeOfPtr(Desc);
244 if (Value *V = MI.getOperand(1).getVRegValueOrNull()) {
245 assert(Size == 4 && "Don't know how to emit non-pointer values!");
246 MCE.emitGlobalAddress(cast<GlobalValue>(V));
248 emitConstant(MI.getOperand(1).getImmedValue(), Size);
252 case X86II::MRMDestReg:
253 MCE.emitByte(BaseOpcode);
254 emitRegModRMByte(MI.getOperand(0).getReg(),
255 getX86RegNum(MI.getOperand(MI.getNumOperands()-1).getReg()));
257 case X86II::MRMDestMem:
258 MCE.emitByte(BaseOpcode);
259 emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
261 case X86II::MRMSrcReg:
262 MCE.emitByte(BaseOpcode);
263 emitRegModRMByte(MI.getOperand(MI.getNumOperands()-1).getReg(),
264 getX86RegNum(MI.getOperand(0).getReg()));
266 case X86II::MRMSrcMem:
267 MCE.emitByte(BaseOpcode);
268 emitMemModRMByte(MI, MI.getNumOperands()-4,
269 getX86RegNum(MI.getOperand(0).getReg()));
272 case X86II::MRMS0r: case X86II::MRMS1r:
273 case X86II::MRMS2r: case X86II::MRMS3r:
274 case X86II::MRMS4r: case X86II::MRMS5r:
275 case X86II::MRMS6r: case X86II::MRMS7r:
276 MCE.emitByte(BaseOpcode);
277 emitRegModRMByte(MI.getOperand(0).getReg(),
278 (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
280 if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
281 unsigned Size = sizeOfPtr(Desc);
282 emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);