1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX. For i8, the ABI
26 // requires the values to be in AL and AH, however this code uses AL and DL
27 // instead. This is because using AH for the second register conflicts with
28 // the way LLVM does multiple return values -- a return of {i16,i8} would end
29 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
30 // for functions that return two i8 values are currently expected to pack the
31 // values into an i16 (which uses AX, and thus AL:AH).
33 // For code that doesn't care about the ABI, we allow returning more than two
34 // integer values in registers.
35 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
36 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
37 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
38 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
40 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
41 // can only be used by ABI non-compliant code. If the target doesn't have XMM
42 // registers, it won't have vector types.
43 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
44 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
46 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
47 // can only be used by ABI non-compliant code. This vector type is only
48 // supported while using the AVX target feature.
49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
50 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
52 // MMX vector types are always returned in MM0. If the target doesn't have
53 // MM0, it doesn't support these vector types.
54 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
56 // Long double types are always returned in ST0 (even with SSE).
57 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
60 // X86-32 C return-value convention.
61 def RetCC_X86_32_C : CallingConv<[
62 // The X86-32 calling convention returns FP values in ST0, unless marked
63 // with "inreg" (used here to distinguish one kind of reg from another,
64 // weirdly; this is really the sse-regparm calling convention) in which
65 // case they use XMM0, otherwise it is the same as the common X86 calling
67 CCIfInReg<CCIfSubtarget<"hasSSE2()",
68 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
69 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
70 CCDelegateTo<RetCC_X86Common>
73 // X86-32 FastCC return-value convention.
74 def RetCC_X86_32_Fast : CallingConv<[
75 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
77 // This can happen when a float, 2 x float, or 3 x float vector is split by
78 // target lowering, and is returned in 1-3 sse regs.
79 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
80 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
82 // For integers, ECX can be used as an extra return register
83 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
84 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
85 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
87 // Otherwise, it is the same as the common X86 calling convention.
88 CCDelegateTo<RetCC_X86Common>
91 // Intel_OCL_BI return-value convention.
92 def RetCC_Intel_OCL_BI : CallingConv<[
93 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
94 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
95 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
98 // No more than 4 registers
99 CCIfType<[v8f32, v4f64, v8i32, v4i64],
100 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
102 // i32, i64 in the standard way
103 CCDelegateTo<RetCC_X86Common>
106 // X86-32 HiPE return-value convention.
107 def RetCC_X86_32_HiPE : CallingConv<[
108 // Promote all types to i32
109 CCIfType<[i8, i16], CCPromoteToType<i32>>,
111 // Return: HP, P, VAL1, VAL2
112 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
115 // X86-64 C return-value convention.
116 def RetCC_X86_64_C : CallingConv<[
117 // The X86-64 calling convention always returns FP values in XMM0.
118 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
119 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
121 // MMX vector types are always returned in XMM0.
122 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
123 CCDelegateTo<RetCC_X86Common>
126 // X86-Win64 C return-value convention.
127 def RetCC_X86_Win64_C : CallingConv<[
128 // The X86-Win64 calling convention always returns __m64 values in RAX.
129 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
131 // Otherwise, everything is the same as 'normal' X86-64 C CC.
132 CCDelegateTo<RetCC_X86_64_C>
135 // X86-64 HiPE return-value convention.
136 def RetCC_X86_64_HiPE : CallingConv<[
137 // Promote all types to i64
138 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
140 // Return: HP, P, VAL1, VAL2
141 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
144 // This is the root return-value convention for the X86-32 backend.
145 def RetCC_X86_32 : CallingConv<[
146 // If FastCC, use RetCC_X86_32_Fast.
147 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
148 // If HiPE, use RetCC_X86_32_HiPE.
149 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
151 // Otherwise, use RetCC_X86_32_C.
152 CCDelegateTo<RetCC_X86_32_C>
155 // This is the root return-value convention for the X86-64 backend.
156 def RetCC_X86_64 : CallingConv<[
157 // HiPE uses RetCC_X86_64_HiPE
158 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
160 // Handle explicit CC selection
161 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
162 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
164 // Mingw64 and native Win64 use Win64 CC
165 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
167 // Otherwise, drop to normal X86-64 CC
168 CCDelegateTo<RetCC_X86_64_C>
171 // This is the return-value convention used for the entire X86 backend.
172 def RetCC_X86 : CallingConv<[
174 // Check if this is the Intel OpenCL built-ins calling convention
175 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
177 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
178 CCDelegateTo<RetCC_X86_32>
181 //===----------------------------------------------------------------------===//
182 // X86-64 Argument Calling Conventions
183 //===----------------------------------------------------------------------===//
185 def CC_X86_64_C : CallingConv<[
186 // Handles byval parameters.
187 CCIfByVal<CCPassByVal<8, 8>>,
189 // Promote i8/i16 arguments to i32.
190 CCIfType<[i8, i16], CCPromoteToType<i32>>,
192 // The 'nest' parameter, if any, is passed in R10.
193 CCIfNest<CCAssignToReg<[R10]>>,
195 // The first 6 integer arguments are passed in integer registers.
196 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
197 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
199 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
201 CCIfSubtarget<"isTargetDarwin()",
202 CCIfSubtarget<"hasSSE2()",
203 CCPromoteToType<v2i64>>>>,
205 // The first 8 FP/Vector arguments are passed in XMM registers.
206 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
207 CCIfSubtarget<"hasSSE1()",
208 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
210 // The first 8 256-bit vector arguments are passed in YMM registers, unless
211 // this is a vararg function.
212 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
213 // fixed arguments to vararg functions are supposed to be passed in
214 // registers. Actually modeling that would be a lot of work, though.
215 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
216 CCIfSubtarget<"hasAVX()",
217 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
218 YMM4, YMM5, YMM6, YMM7]>>>>,
220 // Integer/FP values get stored in stack slots that are 8 bytes in size and
221 // 8-byte aligned if there are no more registers to hold them.
222 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
224 // Long doubles get stack slots whose size and alignment depends on the
226 CCIfType<[f80], CCAssignToStack<0, 0>>,
228 // Vectors get 16-byte stack slots that are 16-byte aligned.
229 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
231 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
232 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
233 CCAssignToStack<32, 32>>
236 // Calling convention used on Win64
237 def CC_X86_Win64_C : CallingConv<[
238 // FIXME: Handle byval stuff.
239 // FIXME: Handle varargs.
241 // Promote i8/i16 arguments to i32.
242 CCIfType<[i8, i16], CCPromoteToType<i32>>,
244 // The 'nest' parameter, if any, is passed in R10.
245 CCIfNest<CCAssignToReg<[R10]>>,
247 // 128 bit vectors are passed by pointer
248 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
251 // 256 bit vectors are passed by pointer
252 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
254 // The first 4 MMX vector arguments are passed in GPRs.
255 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
257 // The first 4 integer arguments are passed in integer registers.
258 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
259 [XMM0, XMM1, XMM2, XMM3]>>,
261 // Do not pass the sret argument in RCX, the Win64 thiscall calling
262 // convention requires "this" to be passed in RCX.
263 CCIfCC<"CallingConv::X86_ThisCall",
264 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
265 [XMM1, XMM2, XMM3]>>>>,
267 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
268 [XMM0, XMM1, XMM2, XMM3]>>,
270 // The first 4 FP/Vector arguments are passed in XMM registers.
271 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
272 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
273 [RCX , RDX , R8 , R9 ]>>,
275 // Integer/FP values get stored in stack slots that are 8 bytes in size and
276 // 8-byte aligned if there are no more registers to hold them.
277 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
279 // Long doubles get stack slots whose size and alignment depends on the
281 CCIfType<[f80], CCAssignToStack<0, 0>>
284 def CC_X86_64_GHC : CallingConv<[
285 // Promote i8/i16/i32 arguments to i64.
286 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
288 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
290 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
292 // Pass in STG registers: F1, F2, F3, F4, D1, D2
293 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
294 CCIfSubtarget<"hasSSE1()",
295 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
298 def CC_X86_64_HiPE : CallingConv<[
299 // Promote i8/i16/i32 arguments to i64.
300 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
302 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
303 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
305 // Integer/FP values get stored in stack slots that are 8 bytes in size and
306 // 8-byte aligned if there are no more registers to hold them.
307 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
310 //===----------------------------------------------------------------------===//
311 // X86 C Calling Convention
312 //===----------------------------------------------------------------------===//
314 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
315 /// values are spilled on the stack, and the first 4 vector values go in XMM
317 def CC_X86_32_Common : CallingConv<[
318 // Handles byval parameters.
319 CCIfByVal<CCPassByVal<4, 4>>,
321 // The first 3 float or double arguments, if marked 'inreg' and if the call
322 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
323 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
324 CCIfSubtarget<"hasSSE2()",
325 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
327 // The first 3 __m64 vector arguments are passed in mmx registers if the
328 // call is not a vararg call.
329 CCIfNotVarArg<CCIfType<[x86mmx],
330 CCAssignToReg<[MM0, MM1, MM2]>>>,
332 // Integer/Float values get stored in stack slots that are 4 bytes in
333 // size and 4-byte aligned.
334 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
336 // Doubles get 8-byte slots that are 4-byte aligned.
337 CCIfType<[f64], CCAssignToStack<8, 4>>,
339 // Long doubles get slots whose size depends on the subtarget.
340 CCIfType<[f80], CCAssignToStack<0, 4>>,
342 // The first 4 SSE vector arguments are passed in XMM registers.
343 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
344 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
346 // The first 4 AVX 256-bit vector arguments are passed in YMM registers.
347 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
348 CCIfSubtarget<"hasAVX()",
349 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
351 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
352 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
354 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
355 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
356 CCAssignToStack<32, 32>>,
358 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
359 // passed in the parameter area.
360 CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
362 def CC_X86_32_C : CallingConv<[
363 // Promote i8/i16 arguments to i32.
364 CCIfType<[i8, i16], CCPromoteToType<i32>>,
366 // The 'nest' parameter, if any, is passed in ECX.
367 CCIfNest<CCAssignToReg<[ECX]>>,
369 // The first 3 integer arguments, if marked 'inreg' and if the call is not
370 // a vararg call, are passed in integer registers.
371 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
373 // Otherwise, same as everything else.
374 CCDelegateTo<CC_X86_32_Common>
377 def CC_X86_32_FastCall : CallingConv<[
378 // Promote i8/i16 arguments to i32.
379 CCIfType<[i8, i16], CCPromoteToType<i32>>,
381 // The 'nest' parameter, if any, is passed in EAX.
382 CCIfNest<CCAssignToReg<[EAX]>>,
384 // The first 2 integer arguments are passed in ECX/EDX
385 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
387 // Otherwise, same as everything else.
388 CCDelegateTo<CC_X86_32_Common>
391 def CC_X86_32_ThisCall : CallingConv<[
392 // Promote i8/i16 arguments to i32.
393 CCIfType<[i8, i16], CCPromoteToType<i32>>,
395 // Pass sret arguments indirectly through stack.
396 CCIfSRet<CCAssignToStack<4, 4>>,
398 // The first integer argument is passed in ECX
399 CCIfType<[i32], CCAssignToReg<[ECX]>>,
401 // Otherwise, same as everything else.
402 CCDelegateTo<CC_X86_32_Common>
405 def CC_X86_32_FastCC : CallingConv<[
406 // Handles byval parameters. Note that we can't rely on the delegation
407 // to CC_X86_32_Common for this because that happens after code that
408 // puts arguments in registers.
409 CCIfByVal<CCPassByVal<4, 4>>,
411 // Promote i8/i16 arguments to i32.
412 CCIfType<[i8, i16], CCPromoteToType<i32>>,
414 // The 'nest' parameter, if any, is passed in EAX.
415 CCIfNest<CCAssignToReg<[EAX]>>,
417 // The first 2 integer arguments are passed in ECX/EDX
418 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
420 // The first 3 float or double arguments, if the call is not a vararg
421 // call and if SSE2 is available, are passed in SSE registers.
422 CCIfNotVarArg<CCIfType<[f32,f64],
423 CCIfSubtarget<"hasSSE2()",
424 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
426 // Doubles get 8-byte slots that are 8-byte aligned.
427 CCIfType<[f64], CCAssignToStack<8, 8>>,
429 // Otherwise, same as everything else.
430 CCDelegateTo<CC_X86_32_Common>
433 def CC_X86_32_GHC : CallingConv<[
434 // Promote i8/i16 arguments to i32.
435 CCIfType<[i8, i16], CCPromoteToType<i32>>,
437 // Pass in STG registers: Base, Sp, Hp, R1
438 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
441 def CC_X86_32_HiPE : CallingConv<[
442 // Promote i8/i16 arguments to i32.
443 CCIfType<[i8, i16], CCPromoteToType<i32>>,
445 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
446 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
448 // Integer/Float values get stored in stack slots that are 4 bytes in
449 // size and 4-byte aligned.
450 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
453 // X86-64 Intel OpenCL built-ins calling convention.
454 def CC_Intel_OCL_BI : CallingConv<[
456 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
457 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
459 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
460 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
462 CCIfType<[i32], CCAssignToStack<4, 4>>,
464 // The SSE vector arguments are passed in XMM registers.
465 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
466 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
468 // The 256-bit vector arguments are passed in YMM registers.
469 CCIfType<[v8f32, v4f64, v8i32, v4i64],
470 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
472 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
473 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
474 CCDelegateTo<CC_X86_32_C>
477 //===----------------------------------------------------------------------===//
478 // X86 Root Argument Calling Conventions
479 //===----------------------------------------------------------------------===//
481 // This is the root argument convention for the X86-32 backend.
482 def CC_X86_32 : CallingConv<[
483 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
484 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
485 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
486 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
487 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
489 // Otherwise, drop to normal X86-32 CC
490 CCDelegateTo<CC_X86_32_C>
493 // This is the root argument convention for the X86-64 backend.
494 def CC_X86_64 : CallingConv<[
495 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
496 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
497 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
498 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
500 // Mingw64 and native Win64 use Win64 CC
501 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
503 // Otherwise, drop to normal X86-64 CC
504 CCDelegateTo<CC_X86_64_C>
507 // This is the argument convention used for the entire X86 backend.
508 def CC_X86 : CallingConv<[
509 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
510 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
511 CCDelegateTo<CC_X86_32>
514 //===----------------------------------------------------------------------===//
515 // Callee-saved Registers.
516 //===----------------------------------------------------------------------===//
518 def CSR_NoRegs : CalleeSavedRegs<(add)>;
520 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
521 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
523 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
524 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
526 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
527 (sequence "XMM%u", 6, 15))>;
529 def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
530 R11, R12, R13, R14, R15, RBP,
531 (sequence "XMM%u", 0, 15))>;
533 // Standard C + YMM6-15
534 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
536 (sequence "YMM%u", 6, 15))>;
538 //Standard C + XMM 8-15
539 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
540 (sequence "XMM%u", 8, 15))>;
542 //Standard C + YMM 8-15
543 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
544 (sequence "YMM%u", 8, 15))>;