1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "X86MCAsmInfo.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "InstPrinter/X86IntelInstPrinter.h"
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Support/Host.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
30 #define GET_REGINFO_MC_DESC
31 #include "X86GenRegisterInfo.inc"
33 #define GET_INSTRINFO_MC_DESC
34 #include "X86GenInstrInfo.inc"
36 #define GET_SUBTARGETINFO_MC_DESC
37 #include "X86GenSubtargetInfo.inc"
42 std::string X86_MC::ParseX86Triple(StringRef TT) {
45 if (TheTriple.getArch() == Triple::x86_64)
52 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
53 /// specified arguments. If we can't run cpuid on the host, return true.
54 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
55 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
56 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
58 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
59 asm ("movq\t%%rbx, %%rsi\n\t"
61 "xchgq\t%%rbx, %%rsi\n\t"
68 #elif defined(_MSC_VER)
70 __cpuid(registers, value);
79 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
81 asm ("movl\t%%ebx, %%esi\n\t"
83 "xchgl\t%%ebx, %%esi\n\t"
90 #elif defined(_MSC_VER)
95 mov dword ptr [esi],eax
97 mov dword ptr [esi],ebx
99 mov dword ptr [esi],ecx
101 mov dword ptr [esi],edx
112 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
113 /// 4 values in the specified arguments. If we can't run cpuid on the host,
115 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
116 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
117 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
118 #if defined(__GNUC__)
119 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
120 asm ("movq\t%%rbx, %%rsi\n\t"
122 "xchgq\t%%rbx, %%rsi\n\t"
130 #elif defined(_MSC_VER)
131 // __cpuidex was added in MSVC++ 9.0 SP1
132 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
134 __cpuidex(registers, value, subleaf);
135 *rEAX = registers[0];
136 *rEBX = registers[1];
137 *rECX = registers[2];
138 *rEDX = registers[3];
146 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
147 #if defined(__GNUC__)
148 asm ("movl\t%%ebx, %%esi\n\t"
150 "xchgl\t%%ebx, %%esi\n\t"
158 #elif defined(_MSC_VER)
164 mov dword ptr [esi],eax
166 mov dword ptr [esi],ebx
168 mov dword ptr [esi],ecx
170 mov dword ptr [esi],edx
181 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
183 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
184 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
185 if (Family == 6 || Family == 0xf) {
187 // Examine extended family ID if family ID is F.
188 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
189 // Examine extended model ID if family ID is 6 or F.
190 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
194 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
195 Triple TheTriple(TT);
196 if (TheTriple.getArch() == Triple::x86_64)
197 return DWARFFlavour::X86_64;
199 if (TheTriple.isOSDarwin())
200 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
201 if (TheTriple.getOS() == Triple::MinGW32 ||
202 TheTriple.getOS() == Triple::Cygwin)
203 // Unsupported by now, just quick fallback
204 return DWARFFlavour::X86_32_Generic;
205 return DWARFFlavour::X86_32_Generic;
208 /// getX86RegNum - This function maps LLVM register identifiers to their X86
209 /// specific numbering, which is used in various places encoding instructions.
210 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
212 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
213 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
214 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
215 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
216 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
218 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
220 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
222 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
225 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
227 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
229 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
231 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
233 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
235 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
237 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
239 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
242 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
243 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
244 return RegNo-X86::ST0;
246 case X86::XMM0: case X86::XMM8:
247 case X86::YMM0: case X86::YMM8: case X86::MM0:
249 case X86::XMM1: case X86::XMM9:
250 case X86::YMM1: case X86::YMM9: case X86::MM1:
252 case X86::XMM2: case X86::XMM10:
253 case X86::YMM2: case X86::YMM10: case X86::MM2:
255 case X86::XMM3: case X86::XMM11:
256 case X86::YMM3: case X86::YMM11: case X86::MM3:
258 case X86::XMM4: case X86::XMM12:
259 case X86::YMM4: case X86::YMM12: case X86::MM4:
261 case X86::XMM5: case X86::XMM13:
262 case X86::YMM5: case X86::YMM13: case X86::MM5:
264 case X86::XMM6: case X86::XMM14:
265 case X86::YMM6: case X86::YMM14: case X86::MM6:
267 case X86::XMM7: case X86::XMM15:
268 case X86::YMM7: case X86::YMM15: case X86::MM7:
271 case X86::ES: return 0;
272 case X86::CS: return 1;
273 case X86::SS: return 2;
274 case X86::DS: return 3;
275 case X86::FS: return 4;
276 case X86::GS: return 5;
278 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
279 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
280 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
281 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
282 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
283 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
284 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
285 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
287 // Pseudo index registers are equivalent to a "none"
288 // scaled index (See Intel Manual 2A, table 2-3)
294 assert((int(RegNo) > 0) && "Unknown physical register!");
299 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
300 // FIXME: TableGen these.
301 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
302 int SEH = X86_MC::getX86RegNum(Reg);
304 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
305 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
306 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
307 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
308 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
309 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
310 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
311 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
312 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
313 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
314 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
315 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
319 MRI->mapLLVMRegToSEHReg(Reg, SEH);
323 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
325 std::string ArchFS = X86_MC::ParseX86Triple(TT);
328 ArchFS = ArchFS + "," + FS.str();
333 std::string CPUName = CPU;
334 if (CPUName.empty()) {
335 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
336 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
337 CPUName = sys::getHostCPUName();
343 MCSubtargetInfo *X = new MCSubtargetInfo();
344 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
348 static MCInstrInfo *createX86MCInstrInfo() {
349 MCInstrInfo *X = new MCInstrInfo();
350 InitX86MCInstrInfo(X);
354 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
355 Triple TheTriple(TT);
356 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
357 ? X86::RIP // Should have dwarf #16.
358 : X86::EIP; // Should have dwarf #8.
360 MCRegisterInfo *X = new MCRegisterInfo();
361 InitX86MCRegisterInfo(X, RA,
362 X86_MC::getDwarfRegFlavour(TT, false),
363 X86_MC::getDwarfRegFlavour(TT, true));
364 X86_MC::InitLLVM2SEHRegisterMapping(X);
368 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
369 Triple TheTriple(TT);
370 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
373 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
375 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
377 MAI = new X86MCAsmInfoDarwin(TheTriple);
378 } else if (TheTriple.getOS() == Triple::Win32) {
379 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
380 } else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) {
381 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
383 MAI = new X86ELFMCAsmInfo(TheTriple);
386 // Initialize initial frame state.
387 // Calculate amount of bytes used for return address storing
388 int stackGrowth = is64Bit ? -8 : -4;
390 // Initial state of the frame pointer is esp+stackGrowth.
391 MachineLocation Dst(MachineLocation::VirtualFP);
392 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
393 MAI->addInitialFrameState(0, Dst, Src);
395 // Add return address to move list
396 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
397 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
398 MAI->addInitialFrameState(0, CSDst, CSSrc);
403 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
405 CodeGenOpt::Level OL) {
406 MCCodeGenInfo *X = new MCCodeGenInfo();
409 bool is64Bit = T.getArch() == Triple::x86_64;
411 if (RM == Reloc::Default) {
412 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
413 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
414 // use static relocation model by default.
415 if (T.isOSDarwin()) {
419 RM = Reloc::DynamicNoPIC;
420 } else if (T.isOSWindows() && is64Bit)
426 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
427 // is defined as a model for code which may be used in static or dynamic
428 // executables but not necessarily a shared library. On X86-32 we just
429 // compile in -static mode, in x86-64 we use PIC.
430 if (RM == Reloc::DynamicNoPIC) {
433 else if (!T.isOSDarwin())
437 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
438 // the Mach-O file format doesn't support it.
439 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
442 // For static codegen, if we're not already set, use Small codegen.
443 if (CM == CodeModel::Default)
444 CM = CodeModel::Small;
445 else if (CM == CodeModel::JITDefault)
446 // 64-bit JIT places everything in the same buffer except external funcs.
447 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
449 X->InitMCCodeGenInfo(RM, CM, OL);
453 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
454 MCContext &Ctx, MCAsmBackend &MAB,
456 MCCodeEmitter *_Emitter,
459 Triple TheTriple(TT);
461 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
462 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
464 if (TheTriple.isOSWindows())
465 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
467 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
470 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
471 unsigned SyntaxVariant,
472 const MCAsmInfo &MAI,
473 const MCSubtargetInfo &STI) {
474 if (SyntaxVariant == 0)
475 return new X86ATTInstPrinter(MAI);
476 if (SyntaxVariant == 1)
477 return new X86IntelInstPrinter(MAI);
481 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
482 return new MCInstrAnalysis(Info);
485 // Force static initialization.
486 extern "C" void LLVMInitializeX86TargetMC() {
487 // Register the MC asm info.
488 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
489 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
491 // Register the MC codegen info.
492 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
493 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
495 // Register the MC instruction info.
496 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
497 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
499 // Register the MC register info.
500 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
501 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
503 // Register the MC subtarget info.
504 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
505 X86_MC::createX86MCSubtargetInfo);
506 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
507 X86_MC::createX86MCSubtargetInfo);
509 // Register the MC instruction analyzer.
510 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
511 createX86MCInstrAnalysis);
512 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
513 createX86MCInstrAnalysis);
515 // Register the code emitter.
516 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
517 createX86MCCodeEmitter);
518 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
519 createX86MCCodeEmitter);
521 // Register the asm backend.
522 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
523 createX86_32AsmBackend);
524 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
525 createX86_64AsmBackend);
527 // Register the object streamer.
528 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
530 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
533 // Register the MCInstPrinter.
534 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
535 createX86MCInstPrinter);
536 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
537 createX86MCInstPrinter);