1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
13 //===----------------------------------------------------------------------===//
15 #include "X86InstComments.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/CodeGen/MachineValueType.h"
20 #include "llvm/Support/raw_ostream.h"
24 static unsigned getVectorRegSize(unsigned RegNo) {
25 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
27 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
29 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
31 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
34 llvm_unreachable("Unknown vector reg!");
38 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
39 unsigned OperandIndex) {
40 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
41 return MVT::getVectorVT(ScalarVT,
42 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
45 /// \brief Extracts the src/dst types for a given zero extension instruction.
46 /// \note While the number of elements in DstVT type correct, the
47 /// number in the SrcVT type is expanded to fill the src xmm register and the
48 /// upper elements may not be included in the dst xmm/ymm register.
49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
50 switch (MI->getOpcode()) {
52 llvm_unreachable("Unknown zero extension instruction");
56 case X86::VPMOVZXBWrm:
57 case X86::VPMOVZXBWrr:
61 case X86::VPMOVZXBWYrm:
62 case X86::VPMOVZXBWYrr:
68 case X86::VPMOVZXBDrm:
69 case X86::VPMOVZXBDrr:
73 case X86::VPMOVZXBDYrm:
74 case X86::VPMOVZXBDYrr:
80 case X86::VPMOVZXBQrm:
81 case X86::VPMOVZXBQrr:
85 case X86::VPMOVZXBQYrm:
86 case X86::VPMOVZXBQYrr:
93 case X86::VPMOVZXWDrm:
94 case X86::VPMOVZXWDrr:
98 case X86::VPMOVZXWDYrm:
99 case X86::VPMOVZXWDYrr:
103 case X86::PMOVZXWQrm:
104 case X86::PMOVZXWQrr:
105 case X86::VPMOVZXWQrm:
106 case X86::VPMOVZXWQrr:
110 case X86::VPMOVZXWQYrm:
111 case X86::VPMOVZXWQYrr:
115 // i32 zero extension
116 case X86::PMOVZXDQrm:
117 case X86::PMOVZXDQrr:
118 case X86::VPMOVZXDQrm:
119 case X86::VPMOVZXDQrr:
123 case X86::VPMOVZXDQYrm:
124 case X86::VPMOVZXDQYrr:
131 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
132 case X86::V##Inst##Suffix##src: \
133 case X86::V##Inst##Suffix##src##k: \
134 case X86::V##Inst##Suffix##src##kz:
136 #define CASE_SSE_INS_COMMON(Inst, src) \
139 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
140 case X86::V##Inst##Suffix##src:
142 #define CASE_MOVDUP(Inst, src) \
143 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
144 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
145 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
146 CASE_AVX_INS_COMMON(Inst, , r##src) \
147 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
148 CASE_SSE_INS_COMMON(Inst, r##src) \
150 #define CASE_UNPCK(Inst, src) \
151 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
152 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
153 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
154 CASE_AVX_INS_COMMON(Inst, , r##src) \
155 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
156 CASE_SSE_INS_COMMON(Inst, r##src) \
158 #define CASE_VSHUF(Inst, src) \
159 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
160 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
161 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
162 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \
164 /// \brief Extracts the types and if it has memory operand for a given
165 /// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
166 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
168 switch (MI->getOpcode()) {
170 llvm_unreachable("Unknown VSHUF64x2 family instructions.");
173 HasMemOp = true; // FALL THROUGH.
175 VT = getRegOperandVectorVT(MI, MVT::i64, 0);
178 HasMemOp = true; // FALL THROUGH.
180 VT = getRegOperandVectorVT(MI, MVT::i32, 0);
185 //===----------------------------------------------------------------------===//
186 // Top Level Entrypoint
187 //===----------------------------------------------------------------------===//
189 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
190 /// newline terminated strings to the specified string if desired. This
191 /// information is shown in disassembly dumps when verbose assembly is enabled.
192 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
193 const char *(*getRegName)(unsigned)) {
194 // If this is a shuffle operation, the switch should fill in this state.
195 SmallVector<int, 8> ShuffleMask;
196 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
198 switch (MI->getOpcode()) {
200 // Not an instruction for which we can decode comments.
203 case X86::BLENDPDrri:
204 case X86::VBLENDPDrri:
205 case X86::VBLENDPDYrri:
206 Src2Name = getRegName(MI->getOperand(2).getReg());
208 case X86::BLENDPDrmi:
209 case X86::VBLENDPDrmi:
210 case X86::VBLENDPDYrmi:
211 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
212 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
213 MI->getOperand(MI->getNumOperands() - 1).getImm(),
215 Src1Name = getRegName(MI->getOperand(1).getReg());
216 DestName = getRegName(MI->getOperand(0).getReg());
219 case X86::BLENDPSrri:
220 case X86::VBLENDPSrri:
221 case X86::VBLENDPSYrri:
222 Src2Name = getRegName(MI->getOperand(2).getReg());
224 case X86::BLENDPSrmi:
225 case X86::VBLENDPSrmi:
226 case X86::VBLENDPSYrmi:
227 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
228 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
229 MI->getOperand(MI->getNumOperands() - 1).getImm(),
231 Src1Name = getRegName(MI->getOperand(1).getReg());
232 DestName = getRegName(MI->getOperand(0).getReg());
235 case X86::PBLENDWrri:
236 case X86::VPBLENDWrri:
237 case X86::VPBLENDWYrri:
238 Src2Name = getRegName(MI->getOperand(2).getReg());
240 case X86::PBLENDWrmi:
241 case X86::VPBLENDWrmi:
242 case X86::VPBLENDWYrmi:
243 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
244 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
245 MI->getOperand(MI->getNumOperands() - 1).getImm(),
247 Src1Name = getRegName(MI->getOperand(1).getReg());
248 DestName = getRegName(MI->getOperand(0).getReg());
251 case X86::VPBLENDDrri:
252 case X86::VPBLENDDYrri:
253 Src2Name = getRegName(MI->getOperand(2).getReg());
255 case X86::VPBLENDDrmi:
256 case X86::VPBLENDDYrmi:
257 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
258 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
259 MI->getOperand(MI->getNumOperands() - 1).getImm(),
261 Src1Name = getRegName(MI->getOperand(1).getReg());
262 DestName = getRegName(MI->getOperand(0).getReg());
265 case X86::INSERTPSrr:
266 case X86::VINSERTPSrr:
267 Src2Name = getRegName(MI->getOperand(2).getReg());
269 case X86::INSERTPSrm:
270 case X86::VINSERTPSrm:
271 DestName = getRegName(MI->getOperand(0).getReg());
272 Src1Name = getRegName(MI->getOperand(1).getReg());
273 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
274 DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
279 case X86::VMOVLHPSrr:
280 Src2Name = getRegName(MI->getOperand(2).getReg());
281 Src1Name = getRegName(MI->getOperand(1).getReg());
282 DestName = getRegName(MI->getOperand(0).getReg());
283 DecodeMOVLHPSMask(2, ShuffleMask);
287 case X86::VMOVHLPSrr:
288 Src2Name = getRegName(MI->getOperand(2).getReg());
289 Src1Name = getRegName(MI->getOperand(1).getReg());
290 DestName = getRegName(MI->getOperand(0).getReg());
291 DecodeMOVHLPSMask(2, ShuffleMask);
294 CASE_MOVDUP(MOVSLDUP, r)
295 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
297 CASE_MOVDUP(MOVSLDUP, m) {
298 MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
299 DestName = getRegName(MI->getOperand(0).getReg());
300 DecodeMOVSLDUPMask(VT, ShuffleMask);
304 CASE_MOVDUP(MOVSHDUP, r)
305 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
307 CASE_MOVDUP(MOVSHDUP, m) {
308 MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
309 DestName = getRegName(MI->getOperand(0).getReg());
310 DecodeMOVSHDUPMask(VT, ShuffleMask);
314 case X86::VMOVDDUPYrr:
315 Src1Name = getRegName(MI->getOperand(1).getReg());
317 case X86::VMOVDDUPYrm:
318 DestName = getRegName(MI->getOperand(0).getReg());
319 DecodeMOVDDUPMask(MVT::v4f64, ShuffleMask);
323 case X86::VMOVDDUPrr:
324 Src1Name = getRegName(MI->getOperand(1).getReg());
327 case X86::VMOVDDUPrm:
328 DestName = getRegName(MI->getOperand(0).getReg());
329 DecodeMOVDDUPMask(MVT::v2f64, ShuffleMask);
334 case X86::VPSLLDQYri:
335 Src1Name = getRegName(MI->getOperand(1).getReg());
336 DestName = getRegName(MI->getOperand(0).getReg());
337 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
338 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
339 MI->getOperand(MI->getNumOperands() - 1).getImm(),
345 case X86::VPSRLDQYri:
346 Src1Name = getRegName(MI->getOperand(1).getReg());
347 DestName = getRegName(MI->getOperand(0).getReg());
348 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
349 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
350 MI->getOperand(MI->getNumOperands() - 1).getImm(),
354 case X86::PALIGNR128rr:
355 case X86::VPALIGNR128rr:
356 case X86::VPALIGNR256rr:
357 Src1Name = getRegName(MI->getOperand(2).getReg());
359 case X86::PALIGNR128rm:
360 case X86::VPALIGNR128rm:
361 case X86::VPALIGNR256rm:
362 Src2Name = getRegName(MI->getOperand(1).getReg());
363 DestName = getRegName(MI->getOperand(0).getReg());
364 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
365 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
366 MI->getOperand(MI->getNumOperands() - 1).getImm(),
372 case X86::VPSHUFDYri:
373 Src1Name = getRegName(MI->getOperand(1).getReg());
377 case X86::VPSHUFDYmi:
378 DestName = getRegName(MI->getOperand(0).getReg());
379 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
380 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
381 MI->getOperand(MI->getNumOperands() - 1).getImm(),
386 case X86::VPSHUFHWri:
387 case X86::VPSHUFHWYri:
388 Src1Name = getRegName(MI->getOperand(1).getReg());
391 case X86::VPSHUFHWmi:
392 case X86::VPSHUFHWYmi:
393 DestName = getRegName(MI->getOperand(0).getReg());
394 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
395 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
396 MI->getOperand(MI->getNumOperands() - 1).getImm(),
401 case X86::VPSHUFLWri:
402 case X86::VPSHUFLWYri:
403 Src1Name = getRegName(MI->getOperand(1).getReg());
406 case X86::VPSHUFLWmi:
407 case X86::VPSHUFLWYmi:
408 DestName = getRegName(MI->getOperand(0).getReg());
409 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
410 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
411 MI->getOperand(MI->getNumOperands() - 1).getImm(),
415 case X86::MMX_PSHUFWri:
416 Src1Name = getRegName(MI->getOperand(1).getReg());
418 case X86::MMX_PSHUFWmi:
419 DestName = getRegName(MI->getOperand(0).getReg());
420 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
421 DecodePSHUFMask(MVT::v4i16,
422 MI->getOperand(MI->getNumOperands() - 1).getImm(),
427 Src1Name = getRegName(MI->getOperand(1).getReg());
430 DestName = getRegName(MI->getOperand(0).getReg());
431 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
434 CASE_UNPCK(PUNPCKHBW, r)
435 case X86::MMX_PUNPCKHBWirr:
436 Src2Name = getRegName(MI->getOperand(2).getReg());
438 CASE_UNPCK(PUNPCKHBW, m)
439 case X86::MMX_PUNPCKHBWirm:
440 Src1Name = getRegName(MI->getOperand(1).getReg());
441 DestName = getRegName(MI->getOperand(0).getReg());
442 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
445 CASE_UNPCK(PUNPCKHWD, r)
446 case X86::MMX_PUNPCKHWDirr:
447 Src2Name = getRegName(MI->getOperand(2).getReg());
449 CASE_UNPCK(PUNPCKHWD, m)
450 case X86::MMX_PUNPCKHWDirm:
451 Src1Name = getRegName(MI->getOperand(1).getReg());
452 DestName = getRegName(MI->getOperand(0).getReg());
453 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
456 CASE_UNPCK(PUNPCKHDQ, r)
457 case X86::MMX_PUNPCKHDQirr:
458 Src2Name = getRegName(MI->getOperand(2).getReg());
460 CASE_UNPCK(PUNPCKHDQ, m)
461 case X86::MMX_PUNPCKHDQirm:
462 Src1Name = getRegName(MI->getOperand(1).getReg());
463 DestName = getRegName(MI->getOperand(0).getReg());
464 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
467 CASE_UNPCK(PUNPCKHQDQ, r)
468 Src2Name = getRegName(MI->getOperand(2).getReg());
470 CASE_UNPCK(PUNPCKHQDQ, m)
471 Src1Name = getRegName(MI->getOperand(1).getReg());
472 DestName = getRegName(MI->getOperand(0).getReg());
473 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
476 CASE_UNPCK(PUNPCKLBW, r)
477 case X86::MMX_PUNPCKLBWirr:
478 Src2Name = getRegName(MI->getOperand(2).getReg());
480 CASE_UNPCK(PUNPCKLBW, m)
481 case X86::MMX_PUNPCKLBWirm:
482 Src1Name = getRegName(MI->getOperand(1).getReg());
483 DestName = getRegName(MI->getOperand(0).getReg());
484 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
487 CASE_UNPCK(PUNPCKLWD, r)
488 case X86::MMX_PUNPCKLWDirr:
489 Src2Name = getRegName(MI->getOperand(2).getReg());
491 CASE_UNPCK(PUNPCKLWD, m)
492 case X86::MMX_PUNPCKLWDirm:
493 Src1Name = getRegName(MI->getOperand(1).getReg());
494 DestName = getRegName(MI->getOperand(0).getReg());
495 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
498 CASE_UNPCK(PUNPCKLDQ, r)
499 case X86::MMX_PUNPCKLDQirr:
500 Src2Name = getRegName(MI->getOperand(2).getReg());
502 CASE_UNPCK(PUNPCKLDQ, m)
503 case X86::MMX_PUNPCKLDQirm:
504 Src1Name = getRegName(MI->getOperand(1).getReg());
505 DestName = getRegName(MI->getOperand(0).getReg());
506 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
509 CASE_UNPCK(PUNPCKLQDQ, r)
510 Src2Name = getRegName(MI->getOperand(2).getReg());
512 CASE_UNPCK(PUNPCKLQDQ, m)
513 Src1Name = getRegName(MI->getOperand(1).getReg());
514 DestName = getRegName(MI->getOperand(0).getReg());
515 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
519 case X86::VSHUFPDrri:
520 case X86::VSHUFPDYrri:
521 Src2Name = getRegName(MI->getOperand(2).getReg());
524 case X86::VSHUFPDrmi:
525 case X86::VSHUFPDYrmi:
526 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
527 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
528 MI->getOperand(MI->getNumOperands() - 1).getImm(),
530 Src1Name = getRegName(MI->getOperand(1).getReg());
531 DestName = getRegName(MI->getOperand(0).getReg());
535 case X86::VSHUFPSrri:
536 case X86::VSHUFPSYrri:
537 Src2Name = getRegName(MI->getOperand(2).getReg());
540 case X86::VSHUFPSrmi:
541 case X86::VSHUFPSYrmi:
542 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
543 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
544 MI->getOperand(MI->getNumOperands() - 1).getImm(),
546 Src1Name = getRegName(MI->getOperand(1).getReg());
547 DestName = getRegName(MI->getOperand(0).getReg());
553 CASE_VSHUF(32X4, m) {
556 unsigned NumOp = MI->getNumOperands();
557 getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
558 decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
560 DestName = getRegName(MI->getOperand(0).getReg());
562 assert((NumOp >= 8) && "Expected at least 8 operands!");
563 Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
565 assert((NumOp >= 4) && "Expected at least 4 operands!");
566 Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
567 Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
572 CASE_UNPCK(UNPCKLPD, r)
573 Src2Name = getRegName(MI->getOperand(2).getReg());
575 CASE_UNPCK(UNPCKLPD, m)
576 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
577 Src1Name = getRegName(MI->getOperand(1).getReg());
578 DestName = getRegName(MI->getOperand(0).getReg());
581 CASE_UNPCK(UNPCKLPS, r)
582 Src2Name = getRegName(MI->getOperand(2).getReg());
584 CASE_UNPCK(UNPCKLPS, m)
585 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
586 Src1Name = getRegName(MI->getOperand(1).getReg());
587 DestName = getRegName(MI->getOperand(0).getReg());
590 CASE_UNPCK(UNPCKHPD, r)
591 Src2Name = getRegName(MI->getOperand(2).getReg());
593 CASE_UNPCK(UNPCKHPD, m)
594 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
595 Src1Name = getRegName(MI->getOperand(1).getReg());
596 DestName = getRegName(MI->getOperand(0).getReg());
599 CASE_UNPCK(UNPCKHPS, r)
600 Src2Name = getRegName(MI->getOperand(2).getReg());
602 CASE_UNPCK(UNPCKHPS, m)
603 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
604 Src1Name = getRegName(MI->getOperand(1).getReg());
605 DestName = getRegName(MI->getOperand(0).getReg());
608 case X86::VPERMILPSri:
609 case X86::VPERMILPSYri:
610 Src1Name = getRegName(MI->getOperand(1).getReg());
612 case X86::VPERMILPSmi:
613 case X86::VPERMILPSYmi:
614 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
615 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
616 MI->getOperand(MI->getNumOperands() - 1).getImm(),
618 DestName = getRegName(MI->getOperand(0).getReg());
621 case X86::VPERMILPDri:
622 case X86::VPERMILPDYri:
623 Src1Name = getRegName(MI->getOperand(1).getReg());
625 case X86::VPERMILPDmi:
626 case X86::VPERMILPDYmi:
627 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
628 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
629 MI->getOperand(MI->getNumOperands() - 1).getImm(),
631 DestName = getRegName(MI->getOperand(0).getReg());
634 case X86::VPERM2F128rr:
635 case X86::VPERM2I128rr:
636 Src2Name = getRegName(MI->getOperand(2).getReg());
638 case X86::VPERM2F128rm:
639 case X86::VPERM2I128rm:
640 // For instruction comments purpose, assume the 256-bit vector is v4i64.
641 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
642 DecodeVPERM2X128Mask(MVT::v4i64,
643 MI->getOperand(MI->getNumOperands() - 1).getImm(),
645 Src1Name = getRegName(MI->getOperand(1).getReg());
646 DestName = getRegName(MI->getOperand(0).getReg());
650 case X86::VPERMPDYri:
651 Src1Name = getRegName(MI->getOperand(1).getReg());
654 case X86::VPERMPDYmi:
655 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
656 DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
658 DestName = getRegName(MI->getOperand(0).getReg());
663 Src2Name = getRegName(MI->getOperand(2).getReg());
664 Src1Name = getRegName(MI->getOperand(1).getReg());
668 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
669 DestName = getRegName(MI->getOperand(0).getReg());
673 Src2Name = getRegName(MI->getOperand(2).getReg());
674 Src1Name = getRegName(MI->getOperand(1).getReg());
678 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
679 DestName = getRegName(MI->getOperand(0).getReg());
682 case X86::MOVPQI2QIrr:
683 case X86::MOVZPQILo2PQIrr:
684 case X86::VMOVPQI2QIrr:
685 case X86::VMOVZPQILo2PQIrr:
686 Src1Name = getRegName(MI->getOperand(1).getReg());
688 case X86::MOVQI2PQIrm:
689 case X86::MOVZQI2PQIrm:
690 case X86::MOVZPQILo2PQIrm:
691 case X86::VMOVQI2PQIrm:
692 case X86::VMOVZQI2PQIrm:
693 case X86::VMOVZPQILo2PQIrm:
694 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
695 DestName = getRegName(MI->getOperand(0).getReg());
698 case X86::MOVDI2PDIrm:
699 case X86::VMOVDI2PDIrm:
700 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
701 DestName = getRegName(MI->getOperand(0).getReg());
705 if (MI->getOperand(2).isImm() &&
706 MI->getOperand(3).isImm())
707 DecodeEXTRQIMask(MI->getOperand(2).getImm(),
708 MI->getOperand(3).getImm(),
711 DestName = getRegName(MI->getOperand(0).getReg());
712 Src1Name = getRegName(MI->getOperand(1).getReg());
716 if (MI->getOperand(3).isImm() &&
717 MI->getOperand(4).isImm())
718 DecodeINSERTQIMask(MI->getOperand(3).getImm(),
719 MI->getOperand(4).getImm(),
722 DestName = getRegName(MI->getOperand(0).getReg());
723 Src1Name = getRegName(MI->getOperand(1).getReg());
724 Src2Name = getRegName(MI->getOperand(2).getReg());
727 case X86::PMOVZXBWrr:
728 case X86::PMOVZXBDrr:
729 case X86::PMOVZXBQrr:
730 case X86::PMOVZXWDrr:
731 case X86::PMOVZXWQrr:
732 case X86::PMOVZXDQrr:
733 case X86::VPMOVZXBWrr:
734 case X86::VPMOVZXBDrr:
735 case X86::VPMOVZXBQrr:
736 case X86::VPMOVZXWDrr:
737 case X86::VPMOVZXWQrr:
738 case X86::VPMOVZXDQrr:
739 case X86::VPMOVZXBWYrr:
740 case X86::VPMOVZXBDYrr:
741 case X86::VPMOVZXBQYrr:
742 case X86::VPMOVZXWDYrr:
743 case X86::VPMOVZXWQYrr:
744 case X86::VPMOVZXDQYrr:
745 Src1Name = getRegName(MI->getOperand(1).getReg());
747 case X86::PMOVZXBWrm:
748 case X86::PMOVZXBDrm:
749 case X86::PMOVZXBQrm:
750 case X86::PMOVZXWDrm:
751 case X86::PMOVZXWQrm:
752 case X86::PMOVZXDQrm:
753 case X86::VPMOVZXBWrm:
754 case X86::VPMOVZXBDrm:
755 case X86::VPMOVZXBQrm:
756 case X86::VPMOVZXWDrm:
757 case X86::VPMOVZXWQrm:
758 case X86::VPMOVZXDQrm:
759 case X86::VPMOVZXBWYrm:
760 case X86::VPMOVZXBDYrm:
761 case X86::VPMOVZXBQYrm:
762 case X86::VPMOVZXWDYrm:
763 case X86::VPMOVZXWQYrm:
764 case X86::VPMOVZXDQYrm: {
766 getZeroExtensionTypes(MI, SrcVT, DstVT);
767 DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask);
768 DestName = getRegName(MI->getOperand(0).getReg());
772 // The only comments we decode are shuffles, so give up if we were unable to
773 // decode a shuffle mask.
774 if (ShuffleMask.empty())
777 if (!DestName) DestName = Src1Name;
778 OS << (DestName ? DestName : "mem") << " = ";
780 // If the two sources are the same, canonicalize the input elements to be
781 // from the first src so that we get larger element spans.
782 if (Src1Name == Src2Name) {
783 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
784 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
785 ShuffleMask[i] >= (int)e) // From second mask.
790 // The shuffle mask specifies which elements of the src1/src2 fill in the
791 // destination, with a few sentinel values. Loop through and print them
793 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
796 if (ShuffleMask[i] == SM_SentinelZero) {
801 // Otherwise, it must come from src1 or src2. Print the span of elements
802 // that comes from this src.
803 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
804 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
805 OS << (SrcName ? SrcName : "mem") << '[';
807 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
808 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
813 if (ShuffleMask[i] == SM_SentinelUndef)
816 OS << ShuffleMask[i] % ShuffleMask.size();
820 --i; // For loop increments element #.
825 // We successfully added a comment to this instruction.