1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/ADT/APFloat.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/ADT/Twine.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
37 static const char OpPrecedence[] = {
52 class X86AsmParser : public MCTargetAsmParser {
55 ParseInstructionInfo *InstInfo;
57 SMLoc consumeToken() {
58 SMLoc Result = Parser.getTok().getLoc();
63 enum InfixCalculatorTok {
78 class InfixCalculator {
79 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
80 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
81 SmallVector<ICToken, 4> PostfixStack;
84 int64_t popOperand() {
85 assert (!PostfixStack.empty() && "Poped an empty stack!");
86 ICToken Op = PostfixStack.pop_back_val();
87 assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
88 && "Expected and immediate or register!");
91 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
92 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
93 "Unexpected operand!");
94 PostfixStack.push_back(std::make_pair(Op, Val));
97 void popOperator() { InfixOperatorStack.pop_back(); }
98 void pushOperator(InfixCalculatorTok Op) {
99 // Push the new operator if the stack is empty.
100 if (InfixOperatorStack.empty()) {
101 InfixOperatorStack.push_back(Op);
105 // Push the new operator if it has a higher precedence than the operator
106 // on the top of the stack or the operator on the top of the stack is a
108 unsigned Idx = InfixOperatorStack.size() - 1;
109 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
110 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
111 InfixOperatorStack.push_back(Op);
115 // The operator on the top of the stack has higher precedence than the
117 unsigned ParenCount = 0;
119 // Nothing to process.
120 if (InfixOperatorStack.empty())
123 Idx = InfixOperatorStack.size() - 1;
124 StackOp = InfixOperatorStack[Idx];
125 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
128 // If we have an even parentheses count and we see a left parentheses,
129 // then stop processing.
130 if (!ParenCount && StackOp == IC_LPAREN)
133 if (StackOp == IC_RPAREN) {
135 InfixOperatorStack.pop_back();
136 } else if (StackOp == IC_LPAREN) {
138 InfixOperatorStack.pop_back();
140 InfixOperatorStack.pop_back();
141 PostfixStack.push_back(std::make_pair(StackOp, 0));
144 // Push the new operator.
145 InfixOperatorStack.push_back(Op);
148 // Push any remaining operators onto the postfix stack.
149 while (!InfixOperatorStack.empty()) {
150 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
151 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
152 PostfixStack.push_back(std::make_pair(StackOp, 0));
155 if (PostfixStack.empty())
158 SmallVector<ICToken, 16> OperandStack;
159 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
160 ICToken Op = PostfixStack[i];
161 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
162 OperandStack.push_back(Op);
164 assert (OperandStack.size() > 1 && "Too few operands.");
166 ICToken Op2 = OperandStack.pop_back_val();
167 ICToken Op1 = OperandStack.pop_back_val();
170 report_fatal_error("Unexpected operator!");
173 Val = Op1.second + Op2.second;
174 OperandStack.push_back(std::make_pair(IC_IMM, Val));
177 Val = Op1.second - Op2.second;
178 OperandStack.push_back(std::make_pair(IC_IMM, Val));
181 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
182 "Multiply operation with an immediate and a register!");
183 Val = Op1.second * Op2.second;
184 OperandStack.push_back(std::make_pair(IC_IMM, Val));
187 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
188 "Divide operation with an immediate and a register!");
189 assert (Op2.second != 0 && "Division by zero!");
190 Val = Op1.second / Op2.second;
191 OperandStack.push_back(std::make_pair(IC_IMM, Val));
194 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
195 "Or operation with an immediate and a register!");
196 Val = Op1.second | Op2.second;
197 OperandStack.push_back(std::make_pair(IC_IMM, Val));
200 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
201 "And operation with an immediate and a register!");
202 Val = Op1.second & Op2.second;
203 OperandStack.push_back(std::make_pair(IC_IMM, Val));
206 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
207 "Left shift operation with an immediate and a register!");
208 Val = Op1.second << Op2.second;
209 OperandStack.push_back(std::make_pair(IC_IMM, Val));
212 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
213 "Right shift operation with an immediate and a register!");
214 Val = Op1.second >> Op2.second;
215 OperandStack.push_back(std::make_pair(IC_IMM, Val));
220 assert (OperandStack.size() == 1 && "Expected a single result.");
221 return OperandStack.pop_back_val().second;
225 enum IntelExprState {
244 class IntelExprStateMachine {
245 IntelExprState State, PrevState;
246 unsigned BaseReg, IndexReg, TmpReg, Scale;
250 bool StopOnLBrac, AddImmPrefix;
252 InlineAsmIdentifierInfo Info;
254 IntelExprStateMachine(int64_t imm, bool stoponlbrac, bool addimmprefix) :
255 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
256 Scale(1), Imm(imm), Sym(0), StopOnLBrac(stoponlbrac),
257 AddImmPrefix(addimmprefix) { Info.clear(); }
259 unsigned getBaseReg() { return BaseReg; }
260 unsigned getIndexReg() { return IndexReg; }
261 unsigned getScale() { return Scale; }
262 const MCExpr *getSym() { return Sym; }
263 StringRef getSymName() { return SymName; }
264 int64_t getImm() { return Imm + IC.execute(); }
265 bool isValidEndState() {
266 return State == IES_RBRAC || State == IES_INTEGER;
268 bool getStopOnLBrac() { return StopOnLBrac; }
269 bool getAddImmPrefix() { return AddImmPrefix; }
270 bool hadError() { return State == IES_ERROR; }
272 InlineAsmIdentifierInfo &getIdentifierInfo() {
277 IntelExprState CurrState = State;
286 IC.pushOperator(IC_OR);
289 PrevState = CurrState;
292 IntelExprState CurrState = State;
301 IC.pushOperator(IC_AND);
304 PrevState = CurrState;
307 IntelExprState CurrState = State;
316 IC.pushOperator(IC_LSHIFT);
319 PrevState = CurrState;
322 IntelExprState CurrState = State;
331 IC.pushOperator(IC_RSHIFT);
334 PrevState = CurrState;
337 IntelExprState CurrState = State;
346 IC.pushOperator(IC_PLUS);
347 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
348 // If we already have a BaseReg, then assume this is the IndexReg with
353 assert (!IndexReg && "BaseReg/IndexReg already set!");
360 PrevState = CurrState;
363 IntelExprState CurrState = State;
378 // Only push the minus operator if it is not a unary operator.
379 if (!(CurrState == IES_PLUS || CurrState == IES_MINUS ||
380 CurrState == IES_MULTIPLY || CurrState == IES_DIVIDE ||
381 CurrState == IES_LPAREN || CurrState == IES_LBRAC))
382 IC.pushOperator(IC_MINUS);
383 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
384 // If we already have a BaseReg, then assume this is the IndexReg with
389 assert (!IndexReg && "BaseReg/IndexReg already set!");
396 PrevState = CurrState;
398 void onRegister(unsigned Reg) {
399 IntelExprState CurrState = State;
406 State = IES_REGISTER;
408 IC.pushOperand(IC_REGISTER);
411 // Index Register - Scale * Register
412 if (PrevState == IES_INTEGER) {
413 assert (!IndexReg && "IndexReg already set!");
414 State = IES_REGISTER;
416 // Get the scale and replace the 'Scale * Register' with '0'.
417 Scale = IC.popOperand();
418 IC.pushOperand(IC_IMM);
425 PrevState = CurrState;
427 void onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName) {
437 SymName = SymRefName;
438 IC.pushOperand(IC_IMM);
442 bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
443 IntelExprState CurrState = State;
458 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
459 // Index Register - Register * Scale
460 assert (!IndexReg && "IndexReg already set!");
463 if(Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
464 ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
467 // Get the scale and replace the 'Register * Scale' with '0'.
469 } else if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
470 PrevState == IES_OR || PrevState == IES_AND ||
471 PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
472 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
473 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
474 CurrState == IES_MINUS) {
475 // Unary minus. No need to pop the minus operand because it was never
477 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm.
479 IC.pushOperand(IC_IMM, TmpInt);
483 PrevState = CurrState;
495 State = IES_MULTIPLY;
496 IC.pushOperator(IC_MULTIPLY);
509 IC.pushOperator(IC_DIVIDE);
521 IC.pushOperator(IC_PLUS);
526 IntelExprState CurrState = State;
535 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
536 // If we already have a BaseReg, then assume this is the IndexReg with
541 assert (!IndexReg && "BaseReg/IndexReg already set!");
548 PrevState = CurrState;
551 IntelExprState CurrState = State;
565 // FIXME: We don't handle this type of unary minus, yet.
566 if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
567 PrevState == IES_OR || PrevState == IES_AND ||
568 PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
569 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
570 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
571 CurrState == IES_MINUS) {
576 IC.pushOperator(IC_LPAREN);
579 PrevState = CurrState;
591 IC.pushOperator(IC_RPAREN);
597 MCAsmParser &getParser() const { return Parser; }
599 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
601 bool Error(SMLoc L, const Twine &Msg,
602 ArrayRef<SMRange> Ranges = None,
603 bool MatchingInlineAsm = false) {
604 if (MatchingInlineAsm) return true;
605 return Parser.Error(L, Msg, Ranges);
608 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
613 X86Operand *DefaultMemSIOperand(SMLoc Loc);
614 X86Operand *DefaultMemDIOperand(SMLoc Loc);
615 X86Operand *ParseOperand();
616 X86Operand *ParseATTOperand();
617 X86Operand *ParseIntelOperand();
618 X86Operand *ParseIntelOffsetOfOperator();
619 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
620 X86Operand *ParseIntelOperator(unsigned OpKind);
621 X86Operand *ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
622 X86Operand *ParseIntelMemOperand(int64_t ImmDisp, SMLoc StartLoc,
624 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
625 X86Operand *ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
626 int64_t ImmDisp, unsigned Size);
627 bool ParseIntelIdentifier(const MCExpr *&Val, StringRef &Identifier,
628 InlineAsmIdentifierInfo &Info,
629 bool IsUnevaluatedOperand, SMLoc &End);
631 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
633 X86Operand *CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
634 unsigned BaseReg, unsigned IndexReg,
635 unsigned Scale, SMLoc Start, SMLoc End,
636 unsigned Size, StringRef Identifier,
637 InlineAsmIdentifierInfo &Info);
639 bool ParseDirectiveWord(unsigned Size, SMLoc L);
640 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
642 bool processInstruction(MCInst &Inst,
643 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
645 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
646 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
647 MCStreamer &Out, unsigned &ErrorInfo,
648 bool MatchingInlineAsm);
650 /// doSrcDstMatch - Returns true if operands are matching in their
651 /// word size (%si and %di, %esi and %edi, etc.). Order depends on
652 /// the parsing mode (Intel vs. AT&T).
653 bool doSrcDstMatch(X86Operand &Op1, X86Operand &Op2);
655 bool is64BitMode() const {
656 // FIXME: Can tablegen auto-generate this?
657 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
659 bool is32BitMode() const {
660 // FIXME: Can tablegen auto-generate this?
661 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
663 bool is16BitMode() const {
664 // FIXME: Can tablegen auto-generate this?
665 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
667 void SwitchMode(uint64_t mode) {
668 uint64_t oldMode = STI.getFeatureBits() &
669 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
670 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
671 setAvailableFeatures(FB);
672 assert(mode == (STI.getFeatureBits() &
673 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
676 bool isParsingIntelSyntax() {
677 return getParser().getAssemblerDialect();
680 /// @name Auto-generated Matcher Functions
683 #define GET_ASSEMBLER_HEADER
684 #include "X86GenAsmMatcher.inc"
689 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
690 const MCInstrInfo &MII)
691 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
693 // Initialize the set of available features.
694 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
696 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
698 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
700 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
702 virtual bool ParseDirective(AsmToken DirectiveID);
704 } // end anonymous namespace
706 /// @name Auto-generated Match Functions
709 static unsigned MatchRegisterName(StringRef Name);
713 static bool isImmSExti16i8Value(uint64_t Value) {
714 return (( Value <= 0x000000000000007FULL)||
715 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
716 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
719 static bool isImmSExti32i8Value(uint64_t Value) {
720 return (( Value <= 0x000000000000007FULL)||
721 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
722 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
725 static bool isImmZExtu32u8Value(uint64_t Value) {
726 return (Value <= 0x00000000000000FFULL);
729 static bool isImmSExti64i8Value(uint64_t Value) {
730 return (( Value <= 0x000000000000007FULL)||
731 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
734 static bool isImmSExti64i32Value(uint64_t Value) {
735 return (( Value <= 0x000000007FFFFFFFULL)||
736 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
740 /// X86Operand - Instances of this class represent a parsed X86 machine
742 struct X86Operand : public MCParsedAsmOperand {
750 SMLoc StartLoc, EndLoc;
785 X86Operand(KindTy K, SMLoc Start, SMLoc End)
786 : Kind(K), StartLoc(Start), EndLoc(End) {}
788 StringRef getSymName() { return SymName; }
789 void *getOpDecl() { return OpDecl; }
791 /// getStartLoc - Get the location of the first token of this operand.
792 SMLoc getStartLoc() const { return StartLoc; }
793 /// getEndLoc - Get the location of the last token of this operand.
794 SMLoc getEndLoc() const { return EndLoc; }
795 /// getLocRange - Get the range between the first and last token of this
797 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
798 /// getOffsetOfLoc - Get the location of the offset operator.
799 SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
801 virtual void print(raw_ostream &OS) const {}
803 StringRef getToken() const {
804 assert(Kind == Token && "Invalid access!");
805 return StringRef(Tok.Data, Tok.Length);
807 void setTokenValue(StringRef Value) {
808 assert(Kind == Token && "Invalid access!");
809 Tok.Data = Value.data();
810 Tok.Length = Value.size();
813 unsigned getReg() const {
814 assert(Kind == Register && "Invalid access!");
818 const MCExpr *getImm() const {
819 assert(Kind == Immediate && "Invalid access!");
823 const MCExpr *getMemDisp() const {
824 assert(Kind == Memory && "Invalid access!");
827 unsigned getMemSegReg() const {
828 assert(Kind == Memory && "Invalid access!");
831 unsigned getMemBaseReg() const {
832 assert(Kind == Memory && "Invalid access!");
835 unsigned getMemIndexReg() const {
836 assert(Kind == Memory && "Invalid access!");
839 unsigned getMemScale() const {
840 assert(Kind == Memory && "Invalid access!");
844 bool isToken() const {return Kind == Token; }
846 bool isImm() const { return Kind == Immediate; }
848 bool isImmSExti16i8() const {
852 // If this isn't a constant expr, just assume it fits and let relaxation
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
858 // Otherwise, check the value is in a range that makes sense for this
860 return isImmSExti16i8Value(CE->getValue());
862 bool isImmSExti32i8() const {
866 // If this isn't a constant expr, just assume it fits and let relaxation
868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
872 // Otherwise, check the value is in a range that makes sense for this
874 return isImmSExti32i8Value(CE->getValue());
876 bool isImmZExtu32u8() const {
880 // If this isn't a constant expr, just assume it fits and let relaxation
882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
886 // Otherwise, check the value is in a range that makes sense for this
888 return isImmZExtu32u8Value(CE->getValue());
890 bool isImmSExti64i8() const {
894 // If this isn't a constant expr, just assume it fits and let relaxation
896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
900 // Otherwise, check the value is in a range that makes sense for this
902 return isImmSExti64i8Value(CE->getValue());
904 bool isImmSExti64i32() const {
908 // If this isn't a constant expr, just assume it fits and let relaxation
910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
914 // Otherwise, check the value is in a range that makes sense for this
916 return isImmSExti64i32Value(CE->getValue());
919 bool isOffsetOf() const {
920 return OffsetOfLoc.getPointer();
923 bool needAddressOf() const {
927 bool isMem() const { return Kind == Memory; }
928 bool isMem8() const {
929 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
931 bool isMem16() const {
932 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
934 bool isMem32() const {
935 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
937 bool isMem64() const {
938 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
940 bool isMem80() const {
941 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
943 bool isMem128() const {
944 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
946 bool isMem256() const {
947 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
949 bool isMem512() const {
950 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
953 bool isMemVX32() const {
954 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
955 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
957 bool isMemVY32() const {
958 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
959 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
961 bool isMemVX64() const {
962 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
963 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
965 bool isMemVY64() const {
966 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
967 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
969 bool isMemVZ32() const {
970 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
971 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
973 bool isMemVZ64() const {
974 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
975 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
978 bool isAbsMem() const {
979 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
980 !getMemIndexReg() && getMemScale() == 1;
983 bool isSrcIdx() const {
984 return !getMemIndexReg() && getMemScale() == 1 &&
985 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
986 getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
987 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
989 bool isSrcIdx8() const {
990 return isMem8() && isSrcIdx();
992 bool isSrcIdx16() const {
993 return isMem16() && isSrcIdx();
995 bool isSrcIdx32() const {
996 return isMem32() && isSrcIdx();
998 bool isSrcIdx64() const {
999 return isMem64() && isSrcIdx();
1002 bool isDstIdx() const {
1003 return !getMemIndexReg() && getMemScale() == 1 &&
1004 (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
1005 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
1006 getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
1007 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
1009 bool isDstIdx8() const {
1010 return isMem8() && isDstIdx();
1012 bool isDstIdx16() const {
1013 return isMem16() && isDstIdx();
1015 bool isDstIdx32() const {
1016 return isMem32() && isDstIdx();
1018 bool isDstIdx64() const {
1019 return isMem64() && isDstIdx();
1022 bool isMemOffs8() const {
1023 return Kind == Memory && !getMemBaseReg() &&
1024 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 8);
1026 bool isMemOffs16() const {
1027 return Kind == Memory && !getMemBaseReg() &&
1028 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 16);
1030 bool isMemOffs32() const {
1031 return Kind == Memory && !getMemBaseReg() &&
1032 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 32);
1034 bool isMemOffs64() const {
1035 return Kind == Memory && !getMemBaseReg() &&
1036 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 64);
1039 bool isReg() const { return Kind == Register; }
1041 bool isGR32orGR64() const {
1042 return Kind == Register &&
1043 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
1044 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
1047 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1048 // Add as immediates when possible.
1049 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1050 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1052 Inst.addOperand(MCOperand::CreateExpr(Expr));
1055 void addRegOperands(MCInst &Inst, unsigned N) const {
1056 assert(N == 1 && "Invalid number of operands!");
1057 Inst.addOperand(MCOperand::CreateReg(getReg()));
1060 static unsigned getGR32FromGR64(unsigned RegNo) {
1062 default: llvm_unreachable("Unexpected register");
1063 case X86::RAX: return X86::EAX;
1064 case X86::RCX: return X86::ECX;
1065 case X86::RDX: return X86::EDX;
1066 case X86::RBX: return X86::EBX;
1067 case X86::RBP: return X86::EBP;
1068 case X86::RSP: return X86::ESP;
1069 case X86::RSI: return X86::ESI;
1070 case X86::RDI: return X86::EDI;
1071 case X86::R8: return X86::R8D;
1072 case X86::R9: return X86::R9D;
1073 case X86::R10: return X86::R10D;
1074 case X86::R11: return X86::R11D;
1075 case X86::R12: return X86::R12D;
1076 case X86::R13: return X86::R13D;
1077 case X86::R14: return X86::R14D;
1078 case X86::R15: return X86::R15D;
1079 case X86::RIP: return X86::EIP;
1083 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
1084 assert(N == 1 && "Invalid number of operands!");
1085 unsigned RegNo = getReg();
1086 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
1087 RegNo = getGR32FromGR64(RegNo);
1088 Inst.addOperand(MCOperand::CreateReg(RegNo));
1091 void addImmOperands(MCInst &Inst, unsigned N) const {
1092 assert(N == 1 && "Invalid number of operands!");
1093 addExpr(Inst, getImm());
1096 void addMemOperands(MCInst &Inst, unsigned N) const {
1097 assert((N == 5) && "Invalid number of operands!");
1098 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1099 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
1100 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
1101 addExpr(Inst, getMemDisp());
1102 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1105 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
1106 assert((N == 1) && "Invalid number of operands!");
1107 // Add as immediates when possible.
1108 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
1109 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1111 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
1114 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
1115 assert((N == 2) && "Invalid number of operands!");
1116 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1117 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1119 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
1120 assert((N == 1) && "Invalid number of operands!");
1121 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1124 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
1125 assert((N == 2) && "Invalid number of operands!");
1126 // Add as immediates when possible.
1127 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
1128 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1130 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
1131 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1134 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
1135 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
1136 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
1137 Res->Tok.Data = Str.data();
1138 Res->Tok.Length = Str.size();
1142 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
1143 bool AddressOf = false,
1144 SMLoc OffsetOfLoc = SMLoc(),
1145 StringRef SymName = StringRef(),
1147 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
1148 Res->Reg.RegNo = RegNo;
1149 Res->AddressOf = AddressOf;
1150 Res->OffsetOfLoc = OffsetOfLoc;
1151 Res->SymName = SymName;
1152 Res->OpDecl = OpDecl;
1156 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
1157 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
1162 /// Create an absolute memory operand.
1163 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
1164 unsigned Size = 0, StringRef SymName = StringRef(),
1166 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
1167 Res->Mem.SegReg = 0;
1168 Res->Mem.Disp = Disp;
1169 Res->Mem.BaseReg = 0;
1170 Res->Mem.IndexReg = 0;
1172 Res->Mem.Size = Size;
1173 Res->SymName = SymName;
1174 Res->OpDecl = OpDecl;
1175 Res->AddressOf = false;
1179 /// Create a generalized memory operand.
1180 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
1181 unsigned BaseReg, unsigned IndexReg,
1182 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
1184 StringRef SymName = StringRef(),
1186 // We should never just have a displacement, that should be parsed as an
1187 // absolute memory operand.
1188 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
1190 // The scale should always be one of {1,2,4,8}.
1191 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
1193 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
1194 Res->Mem.SegReg = SegReg;
1195 Res->Mem.Disp = Disp;
1196 Res->Mem.BaseReg = BaseReg;
1197 Res->Mem.IndexReg = IndexReg;
1198 Res->Mem.Scale = Scale;
1199 Res->Mem.Size = Size;
1200 Res->SymName = SymName;
1201 Res->OpDecl = OpDecl;
1202 Res->AddressOf = false;
1207 } // end anonymous namespace.
1209 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,
1210 StringRef &ErrMsg) {
1211 // If we have both a base register and an index register make sure they are
1212 // both 64-bit or 32-bit registers.
1213 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1214 if (BaseReg != 0 && IndexReg != 0) {
1215 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1216 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1217 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
1218 IndexReg != X86::RIZ) {
1219 ErrMsg = "base register is 64-bit, but index register is not";
1222 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1223 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1224 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
1225 IndexReg != X86::EIZ){
1226 ErrMsg = "base register is 32-bit, but index register is not";
1229 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
1230 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1231 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1232 ErrMsg = "base register is 16-bit, but index register is not";
1235 if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
1236 IndexReg != X86::SI && IndexReg != X86::DI) ||
1237 ((BaseReg == X86::SI || BaseReg == X86::DI) &&
1238 IndexReg != X86::BX && IndexReg != X86::BP)) {
1239 ErrMsg = "invalid 16-bit base/index register combination";
1247 bool X86AsmParser::doSrcDstMatch(X86Operand &Op1, X86Operand &Op2)
1249 // Return true and let a normal complaint about bogus operands happen.
1250 if (!Op1.isMem() || !Op2.isMem())
1253 // Actually these might be the other way round if Intel syntax is
1254 // being used. It doesn't matter.
1255 unsigned diReg = Op1.Mem.BaseReg;
1256 unsigned siReg = Op2.Mem.BaseReg;
1258 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(siReg))
1259 return X86MCRegisterClasses[X86::GR16RegClassID].contains(diReg);
1260 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(siReg))
1261 return X86MCRegisterClasses[X86::GR32RegClassID].contains(diReg);
1262 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(siReg))
1263 return X86MCRegisterClasses[X86::GR64RegClassID].contains(diReg);
1264 // Again, return true and let another error happen.
1268 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1269 SMLoc &StartLoc, SMLoc &EndLoc) {
1271 const AsmToken &PercentTok = Parser.getTok();
1272 StartLoc = PercentTok.getLoc();
1274 // If we encounter a %, ignore it. This code handles registers with and
1275 // without the prefix, unprefixed registers can occur in cfi directives.
1276 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1277 Parser.Lex(); // Eat percent token.
1279 const AsmToken &Tok = Parser.getTok();
1280 EndLoc = Tok.getEndLoc();
1282 if (Tok.isNot(AsmToken::Identifier)) {
1283 if (isParsingIntelSyntax()) return true;
1284 return Error(StartLoc, "invalid register name",
1285 SMRange(StartLoc, EndLoc));
1288 RegNo = MatchRegisterName(Tok.getString());
1290 // If the match failed, try the register name as lowercase.
1292 RegNo = MatchRegisterName(Tok.getString().lower());
1294 if (!is64BitMode()) {
1295 // FIXME: This should be done using Requires<Not64BitMode> and
1296 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1298 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1300 if (RegNo == X86::RIZ ||
1301 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1302 X86II::isX86_64NonExtLowByteReg(RegNo) ||
1303 X86II::isX86_64ExtendedReg(RegNo))
1304 return Error(StartLoc, "register %"
1305 + Tok.getString() + " is only available in 64-bit mode",
1306 SMRange(StartLoc, EndLoc));
1309 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1310 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
1312 Parser.Lex(); // Eat 'st'
1314 // Check to see if we have '(4)' after %st.
1315 if (getLexer().isNot(AsmToken::LParen))
1320 const AsmToken &IntTok = Parser.getTok();
1321 if (IntTok.isNot(AsmToken::Integer))
1322 return Error(IntTok.getLoc(), "expected stack index");
1323 switch (IntTok.getIntVal()) {
1324 case 0: RegNo = X86::ST0; break;
1325 case 1: RegNo = X86::ST1; break;
1326 case 2: RegNo = X86::ST2; break;
1327 case 3: RegNo = X86::ST3; break;
1328 case 4: RegNo = X86::ST4; break;
1329 case 5: RegNo = X86::ST5; break;
1330 case 6: RegNo = X86::ST6; break;
1331 case 7: RegNo = X86::ST7; break;
1332 default: return Error(IntTok.getLoc(), "invalid stack index");
1335 if (getParser().Lex().isNot(AsmToken::RParen))
1336 return Error(Parser.getTok().getLoc(), "expected ')'");
1338 EndLoc = Parser.getTok().getEndLoc();
1339 Parser.Lex(); // Eat ')'
1343 EndLoc = Parser.getTok().getEndLoc();
1345 // If this is "db[0-7]", match it as an alias
1347 if (RegNo == 0 && Tok.getString().size() == 3 &&
1348 Tok.getString().startswith("db")) {
1349 switch (Tok.getString()[2]) {
1350 case '0': RegNo = X86::DR0; break;
1351 case '1': RegNo = X86::DR1; break;
1352 case '2': RegNo = X86::DR2; break;
1353 case '3': RegNo = X86::DR3; break;
1354 case '4': RegNo = X86::DR4; break;
1355 case '5': RegNo = X86::DR5; break;
1356 case '6': RegNo = X86::DR6; break;
1357 case '7': RegNo = X86::DR7; break;
1361 EndLoc = Parser.getTok().getEndLoc();
1362 Parser.Lex(); // Eat it.
1368 if (isParsingIntelSyntax()) return true;
1369 return Error(StartLoc, "invalid register name",
1370 SMRange(StartLoc, EndLoc));
1373 Parser.Lex(); // Eat identifier token.
1377 X86Operand *X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1379 is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
1380 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
1381 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
1382 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
1385 X86Operand *X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1387 is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
1388 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
1389 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
1390 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
1393 X86Operand *X86AsmParser::ParseOperand() {
1394 if (isParsingIntelSyntax())
1395 return ParseIntelOperand();
1396 return ParseATTOperand();
1399 /// getIntelMemOperandSize - Return intel memory operand size.
1400 static unsigned getIntelMemOperandSize(StringRef OpStr) {
1401 unsigned Size = StringSwitch<unsigned>(OpStr)
1402 .Cases("BYTE", "byte", 8)
1403 .Cases("WORD", "word", 16)
1404 .Cases("DWORD", "dword", 32)
1405 .Cases("QWORD", "qword", 64)
1406 .Cases("XWORD", "xword", 80)
1407 .Cases("XMMWORD", "xmmword", 128)
1408 .Cases("YMMWORD", "ymmword", 256)
1409 .Cases("ZMMWORD", "zmmword", 512)
1410 .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter
1416 X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
1417 unsigned BaseReg, unsigned IndexReg,
1418 unsigned Scale, SMLoc Start, SMLoc End,
1419 unsigned Size, StringRef Identifier,
1420 InlineAsmIdentifierInfo &Info){
1421 if (isa<MCSymbolRefExpr>(Disp)) {
1422 // If this is not a VarDecl then assume it is a FuncDecl or some other label
1423 // reference. We need an 'r' constraint here, so we need to create register
1424 // operand to ensure proper matching. Just pick a GPR based on the size of
1426 if (!Info.IsVarDecl) {
1428 is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1429 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,
1430 SMLoc(), Identifier, Info.OpDecl);
1433 Size = Info.Type * 8; // Size is in terms of bits in this context.
1435 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_SizeDirective, Start,
1440 // When parsing inline assembly we set the base register to a non-zero value
1441 // if we don't know the actual value at this time. This is necessary to
1442 // get the matching correct in some cases.
1443 BaseReg = BaseReg ? BaseReg : 1;
1444 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1445 End, Size, Identifier, Info.OpDecl);
1449 RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> *AsmRewrites,
1450 StringRef SymName, int64_t ImmDisp,
1451 int64_t FinalImmDisp, SMLoc &BracLoc,
1452 SMLoc &StartInBrac, SMLoc &End) {
1453 // Remove the '[' and ']' from the IR string.
1454 AsmRewrites->push_back(AsmRewrite(AOK_Skip, BracLoc, 1));
1455 AsmRewrites->push_back(AsmRewrite(AOK_Skip, End, 1));
1457 // If ImmDisp is non-zero, then we parsed a displacement before the
1458 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1459 // If ImmDisp doesn't match the displacement computed by the state machine
1460 // then we have an additional displacement in the bracketed expression.
1461 if (ImmDisp != FinalImmDisp) {
1463 // We have an immediate displacement before the bracketed expression.
1464 // Adjust this to match the final immediate displacement.
1466 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1467 E = AsmRewrites->end(); I != E; ++I) {
1468 if ((*I).Loc.getPointer() > BracLoc.getPointer())
1470 if ((*I).Kind == AOK_ImmPrefix || (*I).Kind == AOK_Imm) {
1471 assert (!Found && "ImmDisp already rewritten.");
1472 (*I).Kind = AOK_Imm;
1473 (*I).Len = BracLoc.getPointer() - (*I).Loc.getPointer();
1474 (*I).Val = FinalImmDisp;
1479 assert (Found && "Unable to rewrite ImmDisp.");
1482 // We have a symbolic and an immediate displacement, but no displacement
1483 // before the bracketed expression. Put the immediate displacement
1484 // before the bracketed expression.
1485 AsmRewrites->push_back(AsmRewrite(AOK_Imm, BracLoc, 0, FinalImmDisp));
1488 // Remove all the ImmPrefix rewrites within the brackets.
1489 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1490 E = AsmRewrites->end(); I != E; ++I) {
1491 if ((*I).Loc.getPointer() < StartInBrac.getPointer())
1493 if ((*I).Kind == AOK_ImmPrefix)
1494 (*I).Kind = AOK_Delete;
1496 const char *SymLocPtr = SymName.data();
1497 // Skip everything before the symbol.
1498 if (unsigned Len = SymLocPtr - StartInBrac.getPointer()) {
1499 assert(Len > 0 && "Expected a non-negative length.");
1500 AsmRewrites->push_back(AsmRewrite(AOK_Skip, StartInBrac, Len));
1502 // Skip everything after the symbol.
1503 if (unsigned Len = End.getPointer() - (SymLocPtr + SymName.size())) {
1504 SMLoc Loc = SMLoc::getFromPointer(SymLocPtr + SymName.size());
1505 assert(Len > 0 && "Expected a non-negative length.");
1506 AsmRewrites->push_back(AsmRewrite(AOK_Skip, Loc, Len));
1510 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1511 const AsmToken &Tok = Parser.getTok();
1515 bool UpdateLocLex = true;
1517 // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1518 // identifier. Don't try an parse it as a register.
1519 if (Tok.getString().startswith("."))
1522 // If we're parsing an immediate expression, we don't expect a '['.
1523 if (SM.getStopOnLBrac() && getLexer().getKind() == AsmToken::LBrac)
1526 switch (getLexer().getKind()) {
1528 if (SM.isValidEndState()) {
1532 return Error(Tok.getLoc(), "unknown token in expression");
1534 case AsmToken::EndOfStatement: {
1538 case AsmToken::Identifier: {
1539 // This could be a register or a symbolic displacement.
1542 SMLoc IdentLoc = Tok.getLoc();
1543 StringRef Identifier = Tok.getString();
1544 if(!ParseRegister(TmpReg, IdentLoc, End)) {
1545 SM.onRegister(TmpReg);
1546 UpdateLocLex = false;
1549 if (!isParsingInlineAsm()) {
1550 if (getParser().parsePrimaryExpr(Val, End))
1551 return Error(Tok.getLoc(), "Unexpected identifier!");
1553 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1554 if (ParseIntelIdentifier(Val, Identifier, Info,
1555 /*Unevaluated=*/false, End))
1558 SM.onIdentifierExpr(Val, Identifier);
1559 UpdateLocLex = false;
1562 return Error(Tok.getLoc(), "Unexpected identifier!");
1564 case AsmToken::Integer: {
1566 if (isParsingInlineAsm() && SM.getAddImmPrefix())
1567 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1569 // Look for 'b' or 'f' following an Integer as a directional label
1570 SMLoc Loc = getTok().getLoc();
1571 int64_t IntVal = getTok().getIntVal();
1572 End = consumeToken();
1573 UpdateLocLex = false;
1574 if (getLexer().getKind() == AsmToken::Identifier) {
1575 StringRef IDVal = getTok().getString();
1576 if (IDVal == "f" || IDVal == "b") {
1578 getContext().GetDirectionalLocalSymbol(IntVal,
1579 IDVal == "f" ? 1 : 0);
1580 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1582 MCSymbolRefExpr::Create(Sym, Variant, getContext());
1583 if (IDVal == "b" && Sym->isUndefined())
1584 return Error(Loc, "invalid reference to undefined symbol");
1585 StringRef Identifier = Sym->getName();
1586 SM.onIdentifierExpr(Val, Identifier);
1587 End = consumeToken();
1589 if (SM.onInteger(IntVal, ErrMsg))
1590 return Error(Loc, ErrMsg);
1593 if (SM.onInteger(IntVal, ErrMsg))
1594 return Error(Loc, ErrMsg);
1598 case AsmToken::Plus: SM.onPlus(); break;
1599 case AsmToken::Minus: SM.onMinus(); break;
1600 case AsmToken::Star: SM.onStar(); break;
1601 case AsmToken::Slash: SM.onDivide(); break;
1602 case AsmToken::Pipe: SM.onOr(); break;
1603 case AsmToken::Amp: SM.onAnd(); break;
1604 case AsmToken::LessLess:
1605 SM.onLShift(); break;
1606 case AsmToken::GreaterGreater:
1607 SM.onRShift(); break;
1608 case AsmToken::LBrac: SM.onLBrac(); break;
1609 case AsmToken::RBrac: SM.onRBrac(); break;
1610 case AsmToken::LParen: SM.onLParen(); break;
1611 case AsmToken::RParen: SM.onRParen(); break;
1614 return Error(Tok.getLoc(), "unknown token in expression");
1616 if (!Done && UpdateLocLex)
1617 End = consumeToken();
1622 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
1625 const AsmToken &Tok = Parser.getTok();
1626 SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
1627 if (getLexer().isNot(AsmToken::LBrac))
1628 return ErrorOperand(BracLoc, "Expected '[' token!");
1629 Parser.Lex(); // Eat '['
1631 SMLoc StartInBrac = Tok.getLoc();
1632 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1633 // may have already parsed an immediate displacement before the bracketed
1635 IntelExprStateMachine SM(ImmDisp, /*StopOnLBrac=*/false, /*AddImmPrefix=*/true);
1636 if (ParseIntelExpression(SM, End))
1640 if (const MCExpr *Sym = SM.getSym()) {
1641 // A symbolic displacement.
1643 if (isParsingInlineAsm())
1644 RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),
1645 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
1648 // An immediate displacement only.
1649 Disp = MCConstantExpr::Create(SM.getImm(), getContext());
1652 // Parse the dot operator (e.g., [ebx].foo.bar).
1653 if (Tok.getString().startswith(".")) {
1654 const MCExpr *NewDisp;
1655 if (ParseIntelDotOperator(Disp, NewDisp))
1658 End = Tok.getEndLoc();
1659 Parser.Lex(); // Eat the field.
1663 int BaseReg = SM.getBaseReg();
1664 int IndexReg = SM.getIndexReg();
1665 int Scale = SM.getScale();
1666 if (!isParsingInlineAsm()) {
1668 if (!BaseReg && !IndexReg) {
1670 return X86Operand::CreateMem(Disp, Start, End, Size);
1672 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
1675 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
1676 Error(StartInBrac, ErrMsg);
1679 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1683 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1684 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1685 End, Size, SM.getSymName(), Info);
1688 // Inline assembly may use variable names with namespace alias qualifiers.
1689 bool X86AsmParser::ParseIntelIdentifier(const MCExpr *&Val,
1690 StringRef &Identifier,
1691 InlineAsmIdentifierInfo &Info,
1692 bool IsUnevaluatedOperand, SMLoc &End) {
1693 assert (isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1696 StringRef LineBuf(Identifier.data());
1697 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1699 const AsmToken &Tok = Parser.getTok();
1701 // Advance the token stream until the end of the current token is
1702 // after the end of what the frontend claimed.
1703 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1705 End = Tok.getEndLoc();
1708 assert(End.getPointer() <= EndPtr && "frontend claimed part of a token?");
1709 if (End.getPointer() == EndPtr) break;
1712 // Create the symbol reference.
1713 Identifier = LineBuf;
1714 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1715 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1716 Val = MCSymbolRefExpr::Create(Sym, Variant, getParser().getContext());
1720 /// \brief Parse intel style segment override.
1721 X86Operand *X86AsmParser::ParseIntelSegmentOverride(unsigned SegReg,
1724 assert(SegReg != 0 && "Tried to parse a segment override without a segment!");
1725 const AsmToken &Tok = Parser.getTok(); // Eat colon.
1726 if (Tok.isNot(AsmToken::Colon))
1727 return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1728 Parser.Lex(); // Eat ':'
1730 int64_t ImmDisp = 0;
1731 if (getLexer().is(AsmToken::Integer)) {
1732 ImmDisp = Tok.getIntVal();
1733 AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
1735 if (isParsingInlineAsm())
1736 InstInfo->AsmRewrites->push_back(
1737 AsmRewrite(AOK_ImmPrefix, ImmDispToken.getLoc()));
1739 if (getLexer().isNot(AsmToken::LBrac)) {
1740 // An immediate following a 'segment register', 'colon' token sequence can
1741 // be followed by a bracketed expression. If it isn't we know we have our
1742 // final segment override.
1743 const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext());
1744 return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0, /*IndexReg=*/0,
1745 /*Scale=*/1, Start, ImmDispToken.getEndLoc(),
1750 if (getLexer().is(AsmToken::LBrac))
1751 return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1755 if (!isParsingInlineAsm()) {
1756 if (getParser().parsePrimaryExpr(Val, End))
1757 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1759 return X86Operand::CreateMem(Val, Start, End, Size);
1762 InlineAsmIdentifierInfo Info;
1763 StringRef Identifier = Tok.getString();
1764 if (ParseIntelIdentifier(Val, Identifier, Info,
1765 /*Unevaluated=*/false, End))
1767 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1768 /*Scale=*/1, Start, End, Size, Identifier, Info);
1771 /// ParseIntelMemOperand - Parse intel style memory operand.
1772 X86Operand *X86AsmParser::ParseIntelMemOperand(int64_t ImmDisp, SMLoc Start,
1774 const AsmToken &Tok = Parser.getTok();
1777 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1778 if (getLexer().is(AsmToken::LBrac))
1779 return ParseIntelBracExpression(/*SegReg=*/0, Start, ImmDisp, Size);
1782 if (!isParsingInlineAsm()) {
1783 if (getParser().parsePrimaryExpr(Val, End))
1784 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1786 return X86Operand::CreateMem(Val, Start, End, Size);
1789 InlineAsmIdentifierInfo Info;
1790 StringRef Identifier = Tok.getString();
1791 if (ParseIntelIdentifier(Val, Identifier, Info,
1792 /*Unevaluated=*/false, End))
1794 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1795 /*Scale=*/1, Start, End, Size, Identifier, Info);
1798 /// Parse the '.' operator.
1799 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
1800 const MCExpr *&NewDisp) {
1801 const AsmToken &Tok = Parser.getTok();
1802 int64_t OrigDispVal, DotDispVal;
1804 // FIXME: Handle non-constant expressions.
1805 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp))
1806 OrigDispVal = OrigDisp->getValue();
1808 return Error(Tok.getLoc(), "Non-constant offsets are not supported!");
1811 StringRef DotDispStr = Tok.getString().drop_front(1);
1813 // .Imm gets lexed as a real.
1814 if (Tok.is(AsmToken::Real)) {
1816 DotDispStr.getAsInteger(10, DotDisp);
1817 DotDispVal = DotDisp.getZExtValue();
1818 } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1820 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1821 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1823 return Error(Tok.getLoc(), "Unable to lookup field reference!");
1824 DotDispVal = DotDisp;
1826 return Error(Tok.getLoc(), "Unexpected token type!");
1828 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1829 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1830 unsigned Len = DotDispStr.size();
1831 unsigned Val = OrigDispVal + DotDispVal;
1832 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
1836 NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
1840 /// Parse the 'offset' operator. This operator is used to specify the
1841 /// location rather then the content of a variable.
1842 X86Operand *X86AsmParser::ParseIntelOffsetOfOperator() {
1843 const AsmToken &Tok = Parser.getTok();
1844 SMLoc OffsetOfLoc = Tok.getLoc();
1845 Parser.Lex(); // Eat offset.
1848 InlineAsmIdentifierInfo Info;
1849 SMLoc Start = Tok.getLoc(), End;
1850 StringRef Identifier = Tok.getString();
1851 if (ParseIntelIdentifier(Val, Identifier, Info,
1852 /*Unevaluated=*/false, End))
1855 // Don't emit the offset operator.
1856 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
1858 // The offset operator will have an 'r' constraint, thus we need to create
1859 // register operand to ensure proper matching. Just pick a GPR based on
1860 // the size of a pointer.
1862 is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1863 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1864 OffsetOfLoc, Identifier, Info.OpDecl);
1867 enum IntelOperatorKind {
1873 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1874 /// returns the number of elements in an array. It returns the value 1 for
1875 /// non-array variables. The SIZE operator returns the size of a C or C++
1876 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1877 /// TYPE operator returns the size of a C or C++ type or variable. If the
1878 /// variable is an array, TYPE returns the size of a single element.
1879 X86Operand *X86AsmParser::ParseIntelOperator(unsigned OpKind) {
1880 const AsmToken &Tok = Parser.getTok();
1881 SMLoc TypeLoc = Tok.getLoc();
1882 Parser.Lex(); // Eat operator.
1884 const MCExpr *Val = 0;
1885 InlineAsmIdentifierInfo Info;
1886 SMLoc Start = Tok.getLoc(), End;
1887 StringRef Identifier = Tok.getString();
1888 if (ParseIntelIdentifier(Val, Identifier, Info,
1889 /*Unevaluated=*/true, End))
1893 return ErrorOperand(Start, "unable to lookup expression");
1897 default: llvm_unreachable("Unexpected operand kind!");
1898 case IOK_LENGTH: CVal = Info.Length; break;
1899 case IOK_SIZE: CVal = Info.Size; break;
1900 case IOK_TYPE: CVal = Info.Type; break;
1903 // Rewrite the type operator and the C or C++ type or variable in terms of an
1904 // immediate. E.g. TYPE foo -> $$4
1905 unsigned Len = End.getPointer() - TypeLoc.getPointer();
1906 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, CVal));
1908 const MCExpr *Imm = MCConstantExpr::Create(CVal, getContext());
1909 return X86Operand::CreateImm(Imm, Start, End);
1912 X86Operand *X86AsmParser::ParseIntelOperand() {
1913 const AsmToken &Tok = Parser.getTok();
1916 // Offset, length, type and size operators.
1917 if (isParsingInlineAsm()) {
1918 StringRef AsmTokStr = Tok.getString();
1919 if (AsmTokStr == "offset" || AsmTokStr == "OFFSET")
1920 return ParseIntelOffsetOfOperator();
1921 if (AsmTokStr == "length" || AsmTokStr == "LENGTH")
1922 return ParseIntelOperator(IOK_LENGTH);
1923 if (AsmTokStr == "size" || AsmTokStr == "SIZE")
1924 return ParseIntelOperator(IOK_SIZE);
1925 if (AsmTokStr == "type" || AsmTokStr == "TYPE")
1926 return ParseIntelOperator(IOK_TYPE);
1929 unsigned Size = getIntelMemOperandSize(Tok.getString());
1931 Parser.Lex(); // Eat operand size (e.g., byte, word).
1932 if (Tok.getString() != "PTR" && Tok.getString() != "ptr")
1933 return ErrorOperand(Start, "Expected 'PTR' or 'ptr' token!");
1934 Parser.Lex(); // Eat ptr.
1936 Start = Tok.getLoc();
1939 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Minus) ||
1940 getLexer().is(AsmToken::LParen)) {
1941 AsmToken StartTok = Tok;
1942 IntelExprStateMachine SM(/*Imm=*/0, /*StopOnLBrac=*/true,
1943 /*AddImmPrefix=*/false);
1944 if (ParseIntelExpression(SM, End))
1947 int64_t Imm = SM.getImm();
1948 if (isParsingInlineAsm()) {
1949 unsigned Len = Tok.getLoc().getPointer() - Start.getPointer();
1950 if (StartTok.getString().size() == Len)
1951 // Just add a prefix if this wasn't a complex immediate expression.
1952 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix, Start));
1954 // Otherwise, rewrite the complex expression as a single immediate.
1955 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, Start, Len, Imm));
1958 if (getLexer().isNot(AsmToken::LBrac)) {
1959 // If a directional label (ie. 1f or 2b) was parsed above from
1960 // ParseIntelExpression() then SM.getSym() was set to a pointer to
1961 // to the MCExpr with the directional local symbol and this is a
1962 // memory operand not an immediate operand.
1964 return X86Operand::CreateMem(SM.getSym(), Start, End, Size);
1966 const MCExpr *ImmExpr = MCConstantExpr::Create(Imm, getContext());
1967 return X86Operand::CreateImm(ImmExpr, Start, End);
1970 // Only positive immediates are valid.
1972 return ErrorOperand(Start, "expected a positive immediate displacement "
1973 "before bracketed expr.");
1975 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1976 return ParseIntelMemOperand(Imm, Start, Size);
1981 if (!ParseRegister(RegNo, Start, End)) {
1982 // If this is a segment register followed by a ':', then this is the start
1983 // of a segment override, otherwise this is a normal register reference.
1984 if (getLexer().isNot(AsmToken::Colon))
1985 return X86Operand::CreateReg(RegNo, Start, End);
1987 return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
1991 return ParseIntelMemOperand(/*Disp=*/0, Start, Size);
1994 X86Operand *X86AsmParser::ParseATTOperand() {
1995 switch (getLexer().getKind()) {
1997 // Parse a memory operand with no segment register.
1998 return ParseMemOperand(0, Parser.getTok().getLoc());
1999 case AsmToken::Percent: {
2000 // Read the register.
2003 if (ParseRegister(RegNo, Start, End)) return 0;
2004 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
2005 Error(Start, "%eiz and %riz can only be used as index registers",
2006 SMRange(Start, End));
2010 // If this is a segment register followed by a ':', then this is the start
2011 // of a memory reference, otherwise this is a normal register reference.
2012 if (getLexer().isNot(AsmToken::Colon))
2013 return X86Operand::CreateReg(RegNo, Start, End);
2015 getParser().Lex(); // Eat the colon.
2016 return ParseMemOperand(RegNo, Start);
2018 case AsmToken::Dollar: {
2019 // $42 -> immediate.
2020 SMLoc Start = Parser.getTok().getLoc(), End;
2023 if (getParser().parseExpression(Val, End))
2025 return X86Operand::CreateImm(Val, Start, End);
2030 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
2031 /// has already been parsed if present.
2032 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
2034 // We have to disambiguate a parenthesized expression "(4+5)" from the start
2035 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
2036 // only way to do this without lookahead is to eat the '(' and see what is
2038 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
2039 if (getLexer().isNot(AsmToken::LParen)) {
2041 if (getParser().parseExpression(Disp, ExprEnd)) return 0;
2043 // After parsing the base expression we could either have a parenthesized
2044 // memory address or not. If not, return now. If so, eat the (.
2045 if (getLexer().isNot(AsmToken::LParen)) {
2046 // Unless we have a segment register, treat this as an immediate.
2048 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
2049 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
2055 // Okay, we have a '('. We don't know if this is an expression or not, but
2056 // so we have to eat the ( to see beyond it.
2057 SMLoc LParenLoc = Parser.getTok().getLoc();
2058 Parser.Lex(); // Eat the '('.
2060 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
2061 // Nothing to do here, fall into the code below with the '(' part of the
2062 // memory operand consumed.
2066 // It must be an parenthesized expression, parse it now.
2067 if (getParser().parseParenExpression(Disp, ExprEnd))
2070 // After parsing the base expression we could either have a parenthesized
2071 // memory address or not. If not, return now. If so, eat the (.
2072 if (getLexer().isNot(AsmToken::LParen)) {
2073 // Unless we have a segment register, treat this as an immediate.
2075 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
2076 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
2084 // If we reached here, then we just ate the ( of the memory operand. Process
2085 // the rest of the memory operand.
2086 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
2087 SMLoc IndexLoc, BaseLoc;
2089 if (getLexer().is(AsmToken::Percent)) {
2090 SMLoc StartLoc, EndLoc;
2091 BaseLoc = Parser.getTok().getLoc();
2092 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
2093 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
2094 Error(StartLoc, "eiz and riz can only be used as index registers",
2095 SMRange(StartLoc, EndLoc));
2100 if (getLexer().is(AsmToken::Comma)) {
2101 Parser.Lex(); // Eat the comma.
2102 IndexLoc = Parser.getTok().getLoc();
2104 // Following the comma we should have either an index register, or a scale
2105 // value. We don't support the later form, but we want to parse it
2108 // Not that even though it would be completely consistent to support syntax
2109 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2110 if (getLexer().is(AsmToken::Percent)) {
2112 if (ParseRegister(IndexReg, L, L)) return 0;
2114 if (getLexer().isNot(AsmToken::RParen)) {
2115 // Parse the scale amount:
2116 // ::= ',' [scale-expression]
2117 if (getLexer().isNot(AsmToken::Comma)) {
2118 Error(Parser.getTok().getLoc(),
2119 "expected comma in scale expression");
2122 Parser.Lex(); // Eat the comma.
2124 if (getLexer().isNot(AsmToken::RParen)) {
2125 SMLoc Loc = Parser.getTok().getLoc();
2128 if (getParser().parseAbsoluteExpression(ScaleVal)){
2129 Error(Loc, "expected scale expression");
2133 // Validate the scale amount.
2134 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2136 Error(Loc, "scale factor in 16-bit address must be 1");
2139 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
2140 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
2143 Scale = (unsigned)ScaleVal;
2146 } else if (getLexer().isNot(AsmToken::RParen)) {
2147 // A scale amount without an index is ignored.
2149 SMLoc Loc = Parser.getTok().getLoc();
2152 if (getParser().parseAbsoluteExpression(Value))
2156 Warning(Loc, "scale factor without index register is ignored");
2161 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2162 if (getLexer().isNot(AsmToken::RParen)) {
2163 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
2166 SMLoc MemEnd = Parser.getTok().getEndLoc();
2167 Parser.Lex(); // Eat the ')'.
2169 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
2170 // and then only in non-64-bit modes. Except for DX, which is a special case
2171 // because an unofficial form of in/out instructions uses it.
2172 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2173 (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
2174 BaseReg != X86::SI && BaseReg != X86::DI)) &&
2175 BaseReg != X86::DX) {
2176 Error(BaseLoc, "invalid 16-bit base register");
2180 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2181 Error(IndexLoc, "16-bit memory operand may not include only index register");
2186 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
2187 Error(BaseLoc, ErrMsg);
2191 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
2196 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2197 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2199 StringRef PatchedName = Name;
2201 // FIXME: Hack to recognize setneb as setne.
2202 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2203 PatchedName != "setb" && PatchedName != "setnb")
2204 PatchedName = PatchedName.substr(0, Name.size()-1);
2206 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
2207 const MCExpr *ExtraImmOp = 0;
2208 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
2209 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2210 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
2211 bool IsVCMP = PatchedName[0] == 'v';
2212 unsigned SSECCIdx = IsVCMP ? 4 : 3;
2213 unsigned SSEComparisonCode = StringSwitch<unsigned>(
2214 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
2218 .Case("unord", 0x03)
2223 /* AVX only from here */
2224 .Case("eq_uq", 0x08)
2227 .Case("false", 0x0B)
2228 .Case("neq_oq", 0x0C)
2232 .Case("eq_os", 0x10)
2233 .Case("lt_oq", 0x11)
2234 .Case("le_oq", 0x12)
2235 .Case("unord_s", 0x13)
2236 .Case("neq_us", 0x14)
2237 .Case("nlt_uq", 0x15)
2238 .Case("nle_uq", 0x16)
2239 .Case("ord_s", 0x17)
2240 .Case("eq_us", 0x18)
2241 .Case("nge_uq", 0x19)
2242 .Case("ngt_uq", 0x1A)
2243 .Case("false_os", 0x1B)
2244 .Case("neq_os", 0x1C)
2245 .Case("ge_oq", 0x1D)
2246 .Case("gt_oq", 0x1E)
2247 .Case("true_us", 0x1F)
2249 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
2250 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
2251 getParser().getContext());
2252 if (PatchedName.endswith("ss")) {
2253 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
2254 } else if (PatchedName.endswith("sd")) {
2255 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
2256 } else if (PatchedName.endswith("ps")) {
2257 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
2259 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
2260 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
2265 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
2267 if (ExtraImmOp && !isParsingIntelSyntax())
2268 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
2270 // Determine whether this is an instruction prefix.
2272 Name == "lock" || Name == "rep" ||
2273 Name == "repe" || Name == "repz" ||
2274 Name == "repne" || Name == "repnz" ||
2275 Name == "rex64" || Name == "data16";
2278 // This does the actual operand parsing. Don't parse any more if we have a
2279 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2280 // just want to parse the "lock" as the first instruction and the "incl" as
2282 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
2284 // Parse '*' modifier.
2285 if (getLexer().is(AsmToken::Star))
2286 Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2288 // Read the first operand.
2289 if (X86Operand *Op = ParseOperand())
2290 Operands.push_back(Op);
2292 Parser.eatToEndOfStatement();
2296 while (getLexer().is(AsmToken::Comma)) {
2297 Parser.Lex(); // Eat the comma.
2299 // Parse and remember the operand.
2300 if (X86Operand *Op = ParseOperand())
2301 Operands.push_back(Op);
2303 Parser.eatToEndOfStatement();
2308 if (STI.getFeatureBits() & X86::FeatureAVX512) {
2309 // Parse mask register {%k1}
2310 if (getLexer().is(AsmToken::LCurly)) {
2311 Operands.push_back(X86Operand::CreateToken("{", consumeToken()));
2312 if (X86Operand *Op = ParseOperand()) {
2313 Operands.push_back(Op);
2314 if (!getLexer().is(AsmToken::RCurly)) {
2315 SMLoc Loc = getLexer().getLoc();
2316 Parser.eatToEndOfStatement();
2317 return Error(Loc, "Expected } at this point");
2319 Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2321 Parser.eatToEndOfStatement();
2325 // TODO: add parsing of broadcasts {1to8}, {1to16}
2326 // Parse "zeroing non-masked" semantic {z}
2327 if (getLexer().is(AsmToken::LCurly)) {
2328 Operands.push_back(X86Operand::CreateToken("{z}", consumeToken()));
2329 if (!getLexer().is(AsmToken::Identifier) || getLexer().getTok().getIdentifier() != "z") {
2330 SMLoc Loc = getLexer().getLoc();
2331 Parser.eatToEndOfStatement();
2332 return Error(Loc, "Expected z at this point");
2334 Parser.Lex(); // Eat the z
2335 if (!getLexer().is(AsmToken::RCurly)) {
2336 SMLoc Loc = getLexer().getLoc();
2337 Parser.eatToEndOfStatement();
2338 return Error(Loc, "Expected } at this point");
2340 Parser.Lex(); // Eat the }
2344 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2345 SMLoc Loc = getLexer().getLoc();
2346 Parser.eatToEndOfStatement();
2347 return Error(Loc, "unexpected token in argument list");
2351 if (getLexer().is(AsmToken::EndOfStatement))
2352 Parser.Lex(); // Consume the EndOfStatement
2353 else if (isPrefix && getLexer().is(AsmToken::Slash))
2354 Parser.Lex(); // Consume the prefix separator Slash
2356 if (ExtraImmOp && isParsingIntelSyntax())
2357 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
2359 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
2360 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2361 // documented form in various unofficial manuals, so a lot of code uses it.
2362 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
2363 Operands.size() == 3) {
2364 X86Operand &Op = *(X86Operand*)Operands.back();
2365 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2366 isa<MCConstantExpr>(Op.Mem.Disp) &&
2367 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2368 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2369 SMLoc Loc = Op.getEndLoc();
2370 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2374 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
2375 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
2376 Operands.size() == 3) {
2377 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2378 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2379 isa<MCConstantExpr>(Op.Mem.Disp) &&
2380 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2381 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2382 SMLoc Loc = Op.getEndLoc();
2383 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2388 // Append default arguments to "ins[bwld]"
2389 if (Name.startswith("ins") && Operands.size() == 1 &&
2390 (Name == "insb" || Name == "insw" || Name == "insl" ||
2392 if (isParsingIntelSyntax()) {
2393 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2394 Operands.push_back(DefaultMemDIOperand(NameLoc));
2396 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2397 Operands.push_back(DefaultMemDIOperand(NameLoc));
2401 // Append default arguments to "outs[bwld]"
2402 if (Name.startswith("outs") && Operands.size() == 1 &&
2403 (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
2404 Name == "outsd" )) {
2405 if (isParsingIntelSyntax()) {
2406 Operands.push_back(DefaultMemSIOperand(NameLoc));
2407 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2409 Operands.push_back(DefaultMemSIOperand(NameLoc));
2410 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2414 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2415 // values of $SIREG according to the mode. It would be nice if this
2416 // could be achieved with InstAlias in the tables.
2417 if (Name.startswith("lods") && Operands.size() == 1 &&
2418 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2419 Name == "lodsl" || Name == "lodsd" || Name == "lodsq"))
2420 Operands.push_back(DefaultMemSIOperand(NameLoc));
2422 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2423 // values of $DIREG according to the mode. It would be nice if this
2424 // could be achieved with InstAlias in the tables.
2425 if (Name.startswith("stos") && Operands.size() == 1 &&
2426 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2427 Name == "stosl" || Name == "stosd" || Name == "stosq"))
2428 Operands.push_back(DefaultMemDIOperand(NameLoc));
2430 // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2431 // values of $DIREG according to the mode. It would be nice if this
2432 // could be achieved with InstAlias in the tables.
2433 if (Name.startswith("scas") && Operands.size() == 1 &&
2434 (Name == "scas" || Name == "scasb" || Name == "scasw" ||
2435 Name == "scasl" || Name == "scasd" || Name == "scasq"))
2436 Operands.push_back(DefaultMemDIOperand(NameLoc));
2438 // Add default SI and DI operands to "cmps[bwlq]".
2439 if (Name.startswith("cmps") &&
2440 (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
2441 Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
2442 if (Operands.size() == 1) {
2443 if (isParsingIntelSyntax()) {
2444 Operands.push_back(DefaultMemSIOperand(NameLoc));
2445 Operands.push_back(DefaultMemDIOperand(NameLoc));
2447 Operands.push_back(DefaultMemDIOperand(NameLoc));
2448 Operands.push_back(DefaultMemSIOperand(NameLoc));
2450 } else if (Operands.size() == 3) {
2451 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2452 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2453 if (!doSrcDstMatch(Op, Op2))
2454 return Error(Op.getStartLoc(),
2455 "mismatching source and destination index registers");
2459 // Add default SI and DI operands to "movs[bwlq]".
2460 if ((Name.startswith("movs") &&
2461 (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2462 Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2463 (Name.startswith("smov") &&
2464 (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2465 Name == "smovl" || Name == "smovd" || Name == "smovq"))) {
2466 if (Operands.size() == 1) {
2467 if (Name == "movsd")
2468 Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2469 if (isParsingIntelSyntax()) {
2470 Operands.push_back(DefaultMemDIOperand(NameLoc));
2471 Operands.push_back(DefaultMemSIOperand(NameLoc));
2473 Operands.push_back(DefaultMemSIOperand(NameLoc));
2474 Operands.push_back(DefaultMemDIOperand(NameLoc));
2476 } else if (Operands.size() == 3) {
2477 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2478 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2479 if (!doSrcDstMatch(Op, Op2))
2480 return Error(Op.getStartLoc(),
2481 "mismatching source and destination index registers");
2485 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2487 if ((Name.startswith("shr") || Name.startswith("sar") ||
2488 Name.startswith("shl") || Name.startswith("sal") ||
2489 Name.startswith("rcl") || Name.startswith("rcr") ||
2490 Name.startswith("rol") || Name.startswith("ror")) &&
2491 Operands.size() == 3) {
2492 if (isParsingIntelSyntax()) {
2494 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
2495 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2496 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2498 Operands.pop_back();
2501 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2502 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2503 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2505 Operands.erase(Operands.begin() + 1);
2510 // Transforms "int $3" into "int3" as a size optimization. We can't write an
2511 // instalias with an immediate operand yet.
2512 if (Name == "int" && Operands.size() == 2) {
2513 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2514 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2515 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
2517 Operands.erase(Operands.begin() + 1);
2518 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
2525 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
2528 TmpInst.setOpcode(Opcode);
2530 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2531 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2532 TmpInst.addOperand(Inst.getOperand(0));
2537 static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
2538 bool isCmp = false) {
2539 if (!Inst.getOperand(0).isImm() ||
2540 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
2543 return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2546 static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
2547 bool isCmp = false) {
2548 if (!Inst.getOperand(0).isImm() ||
2549 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
2552 return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2555 static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
2556 bool isCmp = false) {
2557 if (!Inst.getOperand(0).isImm() ||
2558 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
2561 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2565 processInstruction(MCInst &Inst,
2566 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
2567 switch (Inst.getOpcode()) {
2568 default: return false;
2569 case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2570 case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2571 case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2572 case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2573 case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2574 case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2575 case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
2576 case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
2577 case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
2578 case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2579 case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2580 case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2581 case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2582 case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2583 case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2584 case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2585 case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2586 case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2587 case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2588 case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2589 case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2590 case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2591 case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2592 case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2593 case X86::VMOVAPDrr:
2594 case X86::VMOVAPDYrr:
2595 case X86::VMOVAPSrr:
2596 case X86::VMOVAPSYrr:
2597 case X86::VMOVDQArr:
2598 case X86::VMOVDQAYrr:
2599 case X86::VMOVDQUrr:
2600 case X86::VMOVDQUYrr:
2601 case X86::VMOVUPDrr:
2602 case X86::VMOVUPDYrr:
2603 case X86::VMOVUPSrr:
2604 case X86::VMOVUPSYrr: {
2605 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2606 !X86II::isX86_64ExtendedReg(Inst.getOperand(1).getReg()))
2610 switch (Inst.getOpcode()) {
2611 default: llvm_unreachable("Invalid opcode");
2612 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2613 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2614 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2615 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2616 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2617 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2618 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2619 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2620 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2621 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2622 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2623 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2625 Inst.setOpcode(NewOpc);
2629 case X86::VMOVSSrr: {
2630 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2631 !X86II::isX86_64ExtendedReg(Inst.getOperand(2).getReg()))
2634 switch (Inst.getOpcode()) {
2635 default: llvm_unreachable("Invalid opcode");
2636 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
2637 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
2639 Inst.setOpcode(NewOpc);
2645 static const char *getSubtargetFeatureName(unsigned Val);
2647 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2648 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2649 MCStreamer &Out, unsigned &ErrorInfo,
2650 bool MatchingInlineAsm) {
2651 assert(!Operands.empty() && "Unexpect empty operand list!");
2652 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
2653 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
2654 ArrayRef<SMRange> EmptyRanges = None;
2656 // First, handle aliases that expand to multiple instructions.
2657 // FIXME: This should be replaced with a real .td file alias mechanism.
2658 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2660 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
2661 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
2662 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
2663 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
2665 Inst.setOpcode(X86::WAIT);
2667 if (!MatchingInlineAsm)
2668 Out.EmitInstruction(Inst, STI);
2671 StringSwitch<const char*>(Op->getToken())
2672 .Case("finit", "fninit")
2673 .Case("fsave", "fnsave")
2674 .Case("fstcw", "fnstcw")
2675 .Case("fstcww", "fnstcw")
2676 .Case("fstenv", "fnstenv")
2677 .Case("fstsw", "fnstsw")
2678 .Case("fstsww", "fnstsw")
2679 .Case("fclex", "fnclex")
2681 assert(Repl && "Unknown wait-prefixed instruction");
2683 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2686 bool WasOriginallyInvalidOperand = false;
2689 // First, try a direct match.
2690 switch (MatchInstructionImpl(Operands, Inst,
2691 ErrorInfo, MatchingInlineAsm,
2692 isParsingIntelSyntax())) {
2695 // Some instructions need post-processing to, for example, tweak which
2696 // encoding is selected. Loop on it while changes happen so the
2697 // individual transformations can chain off each other.
2698 if (!MatchingInlineAsm)
2699 while (processInstruction(Inst, Operands))
2703 if (!MatchingInlineAsm)
2704 Out.EmitInstruction(Inst, STI);
2705 Opcode = Inst.getOpcode();
2707 case Match_MissingFeature: {
2708 assert(ErrorInfo && "Unknown missing feature!");
2709 // Special case the error message for the very common case where only
2710 // a single subtarget feature is missing.
2711 std::string Msg = "instruction requires:";
2713 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2714 if (ErrorInfo & Mask) {
2716 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
2720 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2722 case Match_InvalidOperand:
2723 WasOriginallyInvalidOperand = true;
2725 case Match_MnemonicFail:
2729 // FIXME: Ideally, we would only attempt suffix matches for things which are
2730 // valid prefixes, and we could just infer the right unambiguous
2731 // type. However, that requires substantially more matcher support than the
2734 // Change the operand to point to a temporary token.
2735 StringRef Base = Op->getToken();
2736 SmallString<16> Tmp;
2739 Op->setTokenValue(Tmp.str());
2741 // If this instruction starts with an 'f', then it is a floating point stack
2742 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2743 // 80-bit floating point, which use the suffixes s,l,t respectively.
2745 // Otherwise, we assume that this may be an integer instruction, which comes
2746 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2747 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2749 // Check for the various suffix matches.
2750 Tmp[Base.size()] = Suffixes[0];
2751 unsigned ErrorInfoIgnore;
2752 unsigned ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2753 unsigned Match1, Match2, Match3, Match4;
2755 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2756 MatchingInlineAsm, isParsingIntelSyntax());
2757 // If this returned as a missing feature failure, remember that.
2758 if (Match1 == Match_MissingFeature)
2759 ErrorInfoMissingFeature = ErrorInfoIgnore;
2760 Tmp[Base.size()] = Suffixes[1];
2761 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2762 MatchingInlineAsm, isParsingIntelSyntax());
2763 // If this returned as a missing feature failure, remember that.
2764 if (Match2 == Match_MissingFeature)
2765 ErrorInfoMissingFeature = ErrorInfoIgnore;
2766 Tmp[Base.size()] = Suffixes[2];
2767 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2768 MatchingInlineAsm, isParsingIntelSyntax());
2769 // If this returned as a missing feature failure, remember that.
2770 if (Match3 == Match_MissingFeature)
2771 ErrorInfoMissingFeature = ErrorInfoIgnore;
2772 Tmp[Base.size()] = Suffixes[3];
2773 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2774 MatchingInlineAsm, isParsingIntelSyntax());
2775 // If this returned as a missing feature failure, remember that.
2776 if (Match4 == Match_MissingFeature)
2777 ErrorInfoMissingFeature = ErrorInfoIgnore;
2779 // Restore the old token.
2780 Op->setTokenValue(Base);
2782 // If exactly one matched, then we treat that as a successful match (and the
2783 // instruction will already have been filled in correctly, since the failing
2784 // matches won't have modified it).
2785 unsigned NumSuccessfulMatches =
2786 (Match1 == Match_Success) + (Match2 == Match_Success) +
2787 (Match3 == Match_Success) + (Match4 == Match_Success);
2788 if (NumSuccessfulMatches == 1) {
2790 if (!MatchingInlineAsm)
2791 Out.EmitInstruction(Inst, STI);
2792 Opcode = Inst.getOpcode();
2796 // Otherwise, the match failed, try to produce a decent error message.
2798 // If we had multiple suffix matches, then identify this as an ambiguous
2800 if (NumSuccessfulMatches > 1) {
2802 unsigned NumMatches = 0;
2803 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
2804 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
2805 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
2806 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
2808 SmallString<126> Msg;
2809 raw_svector_ostream OS(Msg);
2810 OS << "ambiguous instructions require an explicit suffix (could be ";
2811 for (unsigned i = 0; i != NumMatches; ++i) {
2814 if (i + 1 == NumMatches)
2816 OS << "'" << Base << MatchChars[i] << "'";
2819 Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
2823 // Okay, we know that none of the variants matched successfully.
2825 // If all of the instructions reported an invalid mnemonic, then the original
2826 // mnemonic was invalid.
2827 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
2828 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
2829 if (!WasOriginallyInvalidOperand) {
2830 ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
2832 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2833 Ranges, MatchingInlineAsm);
2836 // Recover location info for the operand if we know which was the problem.
2837 if (ErrorInfo != ~0U) {
2838 if (ErrorInfo >= Operands.size())
2839 return Error(IDLoc, "too few operands for instruction",
2840 EmptyRanges, MatchingInlineAsm);
2842 X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
2843 if (Operand->getStartLoc().isValid()) {
2844 SMRange OperandRange = Operand->getLocRange();
2845 return Error(Operand->getStartLoc(), "invalid operand for instruction",
2846 OperandRange, MatchingInlineAsm);
2850 return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2854 // If one instruction matched with a missing feature, report this as a
2856 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
2857 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
2858 std::string Msg = "instruction requires:";
2860 for (unsigned i = 0; i < (sizeof(ErrorInfoMissingFeature)*8-1); ++i) {
2861 if (ErrorInfoMissingFeature & Mask) {
2863 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2867 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2870 // If one instruction matched with an invalid operand, report this as an
2872 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
2873 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
2874 Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2879 // If all of these were an outright failure, report it in a useless way.
2880 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2881 EmptyRanges, MatchingInlineAsm);
2886 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
2887 StringRef IDVal = DirectiveID.getIdentifier();
2888 if (IDVal == ".word")
2889 return ParseDirectiveWord(2, DirectiveID.getLoc());
2890 else if (IDVal.startswith(".code"))
2891 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
2892 else if (IDVal.startswith(".att_syntax")) {
2893 getParser().setAssemblerDialect(0);
2895 } else if (IDVal.startswith(".intel_syntax")) {
2896 getParser().setAssemblerDialect(1);
2897 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2898 // FIXME: Handle noprefix
2899 if (Parser.getTok().getString() == "noprefix")
2907 /// ParseDirectiveWord
2908 /// ::= .word [ expression (, expression)* ]
2909 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2910 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2912 const MCExpr *Value;
2913 if (getParser().parseExpression(Value))
2916 getParser().getStreamer().EmitValue(Value, Size);
2918 if (getLexer().is(AsmToken::EndOfStatement))
2921 // FIXME: Improve diagnostic.
2922 if (getLexer().isNot(AsmToken::Comma)) {
2923 Error(L, "unexpected token in directive");
2934 /// ParseDirectiveCode
2935 /// ::= .code16 | .code32 | .code64
2936 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
2937 if (IDVal == ".code16") {
2939 if (!is16BitMode()) {
2940 SwitchMode(X86::Mode16Bit);
2941 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2943 } else if (IDVal == ".code32") {
2945 if (!is32BitMode()) {
2946 SwitchMode(X86::Mode32Bit);
2947 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2949 } else if (IDVal == ".code64") {
2951 if (!is64BitMode()) {
2952 SwitchMode(X86::Mode64Bit);
2953 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
2956 Error(L, "unknown directive " + IDVal);
2963 // Force static initialization.
2964 extern "C" void LLVMInitializeX86AsmParser() {
2965 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2966 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2969 #define GET_REGISTER_MATCHER
2970 #define GET_MATCHER_IMPLEMENTATION
2971 #define GET_SUBTARGET_FEATURE_NAME
2972 #include "X86GenAsmMatcher.inc"