1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "llvm/ADT/SmallVector.h"
12 #include "llvm/ADT/Twine.h"
13 #include "llvm/MC/MCAsmLexer.h"
14 #include "llvm/MC/MCAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParsedAsmOperand.h"
19 #include "llvm/Support/SourceMgr.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Target/TargetAsmParser.h"
27 class X86ATTAsmParser : public TargetAsmParser {
31 MCAsmParser &getParser() const { return Parser; }
33 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
35 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
37 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
39 bool ParseRegister(X86Operand &Op);
41 bool ParseOperand(X86Operand &Op);
43 bool ParseMemOperand(X86Operand &Op);
45 bool ParseDirectiveWord(unsigned Size, SMLoc L);
47 /// @name Auto-generated Match Functions
50 bool MatchInstruction(SmallVectorImpl<X86Operand> &Operands,
53 /// MatchRegisterName - Match the given string to a register name, or 0 if
54 /// there is no match.
55 unsigned MatchRegisterName(const StringRef &Name);
60 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
61 : TargetAsmParser(T), Parser(_Parser) {}
63 virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
66 virtual bool ParseDirective(AsmToken DirectiveID);
69 } // end anonymous namespace
74 /// X86Operand - Instances of this class represent a parsed X86 machine
76 struct X86Operand : public MCParsedAsmOperand {
107 StringRef getToken() const {
108 assert(Kind == Token && "Invalid access!");
109 return StringRef(Tok.Data, Tok.Length);
112 unsigned getReg() const {
113 assert(Kind == Register && "Invalid access!");
117 const MCExpr *getImm() const {
118 assert(Kind == Immediate && "Invalid access!");
122 const MCExpr *getMemDisp() const {
123 assert(Kind == Memory && "Invalid access!");
126 unsigned getMemSegReg() const {
127 assert(Kind == Memory && "Invalid access!");
130 unsigned getMemBaseReg() const {
131 assert(Kind == Memory && "Invalid access!");
134 unsigned getMemIndexReg() const {
135 assert(Kind == Memory && "Invalid access!");
138 unsigned getMemScale() const {
139 assert(Kind == Memory && "Invalid access!");
143 bool isToken() const {return Kind == Token; }
145 bool isImm() const { return Kind == Immediate; }
147 bool isImmSExt8() const {
148 // Accept immediates which fit in 8 bits when sign extended, and
149 // non-absolute immediates.
153 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
154 int64_t Value = CE->getValue();
155 return Value == (int64_t) (int8_t) Value;
161 bool isMem() const { return Kind == Memory; }
163 bool isReg() const { return Kind == Register; }
165 void addRegOperands(MCInst &Inst, unsigned N) const {
166 assert(N == 1 && "Invalid number of operands!");
167 Inst.addOperand(MCOperand::CreateReg(getReg()));
170 void addImmOperands(MCInst &Inst, unsigned N) const {
171 assert(N == 1 && "Invalid number of operands!");
172 Inst.addOperand(MCOperand::CreateExpr(getImm()));
175 void addImmSExt8Operands(MCInst &Inst, unsigned N) const {
176 // FIXME: Support user customization of the render method.
177 assert(N == 1 && "Invalid number of operands!");
178 Inst.addOperand(MCOperand::CreateExpr(getImm()));
181 void addMemOperands(MCInst &Inst, unsigned N) const {
182 assert((N == 4 || N == 5) && "Invalid number of operands!");
184 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
185 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
186 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
187 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
189 // FIXME: What a hack.
191 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
194 static X86Operand CreateToken(StringRef Str) {
197 Res.Tok.Data = Str.data();
198 Res.Tok.Length = Str.size();
202 static X86Operand CreateReg(unsigned RegNo) {
205 Res.Reg.RegNo = RegNo;
209 static X86Operand CreateImm(const MCExpr *Val) {
211 Res.Kind = Immediate;
216 static X86Operand CreateMem(unsigned SegReg, const MCExpr *Disp,
217 unsigned BaseReg, unsigned IndexReg,
219 // We should never just have a displacement, that would be an immediate.
220 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
222 // The scale should always be one of {1,2,4,8}.
223 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
227 Res.Mem.SegReg = SegReg;
229 Res.Mem.BaseReg = BaseReg;
230 Res.Mem.IndexReg = IndexReg;
231 Res.Mem.Scale = Scale;
236 } // end anonymous namespace.
239 bool X86ATTAsmParser::ParseRegister(X86Operand &Op) {
240 const AsmToken &TokPercent = getLexer().getTok();
241 (void)TokPercent; // Avoid warning when assertions are disabled.
242 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
243 getLexer().Lex(); // Eat percent token.
245 const AsmToken &Tok = getLexer().getTok();
246 if (Tok.isNot(AsmToken::Identifier))
247 return Error(Tok.getLoc(), "invalid register name");
249 // FIXME: Validate register for the current architecture; we have to do
250 // validation later, so maybe there is no need for this here.
253 RegNo = MatchRegisterName(Tok.getString());
255 return Error(Tok.getLoc(), "invalid register name");
257 Op = X86Operand::CreateReg(RegNo);
258 getLexer().Lex(); // Eat identifier token.
263 bool X86ATTAsmParser::ParseOperand(X86Operand &Op) {
264 switch (getLexer().getKind()) {
266 return ParseMemOperand(Op);
267 case AsmToken::Percent:
268 // FIXME: if a segment register, this could either be just the seg reg, or
269 // the start of a memory operand.
270 return ParseRegister(Op);
271 case AsmToken::Dollar: {
275 if (getParser().ParseExpression(Val))
277 Op = X86Operand::CreateImm(Val);
283 /// ParseMemOperand: segment: disp(basereg, indexreg, scale)
284 bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
285 // FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
288 // We have to disambiguate a parenthesized expression "(4+5)" from the start
289 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
290 // only way to do this without lookahead is to eat the ( and see what is after
292 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
293 if (getLexer().isNot(AsmToken::LParen)) {
294 if (getParser().ParseExpression(Disp)) return true;
296 // After parsing the base expression we could either have a parenthesized
297 // memory address or not. If not, return now. If so, eat the (.
298 if (getLexer().isNot(AsmToken::LParen)) {
299 // Unless we have a segment register, treat this as an immediate.
301 Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
303 Op = X86Operand::CreateImm(Disp);
310 // Okay, we have a '('. We don't know if this is an expression or not, but
311 // so we have to eat the ( to see beyond it.
312 getLexer().Lex(); // Eat the '('.
314 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
315 // Nothing to do here, fall into the code below with the '(' part of the
316 // memory operand consumed.
318 // It must be an parenthesized expression, parse it now.
319 if (getParser().ParseParenExpression(Disp))
322 // After parsing the base expression we could either have a parenthesized
323 // memory address or not. If not, return now. If so, eat the (.
324 if (getLexer().isNot(AsmToken::LParen)) {
325 // Unless we have a segment register, treat this as an immediate.
327 Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
329 Op = X86Operand::CreateImm(Disp);
338 // If we reached here, then we just ate the ( of the memory operand. Process
339 // the rest of the memory operand.
340 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
342 if (getLexer().is(AsmToken::Percent)) {
343 if (ParseRegister(Op))
345 BaseReg = Op.getReg();
348 if (getLexer().is(AsmToken::Comma)) {
349 getLexer().Lex(); // Eat the comma.
351 // Following the comma we should have either an index register, or a scale
352 // value. We don't support the later form, but we want to parse it
355 // Not that even though it would be completely consistent to support syntax
356 // like "1(%eax,,1)", the assembler doesn't.
357 if (getLexer().is(AsmToken::Percent)) {
358 if (ParseRegister(Op))
360 IndexReg = Op.getReg();
362 if (getLexer().isNot(AsmToken::RParen)) {
363 // Parse the scale amount:
364 // ::= ',' [scale-expression]
365 if (getLexer().isNot(AsmToken::Comma))
367 getLexer().Lex(); // Eat the comma.
369 if (getLexer().isNot(AsmToken::RParen)) {
370 SMLoc Loc = getLexer().getTok().getLoc();
373 if (getParser().ParseAbsoluteExpression(ScaleVal))
376 // Validate the scale amount.
377 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8)
378 return Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
379 Scale = (unsigned)ScaleVal;
382 } else if (getLexer().isNot(AsmToken::RParen)) {
383 // Otherwise we have the unsupported form of a scale amount without an
385 SMLoc Loc = getLexer().getTok().getLoc();
388 if (getParser().ParseAbsoluteExpression(Value))
391 return Error(Loc, "cannot have scale factor without index register");
395 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
396 if (getLexer().isNot(AsmToken::RParen))
397 return Error(getLexer().getTok().getLoc(),
398 "unexpected token in memory operand");
399 getLexer().Lex(); // Eat the ')'.
401 Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
405 bool X86ATTAsmParser::ParseInstruction(const StringRef &Name,
406 SMLoc NameLoc, MCInst &Inst) {
407 SmallVector<X86Operand, 8> Operands;
409 Operands.push_back(X86Operand::CreateToken(Name));
411 SMLoc Loc = getLexer().getTok().getLoc();
412 if (getLexer().isNot(AsmToken::EndOfStatement)) {
414 // Parse '*' modifier.
415 if (getLexer().is(AsmToken::Star)) {
416 getLexer().Lex(); // Eat the star.
417 Operands.push_back(X86Operand::CreateToken("*"));
420 // Read the first operand.
421 Operands.push_back(X86Operand());
422 if (ParseOperand(Operands.back()))
425 while (getLexer().is(AsmToken::Comma)) {
426 getLexer().Lex(); // Eat the comma.
428 // Parse and remember the operand.
429 Operands.push_back(X86Operand());
430 if (ParseOperand(Operands.back()))
435 if (!MatchInstruction(Operands, Inst))
438 // FIXME: We should give nicer diagnostics about the exact failure.
440 Error(Loc, "unrecognized instruction");
444 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
445 StringRef IDVal = DirectiveID.getIdentifier();
446 if (IDVal == ".word")
447 return ParseDirectiveWord(2, DirectiveID.getLoc());
451 /// ParseDirectiveWord
452 /// ::= .word [ expression (, expression)* ]
453 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
454 if (getLexer().isNot(AsmToken::EndOfStatement)) {
457 if (getParser().ParseExpression(Value))
460 getParser().getStreamer().EmitValue(Value, Size);
462 if (getLexer().is(AsmToken::EndOfStatement))
465 // FIXME: Improve diagnostic.
466 if (getLexer().isNot(AsmToken::Comma))
467 return Error(L, "unexpected token in directive");
476 // Force static initialization.
477 extern "C" void LLVMInitializeX86AsmParser() {
478 RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
479 RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
482 #include "X86GenAsmMatcher.inc"