1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDMemBarrier : SDTypeProfile<0, 5, [
189 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
193 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
194 SDTypeProfile<0, 1, constraints>;
195 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
196 SDTypeProfile<0, 2, constraints>;
198 //===----------------------------------------------------------------------===//
199 // Selection DAG Node Properties.
201 // Note: These are hard coded into tblgen.
203 class SDNodeProperty;
204 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
205 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
206 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
207 def SDNPOutFlag : SDNodeProperty; // Write a flag result
208 def SDNPInFlag : SDNodeProperty; // Read a flag operand
209 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
210 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
211 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
212 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
214 //===----------------------------------------------------------------------===//
215 // Selection DAG Node definitions.
217 class SDNode<string opcode, SDTypeProfile typeprof,
218 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
219 string Opcode = opcode;
220 string SDClass = sdclass;
221 list<SDNodeProperty> Properties = props;
222 SDTypeProfile TypeProfile = typeprof;
231 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
232 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
233 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
234 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
235 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
236 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
237 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
238 "GlobalAddressSDNode">;
239 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
240 "GlobalAddressSDNode">;
241 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
242 "GlobalAddressSDNode">;
243 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
244 "GlobalAddressSDNode">;
245 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
246 "ConstantPoolSDNode">;
247 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
248 "ConstantPoolSDNode">;
249 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
251 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
253 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
255 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
257 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
258 "ExternalSymbolSDNode">;
259 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
260 "ExternalSymbolSDNode">;
262 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
263 [SDNPCommutative, SDNPAssociative]>;
264 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
265 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
266 [SDNPCommutative, SDNPAssociative]>;
267 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
268 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
269 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
270 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
271 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
272 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
273 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
274 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
275 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
276 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
277 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
278 def and : SDNode<"ISD::AND" , SDTIntBinOp,
279 [SDNPCommutative, SDNPAssociative]>;
280 def or : SDNode<"ISD::OR" , SDTIntBinOp,
281 [SDNPCommutative, SDNPAssociative]>;
282 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
283 [SDNPCommutative, SDNPAssociative]>;
284 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
285 [SDNPCommutative, SDNPOutFlag]>;
286 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
287 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
288 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
290 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
291 [SDNPOutFlag, SDNPInFlag]>;
293 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
294 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
295 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
296 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
297 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
298 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
299 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
300 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
301 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
302 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
303 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
304 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
307 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
308 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
309 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
310 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
311 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
312 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
313 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
314 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
315 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
316 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
318 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
319 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
320 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
322 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
323 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
324 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
325 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
327 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
328 def select : SDNode<"ISD::SELECT" , SDTSelect>;
329 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
331 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
332 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
333 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
334 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
335 def trap : SDNode<"ISD::TRAP" , SDTNone,
336 [SDNPHasChain, SDNPSideEffect]>;
337 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
338 [SDNPHasChain, SDNPSideEffect]>;
340 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
341 // and truncst (see below).
342 def ld : SDNode<"ISD::LOAD" , SDTLoad,
343 [SDNPHasChain, SDNPMayLoad]>;
344 def st : SDNode<"ISD::STORE" , SDTStore,
345 [SDNPHasChain, SDNPMayStore]>;
346 def ist : SDNode<"ISD::STORE" , SDTIStore,
347 [SDNPHasChain, SDNPMayStore]>;
349 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
350 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
351 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
353 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
354 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
355 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
356 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
358 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
359 SDTypeProfile<1, 2, []>>;
360 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
361 SDTypeProfile<1, 3, []>>;
363 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
364 // these internally. Don't reference these directly.
365 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
366 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
368 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
369 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
371 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
372 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
375 //===----------------------------------------------------------------------===//
376 // Selection DAG Condition Codes
378 class CondCode; // ISD::CondCode enums
379 def SETOEQ : CondCode; def SETOGT : CondCode;
380 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
381 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
382 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
383 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
385 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
386 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
389 //===----------------------------------------------------------------------===//
390 // Selection DAG Node Transformation Functions.
392 // This mechanism allows targets to manipulate nodes in the output DAG once a
393 // match has been formed. This is typically used to manipulate immediate
396 class SDNodeXForm<SDNode opc, code xformFunction> {
398 code XFormFunction = xformFunction;
401 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
404 //===----------------------------------------------------------------------===//
405 // Selection DAG Pattern Fragments.
407 // Pattern fragments are reusable chunks of dags that match specific things.
408 // They can take arguments and have C++ predicates that control whether they
409 // match. They are intended to make the patterns for common instructions more
410 // compact and readable.
413 /// PatFrag - Represents a pattern fragment. This can match something on the
414 /// DAG, frame a single node to multiply nested other fragments.
416 class PatFrag<dag ops, dag frag, code pred = [{}],
417 SDNodeXForm xform = NOOP_SDNodeXForm> {
420 code Predicate = pred;
421 SDNodeXForm OperandTransform = xform;
424 // PatLeaf's are pattern fragments that have no operands. This is just a helper
425 // to define immediates and other common things concisely.
426 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
427 : PatFrag<(ops), frag, pred, xform>;
431 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
432 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
434 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
435 def immAllOnesV: PatLeaf<(build_vector), [{
436 return ISD::isBuildVectorAllOnes(N);
438 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
439 return ISD::isBuildVectorAllOnes(N);
441 def immAllZerosV: PatLeaf<(build_vector), [{
442 return ISD::isBuildVectorAllZeros(N);
444 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
445 return ISD::isBuildVectorAllZeros(N);
450 // Other helper fragments.
451 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
452 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
453 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
454 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
457 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
458 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
459 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
460 LD->getAddressingMode() == ISD::UNINDEXED;
464 // extending load fragments.
465 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
466 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
467 return LD->getExtensionType() == ISD::EXTLOAD &&
468 LD->getAddressingMode() == ISD::UNINDEXED &&
469 LD->getMemoryVT() == MVT::i1;
472 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
473 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
474 return LD->getExtensionType() == ISD::EXTLOAD &&
475 LD->getAddressingMode() == ISD::UNINDEXED &&
476 LD->getMemoryVT() == MVT::i8;
479 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
480 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
481 return LD->getExtensionType() == ISD::EXTLOAD &&
482 LD->getAddressingMode() == ISD::UNINDEXED &&
483 LD->getMemoryVT() == MVT::i16;
486 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
487 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
488 return LD->getExtensionType() == ISD::EXTLOAD &&
489 LD->getAddressingMode() == ISD::UNINDEXED &&
490 LD->getMemoryVT() == MVT::i32;
493 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
494 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
495 return LD->getExtensionType() == ISD::EXTLOAD &&
496 LD->getAddressingMode() == ISD::UNINDEXED &&
497 LD->getMemoryVT() == MVT::f32;
500 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
501 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
502 return LD->getExtensionType() == ISD::EXTLOAD &&
503 LD->getAddressingMode() == ISD::UNINDEXED &&
504 LD->getMemoryVT() == MVT::f64;
508 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
509 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
510 return LD->getExtensionType() == ISD::SEXTLOAD &&
511 LD->getAddressingMode() == ISD::UNINDEXED &&
512 LD->getMemoryVT() == MVT::i1;
515 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
516 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
517 return LD->getExtensionType() == ISD::SEXTLOAD &&
518 LD->getAddressingMode() == ISD::UNINDEXED &&
519 LD->getMemoryVT() == MVT::i8;
522 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
523 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
524 return LD->getExtensionType() == ISD::SEXTLOAD &&
525 LD->getAddressingMode() == ISD::UNINDEXED &&
526 LD->getMemoryVT() == MVT::i16;
529 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
530 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
531 return LD->getExtensionType() == ISD::SEXTLOAD &&
532 LD->getAddressingMode() == ISD::UNINDEXED &&
533 LD->getMemoryVT() == MVT::i32;
537 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
538 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
539 return LD->getExtensionType() == ISD::ZEXTLOAD &&
540 LD->getAddressingMode() == ISD::UNINDEXED &&
541 LD->getMemoryVT() == MVT::i1;
544 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
545 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
546 return LD->getExtensionType() == ISD::ZEXTLOAD &&
547 LD->getAddressingMode() == ISD::UNINDEXED &&
548 LD->getMemoryVT() == MVT::i8;
551 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
552 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
553 return LD->getExtensionType() == ISD::ZEXTLOAD &&
554 LD->getAddressingMode() == ISD::UNINDEXED &&
555 LD->getMemoryVT() == MVT::i16;
558 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
559 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
560 return LD->getExtensionType() == ISD::ZEXTLOAD &&
561 LD->getAddressingMode() == ISD::UNINDEXED &&
562 LD->getMemoryVT() == MVT::i32;
567 def store : PatFrag<(ops node:$val, node:$ptr),
568 (st node:$val, node:$ptr), [{
569 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
570 return !ST->isTruncatingStore() &&
571 ST->getAddressingMode() == ISD::UNINDEXED;
575 // truncstore fragments.
576 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
577 (st node:$val, node:$ptr), [{
578 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
579 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
580 ST->getAddressingMode() == ISD::UNINDEXED;
583 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
584 (st node:$val, node:$ptr), [{
585 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
586 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
587 ST->getAddressingMode() == ISD::UNINDEXED;
590 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
591 (st node:$val, node:$ptr), [{
592 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
593 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
594 ST->getAddressingMode() == ISD::UNINDEXED;
597 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
598 (st node:$val, node:$ptr), [{
599 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
600 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
601 ST->getAddressingMode() == ISD::UNINDEXED;
604 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
605 (st node:$val, node:$ptr), [{
606 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
607 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
608 ST->getAddressingMode() == ISD::UNINDEXED;
612 // indexed store fragments.
613 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
614 (ist node:$val, node:$base, node:$offset), [{
615 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
616 ISD::MemIndexedMode AM = ST->getAddressingMode();
617 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
618 !ST->isTruncatingStore();
623 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
624 (ist node:$val, node:$base, node:$offset), [{
625 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
626 ISD::MemIndexedMode AM = ST->getAddressingMode();
627 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
628 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
632 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
633 (ist node:$val, node:$base, node:$offset), [{
634 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
635 ISD::MemIndexedMode AM = ST->getAddressingMode();
636 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
637 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
641 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
642 (ist node:$val, node:$base, node:$offset), [{
643 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
644 ISD::MemIndexedMode AM = ST->getAddressingMode();
645 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
646 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
650 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
651 (ist node:$val, node:$base, node:$offset), [{
652 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
653 ISD::MemIndexedMode AM = ST->getAddressingMode();
654 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
655 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
659 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
660 (ist node:$val, node:$base, node:$offset), [{
661 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
662 ISD::MemIndexedMode AM = ST->getAddressingMode();
663 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
664 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
669 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
670 (ist node:$val, node:$ptr, node:$offset), [{
671 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
672 ISD::MemIndexedMode AM = ST->getAddressingMode();
673 return !ST->isTruncatingStore() &&
674 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
679 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
680 (ist node:$val, node:$base, node:$offset), [{
681 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
682 ISD::MemIndexedMode AM = ST->getAddressingMode();
683 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
684 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
688 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
689 (ist node:$val, node:$base, node:$offset), [{
690 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
691 ISD::MemIndexedMode AM = ST->getAddressingMode();
692 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
693 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
697 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
698 (ist node:$val, node:$base, node:$offset), [{
699 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
700 ISD::MemIndexedMode AM = ST->getAddressingMode();
701 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
702 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
706 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
707 (ist node:$val, node:$base, node:$offset), [{
708 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
709 ISD::MemIndexedMode AM = ST->getAddressingMode();
710 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
711 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
715 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
716 (ist node:$val, node:$base, node:$offset), [{
717 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
718 ISD::MemIndexedMode AM = ST->getAddressingMode();
719 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
720 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
725 // setcc convenience fragments.
726 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
727 (setcc node:$lhs, node:$rhs, SETOEQ)>;
728 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
729 (setcc node:$lhs, node:$rhs, SETOGT)>;
730 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
731 (setcc node:$lhs, node:$rhs, SETOGE)>;
732 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
733 (setcc node:$lhs, node:$rhs, SETOLT)>;
734 def setole : PatFrag<(ops node:$lhs, node:$rhs),
735 (setcc node:$lhs, node:$rhs, SETOLE)>;
736 def setone : PatFrag<(ops node:$lhs, node:$rhs),
737 (setcc node:$lhs, node:$rhs, SETONE)>;
738 def seto : PatFrag<(ops node:$lhs, node:$rhs),
739 (setcc node:$lhs, node:$rhs, SETO)>;
740 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
741 (setcc node:$lhs, node:$rhs, SETUO)>;
742 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
743 (setcc node:$lhs, node:$rhs, SETUEQ)>;
744 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
745 (setcc node:$lhs, node:$rhs, SETUGT)>;
746 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
747 (setcc node:$lhs, node:$rhs, SETUGE)>;
748 def setult : PatFrag<(ops node:$lhs, node:$rhs),
749 (setcc node:$lhs, node:$rhs, SETULT)>;
750 def setule : PatFrag<(ops node:$lhs, node:$rhs),
751 (setcc node:$lhs, node:$rhs, SETULE)>;
752 def setune : PatFrag<(ops node:$lhs, node:$rhs),
753 (setcc node:$lhs, node:$rhs, SETUNE)>;
754 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
755 (setcc node:$lhs, node:$rhs, SETEQ)>;
756 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
757 (setcc node:$lhs, node:$rhs, SETGT)>;
758 def setge : PatFrag<(ops node:$lhs, node:$rhs),
759 (setcc node:$lhs, node:$rhs, SETGE)>;
760 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
761 (setcc node:$lhs, node:$rhs, SETLT)>;
762 def setle : PatFrag<(ops node:$lhs, node:$rhs),
763 (setcc node:$lhs, node:$rhs, SETLE)>;
764 def setne : PatFrag<(ops node:$lhs, node:$rhs),
765 (setcc node:$lhs, node:$rhs, SETNE)>;
767 //===----------------------------------------------------------------------===//
768 // Selection DAG Pattern Support.
770 // Patterns are what are actually matched against the target-flavored
771 // instruction selection DAG. Instructions defined by the target implicitly
772 // define patterns in most cases, but patterns can also be explicitly added when
773 // an operation is defined by a sequence of instructions (e.g. loading a large
774 // immediate value on RISC targets that do not support immediates as large as
778 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
779 dag PatternToMatch = patternToMatch;
780 list<dag> ResultInstrs = resultInstrs;
781 list<Predicate> Predicates = []; // See class Instruction in Target.td.
782 int AddedComplexity = 0; // See class Instruction in Target.td.
785 // Pat - A simple (but common) form of a pattern, which produces a simple result
786 // not needing a full list.
787 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
789 //===----------------------------------------------------------------------===//
790 // Complex pattern definitions.
794 // Pass the parent Operand as root to CP function rather
795 // than the root of the sub-DAG
796 def CPAttrParentAsRoot : CPAttribute;
798 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
799 // in C++. NumOperands is the number of operands returned by the select function;
800 // SelectFunc is the name of the function used to pattern match the max. pattern;
801 // RootNodes are the list of possible root nodes of the sub-dags to match.
802 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
804 class ComplexPattern<ValueType ty, int numops, string fn,
805 list<SDNode> roots = [], list<SDNodeProperty> props = [],
806 list<CPAttribute> attrs = []> {
808 int NumOperands = numops;
809 string SelectFunc = fn;
810 list<SDNode> RootNodes = roots;
811 list<SDNodeProperty> Properties = props;
812 list<CPAttribute> Attributes = attrs;
815 //===----------------------------------------------------------------------===//
818 def SDT_dwarf_loc : SDTypeProfile<0, 3,
819 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
820 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;