1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 // Classify VT as either 32 or 64 bit.
29 static bool is32Bit(EVT VT) {
30 switch (VT.getSimpleVT().SimpleTy) {
36 llvm_unreachable("Unsupported type");
40 // Return a version of MachineOperand that can be safely used before the
42 static MachineOperand earlyUseOperand(MachineOperand Op) {
48 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
49 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
50 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
51 MVT PtrVT = getPointerTy();
53 // Set up the register classes.
54 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
55 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
56 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
57 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
58 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set up special registers.
64 setExceptionPointerRegister(SystemZ::R6D);
65 setExceptionSelectorRegister(SystemZ::R7D);
66 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
68 // TODO: It may be better to default to latency-oriented scheduling, however
69 // LLVM's current latency-oriented scheduler can't handle physreg definitions
70 // such as SystemZ has with CC, so set this to the register-pressure
71 // scheduler, because it can.
72 setSchedulingPreference(Sched::RegPressure);
74 setBooleanContents(ZeroOrOneBooleanContent);
75 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
77 // Instructions are strings of 2-byte aligned 2-byte values.
78 setMinFunctionAlignment(2);
80 // Handle operations that are handled in a similar way for all types.
81 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
82 I <= MVT::LAST_FP_VALUETYPE;
84 MVT VT = MVT::SimpleValueType(I);
85 if (isTypeLegal(VT)) {
86 // Expand SETCC(X, Y, COND) into SELECT_CC(X, Y, 1, 0, COND).
87 setOperationAction(ISD::SETCC, VT, Expand);
89 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
90 setOperationAction(ISD::SELECT, VT, Expand);
92 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
93 setOperationAction(ISD::SELECT_CC, VT, Custom);
94 setOperationAction(ISD::BR_CC, VT, Custom);
98 // Expand jump table branches as address arithmetic followed by an
100 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
102 // Expand BRCOND into a BR_CC (see above).
103 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
105 // Handle integer types.
106 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
107 I <= MVT::LAST_INTEGER_VALUETYPE;
109 MVT VT = MVT::SimpleValueType(I);
110 if (isTypeLegal(VT)) {
111 // Expand individual DIV and REMs into DIVREMs.
112 setOperationAction(ISD::SDIV, VT, Expand);
113 setOperationAction(ISD::UDIV, VT, Expand);
114 setOperationAction(ISD::SREM, VT, Expand);
115 setOperationAction(ISD::UREM, VT, Expand);
116 setOperationAction(ISD::SDIVREM, VT, Custom);
117 setOperationAction(ISD::UDIVREM, VT, Custom);
119 // Expand ATOMIC_LOAD and ATOMIC_STORE using ATOMIC_CMP_SWAP.
120 // FIXME: probably much too conservative.
121 setOperationAction(ISD::ATOMIC_LOAD, VT, Expand);
122 setOperationAction(ISD::ATOMIC_STORE, VT, Expand);
124 // No special instructions for these.
125 setOperationAction(ISD::CTPOP, VT, Expand);
126 setOperationAction(ISD::CTTZ, VT, Expand);
127 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
129 setOperationAction(ISD::ROTR, VT, Expand);
131 // Use *MUL_LOHI where possible and a wider multiplication otherwise.
132 setOperationAction(ISD::MULHS, VT, Expand);
133 setOperationAction(ISD::MULHU, VT, Expand);
135 // We have instructions for signed but not unsigned FP conversion.
136 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
140 // Type legalization will convert 8- and 16-bit atomic operations into
141 // forms that operate on i32s (but still keeping the original memory VT).
142 // Lower them into full i32 operations.
143 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
144 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
145 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
146 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
147 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
148 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
149 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
150 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
151 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
152 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
153 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
154 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
156 // We have instructions for signed but not unsigned FP conversion.
157 // Handle unsigned 32-bit types as signed 64-bit types.
158 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
159 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
161 // We have native support for a 64-bit CTLZ, via FLOGR.
162 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
163 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
165 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
166 setOperationAction(ISD::OR, MVT::i64, Custom);
168 // The architecture has 32-bit SMUL_LOHI and UMUL_LOHI (MR and MLR),
169 // but they aren't really worth using. There is no 64-bit SMUL_LOHI,
170 // but there is a 64-bit UMUL_LOHI: MLGR.
171 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
172 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
173 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
174 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
176 // FIXME: Can we support these natively?
177 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
178 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
179 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
181 // We have native instructions for i8, i16 and i32 extensions, but not i1.
182 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
183 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
184 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
187 // Handle the various types of symbolic address.
188 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
189 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
190 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
191 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
192 setOperationAction(ISD::JumpTable, PtrVT, Custom);
194 // We need to handle dynamic allocations specially because of the
195 // 160-byte area at the bottom of the stack.
196 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
198 // Use custom expanders so that we can force the function to use
200 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
201 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
203 // Handle floating-point types.
204 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
205 I <= MVT::LAST_FP_VALUETYPE;
207 MVT VT = MVT::SimpleValueType(I);
208 if (isTypeLegal(VT)) {
209 // We can use FI for FRINT.
210 setOperationAction(ISD::FRINT, VT, Legal);
212 // No special instructions for these.
213 setOperationAction(ISD::FSIN, VT, Expand);
214 setOperationAction(ISD::FCOS, VT, Expand);
215 setOperationAction(ISD::FREM, VT, Expand);
219 // We have fused multiply-addition for f32 and f64 but not f128.
220 setOperationAction(ISD::FMA, MVT::f32, Legal);
221 setOperationAction(ISD::FMA, MVT::f64, Legal);
222 setOperationAction(ISD::FMA, MVT::f128, Expand);
224 // Needed so that we don't try to implement f128 constant loads using
225 // a load-and-extend of a f80 constant (in cases where the constant
226 // would fit in an f80).
227 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
229 // Floating-point truncation and stores need to be done separately.
230 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
231 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
232 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
234 // We have 64-bit FPR<->GPR moves, but need special handling for
236 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
237 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
239 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
240 // structure, but VAEND is a no-op.
241 setOperationAction(ISD::VASTART, MVT::Other, Custom);
242 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
243 setOperationAction(ISD::VAEND, MVT::Other, Expand);
245 // We want to use MVC in preference to even a single load/store pair.
246 MaxStoresPerMemcpy = 0;
247 MaxStoresPerMemcpyOptSize = 0;
249 // The main memset sequence is a byte store followed by an MVC.
250 // Two STC or MV..I stores win over that, but the kind of fused stores
251 // generated by target-independent code don't when the byte value is
252 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
253 // than "STC;MVC". Handle the choice in target-specific code instead.
254 MaxStoresPerMemset = 0;
255 MaxStoresPerMemsetOptSize = 0;
259 SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
260 VT = VT.getScalarType();
265 switch (VT.getSimpleVT().SimpleTy) {
278 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
279 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
280 return Imm.isZero() || Imm.isNegZero();
283 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
285 // Unaligned accesses should never be slower than the expanded version.
286 // We check specifically for aligned accesses in the few cases where
287 // they are required.
293 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
295 // Punt on globals for now, although they can be used in limited
296 // RELATIVE LONG cases.
300 // Require a 20-bit signed offset.
301 if (!isInt<20>(AM.BaseOffs))
304 // Indexing is OK but no scale factor can be applied.
305 return AM.Scale == 0 || AM.Scale == 1;
308 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
309 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
311 unsigned FromBits = FromType->getPrimitiveSizeInBits();
312 unsigned ToBits = ToType->getPrimitiveSizeInBits();
313 return FromBits > ToBits;
316 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
317 if (!FromVT.isInteger() || !ToVT.isInteger())
319 unsigned FromBits = FromVT.getSizeInBits();
320 unsigned ToBits = ToVT.getSizeInBits();
321 return FromBits > ToBits;
324 //===----------------------------------------------------------------------===//
325 // Inline asm support
326 //===----------------------------------------------------------------------===//
328 TargetLowering::ConstraintType
329 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
330 if (Constraint.size() == 1) {
331 switch (Constraint[0]) {
332 case 'a': // Address register
333 case 'd': // Data register (equivalent to 'r')
334 case 'f': // Floating-point register
335 case 'r': // General-purpose register
336 return C_RegisterClass;
338 case 'Q': // Memory with base and unsigned 12-bit displacement
339 case 'R': // Likewise, plus an index
340 case 'S': // Memory with base and signed 20-bit displacement
341 case 'T': // Likewise, plus an index
342 case 'm': // Equivalent to 'T'.
345 case 'I': // Unsigned 8-bit constant
346 case 'J': // Unsigned 12-bit constant
347 case 'K': // Signed 16-bit constant
348 case 'L': // Signed 20-bit displacement (on all targets we support)
349 case 'M': // 0x7fffffff
356 return TargetLowering::getConstraintType(Constraint);
359 TargetLowering::ConstraintWeight SystemZTargetLowering::
360 getSingleConstraintMatchWeight(AsmOperandInfo &info,
361 const char *constraint) const {
362 ConstraintWeight weight = CW_Invalid;
363 Value *CallOperandVal = info.CallOperandVal;
364 // If we don't have a value, we can't do a match,
365 // but allow it at the lowest weight.
366 if (CallOperandVal == NULL)
368 Type *type = CallOperandVal->getType();
369 // Look at the constraint type.
370 switch (*constraint) {
372 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
375 case 'a': // Address register
376 case 'd': // Data register (equivalent to 'r')
377 case 'r': // General-purpose register
378 if (CallOperandVal->getType()->isIntegerTy())
379 weight = CW_Register;
382 case 'f': // Floating-point register
383 if (type->isFloatingPointTy())
384 weight = CW_Register;
387 case 'I': // Unsigned 8-bit constant
388 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
389 if (isUInt<8>(C->getZExtValue()))
390 weight = CW_Constant;
393 case 'J': // Unsigned 12-bit constant
394 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
395 if (isUInt<12>(C->getZExtValue()))
396 weight = CW_Constant;
399 case 'K': // Signed 16-bit constant
400 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
401 if (isInt<16>(C->getSExtValue()))
402 weight = CW_Constant;
405 case 'L': // Signed 20-bit displacement (on all targets we support)
406 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
407 if (isInt<20>(C->getSExtValue()))
408 weight = CW_Constant;
411 case 'M': // 0x7fffffff
412 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
413 if (C->getZExtValue() == 0x7fffffff)
414 weight = CW_Constant;
420 // Parse a "{tNNN}" register constraint for which the register type "t"
421 // has already been verified. MC is the class associated with "t" and
422 // Map maps 0-based register numbers to LLVM register numbers.
423 static std::pair<unsigned, const TargetRegisterClass *>
424 parseRegisterNumber(const std::string &Constraint,
425 const TargetRegisterClass *RC, const unsigned *Map) {
426 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
427 if (isdigit(Constraint[2])) {
428 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
429 unsigned Index = atoi(Suffix.c_str());
430 if (Index < 16 && Map[Index])
431 return std::make_pair(Map[Index], RC);
433 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
436 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
437 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
438 if (Constraint.size() == 1) {
439 // GCC Constraint Letters
440 switch (Constraint[0]) {
442 case 'd': // Data register (equivalent to 'r')
443 case 'r': // General-purpose register
445 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
446 else if (VT == MVT::i128)
447 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
448 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
450 case 'a': // Address register
452 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
453 else if (VT == MVT::i128)
454 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
455 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
457 case 'f': // Floating-point register
459 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
460 else if (VT == MVT::f128)
461 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
462 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
465 if (Constraint[0] == '{') {
466 // We need to override the default register parsing for GPRs and FPRs
467 // because the interpretation depends on VT. The internal names of
468 // the registers are also different from the external names
469 // (F0D and F0S instead of F0, etc.).
470 if (Constraint[1] == 'r') {
472 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
473 SystemZMC::GR32Regs);
475 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
476 SystemZMC::GR128Regs);
477 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
478 SystemZMC::GR64Regs);
480 if (Constraint[1] == 'f') {
482 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
483 SystemZMC::FP32Regs);
485 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
486 SystemZMC::FP128Regs);
487 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
488 SystemZMC::FP64Regs);
491 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
494 void SystemZTargetLowering::
495 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
496 std::vector<SDValue> &Ops,
497 SelectionDAG &DAG) const {
498 // Only support length 1 constraints for now.
499 if (Constraint.length() == 1) {
500 switch (Constraint[0]) {
501 case 'I': // Unsigned 8-bit constant
502 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
503 if (isUInt<8>(C->getZExtValue()))
504 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
508 case 'J': // Unsigned 12-bit constant
509 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
510 if (isUInt<12>(C->getZExtValue()))
511 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
515 case 'K': // Signed 16-bit constant
516 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
517 if (isInt<16>(C->getSExtValue()))
518 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
522 case 'L': // Signed 20-bit displacement (on all targets we support)
523 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
524 if (isInt<20>(C->getSExtValue()))
525 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
529 case 'M': // 0x7fffffff
530 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
531 if (C->getZExtValue() == 0x7fffffff)
532 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
537 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
540 //===----------------------------------------------------------------------===//
541 // Calling conventions
542 //===----------------------------------------------------------------------===//
544 #include "SystemZGenCallingConv.inc"
546 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
547 Type *ToType) const {
548 return isTruncateFree(FromType, ToType);
551 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
552 if (!CI->isTailCall())
557 // Value is a value that has been passed to us in the location described by VA
558 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
559 // any loads onto Chain.
560 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
561 CCValAssign &VA, SDValue Chain,
563 // If the argument has been promoted from a smaller type, insert an
564 // assertion to capture this.
565 if (VA.getLocInfo() == CCValAssign::SExt)
566 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
567 DAG.getValueType(VA.getValVT()));
568 else if (VA.getLocInfo() == CCValAssign::ZExt)
569 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
570 DAG.getValueType(VA.getValVT()));
573 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
574 else if (VA.getLocInfo() == CCValAssign::Indirect)
575 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
576 MachinePointerInfo(), false, false, false, 0);
578 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
582 // Value is a value of type VA.getValVT() that we need to copy into
583 // the location described by VA. Return a copy of Value converted to
584 // VA.getValVT(). The caller is responsible for handling indirect values.
585 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
586 CCValAssign &VA, SDValue Value) {
587 switch (VA.getLocInfo()) {
588 case CCValAssign::SExt:
589 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
590 case CCValAssign::ZExt:
591 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
592 case CCValAssign::AExt:
593 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
594 case CCValAssign::Full:
597 llvm_unreachable("Unhandled getLocInfo()");
601 SDValue SystemZTargetLowering::
602 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
603 const SmallVectorImpl<ISD::InputArg> &Ins,
604 SDLoc DL, SelectionDAG &DAG,
605 SmallVectorImpl<SDValue> &InVals) const {
606 MachineFunction &MF = DAG.getMachineFunction();
607 MachineFrameInfo *MFI = MF.getFrameInfo();
608 MachineRegisterInfo &MRI = MF.getRegInfo();
609 SystemZMachineFunctionInfo *FuncInfo =
610 MF.getInfo<SystemZMachineFunctionInfo>();
611 const SystemZFrameLowering *TFL =
612 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
614 // Assign locations to all of the incoming arguments.
615 SmallVector<CCValAssign, 16> ArgLocs;
616 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
617 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
619 unsigned NumFixedGPRs = 0;
620 unsigned NumFixedFPRs = 0;
621 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
623 CCValAssign &VA = ArgLocs[I];
624 EVT LocVT = VA.getLocVT();
626 // Arguments passed in registers
627 const TargetRegisterClass *RC;
628 switch (LocVT.getSimpleVT().SimpleTy) {
630 // Integers smaller than i64 should be promoted to i64.
631 llvm_unreachable("Unexpected argument type");
634 RC = &SystemZ::GR32BitRegClass;
638 RC = &SystemZ::GR64BitRegClass;
642 RC = &SystemZ::FP32BitRegClass;
646 RC = &SystemZ::FP64BitRegClass;
650 unsigned VReg = MRI.createVirtualRegister(RC);
651 MRI.addLiveIn(VA.getLocReg(), VReg);
652 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
654 assert(VA.isMemLoc() && "Argument not register or memory");
656 // Create the frame index object for this incoming parameter.
657 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
658 VA.getLocMemOffset(), true);
660 // Create the SelectionDAG nodes corresponding to a load
661 // from this parameter. Unpromoted ints and floats are
662 // passed as right-justified 8-byte values.
663 EVT PtrVT = getPointerTy();
664 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
665 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
666 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
667 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
668 MachinePointerInfo::getFixedStack(FI),
669 false, false, false, 0);
672 // Convert the value of the argument register into the value that's
674 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
678 // Save the number of non-varargs registers for later use by va_start, etc.
679 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
680 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
682 // Likewise the address (in the form of a frame index) of where the
683 // first stack vararg would be. The 1-byte size here is arbitrary.
684 int64_t StackSize = CCInfo.getNextStackOffset();
685 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
687 // ...and a similar frame index for the caller-allocated save area
688 // that will be used to store the incoming registers.
689 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
690 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
691 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
693 // Store the FPR varargs in the reserved frame slots. (We store the
694 // GPRs as part of the prologue.)
695 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
696 SDValue MemOps[SystemZ::NumArgFPRs];
697 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
698 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
699 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
700 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
701 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
702 &SystemZ::FP64BitRegClass);
703 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
704 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
705 MachinePointerInfo::getFixedStack(FI),
709 // Join the stores, which are independent of one another.
710 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
711 &MemOps[NumFixedFPRs],
712 SystemZ::NumArgFPRs - NumFixedFPRs);
719 static bool canUseSiblingCall(CCState ArgCCInfo,
720 SmallVectorImpl<CCValAssign> &ArgLocs) {
721 // Punt if there are any indirect or stack arguments, or if the call
722 // needs the call-saved argument register R6.
723 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
724 CCValAssign &VA = ArgLocs[I];
725 if (VA.getLocInfo() == CCValAssign::Indirect)
729 unsigned Reg = VA.getLocReg();
730 if (Reg == SystemZ::R6W || Reg == SystemZ::R6D)
737 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
738 SmallVectorImpl<SDValue> &InVals) const {
739 SelectionDAG &DAG = CLI.DAG;
741 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
742 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
743 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
744 SDValue Chain = CLI.Chain;
745 SDValue Callee = CLI.Callee;
746 bool &IsTailCall = CLI.IsTailCall;
747 CallingConv::ID CallConv = CLI.CallConv;
748 bool IsVarArg = CLI.IsVarArg;
749 MachineFunction &MF = DAG.getMachineFunction();
750 EVT PtrVT = getPointerTy();
752 // Analyze the operands of the call, assigning locations to each operand.
753 SmallVector<CCValAssign, 16> ArgLocs;
754 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
755 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
757 // We don't support GuaranteedTailCallOpt, only automatically-detected
759 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
762 // Get a count of how many bytes are to be pushed on the stack.
763 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
765 // Mark the start of the call.
767 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
770 // Copy argument values to their designated locations.
771 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
772 SmallVector<SDValue, 8> MemOpChains;
774 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
775 CCValAssign &VA = ArgLocs[I];
776 SDValue ArgValue = OutVals[I];
778 if (VA.getLocInfo() == CCValAssign::Indirect) {
779 // Store the argument in a stack slot and pass its address.
780 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
781 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
782 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
783 MachinePointerInfo::getFixedStack(FI),
785 ArgValue = SpillSlot;
787 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
790 // Queue up the argument copies and emit them at the end.
791 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
793 assert(VA.isMemLoc() && "Argument not register or memory");
795 // Work out the address of the stack slot. Unpromoted ints and
796 // floats are passed as right-justified 8-byte values.
797 if (!StackPtr.getNode())
798 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
799 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
800 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
802 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
803 DAG.getIntPtrConstant(Offset));
806 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
807 MachinePointerInfo(),
812 // Join the stores, which are independent of one another.
813 if (!MemOpChains.empty())
814 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
815 &MemOpChains[0], MemOpChains.size());
817 // Accept direct calls by converting symbolic call addresses to the
818 // associated Target* opcodes. Force %r1 to be used for indirect
821 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
822 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
823 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
824 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
825 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
826 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
827 } else if (IsTailCall) {
828 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
829 Glue = Chain.getValue(1);
830 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
833 // Build a sequence of copy-to-reg nodes, chained and glued together.
834 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
835 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
836 RegsToPass[I].second, Glue);
837 Glue = Chain.getValue(1);
840 // The first call operand is the chain and the second is the target address.
841 SmallVector<SDValue, 8> Ops;
842 Ops.push_back(Chain);
843 Ops.push_back(Callee);
845 // Add argument registers to the end of the list so that they are
846 // known live into the call.
847 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
848 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
849 RegsToPass[I].second.getValueType()));
851 // Glue the call to the argument copies, if any.
856 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
858 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
859 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
860 Glue = Chain.getValue(1);
862 // Mark the end of the call, which is glued to the call itself.
863 Chain = DAG.getCALLSEQ_END(Chain,
864 DAG.getConstant(NumBytes, PtrVT, true),
865 DAG.getConstant(0, PtrVT, true),
867 Glue = Chain.getValue(1);
869 // Assign locations to each value returned by this call.
870 SmallVector<CCValAssign, 16> RetLocs;
871 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
872 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
874 // Copy all of the result registers out of their specified physreg.
875 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
876 CCValAssign &VA = RetLocs[I];
878 // Copy the value out, gluing the copy to the end of the call sequence.
879 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
880 VA.getLocVT(), Glue);
881 Chain = RetValue.getValue(1);
882 Glue = RetValue.getValue(2);
884 // Convert the value of the return register into the value that's
886 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
893 SystemZTargetLowering::LowerReturn(SDValue Chain,
894 CallingConv::ID CallConv, bool IsVarArg,
895 const SmallVectorImpl<ISD::OutputArg> &Outs,
896 const SmallVectorImpl<SDValue> &OutVals,
897 SDLoc DL, SelectionDAG &DAG) const {
898 MachineFunction &MF = DAG.getMachineFunction();
900 // Assign locations to each returned value.
901 SmallVector<CCValAssign, 16> RetLocs;
902 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
903 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
905 // Quick exit for void returns
907 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
909 // Copy the result values into the output registers.
911 SmallVector<SDValue, 4> RetOps;
912 RetOps.push_back(Chain);
913 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
914 CCValAssign &VA = RetLocs[I];
915 SDValue RetValue = OutVals[I];
917 // Make the return register live on exit.
918 assert(VA.isRegLoc() && "Can only return in registers!");
920 // Promote the value as required.
921 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
923 // Chain and glue the copies together.
924 unsigned Reg = VA.getLocReg();
925 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
926 Glue = Chain.getValue(1);
927 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
930 // Update chain and glue.
933 RetOps.push_back(Glue);
935 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
936 RetOps.data(), RetOps.size());
939 // CC is a comparison that will be implemented using an integer or
940 // floating-point comparison. Return the condition code mask for
941 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
942 // unsigned comparisons and clear for signed ones. In the floating-point
943 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
944 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
946 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
947 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
948 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
952 llvm_unreachable("Invalid integer condition!");
961 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
962 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
967 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
968 // can be converted to a comparison against zero, adjust the operands
970 static void adjustZeroCmp(SelectionDAG &DAG, bool &IsUnsigned,
971 SDValue &CmpOp0, SDValue &CmpOp1,
976 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(CmpOp1.getNode());
980 int64_t Value = ConstOp1->getSExtValue();
981 if ((Value == -1 && CCMask == SystemZ::CCMASK_CMP_GT) ||
982 (Value == -1 && CCMask == SystemZ::CCMASK_CMP_LE) ||
983 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_LT) ||
984 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_GE)) {
985 CCMask ^= SystemZ::CCMASK_CMP_EQ;
986 CmpOp1 = DAG.getConstant(0, CmpOp1.getValueType());
990 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
991 // is suitable for CLI(Y), CHHSI or CLHHSI, adjust the operands as necessary.
992 static void adjustSubwordCmp(SelectionDAG &DAG, bool &IsUnsigned,
993 SDValue &CmpOp0, SDValue &CmpOp1,
995 // For us to make any changes, it must a comparison between a single-use
996 // load and a constant.
997 if (!CmpOp0.hasOneUse() ||
998 CmpOp0.getOpcode() != ISD::LOAD ||
999 CmpOp1.getOpcode() != ISD::Constant)
1002 // We must have an 8- or 16-bit load.
1003 LoadSDNode *Load = cast<LoadSDNode>(CmpOp0);
1004 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1005 if (NumBits != 8 && NumBits != 16)
1008 // The load must be an extending one and the constant must be within the
1009 // range of the unextended value.
1010 ConstantSDNode *Constant = cast<ConstantSDNode>(CmpOp1);
1011 uint64_t Value = Constant->getZExtValue();
1012 uint64_t Mask = (1 << NumBits) - 1;
1013 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1014 int64_t SignedValue = Constant->getSExtValue();
1015 if (uint64_t(SignedValue) + (1ULL << (NumBits - 1)) > Mask)
1017 // Unsigned comparison between two sign-extended values is equivalent
1018 // to unsigned comparison between two zero-extended values.
1021 else if (CCMask == SystemZ::CCMASK_CMP_EQ ||
1022 CCMask == SystemZ::CCMASK_CMP_NE)
1023 // Any choice of IsUnsigned is OK for equality comparisons.
1024 // We could use either CHHSI or CLHHSI for 16-bit comparisons,
1025 // but since we use CLHHSI for zero extensions, it seems better
1026 // to be consistent and do the same here.
1027 Value &= Mask, IsUnsigned = true;
1028 else if (NumBits == 8) {
1029 // Try to treat the comparison as unsigned, so that we can use CLI.
1030 // Adjust CCMask and Value as necessary.
1031 if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_LT)
1032 // Test whether the high bit of the byte is set.
1033 Value = 127, CCMask = SystemZ::CCMASK_CMP_GT, IsUnsigned = true;
1034 else if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_GE)
1035 // Test whether the high bit of the byte is clear.
1036 Value = 128, CCMask = SystemZ::CCMASK_CMP_LT, IsUnsigned = true;
1038 // No instruction exists for this combination.
1041 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1044 // Signed comparison between two zero-extended values is equivalent
1045 // to unsigned comparison.
1050 // Make sure that the first operand is an i32 of the right extension type.
1051 ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
1052 if (CmpOp0.getValueType() != MVT::i32 ||
1053 Load->getExtensionType() != ExtType)
1054 CmpOp0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1055 Load->getChain(), Load->getBasePtr(),
1056 Load->getPointerInfo(), Load->getMemoryVT(),
1057 Load->isVolatile(), Load->isNonTemporal(),
1058 Load->getAlignment());
1060 // Make sure that the second operand is an i32 with the right value.
1061 if (CmpOp1.getValueType() != MVT::i32 ||
1062 Value != Constant->getZExtValue())
1063 CmpOp1 = DAG.getConstant(Value, MVT::i32);
1066 // Return true if a comparison described by CCMask, CmpOp0 and CmpOp1
1067 // is an equality comparison that is better implemented using unsigned
1068 // rather than signed comparison instructions.
1069 static bool preferUnsignedComparison(SelectionDAG &DAG, SDValue CmpOp0,
1070 SDValue CmpOp1, unsigned CCMask) {
1071 // The test must be for equality or inequality.
1072 if (CCMask != SystemZ::CCMASK_CMP_EQ && CCMask != SystemZ::CCMASK_CMP_NE)
1075 if (CmpOp1.getOpcode() == ISD::Constant) {
1076 uint64_t Value = cast<ConstantSDNode>(CmpOp1)->getSExtValue();
1078 // If we're comparing with memory, prefer unsigned comparisons for
1079 // values that are in the unsigned 16-bit range but not the signed
1080 // 16-bit range. We want to use CLFHSI and CLGHSI.
1081 if (CmpOp0.hasOneUse() &&
1082 ISD::isNormalLoad(CmpOp0.getNode()) &&
1083 (Value >= 32768 && Value < 65536))
1086 // Use unsigned comparisons for values that are in the CLGFI range
1087 // but not in the CGFI range.
1088 if (CmpOp0.getValueType() == MVT::i64 && (Value >> 31) == 1)
1094 // Prefer CL for zero-extended loads.
1095 if (CmpOp1.getOpcode() == ISD::ZERO_EXTEND ||
1096 ISD::isZEXTLoad(CmpOp1.getNode()))
1099 // ...and for "in-register" zero extensions.
1100 if (CmpOp1.getOpcode() == ISD::AND && CmpOp1.getValueType() == MVT::i64) {
1101 SDValue Mask = CmpOp1.getOperand(1);
1102 if (Mask.getOpcode() == ISD::Constant &&
1103 cast<ConstantSDNode>(Mask)->getZExtValue() == 0xffffffff)
1110 // Return a target node that compares CmpOp0 with CmpOp1 and stores a
1111 // 2-bit result in CC. Set CCValid to the CCMASK_* of all possible
1112 // 2-bit results and CCMask to the subset of those results that are
1113 // associated with Cond.
1114 static SDValue emitCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1115 ISD::CondCode Cond, unsigned &CCValid,
1117 bool IsUnsigned = false;
1118 CCMask = CCMaskForCondCode(Cond);
1119 if (CmpOp0.getValueType().isFloatingPoint())
1120 CCValid = SystemZ::CCMASK_FCMP;
1122 IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
1123 CCValid = SystemZ::CCMASK_ICMP;
1125 adjustZeroCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1126 adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1127 if (preferUnsignedComparison(DAG, CmpOp0, CmpOp1, CCMask))
1132 return DAG.getNode((IsUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
1133 DL, MVT::Glue, CmpOp0, CmpOp1);
1136 // Lower a binary operation that produces two VT results, one in each
1137 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1138 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1139 // on the extended Op0 and (unextended) Op1. Store the even register result
1140 // in Even and the odd register result in Odd.
1141 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1142 unsigned Extend, unsigned Opcode,
1143 SDValue Op0, SDValue Op1,
1144 SDValue &Even, SDValue &Odd) {
1145 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1146 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1147 SDValue(In128, 0), Op1);
1148 bool Is32Bit = is32Bit(VT);
1149 SDValue SubReg0 = DAG.getTargetConstant(SystemZ::even128(Is32Bit), VT);
1150 SDValue SubReg1 = DAG.getTargetConstant(SystemZ::odd128(Is32Bit), VT);
1151 SDNode *Reg0 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1152 VT, Result, SubReg0);
1153 SDNode *Reg1 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1154 VT, Result, SubReg1);
1155 Even = SDValue(Reg0, 0);
1156 Odd = SDValue(Reg1, 0);
1159 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1160 SDValue Chain = Op.getOperand(0);
1161 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1162 SDValue CmpOp0 = Op.getOperand(2);
1163 SDValue CmpOp1 = Op.getOperand(3);
1164 SDValue Dest = Op.getOperand(4);
1167 unsigned CCValid, CCMask;
1168 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1169 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1170 Chain, DAG.getConstant(CCValid, MVT::i32),
1171 DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
1174 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1175 SelectionDAG &DAG) const {
1176 SDValue CmpOp0 = Op.getOperand(0);
1177 SDValue CmpOp1 = Op.getOperand(1);
1178 SDValue TrueOp = Op.getOperand(2);
1179 SDValue FalseOp = Op.getOperand(3);
1180 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1183 unsigned CCValid, CCMask;
1184 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1186 SmallVector<SDValue, 5> Ops;
1187 Ops.push_back(TrueOp);
1188 Ops.push_back(FalseOp);
1189 Ops.push_back(DAG.getConstant(CCValid, MVT::i32));
1190 Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
1191 Ops.push_back(Flags);
1193 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1194 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1197 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1198 SelectionDAG &DAG) const {
1200 const GlobalValue *GV = Node->getGlobal();
1201 int64_t Offset = Node->getOffset();
1202 EVT PtrVT = getPointerTy();
1203 Reloc::Model RM = TM.getRelocationModel();
1204 CodeModel::Model CM = TM.getCodeModel();
1207 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1208 // Make sure that the offset is aligned to a halfword. If it isn't,
1209 // create an "anchor" at the previous 12-bit boundary.
1210 // FIXME check whether there is a better way of handling this.
1212 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1213 Offset & ~uint64_t(0xfff));
1216 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
1219 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1221 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1222 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1223 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1224 MachinePointerInfo::getGOT(), false, false, false, 0);
1227 // If there was a non-zero offset that we didn't fold, create an explicit
1230 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1231 DAG.getConstant(Offset, PtrVT));
1236 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1237 SelectionDAG &DAG) const {
1239 const GlobalValue *GV = Node->getGlobal();
1240 EVT PtrVT = getPointerTy();
1241 TLSModel::Model model = TM.getTLSModel(GV);
1243 if (model != TLSModel::LocalExec)
1244 llvm_unreachable("only local-exec TLS mode supported");
1246 // The high part of the thread pointer is in access register 0.
1247 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1248 DAG.getConstant(0, MVT::i32));
1249 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1251 // The low part of the thread pointer is in access register 1.
1252 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1253 DAG.getConstant(1, MVT::i32));
1254 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1256 // Merge them into a single 64-bit address.
1257 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1258 DAG.getConstant(32, PtrVT));
1259 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1261 // Get the offset of GA from the thread pointer.
1262 SystemZConstantPoolValue *CPV =
1263 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1265 // Force the offset into the constant pool and load it from there.
1266 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1267 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1268 CPAddr, MachinePointerInfo::getConstantPool(),
1269 false, false, false, 0);
1271 // Add the base and offset together.
1272 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1275 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1276 SelectionDAG &DAG) const {
1278 const BlockAddress *BA = Node->getBlockAddress();
1279 int64_t Offset = Node->getOffset();
1280 EVT PtrVT = getPointerTy();
1282 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1283 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1287 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1288 SelectionDAG &DAG) const {
1290 EVT PtrVT = getPointerTy();
1291 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1293 // Use LARL to load the address of the table.
1294 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1297 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1298 SelectionDAG &DAG) const {
1300 EVT PtrVT = getPointerTy();
1303 if (CP->isMachineConstantPoolEntry())
1304 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1305 CP->getAlignment());
1307 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1308 CP->getAlignment(), CP->getOffset());
1310 // Use LARL to load the address of the constant pool entry.
1311 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1314 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1315 SelectionDAG &DAG) const {
1317 SDValue In = Op.getOperand(0);
1318 EVT InVT = In.getValueType();
1319 EVT ResVT = Op.getValueType();
1321 SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
1322 SDValue Shift32 = DAG.getConstant(32, MVT::i64);
1323 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1324 SDValue In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1325 SDValue Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, Shift32);
1326 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shift);
1327 SDNode *Out = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1328 MVT::f32, Out64, SubReg32);
1329 return SDValue(Out, 0);
1331 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1332 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1333 SDNode *In64 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
1334 MVT::f64, SDValue(U64, 0), In, SubReg32);
1335 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, SDValue(In64, 0));
1336 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, Shift32);
1337 SDValue Out = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1340 llvm_unreachable("Unexpected bitcast combination");
1343 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1344 SelectionDAG &DAG) const {
1345 MachineFunction &MF = DAG.getMachineFunction();
1346 SystemZMachineFunctionInfo *FuncInfo =
1347 MF.getInfo<SystemZMachineFunctionInfo>();
1348 EVT PtrVT = getPointerTy();
1350 SDValue Chain = Op.getOperand(0);
1351 SDValue Addr = Op.getOperand(1);
1352 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1355 // The initial values of each field.
1356 const unsigned NumFields = 4;
1357 SDValue Fields[NumFields] = {
1358 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1359 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1360 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1361 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1364 // Store each field into its respective slot.
1365 SDValue MemOps[NumFields];
1366 unsigned Offset = 0;
1367 for (unsigned I = 0; I < NumFields; ++I) {
1368 SDValue FieldAddr = Addr;
1370 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1371 DAG.getIntPtrConstant(Offset));
1372 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1373 MachinePointerInfo(SV, Offset),
1377 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1380 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1381 SelectionDAG &DAG) const {
1382 SDValue Chain = Op.getOperand(0);
1383 SDValue DstPtr = Op.getOperand(1);
1384 SDValue SrcPtr = Op.getOperand(2);
1385 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1386 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1389 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1390 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1391 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1394 SDValue SystemZTargetLowering::
1395 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1396 SDValue Chain = Op.getOperand(0);
1397 SDValue Size = Op.getOperand(1);
1400 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1402 // Get a reference to the stack pointer.
1403 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
1405 // Get the new stack pointer value.
1406 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
1408 // Copy the new stack pointer back.
1409 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
1411 // The allocated data lives above the 160 bytes allocated for the standard
1412 // frame, plus any outgoing stack arguments. We don't know how much that
1413 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
1414 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
1415 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
1417 SDValue Ops[2] = { Result, Chain };
1418 return DAG.getMergeValues(Ops, 2, DL);
1421 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
1422 SelectionDAG &DAG) const {
1423 EVT VT = Op.getValueType();
1425 assert(!is32Bit(VT) && "Only support 64-bit UMUL_LOHI");
1427 // UMUL_LOHI64 returns the low result in the odd register and the high
1428 // result in the even register. UMUL_LOHI is defined to return the
1429 // low half first, so the results are in reverse order.
1431 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1432 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1433 return DAG.getMergeValues(Ops, 2, DL);
1436 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
1437 SelectionDAG &DAG) const {
1438 SDValue Op0 = Op.getOperand(0);
1439 SDValue Op1 = Op.getOperand(1);
1440 EVT VT = Op.getValueType();
1444 // We use DSGF for 32-bit division.
1446 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
1447 Opcode = SystemZISD::SDIVREM32;
1448 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
1449 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
1450 Opcode = SystemZISD::SDIVREM32;
1452 Opcode = SystemZISD::SDIVREM64;
1454 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
1455 // input is "don't care". The instruction returns the remainder in
1456 // the even register and the quotient in the odd register.
1458 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
1459 Op0, Op1, Ops[1], Ops[0]);
1460 return DAG.getMergeValues(Ops, 2, DL);
1463 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
1464 SelectionDAG &DAG) const {
1465 EVT VT = Op.getValueType();
1468 // DL(G) uses a double-width dividend, so we need to clear the even
1469 // register in the GR128 input. The instruction returns the remainder
1470 // in the even register and the quotient in the odd register.
1473 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
1474 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1476 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
1477 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1478 return DAG.getMergeValues(Ops, 2, DL);
1481 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
1482 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
1484 // Get the known-zero masks for each operand.
1485 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1486 APInt KnownZero[2], KnownOne[2];
1487 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
1488 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
1490 // See if the upper 32 bits of one operand and the lower 32 bits of the
1491 // other are known zero. They are the low and high operands respectively.
1492 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
1493 KnownZero[1].getZExtValue() };
1495 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
1497 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
1502 SDValue LowOp = Ops[Low];
1503 SDValue HighOp = Ops[High];
1505 // If the high part is a constant, we're better off using IILH.
1506 if (HighOp.getOpcode() == ISD::Constant)
1509 // If the low part is a constant that is outside the range of LHI,
1510 // then we're better off using IILF.
1511 if (LowOp.getOpcode() == ISD::Constant) {
1512 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
1513 if (!isInt<16>(Value))
1517 // Check whether the high part is an AND that doesn't change the
1518 // high 32 bits and just masks out low bits. We can skip it if so.
1519 if (HighOp.getOpcode() == ISD::AND &&
1520 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
1521 ConstantSDNode *MaskNode = cast<ConstantSDNode>(HighOp.getOperand(1));
1522 uint64_t Mask = MaskNode->getZExtValue() | Masks[High];
1523 if ((Mask >> 32) == 0xffffffff)
1524 HighOp = HighOp.getOperand(0);
1527 // Take advantage of the fact that all GR32 operations only change the
1528 // low 32 bits by truncating Low to an i32 and inserting it directly
1529 // using a subreg. The interesting cases are those where the truncation
1532 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
1533 SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
1534 SDNode *Result = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
1535 MVT::i64, HighOp, Low32, SubReg32);
1536 return SDValue(Result, 0);
1539 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
1540 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
1541 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
1543 unsigned Opcode) const {
1544 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1546 // 32-bit operations need no code outside the main loop.
1547 EVT NarrowVT = Node->getMemoryVT();
1548 EVT WideVT = MVT::i32;
1549 if (NarrowVT == WideVT)
1552 int64_t BitSize = NarrowVT.getSizeInBits();
1553 SDValue ChainIn = Node->getChain();
1554 SDValue Addr = Node->getBasePtr();
1555 SDValue Src2 = Node->getVal();
1556 MachineMemOperand *MMO = Node->getMemOperand();
1558 EVT PtrVT = Addr.getValueType();
1560 // Convert atomic subtracts of constants into additions.
1561 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
1562 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
1563 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
1564 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
1567 // Get the address of the containing word.
1568 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1569 DAG.getConstant(-4, PtrVT));
1571 // Get the number of bits that the word must be rotated left in order
1572 // to bring the field to the top bits of a GR32.
1573 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1574 DAG.getConstant(3, PtrVT));
1575 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1577 // Get the complementing shift amount, for rotating a field in the top
1578 // bits back to its proper position.
1579 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1580 DAG.getConstant(0, WideVT), BitShift);
1582 // Extend the source operand to 32 bits and prepare it for the inner loop.
1583 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
1584 // operations require the source to be shifted in advance. (This shift
1585 // can be folded if the source is constant.) For AND and NAND, the lower
1586 // bits must be set, while for other opcodes they should be left clear.
1587 if (Opcode != SystemZISD::ATOMIC_SWAPW)
1588 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
1589 DAG.getConstant(32 - BitSize, WideVT));
1590 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
1591 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
1592 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
1593 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
1595 // Construct the ATOMIC_LOADW_* node.
1596 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1597 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
1598 DAG.getConstant(BitSize, WideVT) };
1599 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
1600 array_lengthof(Ops),
1603 // Rotate the result of the final CS so that the field is in the lower
1604 // bits of a GR32, then truncate it.
1605 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
1606 DAG.getConstant(BitSize, WideVT));
1607 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
1609 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
1610 return DAG.getMergeValues(RetOps, 2, DL);
1613 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
1614 // into a fullword ATOMIC_CMP_SWAPW operation.
1615 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
1616 SelectionDAG &DAG) const {
1617 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1619 // We have native support for 32-bit compare and swap.
1620 EVT NarrowVT = Node->getMemoryVT();
1621 EVT WideVT = MVT::i32;
1622 if (NarrowVT == WideVT)
1625 int64_t BitSize = NarrowVT.getSizeInBits();
1626 SDValue ChainIn = Node->getOperand(0);
1627 SDValue Addr = Node->getOperand(1);
1628 SDValue CmpVal = Node->getOperand(2);
1629 SDValue SwapVal = Node->getOperand(3);
1630 MachineMemOperand *MMO = Node->getMemOperand();
1632 EVT PtrVT = Addr.getValueType();
1634 // Get the address of the containing word.
1635 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1636 DAG.getConstant(-4, PtrVT));
1638 // Get the number of bits that the word must be rotated left in order
1639 // to bring the field to the top bits of a GR32.
1640 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1641 DAG.getConstant(3, PtrVT));
1642 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1644 // Get the complementing shift amount, for rotating a field in the top
1645 // bits back to its proper position.
1646 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1647 DAG.getConstant(0, WideVT), BitShift);
1649 // Construct the ATOMIC_CMP_SWAPW node.
1650 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1651 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
1652 NegBitShift, DAG.getConstant(BitSize, WideVT) };
1653 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
1654 VTList, Ops, array_lengthof(Ops),
1659 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
1660 SelectionDAG &DAG) const {
1661 MachineFunction &MF = DAG.getMachineFunction();
1662 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1663 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
1664 SystemZ::R15D, Op.getValueType());
1667 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
1668 SelectionDAG &DAG) const {
1669 MachineFunction &MF = DAG.getMachineFunction();
1670 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1671 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
1672 SystemZ::R15D, Op.getOperand(1));
1675 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
1676 SelectionDAG &DAG) const {
1677 switch (Op.getOpcode()) {
1679 return lowerBR_CC(Op, DAG);
1680 case ISD::SELECT_CC:
1681 return lowerSELECT_CC(Op, DAG);
1682 case ISD::GlobalAddress:
1683 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
1684 case ISD::GlobalTLSAddress:
1685 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
1686 case ISD::BlockAddress:
1687 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
1688 case ISD::JumpTable:
1689 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
1690 case ISD::ConstantPool:
1691 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
1693 return lowerBITCAST(Op, DAG);
1695 return lowerVASTART(Op, DAG);
1697 return lowerVACOPY(Op, DAG);
1698 case ISD::DYNAMIC_STACKALLOC:
1699 return lowerDYNAMIC_STACKALLOC(Op, DAG);
1700 case ISD::UMUL_LOHI:
1701 return lowerUMUL_LOHI(Op, DAG);
1703 return lowerSDIVREM(Op, DAG);
1705 return lowerUDIVREM(Op, DAG);
1707 return lowerOR(Op, DAG);
1708 case ISD::ATOMIC_SWAP:
1709 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_SWAPW);
1710 case ISD::ATOMIC_LOAD_ADD:
1711 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
1712 case ISD::ATOMIC_LOAD_SUB:
1713 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
1714 case ISD::ATOMIC_LOAD_AND:
1715 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
1716 case ISD::ATOMIC_LOAD_OR:
1717 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
1718 case ISD::ATOMIC_LOAD_XOR:
1719 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
1720 case ISD::ATOMIC_LOAD_NAND:
1721 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
1722 case ISD::ATOMIC_LOAD_MIN:
1723 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
1724 case ISD::ATOMIC_LOAD_MAX:
1725 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
1726 case ISD::ATOMIC_LOAD_UMIN:
1727 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
1728 case ISD::ATOMIC_LOAD_UMAX:
1729 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
1730 case ISD::ATOMIC_CMP_SWAP:
1731 return lowerATOMIC_CMP_SWAP(Op, DAG);
1732 case ISD::STACKSAVE:
1733 return lowerSTACKSAVE(Op, DAG);
1734 case ISD::STACKRESTORE:
1735 return lowerSTACKRESTORE(Op, DAG);
1737 llvm_unreachable("Unexpected node to lower");
1741 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
1742 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
1747 OPCODE(PCREL_WRAPPER);
1751 OPCODE(SELECT_CCMASK);
1752 OPCODE(ADJDYNALLOC);
1753 OPCODE(EXTRACT_ACCESS);
1754 OPCODE(UMUL_LOHI64);
1762 OPCODE(SEARCH_STRING);
1764 OPCODE(ATOMIC_SWAPW);
1765 OPCODE(ATOMIC_LOADW_ADD);
1766 OPCODE(ATOMIC_LOADW_SUB);
1767 OPCODE(ATOMIC_LOADW_AND);
1768 OPCODE(ATOMIC_LOADW_OR);
1769 OPCODE(ATOMIC_LOADW_XOR);
1770 OPCODE(ATOMIC_LOADW_NAND);
1771 OPCODE(ATOMIC_LOADW_MIN);
1772 OPCODE(ATOMIC_LOADW_MAX);
1773 OPCODE(ATOMIC_LOADW_UMIN);
1774 OPCODE(ATOMIC_LOADW_UMAX);
1775 OPCODE(ATOMIC_CMP_SWAPW);
1781 //===----------------------------------------------------------------------===//
1783 //===----------------------------------------------------------------------===//
1785 // Create a new basic block after MBB.
1786 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
1787 MachineFunction &MF = *MBB->getParent();
1788 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
1789 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
1793 // Split MBB after MI and return the new block (the one that contains
1794 // instructions after MI).
1795 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
1796 MachineBasicBlock *MBB) {
1797 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1798 NewMBB->splice(NewMBB->begin(), MBB,
1799 llvm::next(MachineBasicBlock::iterator(MI)),
1801 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1805 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
1807 SystemZTargetLowering::emitSelect(MachineInstr *MI,
1808 MachineBasicBlock *MBB) const {
1809 const SystemZInstrInfo *TII = TM.getInstrInfo();
1811 unsigned DestReg = MI->getOperand(0).getReg();
1812 unsigned TrueReg = MI->getOperand(1).getReg();
1813 unsigned FalseReg = MI->getOperand(2).getReg();
1814 unsigned CCValid = MI->getOperand(3).getImm();
1815 unsigned CCMask = MI->getOperand(4).getImm();
1816 DebugLoc DL = MI->getDebugLoc();
1818 MachineBasicBlock *StartMBB = MBB;
1819 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
1820 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
1823 // BRC CCMask, JoinMBB
1824 // # fallthrough to FalseMBB
1826 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1827 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
1828 MBB->addSuccessor(JoinMBB);
1829 MBB->addSuccessor(FalseMBB);
1832 // # fallthrough to JoinMBB
1834 MBB->addSuccessor(JoinMBB);
1837 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
1840 BuildMI(*MBB, MBB->begin(), DL, TII->get(SystemZ::PHI), DestReg)
1841 .addReg(TrueReg).addMBB(StartMBB)
1842 .addReg(FalseReg).addMBB(FalseMBB);
1844 MI->eraseFromParent();
1848 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
1849 // StoreOpcode is the store to use and Invert says whether the store should
1850 // happen when the condition is false rather than true. If a STORE ON
1851 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
1853 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
1854 MachineBasicBlock *MBB,
1855 unsigned StoreOpcode, unsigned STOCOpcode,
1856 bool Invert) const {
1857 const SystemZInstrInfo *TII = TM.getInstrInfo();
1859 unsigned SrcReg = MI->getOperand(0).getReg();
1860 MachineOperand Base = MI->getOperand(1);
1861 int64_t Disp = MI->getOperand(2).getImm();
1862 unsigned IndexReg = MI->getOperand(3).getReg();
1863 unsigned CCValid = MI->getOperand(4).getImm();
1864 unsigned CCMask = MI->getOperand(5).getImm();
1865 DebugLoc DL = MI->getDebugLoc();
1867 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
1869 // Use STOCOpcode if possible. We could use different store patterns in
1870 // order to avoid matching the index register, but the performance trade-offs
1871 // might be more complicated in that case.
1872 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
1875 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
1876 .addReg(SrcReg).addOperand(Base).addImm(Disp)
1877 .addImm(CCValid).addImm(CCMask);
1878 MI->eraseFromParent();
1882 // Get the condition needed to branch around the store.
1886 MachineBasicBlock *StartMBB = MBB;
1887 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
1888 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
1891 // BRC CCMask, JoinMBB
1892 // # fallthrough to FalseMBB
1894 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1895 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
1896 MBB->addSuccessor(JoinMBB);
1897 MBB->addSuccessor(FalseMBB);
1900 // store %SrcReg, %Disp(%Index,%Base)
1901 // # fallthrough to JoinMBB
1903 BuildMI(MBB, DL, TII->get(StoreOpcode))
1904 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
1905 MBB->addSuccessor(JoinMBB);
1907 MI->eraseFromParent();
1911 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
1912 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
1913 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
1914 // BitSize is the width of the field in bits, or 0 if this is a partword
1915 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
1916 // is one of the operands. Invert says whether the field should be
1917 // inverted after performing BinOpcode (e.g. for NAND).
1919 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
1920 MachineBasicBlock *MBB,
1923 bool Invert) const {
1924 const SystemZInstrInfo *TII = TM.getInstrInfo();
1925 MachineFunction &MF = *MBB->getParent();
1926 MachineRegisterInfo &MRI = MF.getRegInfo();
1927 bool IsSubWord = (BitSize < 32);
1929 // Extract the operands. Base can be a register or a frame index.
1930 // Src2 can be a register or immediate.
1931 unsigned Dest = MI->getOperand(0).getReg();
1932 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
1933 int64_t Disp = MI->getOperand(2).getImm();
1934 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
1935 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
1936 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
1937 DebugLoc DL = MI->getDebugLoc();
1939 BitSize = MI->getOperand(6).getImm();
1941 // Subword operations use 32-bit registers.
1942 const TargetRegisterClass *RC = (BitSize <= 32 ?
1943 &SystemZ::GR32BitRegClass :
1944 &SystemZ::GR64BitRegClass);
1945 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
1946 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
1948 // Get the right opcodes for the displacement.
1949 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
1950 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
1951 assert(LOpcode && CSOpcode && "Displacement out of range");
1953 // Create virtual registers for temporary results.
1954 unsigned OrigVal = MRI.createVirtualRegister(RC);
1955 unsigned OldVal = MRI.createVirtualRegister(RC);
1956 unsigned NewVal = (BinOpcode || IsSubWord ?
1957 MRI.createVirtualRegister(RC) : Src2.getReg());
1958 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
1959 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
1961 // Insert a basic block for the main loop.
1962 MachineBasicBlock *StartMBB = MBB;
1963 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
1964 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
1968 // %OrigVal = L Disp(%Base)
1969 // # fall through to LoopMMB
1971 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
1972 .addOperand(Base).addImm(Disp).addReg(0);
1973 MBB->addSuccessor(LoopMBB);
1976 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
1977 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
1978 // %RotatedNewVal = OP %RotatedOldVal, %Src2
1979 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
1980 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
1982 // # fall through to DoneMMB
1984 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
1985 .addReg(OrigVal).addMBB(StartMBB)
1986 .addReg(Dest).addMBB(LoopMBB);
1988 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
1989 .addReg(OldVal).addReg(BitShift).addImm(0);
1991 // Perform the operation normally and then invert every bit of the field.
1992 unsigned Tmp = MRI.createVirtualRegister(RC);
1993 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
1994 .addReg(RotatedOldVal).addOperand(Src2);
1996 // XILF with the upper BitSize bits set.
1997 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
1998 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
1999 else if (BitSize == 32)
2000 // XILF with every bit set.
2001 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
2002 .addReg(Tmp).addImm(~uint32_t(0));
2004 // Use LCGR and add -1 to the result, which is more compact than
2005 // an XILF, XILH pair.
2006 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2007 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2008 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2009 .addReg(Tmp2).addImm(-1);
2011 } else if (BinOpcode)
2012 // A simply binary operation.
2013 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2014 .addReg(RotatedOldVal).addOperand(Src2);
2016 // Use RISBG to rotate Src2 into position and use it to replace the
2017 // field in RotatedOldVal.
2018 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2019 .addReg(RotatedOldVal).addReg(Src2.getReg())
2020 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2022 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2023 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2024 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2025 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2026 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2027 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2028 MBB->addSuccessor(LoopMBB);
2029 MBB->addSuccessor(DoneMBB);
2031 MI->eraseFromParent();
2035 // Implement EmitInstrWithCustomInserter for pseudo
2036 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2037 // instruction that should be used to compare the current field with the
2038 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2039 // for when the current field should be kept. BitSize is the width of
2040 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2042 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2043 MachineBasicBlock *MBB,
2044 unsigned CompareOpcode,
2045 unsigned KeepOldMask,
2046 unsigned BitSize) const {
2047 const SystemZInstrInfo *TII = TM.getInstrInfo();
2048 MachineFunction &MF = *MBB->getParent();
2049 MachineRegisterInfo &MRI = MF.getRegInfo();
2050 bool IsSubWord = (BitSize < 32);
2052 // Extract the operands. Base can be a register or a frame index.
2053 unsigned Dest = MI->getOperand(0).getReg();
2054 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2055 int64_t Disp = MI->getOperand(2).getImm();
2056 unsigned Src2 = MI->getOperand(3).getReg();
2057 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2058 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2059 DebugLoc DL = MI->getDebugLoc();
2061 BitSize = MI->getOperand(6).getImm();
2063 // Subword operations use 32-bit registers.
2064 const TargetRegisterClass *RC = (BitSize <= 32 ?
2065 &SystemZ::GR32BitRegClass :
2066 &SystemZ::GR64BitRegClass);
2067 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2068 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2070 // Get the right opcodes for the displacement.
2071 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2072 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2073 assert(LOpcode && CSOpcode && "Displacement out of range");
2075 // Create virtual registers for temporary results.
2076 unsigned OrigVal = MRI.createVirtualRegister(RC);
2077 unsigned OldVal = MRI.createVirtualRegister(RC);
2078 unsigned NewVal = MRI.createVirtualRegister(RC);
2079 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2080 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2081 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2083 // Insert 3 basic blocks for the loop.
2084 MachineBasicBlock *StartMBB = MBB;
2085 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2086 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2087 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2088 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2092 // %OrigVal = L Disp(%Base)
2093 // # fall through to LoopMMB
2095 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2096 .addOperand(Base).addImm(Disp).addReg(0);
2097 MBB->addSuccessor(LoopMBB);
2100 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2101 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2102 // CompareOpcode %RotatedOldVal, %Src2
2103 // BRC KeepOldMask, UpdateMBB
2105 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2106 .addReg(OrigVal).addMBB(StartMBB)
2107 .addReg(Dest).addMBB(UpdateMBB);
2109 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2110 .addReg(OldVal).addReg(BitShift).addImm(0);
2111 BuildMI(MBB, DL, TII->get(CompareOpcode))
2112 .addReg(RotatedOldVal).addReg(Src2);
2113 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2114 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2115 MBB->addSuccessor(UpdateMBB);
2116 MBB->addSuccessor(UseAltMBB);
2119 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2120 // # fall through to UpdateMMB
2123 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2124 .addReg(RotatedOldVal).addReg(Src2)
2125 .addImm(32).addImm(31 + BitSize).addImm(0);
2126 MBB->addSuccessor(UpdateMBB);
2129 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2130 // [ %RotatedAltVal, UseAltMBB ]
2131 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2132 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2134 // # fall through to DoneMMB
2136 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2137 .addReg(RotatedOldVal).addMBB(LoopMBB)
2138 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2140 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2141 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2142 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2143 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2144 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2145 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2146 MBB->addSuccessor(LoopMBB);
2147 MBB->addSuccessor(DoneMBB);
2149 MI->eraseFromParent();
2153 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2156 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2157 MachineBasicBlock *MBB) const {
2158 const SystemZInstrInfo *TII = TM.getInstrInfo();
2159 MachineFunction &MF = *MBB->getParent();
2160 MachineRegisterInfo &MRI = MF.getRegInfo();
2162 // Extract the operands. Base can be a register or a frame index.
2163 unsigned Dest = MI->getOperand(0).getReg();
2164 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2165 int64_t Disp = MI->getOperand(2).getImm();
2166 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2167 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2168 unsigned BitShift = MI->getOperand(5).getReg();
2169 unsigned NegBitShift = MI->getOperand(6).getReg();
2170 int64_t BitSize = MI->getOperand(7).getImm();
2171 DebugLoc DL = MI->getDebugLoc();
2173 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2175 // Get the right opcodes for the displacement.
2176 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2177 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2178 assert(LOpcode && CSOpcode && "Displacement out of range");
2180 // Create virtual registers for temporary results.
2181 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2182 unsigned OldVal = MRI.createVirtualRegister(RC);
2183 unsigned CmpVal = MRI.createVirtualRegister(RC);
2184 unsigned SwapVal = MRI.createVirtualRegister(RC);
2185 unsigned StoreVal = MRI.createVirtualRegister(RC);
2186 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2187 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2188 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2190 // Insert 2 basic blocks for the loop.
2191 MachineBasicBlock *StartMBB = MBB;
2192 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2193 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2194 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2198 // %OrigOldVal = L Disp(%Base)
2199 // # fall through to LoopMMB
2201 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
2202 .addOperand(Base).addImm(Disp).addReg(0);
2203 MBB->addSuccessor(LoopMBB);
2206 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
2207 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
2208 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
2209 // %Dest = RLL %OldVal, BitSize(%BitShift)
2210 // ^^ The low BitSize bits contain the field
2212 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
2213 // ^^ Replace the upper 32-BitSize bits of the
2214 // comparison value with those that we loaded,
2215 // so that we can use a full word comparison.
2216 // CR %Dest, %RetryCmpVal
2218 // # Fall through to SetMBB
2220 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2221 .addReg(OrigOldVal).addMBB(StartMBB)
2222 .addReg(RetryOldVal).addMBB(SetMBB);
2223 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
2224 .addReg(OrigCmpVal).addMBB(StartMBB)
2225 .addReg(RetryCmpVal).addMBB(SetMBB);
2226 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
2227 .addReg(OrigSwapVal).addMBB(StartMBB)
2228 .addReg(RetrySwapVal).addMBB(SetMBB);
2229 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
2230 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
2231 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
2232 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2233 BuildMI(MBB, DL, TII->get(SystemZ::CR))
2234 .addReg(Dest).addReg(RetryCmpVal);
2235 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2236 .addImm(SystemZ::CCMASK_ICMP)
2237 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
2238 MBB->addSuccessor(DoneMBB);
2239 MBB->addSuccessor(SetMBB);
2242 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
2243 // ^^ Replace the upper 32-BitSize bits of the new
2244 // value with those that we loaded.
2245 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
2246 // ^^ Rotate the new field to its proper position.
2247 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
2249 // # fall through to ExitMMB
2251 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
2252 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2253 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
2254 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
2255 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
2256 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2257 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2258 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2259 MBB->addSuccessor(LoopMBB);
2260 MBB->addSuccessor(DoneMBB);
2262 MI->eraseFromParent();
2266 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
2267 // if the high register of the GR128 value must be cleared or false if
2268 // it's "don't care". SubReg is subreg_odd32 when extending a GR32
2269 // and subreg_odd when extending a GR64.
2271 SystemZTargetLowering::emitExt128(MachineInstr *MI,
2272 MachineBasicBlock *MBB,
2273 bool ClearEven, unsigned SubReg) const {
2274 const SystemZInstrInfo *TII = TM.getInstrInfo();
2275 MachineFunction &MF = *MBB->getParent();
2276 MachineRegisterInfo &MRI = MF.getRegInfo();
2277 DebugLoc DL = MI->getDebugLoc();
2279 unsigned Dest = MI->getOperand(0).getReg();
2280 unsigned Src = MI->getOperand(1).getReg();
2281 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2283 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
2285 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2286 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2288 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
2290 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
2291 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_high);
2294 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
2295 .addReg(In128).addReg(Src).addImm(SubReg);
2297 MI->eraseFromParent();
2302 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
2303 MachineBasicBlock *MBB,
2304 unsigned Opcode) const {
2305 const SystemZInstrInfo *TII = TM.getInstrInfo();
2306 DebugLoc DL = MI->getDebugLoc();
2308 MachineOperand DestBase = MI->getOperand(0);
2309 uint64_t DestDisp = MI->getOperand(1).getImm();
2310 MachineOperand SrcBase = MI->getOperand(2);
2311 uint64_t SrcDisp = MI->getOperand(3).getImm();
2312 uint64_t Length = MI->getOperand(4).getImm();
2314 BuildMI(*MBB, MI, DL, TII->get(Opcode))
2315 .addOperand(DestBase).addImm(DestDisp).addImm(Length)
2316 .addOperand(SrcBase).addImm(SrcDisp);
2318 MI->eraseFromParent();
2322 // Decompose string pseudo-instruction MI into a loop that continually performs
2323 // Opcode until CC != 3.
2325 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
2326 MachineBasicBlock *MBB,
2327 unsigned Opcode) const {
2328 const SystemZInstrInfo *TII = TM.getInstrInfo();
2329 MachineFunction &MF = *MBB->getParent();
2330 MachineRegisterInfo &MRI = MF.getRegInfo();
2331 DebugLoc DL = MI->getDebugLoc();
2333 uint64_t End1Reg = MI->getOperand(0).getReg();
2334 uint64_t Start1Reg = MI->getOperand(1).getReg();
2335 uint64_t Start2Reg = MI->getOperand(2).getReg();
2336 uint64_t CharReg = MI->getOperand(3).getReg();
2338 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
2339 uint64_t This1Reg = MRI.createVirtualRegister(RC);
2340 uint64_t This2Reg = MRI.createVirtualRegister(RC);
2341 uint64_t End2Reg = MRI.createVirtualRegister(RC);
2343 MachineBasicBlock *StartMBB = MBB;
2344 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2345 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2348 // # fall through to LoopMMB
2349 MBB->addSuccessor(LoopMBB);
2352 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
2353 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
2355 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0W
2357 // # fall through to DoneMMB
2359 // The load of R0W can be hoisted by post-RA LICM.
2362 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
2363 .addReg(Start1Reg).addMBB(StartMBB)
2364 .addReg(End1Reg).addMBB(LoopMBB);
2365 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
2366 .addReg(Start2Reg).addMBB(StartMBB)
2367 .addReg(End2Reg).addMBB(LoopMBB);
2368 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0W).addReg(CharReg);
2369 BuildMI(MBB, DL, TII->get(Opcode))
2370 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
2371 .addReg(This1Reg).addReg(This2Reg);
2372 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2373 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
2374 MBB->addSuccessor(LoopMBB);
2375 MBB->addSuccessor(DoneMBB);
2377 DoneMBB->addLiveIn(SystemZ::CC);
2379 MI->eraseFromParent();
2383 MachineBasicBlock *SystemZTargetLowering::
2384 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
2385 switch (MI->getOpcode()) {
2386 case SystemZ::Select32:
2387 case SystemZ::SelectF32:
2388 case SystemZ::Select64:
2389 case SystemZ::SelectF64:
2390 case SystemZ::SelectF128:
2391 return emitSelect(MI, MBB);
2393 case SystemZ::CondStore8_32:
2394 return emitCondStore(MI, MBB, SystemZ::STC32, 0, false);
2395 case SystemZ::CondStore8_32Inv:
2396 return emitCondStore(MI, MBB, SystemZ::STC32, 0, true);
2397 case SystemZ::CondStore16_32:
2398 return emitCondStore(MI, MBB, SystemZ::STH32, 0, false);
2399 case SystemZ::CondStore16_32Inv:
2400 return emitCondStore(MI, MBB, SystemZ::STH32, 0, true);
2401 case SystemZ::CondStore32_32:
2402 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, false);
2403 case SystemZ::CondStore32_32Inv:
2404 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, true);
2405 case SystemZ::CondStore8:
2406 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
2407 case SystemZ::CondStore8Inv:
2408 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
2409 case SystemZ::CondStore16:
2410 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
2411 case SystemZ::CondStore16Inv:
2412 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
2413 case SystemZ::CondStore32:
2414 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
2415 case SystemZ::CondStore32Inv:
2416 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
2417 case SystemZ::CondStore64:
2418 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
2419 case SystemZ::CondStore64Inv:
2420 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
2421 case SystemZ::CondStoreF32:
2422 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
2423 case SystemZ::CondStoreF32Inv:
2424 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
2425 case SystemZ::CondStoreF64:
2426 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
2427 case SystemZ::CondStoreF64Inv:
2428 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
2430 case SystemZ::AEXT128_64:
2431 return emitExt128(MI, MBB, false, SystemZ::subreg_low);
2432 case SystemZ::ZEXT128_32:
2433 return emitExt128(MI, MBB, true, SystemZ::subreg_low32);
2434 case SystemZ::ZEXT128_64:
2435 return emitExt128(MI, MBB, true, SystemZ::subreg_low);
2437 case SystemZ::ATOMIC_SWAPW:
2438 return emitAtomicLoadBinary(MI, MBB, 0, 0);
2439 case SystemZ::ATOMIC_SWAP_32:
2440 return emitAtomicLoadBinary(MI, MBB, 0, 32);
2441 case SystemZ::ATOMIC_SWAP_64:
2442 return emitAtomicLoadBinary(MI, MBB, 0, 64);
2444 case SystemZ::ATOMIC_LOADW_AR:
2445 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
2446 case SystemZ::ATOMIC_LOADW_AFI:
2447 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
2448 case SystemZ::ATOMIC_LOAD_AR:
2449 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
2450 case SystemZ::ATOMIC_LOAD_AHI:
2451 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
2452 case SystemZ::ATOMIC_LOAD_AFI:
2453 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
2454 case SystemZ::ATOMIC_LOAD_AGR:
2455 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
2456 case SystemZ::ATOMIC_LOAD_AGHI:
2457 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
2458 case SystemZ::ATOMIC_LOAD_AGFI:
2459 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
2461 case SystemZ::ATOMIC_LOADW_SR:
2462 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
2463 case SystemZ::ATOMIC_LOAD_SR:
2464 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
2465 case SystemZ::ATOMIC_LOAD_SGR:
2466 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
2468 case SystemZ::ATOMIC_LOADW_NR:
2469 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
2470 case SystemZ::ATOMIC_LOADW_NILH:
2471 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0);
2472 case SystemZ::ATOMIC_LOAD_NR:
2473 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
2474 case SystemZ::ATOMIC_LOAD_NILL32:
2475 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32);
2476 case SystemZ::ATOMIC_LOAD_NILH32:
2477 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32);
2478 case SystemZ::ATOMIC_LOAD_NILF32:
2479 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32);
2480 case SystemZ::ATOMIC_LOAD_NGR:
2481 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
2482 case SystemZ::ATOMIC_LOAD_NILL:
2483 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64);
2484 case SystemZ::ATOMIC_LOAD_NILH:
2485 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64);
2486 case SystemZ::ATOMIC_LOAD_NIHL:
2487 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64);
2488 case SystemZ::ATOMIC_LOAD_NIHH:
2489 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64);
2490 case SystemZ::ATOMIC_LOAD_NILF:
2491 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64);
2492 case SystemZ::ATOMIC_LOAD_NIHF:
2493 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64);
2495 case SystemZ::ATOMIC_LOADW_OR:
2496 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
2497 case SystemZ::ATOMIC_LOADW_OILH:
2498 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 0);
2499 case SystemZ::ATOMIC_LOAD_OR:
2500 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
2501 case SystemZ::ATOMIC_LOAD_OILL32:
2502 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL32, 32);
2503 case SystemZ::ATOMIC_LOAD_OILH32:
2504 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 32);
2505 case SystemZ::ATOMIC_LOAD_OILF32:
2506 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF32, 32);
2507 case SystemZ::ATOMIC_LOAD_OGR:
2508 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
2509 case SystemZ::ATOMIC_LOAD_OILL:
2510 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 64);
2511 case SystemZ::ATOMIC_LOAD_OILH:
2512 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 64);
2513 case SystemZ::ATOMIC_LOAD_OIHL:
2514 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL, 64);
2515 case SystemZ::ATOMIC_LOAD_OIHH:
2516 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH, 64);
2517 case SystemZ::ATOMIC_LOAD_OILF:
2518 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 64);
2519 case SystemZ::ATOMIC_LOAD_OIHF:
2520 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF, 64);
2522 case SystemZ::ATOMIC_LOADW_XR:
2523 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
2524 case SystemZ::ATOMIC_LOADW_XILF:
2525 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 0);
2526 case SystemZ::ATOMIC_LOAD_XR:
2527 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
2528 case SystemZ::ATOMIC_LOAD_XILF32:
2529 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 32);
2530 case SystemZ::ATOMIC_LOAD_XGR:
2531 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
2532 case SystemZ::ATOMIC_LOAD_XILF:
2533 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 64);
2534 case SystemZ::ATOMIC_LOAD_XIHF:
2535 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF, 64);
2537 case SystemZ::ATOMIC_LOADW_NRi:
2538 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
2539 case SystemZ::ATOMIC_LOADW_NILHi:
2540 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0, true);
2541 case SystemZ::ATOMIC_LOAD_NRi:
2542 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
2543 case SystemZ::ATOMIC_LOAD_NILL32i:
2544 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32, true);
2545 case SystemZ::ATOMIC_LOAD_NILH32i:
2546 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32, true);
2547 case SystemZ::ATOMIC_LOAD_NILF32i:
2548 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32, true);
2549 case SystemZ::ATOMIC_LOAD_NGRi:
2550 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
2551 case SystemZ::ATOMIC_LOAD_NILLi:
2552 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64, true);
2553 case SystemZ::ATOMIC_LOAD_NILHi:
2554 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64, true);
2555 case SystemZ::ATOMIC_LOAD_NIHLi:
2556 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64, true);
2557 case SystemZ::ATOMIC_LOAD_NIHHi:
2558 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64, true);
2559 case SystemZ::ATOMIC_LOAD_NILFi:
2560 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64, true);
2561 case SystemZ::ATOMIC_LOAD_NIHFi:
2562 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64, true);
2564 case SystemZ::ATOMIC_LOADW_MIN:
2565 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2566 SystemZ::CCMASK_CMP_LE, 0);
2567 case SystemZ::ATOMIC_LOAD_MIN_32:
2568 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2569 SystemZ::CCMASK_CMP_LE, 32);
2570 case SystemZ::ATOMIC_LOAD_MIN_64:
2571 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
2572 SystemZ::CCMASK_CMP_LE, 64);
2574 case SystemZ::ATOMIC_LOADW_MAX:
2575 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2576 SystemZ::CCMASK_CMP_GE, 0);
2577 case SystemZ::ATOMIC_LOAD_MAX_32:
2578 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2579 SystemZ::CCMASK_CMP_GE, 32);
2580 case SystemZ::ATOMIC_LOAD_MAX_64:
2581 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
2582 SystemZ::CCMASK_CMP_GE, 64);
2584 case SystemZ::ATOMIC_LOADW_UMIN:
2585 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2586 SystemZ::CCMASK_CMP_LE, 0);
2587 case SystemZ::ATOMIC_LOAD_UMIN_32:
2588 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2589 SystemZ::CCMASK_CMP_LE, 32);
2590 case SystemZ::ATOMIC_LOAD_UMIN_64:
2591 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
2592 SystemZ::CCMASK_CMP_LE, 64);
2594 case SystemZ::ATOMIC_LOADW_UMAX:
2595 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2596 SystemZ::CCMASK_CMP_GE, 0);
2597 case SystemZ::ATOMIC_LOAD_UMAX_32:
2598 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2599 SystemZ::CCMASK_CMP_GE, 32);
2600 case SystemZ::ATOMIC_LOAD_UMAX_64:
2601 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
2602 SystemZ::CCMASK_CMP_GE, 64);
2604 case SystemZ::ATOMIC_CMP_SWAPW:
2605 return emitAtomicCmpSwapW(MI, MBB);
2606 case SystemZ::MVCWrapper:
2607 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
2608 case SystemZ::CLCWrapper:
2609 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
2610 case SystemZ::CLSTLoop:
2611 return emitStringWrapper(MI, MBB, SystemZ::CLST);
2612 case SystemZ::MVSTLoop:
2613 return emitStringWrapper(MI, MBB, SystemZ::MVST);
2614 case SystemZ::SRSTLoop:
2615 return emitStringWrapper(MI, MBB, SystemZ::SRST);
2617 llvm_unreachable("Unexpected instr type to insert");