1 //===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef SPARCINSTRUCTIONINFO_H
15 #define SPARCINSTRUCTIONINFO_H
17 #include "SparcRegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h"
20 #define GET_INSTRINFO_HEADER
21 #include "SparcGenInstrInfo.inc"
25 /// SPII - This namespace holds all of the target specific flags that
26 /// instruction info tracks.
37 class SparcInstrInfo : public SparcGenInstrInfo {
38 const SparcRegisterInfo RI;
39 const SparcSubtarget& Subtarget;
41 explicit SparcInstrInfo(SparcSubtarget &ST);
43 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
44 /// such, whenever a client has an instance of instruction info, it should
45 /// always be able to get register info as well (through this method).
47 virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
49 /// isLoadFromStackSlot - If the specified machine instruction is a direct
50 /// load from a stack slot, return the virtual or physical register number of
51 /// the destination along with the FrameIndex of the loaded stack slot. If
52 /// not, return 0. This predicate must return 0 if the instruction has
53 /// any side effects other than loading from the stack slot.
54 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
55 int &FrameIndex) const;
57 /// isStoreToStackSlot - If the specified machine instruction is a direct
58 /// store to a stack slot, return the virtual or physical register number of
59 /// the source reg along with the FrameIndex of the loaded stack slot. If
60 /// not, return 0. This predicate must return 0 if the instruction has
61 /// any side effects other than storing to the stack slot.
62 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
63 int &FrameIndex) const;
65 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
66 MachineBasicBlock *&FBB,
67 SmallVectorImpl<MachineOperand> &Cond,
68 bool AllowModify = false) const ;
70 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
72 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
73 MachineBasicBlock *FBB,
74 const SmallVectorImpl<MachineOperand> &Cond,
77 virtual void copyPhysReg(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator I, DebugLoc DL,
79 unsigned DestReg, unsigned SrcReg,
82 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MBBI,
84 unsigned SrcReg, bool isKill, int FrameIndex,
85 const TargetRegisterClass *RC,
86 const TargetRegisterInfo *TRI) const;
88 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator MBBI,
90 unsigned DestReg, int FrameIndex,
91 const TargetRegisterClass *RC,
92 const TargetRegisterInfo *TRI) const;
94 unsigned getGlobalBaseReg(MachineFunction *MF) const;