1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def gds : Operand <i1> {
268 let PrintMethod = "printGDS";
270 def glc : Operand <i1> {
271 let PrintMethod = "printGLC";
273 def slc : Operand <i1> {
274 let PrintMethod = "printSLC";
276 def tfe : Operand <i1> {
277 let PrintMethod = "printTFE";
280 def omod : Operand <i32> {
281 let PrintMethod = "printOModSI";
284 def ClampMod : Operand <i1> {
285 let PrintMethod = "printClampSI";
288 } // End OperandType = "OPERAND_IMMEDIATE"
290 def VOPDstS64 : VOPDstOperand <SReg_64>;
292 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
296 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
297 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
299 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
300 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
301 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
302 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
303 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
304 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
306 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
307 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
308 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
309 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
311 //===----------------------------------------------------------------------===//
312 // SI assembler operands
313 //===----------------------------------------------------------------------===//
334 //===----------------------------------------------------------------------===//
336 // SI Instruction multiclass helpers.
338 // Instructions with _32 take 32-bit operands.
339 // Instructions with _64 take 64-bit operands.
341 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
342 // encoding is the standard encoding, but instruction that make use of
343 // any of the instruction modifiers must use the 64-bit encoding.
345 // Instructions with _e32 use the 32-bit encoding.
346 // Instructions with _e64 use the 64-bit encoding.
348 //===----------------------------------------------------------------------===//
350 class SIMCInstr <string pseudo, int subtarget> {
351 string PseudoInstr = pseudo;
352 int Subtarget = subtarget;
355 //===----------------------------------------------------------------------===//
357 //===----------------------------------------------------------------------===//
359 class EXPCommon : InstSI<
361 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
362 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
363 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
372 let isPseudo = 1, isCodeGenOnly = 1 in {
373 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
376 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
378 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
381 //===----------------------------------------------------------------------===//
383 //===----------------------------------------------------------------------===//
385 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
386 SOP1 <outs, ins, "", pattern>,
387 SIMCInstr<opName, SISubtarget.NONE> {
389 let isCodeGenOnly = 1;
392 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
393 SOP1 <outs, ins, asm, []>,
395 SIMCInstr<opName, SISubtarget.SI>;
397 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
398 SOP1 <outs, ins, asm, []>,
400 SIMCInstr<opName, SISubtarget.VI>;
402 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
405 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
407 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
409 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
413 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
414 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
415 opName#" $dst, $src0", pattern
418 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
419 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
420 opName#" $dst, $src0", pattern
423 // no input, 64-bit output.
424 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
425 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
427 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
432 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
438 // 64-bit input, no output
439 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
440 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
442 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
447 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
453 // 64-bit input, 32-bit output.
454 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
455 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
456 opName#" $dst, $src0", pattern
459 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
460 SOP2<outs, ins, "", pattern>,
461 SIMCInstr<opName, SISubtarget.NONE> {
463 let isCodeGenOnly = 1;
466 // Pseudo instructions have no encodings, but adding this field here allows
468 // let sdst = xxx in {
469 // for multiclasses that include both real and pseudo instructions.
470 field bits<7> sdst = 0;
473 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
474 SOP2<outs, ins, asm, []>,
476 SIMCInstr<opName, SISubtarget.SI>;
478 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
479 SOP2<outs, ins, asm, []>,
481 SIMCInstr<opName, SISubtarget.VI>;
483 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
484 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
485 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
487 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
488 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
489 opName#" $dst, $src0, $src1 [$scc]">;
491 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
492 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
493 opName#" $dst, $src0, $src1 [$scc]">;
496 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
499 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
501 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
503 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
507 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
508 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
509 opName#" $dst, $src0, $src1", pattern
512 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
513 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
514 opName#" $dst, $src0, $src1", pattern
517 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
518 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
519 opName#" $dst, $src0, $src1", pattern
522 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
523 string opName, PatLeaf cond> : SOPC <
524 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
525 opName#" $src0, $src1", []>;
527 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
528 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
530 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
531 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
533 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
534 SOPK <outs, ins, "", pattern>,
535 SIMCInstr<opName, SISubtarget.NONE> {
537 let isCodeGenOnly = 1;
540 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
541 SOPK <outs, ins, asm, []>,
543 SIMCInstr<opName, SISubtarget.SI>;
545 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
546 SOPK <outs, ins, asm, []>,
548 SIMCInstr<opName, SISubtarget.VI>;
550 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
551 string asm = opName#opAsm> {
552 def "" : SOPK_Pseudo <opName, outs, ins, []>;
554 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
556 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
560 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
561 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
564 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
565 opName#" $dst, $src0">;
567 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
568 opName#" $dst, $src0">;
571 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
572 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
573 (ins SReg_32:$src0, u16imm:$src1), pattern>;
575 let DisableEncoding = "$dst" in {
576 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
577 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
579 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
580 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
584 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
585 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
589 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
590 string argAsm, string asm = opName#argAsm> {
592 def "" : SOPK_Pseudo <opName, outs, ins, []>;
594 def _si : SOPK <outs, ins, asm, []>,
596 SIMCInstr<opName, SISubtarget.SI> {
597 let AssemblerPredicates = [isSICI];
598 let isCodeGenOnly = 0;
601 def _vi : SOPK <outs, ins, asm, []>,
603 SIMCInstr<opName, SISubtarget.VI> {
604 let AssemblerPredicates = [isVI];
605 let isCodeGenOnly = 0;
608 //===----------------------------------------------------------------------===//
610 //===----------------------------------------------------------------------===//
612 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
613 SMRD <outs, ins, "", pattern>,
614 SIMCInstr<opName, SISubtarget.NONE> {
616 let isCodeGenOnly = 1;
619 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
621 SMRD <outs, ins, asm, []>,
623 SIMCInstr<opName, SISubtarget.SI>;
625 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
627 SMRD <outs, ins, asm, []>,
629 SIMCInstr<opName, SISubtarget.VI>;
631 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
632 string asm, list<dag> pattern> {
634 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
636 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
638 // glc is only applicable to scalar stores, which are not yet
641 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
645 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
646 RegisterClass dstClass> {
648 op, opName#"_IMM", 1, (outs dstClass:$dst),
649 (ins baseClass:$sbase, u32imm:$offset),
650 opName#" $dst, $sbase, $offset", []
653 defm _SGPR : SMRD_m <
654 op, opName#"_SGPR", 0, (outs dstClass:$dst),
655 (ins baseClass:$sbase, SReg_32:$soff),
656 opName#" $dst, $sbase, $soff", []
660 //===----------------------------------------------------------------------===//
661 // Vector ALU classes
662 //===----------------------------------------------------------------------===//
664 // This must always be right before the operand being input modified.
665 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
666 let PrintMethod = "printOperandAndMods";
668 def InputModsNoDefault : Operand <i32> {
669 let PrintMethod = "printOperandAndMods";
672 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
674 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
675 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
679 // Returns the register class to use for the destination of VOP[123C]
680 // instructions for the given VT.
681 class getVALUDstForVT<ValueType VT> {
682 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
683 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
684 VOPDstOperand<SReg_64>)); // else VT == i1
687 // Returns the register class to use for source 0 of VOP[12C]
688 // instructions for the given VT.
689 class getVOPSrc0ForVT<ValueType VT> {
690 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
693 // Returns the register class to use for source 1 of VOP[12C] for the
695 class getVOPSrc1ForVT<ValueType VT> {
696 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
699 // Returns the register class to use for sources of VOP3 instructions for the
701 class getVOP3SrcForVT<ValueType VT> {
702 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
705 // Returns 1 if the source arguments have modifiers, 0 if they do not.
706 class hasModifiers<ValueType SrcVT> {
707 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
708 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
711 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
712 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
713 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
714 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
718 // Returns the input arguments for VOP3 instructions for the given SrcVT.
719 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
720 RegisterOperand Src2RC, int NumSrcArgs,
724 !if (!eq(NumSrcArgs, 1),
725 !if (!eq(HasModifiers, 1),
726 // VOP1 with modifiers
727 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
728 ClampMod:$clamp, omod:$omod)
730 // VOP1 without modifiers
733 !if (!eq(NumSrcArgs, 2),
734 !if (!eq(HasModifiers, 1),
735 // VOP 2 with modifiers
736 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
737 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
738 ClampMod:$clamp, omod:$omod)
740 // VOP2 without modifiers
741 (ins Src0RC:$src0, Src1RC:$src1)
743 /* NumSrcArgs == 3 */,
744 !if (!eq(HasModifiers, 1),
745 // VOP3 with modifiers
746 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
747 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
748 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
749 ClampMod:$clamp, omod:$omod)
751 // VOP3 without modifiers
752 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
756 // Returns the assembly string for the inputs and outputs of a VOP[12C]
757 // instruction. This does not add the _e32 suffix, so it can be reused
759 class getAsm32 <int NumSrcArgs> {
760 string src1 = ", $src1";
761 string src2 = ", $src2";
762 string ret = "$dst, $src0"#
763 !if(!eq(NumSrcArgs, 1), "", src1)#
764 !if(!eq(NumSrcArgs, 3), src2, "");
767 // Returns the assembly string for the inputs and outputs of a VOP3
769 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
770 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
771 string src1 = !if(!eq(NumSrcArgs, 1), "",
772 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
773 " $src1_modifiers,"));
774 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
776 !if(!eq(HasModifiers, 0),
777 getAsm32<NumSrcArgs>.ret,
778 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
782 class VOPProfile <list<ValueType> _ArgVT> {
784 field list<ValueType> ArgVT = _ArgVT;
786 field ValueType DstVT = ArgVT[0];
787 field ValueType Src0VT = ArgVT[1];
788 field ValueType Src1VT = ArgVT[2];
789 field ValueType Src2VT = ArgVT[3];
790 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
791 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
792 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
793 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
794 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
795 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
797 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
798 field bit HasModifiers = hasModifiers<Src0VT>.ret;
800 field dag Outs = (outs DstRC:$dst);
802 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
803 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
806 field string Asm32 = getAsm32<NumSrcArgs>.ret;
807 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
810 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
811 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
812 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
813 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
814 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
815 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
816 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
817 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
818 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
820 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
821 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
822 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
823 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
824 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
825 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
826 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
827 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
828 let Src0RC32 = VCSrc_32;
831 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
832 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
833 let Asm64 = "$dst, $src0_modifiers, $src1";
836 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
837 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
838 let Asm64 = "$dst, $src0_modifiers, $src1";
841 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
842 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
843 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
844 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
845 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
846 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
847 let Asm64 = "$dst, $src0, $src1, $src2";
850 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
851 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
852 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
853 field string Asm = "$dst, $src0, $vsrc1, $src2";
855 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
856 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
857 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
860 class VOP <string opName> {
861 string OpName = opName;
864 class VOP2_REV <string revOp, bit isOrig> {
865 string RevOp = revOp;
869 class AtomicNoRet <string noRetOp, bit isRet> {
870 string NoRetOp = noRetOp;
874 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
875 VOP1Common <outs, ins, "", pattern>,
877 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
879 let isCodeGenOnly = 1;
885 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
886 VOP1<op.SI, outs, ins, asm, []>,
887 SIMCInstr <opName#"_e32", SISubtarget.SI>;
889 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
890 VOP1<op.VI, outs, ins, asm, []>,
891 SIMCInstr <opName#"_e32", SISubtarget.VI>;
893 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
895 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
897 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
899 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
902 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
904 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
906 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
909 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
910 VOP2Common <outs, ins, "", pattern>,
912 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
914 let isCodeGenOnly = 1;
917 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
918 VOP2 <op.SI, outs, ins, opName#asm, []>,
919 SIMCInstr <opName#"_e32", SISubtarget.SI>;
921 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
922 VOP2 <op.VI, outs, ins, opName#asm, []>,
923 SIMCInstr <opName#"_e32", SISubtarget.VI>;
925 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
926 string opName, string revOp> {
927 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
928 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
930 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
933 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
934 string opName, string revOp> {
935 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
936 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
938 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
940 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
944 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
946 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
947 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
948 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
949 bits<2> omod = !if(HasModifiers, ?, 0);
950 bits<1> clamp = !if(HasModifiers, ?, 0);
951 bits<9> src1 = !if(HasSrc1, ?, 0);
952 bits<9> src2 = !if(HasSrc2, ?, 0);
955 class VOP3DisableModFields <bit HasSrc0Mods,
958 bit HasOutputMods = 0> {
959 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
960 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
961 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
962 bits<2> omod = !if(HasOutputMods, ?, 0);
963 bits<1> clamp = !if(HasOutputMods, ?, 0);
966 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
967 VOP3Common <outs, ins, "", pattern>,
969 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
971 let isCodeGenOnly = 1;
974 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
975 VOP3Common <outs, ins, asm, []>,
977 SIMCInstr<opName#"_e64", SISubtarget.SI>;
979 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
980 VOP3Common <outs, ins, asm, []>,
982 SIMCInstr <opName#"_e64", SISubtarget.VI>;
984 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
985 VOP3Common <outs, ins, asm, []>,
987 SIMCInstr<opName#"_e64", SISubtarget.SI>;
989 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
990 VOP3Common <outs, ins, asm, []>,
992 SIMCInstr <opName#"_e64", SISubtarget.VI>;
994 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
995 string opName, int NumSrcArgs, bit HasMods = 1> {
997 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
999 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1000 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1001 !if(!eq(NumSrcArgs, 2), 0, 1),
1003 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1004 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1005 !if(!eq(NumSrcArgs, 2), 0, 1),
1009 // VOP3_m without source modifiers
1010 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1011 string opName, int NumSrcArgs, bit HasMods = 1> {
1013 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1015 let src0_modifiers = 0,
1020 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1021 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1025 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1026 list<dag> pattern, string opName, bit HasMods = 1> {
1028 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1030 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1031 VOP3DisableFields<0, 0, HasMods>;
1033 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1034 VOP3DisableFields<0, 0, HasMods>;
1037 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1038 list<dag> pattern, string opName, bit HasMods = 1> {
1040 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1042 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1043 VOP3DisableFields<0, 0, HasMods>;
1044 // No VI instruction. This class is for SI only.
1047 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1048 list<dag> pattern, string opName, string revOp,
1049 bit HasMods = 1, bit UseFullOp = 0> {
1051 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1052 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1054 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1055 VOP3DisableFields<1, 0, HasMods>;
1057 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1058 VOP3DisableFields<1, 0, HasMods>;
1061 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1062 list<dag> pattern, string opName, string revOp,
1063 bit HasMods = 1, bit UseFullOp = 0> {
1065 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1066 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1068 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1069 VOP3DisableFields<1, 0, HasMods>;
1071 // No VI instruction. This class is for SI only.
1074 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1075 // option of implicit vcc use?
1076 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1077 list<dag> pattern, string opName, string revOp,
1078 bit HasMods = 1, bit UseFullOp = 0> {
1079 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1080 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1082 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1083 // can write it into any SGPR. We currently don't use the carry out,
1084 // so for now hardcode it to VCC as well.
1085 let sdst = SIOperand.VCC, Defs = [VCC] in {
1086 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1087 VOP3DisableFields<1, 0, HasMods>;
1089 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1090 VOP3DisableFields<1, 0, HasMods>;
1091 } // End sdst = SIOperand.VCC, Defs = [VCC]
1094 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1095 list<dag> pattern, string opName, string revOp,
1096 bit HasMods = 1, bit UseFullOp = 0> {
1097 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1100 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1101 VOP3DisableFields<1, 1, HasMods>;
1103 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1104 VOP3DisableFields<1, 1, HasMods>;
1107 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1108 list<dag> pattern, string opName,
1109 bit HasMods, bit defExec, string revOp> {
1111 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1112 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1114 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1115 VOP3DisableFields<1, 0, HasMods> {
1116 let Defs = !if(defExec, [EXEC], []);
1119 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1120 VOP3DisableFields<1, 0, HasMods> {
1121 let Defs = !if(defExec, [EXEC], []);
1125 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1126 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1127 string asm, list<dag> pattern = []> {
1128 let isPseudo = 1, isCodeGenOnly = 1 in {
1129 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1130 SIMCInstr<opName, SISubtarget.NONE>;
1133 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1134 SIMCInstr <opName, SISubtarget.SI>;
1136 def _vi : VOP3Common <outs, ins, asm, []>,
1138 VOP3DisableFields <1, 0, 0>,
1139 SIMCInstr <opName, SISubtarget.VI>;
1142 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1143 dag ins32, string asm32, list<dag> pat32,
1144 dag ins64, string asm64, list<dag> pat64,
1147 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1149 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1152 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1153 SDPatternOperator node = null_frag> : VOP1_Helper <
1155 P.Ins32, P.Asm32, [],
1158 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1159 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1160 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1164 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1165 SDPatternOperator node = null_frag> {
1167 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1169 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1171 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1172 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1173 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1174 opName, P.HasModifiers>;
1177 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1178 dag ins32, string asm32, list<dag> pat32,
1179 dag ins64, string asm64, list<dag> pat64,
1180 string revOp, bit HasMods> {
1181 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1183 defm _e64 : VOP3_2_m <op,
1184 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1188 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1189 SDPatternOperator node = null_frag,
1190 string revOp = opName> : VOP2_Helper <
1192 P.Ins32, P.Asm32, [],
1196 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1197 i1:$clamp, i32:$omod)),
1198 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1199 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1200 revOp, P.HasModifiers
1203 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1204 SDPatternOperator node = null_frag,
1205 string revOp = opName> {
1206 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1208 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1211 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1212 i1:$clamp, i32:$omod)),
1213 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1214 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1215 opName, revOp, P.HasModifiers>;
1218 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1219 dag ins32, string asm32, list<dag> pat32,
1220 dag ins64, string asm64, list<dag> pat64,
1221 string revOp, bit HasMods> {
1223 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1225 defm _e64 : VOP3b_2_m <op,
1226 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1230 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1231 SDPatternOperator node = null_frag,
1232 string revOp = opName> : VOP2b_Helper <
1234 P.Ins32, P.Asm32, [],
1238 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1239 i1:$clamp, i32:$omod)),
1240 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1241 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1242 revOp, P.HasModifiers
1245 // A VOP2 instruction that is VOP3-only on VI.
1246 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1247 dag ins32, string asm32, list<dag> pat32,
1248 dag ins64, string asm64, list<dag> pat64,
1249 string revOp, bit HasMods> {
1250 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1252 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1256 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1257 SDPatternOperator node = null_frag,
1258 string revOp = opName>
1261 P.Ins32, P.Asm32, [],
1265 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1266 i1:$clamp, i32:$omod)),
1267 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1268 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1269 revOp, P.HasModifiers
1272 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1274 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1276 let isCodeGenOnly = 0 in {
1277 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1278 !strconcat(opName, VOP_MADK.Asm), []>,
1279 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1282 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1283 !strconcat(opName, VOP_MADK.Asm), []>,
1284 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1286 } // End isCodeGenOnly = 0
1289 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1290 VOPCCommon <ins, "", pattern>,
1292 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1294 let isCodeGenOnly = 1;
1297 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1298 string opName, bit DefExec, string revOpName = ""> {
1299 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1301 def _si : VOPC<op.SI, ins, asm, []>,
1302 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1303 let Defs = !if(DefExec, [EXEC], []);
1304 let hasSideEffects = DefExec;
1307 def _vi : VOPC<op.VI, ins, asm, []>,
1308 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1309 let Defs = !if(DefExec, [EXEC], []);
1310 let hasSideEffects = DefExec;
1314 multiclass VOPC_Helper <vopc op, string opName,
1315 dag ins32, string asm32, list<dag> pat32,
1316 dag out64, dag ins64, string asm64, list<dag> pat64,
1317 bit HasMods, bit DefExec, string revOp> {
1318 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1320 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1321 opName, HasMods, DefExec, revOp>;
1324 // Special case for class instructions which only have modifiers on
1325 // the 1st source operand.
1326 multiclass VOPC_Class_Helper <vopc op, string opName,
1327 dag ins32, string asm32, list<dag> pat32,
1328 dag out64, dag ins64, string asm64, list<dag> pat64,
1329 bit HasMods, bit DefExec, string revOp> {
1330 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1332 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1333 opName, HasMods, DefExec, revOp>,
1334 VOP3DisableModFields<1, 0, 0>;
1337 multiclass VOPCInst <vopc op, string opName,
1338 VOPProfile P, PatLeaf cond = COND_NULL,
1339 string revOp = opName,
1340 bit DefExec = 0> : VOPC_Helper <
1342 P.Ins32, P.Asm32, [],
1343 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1346 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1347 i1:$clamp, i32:$omod)),
1348 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1350 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1351 P.HasModifiers, DefExec, revOp
1354 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1355 bit DefExec = 0> : VOPC_Class_Helper <
1357 P.Ins32, P.Asm32, [],
1358 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1361 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1362 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1363 P.HasModifiers, DefExec, opName
1367 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1368 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1370 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1371 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1373 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1374 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1376 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1377 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1380 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1381 PatLeaf cond = COND_NULL,
1383 : VOPCInst <op, opName, P, cond, revOp, 1>;
1385 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1386 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1388 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1389 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1391 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1392 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1394 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1395 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1397 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1398 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1399 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1402 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1403 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1405 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1406 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1408 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1409 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1411 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1412 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1414 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1415 SDPatternOperator node = null_frag> : VOP3_Helper <
1416 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1417 !if(!eq(P.NumSrcArgs, 3),
1420 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1421 i1:$clamp, i32:$omod)),
1422 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1423 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1424 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1426 !if(!eq(P.NumSrcArgs, 2),
1429 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1430 i1:$clamp, i32:$omod)),
1431 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1432 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1433 /* P.NumSrcArgs == 1 */,
1436 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1437 i1:$clamp, i32:$omod))))],
1438 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1439 P.NumSrcArgs, P.HasModifiers
1442 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1443 // only VOP instruction that implicitly reads VCC.
1444 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1446 SDPatternOperator node = null_frag> : VOP3_Helper <
1448 (outs P.DstRC.RegClass:$dst),
1449 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1450 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1451 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1454 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1456 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1457 i1:$clamp, i32:$omod)),
1458 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1459 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1464 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1465 string opName, list<dag> pattern> :
1467 op, (outs vrc:$vdst, SReg_64:$sdst),
1468 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1469 InputModsNoDefault:$src1_modifiers, arc:$src1,
1470 InputModsNoDefault:$src2_modifiers, arc:$src2,
1471 ClampMod:$clamp, omod:$omod),
1472 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1473 opName, opName, 1, 1
1476 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1477 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1479 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1480 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1483 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1484 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1485 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1486 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1487 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1488 i32:$src1_modifiers, P.Src1VT:$src1,
1489 i32:$src2_modifiers, P.Src2VT:$src2,
1493 //===----------------------------------------------------------------------===//
1494 // Interpolation opcodes
1495 //===----------------------------------------------------------------------===//
1497 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1498 VINTRPCommon <outs, ins, "", pattern>,
1499 SIMCInstr<opName, SISubtarget.NONE> {
1501 let isCodeGenOnly = 1;
1504 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1506 VINTRPCommon <outs, ins, asm, []>,
1508 SIMCInstr<opName, SISubtarget.SI>;
1510 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1512 VINTRPCommon <outs, ins, asm, []>,
1514 SIMCInstr<opName, SISubtarget.VI>;
1516 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1517 string disableEncoding = "", string constraints = "",
1518 list<dag> pattern = []> {
1519 let DisableEncoding = disableEncoding,
1520 Constraints = constraints in {
1521 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1523 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1525 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1529 //===----------------------------------------------------------------------===//
1530 // Vector I/O classes
1531 //===----------------------------------------------------------------------===//
1533 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1534 DS <outs, ins, "", pattern>,
1535 SIMCInstr <opName, SISubtarget.NONE> {
1537 let isCodeGenOnly = 1;
1540 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1541 DS <outs, ins, asm, []>,
1543 SIMCInstr <opName, SISubtarget.SI>;
1545 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1546 DS <outs, ins, asm, []>,
1548 SIMCInstr <opName, SISubtarget.VI>;
1550 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1551 DS_Real_si <op,opName, outs, ins, asm> {
1553 // Single load interpret the 2 i8imm operands as a single i16 offset.
1555 let offset0 = offset{7-0};
1556 let offset1 = offset{15-8};
1559 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1560 DS_Real_vi <op, opName, outs, ins, asm> {
1562 // Single load interpret the 2 i8imm operands as a single i16 offset.
1564 let offset0 = offset{7-0};
1565 let offset1 = offset{15-8};
1568 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1569 dag outs = (outs rc:$vdst),
1570 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1571 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1573 def "" : DS_Pseudo <opName, outs, ins, []>;
1575 let data0 = 0, data1 = 0 in {
1576 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1577 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1581 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1582 dag outs = (outs rc:$vdst),
1583 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1584 gds:$gds, M0Reg:$m0),
1585 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1587 def "" : DS_Pseudo <opName, outs, ins, []>;
1589 let data0 = 0, data1 = 0 in {
1590 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1591 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1595 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1597 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1599 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1601 def "" : DS_Pseudo <opName, outs, ins, []>,
1602 AtomicNoRet<opName, 0>;
1604 let data1 = 0, vdst = 0 in {
1605 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1606 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1610 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1612 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1613 ds_offset0:$offset0, ds_offset1:$offset1, gds:$gds, M0Reg:$m0),
1614 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1616 def "" : DS_Pseudo <opName, outs, ins, []>;
1619 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1620 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1624 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1625 string noRetOp = "",
1626 dag outs = (outs rc:$vdst),
1627 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1629 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1631 def "" : DS_Pseudo <opName, outs, ins, []>,
1632 AtomicNoRet<noRetOp, 1>;
1635 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1636 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1640 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1641 string noRetOp = "", dag ins,
1642 dag outs = (outs rc:$vdst),
1643 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1645 def "" : DS_Pseudo <opName, outs, ins, []>,
1646 AtomicNoRet<noRetOp, 1>;
1648 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1649 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1652 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1653 string noRetOp = "", RegisterClass src = rc> :
1654 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1655 (ins VGPR_32:$addr, src:$data0, src:$data1,
1656 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1659 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1660 string noRetOp = opName,
1662 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1663 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1664 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1666 def "" : DS_Pseudo <opName, outs, ins, []>,
1667 AtomicNoRet<noRetOp, 0>;
1670 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1671 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1675 multiclass DS_0A_RET <bits<8> op, string opName,
1676 dag outs = (outs VGPR_32:$vdst),
1677 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1678 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1680 let mayLoad = 1, mayStore = 1 in {
1681 def "" : DS_Pseudo <opName, outs, ins, []>;
1683 let addr = 0, data0 = 0, data1 = 0 in {
1684 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1685 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1686 } // end addr = 0, data0 = 0, data1 = 0
1687 } // end mayLoad = 1, mayStore = 1
1690 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1691 dag outs = (outs VGPR_32:$vdst),
1692 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1693 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1695 def "" : DS_Pseudo <opName, outs, ins, []>;
1697 let data0 = 0, data1 = 0, gds = 1 in {
1698 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1699 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1700 } // end data0 = 0, data1 = 0, gds = 1
1703 multiclass DS_1A_GDS <bits<8> op, string opName,
1705 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1706 string asm = opName#" $addr gds"> {
1708 def "" : DS_Pseudo <opName, outs, ins, []>;
1710 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1711 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1712 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1713 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1716 multiclass DS_1A <bits<8> op, string opName,
1718 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1719 string asm = opName#" $addr"#"$offset"#"$gds"> {
1721 let mayLoad = 1, mayStore = 1 in {
1722 def "" : DS_Pseudo <opName, outs, ins, []>;
1724 let vdst = 0, data0 = 0, data1 = 0 in {
1725 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1726 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1727 } // let vdst = 0, data0 = 0, data1 = 0
1728 } // end mayLoad = 1, mayStore = 1
1731 //===----------------------------------------------------------------------===//
1733 //===----------------------------------------------------------------------===//
1735 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1736 MTBUF <outs, ins, "", pattern>,
1737 SIMCInstr<opName, SISubtarget.NONE> {
1739 let isCodeGenOnly = 1;
1742 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1744 MTBUF <outs, ins, asm, []>,
1746 SIMCInstr<opName, SISubtarget.SI>;
1748 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1749 MTBUF <outs, ins, asm, []>,
1751 SIMCInstr <opName, SISubtarget.VI>;
1753 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1754 list<dag> pattern> {
1756 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1758 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1760 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1764 let mayStore = 1, mayLoad = 0 in {
1766 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1767 RegisterClass regClass> : MTBUF_m <
1769 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1770 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1771 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1772 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1773 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1776 } // mayStore = 1, mayLoad = 0
1778 let mayLoad = 1, mayStore = 0 in {
1780 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1781 RegisterClass regClass> : MTBUF_m <
1782 op, opName, (outs regClass:$dst),
1783 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1784 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1785 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1786 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1787 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1790 } // mayLoad = 1, mayStore = 0
1792 //===----------------------------------------------------------------------===//
1794 //===----------------------------------------------------------------------===//
1796 class mubuf <bits<7> si, bits<7> vi = si> {
1797 field bits<7> SI = si;
1798 field bits<7> VI = vi;
1801 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1802 bit IsAddr64 = is_addr64;
1803 string OpName = NAME # suffix;
1806 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1807 MUBUF <outs, ins, "", pattern>,
1808 SIMCInstr<opName, SISubtarget.NONE> {
1810 let isCodeGenOnly = 1;
1812 // dummy fields, so that we can use let statements around multiclasses
1822 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1824 MUBUF <outs, ins, asm, []>,
1826 SIMCInstr<opName, SISubtarget.SI> {
1830 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1832 MUBUF <outs, ins, asm, []>,
1834 SIMCInstr<opName, SISubtarget.VI> {
1838 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1839 list<dag> pattern> {
1841 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1842 MUBUFAddr64Table <0>;
1845 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1848 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1851 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1852 dag ins, string asm, list<dag> pattern> {
1854 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1855 MUBUFAddr64Table <1>;
1858 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1861 // There is no VI version. If the pseudo is selected, it should be lowered
1862 // for VI appropriately.
1865 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1866 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1870 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1871 string asm, list<dag> pattern, bit is_return> {
1873 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1874 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1875 AtomicNoRet<NAME#"_OFFSET", is_return>;
1877 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1879 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1882 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1886 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1887 string asm, list<dag> pattern, bit is_return> {
1889 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1890 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1891 AtomicNoRet<NAME#"_ADDR64", is_return>;
1893 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1894 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1897 // There is no VI version. If the pseudo is selected, it should be lowered
1898 // for VI appropriately.
1901 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1902 ValueType vt, SDPatternOperator atomic> {
1904 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1906 // No return variants
1909 defm _ADDR64 : MUBUFAtomicAddr64_m <
1910 op, name#"_addr64", (outs),
1911 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1912 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1913 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1916 defm _OFFSET : MUBUFAtomicOffset_m <
1917 op, name#"_offset", (outs),
1918 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
1920 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1924 // Variant that return values
1925 let glc = 1, Constraints = "$vdata = $vdata_in",
1926 DisableEncoding = "$vdata_in" in {
1928 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1929 op, name#"_rtn_addr64", (outs rc:$vdata),
1930 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1931 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1932 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1934 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1935 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1938 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1939 op, name#"_rtn_offset", (outs rc:$vdata),
1940 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
1941 mbuf_offset:$offset, slc:$slc),
1942 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1944 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1945 i1:$slc), vt:$vdata_in))], 1
1950 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1953 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1954 ValueType load_vt = i32,
1955 SDPatternOperator ld = null_frag> {
1957 let mayLoad = 1, mayStore = 0 in {
1958 let offen = 0, idxen = 0, vaddr = 0 in {
1959 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1960 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
1961 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1962 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1963 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1964 i32:$soffset, i16:$offset,
1965 i1:$glc, i1:$slc, i1:$tfe)))]>;
1968 let offen = 1, idxen = 0 in {
1969 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1970 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
1971 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1973 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1976 let offen = 0, idxen = 1 in {
1977 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1978 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
1979 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1980 slc:$slc, tfe:$tfe),
1981 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1984 let offen = 1, idxen = 1 in {
1985 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1986 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
1987 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1988 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1991 let offen = 0, idxen = 0 in {
1992 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1993 (ins VReg_64:$vaddr, SReg_128:$srsrc,
1994 SCSrc_32:$soffset, mbuf_offset:$offset,
1995 glc:$glc, slc:$slc, tfe:$tfe),
1996 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
1997 "$glc"#"$slc"#"$tfe",
1998 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1999 i64:$vaddr, i32:$soffset,
2000 i16:$offset, i1:$glc, i1:$slc,
2006 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2007 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2008 let mayLoad = 0, mayStore = 1 in {
2009 defm : MUBUF_m <op, name, (outs),
2010 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2011 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2013 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2014 "$glc"#"$slc"#"$tfe", []>;
2016 let offen = 0, idxen = 0, vaddr = 0 in {
2017 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2018 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2019 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2020 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2021 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2022 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2023 } // offen = 0, idxen = 0, vaddr = 0
2025 let offen = 1, idxen = 0 in {
2026 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2027 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2028 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2029 slc:$slc, tfe:$tfe),
2030 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2031 "$glc"#"$slc"#"$tfe", []>;
2032 } // end offen = 1, idxen = 0
2034 let offen = 0, idxen = 1 in {
2035 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2036 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2037 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2038 slc:$slc, tfe:$tfe),
2039 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2042 let offen = 1, idxen = 1 in {
2043 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2044 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2045 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2046 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2049 let offen = 0, idxen = 0 in {
2050 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2051 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2053 mbuf_offset:$offset, glc:$glc, slc:$slc,
2055 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2056 "$offset"#"$glc"#"$slc"#"$tfe",
2057 [(st store_vt:$vdata,
2058 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2059 i32:$soffset, i16:$offset,
2060 i1:$glc, i1:$slc, i1:$tfe))]>;
2062 } // End mayLoad = 0, mayStore = 1
2065 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2066 FLAT <op, (outs regClass:$vdst),
2067 (ins VReg_64:$addr),
2068 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2076 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2077 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2078 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2091 class MIMG_Mask <string op, int channels> {
2093 int Channels = channels;
2096 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2097 RegisterClass dst_rc,
2098 RegisterClass src_rc> : MIMG <
2100 (outs dst_rc:$vdata),
2101 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2102 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2104 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2105 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2110 let hasPostISelHook = 1;
2113 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2114 RegisterClass dst_rc,
2116 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2117 MIMG_Mask<asm#"_V1", channels>;
2118 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2119 MIMG_Mask<asm#"_V2", channels>;
2120 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2121 MIMG_Mask<asm#"_V4", channels>;
2124 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2125 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2126 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2127 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2128 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2131 class MIMG_Sampler_Helper <bits<7> op, string asm,
2132 RegisterClass dst_rc,
2133 RegisterClass src_rc, int wqm> : MIMG <
2135 (outs dst_rc:$vdata),
2136 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2137 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2138 SReg_256:$srsrc, SReg_128:$ssamp),
2139 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2140 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2144 let hasPostISelHook = 1;
2148 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2149 RegisterClass dst_rc,
2150 int channels, int wqm> {
2151 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2152 MIMG_Mask<asm#"_V1", channels>;
2153 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2154 MIMG_Mask<asm#"_V2", channels>;
2155 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2156 MIMG_Mask<asm#"_V4", channels>;
2157 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2158 MIMG_Mask<asm#"_V8", channels>;
2159 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2160 MIMG_Mask<asm#"_V16", channels>;
2163 multiclass MIMG_Sampler <bits<7> op, string asm> {
2164 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2165 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2166 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2167 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2170 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2171 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2172 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2173 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2174 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2177 class MIMG_Gather_Helper <bits<7> op, string asm,
2178 RegisterClass dst_rc,
2179 RegisterClass src_rc, int wqm> : MIMG <
2181 (outs dst_rc:$vdata),
2182 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2183 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2184 SReg_256:$srsrc, SReg_128:$ssamp),
2185 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2186 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2191 // DMASK was repurposed for GATHER4. 4 components are always
2192 // returned and DMASK works like a swizzle - it selects
2193 // the component to fetch. The only useful DMASK values are
2194 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2195 // (red,red,red,red) etc.) The ISA document doesn't mention
2197 // Therefore, disable all code which updates DMASK by setting these two:
2199 let hasPostISelHook = 0;
2203 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2204 RegisterClass dst_rc,
2205 int channels, int wqm> {
2206 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2207 MIMG_Mask<asm#"_V1", channels>;
2208 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2209 MIMG_Mask<asm#"_V2", channels>;
2210 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2211 MIMG_Mask<asm#"_V4", channels>;
2212 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2213 MIMG_Mask<asm#"_V8", channels>;
2214 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2215 MIMG_Mask<asm#"_V16", channels>;
2218 multiclass MIMG_Gather <bits<7> op, string asm> {
2219 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2220 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2221 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2222 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2225 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2226 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2227 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2228 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2229 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2232 //===----------------------------------------------------------------------===//
2233 // Vector instruction mappings
2234 //===----------------------------------------------------------------------===//
2236 // Maps an opcode in e32 form to its e64 equivalent
2237 def getVOPe64 : InstrMapping {
2238 let FilterClass = "VOP";
2239 let RowFields = ["OpName"];
2240 let ColFields = ["Size"];
2242 let ValueCols = [["8"]];
2245 // Maps an opcode in e64 form to its e32 equivalent
2246 def getVOPe32 : InstrMapping {
2247 let FilterClass = "VOP";
2248 let RowFields = ["OpName"];
2249 let ColFields = ["Size"];
2251 let ValueCols = [["4"]];
2254 def getMaskedMIMGOp : InstrMapping {
2255 let FilterClass = "MIMG_Mask";
2256 let RowFields = ["Op"];
2257 let ColFields = ["Channels"];
2259 let ValueCols = [["1"], ["2"], ["3"] ];
2262 // Maps an commuted opcode to its original version
2263 def getCommuteOrig : InstrMapping {
2264 let FilterClass = "VOP2_REV";
2265 let RowFields = ["RevOp"];
2266 let ColFields = ["IsOrig"];
2268 let ValueCols = [["1"]];
2271 // Maps an original opcode to its commuted version
2272 def getCommuteRev : InstrMapping {
2273 let FilterClass = "VOP2_REV";
2274 let RowFields = ["RevOp"];
2275 let ColFields = ["IsOrig"];
2277 let ValueCols = [["0"]];
2280 def getCommuteCmpOrig : InstrMapping {
2281 let FilterClass = "VOP2_REV";
2282 let RowFields = ["RevOp"];
2283 let ColFields = ["IsOrig"];
2285 let ValueCols = [["1"]];
2288 // Maps an original opcode to its commuted version
2289 def getCommuteCmpRev : InstrMapping {
2290 let FilterClass = "VOP2_REV";
2291 let RowFields = ["RevOp"];
2292 let ColFields = ["IsOrig"];
2294 let ValueCols = [["0"]];
2298 def getMCOpcodeGen : InstrMapping {
2299 let FilterClass = "SIMCInstr";
2300 let RowFields = ["PseudoInstr"];
2301 let ColFields = ["Subtarget"];
2302 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2303 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2306 def getAddr64Inst : InstrMapping {
2307 let FilterClass = "MUBUFAddr64Table";
2308 let RowFields = ["OpName"];
2309 let ColFields = ["IsAddr64"];
2311 let ValueCols = [["1"]];
2314 // Maps an atomic opcode to its version with a return value.
2315 def getAtomicRetOp : InstrMapping {
2316 let FilterClass = "AtomicNoRet";
2317 let RowFields = ["NoRetOp"];
2318 let ColFields = ["IsRet"];
2320 let ValueCols = [["1"]];
2323 // Maps an atomic opcode to its returnless version.
2324 def getAtomicNoRetOp : InstrMapping {
2325 let FilterClass = "AtomicNoRet";
2326 let RowFields = ["NoRetOp"];
2327 let ColFields = ["IsRet"];
2329 let ValueCols = [["0"]];
2332 include "SIInstructions.td"
2333 include "CIInstructions.td"
2334 include "VIInstructions.td"