1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/MC/MCInstrDesc.h"
28 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
29 : AMDGPUInstrInfo(st),
32 //===----------------------------------------------------------------------===//
33 // TargetInstrInfo callbacks
34 //===----------------------------------------------------------------------===//
36 static unsigned getNumOperandsNoGlue(SDNode *Node) {
37 unsigned N = Node->getNumOperands();
38 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
43 static SDValue findChainOperand(SDNode *Load) {
44 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
45 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
49 /// \brief Returns true if both nodes have the same value for the given
50 /// operand \p Op, or if both nodes do not have this operand.
51 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
52 unsigned Opc0 = N0->getMachineOpcode();
53 unsigned Opc1 = N1->getMachineOpcode();
55 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
56 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
58 if (Op0Idx == -1 && Op1Idx == -1)
62 if ((Op0Idx == -1 && Op1Idx != -1) ||
63 (Op1Idx == -1 && Op0Idx != -1))
66 // getNamedOperandIdx returns the index for the MachineInstr's operands,
67 // which includes the result as the first operand. We are indexing into the
68 // MachineSDNode's operands, so we need to skip the result operand to get
73 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
76 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
78 int64_t &Offset1) const {
79 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
82 unsigned Opc0 = Load0->getMachineOpcode();
83 unsigned Opc1 = Load1->getMachineOpcode();
85 // Make sure both are actually loads.
86 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
89 if (isDS(Opc0) && isDS(Opc1)) {
90 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
92 // TODO: Also shouldn't see read2st
93 assert(Opc0 != AMDGPU::DS_READ2_B32 &&
94 Opc0 != AMDGPU::DS_READ2_B64 &&
95 Opc1 != AMDGPU::DS_READ2_B32 &&
96 Opc1 != AMDGPU::DS_READ2_B64);
99 if (Load0->getOperand(1) != Load1->getOperand(1))
103 if (findChainOperand(Load0) != findChainOperand(Load1))
106 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
107 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
111 if (isSMRD(Opc0) && isSMRD(Opc1)) {
112 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
115 if (Load0->getOperand(0) != Load1->getOperand(0))
119 if (findChainOperand(Load0) != findChainOperand(Load1))
122 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
123 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
127 // MUBUF and MTBUF can access the same addresses.
128 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
130 // MUBUF and MTBUF have vaddr at different indices.
131 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
132 findChainOperand(Load0) != findChainOperand(Load1) ||
133 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
134 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
137 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
138 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
140 if (OffIdx0 == -1 || OffIdx1 == -1)
143 // getNamedOperandIdx returns the index for MachineInstrs. Since they
144 // inlcude the output in the operand list, but SDNodes don't, we need to
145 // subtract the index by one.
149 SDValue Off0 = Load0->getOperand(OffIdx0);
150 SDValue Off1 = Load1->getOperand(OffIdx1);
152 // The offset might be a FrameIndexSDNode.
153 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
156 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
157 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
164 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
165 unsigned &BaseReg, unsigned &Offset,
166 const TargetRegisterInfo *TRI) const {
167 unsigned Opc = LdSt->getOpcode();
169 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
170 AMDGPU::OpName::offset);
172 // Normal, single offset LDS instruction.
173 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
174 AMDGPU::OpName::addr);
176 BaseReg = AddrReg->getReg();
177 Offset = OffsetImm->getImm();
181 // The 2 offset instructions use offset0 and offset1 instead. We can treat
182 // these as a load with a single offset if the 2 offsets are consecutive. We
183 // will use this for some partially aligned loads.
184 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
185 AMDGPU::OpName::offset0);
186 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
187 AMDGPU::OpName::offset1);
189 uint8_t Offset0 = Offset0Imm->getImm();
190 uint8_t Offset1 = Offset1Imm->getImm();
191 assert(Offset1 > Offset0);
193 if (Offset1 - Offset0 == 1) {
194 // Each of these offsets is in element sized units, so we need to convert
195 // to bytes of the individual reads.
199 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
201 assert(LdSt->mayStore());
202 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
203 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
206 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
207 AMDGPU::OpName::addr);
208 BaseReg = AddrReg->getReg();
209 Offset = EltSize * Offset0;
216 if (isMUBUF(Opc) || isMTBUF(Opc)) {
217 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
220 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
221 AMDGPU::OpName::vaddr);
225 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset);
227 BaseReg = AddrReg->getReg();
228 Offset = OffsetImm->getImm();
233 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
234 AMDGPU::OpName::offset);
238 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
239 AMDGPU::OpName::sbase);
240 BaseReg = SBaseReg->getReg();
241 Offset = OffsetImm->getImm();
249 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
250 MachineBasicBlock::iterator MI, DebugLoc DL,
251 unsigned DestReg, unsigned SrcReg,
252 bool KillSrc) const {
254 // If we are trying to copy to or from SCC, there is a bug somewhere else in
255 // the backend. While it may be theoretically possible to do this, it should
256 // never be necessary.
257 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
259 static const int16_t Sub0_15[] = {
260 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
261 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
262 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
263 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
266 static const int16_t Sub0_7[] = {
267 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
268 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
271 static const int16_t Sub0_3[] = {
272 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
275 static const int16_t Sub0_2[] = {
276 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
279 static const int16_t Sub0_1[] = {
280 AMDGPU::sub0, AMDGPU::sub1, 0
284 const int16_t *SubIndices;
286 if (AMDGPU::M0 == DestReg) {
287 // Check if M0 isn't already set to this value
288 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
289 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
291 if (!I->definesRegister(AMDGPU::M0))
294 unsigned Opc = I->getOpcode();
295 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
298 if (!I->readsRegister(SrcReg))
301 // The copy isn't necessary
306 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
307 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
308 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
309 .addReg(SrcReg, getKillRegState(KillSrc));
312 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
313 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
314 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
315 .addReg(SrcReg, getKillRegState(KillSrc));
318 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
319 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
320 Opcode = AMDGPU::S_MOV_B32;
323 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
324 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
325 Opcode = AMDGPU::S_MOV_B32;
328 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
329 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
330 Opcode = AMDGPU::S_MOV_B32;
331 SubIndices = Sub0_15;
333 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
334 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
335 AMDGPU::SReg_32RegClass.contains(SrcReg));
336 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
337 .addReg(SrcReg, getKillRegState(KillSrc));
340 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
341 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
342 AMDGPU::SReg_64RegClass.contains(SrcReg));
343 Opcode = AMDGPU::V_MOV_B32_e32;
346 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
347 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
348 Opcode = AMDGPU::V_MOV_B32_e32;
351 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
352 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
353 AMDGPU::SReg_128RegClass.contains(SrcReg));
354 Opcode = AMDGPU::V_MOV_B32_e32;
357 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
358 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
359 AMDGPU::SReg_256RegClass.contains(SrcReg));
360 Opcode = AMDGPU::V_MOV_B32_e32;
363 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
364 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
365 AMDGPU::SReg_512RegClass.contains(SrcReg));
366 Opcode = AMDGPU::V_MOV_B32_e32;
367 SubIndices = Sub0_15;
370 llvm_unreachable("Can't copy register!");
373 while (unsigned SubIdx = *SubIndices++) {
374 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
375 get(Opcode), RI.getSubReg(DestReg, SubIdx));
377 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
380 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
384 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
387 // Try to map original to commuted opcode
388 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
391 // Try to map commuted to original opcode
392 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
398 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
399 MachineBasicBlock::iterator MI,
400 unsigned SrcReg, bool isKill,
402 const TargetRegisterClass *RC,
403 const TargetRegisterInfo *TRI) const {
404 MachineFunction *MF = MBB.getParent();
405 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
406 DebugLoc DL = MBB.findDebugLoc(MI);
408 if (RI.hasVGPRs(RC)) {
409 LLVMContext &Ctx = MF->getFunction()->getContext();
410 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
411 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
413 } else if (RI.isSGPRClass(RC)) {
414 // We are only allowed to create one new instruction when spilling
415 // registers, so we need to use pseudo instruction for spilling
418 switch (RC->getSize() * 8) {
419 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
420 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
421 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
422 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
423 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
424 default: llvm_unreachable("Cannot spill register class");
427 FrameInfo->setObjectAlignment(FrameIndex, 4);
428 BuildMI(MBB, MI, DL, get(Opcode))
430 .addFrameIndex(FrameIndex);
432 llvm_unreachable("VGPR spilling not supported");
436 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
437 MachineBasicBlock::iterator MI,
438 unsigned DestReg, int FrameIndex,
439 const TargetRegisterClass *RC,
440 const TargetRegisterInfo *TRI) const {
441 MachineFunction *MF = MBB.getParent();
442 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
443 DebugLoc DL = MBB.findDebugLoc(MI);
445 if (RI.hasVGPRs(RC)) {
446 LLVMContext &Ctx = MF->getFunction()->getContext();
447 Ctx.emitError("SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!");
448 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
450 } else if (RI.isSGPRClass(RC)){
452 switch(RC->getSize() * 8) {
453 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
454 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
455 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
456 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
457 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
458 default: llvm_unreachable("Cannot spill register class");
461 FrameInfo->setObjectAlignment(FrameIndex, 4);
462 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
463 .addFrameIndex(FrameIndex);
465 llvm_unreachable("VGPR spilling not supported");
469 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
478 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
483 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
484 MachineBasicBlock &MBB = *MI->getParent();
485 DebugLoc DL = MBB.findDebugLoc(MI);
486 switch (MI->getOpcode()) {
487 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
489 case AMDGPU::SI_CONSTDATA_PTR: {
490 unsigned Reg = MI->getOperand(0).getReg();
491 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
492 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
494 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
496 // Add 32-bit offset from this instruction to the start of the constant data.
497 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_I32), RegLo)
499 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
500 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
501 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
504 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
505 .addReg(AMDGPU::SCC, RegState::Implicit);
506 MI->eraseFromParent();
513 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
516 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
519 // Make sure it s legal to commute operands for VOP2.
520 if (isVOP2(MI->getOpcode()) &&
521 (!isOperandLegal(MI, 1, &MI->getOperand(2)) ||
522 !isOperandLegal(MI, 2, &MI->getOperand(1))))
525 if (!MI->getOperand(2).isReg()) {
526 // XXX: Commute instructions with FPImm operands
527 if (NewMI || MI->getOperand(2).isFPImm() ||
528 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
532 // XXX: Commute VOP3 instructions with abs and neg set .
533 const MachineOperand *Abs = getNamedOperand(*MI, AMDGPU::OpName::abs);
534 const MachineOperand *Neg = getNamedOperand(*MI, AMDGPU::OpName::neg);
535 const MachineOperand *Src0Mods = getNamedOperand(*MI,
536 AMDGPU::OpName::src0_modifiers);
537 const MachineOperand *Src1Mods = getNamedOperand(*MI,
538 AMDGPU::OpName::src1_modifiers);
539 const MachineOperand *Src2Mods = getNamedOperand(*MI,
540 AMDGPU::OpName::src2_modifiers);
542 if ((Abs && Abs->getImm()) || (Neg && Neg->getImm()) ||
543 (Src0Mods && Src0Mods->getImm()) || (Src1Mods && Src1Mods->getImm()) ||
544 (Src2Mods && Src2Mods->getImm()))
547 unsigned Reg = MI->getOperand(1).getReg();
548 unsigned SubReg = MI->getOperand(1).getSubReg();
549 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
550 MI->getOperand(2).ChangeToRegister(Reg, false);
551 MI->getOperand(2).setSubReg(SubReg);
553 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
557 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
562 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
563 MachineBasicBlock::iterator I,
565 unsigned SrcReg) const {
566 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
567 DstReg) .addReg(SrcReg);
570 bool SIInstrInfo::isMov(unsigned Opcode) const {
572 default: return false;
573 case AMDGPU::S_MOV_B32:
574 case AMDGPU::S_MOV_B64:
575 case AMDGPU::V_MOV_B32_e32:
576 case AMDGPU::V_MOV_B32_e64:
582 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
583 return RC != &AMDGPU::EXECRegRegClass;
587 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
588 AliasAnalysis *AA) const {
589 switch(MI->getOpcode()) {
590 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
591 case AMDGPU::S_MOV_B32:
592 case AMDGPU::S_MOV_B64:
593 case AMDGPU::V_MOV_B32_e32:
594 return MI->getOperand(1).isImm();
600 // Helper function generated by tablegen. We are wrapping this with
601 // an SIInstrInfo function that returns bool rather than int.
602 int isDS(uint16_t Opcode);
606 bool SIInstrInfo::isDS(uint16_t Opcode) const {
607 return ::AMDGPU::isDS(Opcode) != -1;
610 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
611 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
614 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
615 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
618 bool SIInstrInfo::isMUBUF(uint16_t Opcode) const {
619 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
622 bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
623 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
626 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
627 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
630 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
631 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
634 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
635 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
638 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
639 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
642 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
643 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
646 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
647 int32_t Val = Imm.getSExtValue();
648 if (Val >= -16 && Val <= 64)
651 // The actual type of the operand does not seem to matter as long
652 // as the bits match one of the inline immediate values. For example:
654 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
655 // so it is a legal inline immediate.
657 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
658 // floating-point, so it is a legal inline immediate.
660 return (APInt::floatToBits(0.0f) == Imm) ||
661 (APInt::floatToBits(1.0f) == Imm) ||
662 (APInt::floatToBits(-1.0f) == Imm) ||
663 (APInt::floatToBits(0.5f) == Imm) ||
664 (APInt::floatToBits(-0.5f) == Imm) ||
665 (APInt::floatToBits(2.0f) == Imm) ||
666 (APInt::floatToBits(-2.0f) == Imm) ||
667 (APInt::floatToBits(4.0f) == Imm) ||
668 (APInt::floatToBits(-4.0f) == Imm);
671 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
673 return isInlineConstant(APInt(32, MO.getImm(), true));
676 APFloat FpImm = MO.getFPImm()->getValueAPF();
677 return isInlineConstant(FpImm.bitcastToAPInt());
683 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
684 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
687 static bool compareMachineOp(const MachineOperand &Op0,
688 const MachineOperand &Op1) {
689 if (Op0.getType() != Op1.getType())
692 switch (Op0.getType()) {
693 case MachineOperand::MO_Register:
694 return Op0.getReg() == Op1.getReg();
695 case MachineOperand::MO_Immediate:
696 return Op0.getImm() == Op1.getImm();
697 case MachineOperand::MO_FPImmediate:
698 return Op0.getFPImm() == Op1.getFPImm();
700 llvm_unreachable("Didn't expect to be comparing these operand types");
704 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
705 const MachineOperand &MO) const {
706 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
708 assert(MO.isImm() || MO.isFPImm());
710 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
713 if (OpInfo.RegClass < 0)
716 return RI.regClassCanUseImmediate(OpInfo.RegClass);
719 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) {
721 case AMDGPUAS::GLOBAL_ADDRESS: {
722 // MUBUF instructions a 12-bit offset in bytes.
723 return isUInt<12>(OffsetSize);
725 case AMDGPUAS::CONSTANT_ADDRESS: {
726 // SMRD instructions have an 8-bit offset in dwords.
727 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
729 case AMDGPUAS::LOCAL_ADDRESS:
730 case AMDGPUAS::REGION_ADDRESS: {
731 // The single offset versions have a 16-bit offset in bytes.
732 return isUInt<16>(OffsetSize);
734 case AMDGPUAS::PRIVATE_ADDRESS:
735 // Indirect register addressing does not use any offsets.
741 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
742 return AMDGPU::getVOPe32(Opcode) != -1;
745 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
746 // The src0_modifier operand is present on all instructions
747 // that have modifiers.
749 return AMDGPU::getNamedOperandIdx(Opcode,
750 AMDGPU::OpName::src0_modifiers) != -1;
753 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
754 StringRef &ErrInfo) const {
755 uint16_t Opcode = MI->getOpcode();
756 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
757 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
758 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
760 // Make sure the number of operands is correct.
761 const MCInstrDesc &Desc = get(Opcode);
762 if (!Desc.isVariadic() &&
763 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
764 ErrInfo = "Instruction has wrong number of operands.";
768 // Make sure the register classes are correct
769 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
770 switch (Desc.OpInfo[i].OperandType) {
771 case MCOI::OPERAND_REGISTER: {
772 int RegClass = Desc.OpInfo[i].RegClass;
773 if (!RI.regClassCanUseImmediate(RegClass) &&
774 (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
775 // Handle some special cases:
776 // Src0 can of VOP1, VOP2, VOPC can be an immediate no matter what
777 // the register class.
778 if (i != Src0Idx || (!isVOP1(Opcode) && !isVOP2(Opcode) &&
780 ErrInfo = "Expected register, but got immediate";
786 case MCOI::OPERAND_IMMEDIATE:
787 // Check if this operand is an immediate.
788 // FrameIndex operands will be replaced by immediates, so they are
790 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
791 !MI->getOperand(i).isFI()) {
792 ErrInfo = "Expected immediate, but got non-immediate";
800 if (!MI->getOperand(i).isReg())
803 int RegClass = Desc.OpInfo[i].RegClass;
804 if (RegClass != -1) {
805 unsigned Reg = MI->getOperand(i).getReg();
806 if (TargetRegisterInfo::isVirtualRegister(Reg))
809 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
810 if (!RC->contains(Reg)) {
811 ErrInfo = "Operand has incorrect register class.";
819 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
820 unsigned ConstantBusCount = 0;
821 unsigned SGPRUsed = AMDGPU::NoRegister;
822 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
823 const MachineOperand &MO = MI->getOperand(i);
824 if (MO.isReg() && MO.isUse() &&
825 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
827 // EXEC register uses the constant bus.
828 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
831 // SGPRs use the constant bus
832 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
834 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
835 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
836 if (SGPRUsed != MO.getReg()) {
838 SGPRUsed = MO.getReg();
842 // Literal constants use the constant bus.
843 if (isLiteralConstant(MO))
846 if (ConstantBusCount > 1) {
847 ErrInfo = "VOP* instruction uses the constant bus more than once";
852 // Verify SRC1 for VOP2 and VOPC
853 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
854 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
855 if (Src1.isImm() || Src1.isFPImm()) {
856 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
862 if (isVOP3(Opcode)) {
863 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
864 ErrInfo = "VOP3 src0 cannot be a literal constant.";
867 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
868 ErrInfo = "VOP3 src1 cannot be a literal constant.";
871 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
872 ErrInfo = "VOP3 src2 cannot be a literal constant.";
877 // Verify misc. restrictions on specific instructions.
878 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
879 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
882 const MachineOperand &Src0 = MI->getOperand(2);
883 const MachineOperand &Src1 = MI->getOperand(3);
884 const MachineOperand &Src2 = MI->getOperand(4);
885 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
886 if (!compareMachineOp(Src0, Src1) &&
887 !compareMachineOp(Src0, Src2)) {
888 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
897 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
898 switch (MI.getOpcode()) {
899 default: return AMDGPU::INSTRUCTION_LIST_END;
900 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
901 case AMDGPU::COPY: return AMDGPU::COPY;
902 case AMDGPU::PHI: return AMDGPU::PHI;
903 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
904 case AMDGPU::S_MOV_B32:
905 return MI.getOperand(1).isReg() ?
906 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
907 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
908 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
909 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
910 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
911 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
912 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
913 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
914 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
915 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
916 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
917 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
918 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
919 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
920 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
921 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
922 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
923 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
924 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
925 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
926 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
927 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
928 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
929 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
930 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
931 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
932 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
933 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
934 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
935 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
936 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
937 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
938 case AMDGPU::S_LOAD_DWORD_IMM:
939 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
940 case AMDGPU::S_LOAD_DWORDX2_IMM:
941 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
942 case AMDGPU::S_LOAD_DWORDX4_IMM:
943 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
944 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
945 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
946 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
950 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
951 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
954 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
955 unsigned OpNo) const {
956 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
957 const MCInstrDesc &Desc = get(MI.getOpcode());
958 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
959 Desc.OpInfo[OpNo].RegClass == -1)
960 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
962 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
963 return RI.getRegClass(RCID);
966 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
967 switch (MI.getOpcode()) {
969 case AMDGPU::REG_SEQUENCE:
971 case AMDGPU::INSERT_SUBREG:
972 return RI.hasVGPRs(getOpRegClass(MI, 0));
974 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
978 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
979 MachineBasicBlock::iterator I = MI;
980 MachineOperand &MO = MI->getOperand(OpIdx);
981 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
982 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
983 const TargetRegisterClass *RC = RI.getRegClass(RCID);
984 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
987 Opcode = AMDGPU::COPY;
988 } else if (RI.isSGPRClass(RC)) {
989 Opcode = AMDGPU::S_MOV_B32;
990 } else if (MO.isImm()) {
991 if (RC == &AMDGPU::VSrc_32RegClass)
992 Opcode = AMDGPU::S_MOV_B32;
995 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
996 unsigned Reg = MRI.createVirtualRegister(VRC);
997 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
999 MO.ChangeToRegister(Reg, false);
1002 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1003 MachineRegisterInfo &MRI,
1004 MachineOperand &SuperReg,
1005 const TargetRegisterClass *SuperRC,
1007 const TargetRegisterClass *SubRC)
1009 assert(SuperReg.isReg());
1011 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1012 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1014 // Just in case the super register is itself a sub-register, copy it to a new
1015 // value so we don't need to worry about merging its subreg index with the
1016 // SubIdx passed to this function. The register coalescer should be able to
1017 // eliminate this extra copy.
1018 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1020 .addOperand(SuperReg);
1022 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1024 .addReg(NewSuperReg, 0, SubIdx);
1028 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1029 MachineBasicBlock::iterator MII,
1030 MachineRegisterInfo &MRI,
1032 const TargetRegisterClass *SuperRC,
1034 const TargetRegisterClass *SubRC) const {
1036 // XXX - Is there a better way to do this?
1037 if (SubIdx == AMDGPU::sub0)
1038 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1039 if (SubIdx == AMDGPU::sub1)
1040 return MachineOperand::CreateImm(Op.getImm() >> 32);
1042 llvm_unreachable("Unhandled register index for immediate");
1045 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1047 return MachineOperand::CreateReg(SubReg, false);
1050 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1051 MachineBasicBlock::iterator MI,
1052 MachineRegisterInfo &MRI,
1053 const TargetRegisterClass *RC,
1054 const MachineOperand &Op) const {
1055 MachineBasicBlock *MBB = MI->getParent();
1056 DebugLoc DL = MI->getDebugLoc();
1057 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1058 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1059 unsigned Dst = MRI.createVirtualRegister(RC);
1061 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1063 .addImm(Op.getImm() & 0xFFFFFFFF);
1064 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1066 .addImm(Op.getImm() >> 32);
1068 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1070 .addImm(AMDGPU::sub0)
1072 .addImm(AMDGPU::sub1);
1074 Worklist.push_back(Lo);
1075 Worklist.push_back(Hi);
1080 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1081 const MachineOperand *MO) const {
1082 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1083 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1084 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1085 const TargetRegisterClass *DefinedRC =
1086 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1088 MO = &MI->getOperand(OpIdx);
1092 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1093 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass));
1097 // Handle non-register types that are treated like immediates.
1098 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1101 // This opperand expects an immediate
1104 return RI.regClassCanUseImmediate(DefinedRC);
1107 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1108 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1110 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1111 AMDGPU::OpName::src0);
1112 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1113 AMDGPU::OpName::src1);
1114 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1115 AMDGPU::OpName::src2);
1118 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1120 if (!isOperandLegal(MI, Src0Idx))
1121 legalizeOpWithMove(MI, Src0Idx);
1124 if (isOperandLegal(MI, Src1Idx))
1127 // Usually src0 of VOP2 instructions allow more types of inputs
1128 // than src1, so try to commute the instruction to decrease our
1129 // chances of having to insert a MOV instruction to legalize src1.
1130 if (MI->isCommutable()) {
1131 if (commuteInstruction(MI))
1132 // If we are successful in commuting, then we know MI is legal, so
1137 legalizeOpWithMove(MI, Src1Idx);
1141 // XXX - Do any VOP3 instructions read VCC?
1143 if (isVOP3(MI->getOpcode())) {
1144 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
1145 unsigned SGPRReg = AMDGPU::NoRegister;
1146 for (unsigned i = 0; i < 3; ++i) {
1147 int Idx = VOP3Idx[i];
1150 MachineOperand &MO = MI->getOperand(Idx);
1153 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1154 continue; // VGPRs are legal
1156 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1158 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1159 SGPRReg = MO.getReg();
1160 // We can use one SGPR in each VOP3 instruction.
1163 } else if (!isLiteralConstant(MO)) {
1164 // If it is not a register and not a literal constant, then it must be
1165 // an inline constant which is always legal.
1168 // If we make it this far, then the operand is not legal and we must
1170 legalizeOpWithMove(MI, Idx);
1174 // Legalize REG_SEQUENCE and PHI
1175 // The register class of the operands much be the same type as the register
1176 // class of the output.
1177 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1178 MI->getOpcode() == AMDGPU::PHI) {
1179 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1180 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1181 if (!MI->getOperand(i).isReg() ||
1182 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1184 const TargetRegisterClass *OpRC =
1185 MRI.getRegClass(MI->getOperand(i).getReg());
1186 if (RI.hasVGPRs(OpRC)) {
1193 // If any of the operands are VGPR registers, then they all most be
1194 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1196 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1199 VRC = RI.getEquivalentVGPRClass(SRC);
1206 // Update all the operands so they have the same type.
1207 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1208 if (!MI->getOperand(i).isReg() ||
1209 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1211 unsigned DstReg = MRI.createVirtualRegister(RC);
1212 MachineBasicBlock *InsertBB;
1213 MachineBasicBlock::iterator Insert;
1214 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1215 InsertBB = MI->getParent();
1218 // MI is a PHI instruction.
1219 InsertBB = MI->getOperand(i + 1).getMBB();
1220 Insert = InsertBB->getFirstTerminator();
1222 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1223 get(AMDGPU::COPY), DstReg)
1224 .addOperand(MI->getOperand(i));
1225 MI->getOperand(i).setReg(DstReg);
1229 // Legalize INSERT_SUBREG
1230 // src0 must have the same register class as dst
1231 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1232 unsigned Dst = MI->getOperand(0).getReg();
1233 unsigned Src0 = MI->getOperand(1).getReg();
1234 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1235 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1236 if (DstRC != Src0RC) {
1237 MachineBasicBlock &MBB = *MI->getParent();
1238 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1239 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1241 MI->getOperand(1).setReg(NewSrc0);
1246 // Legalize MUBUF* instructions
1247 // FIXME: If we start using the non-addr64 instructions for compute, we
1248 // may need to legalize them here.
1250 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1251 if (SRsrcIdx != -1) {
1252 // We have an MUBUF instruction
1253 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1254 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1255 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1256 RI.getRegClass(SRsrcRC))) {
1257 // The operands are legal.
1258 // FIXME: We may need to legalize operands besided srsrc.
1262 MachineBasicBlock &MBB = *MI->getParent();
1263 // Extract the the ptr from the resource descriptor.
1265 // SRsrcPtrLo = srsrc:sub0
1266 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1267 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1269 // SRsrcPtrHi = srsrc:sub1
1270 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1271 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1273 // Create an empty resource descriptor
1274 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1275 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1276 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1277 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1280 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1284 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1285 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1287 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1289 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1290 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1292 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1294 // NewSRsrc = {Zero64, SRsrcFormat}
1295 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1298 .addImm(AMDGPU::sub0_sub1)
1299 .addReg(SRsrcFormatLo)
1300 .addImm(AMDGPU::sub2)
1301 .addReg(SRsrcFormatHi)
1302 .addImm(AMDGPU::sub3);
1304 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1305 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1306 unsigned NewVAddrLo;
1307 unsigned NewVAddrHi;
1309 // This is already an ADDR64 instruction so we need to add the pointer
1310 // extracted from the resource descriptor to the current value of VAddr.
1311 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1312 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1314 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1315 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1318 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1319 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1321 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1322 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1325 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1326 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1327 .addReg(AMDGPU::VCC, RegState::Implicit);
1330 // This instructions is the _OFFSET variant, so we need to convert it to
1332 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1333 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1334 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1335 assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
1336 "with non-zero soffset is not implemented");
1339 // Create the new instruction.
1340 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1341 MachineInstr *Addr64 =
1342 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1345 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1346 // This will be replaced later
1347 // with the new value of vaddr.
1348 .addOperand(*Offset);
1350 MI->removeFromParent();
1353 NewVAddrLo = SRsrcPtrLo;
1354 NewVAddrHi = SRsrcPtrHi;
1355 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1356 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1359 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1360 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1363 .addImm(AMDGPU::sub0)
1365 .addImm(AMDGPU::sub1);
1368 // Update the instruction to use NewVaddr
1369 VAddr->setReg(NewVAddr);
1370 // Update the instruction to use NewSRsrc
1371 SRsrc->setReg(NewSRsrc);
1375 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1376 const TargetRegisterClass *HalfRC,
1377 unsigned HalfImmOp, unsigned HalfSGPROp,
1378 MachineInstr *&Lo, MachineInstr *&Hi) const {
1380 DebugLoc DL = MI->getDebugLoc();
1381 MachineBasicBlock *MBB = MI->getParent();
1382 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1383 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1384 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1385 unsigned HalfSize = HalfRC->getSize();
1386 const MachineOperand *OffOp =
1387 getNamedOperand(*MI, AMDGPU::OpName::offset);
1388 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1391 // Handle the _IMM variant
1392 unsigned LoOffset = OffOp->getImm();
1393 unsigned HiOffset = LoOffset + (HalfSize / 4);
1394 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1398 if (!isUInt<8>(HiOffset)) {
1399 unsigned OffsetSGPR =
1400 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1401 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1402 .addImm(HiOffset << 2); // The immediate offset is in dwords,
1403 // but offset in register is in bytes.
1404 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1406 .addReg(OffsetSGPR);
1408 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1413 // Handle the _SGPR variant
1414 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1415 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1418 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1419 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1422 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1424 .addReg(OffsetSGPR);
1427 unsigned SubLo, SubHi;
1430 SubLo = AMDGPU::sub0;
1431 SubHi = AMDGPU::sub1;
1434 SubLo = AMDGPU::sub0_sub1;
1435 SubHi = AMDGPU::sub2_sub3;
1438 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1439 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1442 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1443 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1446 llvm_unreachable("Unhandled HalfSize");
1449 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1450 .addOperand(MI->getOperand(0))
1457 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1458 MachineBasicBlock *MBB = MI->getParent();
1459 switch (MI->getOpcode()) {
1460 case AMDGPU::S_LOAD_DWORD_IMM:
1461 case AMDGPU::S_LOAD_DWORD_SGPR:
1462 case AMDGPU::S_LOAD_DWORDX2_IMM:
1463 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1464 case AMDGPU::S_LOAD_DWORDX4_IMM:
1465 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1466 unsigned NewOpcode = getVALUOp(*MI);
1470 if (MI->getOperand(2).isReg()) {
1471 RegOffset = MI->getOperand(2).getReg();
1474 assert(MI->getOperand(2).isImm());
1475 // SMRD instructions take a dword offsets and MUBUF instructions
1476 // take a byte offset.
1477 ImmOffset = MI->getOperand(2).getImm() << 2;
1478 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1479 if (isUInt<12>(ImmOffset)) {
1480 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1484 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1491 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1492 unsigned DWord0 = RegOffset;
1493 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1494 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1495 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1497 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1499 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1500 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1501 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1502 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1503 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1505 .addImm(AMDGPU::sub0)
1507 .addImm(AMDGPU::sub1)
1509 .addImm(AMDGPU::sub2)
1511 .addImm(AMDGPU::sub3);
1512 MI->setDesc(get(NewOpcode));
1513 if (MI->getOperand(2).isReg()) {
1514 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1516 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1518 MI->getOperand(1).setReg(SRsrc);
1519 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1521 const TargetRegisterClass *NewDstRC =
1522 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1524 unsigned DstReg = MI->getOperand(0).getReg();
1525 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1526 MRI.replaceRegWith(DstReg, NewDstReg);
1529 case AMDGPU::S_LOAD_DWORDX8_IMM:
1530 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1531 MachineInstr *Lo, *Hi;
1532 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1533 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1534 MI->eraseFromParent();
1535 moveSMRDToVALU(Lo, MRI);
1536 moveSMRDToVALU(Hi, MRI);
1540 case AMDGPU::S_LOAD_DWORDX16_IMM:
1541 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1542 MachineInstr *Lo, *Hi;
1543 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1544 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1545 MI->eraseFromParent();
1546 moveSMRDToVALU(Lo, MRI);
1547 moveSMRDToVALU(Hi, MRI);
1553 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1554 SmallVector<MachineInstr *, 128> Worklist;
1555 Worklist.push_back(&TopInst);
1557 while (!Worklist.empty()) {
1558 MachineInstr *Inst = Worklist.pop_back_val();
1559 MachineBasicBlock *MBB = Inst->getParent();
1560 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1562 unsigned Opcode = Inst->getOpcode();
1563 unsigned NewOpcode = getVALUOp(*Inst);
1565 // Handle some special cases
1568 if (isSMRD(Inst->getOpcode())) {
1569 moveSMRDToVALU(Inst, MRI);
1572 case AMDGPU::S_MOV_B64: {
1573 DebugLoc DL = Inst->getDebugLoc();
1575 // If the source operand is a register we can replace this with a
1577 if (Inst->getOperand(1).isReg()) {
1578 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1579 .addOperand(Inst->getOperand(0))
1580 .addOperand(Inst->getOperand(1));
1581 Worklist.push_back(Copy);
1583 // Otherwise, we need to split this into two movs, because there is
1584 // no 64-bit VALU move instruction.
1585 unsigned Reg = Inst->getOperand(0).getReg();
1586 unsigned Dst = split64BitImm(Worklist,
1589 MRI.getRegClass(Reg),
1590 Inst->getOperand(1));
1591 MRI.replaceRegWith(Reg, Dst);
1593 Inst->eraseFromParent();
1596 case AMDGPU::S_AND_B64:
1597 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1598 Inst->eraseFromParent();
1601 case AMDGPU::S_OR_B64:
1602 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1603 Inst->eraseFromParent();
1606 case AMDGPU::S_XOR_B64:
1607 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1608 Inst->eraseFromParent();
1611 case AMDGPU::S_NOT_B64:
1612 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1613 Inst->eraseFromParent();
1616 case AMDGPU::S_BCNT1_I32_B64:
1617 splitScalar64BitBCNT(Worklist, Inst);
1618 Inst->eraseFromParent();
1621 case AMDGPU::S_BFE_U64:
1622 case AMDGPU::S_BFE_I64:
1623 case AMDGPU::S_BFM_B64:
1624 llvm_unreachable("Moving this op to VALU not implemented");
1627 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1628 // We cannot move this instruction to the VALU, so we should try to
1629 // legalize its operands instead.
1630 legalizeOperands(Inst);
1634 // Use the new VALU Opcode.
1635 const MCInstrDesc &NewDesc = get(NewOpcode);
1636 Inst->setDesc(NewDesc);
1638 // Remove any references to SCC. Vector instructions can't read from it, and
1639 // We're just about to add the implicit use / defs of VCC, and we don't want
1641 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1642 MachineOperand &Op = Inst->getOperand(i);
1643 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1644 Inst->RemoveOperand(i);
1647 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1648 // We are converting these to a BFE, so we need to add the missing
1649 // operands for the size and offset.
1650 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1651 Inst->addOperand(MachineOperand::CreateImm(0));
1652 Inst->addOperand(MachineOperand::CreateImm(Size));
1654 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1655 // The VALU version adds the second operand to the result, so insert an
1657 Inst->addOperand(MachineOperand::CreateImm(0));
1660 addDescImplicitUseDef(NewDesc, Inst);
1662 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1663 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1664 // If we need to move this to VGPRs, we need to unpack the second operand
1665 // back into the 2 separate ones for bit offset and width.
1666 assert(OffsetWidthOp.isImm() &&
1667 "Scalar BFE is only implemented for constant width and offset");
1668 uint32_t Imm = OffsetWidthOp.getImm();
1670 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1671 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1672 Inst->RemoveOperand(2); // Remove old immediate.
1673 Inst->addOperand(MachineOperand::CreateImm(Offset));
1674 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1677 // Update the destination register class.
1679 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1682 // For target instructions, getOpRegClass just returns the virtual
1683 // register class associated with the operand, so we need to find an
1684 // equivalent VGPR register class in order to move the instruction to the
1688 case AMDGPU::REG_SEQUENCE:
1689 case AMDGPU::INSERT_SUBREG:
1690 if (RI.hasVGPRs(NewDstRC))
1692 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1700 unsigned DstReg = Inst->getOperand(0).getReg();
1701 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1702 MRI.replaceRegWith(DstReg, NewDstReg);
1704 // Legalize the operands
1705 legalizeOperands(Inst);
1707 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1708 E = MRI.use_end(); I != E; ++I) {
1709 MachineInstr &UseMI = *I->getParent();
1710 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1711 Worklist.push_back(&UseMI);
1717 //===----------------------------------------------------------------------===//
1718 // Indirect addressing callbacks
1719 //===----------------------------------------------------------------------===//
1721 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1722 unsigned Channel) const {
1723 assert(Channel == 0);
1727 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1728 return &AMDGPU::VReg_32RegClass;
1731 void SIInstrInfo::splitScalar64BitUnaryOp(
1732 SmallVectorImpl<MachineInstr *> &Worklist,
1734 unsigned Opcode) const {
1735 MachineBasicBlock &MBB = *Inst->getParent();
1736 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1738 MachineOperand &Dest = Inst->getOperand(0);
1739 MachineOperand &Src0 = Inst->getOperand(1);
1740 DebugLoc DL = Inst->getDebugLoc();
1742 MachineBasicBlock::iterator MII = Inst;
1744 const MCInstrDesc &InstDesc = get(Opcode);
1745 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1746 MRI.getRegClass(Src0.getReg()) :
1747 &AMDGPU::SGPR_32RegClass;
1749 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1751 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1752 AMDGPU::sub0, Src0SubRC);
1754 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1755 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1757 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1758 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1759 .addOperand(SrcReg0Sub0);
1761 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1762 AMDGPU::sub1, Src0SubRC);
1764 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1765 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1766 .addOperand(SrcReg0Sub1);
1768 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1769 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1771 .addImm(AMDGPU::sub0)
1773 .addImm(AMDGPU::sub1);
1775 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1777 // Try to legalize the operands in case we need to swap the order to keep it
1779 Worklist.push_back(LoHalf);
1780 Worklist.push_back(HiHalf);
1783 void SIInstrInfo::splitScalar64BitBinaryOp(
1784 SmallVectorImpl<MachineInstr *> &Worklist,
1786 unsigned Opcode) const {
1787 MachineBasicBlock &MBB = *Inst->getParent();
1788 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1790 MachineOperand &Dest = Inst->getOperand(0);
1791 MachineOperand &Src0 = Inst->getOperand(1);
1792 MachineOperand &Src1 = Inst->getOperand(2);
1793 DebugLoc DL = Inst->getDebugLoc();
1795 MachineBasicBlock::iterator MII = Inst;
1797 const MCInstrDesc &InstDesc = get(Opcode);
1798 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1799 MRI.getRegClass(Src0.getReg()) :
1800 &AMDGPU::SGPR_32RegClass;
1802 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1803 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1804 MRI.getRegClass(Src1.getReg()) :
1805 &AMDGPU::SGPR_32RegClass;
1807 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1809 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1810 AMDGPU::sub0, Src0SubRC);
1811 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1812 AMDGPU::sub0, Src1SubRC);
1814 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1815 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1817 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1818 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1819 .addOperand(SrcReg0Sub0)
1820 .addOperand(SrcReg1Sub0);
1822 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1823 AMDGPU::sub1, Src0SubRC);
1824 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1825 AMDGPU::sub1, Src1SubRC);
1827 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1828 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1829 .addOperand(SrcReg0Sub1)
1830 .addOperand(SrcReg1Sub1);
1832 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1833 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1835 .addImm(AMDGPU::sub0)
1837 .addImm(AMDGPU::sub1);
1839 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1841 // Try to legalize the operands in case we need to swap the order to keep it
1843 Worklist.push_back(LoHalf);
1844 Worklist.push_back(HiHalf);
1847 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
1848 MachineInstr *Inst) const {
1849 MachineBasicBlock &MBB = *Inst->getParent();
1850 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1852 MachineBasicBlock::iterator MII = Inst;
1853 DebugLoc DL = Inst->getDebugLoc();
1855 MachineOperand &Dest = Inst->getOperand(0);
1856 MachineOperand &Src = Inst->getOperand(1);
1858 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
1859 const TargetRegisterClass *SrcRC = Src.isReg() ?
1860 MRI.getRegClass(Src.getReg()) :
1861 &AMDGPU::SGPR_32RegClass;
1863 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1864 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1866 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
1868 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1869 AMDGPU::sub0, SrcSubRC);
1870 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1871 AMDGPU::sub1, SrcSubRC);
1873 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
1874 .addOperand(SrcRegSub0)
1877 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
1878 .addOperand(SrcRegSub1)
1881 MRI.replaceRegWith(Dest.getReg(), ResultReg);
1883 Worklist.push_back(First);
1884 Worklist.push_back(Second);
1887 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1888 MachineInstr *Inst) const {
1889 // Add the implict and explicit register definitions.
1890 if (NewDesc.ImplicitUses) {
1891 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
1892 unsigned Reg = NewDesc.ImplicitUses[i];
1893 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
1897 if (NewDesc.ImplicitDefs) {
1898 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1899 unsigned Reg = NewDesc.ImplicitDefs[i];
1900 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
1905 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1906 MachineBasicBlock *MBB,
1907 MachineBasicBlock::iterator I,
1909 unsigned Address, unsigned OffsetReg) const {
1910 const DebugLoc &DL = MBB->findDebugLoc(I);
1911 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1912 getIndirectIndexBegin(*MBB->getParent()));
1914 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1915 .addReg(IndirectBaseReg, RegState::Define)
1916 .addOperand(I->getOperand(0))
1917 .addReg(IndirectBaseReg)
1923 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1924 MachineBasicBlock *MBB,
1925 MachineBasicBlock::iterator I,
1927 unsigned Address, unsigned OffsetReg) const {
1928 const DebugLoc &DL = MBB->findDebugLoc(I);
1929 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1930 getIndirectIndexBegin(*MBB->getParent()));
1932 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1933 .addOperand(I->getOperand(0))
1934 .addOperand(I->getOperand(1))
1935 .addReg(IndirectBaseReg)
1941 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1942 const MachineFunction &MF) const {
1943 int End = getIndirectIndexEnd(MF);
1944 int Begin = getIndirectIndexBegin(MF);
1950 for (int Index = Begin; Index <= End; ++Index)
1951 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1953 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1954 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1956 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1957 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1959 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1960 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1962 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1963 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1965 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1966 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
1969 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
1970 unsigned OperandName) const {
1971 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
1975 return &MI.getOperand(Idx);