1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "AMDGPUFrameLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/IR/Argument.h"
29 #include "llvm/IR/Function.h"
33 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
34 AMDGPUTargetLowering(TM),
35 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
43 computeRegisterProperties();
45 // Set condition code actions
46 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
64 setOperationAction(ISD::FCOS, MVT::f32, Custom);
65 setOperationAction(ISD::FSIN, MVT::f32, Custom);
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
70 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
71 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
72 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
74 setOperationAction(ISD::FSUB, MVT::f32, Expand);
76 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
77 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
78 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
83 setOperationAction(ISD::SETCC, MVT::i32, Expand);
84 setOperationAction(ISD::SETCC, MVT::f32, Expand);
85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f32, Expand);
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
94 // Expand sign extension of vectors
95 if (!Subtarget->hasBFE())
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
101 if (!Subtarget->hasBFE())
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
106 if (!Subtarget->hasBFE())
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
118 // Legalize loads and stores to the private address space.
119 setOperationAction(ISD::LOAD, MVT::i32, Custom);
120 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
121 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
123 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
124 // spaces, so it is custom lowered to handle those where it isn't.
125 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
126 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
127 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
128 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
129 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
130 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
132 setOperationAction(ISD::STORE, MVT::i8, Custom);
133 setOperationAction(ISD::STORE, MVT::i32, Custom);
134 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
135 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
136 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
137 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
139 setOperationAction(ISD::LOAD, MVT::i32, Custom);
140 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
141 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
144 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
145 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
146 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
148 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
149 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
150 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
151 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
153 setTargetDAGCombine(ISD::FP_ROUND);
154 setTargetDAGCombine(ISD::FP_TO_SINT);
155 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
156 setTargetDAGCombine(ISD::SELECT_CC);
157 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
159 setOperationAction(ISD::SUB, MVT::i64, Expand);
161 // These should be replaced by UDVIREM, but it does not happen automatically
162 // during Type Legalization
163 setOperationAction(ISD::UDIV, MVT::i64, Custom);
164 setOperationAction(ISD::UREM, MVT::i64, Custom);
165 setOperationAction(ISD::SDIV, MVT::i64, Custom);
166 setOperationAction(ISD::SREM, MVT::i64, Custom);
168 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
169 // to be Legal/Custom in order to avoid library calls.
170 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
171 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
172 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
174 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
176 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
177 for (MVT VT : ScalarIntVTs) {
178 setOperationAction(ISD::ADDC, VT, Expand);
179 setOperationAction(ISD::SUBC, VT, Expand);
180 setOperationAction(ISD::ADDE, VT, Expand);
181 setOperationAction(ISD::SUBE, VT, Expand);
184 setBooleanContents(ZeroOrNegativeOneBooleanContent);
185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
186 setSchedulingPreference(Sched::Source);
189 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
190 MachineInstr * MI, MachineBasicBlock * BB) const {
191 MachineFunction * MF = BB->getParent();
192 MachineRegisterInfo &MRI = MF->getRegInfo();
193 MachineBasicBlock::iterator I = *MI;
194 const R600InstrInfo *TII =
195 static_cast<const R600InstrInfo *>(MF->getSubtarget().getInstrInfo());
197 switch (MI->getOpcode()) {
199 // Replace LDS_*_RET instruction that don't have any uses with the
200 // equivalent LDS_*_NORET instruction.
201 if (TII->isLDSRetInstr(MI->getOpcode())) {
202 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
203 assert(DstIdx != -1);
204 MachineInstrBuilder NewMI;
205 // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
206 // LDS_1A2D support and remove this special case.
207 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) ||
208 MI->getOpcode() == AMDGPU::LDS_CMPST_RET)
211 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
212 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
213 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
214 NewMI.addOperand(MI->getOperand(i));
217 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
220 case AMDGPU::CLAMP_R600: {
221 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
223 MI->getOperand(0).getReg(),
224 MI->getOperand(1).getReg());
225 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
229 case AMDGPU::FABS_R600: {
230 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
232 MI->getOperand(0).getReg(),
233 MI->getOperand(1).getReg());
234 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
238 case AMDGPU::FNEG_R600: {
239 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
241 MI->getOperand(0).getReg(),
242 MI->getOperand(1).getReg());
243 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
247 case AMDGPU::MASK_WRITE: {
248 unsigned maskedRegister = MI->getOperand(0).getReg();
249 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
250 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
251 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
255 case AMDGPU::MOV_IMM_F32:
256 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
257 MI->getOperand(1).getFPImm()->getValueAPF()
258 .bitcastToAPInt().getZExtValue());
260 case AMDGPU::MOV_IMM_I32:
261 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
262 MI->getOperand(1).getImm());
264 case AMDGPU::CONST_COPY: {
265 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
266 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
267 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
268 MI->getOperand(1).getImm());
272 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
273 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
274 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
275 unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
277 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
278 .addOperand(MI->getOperand(0))
279 .addOperand(MI->getOperand(1))
280 .addImm(EOP); // Set End of program bit
285 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
286 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
287 MachineOperand &RID = MI->getOperand(4);
288 MachineOperand &SID = MI->getOperand(5);
289 unsigned TextureId = MI->getOperand(6).getImm();
290 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
291 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
303 case 8: // ShadowRect
314 case 11: // Shadow1DArray
318 case 12: // Shadow2DArray
322 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
323 .addOperand(MI->getOperand(3))
341 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
342 .addOperand(MI->getOperand(2))
360 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
361 .addOperand(MI->getOperand(0))
362 .addOperand(MI->getOperand(1))
380 .addReg(T0, RegState::Implicit)
381 .addReg(T1, RegState::Implicit);
385 case AMDGPU::TXD_SHADOW: {
386 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
387 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
388 MachineOperand &RID = MI->getOperand(4);
389 MachineOperand &SID = MI->getOperand(5);
390 unsigned TextureId = MI->getOperand(6).getImm();
391 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
392 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
404 case 8: // ShadowRect
415 case 11: // Shadow1DArray
419 case 12: // Shadow2DArray
424 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
425 .addOperand(MI->getOperand(3))
443 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
444 .addOperand(MI->getOperand(2))
462 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
463 .addOperand(MI->getOperand(0))
464 .addOperand(MI->getOperand(1))
482 .addReg(T0, RegState::Implicit)
483 .addReg(T1, RegState::Implicit);
488 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
489 .addOperand(MI->getOperand(0));
492 case AMDGPU::BRANCH_COND_f32: {
493 MachineInstr *NewMI =
494 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
495 AMDGPU::PREDICATE_BIT)
496 .addOperand(MI->getOperand(1))
497 .addImm(OPCODE_IS_NOT_ZERO)
499 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
500 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
501 .addOperand(MI->getOperand(0))
502 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
506 case AMDGPU::BRANCH_COND_i32: {
507 MachineInstr *NewMI =
508 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
509 AMDGPU::PREDICATE_BIT)
510 .addOperand(MI->getOperand(1))
511 .addImm(OPCODE_IS_NOT_ZERO_INT)
513 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
514 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
515 .addOperand(MI->getOperand(0))
516 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
520 case AMDGPU::EG_ExportSwz:
521 case AMDGPU::R600_ExportSwz: {
522 // Instruction is left unmodified if its not the last one of its type
523 bool isLastInstructionOfItsType = true;
524 unsigned InstExportType = MI->getOperand(1).getImm();
525 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
526 EndBlock = BB->end(); NextExportInst != EndBlock;
527 NextExportInst = std::next(NextExportInst)) {
528 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
529 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
530 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
532 if (CurrentInstExportType == InstExportType) {
533 isLastInstructionOfItsType = false;
538 bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
539 if (!EOP && !isLastInstructionOfItsType)
541 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
542 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
543 .addOperand(MI->getOperand(0))
544 .addOperand(MI->getOperand(1))
545 .addOperand(MI->getOperand(2))
546 .addOperand(MI->getOperand(3))
547 .addOperand(MI->getOperand(4))
548 .addOperand(MI->getOperand(5))
549 .addOperand(MI->getOperand(6))
554 case AMDGPU::RETURN: {
555 // RETURN instructions must have the live-out registers as implicit uses,
556 // otherwise they appear dead.
557 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
558 MachineInstrBuilder MIB(*MF, MI);
559 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
560 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
565 MI->eraseFromParent();
569 //===----------------------------------------------------------------------===//
570 // Custom DAG Lowering Operations
571 //===----------------------------------------------------------------------===//
573 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
574 MachineFunction &MF = DAG.getMachineFunction();
575 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
576 switch (Op.getOpcode()) {
577 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
578 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
579 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
580 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
582 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
584 case ISD::FSIN: return LowerTrig(Op, DAG);
585 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
586 case ISD::STORE: return LowerSTORE(Op, DAG);
588 SDValue Result = LowerLOAD(Op, DAG);
589 assert((!Result.getNode() ||
590 Result.getNode()->getNumValues() == 2) &&
591 "Load should return a value and a chain");
595 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
596 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
597 case ISD::INTRINSIC_VOID: {
598 SDValue Chain = Op.getOperand(0);
599 unsigned IntrinsicID =
600 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
601 switch (IntrinsicID) {
602 case AMDGPUIntrinsic::AMDGPU_store_output: {
603 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
604 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
605 MFI->LiveOuts.push_back(Reg);
606 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
608 case AMDGPUIntrinsic::R600_store_swizzle: {
609 const SDValue Args[8] = {
611 Op.getOperand(2), // Export Value
612 Op.getOperand(3), // ArrayBase
613 Op.getOperand(4), // Type
614 DAG.getConstant(0, MVT::i32), // SWZ_X
615 DAG.getConstant(1, MVT::i32), // SWZ_Y
616 DAG.getConstant(2, MVT::i32), // SWZ_Z
617 DAG.getConstant(3, MVT::i32) // SWZ_W
619 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args);
622 // default for switch(IntrinsicID)
625 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
628 case ISD::INTRINSIC_WO_CHAIN: {
629 unsigned IntrinsicID =
630 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
631 EVT VT = Op.getValueType();
633 switch(IntrinsicID) {
634 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
635 case AMDGPUIntrinsic::R600_load_input: {
636 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
637 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
638 MachineFunction &MF = DAG.getMachineFunction();
639 MachineRegisterInfo &MRI = MF.getRegInfo();
641 return DAG.getCopyFromReg(DAG.getEntryNode(),
642 SDLoc(DAG.getEntryNode()), Reg, VT);
645 case AMDGPUIntrinsic::R600_interp_input: {
646 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
647 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
648 MachineSDNode *interp;
650 const MachineFunction &MF = DAG.getMachineFunction();
651 const R600InstrInfo *TII = static_cast<const R600InstrInfo *>(
652 MF.getSubtarget().getInstrInfo());
653 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
654 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
655 return DAG.getTargetExtractSubreg(
656 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
657 DL, MVT::f32, SDValue(interp, 0));
659 MachineFunction &MF = DAG.getMachineFunction();
660 MachineRegisterInfo &MRI = MF.getRegInfo();
661 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
662 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
663 MRI.addLiveIn(RegisterI);
664 MRI.addLiveIn(RegisterJ);
665 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
666 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
667 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
668 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
671 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
672 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
673 RegisterJNode, RegisterINode);
675 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
676 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
677 RegisterJNode, RegisterINode);
678 return SDValue(interp, slot % 2);
680 case AMDGPUIntrinsic::R600_interp_xy:
681 case AMDGPUIntrinsic::R600_interp_zw: {
682 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
683 MachineSDNode *interp;
684 SDValue RegisterINode = Op.getOperand(2);
685 SDValue RegisterJNode = Op.getOperand(3);
687 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
688 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
689 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
690 RegisterJNode, RegisterINode);
692 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
693 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
694 RegisterJNode, RegisterINode);
695 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
696 SDValue(interp, 0), SDValue(interp, 1));
698 case AMDGPUIntrinsic::R600_tex:
699 case AMDGPUIntrinsic::R600_texc:
700 case AMDGPUIntrinsic::R600_txl:
701 case AMDGPUIntrinsic::R600_txlc:
702 case AMDGPUIntrinsic::R600_txb:
703 case AMDGPUIntrinsic::R600_txbc:
704 case AMDGPUIntrinsic::R600_txf:
705 case AMDGPUIntrinsic::R600_txq:
706 case AMDGPUIntrinsic::R600_ddx:
707 case AMDGPUIntrinsic::R600_ddy:
708 case AMDGPUIntrinsic::R600_ldptr: {
710 switch (IntrinsicID) {
711 case AMDGPUIntrinsic::R600_tex:
714 case AMDGPUIntrinsic::R600_texc:
717 case AMDGPUIntrinsic::R600_txl:
720 case AMDGPUIntrinsic::R600_txlc:
723 case AMDGPUIntrinsic::R600_txb:
726 case AMDGPUIntrinsic::R600_txbc:
729 case AMDGPUIntrinsic::R600_txf:
732 case AMDGPUIntrinsic::R600_txq:
735 case AMDGPUIntrinsic::R600_ddx:
738 case AMDGPUIntrinsic::R600_ddy:
741 case AMDGPUIntrinsic::R600_ldptr:
745 llvm_unreachable("Unknow Texture Operation");
748 SDValue TexArgs[19] = {
749 DAG.getConstant(TextureOp, MVT::i32),
751 DAG.getConstant(0, MVT::i32),
752 DAG.getConstant(1, MVT::i32),
753 DAG.getConstant(2, MVT::i32),
754 DAG.getConstant(3, MVT::i32),
758 DAG.getConstant(0, MVT::i32),
759 DAG.getConstant(1, MVT::i32),
760 DAG.getConstant(2, MVT::i32),
761 DAG.getConstant(3, MVT::i32),
769 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
771 case AMDGPUIntrinsic::AMDGPU_dp4: {
773 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
774 DAG.getConstant(0, MVT::i32)),
775 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
776 DAG.getConstant(0, MVT::i32)),
777 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
778 DAG.getConstant(1, MVT::i32)),
779 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
780 DAG.getConstant(1, MVT::i32)),
781 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
782 DAG.getConstant(2, MVT::i32)),
783 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
784 DAG.getConstant(2, MVT::i32)),
785 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
786 DAG.getConstant(3, MVT::i32)),
787 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
788 DAG.getConstant(3, MVT::i32))
790 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
793 case Intrinsic::r600_read_ngroups_x:
794 return LowerImplicitParameter(DAG, VT, DL, 0);
795 case Intrinsic::r600_read_ngroups_y:
796 return LowerImplicitParameter(DAG, VT, DL, 1);
797 case Intrinsic::r600_read_ngroups_z:
798 return LowerImplicitParameter(DAG, VT, DL, 2);
799 case Intrinsic::r600_read_global_size_x:
800 return LowerImplicitParameter(DAG, VT, DL, 3);
801 case Intrinsic::r600_read_global_size_y:
802 return LowerImplicitParameter(DAG, VT, DL, 4);
803 case Intrinsic::r600_read_global_size_z:
804 return LowerImplicitParameter(DAG, VT, DL, 5);
805 case Intrinsic::r600_read_local_size_x:
806 return LowerImplicitParameter(DAG, VT, DL, 6);
807 case Intrinsic::r600_read_local_size_y:
808 return LowerImplicitParameter(DAG, VT, DL, 7);
809 case Intrinsic::r600_read_local_size_z:
810 return LowerImplicitParameter(DAG, VT, DL, 8);
812 case Intrinsic::AMDGPU_read_workdim:
813 return LowerImplicitParameter(DAG, VT, DL, MFI->ABIArgOffset / 4);
815 case Intrinsic::r600_read_tgid_x:
816 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
818 case Intrinsic::r600_read_tgid_y:
819 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
821 case Intrinsic::r600_read_tgid_z:
822 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
824 case Intrinsic::r600_read_tidig_x:
825 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
827 case Intrinsic::r600_read_tidig_y:
828 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
830 case Intrinsic::r600_read_tidig_z:
831 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
833 case Intrinsic::AMDGPU_rsq:
834 // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior.
835 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
837 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
840 } // end switch(Op.getOpcode())
844 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
845 SmallVectorImpl<SDValue> &Results,
846 SelectionDAG &DAG) const {
847 switch (N->getOpcode()) {
849 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
851 case ISD::FP_TO_UINT:
852 if (N->getValueType(0) == MVT::i1) {
853 Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
856 // Fall-through. Since we don't care about out of bounds values
857 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
858 // considers some extra cases which are not necessary here.
859 case ISD::FP_TO_SINT: {
861 if (expandFP_TO_SINT(N, Result, DAG))
862 Results.push_back(Result);
866 SDValue Op = SDValue(N, 0);
868 EVT VT = Op.getValueType();
869 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
870 N->getOperand(0), N->getOperand(1));
871 Results.push_back(UDIVREM);
875 SDValue Op = SDValue(N, 0);
877 EVT VT = Op.getValueType();
878 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
879 N->getOperand(0), N->getOperand(1));
880 Results.push_back(UDIVREM.getValue(1));
884 SDValue Op = SDValue(N, 0);
886 EVT VT = Op.getValueType();
887 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
888 N->getOperand(0), N->getOperand(1));
889 Results.push_back(SDIVREM);
893 SDValue Op = SDValue(N, 0);
895 EVT VT = Op.getValueType();
896 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
897 N->getOperand(0), N->getOperand(1));
898 Results.push_back(SDIVREM.getValue(1));
902 SDValue Op = SDValue(N, 1);
903 SDValue RES = LowerSDIVREM(Op, DAG);
904 Results.push_back(RES);
905 Results.push_back(RES.getValue(1));
909 SDValue Op = SDValue(N, 0);
910 LowerUDIVREM64(Op, DAG, Results);
916 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
917 SDValue Vector) const {
920 EVT VecVT = Vector.getValueType();
921 EVT EltVT = VecVT.getVectorElementType();
922 SmallVector<SDValue, 8> Args;
924 for (unsigned i = 0, e = VecVT.getVectorNumElements();
926 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
927 Vector, DAG.getConstant(i, getVectorIdxTy())));
930 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
933 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
934 SelectionDAG &DAG) const {
937 SDValue Vector = Op.getOperand(0);
938 SDValue Index = Op.getOperand(1);
940 if (isa<ConstantSDNode>(Index) ||
941 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
944 Vector = vectorToVerticalVector(DAG, Vector);
945 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
949 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
950 SelectionDAG &DAG) const {
952 SDValue Vector = Op.getOperand(0);
953 SDValue Value = Op.getOperand(1);
954 SDValue Index = Op.getOperand(2);
956 if (isa<ConstantSDNode>(Index) ||
957 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
960 Vector = vectorToVerticalVector(DAG, Vector);
961 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
962 Vector, Value, Index);
963 return vectorToVerticalVector(DAG, Insert);
966 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
967 // On hw >= R700, COS/SIN input must be between -1. and 1.
968 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
969 EVT VT = Op.getValueType();
970 SDValue Arg = Op.getOperand(0);
971 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
972 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
973 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
974 DAG.getConstantFP(0.15915494309, MVT::f32)),
975 DAG.getConstantFP(0.5, MVT::f32)));
977 switch (Op.getOpcode()) {
979 TrigNode = AMDGPUISD::COS_HW;
982 TrigNode = AMDGPUISD::SIN_HW;
985 llvm_unreachable("Wrong trig opcode");
987 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
988 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
989 DAG.getConstantFP(-0.5, MVT::f32)));
990 if (Gen >= AMDGPUSubtarget::R700)
992 // On R600 hw, COS/SIN input must be between -Pi and Pi.
993 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
994 DAG.getConstantFP(3.14159265359, MVT::f32));
997 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
999 EVT VT = Op.getValueType();
1001 SDValue Lo = Op.getOperand(0);
1002 SDValue Hi = Op.getOperand(1);
1003 SDValue Shift = Op.getOperand(2);
1004 SDValue Zero = DAG.getConstant(0, VT);
1005 SDValue One = DAG.getConstant(1, VT);
1007 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1008 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1009 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1010 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1012 // The dance around Width1 is necessary for 0 special case.
1013 // Without it the CompShift might be 32, producing incorrect results in
1014 // Overflow. So we do the shift in two steps, the alternative is to
1015 // add a conditional to filter the special case.
1017 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
1018 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
1020 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
1021 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
1022 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
1024 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
1025 SDValue LoBig = Zero;
1027 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1028 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1030 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1033 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1035 EVT VT = Op.getValueType();
1037 SDValue Lo = Op.getOperand(0);
1038 SDValue Hi = Op.getOperand(1);
1039 SDValue Shift = Op.getOperand(2);
1040 SDValue Zero = DAG.getConstant(0, VT);
1041 SDValue One = DAG.getConstant(1, VT);
1043 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1045 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1046 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1047 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1048 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1050 // The dance around Width1 is necessary for 0 special case.
1051 // Without it the CompShift might be 32, producing incorrect results in
1052 // Overflow. So we do the shift in two steps, the alternative is to
1053 // add a conditional to filter the special case.
1055 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
1056 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1058 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1059 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
1060 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
1062 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1063 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
1065 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1066 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1068 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1071 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1076 Op, DAG.getConstantFP(0.0f, MVT::f32),
1077 DAG.getCondCode(ISD::SETNE)
1081 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
1083 unsigned DwordOffset) const {
1084 unsigned ByteOffset = DwordOffset * 4;
1085 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1086 AMDGPUAS::CONSTANT_BUFFER_0);
1088 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
1089 assert(isInt<16>(ByteOffset));
1091 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1092 DAG.getConstant(ByteOffset, MVT::i32), // PTR
1093 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
1094 false, false, false, 0);
1097 bool R600TargetLowering::isZero(SDValue Op) const {
1098 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
1099 return Cst->isNullValue();
1100 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
1101 return CstFP->isZero();
1107 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1109 EVT VT = Op.getValueType();
1111 SDValue LHS = Op.getOperand(0);
1112 SDValue RHS = Op.getOperand(1);
1113 SDValue True = Op.getOperand(2);
1114 SDValue False = Op.getOperand(3);
1115 SDValue CC = Op.getOperand(4);
1118 // LHS and RHS are guaranteed to be the same value type
1119 EVT CompareVT = LHS.getValueType();
1121 // Check if we can lower this to a native operation.
1123 // Try to lower to a SET* instruction:
1125 // SET* can match the following patterns:
1127 // select_cc f32, f32, -1, 0, cc_supported
1128 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
1129 // select_cc i32, i32, -1, 0, cc_supported
1132 // Move hardware True/False values to the correct operand.
1133 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1134 ISD::CondCode InverseCC =
1135 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1136 if (isHWTrueValue(False) && isHWFalseValue(True)) {
1137 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
1138 std::swap(False, True);
1139 CC = DAG.getCondCode(InverseCC);
1141 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
1142 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
1143 std::swap(False, True);
1144 std::swap(LHS, RHS);
1145 CC = DAG.getCondCode(SwapInvCC);
1150 if (isHWTrueValue(True) && isHWFalseValue(False) &&
1151 (CompareVT == VT || VT == MVT::i32)) {
1152 // This can be matched by a SET* instruction.
1153 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1156 // Try to lower to a CND* instruction:
1158 // CND* can match the following patterns:
1160 // select_cc f32, 0.0, f32, f32, cc_supported
1161 // select_cc f32, 0.0, i32, i32, cc_supported
1162 // select_cc i32, 0, f32, f32, cc_supported
1163 // select_cc i32, 0, i32, i32, cc_supported
1166 // Try to move the zero value to the RHS
1168 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1169 // Try swapping the operands
1170 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
1171 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1172 std::swap(LHS, RHS);
1173 CC = DAG.getCondCode(CCSwapped);
1175 // Try inverting the conditon and then swapping the operands
1176 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
1177 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
1178 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1179 std::swap(True, False);
1180 std::swap(LHS, RHS);
1181 CC = DAG.getCondCode(CCSwapped);
1188 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1189 if (CompareVT != VT) {
1190 // Bitcast True / False to the correct types. This will end up being
1191 // a nop, but it allows us to define only a single pattern in the
1192 // .TD files for each CND* instruction rather than having to have
1193 // one pattern for integer True/False and one for fp True/False
1194 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1195 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1202 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1210 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1213 DAG.getCondCode(CCOpcode));
1214 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1217 // If we make it this for it means we have no native instructions to handle
1218 // this SELECT_CC, so we must lower it.
1219 SDValue HWTrue, HWFalse;
1221 if (CompareVT == MVT::f32) {
1222 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
1223 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
1224 } else if (CompareVT == MVT::i32) {
1225 HWTrue = DAG.getConstant(-1, CompareVT);
1226 HWFalse = DAG.getConstant(0, CompareVT);
1229 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1232 // Lower this unsupported SELECT_CC into a combination of two supported
1233 // SELECT_CC operations.
1234 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1236 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1239 DAG.getCondCode(ISD::SETNE));
1242 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1243 /// convert these pointers to a register index. Each register holds
1244 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1245 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1246 /// for indirect addressing.
1247 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1248 unsigned StackWidth,
1249 SelectionDAG &DAG) const {
1251 switch(StackWidth) {
1261 default: llvm_unreachable("Invalid stack width");
1264 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1265 DAG.getConstant(SRLPad, MVT::i32));
1268 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1271 unsigned &PtrIncr) const {
1272 switch (StackWidth) {
1283 Channel = ElemIdx % 2;
1297 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1299 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1300 SDValue Chain = Op.getOperand(0);
1301 SDValue Value = Op.getOperand(1);
1302 SDValue Ptr = Op.getOperand(2);
1304 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1305 if (Result.getNode()) {
1309 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1310 if (StoreNode->isTruncatingStore()) {
1311 EVT VT = Value.getValueType();
1312 assert(VT.bitsLE(MVT::i32));
1313 EVT MemVT = StoreNode->getMemoryVT();
1314 SDValue MaskConstant;
1315 if (MemVT == MVT::i8) {
1316 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1318 assert(MemVT == MVT::i16);
1319 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1321 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1322 DAG.getConstant(2, MVT::i32));
1323 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1324 DAG.getConstant(0x00000003, VT));
1325 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1326 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1327 DAG.getConstant(3, VT));
1328 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1329 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1330 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1334 DAG.getConstant(0, MVT::i32),
1335 DAG.getConstant(0, MVT::i32),
1338 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1339 SDValue Args[3] = { Chain, Input, DWordAddr };
1340 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1341 Op->getVTList(), Args, MemVT,
1342 StoreNode->getMemOperand());
1343 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1344 Value.getValueType().bitsGE(MVT::i32)) {
1345 // Convert pointer from byte address to dword address.
1346 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1347 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1348 Ptr, DAG.getConstant(2, MVT::i32)));
1350 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1351 llvm_unreachable("Truncated and indexed stores not supported yet");
1353 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1359 EVT ValueVT = Value.getValueType();
1361 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1365 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1366 if (Ret.getNode()) {
1369 // Lowering for indirect addressing
1371 const MachineFunction &MF = DAG.getMachineFunction();
1372 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
1373 getTargetMachine().getSubtargetImpl()->getFrameLowering());
1374 unsigned StackWidth = TFL->getStackWidth(MF);
1376 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1378 if (ValueVT.isVector()) {
1379 unsigned NumElemVT = ValueVT.getVectorNumElements();
1380 EVT ElemVT = ValueVT.getVectorElementType();
1381 SmallVector<SDValue, 4> Stores(NumElemVT);
1383 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1384 "vector width in load");
1386 for (unsigned i = 0; i < NumElemVT; ++i) {
1387 unsigned Channel, PtrIncr;
1388 getStackAddress(StackWidth, i, Channel, PtrIncr);
1389 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1390 DAG.getConstant(PtrIncr, MVT::i32));
1391 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1392 Value, DAG.getConstant(i, MVT::i32));
1394 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1396 DAG.getTargetConstant(Channel, MVT::i32));
1398 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1400 if (ValueVT == MVT::i8) {
1401 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1403 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1404 DAG.getTargetConstant(0, MVT::i32)); // Channel
1410 // return (512 + (kc_bank << 12)
1412 ConstantAddressBlock(unsigned AddressSpace) {
1413 switch (AddressSpace) {
1414 case AMDGPUAS::CONSTANT_BUFFER_0:
1416 case AMDGPUAS::CONSTANT_BUFFER_1:
1418 case AMDGPUAS::CONSTANT_BUFFER_2:
1419 return 512 + 4096 * 2;
1420 case AMDGPUAS::CONSTANT_BUFFER_3:
1421 return 512 + 4096 * 3;
1422 case AMDGPUAS::CONSTANT_BUFFER_4:
1423 return 512 + 4096 * 4;
1424 case AMDGPUAS::CONSTANT_BUFFER_5:
1425 return 512 + 4096 * 5;
1426 case AMDGPUAS::CONSTANT_BUFFER_6:
1427 return 512 + 4096 * 6;
1428 case AMDGPUAS::CONSTANT_BUFFER_7:
1429 return 512 + 4096 * 7;
1430 case AMDGPUAS::CONSTANT_BUFFER_8:
1431 return 512 + 4096 * 8;
1432 case AMDGPUAS::CONSTANT_BUFFER_9:
1433 return 512 + 4096 * 9;
1434 case AMDGPUAS::CONSTANT_BUFFER_10:
1435 return 512 + 4096 * 10;
1436 case AMDGPUAS::CONSTANT_BUFFER_11:
1437 return 512 + 4096 * 11;
1438 case AMDGPUAS::CONSTANT_BUFFER_12:
1439 return 512 + 4096 * 12;
1440 case AMDGPUAS::CONSTANT_BUFFER_13:
1441 return 512 + 4096 * 13;
1442 case AMDGPUAS::CONSTANT_BUFFER_14:
1443 return 512 + 4096 * 14;
1444 case AMDGPUAS::CONSTANT_BUFFER_15:
1445 return 512 + 4096 * 15;
1451 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1453 EVT VT = Op.getValueType();
1455 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1456 SDValue Chain = Op.getOperand(0);
1457 SDValue Ptr = Op.getOperand(1);
1458 SDValue LoweredLoad;
1460 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1461 if (Ret.getNode()) {
1466 return DAG.getMergeValues(Ops, DL);
1469 // Lower loads constant address space global variable loads
1470 if (LoadNode->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1471 isa<GlobalVariable>(
1472 GetUnderlyingObject(LoadNode->getMemOperand()->getValue()))) {
1474 SDValue Ptr = DAG.getZExtOrTrunc(LoadNode->getBasePtr(), DL,
1475 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1476 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1477 DAG.getConstant(2, MVT::i32));
1478 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op->getVTList(),
1479 LoadNode->getChain(), Ptr,
1480 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1483 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1484 SDValue MergedValues[2] = {
1485 ScalarizeVectorLoad(Op, DAG),
1488 return DAG.getMergeValues(MergedValues, DL);
1491 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1492 if (ConstantBlock > -1 &&
1493 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1494 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1496 if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1497 isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1498 isa<ConstantSDNode>(Ptr)) {
1500 for (unsigned i = 0; i < 4; i++) {
1501 // We want Const position encoded with the following formula :
1502 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1503 // const_index is Ptr computed by llvm using an alignment of 16.
1504 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1505 // then div by 4 at the ISel step
1506 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1507 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1508 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1510 EVT NewVT = MVT::v4i32;
1511 unsigned NumElements = 4;
1512 if (VT.isVector()) {
1514 NumElements = VT.getVectorNumElements();
1516 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
1517 makeArrayRef(Slots, NumElements));
1519 // non-constant ptr can't be folded, keeps it as a v4f32 load
1520 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1521 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1522 DAG.getConstant(LoadNode->getAddressSpace() -
1523 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1527 if (!VT.isVector()) {
1528 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1529 DAG.getConstant(0, MVT::i32));
1532 SDValue MergedValues[2] = {
1536 return DAG.getMergeValues(MergedValues, DL);
1539 // For most operations returning SDValue() will result in the node being
1540 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1541 // need to manually expand loads that may be legal in some address spaces and
1542 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1543 // compute shaders, since the data is sign extended when it is uploaded to the
1544 // buffer. However SEXT loads from other address spaces are not supported, so
1545 // we need to expand them here.
1546 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1547 EVT MemVT = LoadNode->getMemoryVT();
1548 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1549 SDValue ShiftAmount =
1550 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1551 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1552 LoadNode->getPointerInfo(), MemVT,
1553 LoadNode->isVolatile(),
1554 LoadNode->isNonTemporal(),
1555 LoadNode->isInvariant(),
1556 LoadNode->getAlignment());
1557 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1558 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1560 SDValue MergedValues[2] = { Sra, Chain };
1561 return DAG.getMergeValues(MergedValues, DL);
1564 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1568 // Lowering for indirect addressing
1569 const MachineFunction &MF = DAG.getMachineFunction();
1570 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
1571 getTargetMachine().getSubtargetImpl()->getFrameLowering());
1572 unsigned StackWidth = TFL->getStackWidth(MF);
1574 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1576 if (VT.isVector()) {
1577 unsigned NumElemVT = VT.getVectorNumElements();
1578 EVT ElemVT = VT.getVectorElementType();
1581 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1582 "vector width in load");
1584 for (unsigned i = 0; i < NumElemVT; ++i) {
1585 unsigned Channel, PtrIncr;
1586 getStackAddress(StackWidth, i, Channel, PtrIncr);
1587 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1588 DAG.getConstant(PtrIncr, MVT::i32));
1589 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1591 DAG.getTargetConstant(Channel, MVT::i32),
1594 for (unsigned i = NumElemVT; i < 4; ++i) {
1595 Loads[i] = DAG.getUNDEF(ElemVT);
1597 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1598 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
1600 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1602 DAG.getTargetConstant(0, MVT::i32), // Channel
1611 return DAG.getMergeValues(Ops, DL);
1614 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1615 SDValue Chain = Op.getOperand(0);
1616 SDValue Cond = Op.getOperand(1);
1617 SDValue Jump = Op.getOperand(2);
1619 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1623 /// XXX Only kernel functions are supported, so we can assume for now that
1624 /// every function is a kernel function, but in the future we should use
1625 /// separate calling conventions for kernel and non-kernel functions.
1626 SDValue R600TargetLowering::LowerFormalArguments(
1628 CallingConv::ID CallConv,
1630 const SmallVectorImpl<ISD::InputArg> &Ins,
1631 SDLoc DL, SelectionDAG &DAG,
1632 SmallVectorImpl<SDValue> &InVals) const {
1633 SmallVector<CCValAssign, 16> ArgLocs;
1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1636 MachineFunction &MF = DAG.getMachineFunction();
1637 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
1639 SmallVector<ISD::InputArg, 8> LocalIns;
1641 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1643 AnalyzeFormalArguments(CCInfo, LocalIns);
1645 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1646 CCValAssign &VA = ArgLocs[i];
1647 const ISD::InputArg &In = Ins[i];
1649 EVT MemVT = VA.getLocVT();
1650 if (!VT.isVector() && MemVT.isVector()) {
1651 // Get load source type if scalarized.
1652 MemVT = MemVT.getVectorElementType();
1655 if (MFI->getShaderType() != ShaderType::COMPUTE) {
1656 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1657 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1658 InVals.push_back(Register);
1662 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1663 AMDGPUAS::CONSTANT_BUFFER_0);
1665 // i64 isn't a legal type, so the register type used ends up as i32, which
1666 // isn't expected here. It attempts to create this sextload, but it ends up
1667 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1670 // The first 36 bytes of the input buffer contains information about
1671 // thread group and global sizes.
1672 ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1673 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1674 // FIXME: This should really check the extload type, but the handling of
1675 // extload vector parameters seems to be broken.
1677 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1678 Ext = ISD::SEXTLOAD;
1681 // Compute the offset from the value.
1682 // XXX - I think PartOffset should give you this, but it seems to give the
1683 // size of the register which isn't useful.
1685 unsigned ValBase = ArgLocs[In.OrigArgIndex].getLocMemOffset();
1686 unsigned PartOffset = VA.getLocMemOffset();
1687 unsigned Offset = 36 + VA.getLocMemOffset();
1689 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
1690 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain,
1691 DAG.getConstant(Offset, MVT::i32),
1692 DAG.getUNDEF(MVT::i32),
1694 MemVT, false, true, true, 4);
1696 // 4 is the preferred alignment for the CONSTANT memory space.
1697 InVals.push_back(Arg);
1698 MFI->ABIArgOffset = Offset + MemVT.getStoreSize();
1703 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1706 return VT.changeVectorElementTypeToInteger();
1709 static SDValue CompactSwizzlableVector(
1710 SelectionDAG &DAG, SDValue VectorEntry,
1711 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1712 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1713 assert(RemapSwizzle.empty());
1714 SDValue NewBldVec[4] = {
1715 VectorEntry.getOperand(0),
1716 VectorEntry.getOperand(1),
1717 VectorEntry.getOperand(2),
1718 VectorEntry.getOperand(3)
1721 for (unsigned i = 0; i < 4; i++) {
1722 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1723 // We mask write here to teach later passes that the ith element of this
1724 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1725 // break false dependencies and additionnaly make assembly easier to read.
1726 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1727 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1729 RemapSwizzle[i] = 4; // SEL_0
1730 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1731 } else if (C->isExactlyValue(1.0)) {
1732 RemapSwizzle[i] = 5; // SEL_1
1733 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1737 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1739 for (unsigned j = 0; j < i; j++) {
1740 if (NewBldVec[i] == NewBldVec[j]) {
1741 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1742 RemapSwizzle[i] = j;
1748 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1749 VectorEntry.getValueType(), NewBldVec);
1752 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1753 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1754 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1755 assert(RemapSwizzle.empty());
1756 SDValue NewBldVec[4] = {
1757 VectorEntry.getOperand(0),
1758 VectorEntry.getOperand(1),
1759 VectorEntry.getOperand(2),
1760 VectorEntry.getOperand(3)
1762 bool isUnmovable[4] = { false, false, false, false };
1763 for (unsigned i = 0; i < 4; i++) {
1764 RemapSwizzle[i] = i;
1765 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1766 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1769 isUnmovable[Idx] = true;
1773 for (unsigned i = 0; i < 4; i++) {
1774 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1775 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1777 if (isUnmovable[Idx])
1780 std::swap(NewBldVec[Idx], NewBldVec[i]);
1781 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1786 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1787 VectorEntry.getValueType(), NewBldVec);
1791 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1792 SDValue Swz[4], SelectionDAG &DAG) const {
1793 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1794 // Old -> New swizzle values
1795 DenseMap<unsigned, unsigned> SwizzleRemap;
1797 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1798 for (unsigned i = 0; i < 4; i++) {
1799 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1800 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1801 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1804 SwizzleRemap.clear();
1805 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1806 for (unsigned i = 0; i < 4; i++) {
1807 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1808 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1809 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1816 //===----------------------------------------------------------------------===//
1817 // Custom DAG Optimizations
1818 //===----------------------------------------------------------------------===//
1820 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1821 DAGCombinerInfo &DCI) const {
1822 SelectionDAG &DAG = DCI.DAG;
1824 switch (N->getOpcode()) {
1825 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1826 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1827 case ISD::FP_ROUND: {
1828 SDValue Arg = N->getOperand(0);
1829 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1830 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1836 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1837 // (i32 select_cc f32, f32, -1, 0 cc)
1839 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1840 // this to one of the SET*_DX10 instructions.
1841 case ISD::FP_TO_SINT: {
1842 SDValue FNeg = N->getOperand(0);
1843 if (FNeg.getOpcode() != ISD::FNEG) {
1846 SDValue SelectCC = FNeg.getOperand(0);
1847 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1848 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1849 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1850 !isHWTrueValue(SelectCC.getOperand(2)) ||
1851 !isHWFalseValue(SelectCC.getOperand(3))) {
1855 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1856 SelectCC.getOperand(0), // LHS
1857 SelectCC.getOperand(1), // RHS
1858 DAG.getConstant(-1, MVT::i32), // True
1859 DAG.getConstant(0, MVT::i32), // Flase
1860 SelectCC.getOperand(4)); // CC
1865 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1866 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1867 case ISD::INSERT_VECTOR_ELT: {
1868 SDValue InVec = N->getOperand(0);
1869 SDValue InVal = N->getOperand(1);
1870 SDValue EltNo = N->getOperand(2);
1873 // If the inserted element is an UNDEF, just use the input vector.
1874 if (InVal.getOpcode() == ISD::UNDEF)
1877 EVT VT = InVec.getValueType();
1879 // If we can't generate a legal BUILD_VECTOR, exit
1880 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1883 // Check that we know which element is being inserted
1884 if (!isa<ConstantSDNode>(EltNo))
1886 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1888 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1889 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1891 SmallVector<SDValue, 8> Ops;
1892 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1893 Ops.append(InVec.getNode()->op_begin(),
1894 InVec.getNode()->op_end());
1895 } else if (InVec.getOpcode() == ISD::UNDEF) {
1896 unsigned NElts = VT.getVectorNumElements();
1897 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1902 // Insert the element
1903 if (Elt < Ops.size()) {
1904 // All the operands of BUILD_VECTOR must have the same type;
1905 // we enforce that here.
1906 EVT OpVT = Ops[0].getValueType();
1907 if (InVal.getValueType() != OpVT)
1908 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1909 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1910 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1914 // Return the new vector
1915 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1918 // Extract_vec (Build_vector) generated by custom lowering
1919 // also needs to be customly combined
1920 case ISD::EXTRACT_VECTOR_ELT: {
1921 SDValue Arg = N->getOperand(0);
1922 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1923 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1924 unsigned Element = Const->getZExtValue();
1925 return Arg->getOperand(Element);
1928 if (Arg.getOpcode() == ISD::BITCAST &&
1929 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1930 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1931 unsigned Element = Const->getZExtValue();
1932 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1933 Arg->getOperand(0).getOperand(Element));
1938 case ISD::SELECT_CC: {
1939 // Try common optimizations
1940 SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1944 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1945 // selectcc x, y, a, b, inv(cc)
1947 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1948 // selectcc x, y, a, b, cc
1949 SDValue LHS = N->getOperand(0);
1950 if (LHS.getOpcode() != ISD::SELECT_CC) {
1954 SDValue RHS = N->getOperand(1);
1955 SDValue True = N->getOperand(2);
1956 SDValue False = N->getOperand(3);
1957 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1959 if (LHS.getOperand(2).getNode() != True.getNode() ||
1960 LHS.getOperand(3).getNode() != False.getNode() ||
1961 RHS.getNode() != False.getNode()) {
1966 default: return SDValue();
1967 case ISD::SETNE: return LHS;
1969 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1970 LHSCC = ISD::getSetCCInverse(LHSCC,
1971 LHS.getOperand(0).getValueType().isInteger());
1972 if (DCI.isBeforeLegalizeOps() ||
1973 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1974 return DAG.getSelectCC(SDLoc(N),
1986 case AMDGPUISD::EXPORT: {
1987 SDValue Arg = N->getOperand(1);
1988 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1991 SDValue NewArgs[8] = {
1992 N->getOperand(0), // Chain
1994 N->getOperand(2), // ArrayBase
1995 N->getOperand(3), // Type
1996 N->getOperand(4), // SWZ_X
1997 N->getOperand(5), // SWZ_Y
1998 N->getOperand(6), // SWZ_Z
1999 N->getOperand(7) // SWZ_W
2002 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
2003 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
2005 case AMDGPUISD::TEXTURE_FETCH: {
2006 SDValue Arg = N->getOperand(1);
2007 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2010 SDValue NewArgs[19] = {
2031 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
2032 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
2037 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2041 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
2042 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2043 const R600InstrInfo *TII =
2044 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2045 if (!Src.isMachineOpcode())
2047 switch (Src.getMachineOpcode()) {
2048 case AMDGPU::FNEG_R600:
2051 Src = Src.getOperand(0);
2052 Neg = DAG.getTargetConstant(1, MVT::i32);
2054 case AMDGPU::FABS_R600:
2057 Src = Src.getOperand(0);
2058 Abs = DAG.getTargetConstant(1, MVT::i32);
2060 case AMDGPU::CONST_COPY: {
2061 unsigned Opcode = ParentNode->getMachineOpcode();
2062 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2067 SDValue CstOffset = Src.getOperand(0);
2068 if (ParentNode->getValueType(0).isVector())
2071 // Gather constants values
2072 int SrcIndices[] = {
2073 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2074 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2075 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
2076 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2077 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2078 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2079 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2080 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2081 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2082 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2083 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2085 std::vector<unsigned> Consts;
2086 for (int OtherSrcIdx : SrcIndices) {
2087 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2088 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2094 if (RegisterSDNode *Reg =
2095 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2096 if (Reg->getReg() == AMDGPU::ALU_CONST) {
2098 = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2099 Consts.push_back(Cst->getZExtValue());
2104 ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2105 Consts.push_back(Cst->getZExtValue());
2106 if (!TII->fitsConstReadLimitations(Consts)) {
2111 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
2114 case AMDGPU::MOV_IMM_I32:
2115 case AMDGPU::MOV_IMM_F32: {
2116 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2117 uint64_t ImmValue = 0;
2120 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
2121 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2122 float FloatValue = FPC->getValueAPF().convertToFloat();
2123 if (FloatValue == 0.0) {
2124 ImmReg = AMDGPU::ZERO;
2125 } else if (FloatValue == 0.5) {
2126 ImmReg = AMDGPU::HALF;
2127 } else if (FloatValue == 1.0) {
2128 ImmReg = AMDGPU::ONE;
2130 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2133 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2134 uint64_t Value = C->getZExtValue();
2136 ImmReg = AMDGPU::ZERO;
2137 } else if (Value == 1) {
2138 ImmReg = AMDGPU::ONE_INT;
2144 // Check that we aren't already using an immediate.
2145 // XXX: It's possible for an instruction to have more than one
2146 // immediate operand, but this is not supported yet.
2147 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2150 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2152 if (C->getZExtValue())
2154 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
2156 Src = DAG.getRegister(ImmReg, MVT::i32);
2165 /// \brief Fold the instructions after selecting them
2166 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2167 SelectionDAG &DAG) const {
2168 const R600InstrInfo *TII =
2169 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2170 if (!Node->isMachineOpcode())
2172 unsigned Opcode = Node->getMachineOpcode();
2175 std::vector<SDValue> Ops;
2176 for (const SDUse &I : Node->ops())
2179 if (Opcode == AMDGPU::DOT_4) {
2180 int OperandIdx[] = {
2181 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2182 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2183 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2184 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2185 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2186 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2187 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2188 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2191 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
2192 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
2193 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
2194 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
2195 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
2196 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
2197 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
2198 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
2201 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
2202 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
2203 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
2204 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
2205 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
2206 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
2207 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
2208 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
2210 for (unsigned i = 0; i < 8; i++) {
2211 if (OperandIdx[i] < 0)
2213 SDValue &Src = Ops[OperandIdx[i] - 1];
2214 SDValue &Neg = Ops[NegIdx[i] - 1];
2215 SDValue &Abs = Ops[AbsIdx[i] - 1];
2216 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2217 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2220 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2221 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2222 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2224 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
2225 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2226 SDValue &Src = Ops[i];
2227 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2228 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2230 } else if (Opcode == AMDGPU::CLAMP_R600) {
2231 SDValue Src = Node->getOperand(0);
2232 if (!Src.isMachineOpcode() ||
2233 !TII->hasInstrModifiers(Src.getMachineOpcode()))
2235 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
2236 AMDGPU::OpName::clamp);
2239 std::vector<SDValue> Ops;
2240 unsigned NumOp = Src.getNumOperands();
2241 for(unsigned i = 0; i < NumOp; ++i)
2242 Ops.push_back(Src.getOperand(i));
2243 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
2244 return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
2245 Node->getVTList(), Ops);
2247 if (!TII->hasInstrModifiers(Opcode))
2249 int OperandIdx[] = {
2250 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2251 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2252 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
2255 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
2256 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
2257 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
2260 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
2261 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
2264 for (unsigned i = 0; i < 3; i++) {
2265 if (OperandIdx[i] < 0)
2267 SDValue &Src = Ops[OperandIdx[i] - 1];
2268 SDValue &Neg = Ops[NegIdx[i] - 1];
2270 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2271 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2272 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2273 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2278 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2279 SDValue &Imm = Ops[ImmIdx];
2280 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2281 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);