1 //===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
11 #include "llvm/ADT/SmallString.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCTargetAsmParser.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
35 class AMDGPUAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "AMDGPUGenAsmMatcher.inc"
49 AMDGPUAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
50 const MCInstrInfo &_MII,
51 const MCTargetOptions &Options)
52 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
53 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
55 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
56 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
57 OperandVector &Operands, MCStreamer &Out,
59 bool MatchingInlineAsm) override;
60 bool ParseDirective(AsmToken DirectiveID) override;
61 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
62 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
63 SMLoc NameLoc, OperandVector &Operands) override;
65 bool parseCnt(int64_t &IntVal);
66 OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
69 class AMDGPUOperand : public MCParsedAsmOperand {
76 AMDGPUOperand(enum KindTy K) : MCParsedAsmOperand(), Kind(K) {}
92 void addImmOperands(MCInst &Inst, unsigned N) const {
93 Inst.addOperand(MCOperand::CreateImm(getImm()));
95 void addRegOperands(MCInst &Inst, unsigned N) const {
96 llvm_unreachable("addRegOperands");
98 StringRef getToken() const {
99 return StringRef(Tok.Data, Tok.Length);
101 bool isToken() const override {
102 return Kind == Token;
105 bool isImm() const override {
106 return Kind == Immediate;
109 int64_t getImm() const {
113 bool isReg() const override {
117 unsigned getReg() const override {
121 bool isMem() const override {
125 SMLoc getStartLoc() const override {
129 SMLoc getEndLoc() const override {
133 void print(raw_ostream &OS) const override { }
135 static std::unique_ptr<AMDGPUOperand> CreateImm(int64_t Val) {
136 auto Op = llvm::make_unique<AMDGPUOperand>(Immediate);
141 static std::unique_ptr<AMDGPUOperand> CreateToken(StringRef Str, SMLoc Loc) {
142 auto Res = llvm::make_unique<AMDGPUOperand>(Token);
143 Res->Tok.Data = Str.data();
144 Res->Tok.Length = Str.size();
148 bool isSWaitCnt() const;
153 bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
158 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
159 OperandVector &Operands,
162 bool MatchingInlineAsm) {
165 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
168 Out.EmitInstruction(Inst, STI);
170 case Match_MissingFeature:
171 return Error(IDLoc, "instruction use requires an option to be enabled");
172 case Match_MnemonicFail:
173 return Error(IDLoc, "unrecognized instruction mnemonic");
174 case Match_InvalidOperand: {
175 if (ErrorInfo != ~0ULL) {
176 if (ErrorInfo >= Operands.size())
177 return Error(IDLoc, "too few operands for instruction");
180 return Error(IDLoc, "invalid operand for instruction");
183 llvm_unreachable("Implement any new match types added!");
186 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
190 AMDGPUAsmParser::OperandMatchResultTy
191 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
193 // Try to parse with a custom parser
194 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
196 // If we successfully parsed the operand or if there as an error parsing,
198 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
201 switch(getLexer().getKind()) {
202 case AsmToken::Integer: {
204 if (getParser().parseAbsoluteExpression(IntVal))
205 return MatchOperand_ParseFail;
206 Operands.push_back(AMDGPUOperand::CreateImm(IntVal));
207 return MatchOperand_Success;
210 return MatchOperand_NoMatch;
214 bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
216 SMLoc NameLoc, OperandVector &Operands) {
217 // Add the instruction mnemonic
218 Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc));
220 if (getLexer().is(AsmToken::EndOfStatement))
223 AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);
225 case MatchOperand_Success: return false;
226 case MatchOperand_ParseFail: return Error(NameLoc,
227 "Failed parsing operand");
228 case MatchOperand_NoMatch: return Error(NameLoc, "Not a valid operand");
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
237 bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
238 StringRef CntName = Parser.getTok().getString();
242 if (getLexer().isNot(AsmToken::LParen))
246 if (getLexer().isNot(AsmToken::Integer))
249 if (getParser().parseAbsoluteExpression(CntVal))
252 if (getLexer().isNot(AsmToken::RParen))
256 if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma))
262 if (CntName == "vmcnt") {
265 } else if (CntName == "expcnt") {
268 } else if (CntName == "lgkmcnt") {
275 IntVal &= ~(CntMask << CntShift);
276 IntVal |= (CntVal << CntShift);
280 AMDGPUAsmParser::OperandMatchResultTy
281 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
282 // Disable all counters by default.
286 int64_t CntVal = 0x77f;
288 switch(getLexer().getKind()) {
289 default: return MatchOperand_ParseFail;
290 case AsmToken::Integer:
291 // The operand can be an integer value.
292 if (getParser().parseAbsoluteExpression(CntVal))
293 return MatchOperand_ParseFail;
296 case AsmToken::Identifier:
298 if (parseCnt(CntVal))
299 return MatchOperand_ParseFail;
300 } while(getLexer().isNot(AsmToken::EndOfStatement));
303 Operands.push_back(AMDGPUOperand::CreateImm(CntVal));
304 return MatchOperand_Success;
307 bool AMDGPUOperand::isSWaitCnt() const {
311 /// Force static initialization.
312 extern "C" void LLVMInitializeR600AsmParser() {
313 RegisterMCAsmParser<AMDGPUAsmParser> A(TheAMDGPUTarget);
314 RegisterMCAsmParser<AMDGPUAsmParser> B(TheGCNTarget);
317 #define GET_REGISTER_MATCHER
318 #define GET_MATCHER_IMPLEMENTATION
319 #include "AMDGPUGenAsmMatcher.inc"