lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19 #include "AMDGPUAsmPrinter.h"
  20 #include "AMDGPU.h"
  21 #include "AMDKernelCodeT.h"
  22 #include "AMDGPUSubtarget.h"
  23 #include "R600Defines.h"
  24 #include "R600MachineFunctionInfo.h"
  25 #include "R600RegisterInfo.h"
  26 #include "SIDefines.h"
  27 #include "SIMachineFunctionInfo.h"
  28 #include "SIRegisterInfo.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/MC/MCContext.h"
  31 #include "llvm/MC/MCSectionELF.h"
  32 #include "llvm/MC/MCStreamer.h"
  33 #include "llvm/Support/ELF.h"
  34 #include "llvm/Support/MathExtras.h"
  35 #include "llvm/Support/TargetRegistry.h"
  36 #include "llvm/Target/TargetLoweringObjectFile.h"
  37
  38 using namespace llvm;
  39
  40 // TODO: This should get the default rounding mode from the kernel. We just set
  41 // the default here, but this could change if the OpenCL rounding mode pragmas
  42 // are used.
  43 //
  44 // The denormal mode here should match what is reported by the OpenCL runtime
  45 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
  46 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
  47 //
  48 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
  49 // precision, and leaves single precision to flush all and does not report
  50 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
  51 // CL_FP_DENORM for both.
  52 //
  53 // FIXME: It seems some instructions do not support single precision denormals
  54 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
  55 // and sin_f32, cos_f32 on most parts).
  56
  57 // We want to use these instructions, and using fp32 denormals also causes
  58 // instructions to run at the double precision rate for the device so it's
  59 // probably best to just report no single precision denormals.
  60 static uint32_t getFPMode(const MachineFunction &F) {
  61   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
  62   // TODO: Is there any real use for the flush in only / flush out only modes?
  63
  64   uint32_t FP32Denormals =
  65     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  66
  67   uint32_t FP64Denormals =
  68     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  69
  70   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
  71          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
  72          FP_DENORM_MODE_SP(FP32Denormals) |
  73          FP_DENORM_MODE_DP(FP64Denormals);
  74 }
  75
  76 static AsmPrinter *
  77 createAMDGPUAsmPrinterPass(TargetMachine &tm,
  78                            std::unique_ptr<MCStreamer> &&Streamer) {
  79   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
  80 }
  81
  82 extern "C" void LLVMInitializeR600AsmPrinter() {
  83   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  84   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
  85 }
  86
  87 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
  88                                    std::unique_ptr<MCStreamer> Streamer)
  89     : AsmPrinter(TM, std::move(Streamer)) {}
  90
  91 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
  92
  93   // This label is used to mark the end of the .text section.
  94   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
  95   OutStreamer.SwitchSection(TLOF.getTextSection());
  96   MCSymbol *EndOfTextLabel =
  97       OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
  98   OutStreamer.EmitLabel(EndOfTextLabel);
  99 }
 100
 101 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 102
 103   // The starting address of all shader programs must be 256 bytes aligned.
 104   MF.setAlignment(8);
 105
 106   SetupMachineFunction(MF);
 107
 108   MCContext &Context = getObjFileLowering().getContext();
 109   const MCSectionELF *ConfigSection =
 110       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
 111   OutStreamer.SwitchSection(ConfigSection);
 112
 113   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 114   SIProgramInfo KernelInfo;
 115   if (STM.isAmdHsaOS()) {
 116     getSIProgramInfo(KernelInfo, MF);
 117     EmitAmdKernelCodeT(MF, KernelInfo);
 118     OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
 119   } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 120     getSIProgramInfo(KernelInfo, MF);
 121     EmitProgramInfoSI(MF, KernelInfo);
 122   } else {
 123     EmitProgramInfoR600(MF);
 124   }
 125
 126   DisasmLines.clear();
 127   HexLines.clear();
 128   DisasmLineMaxLen = 0;
 129
 130   EmitFunctionBody();
 131
 132   if (isVerbose()) {
 133     const MCSectionELF *CommentSection =
 134         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
 135     OutStreamer.SwitchSection(CommentSection);
 136
 137     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 138       OutStreamer.emitRawComment(" Kernel info:", false);
 139       OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
 140                                  false);
 141       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
 142                                  false);
 143       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
 144                                  false);
 145       OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
 146                                  false);
 147       OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
 148                                  false);
 149       OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
 150                                  false);
 151     } else {
 152       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 153       OutStreamer.emitRawComment(
 154         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 155     }
 156   }
 157
 158   if (STM.dumpCode()) {
 159
 160     OutStreamer.SwitchSection(
 161         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
 162
 163     for (size_t i = 0; i < DisasmLines.size(); ++i) {
 164       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 165       Comment += " ; " + HexLines[i] + "\n";
 166
 167       OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 168       OutStreamer.EmitBytes(StringRef(Comment));
 169     }
 170   }
 171
 172   return false;
 173 }
 174
 175 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
 176   unsigned MaxGPR = 0;
 177   bool killPixel = false;
 178   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 179   const R600RegisterInfo *RI =
 180       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
 181   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 182
 183   for (const MachineBasicBlock &MBB : MF) {
 184     for (const MachineInstr &MI : MBB) {
 185       if (MI.getOpcode() == AMDGPU::KILLGT)
 186         killPixel = true;
 187       unsigned numOperands = MI.getNumOperands();
 188       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 189         const MachineOperand &MO = MI.getOperand(op_idx);
 190         if (!MO.isReg())
 191           continue;
 192         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 193
 194         // Register with value > 127 aren't GPR
 195         if (HWReg > 127)
 196           continue;
 197         MaxGPR = std::max(MaxGPR, HWReg);
 198       }
 199     }
 200   }
 201
 202   unsigned RsrcReg;
 203   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 204     // Evergreen / Northern Islands
 205     switch (MFI->getShaderType()) {
 206     default: // Fall through
 207     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 208     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 209     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 210     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 211     }
 212   } else {
 213     // R600 / R700
 214     switch (MFI->getShaderType()) {
 215     default: // Fall through
 216     case ShaderType::GEOMETRY: // Fall through
 217     case ShaderType::COMPUTE:  // Fall through
 218     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 219     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 220     }
 221   }
 222
 223   OutStreamer.EmitIntValue(RsrcReg, 4);
 224   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 225                            S_STACK_SIZE(MFI->StackSize), 4);
 226   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 227   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 228
 229   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 230     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 231     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 232   }
 233 }
 234
 235 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 236                                         const MachineFunction &MF) const {
 237   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 238   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 239   uint64_t CodeSize = 0;
 240   unsigned MaxSGPR = 0;
 241   unsigned MaxVGPR = 0;
 242   bool VCCUsed = false;
 243   bool FlatUsed = false;
 244   const SIRegisterInfo *RI =
 245       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
 246
 247   for (const MachineBasicBlock &MBB : MF) {
 248     for (const MachineInstr &MI : MBB) {
 249       // TODO: CodeSize should account for multiple functions.
 250       CodeSize += MI.getDesc().Size;
 251
 252       unsigned numOperands = MI.getNumOperands();
 253       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 254         const MachineOperand &MO = MI.getOperand(op_idx);
 255         unsigned width = 0;
 256         bool isSGPR = false;
 257
 258         if (!MO.isReg()) {
 259           continue;
 260         }
 261         unsigned reg = MO.getReg();
 262         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
 263             reg == AMDGPU::VCC_HI) {
 264           VCCUsed = true;
 265           continue;
 266         } else if (reg == AMDGPU::FLAT_SCR ||
 267                    reg == AMDGPU::FLAT_SCR_LO ||
 268                    reg == AMDGPU::FLAT_SCR_HI) {
 269           FlatUsed = true;
 270           continue;
 271         }
 272
 273         switch (reg) {
 274         default: break;
 275         case AMDGPU::SCC:
 276         case AMDGPU::EXEC:
 277         case AMDGPU::M0:
 278           continue;
 279         }
 280
 281         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 282           isSGPR = true;
 283           width = 1;
 284         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
 285           isSGPR = false;
 286           width = 1;
 287         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 288           isSGPR = true;
 289           width = 2;
 290         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 291           isSGPR = false;
 292           width = 2;
 293         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 294           isSGPR = false;
 295           width = 3;
 296         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 297           isSGPR = true;
 298           width = 4;
 299         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 300           isSGPR = false;
 301           width = 4;
 302         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 303           isSGPR = true;
 304           width = 8;
 305         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 306           isSGPR = false;
 307           width = 8;
 308         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 309           isSGPR = true;
 310           width = 16;
 311         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 312           isSGPR = false;
 313           width = 16;
 314         } else {
 315           llvm_unreachable("Unknown register class");
 316         }
 317         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 318         unsigned maxUsed = hwReg + width - 1;
 319         if (isSGPR) {
 320           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 321         } else {
 322           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 323         }
 324       }
 325     }
 326   }
 327
 328   if (VCCUsed)
 329     MaxSGPR += 2;
 330
 331   if (FlatUsed)
 332     MaxSGPR += 2;
 333
 334   // We found the maximum register index. They start at 0, so add one to get the
 335   // number of registers.
 336   ProgInfo.NumVGPR = MaxVGPR + 1;
 337   ProgInfo.NumSGPR = MaxSGPR + 1;
 338
 339   if (STM.hasSGPRInitBug()) {
 340     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG)
 341       llvm_unreachable("Too many SGPRs used with the SGPR init bug");
 342
 343     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
 344   }
 345
 346   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
 347   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
 348   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
 349   // register.
 350   ProgInfo.FloatMode = getFPMode(MF);
 351
 352   // XXX: Not quite sure what this does, but sc seems to unset this.
 353   ProgInfo.IEEEMode = 0;
 354
 355   // Do not clamp NAN to 0.
 356   ProgInfo.DX10Clamp = 0;
 357
 358   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
 359   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
 360
 361   ProgInfo.FlatUsed = FlatUsed;
 362   ProgInfo.VCCUsed = VCCUsed;
 363   ProgInfo.CodeLen = CodeSize;
 364
 365   unsigned LDSAlignShift;
 366   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 367     // LDS is allocated in 64 dword blocks.
 368     LDSAlignShift = 8;
 369   } else {
 370     // LDS is allocated in 128 dword blocks.
 371     LDSAlignShift = 9;
 372   }
 373
 374   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
 375                           MFI->getMaximumWorkGroupSize(MF);
 376
 377   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
 378   ProgInfo.LDSBlocks =
 379      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 380
 381   // Scratch is allocated in 256 dword blocks.
 382   unsigned ScratchAlignShift = 10;
 383   // We need to program the hardware with the amount of scratch memory that
 384   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
 385   // scratch memory used per thread.
 386   ProgInfo.ScratchBlocks =
 387     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
 388                        1 << ScratchAlignShift) >> ScratchAlignShift;
 389
 390   ProgInfo.ComputePGMRSrc1 =
 391       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
 392       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
 393       S_00B848_PRIORITY(ProgInfo.Priority) |
 394       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
 395       S_00B848_PRIV(ProgInfo.Priv) |
 396       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
 397       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
 398       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
 399
 400   ProgInfo.ComputePGMRSrc2 =
 401       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
 402       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
 403       S_00B84C_TGID_X_EN(1) |
 404       S_00B84C_TGID_Y_EN(1) |
 405       S_00B84C_TGID_Z_EN(1) |
 406       S_00B84C_TG_SIZE_EN(1) |
 407       S_00B84C_TIDIG_COMP_CNT(2) |
 408       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
 409 }
 410
 411 static unsigned getRsrcReg(unsigned ShaderType) {
 412   switch (ShaderType) {
 413   default: // Fall through
 414   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
 415   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
 416   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
 417   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
 418   }
 419 }
 420
 421 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
 422                                          const SIProgramInfo &KernelInfo) {
 423   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 424   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 425   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
 426
 427   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 428     OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
 429
 430     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
 431
 432     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 433     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
 434
 435     OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
 436     OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 437
 438     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
 439     // 0" comment but I don't see a corresponding field in the register spec.
 440   } else {
 441     OutStreamer.EmitIntValue(RsrcReg, 4);
 442     OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
 443                              S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
 444     if (STM.isVGPRSpillingEnabled(MFI)) {
 445       OutStreamer.EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
 446       OutStreamer.EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 447     }
 448   }
 449
 450   if (MFI->getShaderType() == ShaderType::PIXEL) {
 451     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 452     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
 453     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 454     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 455   }
 456 }
 457
 458 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
 459                                         const SIProgramInfo &KernelInfo) const {
 460   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 461   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
 462   amd_kernel_code_t header;
 463
 464   memset(&header, 0, sizeof(header));
 465
 466   header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
 467   header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
 468
 469   header.struct_byte_size = sizeof(amd_kernel_code_t);
 470
 471   header.target_chip = STM.getAmdKernelCodeChipID();
 472
 473   header.kernel_code_entry_byte_offset = (1ULL << MF.getAlignment());
 474
 475   header.compute_pgm_resource_registers =
 476       KernelInfo.ComputePGMRSrc1 |
 477       (KernelInfo.ComputePGMRSrc2 << 32);
 478
 479   // Code Properties:
 480   header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
 481                            AMD_CODE_PROPERTY_IS_PTR64;
 482
 483   if (KernelInfo.FlatUsed)
 484     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
 485
 486   if (KernelInfo.ScratchBlocks)
 487     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
 488
 489   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
 490   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
 491
 492   // MFI->ABIArgOffset is the number of bytes for the kernel arguments
 493   // plus 36.  36 is the number of bytes reserved at the begining of the
 494   // input buffer to store work-group size information.
 495   // FIXME: We should be adding the size of the implicit arguments
 496   // to this value.
 497   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
 498
 499   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
 500   header.workitem_vgpr_count = KernelInfo.NumVGPR;
 501
 502   // FIXME: What values do I put for these alignments
 503   header.kernarg_segment_alignment = 0;
 504   header.group_segment_alignment = 0;
 505   header.private_segment_alignment = 0;
 506
 507   header.code_type = 1; // HSA_EXT_CODE_KERNEL
 508
 509   header.wavefront_size = STM.getWavefrontSize();
 510
 511   const MCSectionELF *VersionSection =
 512       OutContext.getELFSection(".hsa.version", ELF::SHT_PROGBITS, 0);
 513   OutStreamer.SwitchSection(VersionSection);
 514   OutStreamer.EmitBytes(Twine("HSA Code Unit:" +
 515                         Twine(header.hsail_version_major) + "." +
 516                         Twine(header.hsail_version_minor) + ":" +
 517                         "AMD:" +
 518                         Twine(header.amd_code_version_major) + "." +
 519                         Twine(header.amd_code_version_minor) +  ":" +
 520                         "GFX8.1:0").str());
 521
 522   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 523
 524   if (isVerbose()) {
 525     OutStreamer.emitRawComment("amd_code_version_major = " +
 526                                Twine(header.amd_code_version_major), false);
 527     OutStreamer.emitRawComment("amd_code_version_minor = " +
 528                                Twine(header.amd_code_version_minor), false);
 529     OutStreamer.emitRawComment("struct_byte_size = " +
 530                                Twine(header.struct_byte_size), false);
 531     OutStreamer.emitRawComment("target_chip = " +
 532                                Twine(header.target_chip), false);
 533     OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
 534                                Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
 535     OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
 536                                Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
 537     OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
 538       Twine((bool)(header.code_properties &
 539                    AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
 540     OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
 541       Twine((bool)(header.code_properties &
 542                    AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
 543     OutStreamer.emitRawComment("private_element_size = 2 ", false);
 544     OutStreamer.emitRawComment("is_ptr64 = " +
 545         Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
 546     OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
 547                                Twine(header.workitem_private_segment_byte_size),
 548                                false);
 549     OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
 550                                Twine(header.workgroup_group_segment_byte_size),
 551                                false);
 552     OutStreamer.emitRawComment("gds_segment_byte_size = " +
 553                                Twine(header.gds_segment_byte_size), false);
 554     OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
 555                                Twine(header.kernarg_segment_byte_size), false);
 556     OutStreamer.emitRawComment("wavefront_sgpr_count = " +
 557                                Twine(header.wavefront_sgpr_count), false);
 558     OutStreamer.emitRawComment("workitem_vgpr_count = " +
 559                                Twine(header.workitem_vgpr_count), false);
 560     OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
 561     OutStreamer.emitRawComment("wavefront_size = " +
 562                                Twine((int)header.wavefront_size), false);
 563     OutStreamer.emitRawComment("optimization_level = " +
 564                                Twine(header.optimization_level), false);
 565     OutStreamer.emitRawComment("hsail_profile = " +
 566                                Twine(header.hsail_profile), false);
 567     OutStreamer.emitRawComment("hsail_machine_model = " +
 568                                Twine(header.hsail_machine_model), false);
 569     OutStreamer.emitRawComment("hsail_version_major = " +
 570                                Twine(header.hsail_version_major), false);
 571     OutStreamer.emitRawComment("hsail_version_minor = " +
 572                                Twine(header.hsail_version_minor), false);
 573   }
 574
 575   OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));
 576 }