lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19 #include "AMDGPUAsmPrinter.h"
  20 #include "AMDGPU.h"
  21 #include "AMDKernelCodeT.h"
  22 #include "AMDGPUSubtarget.h"
  23 #include "R600Defines.h"
  24 #include "R600MachineFunctionInfo.h"
  25 #include "R600RegisterInfo.h"
  26 #include "SIDefines.h"
  27 #include "SIMachineFunctionInfo.h"
  28 #include "SIRegisterInfo.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/MC/MCContext.h"
  31 #include "llvm/MC/MCSectionELF.h"
  32 #include "llvm/MC/MCStreamer.h"
  33 #include "llvm/Support/ELF.h"
  34 #include "llvm/Support/MathExtras.h"
  35 #include "llvm/Support/TargetRegistry.h"
  36 #include "llvm/Target/TargetLoweringObjectFile.h"
  37
  38 using namespace llvm;
  39
  40 // TODO: This should get the default rounding mode from the kernel. We just set
  41 // the default here, but this could change if the OpenCL rounding mode pragmas
  42 // are used.
  43 //
  44 // The denormal mode here should match what is reported by the OpenCL runtime
  45 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
  46 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
  47 //
  48 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
  49 // precision, and leaves single precision to flush all and does not report
  50 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
  51 // CL_FP_DENORM for both.
  52 //
  53 // FIXME: It seems some instructions do not support single precision denormals
  54 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
  55 // and sin_f32, cos_f32 on most parts).
  56
  57 // We want to use these instructions, and using fp32 denormals also causes
  58 // instructions to run at the double precision rate for the device so it's
  59 // probably best to just report no single precision denormals.
  60 static uint32_t getFPMode(const MachineFunction &F) {
  61   const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
  62   // TODO: Is there any real use for the flush in only / flush out only modes?
  63
  64   uint32_t FP32Denormals =
  65     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  66
  67   uint32_t FP64Denormals =
  68     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  69
  70   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
  71          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
  72          FP_DENORM_MODE_SP(FP32Denormals) |
  73          FP_DENORM_MODE_DP(FP64Denormals);
  74 }
  75
  76 static AsmPrinter *
  77 createAMDGPUAsmPrinterPass(TargetMachine &tm,
  78                            std::unique_ptr<MCStreamer> &&Streamer) {
  79   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
  80 }
  81
  82 extern "C" void LLVMInitializeR600AsmPrinter() {
  83   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  84   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
  85 }
  86
  87 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
  88                                    std::unique_ptr<MCStreamer> Streamer)
  89     : AsmPrinter(TM, std::move(Streamer)) {
  90   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
  91 }
  92
  93 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
  94
  95   // This label is used to mark the end of the .text section.
  96   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
  97   OutStreamer.SwitchSection(TLOF.getTextSection());
  98   MCSymbol *EndOfTextLabel =
  99       OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
 100   OutStreamer.EmitLabel(EndOfTextLabel);
 101 }
 102
 103 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 104
 105   // The starting address of all shader programs must be 256 bytes aligned.
 106   MF.setAlignment(8);
 107
 108   SetupMachineFunction(MF);
 109
 110   EmitFunctionHeader();
 111
 112   MCContext &Context = getObjFileLowering().getContext();
 113   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
 114                                               ELF::SHT_PROGBITS, 0,
 115                                               SectionKind::getReadOnly());
 116   OutStreamer.SwitchSection(ConfigSection);
 117
 118   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 119   SIProgramInfo KernelInfo;
 120   if (STM.isAmdHsaOS()) {
 121     OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 122     getSIProgramInfo(KernelInfo, MF);
 123     EmitAmdKernelCodeT(MF, KernelInfo);
 124     OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
 125   } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 126     getSIProgramInfo(KernelInfo, MF);
 127     EmitProgramInfoSI(MF, KernelInfo);
 128   } else {
 129     EmitProgramInfoR600(MF);
 130   }
 131
 132   DisasmLines.clear();
 133   HexLines.clear();
 134   DisasmLineMaxLen = 0;
 135
 136   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
 137   EmitFunctionBody();
 138
 139   if (isVerbose()) {
 140     const MCSectionELF *CommentSection
 141       = Context.getELFSection(".AMDGPU.csdata",
 142                               ELF::SHT_PROGBITS, 0,
 143                               SectionKind::getReadOnly());
 144     OutStreamer.SwitchSection(CommentSection);
 145
 146     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
 147       OutStreamer.emitRawComment(" Kernel info:", false);
 148       OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
 149                                  false);
 150       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
 151                                  false);
 152       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
 153                                  false);
 154       OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
 155                                  false);
 156       OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
 157                                  false);
 158       OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
 159                                  false);
 160     } else {
 161       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 162       OutStreamer.emitRawComment(
 163         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 164     }
 165   }
 166
 167   if (STM.dumpCode() && DisasmEnabled) {
 168
 169     OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 170                                                 ELF::SHT_NOTE, 0,
 171                                                 SectionKind::getReadOnly()));
 172
 173     for (size_t i = 0; i < DisasmLines.size(); ++i) {
 174       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 175       Comment += " ; " + HexLines[i] + "\n";
 176
 177       OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 178       OutStreamer.EmitBytes(StringRef(Comment));
 179     }
 180   }
 181
 182   return false;
 183 }
 184
 185 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
 186   unsigned MaxGPR = 0;
 187   bool killPixel = false;
 188   const R600RegisterInfo *RI = static_cast<const R600RegisterInfo *>(
 189       TM.getSubtargetImpl()->getRegisterInfo());
 190   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 191   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 192
 193   for (const MachineBasicBlock &MBB : MF) {
 194     for (const MachineInstr &MI : MBB) {
 195       if (MI.getOpcode() == AMDGPU::KILLGT)
 196         killPixel = true;
 197       unsigned numOperands = MI.getNumOperands();
 198       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 199         const MachineOperand &MO = MI.getOperand(op_idx);
 200         if (!MO.isReg())
 201           continue;
 202         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 203
 204         // Register with value > 127 aren't GPR
 205         if (HWReg > 127)
 206           continue;
 207         MaxGPR = std::max(MaxGPR, HWReg);
 208       }
 209     }
 210   }
 211
 212   unsigned RsrcReg;
 213   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 214     // Evergreen / Northern Islands
 215     switch (MFI->getShaderType()) {
 216     default: // Fall through
 217     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 218     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 219     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 220     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 221     }
 222   } else {
 223     // R600 / R700
 224     switch (MFI->getShaderType()) {
 225     default: // Fall through
 226     case ShaderType::GEOMETRY: // Fall through
 227     case ShaderType::COMPUTE:  // Fall through
 228     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 229     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 230     }
 231   }
 232
 233   OutStreamer.EmitIntValue(RsrcReg, 4);
 234   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 235                            S_STACK_SIZE(MFI->StackSize), 4);
 236   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 237   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 238
 239   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 240     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 241     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 242   }
 243 }
 244
 245 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 246                                         const MachineFunction &MF) const {
 247   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 248   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 249   uint64_t CodeSize = 0;
 250   unsigned MaxSGPR = 0;
 251   unsigned MaxVGPR = 0;
 252   bool VCCUsed = false;
 253   bool FlatUsed = false;
 254   const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
 255       TM.getSubtargetImpl()->getRegisterInfo());
 256
 257   for (const MachineBasicBlock &MBB : MF) {
 258     for (const MachineInstr &MI : MBB) {
 259       // TODO: CodeSize should account for multiple functions.
 260       CodeSize += MI.getDesc().Size;
 261
 262       unsigned numOperands = MI.getNumOperands();
 263       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 264         const MachineOperand &MO = MI.getOperand(op_idx);
 265         unsigned width = 0;
 266         bool isSGPR = false;
 267
 268         if (!MO.isReg()) {
 269           continue;
 270         }
 271         unsigned reg = MO.getReg();
 272         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
 273             reg == AMDGPU::VCC_HI) {
 274           VCCUsed = true;
 275           continue;
 276         } else if (reg == AMDGPU::FLAT_SCR ||
 277                    reg == AMDGPU::FLAT_SCR_LO ||
 278                    reg == AMDGPU::FLAT_SCR_HI) {
 279           FlatUsed = true;
 280           continue;
 281         }
 282
 283         switch (reg) {
 284         default: break;
 285         case AMDGPU::SCC:
 286         case AMDGPU::EXEC:
 287         case AMDGPU::M0:
 288           continue;
 289         }
 290
 291         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 292           isSGPR = true;
 293           width = 1;
 294         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
 295           isSGPR = false;
 296           width = 1;
 297         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 298           isSGPR = true;
 299           width = 2;
 300         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 301           isSGPR = false;
 302           width = 2;
 303         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 304           isSGPR = false;
 305           width = 3;
 306         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 307           isSGPR = true;
 308           width = 4;
 309         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 310           isSGPR = false;
 311           width = 4;
 312         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 313           isSGPR = true;
 314           width = 8;
 315         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 316           isSGPR = false;
 317           width = 8;
 318         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 319           isSGPR = true;
 320           width = 16;
 321         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 322           isSGPR = false;
 323           width = 16;
 324         } else {
 325           llvm_unreachable("Unknown register class");
 326         }
 327         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 328         unsigned maxUsed = hwReg + width - 1;
 329         if (isSGPR) {
 330           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 331         } else {
 332           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 333         }
 334       }
 335     }
 336   }
 337
 338   if (VCCUsed)
 339     MaxSGPR += 2;
 340
 341   if (FlatUsed)
 342     MaxSGPR += 2;
 343
 344   // We found the maximum register index. They start at 0, so add one to get the
 345   // number of registers.
 346   ProgInfo.NumVGPR = MaxVGPR + 1;
 347   ProgInfo.NumSGPR = MaxSGPR + 1;
 348
 349   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
 350   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
 351   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
 352   // register.
 353   ProgInfo.FloatMode = getFPMode(MF);
 354
 355   // XXX: Not quite sure what this does, but sc seems to unset this.
 356   ProgInfo.IEEEMode = 0;
 357
 358   // Do not clamp NAN to 0.
 359   ProgInfo.DX10Clamp = 0;
 360
 361   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
 362   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
 363
 364   ProgInfo.FlatUsed = FlatUsed;
 365   ProgInfo.VCCUsed = VCCUsed;
 366   ProgInfo.CodeLen = CodeSize;
 367
 368   unsigned LDSAlignShift;
 369   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 370     // LDS is allocated in 64 dword blocks.
 371     LDSAlignShift = 8;
 372   } else {
 373     // LDS is allocated in 128 dword blocks.
 374     LDSAlignShift = 9;
 375   }
 376
 377   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
 378                           MFI->getMaximumWorkGroupSize(MF);
 379
 380   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
 381   ProgInfo.LDSBlocks =
 382      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 383
 384   // Scratch is allocated in 256 dword blocks.
 385   unsigned ScratchAlignShift = 10;
 386   // We need to program the hardware with the amount of scratch memory that
 387   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
 388   // scratch memory used per thread.
 389   ProgInfo.ScratchBlocks =
 390     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
 391                        1 << ScratchAlignShift) >> ScratchAlignShift;
 392
 393   ProgInfo.ComputePGMRSrc1 =
 394       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
 395       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
 396       S_00B848_PRIORITY(ProgInfo.Priority) |
 397       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
 398       S_00B848_PRIV(ProgInfo.Priv) |
 399       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
 400       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
 401       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
 402
 403   ProgInfo.ComputePGMRSrc2 =
 404       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
 405       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
 406       S_00B84C_TGID_X_EN(1) |
 407       S_00B84C_TGID_Y_EN(1) |
 408       S_00B84C_TGID_Z_EN(1) |
 409       S_00B84C_TG_SIZE_EN(1) |
 410       S_00B84C_TIDIG_COMP_CNT(2) |
 411       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
 412 }
 413
 414 static unsigned getRsrcReg(unsigned ShaderType) {
 415   switch (ShaderType) {
 416   default: // Fall through
 417   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
 418   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
 419   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
 420   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
 421   }
 422 }
 423
 424 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
 425                                          const SIProgramInfo &KernelInfo) {
 426   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 427   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 428   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
 429
 430   if (MFI->getShaderType() == ShaderType::COMPUTE) {
 431     OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
 432
 433     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
 434
 435     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 436     OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
 437
 438     OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
 439     OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 440
 441     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
 442     // 0" comment but I don't see a corresponding field in the register spec.
 443   } else {
 444     OutStreamer.EmitIntValue(RsrcReg, 4);
 445     OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
 446                              S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
 447     if (STM.isVGPRSpillingEnabled(MFI)) {
 448       OutStreamer.EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
 449       OutStreamer.EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
 450     }
 451   }
 452
 453   if (MFI->getShaderType() == ShaderType::PIXEL) {
 454     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 455     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
 456     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 457     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 458   }
 459 }
 460
 461 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
 462                                         const SIProgramInfo &KernelInfo) const {
 463   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 464   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 465   amd_kernel_code_t header;
 466
 467   memset(&header, 0, sizeof(header));
 468
 469   header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
 470   header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
 471
 472   header.struct_byte_size = sizeof(amd_kernel_code_t);
 473
 474   header.target_chip = STM.getAmdKernelCodeChipID();
 475
 476   header.kernel_code_entry_byte_offset = (1ULL << MF.getAlignment());
 477
 478   header.compute_pgm_resource_registers =
 479       KernelInfo.ComputePGMRSrc1 |
 480       (KernelInfo.ComputePGMRSrc2 << 32);
 481
 482   // Code Properties:
 483   header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
 484                            AMD_CODE_PROPERTY_IS_PTR64;
 485
 486   if (KernelInfo.FlatUsed)
 487     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
 488
 489   if (KernelInfo.ScratchBlocks)
 490     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
 491
 492   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
 493   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
 494
 495   // MFI->ABIArgOffset is the number of bytes for the kernel arguments
 496   // plus 36.  36 is the number of bytes reserved at the begining of the
 497   // input buffer to store work-group size information.
 498   // FIXME: We should be adding the size of the implicit arguments
 499   // to this value.
 500   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
 501
 502   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
 503   header.workitem_vgpr_count = KernelInfo.NumVGPR;
 504
 505   // FIXME: What values do I put for these alignments
 506   header.kernarg_segment_alignment = 0;
 507   header.group_segment_alignment = 0;
 508   header.private_segment_alignment = 0;
 509
 510   header.code_type = 1; // HSA_EXT_CODE_KERNEL
 511
 512   header.wavefront_size = STM.getWavefrontSize();
 513
 514   if (isVerbose()) {
 515     OutStreamer.emitRawComment("amd_code_version_major = " +
 516                                Twine(header.amd_code_version_major), false);
 517     OutStreamer.emitRawComment("amd_code_version_minor = " +
 518                                Twine(header.amd_code_version_minor), false);
 519     OutStreamer.emitRawComment("struct_byte_size = " +
 520                                Twine(header.struct_byte_size), false);
 521     OutStreamer.emitRawComment("target_chip = " +
 522                                Twine(header.target_chip), false);
 523     OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
 524                                Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
 525     OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
 526                                Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
 527     OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
 528       Twine((bool)(header.code_properties &
 529                    AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
 530     OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
 531       Twine((bool)(header.code_properties &
 532                    AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
 533     OutStreamer.emitRawComment("private_element_size = 2 ", false);
 534     OutStreamer.emitRawComment("is_ptr64 = " +
 535         Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
 536     OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
 537                                Twine(header.workitem_private_segment_byte_size),
 538                                false);
 539     OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
 540                                Twine(header.workgroup_group_segment_byte_size),
 541                                false);
 542     OutStreamer.emitRawComment("gds_segment_byte_size = " +
 543                                Twine(header.gds_segment_byte_size), false);
 544     OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
 545                                Twine(header.kernarg_segment_byte_size), false);
 546     OutStreamer.emitRawComment("wavefront_sgpr_count = " +
 547                                Twine(header.wavefront_sgpr_count), false);
 548     OutStreamer.emitRawComment("workitem_vgpr_count = " +
 549                                Twine(header.workitem_vgpr_count), false);
 550     OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
 551     OutStreamer.emitRawComment("wavefront_size = " +
 552                                Twine((int)header.wavefront_size), false);
 553     OutStreamer.emitRawComment("optimization_level = " +
 554                                Twine(header.optimization_level), false);
 555     OutStreamer.emitRawComment("hsail_profile = " +
 556                                Twine(header.hsail_profile), false);
 557     OutStreamer.emitRawComment("hsail_machine_model = " +
 558                                Twine(header.hsail_machine_model), false);
 559     OutStreamer.emitRawComment("hsail_version_major = " +
 560                                Twine(header.hsail_version_major), false);
 561     OutStreamer.emitRawComment("hsail_version_minor = " +
 562                                Twine(header.hsail_version_minor), false);
 563   }
 564
 565   OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));
 566 }