lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19
  20 #include "AMDGPUAsmPrinter.h"
  21 #include "AMDGPU.h"
  22 #include "R600Defines.h"
  23 #include "R600MachineFunctionInfo.h"
  24 #include "R600RegisterInfo.h"
  25 #include "SIDefines.h"
  26 #include "SIMachineFunctionInfo.h"
  27 #include "SIRegisterInfo.h"
  28 #include "llvm/MC/MCContext.h"
  29 #include "llvm/MC/MCSectionELF.h"
  30 #include "llvm/MC/MCStreamer.h"
  31 #include "llvm/Support/ELF.h"
  32 #include "llvm/Support/MathExtras.h"
  33 #include "llvm/Support/TargetRegistry.h"
  34 #include "llvm/Target/TargetLoweringObjectFile.h"
  35
  36 using namespace llvm;
  37
  38
  39 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
  40                                               MCStreamer &Streamer) {
  41   return new AMDGPUAsmPrinter(tm, Streamer);
  42 }
  43
  44 extern "C" void LLVMInitializeR600AsmPrinter() {
  45   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  46 }
  47
  48 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
  49     : AsmPrinter(TM, Streamer) {
  50   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode() &&
  51                   ! Streamer.hasRawTextSupport();
  52 }
  53
  54 /// We need to override this function so we can avoid
  55 /// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
  56 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
  57   SetupMachineFunction(MF);
  58
  59   if (OutStreamer.hasRawTextSupport()) {
  60     OutStreamer.EmitRawText("@" + MF.getName() + ":");
  61   }
  62
  63   MCContext &Context = getObjFileLowering().getContext();
  64   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
  65                                               ELF::SHT_PROGBITS, 0,
  66                                               SectionKind::getReadOnly());
  67   OutStreamer.SwitchSection(ConfigSection);
  68
  69   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
  70   SIProgramInfo KernelInfo;
  71   if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  72     findNumUsedRegistersSI(MF, KernelInfo.NumSGPR, KernelInfo.NumVGPR);
  73     EmitProgramInfoSI(MF, KernelInfo);
  74   } else {
  75     EmitProgramInfoR600(MF);
  76   }
  77
  78   DisasmLines.clear();
  79   HexLines.clear();
  80   DisasmLineMaxLen = 0;
  81
  82   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
  83   EmitFunctionBody();
  84
  85   if (isVerbose() && OutStreamer.hasRawTextSupport()) {
  86     const MCSectionELF *CommentSection
  87       = Context.getELFSection(".AMDGPU.csdata",
  88                               ELF::SHT_PROGBITS, 0,
  89                               SectionKind::getReadOnly());
  90     OutStreamer.SwitchSection(CommentSection);
  91
  92     if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  93       OutStreamer.emitRawComment("Kernel info:", false);
  94       OutStreamer.emitRawComment("NumSgprs: " + Twine(KernelInfo.NumSGPR),
  95                                  false);
  96       OutStreamer.emitRawComment("NumVgprs: " + Twine(KernelInfo.NumVGPR),
  97                                  false);
  98     } else {
  99       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 100       OutStreamer.EmitRawText(
 101         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 102     }
 103   }
 104
 105   if (STM.dumpCode()) {
 106 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 107     MF.dump();
 108 #endif
 109
 110     if (DisasmEnabled) {
 111       OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 112                                                   ELF::SHT_NOTE, 0,
 113                                                   SectionKind::getReadOnly()));
 114
 115       for (size_t i = 0; i < DisasmLines.size(); ++i) {
 116         std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 117         Comment += " ; " + HexLines[i] + "\n";
 118
 119         OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 120         OutStreamer.EmitBytes(StringRef(Comment));
 121       }
 122     }
 123   }
 124
 125   return false;
 126 }
 127
 128 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
 129   unsigned MaxGPR = 0;
 130   bool killPixel = false;
 131   const R600RegisterInfo * RI =
 132                 static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
 133   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 134   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 135
 136   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 137                                                   BB != BB_E; ++BB) {
 138     MachineBasicBlock &MBB = *BB;
 139     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 140                                                     I != E; ++I) {
 141       MachineInstr &MI = *I;
 142       if (MI.getOpcode() == AMDGPU::KILLGT)
 143         killPixel = true;
 144       unsigned numOperands = MI.getNumOperands();
 145       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 146         MachineOperand & MO = MI.getOperand(op_idx);
 147         if (!MO.isReg())
 148           continue;
 149         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 150
 151         // Register with value > 127 aren't GPR
 152         if (HWReg > 127)
 153           continue;
 154         MaxGPR = std::max(MaxGPR, HWReg);
 155       }
 156     }
 157   }
 158
 159   unsigned RsrcReg;
 160   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 161     // Evergreen / Northern Islands
 162     switch (MFI->ShaderType) {
 163     default: // Fall through
 164     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 165     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 166     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 167     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 168     }
 169   } else {
 170     // R600 / R700
 171     switch (MFI->ShaderType) {
 172     default: // Fall through
 173     case ShaderType::GEOMETRY: // Fall through
 174     case ShaderType::COMPUTE:  // Fall through
 175     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 176     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 177     }
 178   }
 179
 180   OutStreamer.EmitIntValue(RsrcReg, 4);
 181   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 182                            S_STACK_SIZE(MFI->StackSize), 4);
 183   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 184   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 185
 186   if (MFI->ShaderType == ShaderType::COMPUTE) {
 187     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 188     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 189   }
 190 }
 191
 192 void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
 193                                               unsigned &NumSGPR,
 194                                               unsigned &NumVGPR) const {
 195   unsigned MaxSGPR = 0;
 196   unsigned MaxVGPR = 0;
 197   bool VCCUsed = false;
 198   const SIRegisterInfo * RI =
 199                 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
 200
 201   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 202                                                   BB != BB_E; ++BB) {
 203     MachineBasicBlock &MBB = *BB;
 204     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 205                                                     I != E; ++I) {
 206       MachineInstr &MI = *I;
 207
 208       unsigned numOperands = MI.getNumOperands();
 209       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 210         MachineOperand &MO = MI.getOperand(op_idx);
 211         unsigned width = 0;
 212         bool isSGPR = false;
 213
 214         if (!MO.isReg()) {
 215           continue;
 216         }
 217         unsigned reg = MO.getReg();
 218         if (reg == AMDGPU::VCC) {
 219           VCCUsed = true;
 220           continue;
 221         }
 222
 223         switch (reg) {
 224         default: break;
 225         case AMDGPU::SCC:
 226         case AMDGPU::EXEC:
 227         case AMDGPU::M0:
 228           continue;
 229         }
 230
 231         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 232           isSGPR = true;
 233           width = 1;
 234         } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
 235           isSGPR = false;
 236           width = 1;
 237         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 238           isSGPR = true;
 239           width = 2;
 240         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 241           isSGPR = false;
 242           width = 2;
 243         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 244           isSGPR = false;
 245           width = 3;
 246         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 247           isSGPR = true;
 248           width = 4;
 249         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 250           isSGPR = false;
 251           width = 4;
 252         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 253           isSGPR = true;
 254           width = 8;
 255         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 256           isSGPR = false;
 257           width = 8;
 258         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 259           isSGPR = true;
 260           width = 16;
 261         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 262           isSGPR = false;
 263           width = 16;
 264         } else {
 265           llvm_unreachable("Unknown register class");
 266         }
 267         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 268         unsigned maxUsed = hwReg + width - 1;
 269         if (isSGPR) {
 270           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 271         } else {
 272           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 273         }
 274       }
 275     }
 276   }
 277
 278   if (VCCUsed)
 279     MaxSGPR += 2;
 280
 281   NumSGPR = MaxSGPR;
 282   NumVGPR = MaxVGPR;
 283 }
 284
 285 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &Out,
 286                                         MachineFunction &MF) const {
 287   findNumUsedRegistersSI(MF, Out.NumSGPR, Out.NumVGPR);
 288 }
 289
 290 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
 291                                          const SIProgramInfo &KernelInfo) {
 292   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 293
 294   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 295   unsigned RsrcReg;
 296   switch (MFI->ShaderType) {
 297   default: // Fall through
 298   case ShaderType::COMPUTE:  RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
 299   case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
 300   case ShaderType::PIXEL:    RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
 301   case ShaderType::VERTEX:   RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
 302   }
 303
 304   OutStreamer.EmitIntValue(RsrcReg, 4);
 305   OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
 306                            S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
 307
 308   unsigned LDSAlignShift;
 309   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 310     // LDS is allocated in 64 dword blocks
 311     LDSAlignShift = 8;
 312   } else {
 313     // LDS is allocated in 128 dword blocks
 314     LDSAlignShift = 9;
 315   }
 316   unsigned LDSBlocks =
 317           RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 318
 319   if (MFI->ShaderType == ShaderType::COMPUTE) {
 320     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 321     OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
 322   }
 323   if (MFI->ShaderType == ShaderType::PIXEL) {
 324     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 325     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
 326     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 327     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 328   }
 329 }