lib/Target/R600/AMDGPU.td

   1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  24         "EnableIRStructurizer",
  25         "false",
  26         "Disable IR Structurizer">;
  27
  28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
  29         "EnablePromoteAlloca",
  30         "true",
  31         "Enable promote alloca pass">;
  32
  33 // Target features
  34
  35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  36         "EnableIfCvt",
  37         "false",
  38         "Disable the if conversion pass">;
  39
  40 def FeatureFP64 : SubtargetFeature<"fp64",
  41         "FP64",
  42         "true",
  43         "Enable double precision operations">;
  44
  45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
  46         "FP64Denormals",
  47         "true",
  48         "Enable double precision denormal handling",
  49         [FeatureFP64]>;
  50
  51 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  52         "FastFMAF32",
  53         "true",
  54         "Assuming f32 fma is at least as fast as mul + add",
  55         []>;
  56
  57 // Some instructions do not support denormals despite this flag. Using
  58 // fp32 denormals also causes instructions to run at the double
  59 // precision rate for the device.
  60 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
  61         "FP32Denormals",
  62         "true",
  63         "Enable single precision denormal handling">;
  64
  65 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  66         "Is64bit",
  67         "true",
  68         "Specify if 64-bit addressing should be used">;
  69
  70 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  71         "R600ALUInst",
  72         "false",
  73         "Older version of ALU instructions encoding">;
  74
  75 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  76         "HasVertexCache",
  77         "true",
  78         "Specify use of dedicated vertex cache">;
  79
  80 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  81         "CaymanISA",
  82         "true",
  83         "Use Cayman ISA">;
  84
  85 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  86         "CFALUBug",
  87         "true",
  88         "GPU has CF_ALU bug">;
  89
  90 // XXX - This should probably be removed once enabled by default
  91 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
  92         "EnableLoadStoreOpt",
  93         "true",
  94         "Enable SI load/store optimizer pass">;
  95
  96 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  97         "FlatAddressSpace",
  98         "true",
  99         "Support flat address space">;
 100
 101 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
 102         "EnableVGPRSpilling",
 103         "true",
 104         "Enable spilling of VGPRs to scratch memory">;
 105
 106 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 107         "SGPRInitBug",
 108         "true",
 109         "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
 110
 111 class SubtargetFeatureFetchLimit <string Value> :
 112                           SubtargetFeature <"fetch"#Value,
 113         "TexVTXClauseSize",
 114         Value,
 115         "Limit the maximum number of fetches in a clause to "#Value>;
 116
 117 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
 118 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
 119
 120 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
 121         "wavefrontsize"#Value,
 122         "WavefrontSize",
 123         !cast<string>(Value),
 124         "The number of threads per wavefront">;
 125
 126 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
 127 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
 128 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
 129
 130 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
 131         "localmemorysize"#Value,
 132         "LocalMemorySize",
 133         !cast<string>(Value),
 134         "The size of local memory in bytes">;
 135
 136 class SubtargetFeatureGeneration <string Value,
 137                                   list<SubtargetFeature> Implies> :
 138         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
 139                           Value#" GPU generation", Implies>;
 140
 141 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
 142 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
 143 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
 144
 145 def FeatureR600 : SubtargetFeatureGeneration<"R600",
 146         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
 147
 148 def FeatureR700 : SubtargetFeatureGeneration<"R700",
 149         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
 150
 151 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 152         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
 153
 154 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 155         [FeatureFetchLimit16, FeatureWavefrontSize64,
 156          FeatureLocalMemorySize32768]
 157 >;
 158
 159 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 160         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
 161          FeatureWavefrontSize64]>;
 162
 163 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 164         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 165          FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
 166
 167 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 168         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 169          FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
 170
 171 //===----------------------------------------------------------------------===//
 172
 173 def AMDGPUInstrInfo : InstrInfo {
 174   let guessInstructionProperties = 1;
 175   let noNamedPositionallyEncodedOperands = 1;
 176 }
 177
 178 def AMDGPUAsmParser : AsmParser {
 179   // Some of the R600 registers have the same name, so this crashes.
 180   // For example T0_XYZW and T0_XY both have the asm name T0.
 181   let ShouldEmitMatchRegisterName = 0;
 182 }
 183
 184 def AMDGPU : Target {
 185   // Pull in Instruction Info:
 186   let InstructionSet = AMDGPUInstrInfo;
 187   let AssemblyParsers = [AMDGPUAsmParser];
 188 }
 189
 190 // Dummy Instruction itineraries for pseudo instructions
 191 def ALU_NULL : FuncUnit;
 192 def NullALU : InstrItinClass;
 193
 194 //===----------------------------------------------------------------------===//
 195 // Predicate helper class
 196 //===----------------------------------------------------------------------===//
 197
 198 class PredicateControl {
 199   Predicate SubtargetPredicate;
 200   list<Predicate> OtherPredicates = [];
 201   list<Predicate> Predicates = !listconcat([SubtargetPredicate],
 202                                             OtherPredicates);
 203 }
 204
 205 // Include AMDGPU TD files
 206 include "R600Schedule.td"
 207 include "SISchedule.td"
 208 include "Processors.td"
 209 include "AMDGPUInstrInfo.td"
 210 include "AMDGPUIntrinsics.td"
 211 include "AMDGPURegisterInfo.td"
 212 include "AMDGPUInstructions.td"
 213 include "AMDGPUCallingConv.td"