lib/Target/R600/AMDGPU.td

   1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  24         "EnableIRStructurizer",
  25         "false",
  26         "Disable IR Structurizer">;
  27
  28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
  29         "EnablePromoteAlloca",
  30         "true",
  31         "Enable promote alloca pass">;
  32
  33 // Target features
  34
  35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  36         "EnableIfCvt",
  37         "false",
  38         "Disable the if conversion pass">;
  39
  40 def FeatureFP64 : SubtargetFeature<"fp64",
  41         "FP64",
  42         "true",
  43         "Enable double precision operations">;
  44
  45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
  46         "FP64Denormals",
  47         "true",
  48         "Enable double precision denormal handling",
  49         [FeatureFP64]>;
  50
  51 // Some instructions do not support denormals despite this flag. Using
  52 // fp32 denormals also causes instructions to run at the double
  53 // precision rate for the device.
  54 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
  55         "FP32Denormals",
  56         "true",
  57         "Enable single precision denormal handling">;
  58
  59 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  60         "Is64bit",
  61         "true",
  62         "Specify if 64-bit addressing should be used">;
  63
  64 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  65         "R600ALUInst",
  66         "false",
  67         "Older version of ALU instructions encoding">;
  68
  69 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  70         "HasVertexCache",
  71         "true",
  72         "Specify use of dedicated vertex cache">;
  73
  74 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  75         "CaymanISA",
  76         "true",
  77         "Use Cayman ISA">;
  78
  79 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  80         "CFALUBug",
  81         "true",
  82         "GPU has CF_ALU bug">;
  83
  84 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  85         "FlatAddressSpace",
  86         "true",
  87         "Support flat address space">;
  88
  89 class SubtargetFeatureFetchLimit <string Value> :
  90                           SubtargetFeature <"fetch"#Value,
  91         "TexVTXClauseSize",
  92         Value,
  93         "Limit the maximum number of fetches in a clause to "#Value>;
  94
  95 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
  96 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
  97
  98 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
  99         "wavefrontsize"#Value,
 100         "WavefrontSize",
 101         !cast<string>(Value),
 102         "The number of threads per wavefront">;
 103
 104 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
 105 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
 106 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
 107
 108 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
 109         "localmemorysize"#Value,
 110         "LocalMemorySize",
 111         !cast<string>(Value),
 112         "The size of local memory in bytes">;
 113
 114 class SubtargetFeatureGeneration <string Value,
 115                                   list<SubtargetFeature> Implies> :
 116         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
 117                           Value#" GPU generation", Implies>;
 118
 119 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
 120 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
 121 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
 122
 123 def FeatureR600 : SubtargetFeatureGeneration<"R600",
 124         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
 125
 126 def FeatureR700 : SubtargetFeatureGeneration<"R700",
 127         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
 128
 129 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 130         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
 131
 132 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 133         [FeatureFetchLimit16, FeatureWavefrontSize64,
 134          FeatureLocalMemorySize32768]
 135 >;
 136
 137 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 138         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
 139          FeatureWavefrontSize64]>;
 140
 141 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 142         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 143          FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
 144 //===----------------------------------------------------------------------===//
 145
 146 def AMDGPUInstrInfo : InstrInfo {
 147   let guessInstructionProperties = 1;
 148 }
 149
 150 def AMDGPU : Target {
 151   // Pull in Instruction Info:
 152   let InstructionSet = AMDGPUInstrInfo;
 153 }
 154
 155 // Dummy Instruction itineraries for pseudo instructions
 156 def ALU_NULL : FuncUnit;
 157 def NullALU : InstrItinClass;
 158
 159 //===----------------------------------------------------------------------===//
 160 // Predicate helper class
 161 //===----------------------------------------------------------------------===//
 162
 163 class PredicateControl {
 164   Predicate SubtargetPredicate;
 165   list<Predicate> OtherPredicates = [];
 166   list<Predicate> Predicates = !listconcat([SubtargetPredicate],
 167                                             OtherPredicates);
 168 }
 169
 170 // Include AMDGPU TD files
 171 include "R600Schedule.td"
 172 include "SISchedule.td"
 173 include "Processors.td"
 174 include "AMDGPUInstrInfo.td"
 175 include "AMDGPUIntrinsics.td"
 176 include "AMDGPURegisterInfo.td"
 177 include "AMDGPUInstructions.td"
 178 include "AMDGPUCallingConv.td"