1 //===- PowerPCRegisterInfo.cpp - PowerPC Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCRegisterInfo.h"
17 #include "PowerPCInstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "Support/CommandLine.h"
28 #include "Support/Debug.h"
29 #include "Support/STLExtras.h"
34 // Switch toggling compilation for AIX
35 extern cl::opt<bool> AIX;
38 PowerPCRegisterInfo::PowerPCRegisterInfo(bool is64b)
39 : PowerPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
41 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
42 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
43 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
44 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
45 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
46 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
47 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
48 ImmToIdxMap[PPC::ADDI] = PPC::ADD;
51 static unsigned getIdx(const TargetRegisterClass *RC) {
52 if (RC == PowerPC::GPRCRegisterClass) {
53 switch (RC->getSize()) {
54 default: assert(0 && "Invalid data size!");
60 } else if (RC == PowerPC::FPRCRegisterClass) {
61 switch (RC->getSize()) {
62 default: assert(0 && "Invalid data size!");
67 std::cerr << "Invalid register class to getIdx()!\n";
72 PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MI,
74 unsigned SrcReg, int FrameIdx) const {
75 const TargetRegisterClass *RC = getRegClass(SrcReg);
76 static const unsigned Opcode[] = {
77 PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
80 unsigned OC = Opcode[getIdx(RC)];
81 if (SrcReg == PPC::LR) {
82 BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R0);
83 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R0),FrameIdx);
85 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
86 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
91 PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 unsigned DestReg, int FrameIdx) const{
94 static const unsigned Opcode[] = {
95 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
97 const TargetRegisterClass *RC = getRegClass(DestReg);
98 unsigned OC = Opcode[getIdx(RC)];
99 if (DestReg == PPC::LR) {
100 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R0), FrameIdx);
101 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R0);
103 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
104 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
108 void PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MI,
110 unsigned DestReg, unsigned SrcReg,
111 const TargetRegisterClass *RC) const {
114 if (RC == PowerPC::GPRCRegisterClass) {
115 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
116 } else if (RC == PowerPC::FPRCRegisterClass) {
117 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
119 std::cerr << "Attempt to copy register that is not GPR or FPR";
124 //===----------------------------------------------------------------------===//
125 // Stack Frame Processing methods
126 //===----------------------------------------------------------------------===//
128 // hasFP - Return true if the specified function should have a dedicated frame
129 // pointer register. This is true if the function has variable sized allocas or
130 // if frame pointer elimination is disabled.
132 static bool hasFP(MachineFunction &MF) {
133 MachineFrameInfo *MFI = MF.getFrameInfo();
134 return MFI->hasVarSizedObjects() || MFI->getStackSize() > 32700;
137 static bool setFPFirst(MachineFunction &MF) {
138 return MF.getFrameInfo()->getStackSize() > 32700;
141 void PowerPCRegisterInfo::
142 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
143 MachineBasicBlock::iterator I) const {
145 // If we have a frame pointer, convert as follows:
146 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
147 // ADJCALLSTACKUP -> addi, r1, r1, amount
148 MachineInstr *Old = I;
149 unsigned Amount = Old->getOperand(0).getImmedValue();
151 // We need to keep the stack aligned properly. To do this, we round the
152 // amount of space needed for the outgoing arguments up to the next
153 // alignment boundary.
154 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
155 Amount = (Amount+Align-1)/Align*Align;
157 // Replace the pseudo instruction with a new instruction...
158 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
159 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
162 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
163 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
172 PowerPCRegisterInfo::
173 eliminateFrameIndex(MachineBasicBlock::iterator II) const {
175 MachineInstr &MI = *II;
176 MachineBasicBlock &MBB = *MI.getParent();
177 MachineFunction &MF = *MBB.getParent();
179 while (!MI.getOperand(i).isFrameIndex()) {
181 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
184 int FrameIndex = MI.getOperand(i).getFrameIndex();
186 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
187 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
189 // Take into account whether it's an add or mem instruction
190 unsigned OffIdx = (i == 2) ? 1 : 2;
192 // Now add the frame object offset to the offset from r1.
193 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
194 MI.getOperand(OffIdx).getImmedValue();
196 // If we're not using a Frame Pointer that has been set to the value of the
197 // SP before having the stack size subtracted from it, then add the stack size
198 // to Offset to get the correct offset.
200 Offset += MF.getFrameInfo()->getStackSize();
202 if (Offset > 32767 || Offset < -32768) {
203 // Insert a set of r0 with the full offset value before the ld, st, or add
204 MachineBasicBlock *MBB = MI.getParent();
205 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
206 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
208 // convert into indexed form of the instruction
209 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
210 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
211 unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
212 assert(NewOpcode && "No indexed form of load or store available!");
213 MI.setOpcode(NewOpcode);
214 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
215 MI.SetMachineOperandReg(2, PPC::R0);
217 MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
222 void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
223 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
224 MachineBasicBlock::iterator MBBI = MBB.begin();
225 MachineFrameInfo *MFI = MF.getFrameInfo();
228 // Get the number of bytes to allocate from the FrameInfo
229 unsigned NumBytes = MFI->getStackSize();
231 // If we have calls, we cannot use the red zone to store callee save registers
232 // and we must set up a stack frame, so calculate the necessary size here.
233 if (MFI->hasCalls()) {
234 // We reserve argument space for call sites in the function immediately on
235 // entry to the current function. This eliminates the need for add/sub
236 // brackets around call sites.
237 NumBytes += MFI->getMaxCallFrameSize();
240 // Do we need to allocate space on the stack?
241 if (NumBytes == 0) return;
243 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
244 // of the stack and round the size to a multiple of the alignment.
245 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
246 unsigned Size = getRegClass(PPC::R1)->getSize();
247 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
249 // Update frame info to pretend that this is part of the stack...
250 MFI->setStackSize(NumBytes);
252 if (setFPFirst(MF)) {
253 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
254 MBB.insert(MBBI, MI);
257 // adjust stack pointer: r1 -= numbytes
258 if (NumBytes <= 32768) {
259 unsigned StoreOpcode = is64bit ? PPC::STDU : PPC::STWU;
260 MI = BuildMI(StoreOpcode, 3).addReg(PPC::R1).addSImm(-NumBytes)
262 MBB.insert(MBBI, MI);
264 int NegNumbytes = -NumBytes;
265 unsigned StoreOpcode = is64bit ? PPC::STDUX : PPC::STWUX;
266 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
267 MBB.insert(MBBI, MI);
268 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
269 .addImm(NegNumbytes & 0xFFFF);
270 MBB.insert(MBBI, MI);
271 MI = BuildMI(StoreOpcode, 3).addReg(PPC::R1).addReg(PPC::R1)
273 MBB.insert(MBBI, MI);
276 if (hasFP(MF) && !setFPFirst(MF)) {
277 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
278 MBB.insert(MBBI, MI);
282 void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
283 MachineBasicBlock &MBB) const {
284 const MachineFrameInfo *MFI = MF.getFrameInfo();
285 MachineBasicBlock::iterator MBBI = prior(MBB.end());
287 assert(MBBI->getOpcode() == PPC::BLR &&
288 "Can only insert epilog into returning blocks");
290 // Get the number of bytes allocated from the FrameInfo...
291 unsigned NumBytes = MFI->getStackSize();
293 // If we have any variable size objects, restore the stack frame with the
294 // frame pointer rather than the stack pointer.
295 unsigned FrameReg = hasFP(MF) ? PPC::R31 : PPC::R1;
298 unsigned Opcode = is64bit ? PPC::LD : PPC::LWZ;
299 MI = BuildMI(Opcode, 2, PPC::R1).addSImm(0).addReg(FrameReg);
300 MBB.insert(MBBI, MI);
304 #include "PowerPCGenRegisterInfo.inc"
306 const TargetRegisterClass*
307 PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
308 switch (Ty->getTypeID()) {
309 default: assert(0 && "Invalid type to getClass!");
311 case Type::ULongTyID:
312 if (!is64bit) assert(0 && "Long values can't fit in registers!");
314 case Type::SByteTyID:
315 case Type::UByteTyID:
316 case Type::ShortTyID:
317 case Type::UShortTyID:
320 case Type::PointerTyID: return &GPRCInstance;
322 case Type::FloatTyID:
323 case Type::DoubleTyID: return &FPRCInstance;