lib/Target/PowerPC/PPCSchedule440.td

   1 //===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // Primary reference:
  11 // PowerPC 440x6 Embedded Processor Core User's Manual.
  12 // IBM (as updated in) 2010.
  13
  14 // The basic PPC 440 does not include a floating-point unit; the pipeline
  15 // timings here are constructed to match the FP2 unit shipped with the
  16 // PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
  17 // References:
  18 // S. Chatterjee, et al. Design and exploitation of a high-performance
  19 // SIMD floating-point unit for Blue Gene/L.
  20 // IBM J. Res. & Dev. 49 (2/3) March/May 2005.
  21 // also:
  22 // Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
  23 // Blue Gene/P Application Development.
  24 // IBM (as updated in) 2009.
  25
  26 //===----------------------------------------------------------------------===//
  27 // Functional units on the PowerPC 440/450 chip sets
  28 //
  29 def IFTH1  : FuncUnit; // Fetch unit 1
  30 def IFTH2  : FuncUnit; // Fetch unit 2
  31 def PDCD1  : FuncUnit; // Decode unit 1
  32 def PDCD2  : FuncUnit; // Decode unit 2
  33 def DISS1  : FuncUnit; // Issue unit 1
  34 def DISS2  : FuncUnit; // Issue unit 2
  35 def LRACC  : FuncUnit; // Register access and dispatch for
  36                        // the simple integer (J-pipe) and
  37                        // load/store (L-pipe) pipelines
  38 def IRACC  : FuncUnit; // Register access and dispatch for
  39                        // the complex integer (I-pipe) pipeline
  40 def FRACC  : FuncUnit; // Register access and dispatch for
  41                        // the floating-point execution (F-pipe) pipeline
  42 def IEXE1  : FuncUnit; // Execution stage 1 for the I pipeline
  43 def IEXE2  : FuncUnit; // Execution stage 2 for the I pipeline
  44 def IWB    : FuncUnit; // Write-back unit for the I pipeline
  45 def JEXE1  : FuncUnit; // Execution stage 1 for the J pipeline
  46 def JEXE2  : FuncUnit; // Execution stage 2 for the J pipeline
  47 def JWB    : FuncUnit; // Write-back unit for the J pipeline
  48 def AGEN   : FuncUnit; // Address generation for the L pipeline
  49 def CRD    : FuncUnit; // D-cache access for the L pipeline
  50 def LWB    : FuncUnit; // Write-back unit for the L pipeline
  51 def FEXE1  : FuncUnit; // Execution stage 1 for the F pipeline
  52 def FEXE2  : FuncUnit; // Execution stage 2 for the F pipeline
  53 def FEXE3  : FuncUnit; // Execution stage 3 for the F pipeline
  54 def FEXE4  : FuncUnit; // Execution stage 4 for the F pipeline
  55 def FEXE5  : FuncUnit; // Execution stage 5 for the F pipeline
  56 def FEXE6  : FuncUnit; // Execution stage 6 for the F pipeline
  57 def FWB    : FuncUnit; // Write-back unit for the F pipeline
  58
  59 def LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
  60                            // to make sure that no lwarx/stwcx.
  61                            // instructions are issued while another
  62                            // lwarx/stwcx. is in the L pipe.
  63
  64 def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
  65 def FPR_Bypass : Bypass; // The bypass for floating-point regs.
  66
  67 // Notes:
  68 // Instructions are held in the FRACC, LRACC and IRACC pipeline
  69 // stages until their source operands become ready. Exceptions:
  70 //  - Store instructions will hold in the AGEN stage
  71 //  - The integer multiply-accumulate instruction will hold in
  72 //    the IEXE1 stage
  73 //
  74 // For most I-pipe operations, the result is available at the end of
  75 // the IEXE1 stage. Operations such as multiply and divide must
  76 // continue to execute in IEXE2 and IWB. Divide resides in IWB for
  77 // 33 cycles (multiply also calculates its result in IWB). For all
  78 // J-pipe instructions, the result is available
  79 // at the end of the JEXE1 stage. Loads have a 3-cycle latency
  80 // (data is not available until after the LWB stage).
  81 //
  82 // The L1 cache hit latency is four cycles for floating point loads
  83 // and three cycles for integer loads.
  84 //
  85 // The stwcx. instruction requires both the LRACC and the IRACC
  86 // dispatch stages. It must be issued from DISS0.
  87 //
  88 // All lwarx/stwcx. instructions hold in LRACC if another
  89 // uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
  90 //
  91 // msync (a.k.a. sync) and mbar will hold in LWB until all load/store
  92 // resources are empty. AGEN and CRD are held empty until the msync/mbar
  93 // commits.
  94 //
  95 // Most floating-point instructions, computational and move,
  96 // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
  97 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
  98 // loads take 4 cycles (for L1 hit).
  99
 100 //
 101 // This file defines the itinerary class data for the PPC 440 processor.
 102 //
 103 //===----------------------------------------------------------------------===//
 104
 105
 106 def PPC440Itineraries : ProcessorItineraries<
 107   [IFTH1, IFTH2, PDCD1, PDCD2, DISS1, DISS2, FRACC,
 108    IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB,
 109    FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold],
 110   [GPR_Bypass, FPR_Bypass], [
 111   InstrItinData<IntGeneral  , [InstrStage<1, [IFTH1, IFTH2]>,
 112                                InstrStage<1, [PDCD1, PDCD2]>,
 113                                InstrStage<1, [DISS1, DISS2]>,
 114                                InstrStage<1, [IRACC, LRACC]>,
 115                                InstrStage<1, [IEXE1, JEXE1]>,
 116                                InstrStage<1, [IEXE2, JEXE2]>,
 117                                InstrStage<1, [IWB, JWB]>],
 118                               [6, 4, 4],
 119                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 120   InstrItinData<IntCompare  , [InstrStage<1, [IFTH1, IFTH2]>,
 121                                InstrStage<1, [PDCD1, PDCD2]>,
 122                                InstrStage<1, [DISS1, DISS2]>,
 123                                InstrStage<1, [IRACC, LRACC]>,
 124                                InstrStage<1, [IEXE1, JEXE1]>,
 125                                InstrStage<1, [IEXE2, JEXE2]>,
 126                                InstrStage<1, [IWB, JWB]>],
 127                               [6, 4, 4],
 128                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 129   InstrItinData<IntDivW     , [InstrStage<1, [IFTH1, IFTH2]>,
 130                                InstrStage<1, [PDCD1, PDCD2]>,
 131                                InstrStage<1, [DISS1, DISS2]>,
 132                                InstrStage<1, [IRACC]>,
 133                                InstrStage<1, [IEXE1]>,
 134                                InstrStage<1, [IEXE2]>,
 135                                InstrStage<33, [IWB]>],
 136                               [40, 4, 4],
 137                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 138   InstrItinData<IntMFFS     , [InstrStage<1, [IFTH1, IFTH2]>,
 139                                InstrStage<1, [PDCD1, PDCD2]>,
 140                                InstrStage<1, [DISS1, DISS2]>,
 141                                InstrStage<1, [IRACC]>,
 142                                InstrStage<1, [IEXE1]>,
 143                                InstrStage<1, [IEXE2]>,
 144                                InstrStage<1, [IWB]>],
 145                               [7, 4, 4],
 146                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 147   InstrItinData<IntMTFSB0   , [InstrStage<1, [IFTH1, IFTH2]>,
 148                                InstrStage<1, [PDCD1, PDCD2]>,
 149                                InstrStage<1, [DISS1, DISS2]>,
 150                                InstrStage<1, [IRACC]>,
 151                                InstrStage<1, [IEXE1]>,
 152                                InstrStage<1, [IEXE2]>,
 153                                InstrStage<1, [IWB]>],
 154                               [7, 4, 4],
 155                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 156   InstrItinData<IntMulHW    , [InstrStage<1, [IFTH1, IFTH2]>,
 157                                InstrStage<1, [PDCD1, PDCD2]>,
 158                                InstrStage<1, [DISS1, DISS2]>,
 159                                InstrStage<1, [IRACC]>,
 160                                InstrStage<1, [IEXE1]>,
 161                                InstrStage<1, [IEXE2]>,
 162                                InstrStage<1, [IWB]>],
 163                               [8, 4, 4],
 164                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 165   InstrItinData<IntMulHWU   , [InstrStage<1, [IFTH1, IFTH2]>,
 166                                InstrStage<1, [PDCD1, PDCD2]>,
 167                                InstrStage<1, [DISS1, DISS2]>,
 168                                InstrStage<1, [IRACC]>,
 169                                InstrStage<1, [IEXE1]>,
 170                                InstrStage<1, [IEXE2]>,
 171                                InstrStage<1, [IWB]>],
 172                               [8, 4, 4],
 173                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 174   InstrItinData<IntMulLI    , [InstrStage<1, [IFTH1, IFTH2]>,
 175                                InstrStage<1, [PDCD1, PDCD2]>,
 176                                InstrStage<1, [DISS1, DISS2]>,
 177                                InstrStage<1, [IRACC]>,
 178                                InstrStage<1, [IEXE1]>,
 179                                InstrStage<1, [IEXE2]>,
 180                                InstrStage<1, [IWB]>],
 181                               [8, 4, 4],
 182                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 183   InstrItinData<IntRotate   , [InstrStage<1, [IFTH1, IFTH2]>,
 184                                InstrStage<1, [PDCD1, PDCD2]>,
 185                                InstrStage<1, [DISS1, DISS2]>,
 186                                InstrStage<1, [IRACC, LRACC]>,
 187                                InstrStage<1, [IEXE1, JEXE1]>,
 188                                InstrStage<1, [IEXE2, JEXE2]>,
 189                                InstrStage<1, [IWB, JWB]>],
 190                               [6, 4, 4],
 191                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 192   InstrItinData<IntShift    , [InstrStage<1, [IFTH1, IFTH2]>,
 193                                InstrStage<1, [PDCD1, PDCD2]>,
 194                                InstrStage<1, [DISS1, DISS2]>,
 195                                InstrStage<1, [IRACC, LRACC]>,
 196                                InstrStage<1, [IEXE1, JEXE1]>,
 197                                InstrStage<1, [IEXE2, JEXE2]>,
 198                                InstrStage<1, [IWB, JWB]>],
 199                               [6, 4, 4],
 200                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 201   InstrItinData<IntTrapW    , [InstrStage<1, [IFTH1, IFTH2]>,
 202                                InstrStage<1, [PDCD1, PDCD2]>,
 203                                InstrStage<1, [DISS1, DISS2]>,
 204                                InstrStage<1, [IRACC]>,
 205                                InstrStage<1, [IEXE1]>,
 206                                InstrStage<1, [IEXE2]>,
 207                                InstrStage<1, [IWB]>],
 208                               [6, 4],
 209                               [GPR_Bypass, GPR_Bypass]>,
 210   InstrItinData<BrB         , [InstrStage<1, [IFTH1, IFTH2]>,
 211                                InstrStage<1, [PDCD1, PDCD2]>,
 212                                InstrStage<1, [DISS1, DISS2]>,
 213                                InstrStage<1, [IRACC]>,
 214                                InstrStage<1, [IEXE1]>,
 215                                InstrStage<1, [IEXE2]>,
 216                                InstrStage<1, [IWB]>],
 217                               [8, 4],
 218                               [NoBypass, GPR_Bypass]>,
 219   InstrItinData<BrCR        , [InstrStage<1, [IFTH1, IFTH2]>,
 220                                InstrStage<1, [PDCD1, PDCD2]>,
 221                                InstrStage<1, [DISS1, DISS2]>,
 222                                InstrStage<1, [IRACC]>,
 223                                InstrStage<1, [IEXE1]>,
 224                                InstrStage<1, [IEXE2]>,
 225                                InstrStage<1, [IWB]>],
 226                               [8, 4, 4],
 227                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 228   InstrItinData<BrMCR       , [InstrStage<1, [IFTH1, IFTH2]>,
 229                                InstrStage<1, [PDCD1, PDCD2]>,
 230                                InstrStage<1, [DISS1, DISS2]>,
 231                                InstrStage<1, [IRACC]>,
 232                                InstrStage<1, [IEXE1]>,
 233                                InstrStage<1, [IEXE2]>,
 234                                InstrStage<1, [IWB]>],
 235                               [8, 4, 4],
 236                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 237   InstrItinData<BrMCRX      , [InstrStage<1, [IFTH1, IFTH2]>,
 238                                InstrStage<1, [PDCD1, PDCD2]>,
 239                                InstrStage<1, [DISS1, DISS2]>,
 240                                InstrStage<1, [IRACC]>,
 241                                InstrStage<1, [IEXE1]>,
 242                                InstrStage<1, [IEXE2]>,
 243                                InstrStage<1, [IWB]>],
 244                               [8, 4, 4],
 245                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 246   InstrItinData<LdStDCBA    , [InstrStage<1, [IFTH1, IFTH2]>,
 247                                InstrStage<1, [PDCD1, PDCD2]>,
 248                                InstrStage<1, [DISS1, DISS2]>,
 249                                InstrStage<1, [LRACC]>,
 250                                InstrStage<1, [AGEN]>,
 251                                InstrStage<1, [CRD]>,
 252                                InstrStage<1, [LWB]>],
 253                               [8, 5],
 254                               [NoBypass, GPR_Bypass]>,
 255   InstrItinData<LdStDCBF    , [InstrStage<1, [IFTH1, IFTH2]>,
 256                                InstrStage<1, [PDCD1, PDCD2]>,
 257                                InstrStage<1, [DISS1, DISS2]>,
 258                                InstrStage<1, [LRACC]>,
 259                                InstrStage<1, [AGEN]>,
 260                                InstrStage<1, [CRD]>,
 261                                InstrStage<1, [LWB]>],
 262                               [8, 5],
 263                               [NoBypass, GPR_Bypass]>,
 264   InstrItinData<LdStDCBI    , [InstrStage<1, [IFTH1, IFTH2]>,
 265                                InstrStage<1, [PDCD1, PDCD2]>,
 266                                InstrStage<1, [DISS1, DISS2]>,
 267                                InstrStage<1, [LRACC]>,
 268                                InstrStage<1, [AGEN]>,
 269                                InstrStage<1, [CRD]>,
 270                                InstrStage<1, [LWB]>],
 271                               [8, 5],
 272                               [NoBypass, GPR_Bypass]>,
 273   InstrItinData<LdStGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
 274                                InstrStage<1, [PDCD1, PDCD2]>,
 275                                InstrStage<1, [DISS1, DISS2]>,
 276                                InstrStage<1, [LRACC]>,
 277                                InstrStage<1, [AGEN]>,
 278                                InstrStage<1, [CRD]>,
 279                                InstrStage<2, [LWB]>],
 280                               [9, 5], // FIXME: should be [9, 5] for loads and
 281                                        // [8, 5] for stores.
 282                               [NoBypass, GPR_Bypass]>,
 283   InstrItinData<LdStICBI    , [InstrStage<1, [IFTH1, IFTH2]>,
 284                                InstrStage<1, [PDCD1, PDCD2]>,
 285                                InstrStage<1, [DISS1, DISS2]>,
 286                                InstrStage<1, [LRACC]>,
 287                                InstrStage<1, [AGEN]>,
 288                                InstrStage<1, [CRD]>,
 289                                InstrStage<1, [LWB]>],
 290                               [8, 5],
 291                               [NoBypass, GPR_Bypass]>,
 292   InstrItinData<LdStUX      , [InstrStage<1, [IFTH1, IFTH2]>,
 293                                InstrStage<1, [PDCD1, PDCD2]>,
 294                                InstrStage<1, [DISS1, DISS2]>,
 295                                InstrStage<1, [LRACC]>,
 296                                InstrStage<1, [AGEN]>,
 297                                InstrStage<1, [CRD]>,
 298                                InstrStage<1, [LWB]>],
 299                               [8, 5, 5],
 300                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 301   InstrItinData<LdStLFD     , [InstrStage<1, [IFTH1, IFTH2]>,
 302                                InstrStage<1, [PDCD1, PDCD2]>,
 303                                InstrStage<1, [DISS1, DISS2]>,
 304                                InstrStage<1, [LRACC]>,
 305                                InstrStage<1, [AGEN]>,
 306                                InstrStage<1, [CRD]>,
 307                                InstrStage<2, [LWB]>],
 308                               [9, 5, 5],
 309                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 310   InstrItinData<LdStLFDU    , [InstrStage<1, [IFTH1, IFTH2]>,
 311                                InstrStage<1, [PDCD1, PDCD2]>,
 312                                InstrStage<1, [DISS1, DISS2]>,
 313                                InstrStage<1, [LRACC]>,
 314                                InstrStage<1, [AGEN]>,
 315                                InstrStage<1, [CRD]>,
 316                                InstrStage<1, [LWB]>],
 317                               [9, 5, 5],
 318                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 319   InstrItinData<LdStLHA     , [InstrStage<1, [IFTH1, IFTH2]>,
 320                                InstrStage<1, [PDCD1, PDCD2]>,
 321                                InstrStage<1, [DISS1, DISS2]>,
 322                                InstrStage<1, [LRACC]>,
 323                                InstrStage<1, [AGEN]>,
 324                                InstrStage<1, [CRD]>,
 325                                InstrStage<1, [LWB]>],
 326                               [8, 5],
 327                               [NoBypass, GPR_Bypass]>,
 328   InstrItinData<LdStLMW     , [InstrStage<1, [IFTH1, IFTH2]>,
 329                                InstrStage<1, [PDCD1, PDCD2]>,
 330                                InstrStage<1, [DISS1, DISS2]>,
 331                                InstrStage<1, [LRACC]>,
 332                                InstrStage<1, [AGEN]>,
 333                                InstrStage<1, [CRD]>,
 334                                InstrStage<1, [LWB]>],
 335                               [8, 5],
 336                               [NoBypass, GPR_Bypass]>,
 337   InstrItinData<LdStLWARX   , [InstrStage<1, [IFTH1, IFTH2]>,
 338                                InstrStage<1, [PDCD1, PDCD2]>,
 339                                InstrStage<1, [DISS1]>,
 340                                InstrStage<1, [IRACC], 0>,
 341                                InstrStage<4, [LWARX_Hold], 0>,
 342                                InstrStage<1, [LRACC]>,
 343                                InstrStage<1, [AGEN]>,
 344                                InstrStage<1, [CRD]>,
 345                                InstrStage<1, [LWB]>],
 346                               [8, 5],
 347                               [NoBypass, GPR_Bypass]>,
 348   InstrItinData<LdStSTWCX   , [InstrStage<1, [IFTH1, IFTH2]>,
 349                                InstrStage<1, [PDCD1, PDCD2]>,
 350                                InstrStage<1, [DISS1]>,
 351                                InstrStage<1, [IRACC], 0>,
 352                                InstrStage<4, [LWARX_Hold], 0>,
 353                                InstrStage<1, [LRACC]>,
 354                                InstrStage<1, [AGEN]>,
 355                                InstrStage<1, [CRD]>,
 356                                InstrStage<1, [LWB]>],
 357                               [8, 5],
 358                               [NoBypass, GPR_Bypass]>,
 359   InstrItinData<LdStSync    , [InstrStage<1, [IFTH1, IFTH2]>,
 360                                InstrStage<1, [PDCD1, PDCD2]>,
 361                                InstrStage<1, [DISS1, DISS2]>,
 362                                InstrStage<1, [LRACC]>,
 363                                InstrStage<3, [AGEN], 1>,
 364                                InstrStage<2, [CRD],  1>,
 365                                InstrStage<1, [LWB]>]>,
 366   InstrItinData<SprISYNC    , [InstrStage<1, [IFTH1, IFTH2]>,
 367                                InstrStage<1, [PDCD1, PDCD2]>,
 368                                InstrStage<1, [DISS1, DISS2]>,
 369                                InstrStage<1, [FRACC], 0>,
 370                                InstrStage<1, [LRACC], 0>,
 371                                InstrStage<1, [IRACC]>,
 372                                InstrStage<1, [FEXE1], 0>,
 373                                InstrStage<1, [AGEN],  0>,
 374                                InstrStage<1, [JEXE1], 0>,
 375                                InstrStage<1, [IEXE1]>,
 376                                InstrStage<1, [FEXE2], 0>,
 377                                InstrStage<1, [CRD],   0>,
 378                                InstrStage<1, [JEXE2], 0>,
 379                                InstrStage<1, [IEXE2]>,
 380                                InstrStage<6, [FEXE3], 0>,
 381                                InstrStage<6, [LWB],   0>,
 382                                InstrStage<6, [JWB],   0>,
 383                                InstrStage<6, [IWB]>]>,
 384   InstrItinData<SprMFSR     , [InstrStage<1, [IFTH1, IFTH2]>,
 385                                InstrStage<1, [PDCD1, PDCD2]>,
 386                                InstrStage<1, [DISS1, DISS2]>,
 387                                InstrStage<1, [IRACC]>,
 388                                InstrStage<1, [IEXE1]>,
 389                                InstrStage<1, [IEXE2]>,
 390                                InstrStage<1, [IWB]>],
 391                               [6, 4],
 392                               [GPR_Bypass, GPR_Bypass]>,
 393   InstrItinData<SprMTMSR    , [InstrStage<1, [IFTH1, IFTH2]>,
 394                                InstrStage<1, [PDCD1, PDCD2]>,
 395                                InstrStage<1, [DISS1, DISS2]>,
 396                                InstrStage<1, [IRACC]>,
 397                                InstrStage<1, [IEXE1]>,
 398                                InstrStage<1, [IEXE2]>,
 399                                InstrStage<1, [IWB]>],
 400                               [6, 4],
 401                               [GPR_Bypass, GPR_Bypass]>,
 402   InstrItinData<SprMTSR     , [InstrStage<1, [IFTH1, IFTH2]>,
 403                                InstrStage<1, [PDCD1, PDCD2]>,
 404                                InstrStage<1, [DISS1, DISS2]>,
 405                                InstrStage<1, [IRACC]>,
 406                                InstrStage<1, [IEXE1]>,
 407                                InstrStage<1, [IEXE2]>,
 408                                InstrStage<3, [IWB]>],
 409                               [9, 4],
 410                               [NoBypass, GPR_Bypass]>,
 411   InstrItinData<SprTLBSYNC  , [InstrStage<1, [IFTH1, IFTH2]>,
 412                                InstrStage<1, [PDCD1, PDCD2]>,
 413                                InstrStage<1, [DISS1, DISS2]>,
 414                                InstrStage<1, [IRACC]>,
 415                                InstrStage<1, [IEXE1]>,
 416                                InstrStage<1, [IEXE2]>,
 417                                InstrStage<1, [IWB]>]>,
 418   InstrItinData<SprMFCR     , [InstrStage<1, [IFTH1, IFTH2]>,
 419                                InstrStage<1, [PDCD1, PDCD2]>,
 420                                InstrStage<1, [DISS1, DISS2]>,
 421                                InstrStage<1, [IRACC]>,
 422                                InstrStage<1, [IEXE1]>,
 423                                InstrStage<1, [IEXE2]>,
 424                                InstrStage<1, [IWB]>],
 425                               [8, 4],
 426                               [NoBypass, GPR_Bypass]>,
 427   InstrItinData<SprMFMSR    , [InstrStage<1, [IFTH1, IFTH2]>,
 428                                InstrStage<1, [PDCD1, PDCD2]>,
 429                                InstrStage<1, [DISS1, DISS2]>,
 430                                InstrStage<1, [IRACC]>,
 431                                InstrStage<1, [IEXE1]>,
 432                                InstrStage<1, [IEXE2]>,
 433                                InstrStage<1, [IWB]>],
 434                               [7, 4],
 435                               [GPR_Bypass, GPR_Bypass]>,
 436   InstrItinData<SprMFSPR    , [InstrStage<1, [IFTH1, IFTH2]>,
 437                                InstrStage<1, [PDCD1, PDCD2]>,
 438                                InstrStage<1, [DISS1, DISS2]>,
 439                                InstrStage<1, [IRACC]>,
 440                                InstrStage<1, [IEXE1]>,
 441                                InstrStage<1, [IEXE2]>,
 442                                InstrStage<3, [IWB]>],
 443                               [10, 4],
 444                               [NoBypass, GPR_Bypass]>,
 445   InstrItinData<SprMFTB     , [InstrStage<1, [IFTH1, IFTH2]>,
 446                                InstrStage<1, [PDCD1, PDCD2]>,
 447                                InstrStage<1, [DISS1, DISS2]>,
 448                                InstrStage<1, [IRACC]>,
 449                                InstrStage<1, [IEXE1]>,
 450                                InstrStage<1, [IEXE2]>,
 451                                InstrStage<3, [IWB]>],
 452                               [10, 4],
 453                               [NoBypass, GPR_Bypass]>,
 454   InstrItinData<SprMTSPR    , [InstrStage<1, [IFTH1, IFTH2]>,
 455                                InstrStage<1, [PDCD1, PDCD2]>,
 456                                InstrStage<1, [DISS1, DISS2]>,
 457                                InstrStage<1, [IRACC]>,
 458                                InstrStage<1, [IEXE1]>,
 459                                InstrStage<1, [IEXE2]>,
 460                                InstrStage<3, [IWB]>],
 461                               [10, 4],
 462                               [NoBypass, GPR_Bypass]>,
 463   InstrItinData<SprMTSRIN   , [InstrStage<1, [IFTH1, IFTH2]>,
 464                                InstrStage<1, [PDCD1, PDCD2]>,
 465                                InstrStage<1, [DISS1, DISS2]>,
 466                                InstrStage<1, [IRACC]>,
 467                                InstrStage<1, [IEXE1]>,
 468                                InstrStage<1, [IEXE2]>,
 469                                InstrStage<3, [IWB]>],
 470                               [10, 4],
 471                               [NoBypass, GPR_Bypass]>,
 472   InstrItinData<SprRFI      , [InstrStage<1, [IFTH1, IFTH2]>,
 473                                InstrStage<1, [PDCD1, PDCD2]>,
 474                                InstrStage<1, [DISS1, DISS2]>,
 475                                InstrStage<1, [IRACC]>,
 476                                InstrStage<1, [IEXE1]>,
 477                                InstrStage<1, [IEXE2]>,
 478                                InstrStage<1, [IWB]>],
 479                               [8, 4],
 480                               [NoBypass, GPR_Bypass]>,
 481   InstrItinData<SprSC       , [InstrStage<1, [IFTH1, IFTH2]>,
 482                                InstrStage<1, [PDCD1, PDCD2]>,
 483                                InstrStage<1, [DISS1, DISS2]>,
 484                                InstrStage<1, [IRACC]>,
 485                                InstrStage<1, [IEXE1]>,
 486                                InstrStage<1, [IEXE2]>,
 487                                InstrStage<1, [IWB]>],
 488                               [8, 4],
 489                               [NoBypass, GPR_Bypass]>,
 490   InstrItinData<FPGeneral   , [InstrStage<1, [IFTH1, IFTH2]>,
 491                                InstrStage<1, [PDCD1, PDCD2]>,
 492                                InstrStage<1, [DISS1, DISS2]>,
 493                                InstrStage<1, [FRACC]>,
 494                                InstrStage<1, [FEXE1]>,
 495                                InstrStage<1, [FEXE2]>,
 496                                InstrStage<1, [FEXE3]>,
 497                                InstrStage<1, [FEXE4]>,
 498                                InstrStage<1, [FEXE5]>,
 499                                InstrStage<1, [FEXE6]>,
 500                                InstrStage<1, [FWB]>],
 501                               [10, 4, 4],
 502                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 503   InstrItinData<FPCompare   , [InstrStage<1, [IFTH1, IFTH2]>,
 504                                InstrStage<1, [PDCD1, PDCD2]>,
 505                                InstrStage<1, [DISS1, DISS2]>,
 506                                InstrStage<1, [FRACC]>,
 507                                InstrStage<1, [FEXE1]>,
 508                                InstrStage<1, [FEXE2]>,
 509                                InstrStage<1, [FEXE3]>,
 510                                InstrStage<1, [FEXE4]>,
 511                                InstrStage<1, [FEXE5]>,
 512                                InstrStage<1, [FEXE6]>,
 513                                InstrStage<1, [FWB]>],
 514                               [10, 4, 4],
 515                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 516   InstrItinData<FPDivD      , [InstrStage<1, [IFTH1, IFTH2]>,
 517                                InstrStage<1, [PDCD1, PDCD2]>,
 518                                InstrStage<1, [DISS1, DISS2]>,
 519                                InstrStage<1, [FRACC]>,
 520                                InstrStage<1, [FEXE1]>,
 521                                InstrStage<1, [FEXE2]>,
 522                                InstrStage<1, [FEXE3]>,
 523                                InstrStage<1, [FEXE4]>,
 524                                InstrStage<1, [FEXE5]>,
 525                                InstrStage<1, [FEXE6]>,
 526                                InstrStage<25, [FWB]>],
 527                               [35, 4, 4],
 528                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 529   InstrItinData<FPDivS      , [InstrStage<1, [IFTH1, IFTH2]>,
 530                                InstrStage<1, [PDCD1, PDCD2]>,
 531                                InstrStage<1, [DISS1, DISS2]>,
 532                                InstrStage<1, [FRACC]>,
 533                                InstrStage<1, [FEXE1]>,
 534                                InstrStage<1, [FEXE2]>,
 535                                InstrStage<1, [FEXE3]>,
 536                                InstrStage<1, [FEXE4]>,
 537                                InstrStage<1, [FEXE5]>,
 538                                InstrStage<1, [FEXE6]>,
 539                                InstrStage<13, [FWB]>],
 540                               [23, 4, 4],
 541                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 542   InstrItinData<FPFused     , [InstrStage<1, [IFTH1, IFTH2]>,
 543                                InstrStage<1, [PDCD1, PDCD2]>,
 544                                InstrStage<1, [DISS1, DISS2]>,
 545                                InstrStage<1, [FRACC]>,
 546                                InstrStage<1, [FEXE1]>,
 547                                InstrStage<1, [FEXE2]>,
 548                                InstrStage<1, [FEXE3]>,
 549                                InstrStage<1, [FEXE4]>,
 550                                InstrStage<1, [FEXE5]>,
 551                                InstrStage<1, [FEXE6]>,
 552                                InstrStage<1, [FWB]>],
 553                               [10, 4, 4, 4],
 554                               [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 555   InstrItinData<FPRes       , [InstrStage<1, [IFTH1, IFTH2]>,
 556                                InstrStage<1, [PDCD1, PDCD2]>,
 557                                InstrStage<1, [DISS1, DISS2]>,
 558                                InstrStage<1, [FRACC]>,
 559                                InstrStage<1, [FEXE1]>,
 560                                InstrStage<1, [FEXE2]>,
 561                                InstrStage<1, [FEXE3]>,
 562                                InstrStage<1, [FEXE4]>,
 563                                InstrStage<1, [FEXE5]>,
 564                                InstrStage<1, [FEXE6]>,
 565                                InstrStage<1, [FWB]>],
 566                               [10, 4],
 567                               [FPR_Bypass, FPR_Bypass]>
 568 ]>;