1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineLocation.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/RegisterScavenging.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/STLExtras.h"
48 // FIXME This disables some code that aligns the stack to a boundary
49 // bigger than the default (16 bytes on Darwin) when there is a stack local
50 // of greater alignment. This does not currently work, because the delta
51 // between old and new stack pointers is added to offsets that reference
52 // incoming parameters after the prolog is generated, and the code that
53 // does that doesn't handle a variable delta. You don't want to do that
54 // anyway; a better approach is to reserve another register that retains
55 // to the incoming stack pointer, and reference parameters relative to that.
58 // FIXME (64-bit): Eventually enable by default.
59 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
61 cl::desc("Enable PPC32 register scavenger"),
63 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
65 cl::desc("Enable PPC64 register scavenger"),
67 #define EnableRegisterScavenging \
68 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
69 (EnablePPC64RS && Subtarget.isPPC64()))
71 // FIXME (64-bit): Should be inlined.
73 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
74 return EnableRegisterScavenging;
77 /// getRegisterNumbering - Given the enum value for some register, e.g.
78 /// PPC::F14, return the number that it corresponds to (e.g. 14).
79 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
83 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
84 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
85 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
86 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
87 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
88 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
89 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
90 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
91 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
92 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
93 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
94 case R11: case X11: case F11: case V11: case CR2UN: return 11;
95 case R12: case X12: case F12: case V12: case CR3LT: return 12;
96 case R13: case X13: case F13: case V13: case CR3GT: return 13;
97 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
98 case R15: case X15: case F15: case V15: case CR3UN: return 15;
99 case R16: case X16: case F16: case V16: case CR4LT: return 16;
100 case R17: case X17: case F17: case V17: case CR4GT: return 17;
101 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
102 case R19: case X19: case F19: case V19: case CR4UN: return 19;
103 case R20: case X20: case F20: case V20: case CR5LT: return 20;
104 case R21: case X21: case F21: case V21: case CR5GT: return 21;
105 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
106 case R23: case X23: case F23: case V23: case CR5UN: return 23;
107 case R24: case X24: case F24: case V24: case CR6LT: return 24;
108 case R25: case X25: case F25: case V25: case CR6GT: return 25;
109 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
110 case R27: case X27: case F27: case V27: case CR6UN: return 27;
111 case R28: case X28: case F28: case V28: case CR7LT: return 28;
112 case R29: case X29: case F29: case V29: case CR7GT: return 29;
113 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
114 case R31: case X31: case F31: case V31: case CR7UN: return 31;
116 LLVM_UNREACHABLE("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
120 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
121 const TargetInstrInfo &tii)
122 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
123 Subtarget(ST), TII(tii) {
124 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
125 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
126 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
127 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
128 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
129 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
130 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
131 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
134 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
135 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
136 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
137 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
138 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
141 /// getPointerRegClass - Return the register class to use to hold pointers.
142 /// This is used for addressing modes.
143 const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
144 if (Subtarget.isPPC64())
145 return &PPC::G8RCRegClass;
147 return &PPC::GPRCRegClass;
151 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
152 // 32-bit Darwin calling convention.
153 static const unsigned Darwin32_CalleeSavedRegs[] = {
154 PPC::R13, PPC::R14, PPC::R15,
155 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
156 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
157 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
158 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
160 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
161 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
162 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
163 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
166 PPC::CR2, PPC::CR3, PPC::CR4,
167 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
168 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
169 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
171 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
172 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
173 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
178 static const unsigned SVR4_CalleeSavedRegs[] = {
180 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
181 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
182 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
183 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
185 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
186 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
187 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
188 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
191 PPC::CR2, PPC::CR3, PPC::CR4,
195 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
196 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
197 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
199 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
200 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
201 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
205 // 64-bit Darwin calling convention.
206 static const unsigned Darwin64_CalleeSavedRegs[] = {
208 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
209 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
210 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
211 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
213 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
214 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
215 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
216 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
219 PPC::CR2, PPC::CR3, PPC::CR4,
220 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
221 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
222 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
224 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
225 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
226 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
231 if (Subtarget.isDarwinABI())
232 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
233 Darwin32_CalleeSavedRegs;
235 return SVR4_CalleeSavedRegs;
238 const TargetRegisterClass* const*
239 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
240 // 32-bit Darwin calling convention.
241 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
242 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
243 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
244 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
245 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
246 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
248 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
249 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
250 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
251 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
252 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
254 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
256 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
257 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
258 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
260 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
261 &PPC::CRBITRCRegClass,
262 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
263 &PPC::CRBITRCRegClass,
264 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
265 &PPC::CRBITRCRegClass,
267 &PPC::GPRCRegClass, 0
270 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = {
271 &PPC::GPRCRegClass,&PPC::GPRCRegClass,
272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
275 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
277 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
281 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
283 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
285 &PPC::VRSAVERCRegClass,
287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
289 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
291 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
292 &PPC::CRBITRCRegClass,
293 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
294 &PPC::CRBITRCRegClass,
295 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
296 &PPC::CRBITRCRegClass,
298 &PPC::GPRCRegClass, 0
301 // 64-bit Darwin calling convention.
302 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
303 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
304 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
305 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
306 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
307 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
310 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
311 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
312 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
313 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
315 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
317 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
318 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
319 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
321 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
322 &PPC::CRBITRCRegClass,
323 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
324 &PPC::CRBITRCRegClass,
325 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
326 &PPC::CRBITRCRegClass,
328 &PPC::G8RCRegClass, 0
331 if (Subtarget.isDarwinABI())
332 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
333 Darwin32_CalleeSavedRegClasses;
335 return SVR4_CalleeSavedRegClasses;
338 // needsFP - Return true if the specified function should have a dedicated frame
339 // pointer register. This is true if the function has variable sized allocas or
340 // if frame pointer elimination is disabled.
342 static bool needsFP(const MachineFunction &MF) {
343 const MachineFrameInfo *MFI = MF.getFrameInfo();
344 return NoFramePointerElim || MFI->hasVarSizedObjects() ||
345 (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall());
348 static bool spillsCR(const MachineFunction &MF) {
349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350 return FuncInfo->isCRSpilled();
353 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
354 BitVector Reserved(getNumRegs());
355 Reserved.set(PPC::R0);
356 Reserved.set(PPC::R1);
357 Reserved.set(PPC::LR);
358 Reserved.set(PPC::LR8);
359 Reserved.set(PPC::RM);
361 // The SVR4 ABI reserves r2 and r13
362 if (Subtarget.isSVR4ABI()) {
363 Reserved.set(PPC::R2); // System-reserved register
364 Reserved.set(PPC::R13); // Small Data Area pointer register
367 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
368 // that this is over conservative, as it also prevents allocation of R31 when
369 // the FP is not needed.
370 if (Subtarget.isPPC64()) {
371 Reserved.set(PPC::R13);
372 Reserved.set(PPC::R31);
374 if (!EnableRegisterScavenging)
375 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
377 Reserved.set(PPC::X0);
378 Reserved.set(PPC::X1);
379 Reserved.set(PPC::X13);
380 Reserved.set(PPC::X31);
384 Reserved.set(PPC::R31);
389 //===----------------------------------------------------------------------===//
390 // Stack Frame Processing methods
391 //===----------------------------------------------------------------------===//
393 // hasFP - Return true if the specified function actually has a dedicated frame
394 // pointer register. This is true if the function needs a frame pointer and has
395 // a non-zero stack size.
396 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
397 const MachineFrameInfo *MFI = MF.getFrameInfo();
398 return MFI->getStackSize() && needsFP(MF);
401 /// MustSaveLR - Return true if this function requires that we save the LR
402 /// register onto the stack in the prolog and restore it in the epilog of the
404 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
405 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
407 // We need a save/restore of LR if there is any def of LR (which is
408 // defined by calls, including the PIC setup sequence), or if there is
409 // some use of the LR stack slot (e.g. for builtin_return_address).
410 // (LR comes in 32 and 64 bit versions.)
411 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
412 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
417 void PPCRegisterInfo::
418 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
419 MachineBasicBlock::iterator I) const {
420 if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
421 // Add (actually subtract) back the amount the callee popped on return.
422 if (int CalleeAmt = I->getOperand(1).getImm()) {
423 bool is64Bit = Subtarget.isPPC64();
425 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
426 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
427 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
428 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
429 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
430 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
431 MachineInstr *MI = I;
432 DebugLoc dl = MI->getDebugLoc();
434 if (isInt16(CalleeAmt)) {
435 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
438 MachineBasicBlock::iterator MBBI = I;
439 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
440 .addImm(CalleeAmt >> 16);
441 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
442 .addReg(TmpReg, RegState::Kill)
443 .addImm(CalleeAmt & 0xFFFF);
444 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
451 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
455 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
456 /// register first and then a spilled callee-saved register if that fails.
458 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
459 const TargetRegisterClass *RC, int SPAdj) {
460 assert(RS && "Register scavenging must be on");
461 unsigned Reg = RS->FindUnusedReg(RC, true);
462 // FIXME: move ARM callee-saved reg scan to target independent code, then
463 // search for already spilled CS register here.
465 Reg = RS->scavengeRegister(RC, II, SPAdj);
469 /// lowerDynamicAlloc - Generate the code for allocating an object in the
470 /// current frame. The sequence of code with be in the general form
472 /// addi R0, SP, \#frameSize ; get the address of the previous frame
473 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
474 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
476 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
477 int SPAdj, RegScavenger *RS) const {
478 // Get the instruction.
479 MachineInstr &MI = *II;
480 // Get the instruction's basic block.
481 MachineBasicBlock &MBB = *MI.getParent();
482 // Get the basic block's function.
483 MachineFunction &MF = *MBB.getParent();
484 // Get the frame info.
485 MachineFrameInfo *MFI = MF.getFrameInfo();
486 // Determine whether 64-bit pointers are used.
487 bool LP64 = Subtarget.isPPC64();
488 DebugLoc dl = MI.getDebugLoc();
490 // Get the maximum call stack size.
491 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
492 // Get the total frame size.
493 unsigned FrameSize = MFI->getStackSize();
495 // Get stack alignments.
496 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
497 unsigned MaxAlign = MFI->getMaxAlignment();
498 assert(MaxAlign <= TargetAlign &&
499 "Dynamic alloca with large aligns not supported");
501 // Determine the previous frame's address. If FrameSize can't be
502 // represented as 16 bits or we need special alignment, then we load the
503 // previous frame's address from 0(SP). Why not do an addis of the hi?
504 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
505 // Constructing the constant and adding would take 3 instructions.
506 // Fortunately, a frame greater than 32K is rare.
507 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
508 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
509 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
511 // FIXME (64-bit): Use "findScratchRegister"
513 if (EnableRegisterScavenging)
514 Reg = findScratchRegister(II, RS, RC, SPAdj);
518 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
519 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
523 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
524 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
528 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
532 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
537 // Grow the stack and update the stack pointer link, then determine the
538 // address of new allocated space.
540 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
541 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
542 .addReg(Reg, RegState::Kill)
544 .addReg(MI.getOperand(1).getReg());
546 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
547 .addReg(PPC::X0, RegState::Kill)
549 .addReg(MI.getOperand(1).getReg());
551 if (!MI.getOperand(1).isKill())
552 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
554 .addImm(maxCallFrameSize);
556 // Implicitly kill the register.
557 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
559 .addImm(maxCallFrameSize)
560 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
562 BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
563 .addReg(Reg, RegState::Kill)
565 .addReg(MI.getOperand(1).getReg());
567 if (!MI.getOperand(1).isKill())
568 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
570 .addImm(maxCallFrameSize);
572 // Implicitly kill the register.
573 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
575 .addImm(maxCallFrameSize)
576 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
579 // Discard the DYNALLOC instruction.
583 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
584 /// reserving a whole register (R0), we scrounge for one here. This generates
587 /// mfcr rA ; Move the conditional register into GPR rA.
588 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
589 /// stw rA, FI ; Store rA to the frame.
591 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
592 unsigned FrameIndex, int SPAdj,
593 RegScavenger *RS) const {
594 // Get the instruction.
595 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
596 // Get the instruction's basic block.
597 MachineBasicBlock &MBB = *MI.getParent();
598 DebugLoc dl = MI.getDebugLoc();
600 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
601 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
602 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
603 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
605 // We need to store the CR in the low 4-bits of the saved value. First, issue
606 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
607 if (!MI.getOperand(0).isKill())
608 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg);
610 // Implicitly kill the CR register.
611 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg)
612 .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill);
614 // If the saved register wasn't CR0, shift the bits left so that they are in
616 unsigned SrcReg = MI.getOperand(0).getReg();
617 if (SrcReg != PPC::CR0)
618 // rlwinm rA, rA, ShiftBits, 0, 31.
619 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
620 .addReg(Reg, RegState::Kill)
621 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
625 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
626 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
629 // Discard the pseudo instruction.
633 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
634 int SPAdj, RegScavenger *RS) const {
635 assert(SPAdj == 0 && "Unexpected");
637 // Get the instruction.
638 MachineInstr &MI = *II;
639 // Get the instruction's basic block.
640 MachineBasicBlock &MBB = *MI.getParent();
641 // Get the basic block's function.
642 MachineFunction &MF = *MBB.getParent();
643 // Get the frame info.
644 MachineFrameInfo *MFI = MF.getFrameInfo();
645 DebugLoc dl = MI.getDebugLoc();
647 // Find out which operand is the frame index.
648 unsigned FIOperandNo = 0;
649 while (!MI.getOperand(FIOperandNo).isFI()) {
651 assert(FIOperandNo != MI.getNumOperands() &&
652 "Instr doesn't have FrameIndex operand!");
654 // Take into account whether it's an add or mem instruction
655 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
656 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
657 OffsetOperandNo = FIOperandNo-1;
659 // Get the frame index.
660 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
662 // Get the frame pointer save index. Users of this index are primarily
663 // DYNALLOC instructions.
664 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
665 int FPSI = FI->getFramePointerSaveIndex();
666 // Get the instruction opcode.
667 unsigned OpC = MI.getOpcode();
669 // Special case for dynamic alloca.
670 if (FPSI && FrameIndex == FPSI &&
671 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
672 lowerDynamicAlloc(II, SPAdj, RS);
676 // Special case for pseudo-op SPILL_CR.
677 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
678 if (OpC == PPC::SPILL_CR) {
679 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
683 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
684 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
687 // Figure out if the offset in the instruction is shifted right two bits. This
688 // is true for instructions like "STD", which the machine implicitly adds two
690 bool isIXAddr = false;
700 // Now add the frame object offset to the offset from r1.
701 int Offset = MFI->getObjectOffset(FrameIndex);
703 Offset += MI.getOperand(OffsetOperandNo).getImm();
705 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
707 // If we're not using a Frame Pointer that has been set to the value of the
708 // SP before having the stack size subtracted from it, then add the stack size
709 // to Offset to get the correct offset.
710 Offset += MFI->getStackSize();
712 // If we can, encode the offset directly into the instruction. If this is a
713 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
714 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
715 // clear can be encoded. This is extremely uncommon, because normally you
716 // only "std" to a stack slot that is at least 4-byte aligned, but it can
717 // happen in invalid code.
718 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
720 Offset >>= 2; // The actual encoded value has the low two bits zero.
721 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
725 // The offset doesn't fit into a single register, scavenge one to build the
727 // FIXME: figure out what SPAdj is doing here.
729 // FIXME (64-bit): Use "findScratchRegister".
731 if (EnableRegisterScavenging)
732 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
736 // Insert a set of rA with the full offset value before the ld, st, or add
737 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
738 .addImm(Offset >> 16);
739 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
740 .addReg(SReg, RegState::Kill)
743 // Convert into indexed form of the instruction:
745 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
746 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
747 unsigned OperandBase;
749 if (OpC != TargetInstrInfo::INLINEASM) {
750 assert(ImmToIdxMap.count(OpC) &&
751 "No indexed form of load or store available!");
752 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
753 MI.setDesc(TII.get(NewOpcode));
756 OperandBase = OffsetOperandNo;
759 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
760 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
761 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
764 /// VRRegNo - Map from a numbered VR register to its enum value.
766 static const unsigned short VRRegNo[] = {
767 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
768 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
769 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
770 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
773 /// RemoveVRSaveCode - We have found that this function does not need any code
774 /// to manipulate the VRSAVE register, even though it uses vector registers.
775 /// This can happen when the only registers used are known to be live in or out
776 /// of the function. Remove all of the VRSAVE related code from the function.
777 static void RemoveVRSaveCode(MachineInstr *MI) {
778 MachineBasicBlock *Entry = MI->getParent();
779 MachineFunction *MF = Entry->getParent();
781 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
782 MachineBasicBlock::iterator MBBI = MI;
784 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
785 MBBI->eraseFromParent();
787 bool RemovedAllMTVRSAVEs = true;
788 // See if we can find and remove the MTVRSAVE instruction from all of the
790 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
791 // If last instruction is a return instruction, add an epilogue
792 if (!I->empty() && I->back().getDesc().isReturn()) {
793 bool FoundIt = false;
794 for (MBBI = I->end(); MBBI != I->begin(); ) {
796 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
797 MBBI->eraseFromParent(); // remove it.
802 RemovedAllMTVRSAVEs &= FoundIt;
806 // If we found and removed all MTVRSAVE instructions, remove the read of
808 if (RemovedAllMTVRSAVEs) {
810 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
812 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
813 MBBI->eraseFromParent();
816 // Finally, nuke the UPDATE_VRSAVE.
817 MI->eraseFromParent();
820 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
821 // instruction selector. Based on the vector registers that have been used,
822 // transform this into the appropriate ORI instruction.
823 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
824 MachineFunction *MF = MI->getParent()->getParent();
825 DebugLoc dl = MI->getDebugLoc();
827 unsigned UsedRegMask = 0;
828 for (unsigned i = 0; i != 32; ++i)
829 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
830 UsedRegMask |= 1 << (31-i);
832 // Live in and live out values already must be in the mask, so don't bother
834 for (MachineRegisterInfo::livein_iterator
835 I = MF->getRegInfo().livein_begin(),
836 E = MF->getRegInfo().livein_end(); I != E; ++I) {
837 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
838 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
839 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
841 for (MachineRegisterInfo::liveout_iterator
842 I = MF->getRegInfo().liveout_begin(),
843 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
844 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
845 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
846 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
849 // If no registers are used, turn this into a copy.
850 if (UsedRegMask == 0) {
851 // Remove all VRSAVE code.
852 RemoveVRSaveCode(MI);
856 unsigned SrcReg = MI->getOperand(1).getReg();
857 unsigned DstReg = MI->getOperand(0).getReg();
859 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
860 if (DstReg != SrcReg)
861 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
863 .addImm(UsedRegMask);
865 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
866 .addReg(SrcReg, RegState::Kill)
867 .addImm(UsedRegMask);
868 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
869 if (DstReg != SrcReg)
870 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
872 .addImm(UsedRegMask >> 16);
874 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
875 .addReg(SrcReg, RegState::Kill)
876 .addImm(UsedRegMask >> 16);
878 if (DstReg != SrcReg)
879 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
881 .addImm(UsedRegMask >> 16);
883 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
884 .addReg(SrcReg, RegState::Kill)
885 .addImm(UsedRegMask >> 16);
887 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
888 .addReg(DstReg, RegState::Kill)
889 .addImm(UsedRegMask & 0xFFFF);
892 // Remove the old UPDATE_VRSAVE instruction.
893 MI->eraseFromParent();
896 /// determineFrameLayout - Determine the size of the frame and maximum call
898 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
899 MachineFrameInfo *MFI = MF.getFrameInfo();
901 // Get the number of bytes to allocate from the FrameInfo
902 unsigned FrameSize = MFI->getStackSize();
904 // Get the alignments provided by the target, and the maximum alignment
905 // (if any) of the fixed frame objects.
906 unsigned MaxAlign = MFI->getMaxAlignment();
907 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
908 unsigned AlignMask = TargetAlign - 1; //
910 // If we are a leaf function, and use up to 224 bytes of stack space,
911 // don't have a frame pointer, calls, or dynamic alloca then we do not need
912 // to adjust the stack pointer (we fit in the Red Zone).
913 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
914 // FIXME SVR4 The SVR4 ABI has no red zone.
915 if (!DisableRedZone &&
916 FrameSize <= 224 && // Fits in red zone.
917 !MFI->hasVarSizedObjects() && // No dynamic alloca.
918 !MFI->hasCalls() && // No calls.
919 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
921 MFI->setStackSize(0);
925 // Get the maximum call frame size of all the calls.
926 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
928 // Maximum call frame needs to be at least big enough for linkage and 8 args.
929 unsigned minCallFrameSize =
930 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
931 Subtarget.isDarwinABI());
932 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
934 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
935 // that allocations will be aligned.
936 if (MFI->hasVarSizedObjects())
937 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
939 // Update maximum call frame size.
940 MFI->setMaxCallFrameSize(maxCallFrameSize);
942 // Include call frame size in total.
943 FrameSize += maxCallFrameSize;
945 // Make sure the frame is aligned.
946 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
948 // Update frame info.
949 MFI->setStackSize(FrameSize);
953 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
954 RegScavenger *RS) const {
955 // Save and clear the LR state.
956 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
957 unsigned LR = getRARegister();
958 FI->setMustSaveLR(MustSaveLR(MF, LR));
959 MF.getRegInfo().setPhysRegUnused(LR);
961 // Save R31 if necessary
962 int FPSI = FI->getFramePointerSaveIndex();
963 bool IsPPC64 = Subtarget.isPPC64();
964 bool IsSVR4ABI = Subtarget.isSVR4ABI();
965 bool isDarwinABI = Subtarget.isDarwinABI();
966 MachineFrameInfo *MFI = MF.getFrameInfo();
968 // If the frame pointer save index hasn't been defined yet.
969 if (!FPSI && needsFP(MF) && IsSVR4ABI) {
970 // Find out what the fix offset of the frame pointer save area.
971 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
973 // Allocate the frame index for frame pointer save area.
974 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
976 FI->setFramePointerSaveIndex(FPSI);
979 // Reserve stack space to move the linkage area to in case of a tail call.
981 if (PerformTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
982 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta);
985 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
986 // a large stack, which will require scavenging a register to materialize a
988 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
989 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
992 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
993 if (needsFP(MF) || spillsCR(MF)) {
994 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
995 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
996 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
997 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
998 RC->getAlignment()));
1003 PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
1005 // Early exit if not using the SVR4 ABI.
1006 if (!Subtarget.isSVR4ABI()) {
1010 // Get callee saved register information.
1011 MachineFrameInfo *FFI = MF.getFrameInfo();
1012 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1014 // Early exit if no callee saved registers are modified!
1015 if (CSI.empty() && !needsFP(MF)) {
1019 unsigned MinGPR = PPC::R31;
1020 unsigned MinFPR = PPC::F31;
1021 unsigned MinVR = PPC::V31;
1023 bool HasGPSaveArea = false;
1024 bool HasFPSaveArea = false;
1025 bool HasCRSaveArea = false;
1026 bool HasVRSAVESaveArea = false;
1027 bool HasVRSaveArea = false;
1029 SmallVector<CalleeSavedInfo, 18> GPRegs;
1030 SmallVector<CalleeSavedInfo, 18> FPRegs;
1031 SmallVector<CalleeSavedInfo, 18> VRegs;
1033 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1034 unsigned Reg = CSI[i].getReg();
1035 const TargetRegisterClass *RC = CSI[i].getRegClass();
1037 if (RC == PPC::GPRCRegisterClass) {
1038 HasGPSaveArea = true;
1040 GPRegs.push_back(CSI[i]);
1045 } else if (RC == PPC::F8RCRegisterClass) {
1046 HasFPSaveArea = true;
1048 FPRegs.push_back(CSI[i]);
1053 // FIXME SVR4: Disable CR save area for now.
1054 } else if ( RC == PPC::CRBITRCRegisterClass
1055 || RC == PPC::CRRCRegisterClass) {
1056 // HasCRSaveArea = true;
1057 } else if (RC == PPC::VRSAVERCRegisterClass) {
1058 HasVRSAVESaveArea = true;
1059 } else if (RC == PPC::VRRCRegisterClass) {
1060 HasVRSaveArea = true;
1062 VRegs.push_back(CSI[i]);
1068 assert(0 && "Unknown RegisterClass!");
1072 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1074 int64_t LowerBound = 0;
1076 // Take into account stack space reserved for tail calls.
1078 if (PerformTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1079 LowerBound = TCSPDelta;
1082 // The Floating-point register save area is right below the back chain word
1083 // of the previous stack frame.
1084 if (HasFPSaveArea) {
1085 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1086 int FI = FPRegs[i].getFrameIdx();
1088 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1091 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8;
1094 // Check whether the frame pointer register is allocated. If so, make sure it
1095 // is spilled to the correct offset.
1097 HasGPSaveArea = true;
1099 int FI = PFI->getFramePointerSaveIndex();
1100 assert(FI && "No Frame Pointer Save Slot!");
1102 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1105 // General register save area starts right below the Floating-point
1106 // register save area.
1107 if (HasGPSaveArea) {
1108 // Move general register save area spill slots down, taking into account
1109 // the size of the Floating-point register save area.
1110 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1111 int FI = GPRegs[i].getFrameIdx();
1113 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1116 LowerBound -= (31 - getRegisterNumbering(MinGPR) + 1) * 4;
1119 // The CR save area is below the general register save area.
1120 if (HasCRSaveArea) {
1121 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1122 // which have the CR/CRBIT register class?
1123 // Adjust the frame index of the CR spill slot.
1124 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1125 const TargetRegisterClass *RC = CSI[i].getRegClass();
1127 if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) {
1128 int FI = CSI[i].getFrameIdx();
1130 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1134 LowerBound -= 4; // The CR save area is always 4 bytes long.
1137 if (HasVRSAVESaveArea) {
1138 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1139 // which have the VRSAVE register class?
1140 // Adjust the frame index of the VRSAVE spill slot.
1141 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1142 const TargetRegisterClass *RC = CSI[i].getRegClass();
1144 if (RC == PPC::VRSAVERCRegisterClass) {
1145 int FI = CSI[i].getFrameIdx();
1147 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1151 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1154 if (HasVRSaveArea) {
1155 // Insert alignment padding, we need 16-byte alignment.
1156 LowerBound = (LowerBound - 15) & ~(15);
1158 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1159 int FI = VRegs[i].getFrameIdx();
1161 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1167 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
1168 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1169 MachineBasicBlock::iterator MBBI = MBB.begin();
1170 MachineFrameInfo *MFI = MF.getFrameInfo();
1171 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1172 DebugLoc dl = DebugLoc::getUnknownLoc();
1173 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
1174 !MF.getFunction()->doesNotThrow() ||
1175 UnwindTablesMandatory;
1177 // Prepare for frame info.
1178 unsigned FrameLabelId = 0;
1180 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
1182 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
1183 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
1184 HandleVRSaveUpdate(MBBI, TII);
1189 // Move MBBI back to the beginning of the function.
1192 // Work out frame sizes.
1193 determineFrameLayout(MF);
1194 unsigned FrameSize = MFI->getStackSize();
1196 int NegFrameSize = -FrameSize;
1198 // Get processor type.
1199 bool IsPPC64 = Subtarget.isPPC64();
1200 // Get operating system
1201 bool isDarwinABI = Subtarget.isDarwinABI();
1202 // Check if the link register (LR) must be saved.
1203 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1204 bool MustSaveLR = FI->mustSaveLR();
1205 // Do we have a frame pointer for this function?
1206 bool HasFP = hasFP(MF) && FrameSize;
1208 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
1212 if (Subtarget.isSVR4ABI()) {
1213 MachineFrameInfo *FFI = MF.getFrameInfo();
1214 int FPIndex = FI->getFramePointerSaveIndex();
1215 assert(FPIndex && "No Frame Pointer Save Slot!");
1216 FPOffset = FFI->getObjectOffset(FPIndex);
1218 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
1224 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
1227 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1233 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1235 .addImm(LROffset / 4)
1239 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
1242 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1248 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1254 // Skip if a leaf routine.
1255 if (!FrameSize) return;
1257 // Get stack alignments.
1258 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1259 unsigned MaxAlign = MFI->getMaxAlignment();
1261 if (needsFrameMoves) {
1262 // Mark effective beginning of when frame pointer becomes valid.
1263 FrameLabelId = MMI->NextLabelID();
1264 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
1267 // Adjust stack pointer: r1 += NegFrameSize.
1268 // If there is a preferred stack alignment, align R1 now
1271 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1272 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1273 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1275 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
1278 .addImm(32 - Log2_32(MaxAlign))
1280 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
1281 .addReg(PPC::R0, RegState::Kill)
1282 .addImm(NegFrameSize);
1283 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1287 } else if (isInt16(NegFrameSize)) {
1288 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
1290 .addImm(NegFrameSize)
1293 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1294 .addImm(NegFrameSize >> 16);
1295 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1296 .addReg(PPC::R0, RegState::Kill)
1297 .addImm(NegFrameSize & 0xFFFF);
1298 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1304 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1305 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1306 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1308 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
1311 .addImm(64 - Log2_32(MaxAlign));
1312 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
1314 .addImm(NegFrameSize);
1315 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1319 } else if (isInt16(NegFrameSize)) {
1320 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
1322 .addImm(NegFrameSize / 4)
1325 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1326 .addImm(NegFrameSize >> 16);
1327 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1328 .addReg(PPC::X0, RegState::Kill)
1329 .addImm(NegFrameSize & 0xFFFF);
1330 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1337 if (needsFrameMoves) {
1338 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1341 // Show update of SP.
1342 MachineLocation SPDst(MachineLocation::VirtualFP);
1343 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1344 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1346 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1347 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1351 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1352 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1353 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1356 // Add callee saved registers to move list.
1357 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1358 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1359 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1360 unsigned Reg = CSI[I].getReg();
1361 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1362 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1363 MachineLocation CSSrc(Reg);
1364 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1367 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1368 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1369 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1371 // Mark effective beginning of when frame pointer is ready.
1372 unsigned ReadyLabelId = MMI->NextLabelID();
1373 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
1375 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1376 (IsPPC64 ? PPC::X1 : PPC::R1));
1377 MachineLocation FPSrc(MachineLocation::VirtualFP);
1378 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1381 // If there is a frame pointer, copy R1 into R31
1384 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
1388 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
1395 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1396 MachineBasicBlock &MBB) const {
1397 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1398 unsigned RetOpcode = MBBI->getOpcode();
1399 DebugLoc dl = DebugLoc::getUnknownLoc();
1401 assert( (RetOpcode == PPC::BLR ||
1402 RetOpcode == PPC::TCRETURNri ||
1403 RetOpcode == PPC::TCRETURNdi ||
1404 RetOpcode == PPC::TCRETURNai ||
1405 RetOpcode == PPC::TCRETURNri8 ||
1406 RetOpcode == PPC::TCRETURNdi8 ||
1407 RetOpcode == PPC::TCRETURNai8) &&
1408 "Can only insert epilog into returning blocks");
1410 // Get alignment info so we know how to restore r1
1411 const MachineFrameInfo *MFI = MF.getFrameInfo();
1412 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1413 unsigned MaxAlign = MFI->getMaxAlignment();
1415 // Get the number of bytes allocated from the FrameInfo.
1416 int FrameSize = MFI->getStackSize();
1418 // Get processor type.
1419 bool IsPPC64 = Subtarget.isPPC64();
1420 // Get operating system
1421 bool isDarwinABI = Subtarget.isDarwinABI();
1422 // Check if the link register (LR) has been saved.
1423 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1424 bool MustSaveLR = FI->mustSaveLR();
1425 // Do we have a frame pointer for this function?
1426 bool HasFP = hasFP(MF) && FrameSize;
1428 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
1432 if (Subtarget.isSVR4ABI()) {
1433 MachineFrameInfo *FFI = MF.getFrameInfo();
1434 int FPIndex = FI->getFramePointerSaveIndex();
1435 assert(FPIndex && "No Frame Pointer Save Slot!");
1436 FPOffset = FFI->getObjectOffset(FPIndex);
1438 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
1442 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1443 RetOpcode == PPC::TCRETURNdi ||
1444 RetOpcode == PPC::TCRETURNai ||
1445 RetOpcode == PPC::TCRETURNri8 ||
1446 RetOpcode == PPC::TCRETURNdi8 ||
1447 RetOpcode == PPC::TCRETURNai8;
1450 int MaxTCRetDelta = FI->getTailCallSPDelta();
1451 MachineOperand &StackAdjust = MBBI->getOperand(1);
1452 assert(StackAdjust.isImm() && "Expecting immediate value.");
1453 // Adjust stack pointer.
1454 int StackAdj = StackAdjust.getImm();
1455 int Delta = StackAdj - MaxTCRetDelta;
1456 assert((Delta >= 0) && "Delta must be positive");
1457 if (MaxTCRetDelta>0)
1458 FrameSize += (StackAdj +Delta);
1460 FrameSize += StackAdj;
1464 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1465 // on entry to the function. Add this offset back now.
1467 // If this function contained a fastcc call and PerformTailCallOpt is
1468 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1469 // call which invalidates the stack pointer value in SP(0). So we use the
1470 // value of R31 in this case.
1471 if (FI->hasFastCall() && isInt16(FrameSize)) {
1472 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1473 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1474 .addReg(PPC::R31).addImm(FrameSize);
1475 } else if(FI->hasFastCall()) {
1476 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1477 .addImm(FrameSize >> 16);
1478 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1479 .addReg(PPC::R0, RegState::Kill)
1480 .addImm(FrameSize & 0xFFFF);
1481 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
1485 } else if (isInt16(FrameSize) &&
1486 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1487 !MFI->hasVarSizedObjects()) {
1488 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1489 .addReg(PPC::R1).addImm(FrameSize);
1491 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
1492 .addImm(0).addReg(PPC::R1);
1495 if (FI->hasFastCall() && isInt16(FrameSize)) {
1496 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1497 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1498 .addReg(PPC::X31).addImm(FrameSize);
1499 } else if(FI->hasFastCall()) {
1500 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1501 .addImm(FrameSize >> 16);
1502 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1503 .addReg(PPC::X0, RegState::Kill)
1504 .addImm(FrameSize & 0xFFFF);
1505 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
1509 } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1510 !MFI->hasVarSizedObjects()) {
1511 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1512 .addReg(PPC::X1).addImm(FrameSize);
1514 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
1515 .addImm(0).addReg(PPC::X1);
1522 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
1523 .addImm(LROffset/4).addReg(PPC::X1);
1526 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
1527 .addImm(FPOffset/4).addReg(PPC::X1);
1530 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1533 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
1534 .addImm(LROffset).addReg(PPC::R1);
1537 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
1538 .addImm(FPOffset).addReg(PPC::R1);
1541 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
1544 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1545 // call optimization
1546 if (PerformTailCallOpt && RetOpcode == PPC::BLR &&
1547 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1548 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1549 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1550 unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1;
1551 unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31;
1552 unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0;
1553 unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI;
1554 unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4;
1555 unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS;
1556 unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI;
1558 if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
1559 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
1560 .addReg(StackReg).addImm(CallerAllocatedAmt);
1562 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1563 .addImm(CallerAllocatedAmt >> 16);
1564 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1565 .addReg(TmpReg, RegState::Kill)
1566 .addImm(CallerAllocatedAmt & 0xFFFF);
1567 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
1572 } else if (RetOpcode == PPC::TCRETURNdi) {
1573 MBBI = prior(MBB.end());
1574 MachineOperand &JumpTarget = MBBI->getOperand(0);
1575 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1576 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1577 } else if (RetOpcode == PPC::TCRETURNri) {
1578 MBBI = prior(MBB.end());
1579 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1580 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1581 } else if (RetOpcode == PPC::TCRETURNai) {
1582 MBBI = prior(MBB.end());
1583 MachineOperand &JumpTarget = MBBI->getOperand(0);
1584 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1585 } else if (RetOpcode == PPC::TCRETURNdi8) {
1586 MBBI = prior(MBB.end());
1587 MachineOperand &JumpTarget = MBBI->getOperand(0);
1588 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1589 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1590 } else if (RetOpcode == PPC::TCRETURNri8) {
1591 MBBI = prior(MBB.end());
1592 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1593 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1594 } else if (RetOpcode == PPC::TCRETURNai8) {
1595 MBBI = prior(MBB.end());
1596 MachineOperand &JumpTarget = MBBI->getOperand(0);
1597 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1601 unsigned PPCRegisterInfo::getRARegister() const {
1602 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1605 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1606 if (!Subtarget.isPPC64())
1607 return hasFP(MF) ? PPC::R31 : PPC::R1;
1609 return hasFP(MF) ? PPC::X31 : PPC::X1;
1612 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1614 // Initial state of the frame pointer is R1.
1615 MachineLocation Dst(MachineLocation::VirtualFP);
1616 MachineLocation Src(PPC::R1, 0);
1617 Moves.push_back(MachineMove(0, Dst, Src));
1620 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1621 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1624 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1625 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1628 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1629 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1630 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1633 #include "PPCGenRegisterInfo.inc"