1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Target/TargetAsmInfo.h"
26 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
27 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
29 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31 RI(*TM.getSubtargetImpl(), *this) {}
33 /// getPointerRegClass - Return the register class to use to hold pointers.
34 /// This is used for addressing modes.
35 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
36 if (TM.getSubtargetImpl()->isPPC64())
37 return &PPC::G8RCRegClass;
39 return &PPC::GPRCRegClass;
43 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
46 unsigned& sourceSubIdx,
47 unsigned& destSubIdx) const {
48 sourceSubIdx = destSubIdx = 0; // No sub-registers.
50 unsigned oc = MI.getOpcode();
51 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
52 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
53 assert(MI.getNumOperands() >= 3 &&
54 MI.getOperand(0).isReg() &&
55 MI.getOperand(1).isReg() &&
56 MI.getOperand(2).isReg() &&
57 "invalid PPC OR instruction!");
58 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
59 sourceReg = MI.getOperand(1).getReg();
60 destReg = MI.getOperand(0).getReg();
63 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
64 assert(MI.getNumOperands() >= 3 &&
65 MI.getOperand(0).isReg() &&
66 MI.getOperand(2).isImm() &&
67 "invalid PPC ADDI instruction!");
68 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
69 sourceReg = MI.getOperand(1).getReg();
70 destReg = MI.getOperand(0).getReg();
73 } else if (oc == PPC::ORI) { // ori r1, r2, 0
74 assert(MI.getNumOperands() >= 3 &&
75 MI.getOperand(0).isReg() &&
76 MI.getOperand(1).isReg() &&
77 MI.getOperand(2).isImm() &&
78 "invalid PPC ORI instruction!");
79 if (MI.getOperand(2).getImm() == 0) {
80 sourceReg = MI.getOperand(1).getReg();
81 destReg = MI.getOperand(0).getReg();
84 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
85 oc == PPC::FMRSD) { // fmr r1, r2
86 assert(MI.getNumOperands() >= 2 &&
87 MI.getOperand(0).isReg() &&
88 MI.getOperand(1).isReg() &&
89 "invalid PPC FMR instruction");
90 sourceReg = MI.getOperand(1).getReg();
91 destReg = MI.getOperand(0).getReg();
93 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
94 assert(MI.getNumOperands() >= 2 &&
95 MI.getOperand(0).isReg() &&
96 MI.getOperand(1).isReg() &&
97 "invalid PPC MCRF instruction");
98 sourceReg = MI.getOperand(1).getReg();
99 destReg = MI.getOperand(0).getReg();
105 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
106 int &FrameIndex) const {
107 switch (MI->getOpcode()) {
113 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
114 MI->getOperand(2).isFI()) {
115 FrameIndex = MI->getOperand(2).getIndex();
116 return MI->getOperand(0).getReg();
123 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
124 int &FrameIndex) const {
125 switch (MI->getOpcode()) {
131 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
132 MI->getOperand(2).isFI()) {
133 FrameIndex = MI->getOperand(2).getIndex();
134 return MI->getOperand(0).getReg();
141 // commuteInstruction - We can commute rlwimi instructions, but only if the
142 // rotate amt is zero. We also have to munge the immediates a bit.
144 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
145 MachineFunction &MF = *MI->getParent()->getParent();
147 // Normal instructions can be commuted the obvious way.
148 if (MI->getOpcode() != PPC::RLWIMI)
149 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
151 // Cannot commute if it has a non-zero rotate count.
152 if (MI->getOperand(3).getImm() != 0)
155 // If we have a zero rotate count, we have:
157 // Op0 = (Op1 & ~M) | (Op2 & M)
159 // M = mask((ME+1)&31, (MB-1)&31)
160 // Op0 = (Op2 & ~M) | (Op1 & M)
163 unsigned Reg0 = MI->getOperand(0).getReg();
164 unsigned Reg1 = MI->getOperand(1).getReg();
165 unsigned Reg2 = MI->getOperand(2).getReg();
166 bool Reg1IsKill = MI->getOperand(1).isKill();
167 bool Reg2IsKill = MI->getOperand(2).isKill();
168 bool ChangeReg0 = false;
169 // If machine instrs are no longer in two-address forms, update
170 // destination register as well.
172 // Must be two address instruction!
173 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
174 "Expecting a two-address instruction!");
180 unsigned MB = MI->getOperand(4).getImm();
181 unsigned ME = MI->getOperand(5).getImm();
184 // Create a new instruction.
185 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
186 bool Reg0IsDead = MI->getOperand(0).isDead();
187 return BuildMI(MF, MI->getDesc())
188 .addReg(Reg0, true, false, false, Reg0IsDead)
189 .addReg(Reg2, false, false, Reg2IsKill)
190 .addReg(Reg1, false, false, Reg1IsKill)
192 .addImm((MB-1) & 31);
196 MI->getOperand(0).setReg(Reg2);
197 MI->getOperand(2).setReg(Reg1);
198 MI->getOperand(1).setReg(Reg2);
199 MI->getOperand(2).setIsKill(Reg1IsKill);
200 MI->getOperand(1).setIsKill(Reg2IsKill);
202 // Swap the mask around.
203 MI->getOperand(4).setImm((ME+1) & 31);
204 MI->getOperand(5).setImm((MB-1) & 31);
208 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
209 MachineBasicBlock::iterator MI) const {
210 BuildMI(MBB, MI, get(PPC::NOP));
215 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
216 MachineBasicBlock *&FBB,
217 SmallVectorImpl<MachineOperand> &Cond) const {
218 // If the block has no terminators, it just falls into the block after it.
219 MachineBasicBlock::iterator I = MBB.end();
220 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
223 // Get the last instruction in the block.
224 MachineInstr *LastInst = I;
226 // If there is only one terminator instruction, process it.
227 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
228 if (LastInst->getOpcode() == PPC::B) {
229 TBB = LastInst->getOperand(0).getMBB();
231 } else if (LastInst->getOpcode() == PPC::BCC) {
232 // Block ends with fall-through condbranch.
233 TBB = LastInst->getOperand(2).getMBB();
234 Cond.push_back(LastInst->getOperand(0));
235 Cond.push_back(LastInst->getOperand(1));
238 // Otherwise, don't know what this is.
242 // Get the instruction before it if it's a terminator.
243 MachineInstr *SecondLastInst = I;
245 // If there are three terminators, we don't know what sort of block this is.
246 if (SecondLastInst && I != MBB.begin() &&
247 isUnpredicatedTerminator(--I))
250 // If the block ends with PPC::B and PPC:BCC, handle it.
251 if (SecondLastInst->getOpcode() == PPC::BCC &&
252 LastInst->getOpcode() == PPC::B) {
253 TBB = SecondLastInst->getOperand(2).getMBB();
254 Cond.push_back(SecondLastInst->getOperand(0));
255 Cond.push_back(SecondLastInst->getOperand(1));
256 FBB = LastInst->getOperand(0).getMBB();
260 // If the block ends with two PPC:Bs, handle it. The second one is not
261 // executed, so remove it.
262 if (SecondLastInst->getOpcode() == PPC::B &&
263 LastInst->getOpcode() == PPC::B) {
264 TBB = SecondLastInst->getOperand(0).getMBB();
266 I->eraseFromParent();
270 // Otherwise, can't handle this.
274 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
275 MachineBasicBlock::iterator I = MBB.end();
276 if (I == MBB.begin()) return 0;
278 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
281 // Remove the branch.
282 I->eraseFromParent();
286 if (I == MBB.begin()) return 1;
288 if (I->getOpcode() != PPC::BCC)
291 // Remove the branch.
292 I->eraseFromParent();
297 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
298 MachineBasicBlock *FBB,
299 const SmallVectorImpl<MachineOperand> &Cond) const {
300 // Shouldn't be a fall through.
301 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
302 assert((Cond.size() == 2 || Cond.size() == 0) &&
303 "PPC branch conditions have two components!");
307 if (Cond.empty()) // Unconditional branch
308 BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
309 else // Conditional branch
310 BuildMI(&MBB, get(PPC::BCC))
311 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
315 // Two-way Conditional Branch.
316 BuildMI(&MBB, get(PPC::BCC))
317 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
318 BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
322 bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
323 MachineBasicBlock::iterator MI,
324 unsigned DestReg, unsigned SrcReg,
325 const TargetRegisterClass *DestRC,
326 const TargetRegisterClass *SrcRC) const {
327 if (DestRC != SrcRC) {
328 // Not yet supported!
332 if (DestRC == PPC::GPRCRegisterClass) {
333 BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
334 } else if (DestRC == PPC::G8RCRegisterClass) {
335 BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
336 } else if (DestRC == PPC::F4RCRegisterClass) {
337 BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
338 } else if (DestRC == PPC::F8RCRegisterClass) {
339 BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
340 } else if (DestRC == PPC::CRRCRegisterClass) {
341 BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
342 } else if (DestRC == PPC::VRRCRegisterClass) {
343 BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
344 } else if (DestRC == PPC::CRBITRCRegisterClass) {
345 BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
347 // Attempt to copy register that is not GPR or FPR
355 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
356 unsigned SrcReg, bool isKill,
358 const TargetRegisterClass *RC,
359 SmallVectorImpl<MachineInstr*> &NewMIs) const{
360 if (RC == PPC::GPRCRegisterClass) {
361 if (SrcReg != PPC::LR) {
362 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
363 .addReg(SrcReg, false, false, isKill),
366 // FIXME: this spills LR immediately to memory in one step. To do this,
367 // we use R11, which we know cannot be used in the prolog/epilog. This is
369 NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
370 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
371 .addReg(PPC::R11, false, false, isKill),
374 } else if (RC == PPC::G8RCRegisterClass) {
375 if (SrcReg != PPC::LR8) {
376 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
377 .addReg(SrcReg, false, false, isKill), FrameIdx));
379 // FIXME: this spills LR immediately to memory in one step. To do this,
380 // we use R11, which we know cannot be used in the prolog/epilog. This is
382 NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
383 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
384 .addReg(PPC::X11, false, false, isKill), FrameIdx));
386 } else if (RC == PPC::F8RCRegisterClass) {
387 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
388 .addReg(SrcReg, false, false, isKill), FrameIdx));
389 } else if (RC == PPC::F4RCRegisterClass) {
390 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
391 .addReg(SrcReg, false, false, isKill), FrameIdx));
392 } else if (RC == PPC::CRRCRegisterClass) {
393 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
394 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
395 // FIXME (64-bit): Enable
396 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
397 .addReg(SrcReg, false, false, isKill),
401 // FIXME: We use R0 here, because it isn't available for RA. We need to
402 // store the CR in the low 4-bits of the saved value. First, issue a MFCR
403 // to save all of the CRBits.
404 NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
406 // If the saved register wasn't CR0, shift the bits left so that they are
408 if (SrcReg != PPC::CR0) {
409 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
410 // rlwinm r0, r0, ShiftBits, 0, 31.
411 NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
412 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
415 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
416 .addReg(PPC::R0, false, false, isKill),
419 } else if (RC == PPC::CRBITRCRegisterClass) {
420 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
421 // backend currently only uses CR1EQ as an individual bit, this should
422 // not cause any bug. If we need other uses of CR bits, the following
423 // code may be invalid.
425 if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
427 else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
429 else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
431 else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
433 else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
435 else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
437 else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
439 else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
442 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
443 PPC::CRRCRegisterClass, NewMIs);
445 } else if (RC == PPC::VRRCRegisterClass) {
446 // We don't have indexed addressing for vector loads. Emit:
450 // FIXME: We use R0 here, because it isn't available for RA.
451 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
453 NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
454 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
456 assert(0 && "Unknown regclass!");
464 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
465 MachineBasicBlock::iterator MI,
466 unsigned SrcReg, bool isKill, int FrameIdx,
467 const TargetRegisterClass *RC) const {
468 MachineFunction &MF = *MBB.getParent();
469 SmallVector<MachineInstr*, 4> NewMIs;
471 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
472 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
473 FuncInfo->setSpillsCR();
476 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
477 MBB.insert(MI, NewMIs[i]);
480 void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
482 SmallVectorImpl<MachineOperand> &Addr,
483 const TargetRegisterClass *RC,
484 SmallVectorImpl<MachineInstr*> &NewMIs) const{
485 if (Addr[0].isFI()) {
486 if (StoreRegToStackSlot(MF, SrcReg, isKill,
487 Addr[0].getIndex(), RC, NewMIs)) {
488 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
489 FuncInfo->setSpillsCR();
496 if (RC == PPC::GPRCRegisterClass) {
498 } else if (RC == PPC::G8RCRegisterClass) {
500 } else if (RC == PPC::F8RCRegisterClass) {
502 } else if (RC == PPC::F4RCRegisterClass) {
504 } else if (RC == PPC::VRRCRegisterClass) {
507 assert(0 && "Unknown regclass!");
510 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
511 .addReg(SrcReg, false, false, isKill);
512 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
513 MachineOperand &MO = Addr[i];
515 MIB.addReg(MO.getReg());
517 MIB.addImm(MO.getImm());
519 MIB.addFrameIndex(MO.getIndex());
521 NewMIs.push_back(MIB);
526 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
527 unsigned DestReg, int FrameIdx,
528 const TargetRegisterClass *RC,
529 SmallVectorImpl<MachineInstr*> &NewMIs)const{
530 if (RC == PPC::GPRCRegisterClass) {
531 if (DestReg != PPC::LR) {
532 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
535 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
537 NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
539 } else if (RC == PPC::G8RCRegisterClass) {
540 if (DestReg != PPC::LR8) {
541 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
544 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
546 NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
548 } else if (RC == PPC::F8RCRegisterClass) {
549 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
551 } else if (RC == PPC::F4RCRegisterClass) {
552 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
554 } else if (RC == PPC::CRRCRegisterClass) {
555 // FIXME: We use R0 here, because it isn't available for RA.
556 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
559 // If the reloaded register isn't CR0, shift the bits right so that they are
560 // in the right CR's slot.
561 if (DestReg != PPC::CR0) {
562 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
563 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
564 NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
565 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
568 NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
569 } else if (RC == PPC::CRBITRCRegisterClass) {
572 if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
574 else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
576 else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
578 else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
580 else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
582 else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
584 else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
586 else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
589 return LoadRegFromStackSlot(MF, Reg, FrameIdx,
590 PPC::CRRCRegisterClass, NewMIs);
592 } else if (RC == PPC::VRRCRegisterClass) {
593 // We don't have indexed addressing for vector loads. Emit:
597 // FIXME: We use R0 here, because it isn't available for RA.
598 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
600 NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
603 assert(0 && "Unknown regclass!");
609 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
610 MachineBasicBlock::iterator MI,
611 unsigned DestReg, int FrameIdx,
612 const TargetRegisterClass *RC) const {
613 MachineFunction &MF = *MBB.getParent();
614 SmallVector<MachineInstr*, 4> NewMIs;
615 LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
616 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
617 MBB.insert(MI, NewMIs[i]);
620 void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
621 SmallVectorImpl<MachineOperand> &Addr,
622 const TargetRegisterClass *RC,
623 SmallVectorImpl<MachineInstr*> &NewMIs)const{
624 if (Addr[0].isFI()) {
625 LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
630 if (RC == PPC::GPRCRegisterClass) {
631 assert(DestReg != PPC::LR && "Can't handle this yet!");
633 } else if (RC == PPC::G8RCRegisterClass) {
634 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
636 } else if (RC == PPC::F8RCRegisterClass) {
638 } else if (RC == PPC::F4RCRegisterClass) {
640 } else if (RC == PPC::VRRCRegisterClass) {
643 assert(0 && "Unknown regclass!");
646 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
647 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
648 MachineOperand &MO = Addr[i];
650 MIB.addReg(MO.getReg());
652 MIB.addImm(MO.getImm());
654 MIB.addFrameIndex(MO.getIndex());
656 NewMIs.push_back(MIB);
660 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
661 /// copy instructions, turning them into load/store instructions.
662 MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
664 const SmallVectorImpl<unsigned> &Ops,
665 int FrameIndex) const {
666 if (Ops.size() != 1) return NULL;
668 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
669 // it takes more than one instruction to store it.
670 unsigned Opc = MI->getOpcode();
671 unsigned OpNum = Ops[0];
673 MachineInstr *NewMI = NULL;
674 if ((Opc == PPC::OR &&
675 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
676 if (OpNum == 0) { // move -> store
677 unsigned InReg = MI->getOperand(1).getReg();
678 bool isKill = MI->getOperand(1).isKill();
679 NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
680 .addReg(InReg, false, false, isKill),
682 } else { // move -> load
683 unsigned OutReg = MI->getOperand(0).getReg();
684 bool isDead = MI->getOperand(0).isDead();
685 NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
686 .addReg(OutReg, true, false, false, isDead),
689 } else if ((Opc == PPC::OR8 &&
690 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
691 if (OpNum == 0) { // move -> store
692 unsigned InReg = MI->getOperand(1).getReg();
693 bool isKill = MI->getOperand(1).isKill();
694 NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
695 .addReg(InReg, false, false, isKill),
697 } else { // move -> load
698 unsigned OutReg = MI->getOperand(0).getReg();
699 bool isDead = MI->getOperand(0).isDead();
700 NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
701 .addReg(OutReg, true, false, false, isDead),
704 } else if (Opc == PPC::FMRD) {
705 if (OpNum == 0) { // move -> store
706 unsigned InReg = MI->getOperand(1).getReg();
707 bool isKill = MI->getOperand(1).isKill();
708 NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
709 .addReg(InReg, false, false, isKill),
711 } else { // move -> load
712 unsigned OutReg = MI->getOperand(0).getReg();
713 bool isDead = MI->getOperand(0).isDead();
714 NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
715 .addReg(OutReg, true, false, false, isDead),
718 } else if (Opc == PPC::FMRS) {
719 if (OpNum == 0) { // move -> store
720 unsigned InReg = MI->getOperand(1).getReg();
721 bool isKill = MI->getOperand(1).isKill();
722 NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
723 .addReg(InReg, false, false, isKill),
725 } else { // move -> load
726 unsigned OutReg = MI->getOperand(0).getReg();
727 bool isDead = MI->getOperand(0).isDead();
728 NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
729 .addReg(OutReg, true, false, false, isDead),
737 bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
738 const SmallVectorImpl<unsigned> &Ops) const {
739 if (Ops.size() != 1) return false;
741 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
742 // it takes more than one instruction to store it.
743 unsigned Opc = MI->getOpcode();
745 if ((Opc == PPC::OR &&
746 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
748 else if ((Opc == PPC::OR8 &&
749 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
751 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
758 bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
759 if (MBB.empty()) return false;
761 switch (MBB.back().getOpcode()) {
762 case PPC::BLR: // Return.
763 case PPC::B: // Uncond branch.
764 case PPC::BCTR: // Indirect branch.
766 default: return false;
771 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
772 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
773 // Leave the CR# the same, but invert the condition.
774 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
778 /// GetInstSize - Return the number of bytes of code the specified
779 /// instruction may be. This returns the maximum number of bytes.
781 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
782 switch (MI->getOpcode()) {
783 case PPC::INLINEASM: { // Inline Asm: Variable size.
784 const MachineFunction *MF = MI->getParent()->getParent();
785 const char *AsmStr = MI->getOperand(0).getSymbolName();
786 return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
793 return 4; // PowerPC instructions are all 4 bytes