1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/Target/TargetLowering.h"
29 // Start the numbering where the builtin ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
32 /// FSEL - Traditional three-operand fsel node.
36 /// FCFID - The FCFID instruction, taking an f64 operand and producing
37 /// and f64 value containing the FP representation of the integer that
38 /// was temporarily in the f64 operand.
41 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
42 /// unsigned integers and single-precision outputs.
43 FCFIDU, FCFIDS, FCFIDUS,
45 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
46 /// operand, producing an f64 value containing the integer representation
50 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
51 /// unsigned integers.
54 /// Reciprocal estimate instructions (unary FP ops).
57 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
58 // three v4f32 operands and producing a v4f32 result.
61 /// VPERM - The PPC VPERM Instruction.
65 /// Hi/Lo - These represent the high and low 16-bit parts of a global
66 /// address respectively. These nodes have two operands, the first of
67 /// which must be a TargetGlobalAddress, and the second of which must be a
68 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
69 /// though these are usually folded into other nodes.
74 /// The following three target-specific nodes are used for calls through
75 /// function pointers in the 64-bit SVR4 ABI.
77 /// Restore the TOC from the TOC save area of the current stack frame.
78 /// This is basically a hard coded load instruction which additionally
79 /// takes/produces a flag.
82 /// Like a regular LOAD but additionally taking/producing a flag.
85 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
86 /// a hard coded load instruction.
89 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
90 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
91 /// compute an allocation on the stack.
94 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
95 /// at function entry, used for PIC code.
98 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
99 /// shift amounts. These nodes are generated by the multi-precision shift
103 /// CALL - A direct function call.
104 /// CALL_NOP is a call with the special NOP which follows 64-bit
108 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
109 /// MTCTR instruction.
112 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
113 /// BCTRL instruction.
116 /// Return with a flag operand, matched by 'blr'
119 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
120 /// This copies the bits corresponding to the specified CRREG into the
121 /// resultant GPR. Bits corresponding to other CR regs are undefined.
124 // FIXME: Remove these once the ANDI glue bug is fixed:
125 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
126 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
127 /// implement truncation of i32 or i64 to i1.
128 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
130 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
133 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
136 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
137 /// instructions. For lack of better number, we use the opcode number
138 /// encoding for the OPC field to identify the compare. For example, 838
142 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
143 /// altivec VCMP*o instructions. For lack of better number, we use the
144 /// opcode number encoding for the OPC field to identify the compare. For
145 /// example, 838 is VCMPGTSH.
148 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
149 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
150 /// condition register to branch on, OPC is the branch opcode to use (e.g.
151 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
152 /// an optional input flag argument.
155 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
159 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
160 /// towards zero. Used only as part of the long double-to-int
161 /// conversion sequence.
164 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
167 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
168 /// reserve indexed. This is used to implement atomic operations.
171 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
172 /// indexed. This is used to implement atomic operations.
175 /// TC_RETURN - A tail call return.
177 /// operand #1 callee (register or absolute)
178 /// operand #2 stack adjustment
179 /// operand #3 optional in flag
182 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
186 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
190 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
191 /// TLS model, produces an ADDIS8 instruction that adds the GOT
192 /// base to sym\@got\@tprel\@ha.
195 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
196 /// TLS model, produces a LD instruction with base register G8RReg
197 /// and offset sym\@got\@tprel\@l. This completes the addition that
198 /// finds the offset of "sym" relative to the thread pointer.
201 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
202 /// model, produces an ADD instruction that adds the contents of
203 /// G8RReg to the thread pointer. Symbol contains a relocation
204 /// sym\@tls which is to be replaced by the thread pointer and
205 /// identifies to the linker that the instruction is part of a
209 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
210 /// model, produces an ADDIS8 instruction that adds the GOT base
211 /// register to sym\@got\@tlsgd\@ha.
214 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
215 /// model, produces an ADDI8 instruction that adds G8RReg to
216 /// sym\@got\@tlsgd\@l.
219 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
220 /// model, produces a call to __tls_get_addr(sym\@tlsgd).
223 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
224 /// model, produces an ADDIS8 instruction that adds the GOT base
225 /// register to sym\@got\@tlsld\@ha.
228 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
229 /// model, produces an ADDI8 instruction that adds G8RReg to
230 /// sym\@got\@tlsld\@l.
233 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
234 /// model, produces a call to __tls_get_addr(sym\@tlsld).
237 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
238 /// local-dynamic TLS model, produces an ADDIS8 instruction
239 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
240 /// to tie this in place following a copy to %X3 from the result
241 /// of a GET_TLSLD_ADDR.
244 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
245 /// model, produces an ADDI8 instruction that adds G8RReg to
246 /// sym\@got\@dtprel\@l.
249 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
250 /// during instruction selection to optimize a BUILD_VECTOR into
251 /// operations on splats. This is necessary to avoid losing these
252 /// optimizations due to constant folding.
255 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
256 /// operand identifies the operating system entry point.
259 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
260 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
261 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
263 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
265 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
266 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
267 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
271 /// STFIWX - The STFIWX instruction. The first operand is an input token
272 /// chain, then an f64 value to store, then an address to store it to.
275 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
276 /// load which sign-extends from a 32-bit integer value into the
277 /// destination 64-bit register.
280 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
281 /// load which zero-extends from a 32-bit integer value into the
282 /// destination 64-bit register.
285 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
286 /// produces an ADDIS8 instruction that adds the TOC base register to
290 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
291 /// produces a LD instruction with base register G8RReg and offset
292 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
295 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
296 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
297 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
302 /// Define some predicates that are used for node matching.
304 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
305 /// VPKUHUM instruction.
306 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
308 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
309 /// VPKUWUM instruction.
310 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
312 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
313 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
314 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
317 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
318 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
319 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
322 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
323 /// amount, otherwise return -1.
324 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
326 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
327 /// specifies a splat of a single element that is suitable for input to
328 /// VSPLTB/VSPLTH/VSPLTW.
329 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
331 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
333 bool isAllNegativeZeroVector(SDNode *N);
335 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
336 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
337 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
339 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
340 /// formed by using a vspltis[bhw] instruction of the specified element
341 /// size, return the constant being splatted. The ByteSize field indicates
342 /// the number of bytes of each element [124] -> [bhw].
343 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
346 class PPCTargetLowering : public TargetLowering {
347 const PPCSubtarget &PPCSubTarget;
350 explicit PPCTargetLowering(PPCTargetMachine &TM);
352 /// getTargetNodeName() - This method returns the name of a target specific
354 virtual const char *getTargetNodeName(unsigned Opcode) const;
356 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
358 /// getSetCCResultType - Return the ISD::SETCC ValueType
359 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
361 /// getPreIndexedAddressParts - returns true by value, base pointer and
362 /// offset pointer and addressing mode by reference if the node's address
363 /// can be legally represented as pre-indexed load / store address.
364 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
366 ISD::MemIndexedMode &AM,
367 SelectionDAG &DAG) const;
369 /// SelectAddressRegReg - Given the specified addressed, check to see if it
370 /// can be represented as an indexed [r+r] operation. Returns false if it
371 /// can be more efficiently represented with [r+imm].
372 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
373 SelectionDAG &DAG) const;
375 /// SelectAddressRegImm - Returns true if the address N can be represented
376 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
377 /// is not better represented as reg+reg. If Aligned is true, only accept
378 /// displacements suitable for STD and friends, i.e. multiples of 4.
379 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
380 SelectionDAG &DAG, bool Aligned) const;
382 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
383 /// represented as an indexed [r+r] operation.
384 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
385 SelectionDAG &DAG) const;
387 Sched::Preference getSchedulingPreference(SDNode *N) const;
389 /// LowerOperation - Provide custom lowering hooks for some operations.
391 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
393 /// ReplaceNodeResults - Replace the results of node with an illegal result
394 /// type with new values built out of custom code.
396 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
397 SelectionDAG &DAG) const;
399 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
401 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
404 const SelectionDAG &DAG,
405 unsigned Depth = 0) const;
407 virtual MachineBasicBlock *
408 EmitInstrWithCustomInserter(MachineInstr *MI,
409 MachineBasicBlock *MBB) const;
410 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
411 MachineBasicBlock *MBB, bool is64Bit,
412 unsigned BinOpcode) const;
413 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
414 MachineBasicBlock *MBB,
415 bool is8bit, unsigned Opcode) const;
417 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
418 MachineBasicBlock *MBB) const;
420 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
421 MachineBasicBlock *MBB) const;
423 ConstraintType getConstraintType(const std::string &Constraint) const;
425 /// Examine constraint string and operand type and determine a weight value.
426 /// The operand object must already have been set up with the operand type.
427 ConstraintWeight getSingleConstraintMatchWeight(
428 AsmOperandInfo &info, const char *constraint) const;
430 std::pair<unsigned, const TargetRegisterClass*>
431 getRegForInlineAsmConstraint(const std::string &Constraint,
434 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
435 /// function arguments in the caller parameter area. This is the actual
436 /// alignment, not its logarithm.
437 unsigned getByValTypeAlignment(Type *Ty) const;
439 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
440 /// vector. If it is invalid, don't add anything to Ops.
441 virtual void LowerAsmOperandForConstraint(SDValue Op,
442 std::string &Constraint,
443 std::vector<SDValue> &Ops,
444 SelectionDAG &DAG) const;
446 /// isLegalAddressingMode - Return true if the addressing mode represented
447 /// by AM is legal for this target, for a load/store of the specified type.
448 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
450 /// isLegalICmpImmediate - Return true if the specified immediate is legal
451 /// icmp immediate, that is the target has icmp instructions which can
452 /// compare a register against the immediate without having to materialize
453 /// the immediate into a register.
454 bool isLegalICmpImmediate(int64_t Imm) const override;
456 /// isLegalAddImmediate - Return true if the specified immediate is legal
457 /// add immediate, that is the target has add instructions which can
458 /// add a register and the immediate without having to materialize
459 /// the immediate into a register.
460 bool isLegalAddImmediate(int64_t Imm) const override;
462 /// isTruncateFree - Return true if it's free to truncate a value of
463 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
464 /// register X1 to i32 by referencing its sub-register R1.
465 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
466 bool isTruncateFree(EVT VT1, EVT VT2) const override;
468 /// \brief Returns true if it is beneficial to convert a load of a constant
469 /// to just the constant itself.
470 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
471 Type *Ty) const override;
473 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
475 /// getOptimalMemOpType - Returns the target specific optimal type for load
476 /// and store operations as a result of memset, memcpy, and memmove
477 /// lowering. If DstAlign is zero that means it's safe to destination
478 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
479 /// means there isn't a need to check it against alignment requirement,
480 /// probably because the source does not need to be loaded. If 'IsMemset' is
481 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
482 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
483 /// source is constant so it does not need to be loaded.
484 /// It returns EVT::Other if the type should be determined using generic
485 /// target-independent logic.
487 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
488 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
489 MachineFunction &MF) const;
491 /// Is unaligned memory access allowed for the given type, and is it fast
492 /// relative to software emulation.
493 virtual bool allowsUnalignedMemoryAccesses(EVT VT,
495 bool *Fast = 0) const;
497 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
498 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
499 /// expanded to FMAs when this method returns true, otherwise fmuladd is
500 /// expanded to fmul + fadd.
501 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
503 // Should we expand the build vector with shuffles?
505 shouldExpandBuildVectorWithShuffles(EVT VT,
506 unsigned DefinedValues) const;
508 /// createFastISel - This method returns a target-specific FastISel object,
509 /// or null if the target does not support "fast" instruction selection.
510 virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
511 const TargetLibraryInfo *LibInfo) const;
514 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
515 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
518 IsEligibleForTailCallOptimization(SDValue Callee,
519 CallingConv::ID CalleeCC,
521 const SmallVectorImpl<ISD::InputArg> &Ins,
522 SelectionDAG& DAG) const;
524 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
532 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
533 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
534 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
535 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
536 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
537 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
538 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
539 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
540 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
541 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
542 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
543 const PPCSubtarget &Subtarget) const;
544 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
545 const PPCSubtarget &Subtarget) const;
546 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
547 const PPCSubtarget &Subtarget) const;
548 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
549 const PPCSubtarget &Subtarget) const;
550 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
551 const PPCSubtarget &Subtarget) const;
552 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
553 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
554 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
556 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
557 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
558 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
559 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
560 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
561 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
562 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
563 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
564 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
565 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
566 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
567 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
569 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
570 CallingConv::ID CallConv, bool isVarArg,
571 const SmallVectorImpl<ISD::InputArg> &Ins,
572 SDLoc dl, SelectionDAG &DAG,
573 SmallVectorImpl<SDValue> &InVals) const;
574 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
577 SmallVector<std::pair<unsigned, SDValue>, 8>
579 SDValue InFlag, SDValue Chain,
581 int SPDiff, unsigned NumBytes,
582 const SmallVectorImpl<ISD::InputArg> &Ins,
583 SmallVectorImpl<SDValue> &InVals) const;
586 LowerFormalArguments(SDValue Chain,
587 CallingConv::ID CallConv, bool isVarArg,
588 const SmallVectorImpl<ISD::InputArg> &Ins,
589 SDLoc dl, SelectionDAG &DAG,
590 SmallVectorImpl<SDValue> &InVals) const;
593 LowerCall(TargetLowering::CallLoweringInfo &CLI,
594 SmallVectorImpl<SDValue> &InVals) const;
597 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
599 const SmallVectorImpl<ISD::OutputArg> &Outs,
600 LLVMContext &Context) const;
603 LowerReturn(SDValue Chain,
604 CallingConv::ID CallConv, bool isVarArg,
605 const SmallVectorImpl<ISD::OutputArg> &Outs,
606 const SmallVectorImpl<SDValue> &OutVals,
607 SDLoc dl, SelectionDAG &DAG) const;
610 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
611 SDValue ArgVal, SDLoc dl) const;
614 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
615 unsigned nAltivecParamsAtEnd,
616 unsigned MinReservedArea, bool isPPC64) const;
619 LowerFormalArguments_Darwin(SDValue Chain,
620 CallingConv::ID CallConv, bool isVarArg,
621 const SmallVectorImpl<ISD::InputArg> &Ins,
622 SDLoc dl, SelectionDAG &DAG,
623 SmallVectorImpl<SDValue> &InVals) const;
625 LowerFormalArguments_64SVR4(SDValue Chain,
626 CallingConv::ID CallConv, bool isVarArg,
627 const SmallVectorImpl<ISD::InputArg> &Ins,
628 SDLoc dl, SelectionDAG &DAG,
629 SmallVectorImpl<SDValue> &InVals) const;
631 LowerFormalArguments_32SVR4(SDValue Chain,
632 CallingConv::ID CallConv, bool isVarArg,
633 const SmallVectorImpl<ISD::InputArg> &Ins,
634 SDLoc dl, SelectionDAG &DAG,
635 SmallVectorImpl<SDValue> &InVals) const;
638 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
639 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
640 SelectionDAG &DAG, SDLoc dl) const;
643 LowerCall_Darwin(SDValue Chain, SDValue Callee,
644 CallingConv::ID CallConv,
645 bool isVarArg, bool isTailCall,
646 const SmallVectorImpl<ISD::OutputArg> &Outs,
647 const SmallVectorImpl<SDValue> &OutVals,
648 const SmallVectorImpl<ISD::InputArg> &Ins,
649 SDLoc dl, SelectionDAG &DAG,
650 SmallVectorImpl<SDValue> &InVals) const;
652 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
653 CallingConv::ID CallConv,
654 bool isVarArg, bool isTailCall,
655 const SmallVectorImpl<ISD::OutputArg> &Outs,
656 const SmallVectorImpl<SDValue> &OutVals,
657 const SmallVectorImpl<ISD::InputArg> &Ins,
658 SDLoc dl, SelectionDAG &DAG,
659 SmallVectorImpl<SDValue> &InVals) const;
661 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
662 bool isVarArg, bool isTailCall,
663 const SmallVectorImpl<ISD::OutputArg> &Outs,
664 const SmallVectorImpl<SDValue> &OutVals,
665 const SmallVectorImpl<ISD::InputArg> &Ins,
666 SDLoc dl, SelectionDAG &DAG,
667 SmallVectorImpl<SDValue> &InVals) const;
669 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
670 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
672 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
673 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
674 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
675 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
677 CCAssignFn *useFastISelCCs(unsigned Flag) const;
681 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
682 const TargetLibraryInfo *LibInfo);
685 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
686 CCValAssign::LocInfo &LocInfo,
687 ISD::ArgFlagsTy &ArgFlags,
690 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
692 CCValAssign::LocInfo &LocInfo,
693 ISD::ArgFlagsTy &ArgFlags,
696 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
698 CCValAssign::LocInfo &LocInfo,
699 ISD::ArgFlagsTy &ArgFlags,
703 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H