lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49
  50 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  51                                         "Enable 64-bit instructions">;
  52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  53                               "Enable 64-bit registers usage for ppc32 [beta]">;
  54 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  55                                         "Enable Altivec instructions">;
  56 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  57                                         "Enable the MFOCRF instruction">;
  58 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  59                                         "Enable the fsqrt instruction">;
  60 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  61                                         "Enable the fcpsgn instruction">;
  62 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  63                                         "Enable the fre instruction">;
  64 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  65                                         "Enable the fres instruction">;
  66 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  67                                         "Enable the frsqrte instruction">;
  68 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  69                                         "Enable the frsqrtes instruction">;
  70 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  71                               "Assume higher precision reciprocal estimates">;
  72 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  73                                         "Enable the stfiwx instruction">;
  74 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  75                                         "Enable the lfiwax instruction">;
  76 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  77                                         "Enable the fri[mnpz] instructions">;
  78 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  79   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  80 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  81                                         "Enable the isel instruction">;
  82 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
  83                                         "Enable the popcnt[dw] instructions">;
  84 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  85                                         "Enable the ldbrx instruction">;
  86 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  87                                         "Enable Book E instructions">;
  88 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
  89                                         "Enable QPX instructions">;
  90
  91 def DeprecatedMFTB   : SubtargetFeature<"", "DeprecatedMFTB", "true",
  92                                         "Treat mftb as deprecated">;
  93 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
  94   "Treat vector data stream cache control instructions as deprecated">;
  95
  96 // Note: Future features to add when support is extended to more
  97 // recent ISA levels:
  98 //
  99 // CMPB         p6, p6x, p7        cmpb
 100 // DFP          p6, p6x, p7        decimal floating-point instructions
 101 // POPCNTB      p5 through p7      popcntb and related instructions
 102 // VSX          p7                 vector-scalar instruction set
 103
 104 //===----------------------------------------------------------------------===//
 105 // Classes used for relation maps.
 106 //===----------------------------------------------------------------------===//
 107 // RecFormRel - Filter class used to relate non-record-form instructions with
 108 // their record-form variants.
 109 class RecFormRel;
 110
 111 //===----------------------------------------------------------------------===//
 112 // Relation Map Definitions.
 113 //===----------------------------------------------------------------------===//
 114
 115 def getRecordFormOpcode : InstrMapping {
 116   let FilterClass = "RecFormRel";
 117   // Instructions with the same BaseName and Interpretation64Bit values
 118   // form a row.
 119   let RowFields = ["BaseName", "Interpretation64Bit"];
 120   // Instructions with the same RC value form a column.
 121   let ColFields = ["RC"];
 122   // The key column are the non-record-form instructions.
 123   let KeyCol = ["0"];
 124   // Value columns RC=1
 125   let ValueCols = [["1"]];
 126 }
 127
 128 def getNonRecordFormOpcode : InstrMapping {
 129   let FilterClass = "RecFormRel";
 130   // Instructions with the same BaseName and Interpretation64Bit values
 131   // form a row.
 132   let RowFields = ["BaseName", "Interpretation64Bit"];
 133   // Instructions with the same RC value form a column.
 134   let ColFields = ["RC"];
 135   // The key column are the record-form instructions.
 136   let KeyCol = ["1"];
 137   // Value columns are RC=0
 138   let ValueCols = [["0"]];
 139 }
 140
 141 //===----------------------------------------------------------------------===//
 142 // Register File Description
 143 //===----------------------------------------------------------------------===//
 144
 145 include "PPCRegisterInfo.td"
 146 include "PPCSchedule.td"
 147 include "PPCInstrInfo.td"
 148
 149 //===----------------------------------------------------------------------===//
 150 // PowerPC processors supported.
 151 //
 152
 153 def : Processor<"generic", G3Itineraries, [Directive32]>;
 154 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
 155                                            FeatureFRES, FeatureFRSQRTE,
 156                                            FeatureBookE, DeprecatedMFTB]>;
 157 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
 158                                            FeatureFRES, FeatureFRSQRTE,
 159                                            FeatureBookE, DeprecatedMFTB]>;
 160 def : Processor<"601", G3Itineraries, [Directive601]>;
 161 def : Processor<"602", G3Itineraries, [Directive602]>;
 162 def : Processor<"603", G3Itineraries, [Directive603,
 163                                        FeatureFRES, FeatureFRSQRTE]>;
 164 def : Processor<"603e", G3Itineraries, [Directive603,
 165                                         FeatureFRES, FeatureFRSQRTE]>;
 166 def : Processor<"603ev", G3Itineraries, [Directive603,
 167                                          FeatureFRES, FeatureFRSQRTE]>;
 168 def : Processor<"604", G3Itineraries, [Directive604,
 169                                        FeatureFRES, FeatureFRSQRTE]>;
 170 def : Processor<"604e", G3Itineraries, [Directive604,
 171                                         FeatureFRES, FeatureFRSQRTE]>;
 172 def : Processor<"620", G3Itineraries, [Directive620,
 173                                        FeatureFRES, FeatureFRSQRTE]>;
 174 def : Processor<"750", G4Itineraries, [Directive750,
 175                                        FeatureFRES, FeatureFRSQRTE]>;
 176 def : Processor<"g3", G3Itineraries, [Directive750,
 177                                       FeatureFRES, FeatureFRSQRTE]>;
 178 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 179                                         FeatureFRES, FeatureFRSQRTE]>;
 180 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 181                                       FeatureFRES, FeatureFRSQRTE]>;
 182 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 183                                             FeatureFRES, FeatureFRSQRTE]>;
 184 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 185                                            FeatureFRES, FeatureFRSQRTE]>;
 186 def : ProcessorModel<"970", G5Model,
 187                   [Directive970, FeatureAltivec,
 188                    FeatureMFOCRF, FeatureFSqrt,
 189                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 190                    Feature64Bit /*, Feature64BitRegs */]>;
 191 def : ProcessorModel<"g5", G5Model,
 192                   [Directive970, FeatureAltivec,
 193                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 194                    FeatureFRES, FeatureFRSQRTE,
 195                    Feature64Bit /*, Feature64BitRegs */,
 196                    DeprecatedMFTB, DeprecatedDST]>;
 197 def : ProcessorModel<"e500mc", PPCE500mcModel,
 198                   [DirectiveE500mc, FeatureMFOCRF,
 199                    FeatureSTFIWX, FeatureBookE, FeatureISEL,
 200                    DeprecatedMFTB]>;
 201 def : ProcessorModel<"e5500", PPCE5500Model,
 202                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 203                    FeatureSTFIWX, FeatureBookE, FeatureISEL,
 204                    DeprecatedMFTB]>;
 205 def : ProcessorModel<"a2", PPCA2Model,
 206                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 207                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 208                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 209                    FeatureSTFIWX, FeatureLFIWAX,
 210                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 211                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 212                /*, Feature64BitRegs */, DeprecatedMFTB]>;
 213 def : ProcessorModel<"a2q", PPCA2Model,
 214                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 215                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 216                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 217                    FeatureSTFIWX, FeatureLFIWAX,
 218                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 219                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 220                /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
 221 def : ProcessorModel<"pwr3", G5Model,
 222                   [DirectivePwr3, FeatureAltivec,
 223                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 224                    FeatureSTFIWX, Feature64Bit]>;
 225 def : ProcessorModel<"pwr4", G5Model,
 226                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 227                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 228                    FeatureSTFIWX, Feature64Bit]>;
 229 def : ProcessorModel<"pwr5", G5Model,
 230                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 231                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 232                    FeatureFRSQRTE, FeatureFRSQRTES,
 233                    FeatureSTFIWX, Feature64Bit,
 234                    DeprecatedMFTB, DeprecatedDST]>;
 235 def : ProcessorModel<"pwr5x", G5Model,
 236                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 237                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 238                    FeatureFRSQRTE, FeatureFRSQRTES,
 239                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 240                    DeprecatedMFTB, DeprecatedDST]>;
 241 def : ProcessorModel<"pwr6", G5Model,
 242                   [DirectivePwr6, FeatureAltivec,
 243                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 244                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 245                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 246                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 247                    DeprecatedMFTB, DeprecatedDST]>;
 248 def : ProcessorModel<"pwr6x", G5Model,
 249                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 250                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 251                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 252                    FeatureSTFIWX, FeatureLFIWAX,
 253                    FeatureFPRND, Feature64Bit,
 254                    DeprecatedMFTB, DeprecatedDST]>;
 255 def : ProcessorModel<"pwr7", G5Model,
 256                   [DirectivePwr7, FeatureAltivec,
 257                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 258                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 259                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 260                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 261                    FeaturePOPCNTD, FeatureLDBRX,
 262                    Feature64Bit /*, Feature64BitRegs */,
 263                    DeprecatedMFTB, DeprecatedDST]>;
 264 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 265 def : ProcessorModel<"ppc64", G5Model,
 266                   [Directive64, FeatureAltivec,
 267                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 268                    FeatureFRSQRTE, FeatureSTFIWX,
 269                    Feature64Bit /*, Feature64BitRegs */]>;
 270 def : ProcessorModel<"ppc64le", G5Model,
 271                   [Directive64, FeatureAltivec,
 272                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 273                    FeatureFRSQRTE, FeatureSTFIWX,
 274                    Feature64Bit /*, Feature64BitRegs */]>;
 275
 276 //===----------------------------------------------------------------------===//
 277 // Calling Conventions
 278 //===----------------------------------------------------------------------===//
 279
 280 include "PPCCallingConv.td"
 281
 282 def PPCInstrInfo : InstrInfo {
 283   let isLittleEndianEncoding = 1;
 284 }
 285
 286 def PPCAsmWriter : AsmWriter {
 287   string AsmWriterClassName  = "InstPrinter";
 288   bit isMCAsmWriter = 1;
 289 }
 290
 291 def PPCAsmParser : AsmParser {
 292   let ShouldEmitMatchRegisterName = 0;
 293 }
 294
 295 def PPCAsmParserVariant : AsmParserVariant {
 296   int Variant = 0;
 297
 298   // We do not use hard coded registers in asm strings.  However, some
 299   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 300   // so that those are not misinterpreted as registers.
 301   string RegisterPrefix = "%";
 302 }
 303
 304 def PPC : Target {
 305   // Information about the instructions.
 306   let InstructionSet = PPCInstrInfo;
 307
 308   let AssemblyWriters = [PPCAsmWriter];
 309   let AssemblyParsers = [PPCAsmParser];
 310   let AssemblyParserVariants = [PPCAsmParserVariant];
 311 }