1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an PPC MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstPrinter.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetOpcodes.h"
26 #define DEBUG_TYPE "asm-printer"
28 // FIXME: Once the integrated assembler supports full register names, tie this
29 // to the verbose-asm setting.
31 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
32 cl::desc("Use full register names when printing assembly"));
34 #define PRINT_ALIAS_INSTR
35 #include "PPCGenAsmWriter.inc"
37 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
38 const char *RegName = getRegisterName(RegNo);
39 if (RegName[0] == 'q' /* QPX */) {
40 // The system toolchain on the BG/Q does not understand QPX register names
41 // in .cfi_* directives, so print the name of the floating-point
42 // subregister instead.
43 std::string RN(RegName);
54 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
55 StringRef Annot, const MCSubtargetInfo &STI) {
56 // Check for slwi/srwi mnemonics.
57 if (MI->getOpcode() == PPC::RLWINM) {
58 unsigned char SH = MI->getOperand(2).getImm();
59 unsigned char MB = MI->getOperand(3).getImm();
60 unsigned char ME = MI->getOperand(4).getImm();
61 bool useSubstituteMnemonic = false;
62 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
63 O << "\tslwi "; useSubstituteMnemonic = true;
65 if (SH <= 31 && MB == (32-SH) && ME == 31) {
66 O << "\tsrwi "; useSubstituteMnemonic = true;
69 if (useSubstituteMnemonic) {
70 printOperand(MI, 0, O);
72 printOperand(MI, 1, O);
73 O << ", " << (unsigned int)SH;
75 printAnnotation(O, Annot);
80 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
81 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
83 printOperand(MI, 0, O);
85 printOperand(MI, 1, O);
86 printAnnotation(O, Annot);
90 if (MI->getOpcode() == PPC::RLDICR) {
91 unsigned char SH = MI->getOperand(2).getImm();
92 unsigned char ME = MI->getOperand(3).getImm();
93 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
96 printOperand(MI, 0, O);
98 printOperand(MI, 1, O);
99 O << ", " << (unsigned int)SH;
100 printAnnotation(O, Annot);
105 // dcbt[st] is printed manually here because:
106 // 1. The assembly syntax is different between embedded and server targets
107 // 2. We must print the short mnemonics for TH == 0 because the
108 // embedded/server syntax default will not be stable across assemblers
109 // The syntax for dcbt is:
110 // dcbt ra, rb, th [server]
111 // dcbt th, ra, rb [embedded]
112 // where th can be omitted when it is 0. dcbtst is the same.
113 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
114 unsigned char TH = MI->getOperand(0).getImm();
116 if (MI->getOpcode() == PPC::DCBTST)
122 bool IsBookE = (STI.getFeatureBits() & PPC::FeatureBookE) != 0;
123 if (IsBookE && TH != 0 && TH != 16)
124 O << (unsigned int) TH << ", ";
126 printOperand(MI, 1, O);
128 printOperand(MI, 2, O);
130 if (!IsBookE && TH != 0 && TH != 16)
131 O << ", " << (unsigned int) TH;
133 printAnnotation(O, Annot);
137 // For fast-isel, a COPY_TO_REGCLASS may survive this long. This is
138 // used when converting a 32-bit float to a 64-bit float as part of
139 // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
140 // as otherwise we have problems with incorrect register classes
141 // in machine instruction verification. For now, just avoid trying
142 // to print it as such an instruction has no effect (a 32-bit float
143 // in a register is already in 64-bit form, just with lower
144 // precision). FIXME: Is there a better solution?
145 if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
148 if (!printAliasInstr(MI, O))
149 printInstruction(MI, O);
150 printAnnotation(O, Annot);
154 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
156 const char *Modifier) {
157 unsigned Code = MI->getOperand(OpNo).getImm();
159 if (StringRef(Modifier) == "cc") {
160 switch ((PPC::Predicate)Code) {
161 case PPC::PRED_LT_MINUS:
162 case PPC::PRED_LT_PLUS:
166 case PPC::PRED_LE_MINUS:
167 case PPC::PRED_LE_PLUS:
171 case PPC::PRED_EQ_MINUS:
172 case PPC::PRED_EQ_PLUS:
176 case PPC::PRED_GE_MINUS:
177 case PPC::PRED_GE_PLUS:
181 case PPC::PRED_GT_MINUS:
182 case PPC::PRED_GT_PLUS:
186 case PPC::PRED_NE_MINUS:
187 case PPC::PRED_NE_PLUS:
191 case PPC::PRED_UN_MINUS:
192 case PPC::PRED_UN_PLUS:
196 case PPC::PRED_NU_MINUS:
197 case PPC::PRED_NU_PLUS:
201 case PPC::PRED_BIT_SET:
202 case PPC::PRED_BIT_UNSET:
203 llvm_unreachable("Invalid use of bit predicate code");
205 llvm_unreachable("Invalid predicate code");
208 if (StringRef(Modifier) == "pm") {
209 switch ((PPC::Predicate)Code) {
219 case PPC::PRED_LT_MINUS:
220 case PPC::PRED_LE_MINUS:
221 case PPC::PRED_EQ_MINUS:
222 case PPC::PRED_GE_MINUS:
223 case PPC::PRED_GT_MINUS:
224 case PPC::PRED_NE_MINUS:
225 case PPC::PRED_UN_MINUS:
226 case PPC::PRED_NU_MINUS:
229 case PPC::PRED_LT_PLUS:
230 case PPC::PRED_LE_PLUS:
231 case PPC::PRED_EQ_PLUS:
232 case PPC::PRED_GE_PLUS:
233 case PPC::PRED_GT_PLUS:
234 case PPC::PRED_NE_PLUS:
235 case PPC::PRED_UN_PLUS:
236 case PPC::PRED_NU_PLUS:
239 case PPC::PRED_BIT_SET:
240 case PPC::PRED_BIT_UNSET:
241 llvm_unreachable("Invalid use of bit predicate code");
243 llvm_unreachable("Invalid predicate code");
246 assert(StringRef(Modifier) == "reg" &&
247 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
248 printOperand(MI, OpNo+1, O);
251 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
253 unsigned int Value = MI->getOperand(OpNo).getImm();
254 assert(Value <= 1 && "Invalid u1imm argument!");
255 O << (unsigned int)Value;
258 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
260 unsigned int Value = MI->getOperand(OpNo).getImm();
261 assert(Value <= 3 && "Invalid u2imm argument!");
262 O << (unsigned int)Value;
265 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
267 unsigned int Value = MI->getOperand(OpNo).getImm();
268 assert(Value <= 8 && "Invalid u3imm argument!");
269 O << (unsigned int)Value;
272 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
274 unsigned int Value = MI->getOperand(OpNo).getImm();
275 assert(Value <= 15 && "Invalid u4imm argument!");
276 O << (unsigned int)Value;
279 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
281 int Value = MI->getOperand(OpNo).getImm();
282 Value = SignExtend32<5>(Value);
286 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
288 unsigned int Value = MI->getOperand(OpNo).getImm();
289 assert(Value <= 31 && "Invalid u5imm argument!");
290 O << (unsigned int)Value;
293 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
295 unsigned int Value = MI->getOperand(OpNo).getImm();
296 assert(Value <= 63 && "Invalid u6imm argument!");
297 O << (unsigned int)Value;
300 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
302 unsigned short Value = MI->getOperand(OpNo).getImm();
303 assert(Value <= 4095 && "Invalid u12imm argument!");
304 O << (unsigned short)Value;
307 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
309 if (MI->getOperand(OpNo).isImm())
310 O << (short)MI->getOperand(OpNo).getImm();
312 printOperand(MI, OpNo, O);
315 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
317 if (MI->getOperand(OpNo).isImm())
318 O << (unsigned short)MI->getOperand(OpNo).getImm();
320 printOperand(MI, OpNo, O);
323 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
325 if (!MI->getOperand(OpNo).isImm())
326 return printOperand(MI, OpNo, O);
328 // Branches can take an immediate operand. This is used by the branch
329 // selection pass to print .+8, an eight byte displacement from the PC.
331 printAbsBranchOperand(MI, OpNo, O);
334 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
336 if (!MI->getOperand(OpNo).isImm())
337 return printOperand(MI, OpNo, O);
339 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
343 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
345 unsigned CCReg = MI->getOperand(OpNo).getReg();
348 default: llvm_unreachable("Unknown CR register");
349 case PPC::CR0: RegNo = 0; break;
350 case PPC::CR1: RegNo = 1; break;
351 case PPC::CR2: RegNo = 2; break;
352 case PPC::CR3: RegNo = 3; break;
353 case PPC::CR4: RegNo = 4; break;
354 case PPC::CR5: RegNo = 5; break;
355 case PPC::CR6: RegNo = 6; break;
356 case PPC::CR7: RegNo = 7; break;
358 O << (0x80 >> RegNo);
361 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
363 printS16ImmOperand(MI, OpNo, O);
365 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
368 printOperand(MI, OpNo+1, O);
372 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
374 // When used as the base register, r0 reads constant zero rather than
375 // the value contained in the register. For this reason, the darwin
376 // assembler requires that we print r0 as 0 (no r) when used as the base.
377 if (MI->getOperand(OpNo).getReg() == PPC::R0)
380 printOperand(MI, OpNo, O);
382 printOperand(MI, OpNo+1, O);
385 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
387 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
388 // come at the _end_ of the expression.
389 const MCOperand &Op = MI->getOperand(OpNo);
390 const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
391 O << refExp.getSymbol().getName();
393 printOperand(MI, OpNo+1, O);
395 if (refExp.getKind() != MCSymbolRefExpr::VK_None)
396 O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
400 /// stripRegisterPrefix - This method strips the character prefix from a
401 /// register name so that only the number is left. Used by for linux asm.
402 static const char *stripRegisterPrefix(const char *RegName) {
406 switch (RegName[0]) {
411 if (RegName[1] == 's')
414 case 'c': if (RegName[1] == 'r') return RegName + 2;
420 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
422 const MCOperand &Op = MI->getOperand(OpNo);
424 const char *RegName = getRegisterName(Op.getReg());
425 // The linux and AIX assembler does not take register prefixes.
426 if (!isDarwinSyntax())
427 RegName = stripRegisterPrefix(RegName);
438 assert(Op.isExpr() && "unknown operand kind in printOperand");