1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXTargetObjectFile.h"
20 #include "NVPTXTargetTransformInfo.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/IR/Verifier.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSubtargetInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
51 void initializeNVVMReflectPass(PassRegistry&);
52 void initializeGenericToNVVMPass(PassRegistry&);
53 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
54 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
55 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
56 void initializeNVPTXLowerStructArgsPass(PassRegistry &);
59 extern "C" void LLVMInitializeNVPTXTarget() {
60 // Register the target.
61 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
62 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
64 // FIXME: This pass is really intended to be invoked during IR optimization,
65 // but it's very NVPTX-specific.
66 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
67 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
68 initializeNVPTXAllocaHoistingPass(*PassRegistry::getPassRegistry());
69 initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
70 initializeNVPTXFavorNonGenericAddrSpacesPass(
71 *PassRegistry::getPassRegistry());
72 initializeNVPTXLowerStructArgsPass(*PassRegistry::getPassRegistry());
75 static std::string computeDataLayout(bool is64Bit) {
76 std::string Ret = "e";
81 Ret += "-i64:64-v16:16-v32:32-n16:32:64";
86 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
87 StringRef CPU, StringRef FS,
88 const TargetOptions &Options,
89 Reloc::Model RM, CodeModel::Model CM,
90 CodeGenOpt::Level OL, bool is64bit)
91 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), is64bit(is64bit),
92 TLOF(make_unique<NVPTXTargetObjectFile>()),
93 DL(computeDataLayout(is64bit)), Subtarget(TT, CPU, FS, *this) {
94 if (Triple(TT).getOS() == Triple::NVCL)
95 drvInterface = NVPTX::NVCL;
97 drvInterface = NVPTX::CUDA;
101 NVPTXTargetMachine::~NVPTXTargetMachine() {}
103 void NVPTXTargetMachine32::anchor() {}
105 NVPTXTargetMachine32::NVPTXTargetMachine32(
106 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
107 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
108 CodeGenOpt::Level OL)
109 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
111 void NVPTXTargetMachine64::anchor() {}
113 NVPTXTargetMachine64::NVPTXTargetMachine64(
114 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
115 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
116 CodeGenOpt::Level OL)
117 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
120 class NVPTXPassConfig : public TargetPassConfig {
122 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
123 : TargetPassConfig(TM, PM) {}
125 NVPTXTargetMachine &getNVPTXTargetMachine() const {
126 return getTM<NVPTXTargetMachine>();
129 void addIRPasses() override;
130 bool addInstSelector() override;
131 void addPostRegAlloc() override;
132 void addMachineSSAOptimization() override;
134 FunctionPass *createTargetRegisterAllocator(bool) override;
135 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
136 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
138 } // end anonymous namespace
140 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
141 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
145 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
146 return TargetIRAnalysis(
147 [this](Function &) { return TargetTransformInfo(NVPTXTTIImpl(this)); });
150 void NVPTXPassConfig::addIRPasses() {
151 // The following passes are known to not play well with virtual regs hanging
152 // around after register allocation (which in our case, is *all* registers).
153 // We explicitly disable them here. We do, however, need some functionality
154 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
155 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
156 disablePass(&PrologEpilogCodeInserterID);
157 disablePass(&MachineCopyPropagationID);
158 disablePass(&BranchFolderPassID);
159 disablePass(&TailDuplicateID);
161 addPass(createNVPTXImageOptimizerPass());
162 TargetPassConfig::addIRPasses();
163 addPass(createNVPTXAssignValidGlobalNamesPass());
164 addPass(createGenericToNVVMPass());
165 addPass(createNVPTXFavorNonGenericAddrSpacesPass());
166 addPass(createStraightLineStrengthReducePass());
167 addPass(createSeparateConstOffsetFromGEPPass());
168 // The SeparateConstOffsetFromGEP pass creates variadic bases that can be used
169 // by multiple GEPs. Run GVN or EarlyCSE to really reuse them. GVN generates
170 // significantly better code than EarlyCSE for some of our benchmarks.
171 if (getOptLevel() == CodeGenOpt::Aggressive)
172 addPass(createGVNPass());
174 addPass(createEarlyCSEPass());
175 // Both FavorNonGenericAddrSpaces and SeparateConstOffsetFromGEP may leave
176 // some dead code. We could remove dead code in an ad-hoc manner, but that
177 // requires manual work and might be error-prone.
179 // The FavorNonGenericAddrSpaces pass shortcuts unnecessary addrspacecasts,
180 // and leave them unused.
182 // SeparateConstOffsetFromGEP rebuilds a new index from the old index, and the
183 // old index and some of its intermediate results may become unused.
184 addPass(createDeadCodeEliminationPass());
187 bool NVPTXPassConfig::addInstSelector() {
188 const NVPTXSubtarget &ST =
189 getTM<NVPTXTargetMachine>().getSubtarget<NVPTXSubtarget>();
191 addPass(createLowerAggrCopies());
192 addPass(createAllocaHoisting());
193 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
195 if (!ST.hasImageHandles())
196 addPass(createNVPTXReplaceImageHandlesPass());
201 void NVPTXPassConfig::addPostRegAlloc() {
202 addPass(createNVPTXPrologEpilogPass(), false);
205 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
206 return nullptr; // No reg alloc
209 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
210 assert(!RegAllocPass && "NVPTX uses no regalloc!");
211 addPass(&PHIEliminationID);
212 addPass(&TwoAddressInstructionPassID);
215 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
216 assert(!RegAllocPass && "NVPTX uses no regalloc!");
218 addPass(&ProcessImplicitDefsID);
219 addPass(&LiveVariablesID);
220 addPass(&MachineLoopInfoID);
221 addPass(&PHIEliminationID);
223 addPass(&TwoAddressInstructionPassID);
224 addPass(&RegisterCoalescerID);
226 // PreRA instruction scheduling.
227 if (addPass(&MachineSchedulerID))
228 printAndVerify("After Machine Scheduling");
231 addPass(&StackSlotColoringID);
233 // FIXME: Needs physical registers
234 //addPass(&PostRAMachineLICMID);
236 printAndVerify("After StackSlotColoring");
239 void NVPTXPassConfig::addMachineSSAOptimization() {
240 // Pre-ra tail duplication.
241 if (addPass(&EarlyTailDuplicateID))
242 printAndVerify("After Pre-RegAlloc TailDuplicate");
244 // Optimize PHIs before DCE: removing dead PHI cycles may make more
245 // instructions dead.
246 addPass(&OptimizePHIsID);
248 // This pass merges large allocas. StackSlotColoring is a different pass
249 // which merges spill slots.
250 addPass(&StackColoringID);
252 // If the target requests it, assign local variables to stack slots relative
253 // to one another and simplify frame index references where possible.
254 addPass(&LocalStackSlotAllocationID);
256 // With optimization, dead code should already be eliminated. However
257 // there is one known exception: lowered code for arguments that are only
258 // used by tail calls, where the tail calls reuse the incoming stack
259 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
260 addPass(&DeadMachineInstructionElimID);
261 printAndVerify("After codegen DCE pass");
263 // Allow targets to insert passes that improve instruction level parallelism,
264 // like if-conversion. Such passes will typically need dominator trees and
265 // loop info, just like LICM and CSE below.
267 printAndVerify("After ILP optimizations");
269 addPass(&MachineLICMID);
270 addPass(&MachineCSEID);
272 addPass(&MachineSinkingID);
273 printAndVerify("After Machine LICM, CSE and Sinking passes");
275 addPass(&PeepholeOptimizerID);
276 printAndVerify("After codegen peephole optimization pass");