lib/Target/NVPTX/NVPTXIntrinsics.td

   1 //===- NVPTXIntrinsics.td - PTX Intrinsics Instructions -------*- tblgen -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 def immFloat0 : PatLeaf<(fpimm), [{
  11     float f = (float)N->getValueAPF().convertToFloat();
  12     return (f==0.0f);
  13 }]>;
  14
  15 def immFloat1 : PatLeaf<(fpimm), [{
  16     float f = (float)N->getValueAPF().convertToFloat();
  17     return (f==1.0f);
  18 }]>;
  19
  20 def immDouble0 : PatLeaf<(fpimm), [{
  21     double d = (double)N->getValueAPF().convertToDouble();
  22     return (d==0.0);
  23 }]>;
  24
  25 def immDouble1 : PatLeaf<(fpimm), [{
  26     double d = (double)N->getValueAPF().convertToDouble();
  27     return (d==1.0);
  28 }]>;
  29
  30
  31
  32 //-----------------------------------
  33 // Synchronization Functions
  34 //-----------------------------------
  35 def INT_CUDA_SYNCTHREADS : NVPTXInst<(outs), (ins),
  36                   "bar.sync \t0;",
  37       [(int_cuda_syncthreads)]>;
  38 def INT_BARRIER0 : NVPTXInst<(outs), (ins),
  39                   "bar.sync \t0;",
  40       [(int_nvvm_barrier0)]>;
  41 def INT_BARRIER0_POPC : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$pred),
  42   !strconcat("{{ \n\t",
  43       !strconcat(".reg .pred \t%p1; \n\t",
  44       !strconcat("setp.ne.u32 \t%p1, $pred, 0; \n\t",
  45       !strconcat("bar.red.popc.u32 \t$dst, 0, %p1; \n\t",
  46         !strconcat("}}", ""))))),
  47       [(set Int32Regs:$dst, (int_nvvm_barrier0_popc Int32Regs:$pred))]>;
  48 def INT_BARRIER0_AND : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$pred),
  49   !strconcat("{{ \n\t",
  50       !strconcat(".reg .pred \t%p1; \n\t",
  51       !strconcat(".reg .pred \t%p2; \n\t",
  52       !strconcat("setp.ne.u32 \t%p1, $pred, 0; \n\t",
  53       !strconcat("bar.red.and.pred \t%p2, 0, %p1; \n\t",
  54       !strconcat("selp.u32 \t$dst, 1, 0, %p2; \n\t",
  55         !strconcat("}}", ""))))))),
  56       [(set Int32Regs:$dst, (int_nvvm_barrier0_and Int32Regs:$pred))]>;
  57 def INT_BARRIER0_OR : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$pred),
  58   !strconcat("{{ \n\t",
  59       !strconcat(".reg .pred \t%p1; \n\t",
  60       !strconcat(".reg .pred \t%p2; \n\t",
  61       !strconcat("setp.ne.u32 \t%p1, $pred, 0; \n\t",
  62       !strconcat("bar.red.or.pred \t%p2, 0, %p1; \n\t",
  63       !strconcat("selp.u32 \t$dst, 1, 0, %p2; \n\t",
  64         !strconcat("}}", ""))))))),
  65       [(set Int32Regs:$dst, (int_nvvm_barrier0_or Int32Regs:$pred))]>;
  66
  67
  68 //-----------------------------------
  69 // Explicit Memory Fence Functions
  70 //-----------------------------------
  71 class MEMBAR<string StrOp, Intrinsic IntOP> :
  72               NVPTXInst<(outs), (ins),
  73             StrOp, [(IntOP)]>;
  74
  75 def INT_MEMBAR_CTA : MEMBAR<"membar.cta;", int_nvvm_membar_cta>;
  76 def INT_MEMBAR_GL  : MEMBAR<"membar.gl;",  int_nvvm_membar_gl>;
  77 def INT_MEMBAR_SYS : MEMBAR<"membar.sys;", int_nvvm_membar_sys>;
  78
  79
  80 //-----------------------------------
  81 // Math Functions
  82 //-----------------------------------
  83
  84 // Map min(1.0, max(0.0, x)) to sat(x)
  85 // Note that max(0.0, min(x, 1.0)) cannot be mapped to sat(x) because when x is
  86 // NaN
  87 // max(0.0, min(x, 1.0)) is 1.0 while sat(x) is 0.
  88 // Same story for fmax, fmin.
  89
  90 def : Pat<(int_nvvm_fmin_f immFloat1,
  91             (int_nvvm_fmax_f immFloat0, Float32Regs:$a)),
  92           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
  93 def : Pat<(int_nvvm_fmin_f immFloat1,
  94             (int_nvvm_fmax_f Float32Regs:$a, immFloat0)),
  95           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
  96 def : Pat<(int_nvvm_fmin_f
  97             (int_nvvm_fmax_f immFloat0, Float32Regs:$a), immFloat1),
  98           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
  99 def : Pat<(int_nvvm_fmin_f
 100             (int_nvvm_fmax_f Float32Regs:$a, immFloat0), immFloat1),
 101           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
 102
 103 def : Pat<(int_nvvm_fmin_d immDouble1,
 104             (int_nvvm_fmax_d immDouble0, Float64Regs:$a)),
 105           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 106 def : Pat<(int_nvvm_fmin_d immDouble1,
 107             (int_nvvm_fmax_d Float64Regs:$a, immDouble0)),
 108           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 109 def : Pat<(int_nvvm_fmin_d
 110             (int_nvvm_fmax_d immDouble0, Float64Regs:$a), immDouble1),
 111           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 112 def : Pat<(int_nvvm_fmin_d
 113             (int_nvvm_fmax_d Float64Regs:$a, immDouble0), immDouble1),
 114           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 115
 116
 117 // We need a full string for OpcStr here because we need to deal with case like
 118 // INT_PTX_RECIP.
 119 class F_MATH_1<string OpcStr, NVPTXRegClass target_regclass,
 120   NVPTXRegClass src_regclass, Intrinsic IntOP>
 121             : NVPTXInst<(outs target_regclass:$dst), (ins src_regclass:$src0),
 122             OpcStr,
 123         [(set target_regclass:$dst, (IntOP src_regclass:$src0))]>;
 124
 125 // We need a full string for OpcStr here because we need to deal with the case
 126 // like INT_PTX_NATIVE_POWR_F.
 127 class F_MATH_2<string OpcStr, NVPTXRegClass t_regclass,
 128   NVPTXRegClass s0_regclass, NVPTXRegClass s1_regclass, Intrinsic IntOP>
 129             : NVPTXInst<(outs t_regclass:$dst),
 130               (ins s0_regclass:$src0, s1_regclass:$src1),
 131             OpcStr,
 132         [(set t_regclass:$dst, (IntOP s0_regclass:$src0, s1_regclass:$src1))]>;
 133
 134 class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
 135   NVPTXRegClass s0_regclass, NVPTXRegClass s1_regclass,
 136   NVPTXRegClass s2_regclass, Intrinsic IntOP>
 137             : NVPTXInst<(outs t_regclass:$dst),
 138               (ins s0_regclass:$src0, s1_regclass:$src1, s2_regclass:$src2),
 139             OpcStr,
 140         [(set t_regclass:$dst,
 141           (IntOP s0_regclass:$src0, s1_regclass:$src1, s2_regclass:$src2))]>;
 142
 143 //
 144 // MISC
 145 //
 146
 147 def INT_NVVM_CLZ_I : F_MATH_1<"clz.b32 \t$dst, $src0;", Int32Regs, Int32Regs,
 148   int_nvvm_clz_i>;
 149 def INT_NVVM_CLZ_LL : F_MATH_1<"clz.b64 \t$dst, $src0;", Int32Regs, Int64Regs,
 150   int_nvvm_clz_ll>;
 151
 152 def INT_NVVM_POPC_I : F_MATH_1<"popc.b32 \t$dst, $src0;", Int32Regs, Int32Regs,
 153   int_nvvm_popc_i>;
 154 def INT_NVVM_POPC_LL : F_MATH_1<"popc.b64 \t$dst, $src0;", Int32Regs, Int64Regs,
 155   int_nvvm_popc_ll>;
 156
 157 def INT_NVVM_PRMT : F_MATH_3<"prmt.b32 \t$dst, $src0, $src1, $src2;", Int32Regs,
 158   Int32Regs, Int32Regs, Int32Regs, int_nvvm_prmt>;
 159
 160 //
 161 // Min Max
 162 //
 163
 164 def INT_NVVM_MIN_I : F_MATH_2<"min.s32 \t$dst, $src0, $src1;", Int32Regs,
 165   Int32Regs, Int32Regs, int_nvvm_min_i>;
 166 def INT_NVVM_MIN_UI : F_MATH_2<"min.u32 \t$dst, $src0, $src1;", Int32Regs,
 167   Int32Regs, Int32Regs, int_nvvm_min_ui>;
 168
 169 def INT_NVVM_MIN_LL : F_MATH_2<"min.s64 \t$dst, $src0, $src1;", Int64Regs,
 170   Int64Regs, Int64Regs, int_nvvm_min_ll>;
 171 def INT_NVVM_MIN_ULL : F_MATH_2<"min.u64 \t$dst, $src0, $src1;", Int64Regs,
 172   Int64Regs, Int64Regs, int_nvvm_min_ull>;
 173
 174 def INT_NVVM_MAX_I : F_MATH_2<"max.s32 \t$dst, $src0, $src1;", Int32Regs,
 175   Int32Regs, Int32Regs, int_nvvm_max_i>;
 176 def INT_NVVM_MAX_UI : F_MATH_2<"max.u32 \t$dst, $src0, $src1;", Int32Regs,
 177   Int32Regs, Int32Regs, int_nvvm_max_ui>;
 178
 179 def INT_NVVM_MAX_LL : F_MATH_2<"max.s64 \t$dst, $src0, $src1;", Int64Regs,
 180   Int64Regs, Int64Regs, int_nvvm_max_ll>;
 181 def INT_NVVM_MAX_ULL : F_MATH_2<"max.u64 \t$dst, $src0, $src1;", Int64Regs,
 182   Int64Regs, Int64Regs, int_nvvm_max_ull>;
 183
 184 def INT_NVVM_FMIN_F : F_MATH_2<"min.f32 \t$dst, $src0, $src1;", Float32Regs,
 185   Float32Regs, Float32Regs, int_nvvm_fmin_f>;
 186 def INT_NVVM_FMIN_FTZ_F : F_MATH_2<"min.ftz.f32 \t$dst, $src0, $src1;",
 187   Float32Regs, Float32Regs, Float32Regs, int_nvvm_fmin_ftz_f>;
 188
 189 def INT_NVVM_FMAX_F : F_MATH_2<"max.f32 \t$dst, $src0, $src1;", Float32Regs,
 190   Float32Regs, Float32Regs, int_nvvm_fmax_f>;
 191 def INT_NVVM_FMAX_FTZ_F : F_MATH_2<"max.ftz.f32 \t$dst, $src0, $src1;",
 192   Float32Regs, Float32Regs, Float32Regs, int_nvvm_fmax_ftz_f>;
 193
 194 def INT_NVVM_FMIN_D : F_MATH_2<"min.f64 \t$dst, $src0, $src1;", Float64Regs,
 195   Float64Regs, Float64Regs, int_nvvm_fmin_d>;
 196 def INT_NVVM_FMAX_D : F_MATH_2<"max.f64 \t$dst, $src0, $src1;", Float64Regs,
 197   Float64Regs, Float64Regs, int_nvvm_fmax_d>;
 198
 199 //
 200 // Multiplication
 201 //
 202
 203 def INT_NVVM_MULHI_I : F_MATH_2<"mul.hi.s32 \t$dst, $src0, $src1;", Int32Regs,
 204   Int32Regs, Int32Regs, int_nvvm_mulhi_i>;
 205 def INT_NVVM_MULHI_UI : F_MATH_2<"mul.hi.u32 \t$dst, $src0, $src1;", Int32Regs,
 206   Int32Regs, Int32Regs, int_nvvm_mulhi_ui>;
 207
 208 def INT_NVVM_MULHI_LL : F_MATH_2<"mul.hi.s64 \t$dst, $src0, $src1;", Int64Regs,
 209   Int64Regs, Int64Regs, int_nvvm_mulhi_ll>;
 210 def INT_NVVM_MULHI_ULL : F_MATH_2<"mul.hi.u64 \t$dst, $src0, $src1;", Int64Regs,
 211   Int64Regs, Int64Regs, int_nvvm_mulhi_ull>;
 212
 213 def INT_NVVM_MUL_RN_FTZ_F : F_MATH_2<"mul.rn.ftz.f32 \t$dst, $src0, $src1;",
 214   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rn_ftz_f>;
 215 def INT_NVVM_MUL_RN_F : F_MATH_2<"mul.rn.f32 \t$dst, $src0, $src1;",
 216   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rn_f>;
 217 def INT_NVVM_MUL_RZ_FTZ_F : F_MATH_2<"mul.rz.ftz.f32 \t$dst, $src0, $src1;",
 218   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rz_ftz_f>;
 219 def INT_NVVM_MUL_RZ_F : F_MATH_2<"mul.rz.f32 \t$dst, $src0, $src1;",
 220   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rz_f>;
 221 def INT_NVVM_MUL_RM_FTZ_F : F_MATH_2<"mul.rm.ftz.f32 \t$dst, $src0, $src1;",
 222   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rm_ftz_f>;
 223 def INT_NVVM_MUL_RM_F : F_MATH_2<"mul.rm.f32 \t$dst, $src0, $src1;",
 224   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rm_f>;
 225 def INT_NVVM_MUL_RP_FTZ_F : F_MATH_2<"mul.rp.ftz.f32 \t$dst, $src0, $src1;",
 226   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rp_ftz_f>;
 227 def INT_NVVM_MUL_RP_F : F_MATH_2<"mul.rp.f32 \t$dst, $src0, $src1;",
 228   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rp_f>;
 229
 230 def INT_NVVM_MUL_RN_D : F_MATH_2<"mul.rn.f64 \t$dst, $src0, $src1;",
 231   Float64Regs, Float64Regs, Float64Regs, int_nvvm_mul_rn_d>;
 232 def INT_NVVM_MUL_RZ_D : F_MATH_2<"mul.rz.f64 \t$dst, $src0, $src1;",
 233   Float64Regs, Float64Regs, Float64Regs, int_nvvm_mul_rz_d>;
 234 def INT_NVVM_MUL_RM_D : F_MATH_2<"mul.rm.f64 \t$dst, $src0, $src1;",
 235   Float64Regs, Float64Regs, Float64Regs, int_nvvm_mul_rm_d>;
 236 def INT_NVVM_MUL_RP_D : F_MATH_2<"mul.rp.f64 \t$dst, $src0, $src1;",
 237   Float64Regs, Float64Regs, Float64Regs, int_nvvm_mul_rp_d>;
 238
 239 def INT_NVVM_MUL24_I : F_MATH_2<"mul24.lo.s32 \t$dst, $src0, $src1;",
 240   Int32Regs, Int32Regs, Int32Regs, int_nvvm_mul24_i>;
 241 def INT_NVVM_MUL24_UI : F_MATH_2<"mul24.lo.u32 \t$dst, $src0, $src1;",
 242   Int32Regs, Int32Regs, Int32Regs, int_nvvm_mul24_ui>;
 243
 244 //
 245 // Div
 246 //
 247
 248 def INT_NVVM_DIV_APPROX_FTZ_F
 249   : F_MATH_2<"div.approx.ftz.f32 \t$dst, $src0, $src1;", Float32Regs,
 250     Float32Regs, Float32Regs, int_nvvm_div_approx_ftz_f>;
 251 def INT_NVVM_DIV_APPROX_F : F_MATH_2<"div.approx.f32 \t$dst, $src0, $src1;",
 252   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_approx_f>;
 253
 254 def INT_NVVM_DIV_RN_FTZ_F : F_MATH_2<"div.rn.ftz.f32 \t$dst, $src0, $src1;",
 255   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rn_ftz_f>;
 256 def INT_NVVM_DIV_RN_F     : F_MATH_2<"div.rn.f32 \t$dst, $src0, $src1;",
 257   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rn_f>;
 258 def INT_NVVM_DIV_RZ_FTZ_F : F_MATH_2<"div.rz.ftz.f32 \t$dst, $src0, $src1;",
 259   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rz_ftz_f>;
 260 def INT_NVVM_DIV_RZ_F     : F_MATH_2<"div.rz.f32 \t$dst, $src0, $src1;",
 261   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rz_f>;
 262 def INT_NVVM_DIV_RM_FTZ_F : F_MATH_2<"div.rm.ftz.f32 \t$dst, $src0, $src1;",
 263   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rm_ftz_f>;
 264 def INT_NVVM_DIV_RM_F     : F_MATH_2<"div.rm.f32 \t$dst, $src0, $src1;",
 265   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rm_f>;
 266 def INT_NVVM_DIV_RP_FTZ_F : F_MATH_2<"div.rp.ftz.f32 \t$dst, $src0, $src1;",
 267   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rp_ftz_f>;
 268 def INT_NVVM_DIV_RP_F     : F_MATH_2<"div.rp.f32 \t$dst, $src0, $src1;",
 269   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rp_f>;
 270
 271 def INT_NVVM_DIV_RN_D : F_MATH_2<"div.rn.f64 \t$dst, $src0, $src1;",
 272   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rn_d>;
 273 def INT_NVVM_DIV_RZ_D : F_MATH_2<"div.rz.f64 \t$dst, $src0, $src1;",
 274   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rz_d>;
 275 def INT_NVVM_DIV_RM_D : F_MATH_2<"div.rm.f64 \t$dst, $src0, $src1;",
 276   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rm_d>;
 277 def INT_NVVM_DIV_RP_D : F_MATH_2<"div.rp.f64 \t$dst, $src0, $src1;",
 278   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rp_d>;
 279
 280 //
 281 // Brev
 282 //
 283
 284 def INT_NVVM_BREV32 : F_MATH_1<"brev.b32 \t$dst, $src0;", Int32Regs, Int32Regs,
 285   int_nvvm_brev32>;
 286 def INT_NVVM_BREV64 : F_MATH_1<"brev.b64 \t$dst, $src0;", Int64Regs, Int64Regs,
 287   int_nvvm_brev64>;
 288
 289 //
 290 // Sad
 291 //
 292
 293 def INT_NVVM_SAD_I : F_MATH_3<"sad.s32 \t$dst, $src0, $src1, $src2;",
 294   Int32Regs, Int32Regs, Int32Regs, Int32Regs, int_nvvm_sad_i>;
 295 def INT_NVVM_SAD_UI : F_MATH_3<"sad.u32 \t$dst, $src0, $src1, $src2;",
 296   Int32Regs, Int32Regs, Int32Regs, Int32Regs, int_nvvm_sad_ui>;
 297
 298 //
 299 // Floor  Ceil
 300 //
 301
 302 def : Pat<(int_nvvm_floor_ftz_f Float32Regs:$a),
 303           (CVT_f32_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 304 def : Pat<(int_nvvm_floor_f Float32Regs:$a),
 305           (CVT_f32_f32 Float32Regs:$a, CvtRMI)>;
 306 def : Pat<(int_nvvm_floor_d Float64Regs:$a),
 307           (CVT_f64_f64 Float64Regs:$a, CvtRMI)>;
 308
 309 def : Pat<(int_nvvm_ceil_ftz_f Float32Regs:$a),
 310           (CVT_f32_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 311 def : Pat<(int_nvvm_ceil_f Float32Regs:$a),
 312           (CVT_f32_f32 Float32Regs:$a, CvtRPI)>;
 313 def : Pat<(int_nvvm_ceil_d Float64Regs:$a),
 314           (CVT_f64_f64 Float64Regs:$a, CvtRPI)>;
 315
 316 //
 317 // Abs
 318 //
 319
 320 def INT_NVVM_ABS_I : F_MATH_1<"abs.s32 \t$dst, $src0;", Int32Regs, Int32Regs,
 321   int_nvvm_abs_i>;
 322 def INT_NVVM_ABS_LL : F_MATH_1<"abs.s64 \t$dst, $src0;", Int64Regs, Int64Regs,
 323   int_nvvm_abs_ll>;
 324
 325 def INT_NVVM_FABS_FTZ_F : F_MATH_1<"abs.ftz.f32 \t$dst, $src0;", Float32Regs,
 326   Float32Regs, int_nvvm_fabs_ftz_f>;
 327 def INT_NVVM_FABS_F : F_MATH_1<"abs.f32 \t$dst, $src0;", Float32Regs,
 328   Float32Regs, int_nvvm_fabs_f>;
 329
 330 def INT_NVVM_FABS_D : F_MATH_1<"abs.f64 \t$dst, $src0;", Float64Regs,
 331   Float64Regs, int_nvvm_fabs_d>;
 332
 333 //
 334 // Round
 335 //
 336
 337 def : Pat<(int_nvvm_round_ftz_f Float32Regs:$a),
 338           (CVT_f32_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 339 def : Pat<(int_nvvm_round_f Float32Regs:$a),
 340           (CVT_f32_f32 Float32Regs:$a, CvtRNI)>;
 341 def : Pat<(int_nvvm_round_d Float64Regs:$a),
 342           (CVT_f64_f64 Float64Regs:$a, CvtRNI)>;
 343
 344 //
 345 // Trunc
 346 //
 347
 348 def : Pat<(int_nvvm_trunc_ftz_f Float32Regs:$a),
 349           (CVT_f32_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 350 def : Pat<(int_nvvm_trunc_f Float32Regs:$a),
 351           (CVT_f32_f32 Float32Regs:$a, CvtRZI)>;
 352 def : Pat<(int_nvvm_trunc_d Float64Regs:$a),
 353           (CVT_f64_f64 Float64Regs:$a, CvtRZI)>;
 354
 355 //
 356 // Saturate
 357 //
 358
 359 def : Pat<(int_nvvm_saturate_ftz_f Float32Regs:$a),
 360           (CVT_f32_f32 Float32Regs:$a, CvtSAT_FTZ)>;
 361 def : Pat<(int_nvvm_saturate_f Float32Regs:$a),
 362           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
 363 def : Pat<(int_nvvm_saturate_d Float64Regs:$a),
 364           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 365
 366 //
 367 // Exp2  Log2
 368 //
 369
 370 def INT_NVVM_EX2_APPROX_FTZ_F : F_MATH_1<"ex2.approx.ftz.f32 \t$dst, $src0;",
 371   Float32Regs, Float32Regs, int_nvvm_ex2_approx_ftz_f>;
 372 def INT_NVVM_EX2_APPROX_F : F_MATH_1<"ex2.approx.f32 \t$dst, $src0;",
 373   Float32Regs, Float32Regs, int_nvvm_ex2_approx_f>;
 374 def INT_NVVM_EX2_APPROX_D : F_MATH_1<"ex2.approx.f64 \t$dst, $src0;",
 375   Float64Regs, Float64Regs, int_nvvm_ex2_approx_d>;
 376
 377 def INT_NVVM_LG2_APPROX_FTZ_F : F_MATH_1<"lg2.approx.ftz.f32 \t$dst, $src0;",
 378   Float32Regs, Float32Regs, int_nvvm_lg2_approx_ftz_f>;
 379 def INT_NVVM_LG2_APPROX_F : F_MATH_1<"lg2.approx.f32 \t$dst, $src0;",
 380   Float32Regs, Float32Regs, int_nvvm_lg2_approx_f>;
 381 def INT_NVVM_LG2_APPROX_D : F_MATH_1<"lg2.approx.f64 \t$dst, $src0;",
 382   Float64Regs, Float64Regs, int_nvvm_lg2_approx_d>;
 383
 384 //
 385 // Sin  Cos
 386 //
 387
 388 def INT_NVVM_SIN_APPROX_FTZ_F : F_MATH_1<"sin.approx.ftz.f32 \t$dst, $src0;",
 389   Float32Regs, Float32Regs, int_nvvm_sin_approx_ftz_f>;
 390 def INT_NVVM_SIN_APPROX_F : F_MATH_1<"sin.approx.f32 \t$dst, $src0;",
 391   Float32Regs, Float32Regs, int_nvvm_sin_approx_f>;
 392
 393 def INT_NVVM_COS_APPROX_FTZ_F : F_MATH_1<"cos.approx.ftz.f32 \t$dst, $src0;",
 394   Float32Regs, Float32Regs, int_nvvm_cos_approx_ftz_f>;
 395 def INT_NVVM_COS_APPROX_F : F_MATH_1<"cos.approx.f32 \t$dst, $src0;",
 396   Float32Regs, Float32Regs, int_nvvm_cos_approx_f>;
 397
 398 //
 399 // Fma
 400 //
 401
 402 def INT_NVVM_FMA_RN_FTZ_F
 403   : F_MATH_3<"fma.rn.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
 404     Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rn_ftz_f>;
 405 def INT_NVVM_FMA_RN_F : F_MATH_3<"fma.rn.f32 \t$dst, $src0, $src1, $src2;",
 406   Float32Regs, Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rn_f>;
 407 def INT_NVVM_FMA_RZ_FTZ_F
 408   : F_MATH_3<"fma.rz.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
 409     Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rz_ftz_f>;
 410 def INT_NVVM_FMA_RZ_F : F_MATH_3<"fma.rz.f32 \t$dst, $src0, $src1, $src2;",
 411   Float32Regs, Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rz_f>;
 412 def INT_NVVM_FMA_RM_FTZ_F
 413   : F_MATH_3<"fma.rm.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
 414     Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rm_ftz_f>;
 415 def INT_NVVM_FMA_RM_F : F_MATH_3<"fma.rm.f32 \t$dst, $src0, $src1, $src2;",
 416   Float32Regs, Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rm_f>;
 417 def INT_NVVM_FMA_RP_FTZ_F
 418   : F_MATH_3<"fma.rp.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
 419     Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rp_ftz_f>;
 420 def INT_NVVM_FMA_RP_F : F_MATH_3<"fma.rp.f32 \t$dst, $src0, $src1, $src2;",
 421   Float32Regs, Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rp_f>;
 422
 423 def INT_NVVM_FMA_RN_D : F_MATH_3<"fma.rn.f64 \t$dst, $src0, $src1, $src2;",
 424   Float64Regs, Float64Regs, Float64Regs, Float64Regs, int_nvvm_fma_rn_d>;
 425 def INT_NVVM_FMA_RZ_D : F_MATH_3<"fma.rz.f64 \t$dst, $src0, $src1, $src2;",
 426   Float64Regs, Float64Regs, Float64Regs, Float64Regs, int_nvvm_fma_rz_d>;
 427 def INT_NVVM_FMA_RM_D : F_MATH_3<"fma.rm.f64 \t$dst, $src0, $src1, $src2;",
 428   Float64Regs, Float64Regs, Float64Regs, Float64Regs, int_nvvm_fma_rm_d>;
 429 def INT_NVVM_FMA_RP_D : F_MATH_3<"fma.rp.f64 \t$dst, $src0, $src1, $src2;",
 430   Float64Regs, Float64Regs, Float64Regs, Float64Regs, int_nvvm_fma_rp_d>;
 431
 432 //
 433 // Rcp
 434 //
 435
 436 def INT_NVVM_RCP_RN_FTZ_F : F_MATH_1<"rcp.rn.ftz.f32 \t$dst, $src0;",
 437   Float32Regs, Float32Regs, int_nvvm_rcp_rn_ftz_f>;
 438 def INT_NVVM_RCP_RN_F : F_MATH_1<"rcp.rn.f32 \t$dst, $src0;",
 439   Float32Regs, Float32Regs, int_nvvm_rcp_rn_f>;
 440 def INT_NVVM_RCP_RZ_FTZ_F : F_MATH_1<"rcp.rz.ftz.f32 \t$dst, $src0;",
 441   Float32Regs, Float32Regs, int_nvvm_rcp_rz_ftz_f>;
 442 def INT_NVVM_RCP_RZ_F : F_MATH_1<"rcp.rz.f32 \t$dst, $src0;",
 443   Float32Regs, Float32Regs, int_nvvm_rcp_rz_f>;
 444 def INT_NVVM_RCP_RM_FTZ_F : F_MATH_1<"rcp.rm.ftz.f32 \t$dst, $src0;",
 445   Float32Regs, Float32Regs, int_nvvm_rcp_rm_ftz_f>;
 446 def INT_NVVM_RCP_RM_F : F_MATH_1<"rcp.rm.f32 \t$dst, $src0;",
 447   Float32Regs, Float32Regs, int_nvvm_rcp_rm_f>;
 448 def INT_NVVM_RCP_RP_FTZ_F : F_MATH_1<"rcp.rp.ftz.f32 \t$dst, $src0;",
 449   Float32Regs, Float32Regs, int_nvvm_rcp_rp_ftz_f>;
 450 def INT_NVVM_RCP_RP_F : F_MATH_1<"rcp.rp.f32 \t$dst, $src0;",
 451   Float32Regs, Float32Regs, int_nvvm_rcp_rp_f>;
 452
 453 def INT_NVVM_RCP_RN_D : F_MATH_1<"rcp.rn.f64 \t$dst, $src0;", Float64Regs,
 454   Float64Regs, int_nvvm_rcp_rn_d>;
 455 def INT_NVVM_RCP_RZ_D : F_MATH_1<"rcp.rz.f64 \t$dst, $src0;", Float64Regs,
 456   Float64Regs, int_nvvm_rcp_rz_d>;
 457 def INT_NVVM_RCP_RM_D : F_MATH_1<"rcp.rm.f64 \t$dst, $src0;", Float64Regs,
 458   Float64Regs, int_nvvm_rcp_rm_d>;
 459 def INT_NVVM_RCP_RP_D : F_MATH_1<"rcp.rp.f64 \t$dst, $src0;", Float64Regs,
 460   Float64Regs, int_nvvm_rcp_rp_d>;
 461
 462 def INT_NVVM_RCP_APPROX_FTZ_D : F_MATH_1<"rcp.approx.ftz.f64 \t$dst, $src0;",
 463   Float64Regs, Float64Regs, int_nvvm_rcp_approx_ftz_d>;
 464
 465 //
 466 // Sqrt
 467 //
 468
 469 def INT_NVVM_SQRT_RN_FTZ_F : F_MATH_1<"sqrt.rn.ftz.f32 \t$dst, $src0;",
 470   Float32Regs, Float32Regs, int_nvvm_sqrt_rn_ftz_f>;
 471 def INT_NVVM_SQRT_RN_F : F_MATH_1<"sqrt.rn.f32 \t$dst, $src0;", Float32Regs,
 472   Float32Regs, int_nvvm_sqrt_rn_f>;
 473 def INT_NVVM_SQRT_RZ_FTZ_F : F_MATH_1<"sqrt.rz.ftz.f32 \t$dst, $src0;",
 474   Float32Regs, Float32Regs, int_nvvm_sqrt_rz_ftz_f>;
 475 def INT_NVVM_SQRT_RZ_F : F_MATH_1<"sqrt.rz.f32 \t$dst, $src0;", Float32Regs,
 476   Float32Regs, int_nvvm_sqrt_rz_f>;
 477 def INT_NVVM_SQRT_RM_FTZ_F : F_MATH_1<"sqrt.rm.ftz.f32 \t$dst, $src0;",
 478   Float32Regs, Float32Regs, int_nvvm_sqrt_rm_ftz_f>;
 479 def INT_NVVM_SQRT_RM_F : F_MATH_1<"sqrt.rm.f32 \t$dst, $src0;", Float32Regs,
 480   Float32Regs, int_nvvm_sqrt_rm_f>;
 481 def INT_NVVM_SQRT_RP_FTZ_F : F_MATH_1<"sqrt.rp.ftz.f32 \t$dst, $src0;",
 482   Float32Regs, Float32Regs, int_nvvm_sqrt_rp_ftz_f>;
 483 def INT_NVVM_SQRT_RP_F : F_MATH_1<"sqrt.rp.f32 \t$dst, $src0;", Float32Regs,
 484   Float32Regs, int_nvvm_sqrt_rp_f>;
 485 def INT_NVVM_SQRT_APPROX_FTZ_F : F_MATH_1<"sqrt.approx.ftz.f32 \t$dst, $src0;",
 486   Float32Regs, Float32Regs, int_nvvm_sqrt_approx_ftz_f>;
 487 def INT_NVVM_SQRT_APPROX_F : F_MATH_1<"sqrt.approx.f32 \t$dst, $src0;",
 488   Float32Regs, Float32Regs, int_nvvm_sqrt_approx_f>;
 489
 490 def INT_NVVM_SQRT_RN_D : F_MATH_1<"sqrt.rn.f64 \t$dst, $src0;", Float64Regs,
 491   Float64Regs, int_nvvm_sqrt_rn_d>;
 492 def INT_NVVM_SQRT_RZ_D : F_MATH_1<"sqrt.rz.f64 \t$dst, $src0;", Float64Regs,
 493   Float64Regs, int_nvvm_sqrt_rz_d>;
 494 def INT_NVVM_SQRT_RM_D : F_MATH_1<"sqrt.rm.f64 \t$dst, $src0;", Float64Regs,
 495   Float64Regs, int_nvvm_sqrt_rm_d>;
 496 def INT_NVVM_SQRT_RP_D : F_MATH_1<"sqrt.rp.f64 \t$dst, $src0;", Float64Regs,
 497   Float64Regs, int_nvvm_sqrt_rp_d>;
 498
 499 // nvvm_sqrt intrinsic
 500 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
 501           (INT_NVVM_SQRT_RN_FTZ_F Float32Regs:$a)>, Requires<[doF32FTZ, do_SQRTF32_RN]>;
 502 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
 503           (INT_NVVM_SQRT_RN_F Float32Regs:$a)>, Requires<[do_SQRTF32_RN]>;
 504 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
 505           (INT_NVVM_SQRT_APPROX_FTZ_F Float32Regs:$a)>, Requires<[doF32FTZ]>;
 506 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
 507           (INT_NVVM_SQRT_APPROX_F Float32Regs:$a)>;
 508
 509 //
 510 // Rsqrt
 511 //
 512
 513 def INT_NVVM_RSQRT_APPROX_FTZ_F
 514   : F_MATH_1<"rsqrt.approx.ftz.f32 \t$dst, $src0;", Float32Regs, Float32Regs,
 515     int_nvvm_rsqrt_approx_ftz_f>;
 516 def INT_NVVM_RSQRT_APPROX_F : F_MATH_1<"rsqrt.approx.f32 \t$dst, $src0;",
 517   Float32Regs, Float32Regs, int_nvvm_rsqrt_approx_f>;
 518 def INT_NVVM_RSQRT_APPROX_D : F_MATH_1<"rsqrt.approx.f64 \t$dst, $src0;",
 519   Float64Regs, Float64Regs, int_nvvm_rsqrt_approx_d>;
 520
 521 //
 522 // Add
 523 //
 524
 525 def INT_NVVM_ADD_RN_FTZ_F : F_MATH_2<"add.rn.ftz.f32 \t$dst, $src0, $src1;",
 526   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rn_ftz_f>;
 527 def INT_NVVM_ADD_RN_F : F_MATH_2<"add.rn.f32 \t$dst, $src0, $src1;",
 528   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rn_f>;
 529 def INT_NVVM_ADD_RZ_FTZ_F : F_MATH_2<"add.rz.ftz.f32 \t$dst, $src0, $src1;",
 530   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rz_ftz_f>;
 531 def INT_NVVM_ADD_RZ_F : F_MATH_2<"add.rz.f32 \t$dst, $src0, $src1;",
 532   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rz_f>;
 533 def INT_NVVM_ADD_RM_FTZ_F : F_MATH_2<"add.rm.ftz.f32 \t$dst, $src0, $src1;",
 534   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rm_ftz_f>;
 535 def INT_NVVM_ADD_RM_F : F_MATH_2<"add.rm.f32 \t$dst, $src0, $src1;",
 536   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rm_f>;
 537 def INT_NVVM_ADD_RP_FTZ_F : F_MATH_2<"add.rp.ftz.f32 \t$dst, $src0, $src1;",
 538   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rp_ftz_f>;
 539 def INT_NVVM_ADD_RP_F : F_MATH_2<"add.rp.f32 \t$dst, $src0, $src1;",
 540   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rp_f>;
 541
 542 def INT_NVVM_ADD_RN_D : F_MATH_2<"add.rn.f64 \t$dst, $src0, $src1;",
 543   Float64Regs, Float64Regs, Float64Regs, int_nvvm_add_rn_d>;
 544 def INT_NVVM_ADD_RZ_D : F_MATH_2<"add.rz.f64 \t$dst, $src0, $src1;",
 545   Float64Regs, Float64Regs, Float64Regs, int_nvvm_add_rz_d>;
 546 def INT_NVVM_ADD_RM_D : F_MATH_2<"add.rm.f64 \t$dst, $src0, $src1;",
 547   Float64Regs, Float64Regs, Float64Regs, int_nvvm_add_rm_d>;
 548 def INT_NVVM_ADD_RP_D : F_MATH_2<"add.rp.f64 \t$dst, $src0, $src1;",
 549   Float64Regs, Float64Regs, Float64Regs, int_nvvm_add_rp_d>;
 550
 551 //
 552 // Convert
 553 //
 554
 555 def : Pat<(int_nvvm_d2f_rn_ftz Float64Regs:$a),
 556           (CVT_f32_f64 Float64Regs:$a, CvtRN_FTZ)>;
 557 def : Pat<(int_nvvm_d2f_rn Float64Regs:$a),
 558           (CVT_f32_f64 Float64Regs:$a, CvtRN)>;
 559 def : Pat<(int_nvvm_d2f_rz_ftz Float64Regs:$a),
 560           (CVT_f32_f64 Float64Regs:$a, CvtRZ_FTZ)>;
 561 def : Pat<(int_nvvm_d2f_rz Float64Regs:$a),
 562           (CVT_f32_f64 Float64Regs:$a, CvtRZ)>;
 563 def : Pat<(int_nvvm_d2f_rm_ftz Float64Regs:$a),
 564           (CVT_f32_f64 Float64Regs:$a, CvtRM_FTZ)>;
 565 def : Pat<(int_nvvm_d2f_rm Float64Regs:$a),
 566           (CVT_f32_f64 Float64Regs:$a, CvtRM)>;
 567 def : Pat<(int_nvvm_d2f_rp_ftz Float64Regs:$a),
 568           (CVT_f32_f64 Float64Regs:$a, CvtRP_FTZ)>;
 569 def : Pat<(int_nvvm_d2f_rp Float64Regs:$a),
 570           (CVT_f32_f64 Float64Regs:$a, CvtRP)>;
 571
 572 def : Pat<(int_nvvm_d2i_rn Float64Regs:$a),
 573           (CVT_s32_f64 Float64Regs:$a, CvtRNI)>;
 574 def : Pat<(int_nvvm_d2i_rz Float64Regs:$a),
 575           (CVT_s32_f64 Float64Regs:$a, CvtRZI)>;
 576 def : Pat<(int_nvvm_d2i_rm Float64Regs:$a),
 577           (CVT_s32_f64 Float64Regs:$a, CvtRMI)>;
 578 def : Pat<(int_nvvm_d2i_rp Float64Regs:$a),
 579           (CVT_s32_f64 Float64Regs:$a, CvtRPI)>;
 580
 581 def : Pat<(int_nvvm_d2ui_rn Float64Regs:$a),
 582           (CVT_u32_f64 Float64Regs:$a, CvtRNI)>;
 583 def : Pat<(int_nvvm_d2ui_rz Float64Regs:$a),
 584           (CVT_u32_f64 Float64Regs:$a, CvtRZI)>;
 585 def : Pat<(int_nvvm_d2ui_rm Float64Regs:$a),
 586           (CVT_u32_f64 Float64Regs:$a, CvtRMI)>;
 587 def : Pat<(int_nvvm_d2ui_rp Float64Regs:$a),
 588           (CVT_u32_f64 Float64Regs:$a, CvtRPI)>;
 589
 590 def : Pat<(int_nvvm_i2d_rn Int32Regs:$a),
 591           (CVT_f64_s32 Int32Regs:$a, CvtRN)>;
 592 def : Pat<(int_nvvm_i2d_rz Int32Regs:$a),
 593           (CVT_f64_s32 Int32Regs:$a, CvtRZ)>;
 594 def : Pat<(int_nvvm_i2d_rm Int32Regs:$a),
 595           (CVT_f64_s32 Int32Regs:$a, CvtRM)>;
 596 def : Pat<(int_nvvm_i2d_rp Int32Regs:$a),
 597           (CVT_f64_s32 Int32Regs:$a, CvtRP)>;
 598
 599 def : Pat<(int_nvvm_ui2d_rn Int32Regs:$a),
 600           (CVT_f64_u32 Int32Regs:$a, CvtRN)>;
 601 def : Pat<(int_nvvm_ui2d_rz Int32Regs:$a),
 602           (CVT_f64_u32 Int32Regs:$a, CvtRZ)>;
 603 def : Pat<(int_nvvm_ui2d_rm Int32Regs:$a),
 604           (CVT_f64_u32 Int32Regs:$a, CvtRM)>;
 605 def : Pat<(int_nvvm_ui2d_rp Int32Regs:$a),
 606           (CVT_f64_u32 Int32Regs:$a, CvtRP)>;
 607
 608 def : Pat<(int_nvvm_f2i_rn_ftz Float32Regs:$a),
 609           (CVT_s32_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 610 def : Pat<(int_nvvm_f2i_rn Float32Regs:$a),
 611           (CVT_s32_f32 Float32Regs:$a, CvtRNI)>;
 612 def : Pat<(int_nvvm_f2i_rz_ftz Float32Regs:$a),
 613           (CVT_s32_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 614 def : Pat<(int_nvvm_f2i_rz Float32Regs:$a),
 615           (CVT_s32_f32 Float32Regs:$a, CvtRZI)>;
 616 def : Pat<(int_nvvm_f2i_rm_ftz Float32Regs:$a),
 617           (CVT_s32_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 618 def : Pat<(int_nvvm_f2i_rm Float32Regs:$a),
 619           (CVT_s32_f32 Float32Regs:$a, CvtRMI)>;
 620 def : Pat<(int_nvvm_f2i_rp_ftz Float32Regs:$a),
 621           (CVT_s32_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 622 def : Pat<(int_nvvm_f2i_rp Float32Regs:$a),
 623           (CVT_s32_f32 Float32Regs:$a, CvtRPI)>;
 624
 625 def : Pat<(int_nvvm_f2ui_rn_ftz Float32Regs:$a),
 626           (CVT_u32_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 627 def : Pat<(int_nvvm_f2ui_rn Float32Regs:$a),
 628           (CVT_u32_f32 Float32Regs:$a, CvtRNI)>;
 629 def : Pat<(int_nvvm_f2ui_rz_ftz Float32Regs:$a),
 630           (CVT_u32_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 631 def : Pat<(int_nvvm_f2ui_rz Float32Regs:$a),
 632           (CVT_u32_f32 Float32Regs:$a, CvtRZI)>;
 633 def : Pat<(int_nvvm_f2ui_rm_ftz Float32Regs:$a),
 634           (CVT_u32_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 635 def : Pat<(int_nvvm_f2ui_rm Float32Regs:$a),
 636           (CVT_u32_f32 Float32Regs:$a, CvtRMI)>;
 637 def : Pat<(int_nvvm_f2ui_rp_ftz Float32Regs:$a),
 638           (CVT_u32_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 639 def : Pat<(int_nvvm_f2ui_rp Float32Regs:$a),
 640           (CVT_u32_f32 Float32Regs:$a, CvtRPI)>;
 641
 642 def : Pat<(int_nvvm_i2f_rn Int32Regs:$a),
 643           (CVT_f32_s32 Int32Regs:$a, CvtRN)>;
 644 def : Pat<(int_nvvm_i2f_rz Int32Regs:$a),
 645           (CVT_f32_s32 Int32Regs:$a, CvtRZ)>;
 646 def : Pat<(int_nvvm_i2f_rm Int32Regs:$a),
 647           (CVT_f32_s32 Int32Regs:$a, CvtRM)>;
 648 def : Pat<(int_nvvm_i2f_rp Int32Regs:$a),
 649           (CVT_f32_s32 Int32Regs:$a, CvtRP)>;
 650
 651 def : Pat<(int_nvvm_ui2f_rn Int32Regs:$a),
 652           (CVT_f32_u32 Int32Regs:$a, CvtRN)>;
 653 def : Pat<(int_nvvm_ui2f_rz Int32Regs:$a),
 654           (CVT_f32_u32 Int32Regs:$a, CvtRZ)>;
 655 def : Pat<(int_nvvm_ui2f_rm Int32Regs:$a),
 656           (CVT_f32_u32 Int32Regs:$a, CvtRM)>;
 657 def : Pat<(int_nvvm_ui2f_rp Int32Regs:$a),
 658           (CVT_f32_u32 Int32Regs:$a, CvtRP)>;
 659
 660 def INT_NVVM_LOHI_I2D : F_MATH_2<"mov.b64 \t$dst, {{$src0, $src1}};",
 661   Float64Regs, Int32Regs, Int32Regs, int_nvvm_lohi_i2d>;
 662
 663 def INT_NVVM_D2I_LO : F_MATH_1<!strconcat("{{\n\t",
 664                        !strconcat(".reg .b32 %temp; \n\t",
 665              !strconcat("mov.b64 \t{$dst, %temp}, $src0;\n\t",
 666                "}}"))),
 667              Int32Regs, Float64Regs, int_nvvm_d2i_lo>;
 668 def INT_NVVM_D2I_HI : F_MATH_1<!strconcat("{{\n\t",
 669                        !strconcat(".reg .b32 %temp; \n\t",
 670                          !strconcat("mov.b64 \t{%temp, $dst}, $src0;\n\t",
 671                            "}}"))),
 672              Int32Regs, Float64Regs, int_nvvm_d2i_hi>;
 673
 674 def : Pat<(int_nvvm_f2ll_rn_ftz Float32Regs:$a),
 675           (CVT_s64_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 676 def : Pat<(int_nvvm_f2ll_rn Float32Regs:$a),
 677           (CVT_s64_f32 Float32Regs:$a, CvtRNI)>;
 678 def : Pat<(int_nvvm_f2ll_rz_ftz Float32Regs:$a),
 679           (CVT_s64_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 680 def : Pat<(int_nvvm_f2ll_rz Float32Regs:$a),
 681           (CVT_s64_f32 Float32Regs:$a, CvtRZI)>;
 682 def : Pat<(int_nvvm_f2ll_rm_ftz Float32Regs:$a),
 683           (CVT_s64_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 684 def : Pat<(int_nvvm_f2ll_rm Float32Regs:$a),
 685           (CVT_s64_f32 Float32Regs:$a, CvtRMI)>;
 686 def : Pat<(int_nvvm_f2ll_rp_ftz Float32Regs:$a),
 687           (CVT_s64_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 688 def : Pat<(int_nvvm_f2ll_rp Float32Regs:$a),
 689           (CVT_s64_f32 Float32Regs:$a, CvtRPI)>;
 690
 691 def : Pat<(int_nvvm_f2ull_rn_ftz Float32Regs:$a),
 692           (CVT_u64_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 693 def : Pat<(int_nvvm_f2ull_rn Float32Regs:$a),
 694           (CVT_u64_f32 Float32Regs:$a, CvtRNI)>;
 695 def : Pat<(int_nvvm_f2ull_rz_ftz Float32Regs:$a),
 696           (CVT_u64_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 697 def : Pat<(int_nvvm_f2ull_rz Float32Regs:$a),
 698           (CVT_u64_f32 Float32Regs:$a, CvtRZI)>;
 699 def : Pat<(int_nvvm_f2ull_rm_ftz Float32Regs:$a),
 700           (CVT_u64_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 701 def : Pat<(int_nvvm_f2ull_rm Float32Regs:$a),
 702           (CVT_u64_f32 Float32Regs:$a, CvtRMI)>;
 703 def : Pat<(int_nvvm_f2ull_rp_ftz Float32Regs:$a),
 704           (CVT_u64_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 705 def : Pat<(int_nvvm_f2ull_rp Float32Regs:$a),
 706           (CVT_u64_f32 Float32Regs:$a, CvtRPI)>;
 707
 708 def : Pat<(int_nvvm_d2ll_rn Float64Regs:$a),
 709           (CVT_s64_f64 Float64Regs:$a, CvtRNI)>;
 710 def : Pat<(int_nvvm_d2ll_rz Float64Regs:$a),
 711           (CVT_s64_f64 Float64Regs:$a, CvtRZI)>;
 712 def : Pat<(int_nvvm_d2ll_rm Float64Regs:$a),
 713           (CVT_s64_f64 Float64Regs:$a, CvtRMI)>;
 714 def : Pat<(int_nvvm_d2ll_rp Float64Regs:$a),
 715           (CVT_s64_f64 Float64Regs:$a, CvtRPI)>;
 716
 717 def : Pat<(int_nvvm_d2ull_rn Float64Regs:$a),
 718           (CVT_u64_f64 Float64Regs:$a, CvtRNI)>;
 719 def : Pat<(int_nvvm_d2ull_rz Float64Regs:$a),
 720           (CVT_u64_f64 Float64Regs:$a, CvtRZI)>;
 721 def : Pat<(int_nvvm_d2ull_rm Float64Regs:$a),
 722           (CVT_u64_f64 Float64Regs:$a, CvtRMI)>;
 723 def : Pat<(int_nvvm_d2ull_rp Float64Regs:$a),
 724           (CVT_u64_f64 Float64Regs:$a, CvtRPI)>;
 725
 726 def : Pat<(int_nvvm_ll2f_rn Int64Regs:$a),
 727           (CVT_f32_s64 Int64Regs:$a, CvtRN)>;
 728 def : Pat<(int_nvvm_ll2f_rz Int64Regs:$a),
 729           (CVT_f32_s64 Int64Regs:$a, CvtRZ)>;
 730 def : Pat<(int_nvvm_ll2f_rm Int64Regs:$a),
 731           (CVT_f32_s64 Int64Regs:$a, CvtRM)>;
 732 def : Pat<(int_nvvm_ll2f_rp Int64Regs:$a),
 733           (CVT_f32_s64 Int64Regs:$a, CvtRP)>;
 734
 735 def : Pat<(int_nvvm_ull2f_rn Int64Regs:$a),
 736           (CVT_f32_u64 Int64Regs:$a, CvtRN)>;
 737 def : Pat<(int_nvvm_ull2f_rz Int64Regs:$a),
 738           (CVT_f32_u64 Int64Regs:$a, CvtRZ)>;
 739 def : Pat<(int_nvvm_ull2f_rm Int64Regs:$a),
 740           (CVT_f32_u64 Int64Regs:$a, CvtRM)>;
 741 def : Pat<(int_nvvm_ull2f_rp Int64Regs:$a),
 742           (CVT_f32_u64 Int64Regs:$a, CvtRP)>;
 743
 744 def : Pat<(int_nvvm_ll2d_rn Int64Regs:$a),
 745           (CVT_f64_s64 Int64Regs:$a, CvtRN)>;
 746 def : Pat<(int_nvvm_ll2d_rz Int64Regs:$a),
 747           (CVT_f64_s64 Int64Regs:$a, CvtRZ)>;
 748 def : Pat<(int_nvvm_ll2d_rm Int64Regs:$a),
 749           (CVT_f64_s64 Int64Regs:$a, CvtRM)>;
 750 def : Pat<(int_nvvm_ll2d_rp Int64Regs:$a),
 751           (CVT_f64_s64 Int64Regs:$a, CvtRP)>;
 752
 753 def : Pat<(int_nvvm_ull2d_rn Int64Regs:$a),
 754           (CVT_f64_u64 Int64Regs:$a, CvtRN)>;
 755 def : Pat<(int_nvvm_ull2d_rz Int64Regs:$a),
 756           (CVT_f64_u64 Int64Regs:$a, CvtRZ)>;
 757 def : Pat<(int_nvvm_ull2d_rm Int64Regs:$a),
 758           (CVT_f64_u64 Int64Regs:$a, CvtRM)>;
 759 def : Pat<(int_nvvm_ull2d_rp Int64Regs:$a),
 760           (CVT_f64_u64 Int64Regs:$a, CvtRP)>;
 761
 762
 763 // FIXME: Ideally, we could use these patterns instead of the scope-creating
 764 // patterns, but ptxas does not like these since .s16 is not compatible with
 765 // .f16.  The solution is to use .bXX for all integer register types, but we
 766 // are not there yet.
 767 //def : Pat<(int_nvvm_f2h_rn_ftz Float32Regs:$a),
 768 //          (CVT_f16_f32 Float32Regs:$a, CvtRN_FTZ)>;
 769 //def : Pat<(int_nvvm_f2h_rn Float32Regs:$a),
 770 //          (CVT_f16_f32 Float32Regs:$a, CvtRN)>;
 771 //
 772 //def : Pat<(int_nvvm_h2f Int16Regs:$a),
 773 //          (CVT_f32_f16 Int16Regs:$a, CvtNONE)>;
 774
 775 def INT_NVVM_F2H_RN_FTZ : F_MATH_1<!strconcat("{{\n\t",
 776                                    !strconcat(".reg .b16 %temp;\n\t",
 777            !strconcat("cvt.rn.ftz.f16.f32 \t%temp, $src0;\n\t",
 778            !strconcat("mov.b16 \t$dst, %temp;\n",
 779              "}}")))),
 780                                    Int16Regs, Float32Regs, int_nvvm_f2h_rn_ftz>;
 781 def INT_NVVM_F2H_RN : F_MATH_1<!strconcat("{{\n\t",
 782                                    !strconcat(".reg .b16 %temp;\n\t",
 783            !strconcat("cvt.rn.f16.f32 \t%temp, $src0;\n\t",
 784            !strconcat("mov.b16 \t$dst, %temp;\n",
 785              "}}")))),
 786            Int16Regs, Float32Regs, int_nvvm_f2h_rn>;
 787
 788 def INT_NVVM_H2F : F_MATH_1<!strconcat("{{\n\t",
 789                             !strconcat(".reg .b16 %temp;\n\t",
 790           !strconcat("mov.b16 \t%temp, $src0;\n\t",
 791           !strconcat("cvt.f32.f16 \t$dst, %temp;\n\t",
 792             "}}")))),
 793           Float32Regs, Int16Regs, int_nvvm_h2f>;
 794
 795 def : Pat<(f32 (f16_to_f32 Int16Regs:$a)),
 796           (CVT_f32_f16 Int16Regs:$a, CvtNONE)>;
 797 def : Pat<(i16 (f32_to_f16 Float32Regs:$a)),
 798           (CVT_f16_f32 Float32Regs:$a, CvtRN_FTZ)>, Requires<[doF32FTZ]>;
 799 def : Pat<(i16 (f32_to_f16 Float32Regs:$a)),
 800           (CVT_f16_f32 Float32Regs:$a, CvtRN)>;
 801
 802 //
 803 // Bitcast
 804 //
 805
 806 def INT_NVVM_BITCAST_F2I : F_MATH_1<"mov.b32 \t$dst, $src0;", Int32Regs,
 807   Float32Regs, int_nvvm_bitcast_f2i>;
 808 def INT_NVVM_BITCAST_I2F : F_MATH_1<"mov.b32 \t$dst, $src0;", Float32Regs,
 809   Int32Regs, int_nvvm_bitcast_i2f>;
 810
 811 def INT_NVVM_BITCAST_LL2D : F_MATH_1<"mov.b64 \t$dst, $src0;", Float64Regs,
 812   Int64Regs, int_nvvm_bitcast_ll2d>;
 813 def INT_NVVM_BITCAST_D2LL : F_MATH_1<"mov.b64 \t$dst, $src0;", Int64Regs,
 814   Float64Regs, int_nvvm_bitcast_d2ll>;
 815
 816 //-----------------------------------
 817 // Atomic Functions
 818 //-----------------------------------
 819
 820 class ATOMIC_GLOBAL_CHK <dag ops, dag frag>
 821  : PatFrag<ops, frag, [{
 822    return ChkMemSDNodeAddressSpace(N, llvm::ADDRESS_SPACE_GLOBAL);
 823 }]>;
 824 class ATOMIC_SHARED_CHK <dag ops, dag frag>
 825  : PatFrag<ops, frag, [{
 826    return ChkMemSDNodeAddressSpace(N, llvm::ADDRESS_SPACE_SHARED);
 827 }]>;
 828 class ATOMIC_GENERIC_CHK <dag ops, dag frag>
 829  : PatFrag<ops, frag, [{
 830    return ChkMemSDNodeAddressSpace(N, llvm::ADDRESS_SPACE_GENERIC);
 831 }]>;
 832
 833 multiclass F_ATOMIC_2_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
 834   string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
 835   Operand IMMType, SDNode IMM, Predicate Pred> {
 836   def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
 837                !strconcat("atom",
 838          !strconcat(SpaceStr,
 839          !strconcat(OpcStr,
 840          !strconcat(TypeStr,
 841          !strconcat(" \t$dst, [$addr], $b;", ""))))),
 842          [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
 843   Requires<[Pred]>;
 844   def imm : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, IMMType:$b),
 845                !strconcat("atom",
 846          !strconcat(SpaceStr,
 847          !strconcat(OpcStr,
 848          !strconcat(TypeStr,
 849          !strconcat(" \t$dst, [$addr], $b;", ""))))),
 850          [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
 851   Requires<[Pred]>;
 852 }
 853 multiclass F_ATOMIC_2<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
 854   string OpcStr, PatFrag IntOp, Operand IMMType, SDNode IMM, Predicate Pred> {
 855   defm p32 : F_ATOMIC_2_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
 856     IntOp, IMMType, IMM, Pred>;
 857   defm p64 : F_ATOMIC_2_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
 858     IntOp, IMMType, IMM, Pred>;
 859 }
 860
 861 // has 2 operands, neg the second one
 862 multiclass F_ATOMIC_2_NEG_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
 863   string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
 864   Operand IMMType, Predicate Pred> {
 865   def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
 866     !strconcat("{{ \n\t",
 867          !strconcat(".reg \t.s",
 868          !strconcat(TypeStr,
 869          !strconcat(" temp; \n\t",
 870          !strconcat("neg.s",
 871          !strconcat(TypeStr,
 872          !strconcat(" \ttemp, $b; \n\t",
 873                !strconcat("atom",
 874          !strconcat(SpaceStr,
 875          !strconcat(OpcStr,
 876          !strconcat(".u",
 877          !strconcat(TypeStr,
 878          !strconcat(" \t$dst, [$addr], temp; \n\t",
 879            !strconcat("}}", "")))))))))))))),
 880          [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
 881   Requires<[Pred]>;
 882 }
 883 multiclass F_ATOMIC_2_NEG<NVPTXRegClass regclass, string SpaceStr,
 884   string TypeStr, string OpcStr, PatFrag IntOp, Operand IMMType,
 885   Predicate Pred> {
 886  defm p32: F_ATOMIC_2_NEG_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
 887    IntOp, IMMType, Pred> ;
 888  defm p64: F_ATOMIC_2_NEG_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
 889    IntOp, IMMType, Pred> ;
 890 }
 891
 892 // has 3 operands
 893 multiclass F_ATOMIC_3_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
 894   string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
 895   Operand IMMType, Predicate Pred> {
 896   def reg : NVPTXInst<(outs regclass:$dst),
 897     (ins ptrclass:$addr, regclass:$b, regclass:$c),
 898                !strconcat("atom",
 899          !strconcat(SpaceStr,
 900          !strconcat(OpcStr,
 901          !strconcat(TypeStr,
 902          !strconcat(" \t$dst, [$addr], $b, $c;", ""))))),
 903          [(set regclass:$dst,
 904            (IntOp ptrclass:$addr, regclass:$b, regclass:$c))]>,
 905          Requires<[Pred]>;
 906   def imm1 : NVPTXInst<(outs regclass:$dst),
 907     (ins ptrclass:$addr, IMMType:$b, regclass:$c),
 908                !strconcat("atom",
 909          !strconcat(SpaceStr,
 910          !strconcat(OpcStr,
 911          !strconcat(TypeStr,
 912          !strconcat(" \t$dst, [$addr], $b, $c;", ""))))),
 913          [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, regclass:$c))]>,
 914   Requires<[Pred]>;
 915   def imm2 : NVPTXInst<(outs regclass:$dst),
 916     (ins ptrclass:$addr, regclass:$b, IMMType:$c),
 917                !strconcat("atom",
 918          !strconcat(SpaceStr,
 919          !strconcat(OpcStr,
 920          !strconcat(TypeStr,
 921          !strconcat(" \t$dst, [$addr], $b, $c;", ""))))),
 922          [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b, imm:$c))]>,
 923   Requires<[Pred]>;
 924   def imm3 : NVPTXInst<(outs regclass:$dst),
 925     (ins ptrclass:$addr, IMMType:$b, IMMType:$c),
 926                !strconcat("atom",
 927          !strconcat(SpaceStr,
 928          !strconcat(OpcStr,
 929          !strconcat(TypeStr,
 930          !strconcat(" \t$dst, [$addr], $b, $c;", ""))))),
 931          [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, imm:$c))]>,
 932   Requires<[Pred]>;
 933 }
 934 multiclass F_ATOMIC_3<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
 935   string OpcStr, PatFrag IntOp, Operand IMMType, Predicate Pred> {
 936   defm p32 : F_ATOMIC_3_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
 937     IntOp, IMMType, Pred>;
 938   defm p64 : F_ATOMIC_3_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
 939     IntOp, IMMType, Pred>;
 940 }
 941
 942 // atom_add
 943
 944 def atomic_load_add_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 945   (atomic_load_add_32 node:$a, node:$b)>;
 946 def atomic_load_add_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 947   (atomic_load_add_32 node:$a, node:$b)>;
 948 def atomic_load_add_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
 949   (atomic_load_add_32 node:$a, node:$b)>;
 950 def atomic_load_add_64_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 951   (atomic_load_add_64 node:$a, node:$b)>;
 952 def atomic_load_add_64_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 953   (atomic_load_add_64 node:$a, node:$b)>;
 954 def atomic_load_add_64_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
 955   (atomic_load_add_64 node:$a, node:$b)>;
 956 def atomic_load_add_f32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 957   (int_nvvm_atomic_load_add_f32 node:$a, node:$b)>;
 958 def atomic_load_add_f32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 959   (int_nvvm_atomic_load_add_f32 node:$a, node:$b)>;
 960 def atomic_load_add_f32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
 961   (int_nvvm_atomic_load_add_f32 node:$a, node:$b)>;
 962
 963 defm INT_PTX_ATOM_ADD_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32", ".add",
 964   atomic_load_add_32_g, i32imm, imm, hasAtomRedG32>;
 965 defm INT_PTX_ATOM_ADD_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32", ".add",
 966   atomic_load_add_32_s, i32imm, imm, hasAtomRedS32>;
 967 defm INT_PTX_ATOM_ADD_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".add",
 968   atomic_load_add_32_gen, i32imm, imm, hasAtomRedGen32>;
 969 defm INT_PTX_ATOM_ADD_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".u32",
 970   ".add", atomic_load_add_32_gen, i32imm, imm, useAtomRedG32forGen32>;
 971
 972 defm INT_PTX_ATOM_ADD_G_64 : F_ATOMIC_2<Int64Regs, ".global", ".u64", ".add",
 973   atomic_load_add_64_g, i64imm, imm, hasAtomRedG64>;
 974 defm INT_PTX_ATOM_ADD_S_64 : F_ATOMIC_2<Int64Regs, ".shared", ".u64", ".add",
 975   atomic_load_add_64_s, i64imm, imm, hasAtomRedS64>;
 976 defm INT_PTX_ATOM_ADD_GEN_64 : F_ATOMIC_2<Int64Regs, "", ".u64", ".add",
 977   atomic_load_add_64_gen, i64imm, imm, hasAtomRedGen64>;
 978 defm INT_PTX_ATOM_ADD_GEN_64_USE_G : F_ATOMIC_2<Int64Regs, ".global", ".u64",
 979   ".add", atomic_load_add_64_gen, i64imm, imm, useAtomRedG64forGen64>;
 980
 981 defm INT_PTX_ATOM_ADD_G_F32 : F_ATOMIC_2<Float32Regs, ".global", ".f32", ".add",
 982   atomic_load_add_f32_g, f32imm, fpimm, hasAtomAddF32>;
 983 defm INT_PTX_ATOM_ADD_S_F32 : F_ATOMIC_2<Float32Regs, ".shared", ".f32", ".add",
 984   atomic_load_add_f32_s, f32imm, fpimm, hasAtomAddF32>;
 985 defm INT_PTX_ATOM_ADD_GEN_F32 : F_ATOMIC_2<Float32Regs, "", ".f32", ".add",
 986   atomic_load_add_f32_gen, f32imm, fpimm, hasAtomAddF32>;
 987
 988 // atom_sub
 989
 990 def atomic_load_sub_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 991   (atomic_load_sub_32 node:$a, node:$b)>;
 992 def atomic_load_sub_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 993   (atomic_load_sub_32 node:$a, node:$b)>;
 994 def atomic_load_sub_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
 995   (atomic_load_sub_32 node:$a, node:$b)>;
 996 def atomic_load_sub_64_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 997   (atomic_load_sub_64 node:$a, node:$b)>;
 998 def atomic_load_sub_64_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 999   (atomic_load_sub_64 node:$a, node:$b)>;
1000 def atomic_load_sub_64_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1001   (atomic_load_sub_64 node:$a, node:$b)>;
1002
1003 defm INT_PTX_ATOM_SUB_G_32 : F_ATOMIC_2_NEG<Int32Regs, ".global", "32", ".add",
1004   atomic_load_sub_32_g, i32imm, hasAtomRedG32>;
1005 defm INT_PTX_ATOM_SUB_G_64 : F_ATOMIC_2_NEG<Int64Regs, ".global", "64", ".add",
1006   atomic_load_sub_64_g, i64imm, hasAtomRedG64>;
1007 defm INT_PTX_ATOM_SUB_GEN_32 : F_ATOMIC_2_NEG<Int32Regs, "", "32", ".add",
1008   atomic_load_sub_32_gen, i32imm, hasAtomRedGen32>;
1009 defm INT_PTX_ATOM_SUB_GEN_32_USE_G : F_ATOMIC_2_NEG<Int32Regs, ".global", "32",
1010   ".add", atomic_load_sub_32_gen, i32imm, useAtomRedG32forGen32>;
1011 defm INT_PTX_ATOM_SUB_S_32 : F_ATOMIC_2_NEG<Int32Regs, ".shared", "32", ".add",
1012   atomic_load_sub_32_s, i32imm, hasAtomRedS32>;
1013 defm INT_PTX_ATOM_SUB_S_64 : F_ATOMIC_2_NEG<Int64Regs, ".shared", "64", ".add",
1014   atomic_load_sub_64_s, i64imm, hasAtomRedS64>;
1015 defm INT_PTX_ATOM_SUB_GEN_64 : F_ATOMIC_2_NEG<Int64Regs, "", "64", ".add",
1016   atomic_load_sub_64_gen, i64imm, hasAtomRedGen64>;
1017 defm INT_PTX_ATOM_SUB_GEN_64_USE_G : F_ATOMIC_2_NEG<Int64Regs, ".global", "64",
1018   ".add", atomic_load_sub_64_gen, i64imm, useAtomRedG64forGen64>;
1019
1020 // atom_swap
1021
1022 def atomic_swap_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1023   (atomic_swap_32 node:$a, node:$b)>;
1024 def atomic_swap_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1025   (atomic_swap_32 node:$a, node:$b)>;
1026 def atomic_swap_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1027   (atomic_swap_32 node:$a, node:$b)>;
1028 def atomic_swap_64_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1029   (atomic_swap_64 node:$a, node:$b)>;
1030 def atomic_swap_64_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1031   (atomic_swap_64 node:$a, node:$b)>;
1032 def atomic_swap_64_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1033   (atomic_swap_64 node:$a, node:$b)>;
1034
1035 defm INT_PTX_ATOM_SWAP_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".b32", ".exch",
1036   atomic_swap_32_g, i32imm, imm, hasAtomRedG32>;
1037 defm INT_PTX_ATOM_SWAP_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".b32", ".exch",
1038   atomic_swap_32_s, i32imm, imm, hasAtomRedS32>;
1039 defm INT_PTX_ATOM_SWAP_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".b32", ".exch",
1040   atomic_swap_32_gen, i32imm, imm, hasAtomRedGen32>;
1041 defm INT_PTX_ATOM_SWAP_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".b32",
1042   ".exch", atomic_swap_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1043 defm INT_PTX_ATOM_SWAP_G_64 : F_ATOMIC_2<Int64Regs, ".global", ".b64", ".exch",
1044   atomic_swap_64_g, i64imm, imm, hasAtomRedG64>;
1045 defm INT_PTX_ATOM_SWAP_S_64 : F_ATOMIC_2<Int64Regs, ".shared", ".b64", ".exch",
1046   atomic_swap_64_s, i64imm, imm, hasAtomRedS64>;
1047 defm INT_PTX_ATOM_SWAP_GEN_64 : F_ATOMIC_2<Int64Regs, "", ".b64", ".exch",
1048   atomic_swap_64_gen, i64imm, imm, hasAtomRedGen64>;
1049 defm INT_PTX_ATOM_SWAP_GEN_64_USE_G : F_ATOMIC_2<Int64Regs, ".global", ".b64",
1050   ".exch", atomic_swap_64_gen, i64imm, imm, useAtomRedG64forGen64>;
1051
1052 // atom_max
1053
1054 def atomic_load_max_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b)
1055   , (atomic_load_max_32 node:$a, node:$b)>;
1056 def atomic_load_max_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1057   (atomic_load_max_32 node:$a, node:$b)>;
1058 def atomic_load_max_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1059   (atomic_load_max_32 node:$a, node:$b)>;
1060 def atomic_load_umax_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1061   (atomic_load_umax_32 node:$a, node:$b)>;
1062 def atomic_load_umax_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1063   (atomic_load_umax_32 node:$a, node:$b)>;
1064 def atomic_load_umax_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1065   (atomic_load_umax_32 node:$a, node:$b)>;
1066
1067 defm INT_PTX_ATOM_LOAD_MAX_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".s32",
1068   ".max", atomic_load_max_32_g, i32imm, imm, hasAtomRedG32>;
1069 defm INT_PTX_ATOM_LOAD_MAX_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".s32",
1070   ".max", atomic_load_max_32_s, i32imm, imm, hasAtomRedS32>;
1071 defm INT_PTX_ATOM_LOAD_MAX_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".s32", ".max",
1072   atomic_load_max_32_gen, i32imm, imm, hasAtomRedGen32>;
1073 defm INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global",
1074   ".s32", ".max", atomic_load_max_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1075 defm INT_PTX_ATOM_LOAD_UMAX_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32",
1076   ".max", atomic_load_umax_32_g, i32imm, imm, hasAtomRedG32>;
1077 defm INT_PTX_ATOM_LOAD_UMAX_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32",
1078   ".max", atomic_load_umax_32_s, i32imm, imm, hasAtomRedS32>;
1079 defm INT_PTX_ATOM_LOAD_UMAX_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".max",
1080   atomic_load_umax_32_gen, i32imm, imm, hasAtomRedGen32>;
1081 defm INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global",
1082   ".u32", ".max", atomic_load_umax_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1083
1084 // atom_min
1085
1086 def atomic_load_min_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1087   (atomic_load_min_32 node:$a, node:$b)>;
1088 def atomic_load_min_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1089   (atomic_load_min_32 node:$a, node:$b)>;
1090 def atomic_load_min_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1091   (atomic_load_min_32 node:$a, node:$b)>;
1092 def atomic_load_umin_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1093   (atomic_load_umin_32 node:$a, node:$b)>;
1094 def atomic_load_umin_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1095   (atomic_load_umin_32 node:$a, node:$b)>;
1096 def atomic_load_umin_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1097   (atomic_load_umin_32 node:$a, node:$b)>;
1098
1099 defm INT_PTX_ATOM_LOAD_MIN_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".s32",
1100   ".min", atomic_load_min_32_g, i32imm, imm, hasAtomRedG32>;
1101 defm INT_PTX_ATOM_LOAD_MIN_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".s32",
1102   ".min", atomic_load_min_32_s, i32imm, imm, hasAtomRedS32>;
1103 defm INT_PTX_ATOM_LOAD_MIN_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".s32", ".min",
1104   atomic_load_min_32_gen, i32imm, imm, hasAtomRedGen32>;
1105 defm INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global",
1106   ".s32", ".min", atomic_load_min_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1107 defm INT_PTX_ATOM_LOAD_UMIN_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32",
1108   ".min", atomic_load_umin_32_g, i32imm, imm, hasAtomRedG32>;
1109 defm INT_PTX_ATOM_LOAD_UMIN_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32",
1110   ".min", atomic_load_umin_32_s, i32imm, imm, hasAtomRedS32>;
1111 defm INT_PTX_ATOM_LOAD_UMIN_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".min",
1112   atomic_load_umin_32_gen, i32imm, imm, hasAtomRedGen32>;
1113 defm INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global",
1114   ".u32", ".min", atomic_load_umin_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1115
1116 // atom_inc  atom_dec
1117
1118 def atomic_load_inc_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1119   (int_nvvm_atomic_load_inc_32 node:$a, node:$b)>;
1120 def atomic_load_inc_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1121   (int_nvvm_atomic_load_inc_32 node:$a, node:$b)>;
1122 def atomic_load_inc_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1123   (int_nvvm_atomic_load_inc_32 node:$a, node:$b)>;
1124 def atomic_load_dec_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1125   (int_nvvm_atomic_load_dec_32 node:$a, node:$b)>;
1126 def atomic_load_dec_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1127   (int_nvvm_atomic_load_dec_32 node:$a, node:$b)>;
1128 def atomic_load_dec_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1129   (int_nvvm_atomic_load_dec_32 node:$a, node:$b)>;
1130
1131 defm INT_PTX_ATOM_INC_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32", ".inc",
1132   atomic_load_inc_32_g, i32imm, imm, hasAtomRedG32>;
1133 defm INT_PTX_ATOM_INC_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32", ".inc",
1134   atomic_load_inc_32_s, i32imm, imm, hasAtomRedS32>;
1135 defm INT_PTX_ATOM_INC_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".inc",
1136   atomic_load_inc_32_gen, i32imm, imm, hasAtomRedGen32>;
1137 defm INT_PTX_ATOM_INC_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".u32",
1138   ".inc", atomic_load_inc_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1139 defm INT_PTX_ATOM_DEC_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32", ".dec",
1140   atomic_load_dec_32_g, i32imm, imm, hasAtomRedG32>;
1141 defm INT_PTX_ATOM_DEC_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32", ".dec",
1142   atomic_load_dec_32_s, i32imm, imm, hasAtomRedS32>;
1143 defm INT_PTX_ATOM_DEC_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".dec",
1144   atomic_load_dec_32_gen, i32imm, imm, hasAtomRedGen32>;
1145 defm INT_PTX_ATOM_DEC_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".u32",
1146   ".dec", atomic_load_dec_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1147
1148 // atom_and
1149
1150 def atomic_load_and_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1151   (atomic_load_and_32 node:$a, node:$b)>;
1152 def atomic_load_and_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1153   (atomic_load_and_32 node:$a, node:$b)>;
1154 def atomic_load_and_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1155   (atomic_load_and_32 node:$a, node:$b)>;
1156
1157 defm INT_PTX_ATOM_AND_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".b32", ".and",
1158   atomic_load_and_32_g, i32imm, imm, hasAtomRedG32>;
1159 defm INT_PTX_ATOM_AND_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".b32", ".and",
1160   atomic_load_and_32_s, i32imm, imm, hasAtomRedS32>;
1161 defm INT_PTX_ATOM_AND_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".b32", ".and",
1162   atomic_load_and_32_gen, i32imm, imm, hasAtomRedGen32>;
1163 defm INT_PTX_ATOM_AND_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".b32",
1164   ".and", atomic_load_and_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1165
1166 // atom_or
1167
1168 def atomic_load_or_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1169   (atomic_load_or_32 node:$a, node:$b)>;
1170 def atomic_load_or_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1171   (atomic_load_or_32 node:$a, node:$b)>;
1172 def atomic_load_or_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1173   (atomic_load_or_32 node:$a, node:$b)>;
1174
1175 defm INT_PTX_ATOM_OR_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".b32", ".or",
1176   atomic_load_or_32_g, i32imm, imm, hasAtomRedG32>;
1177 defm INT_PTX_ATOM_OR_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".b32", ".or",
1178   atomic_load_or_32_gen, i32imm, imm, hasAtomRedGen32>;
1179 defm INT_PTX_ATOM_OR_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".b32",
1180   ".or", atomic_load_or_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1181 defm INT_PTX_ATOM_OR_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".b32", ".or",
1182   atomic_load_or_32_s, i32imm, imm, hasAtomRedS32>;
1183
1184 // atom_xor
1185
1186 def atomic_load_xor_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1187   (atomic_load_xor_32 node:$a, node:$b)>;
1188 def atomic_load_xor_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1189   (atomic_load_xor_32 node:$a, node:$b)>;
1190 def atomic_load_xor_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1191   (atomic_load_xor_32 node:$a, node:$b)>;
1192
1193 defm INT_PTX_ATOM_XOR_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".b32", ".xor",
1194   atomic_load_xor_32_g, i32imm, imm, hasAtomRedG32>;
1195 defm INT_PTX_ATOM_XOR_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".b32", ".xor",
1196   atomic_load_xor_32_s, i32imm, imm, hasAtomRedS32>;
1197 defm INT_PTX_ATOM_XOR_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".b32", ".xor",
1198   atomic_load_xor_32_gen, i32imm, imm, hasAtomRedGen32>;
1199 defm INT_PTX_ATOM_XOR_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".b32",
1200   ".xor", atomic_load_xor_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1201
1202 // atom_cas
1203
1204 def atomic_cmp_swap_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b, node:$c),
1205   (atomic_cmp_swap_32 node:$a, node:$b, node:$c)>;
1206 def atomic_cmp_swap_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b, node:$c),
1207   (atomic_cmp_swap_32 node:$a, node:$b, node:$c)>;
1208 def atomic_cmp_swap_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b, node:$c),
1209   (atomic_cmp_swap_32 node:$a, node:$b, node:$c)>;
1210 def atomic_cmp_swap_64_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b, node:$c),
1211   (atomic_cmp_swap_64 node:$a, node:$b, node:$c)>;
1212 def atomic_cmp_swap_64_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b, node:$c),
1213   (atomic_cmp_swap_64 node:$a, node:$b, node:$c)>;
1214 def atomic_cmp_swap_64_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b, node:$c),
1215   (atomic_cmp_swap_64 node:$a, node:$b, node:$c)>;
1216
1217 defm INT_PTX_ATOM_CAS_G_32 : F_ATOMIC_3<Int32Regs, ".global", ".b32", ".cas",
1218   atomic_cmp_swap_32_g, i32imm, hasAtomRedG32>;
1219 defm INT_PTX_ATOM_CAS_S_32 : F_ATOMIC_3<Int32Regs, ".shared", ".b32", ".cas",
1220   atomic_cmp_swap_32_s, i32imm, hasAtomRedS32>;
1221 defm INT_PTX_ATOM_CAS_GEN_32 : F_ATOMIC_3<Int32Regs, "", ".b32", ".cas",
1222   atomic_cmp_swap_32_gen, i32imm, hasAtomRedGen32>;
1223 defm INT_PTX_ATOM_CAS_GEN_32_USE_G : F_ATOMIC_3<Int32Regs, ".global", ".b32",
1224   ".cas", atomic_cmp_swap_32_gen, i32imm, useAtomRedG32forGen32>;
1225 defm INT_PTX_ATOM_CAS_G_64 : F_ATOMIC_3<Int64Regs, ".global", ".b64", ".cas",
1226   atomic_cmp_swap_64_g, i64imm, hasAtomRedG64>;
1227 defm INT_PTX_ATOM_CAS_S_64 : F_ATOMIC_3<Int64Regs, ".shared", ".b64", ".cas",
1228   atomic_cmp_swap_64_s, i64imm, hasAtomRedS64>;
1229 defm INT_PTX_ATOM_CAS_GEN_64 : F_ATOMIC_3<Int64Regs, "", ".b64", ".cas",
1230   atomic_cmp_swap_64_gen, i64imm, hasAtomRedGen64>;
1231 defm INT_PTX_ATOM_CAS_GEN_64_USE_G : F_ATOMIC_3<Int64Regs, ".global", ".b64",
1232   ".cas", atomic_cmp_swap_64_gen, i64imm, useAtomRedG64forGen64>;
1233
1234
1235 //-----------------------------------
1236 // Read Special Registers
1237 //-----------------------------------
1238 class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> :
1239       NVPTXInst<(outs regclassOut:$dst), (ins),
1240                OpStr,
1241          [(set regclassOut:$dst, (IntOp))]>;
1242
1243 def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32Regs,
1244   int_nvvm_read_ptx_sreg_tid_x>;
1245 def INT_PTX_SREG_TID_Y : F_SREG<"mov.u32 \t$dst, %tid.y;", Int32Regs,
1246   int_nvvm_read_ptx_sreg_tid_y>;
1247 def INT_PTX_SREG_TID_Z : F_SREG<"mov.u32 \t$dst, %tid.z;", Int32Regs,
1248   int_nvvm_read_ptx_sreg_tid_z>;
1249
1250 def INT_PTX_SREG_NTID_X : F_SREG<"mov.u32 \t$dst, %ntid.x;", Int32Regs,
1251   int_nvvm_read_ptx_sreg_ntid_x>;
1252 def INT_PTX_SREG_NTID_Y : F_SREG<"mov.u32 \t$dst, %ntid.y;", Int32Regs,
1253   int_nvvm_read_ptx_sreg_ntid_y>;
1254 def INT_PTX_SREG_NTID_Z : F_SREG<"mov.u32 \t$dst, %ntid.z;", Int32Regs,
1255   int_nvvm_read_ptx_sreg_ntid_z>;
1256
1257 def INT_PTX_SREG_CTAID_X : F_SREG<"mov.u32 \t$dst, %ctaid.x;", Int32Regs,
1258   int_nvvm_read_ptx_sreg_ctaid_x>;
1259 def INT_PTX_SREG_CTAID_Y : F_SREG<"mov.u32 \t$dst, %ctaid.y;", Int32Regs,
1260   int_nvvm_read_ptx_sreg_ctaid_y>;
1261 def INT_PTX_SREG_CTAID_Z : F_SREG<"mov.u32 \t$dst, %ctaid.z;", Int32Regs,
1262   int_nvvm_read_ptx_sreg_ctaid_z>;
1263
1264 def INT_PTX_SREG_NCTAID_X : F_SREG<"mov.u32 \t$dst, %nctaid.x;", Int32Regs,
1265   int_nvvm_read_ptx_sreg_nctaid_x>;
1266 def INT_PTX_SREG_NCTAID_Y : F_SREG<"mov.u32 \t$dst, %nctaid.y;", Int32Regs,
1267   int_nvvm_read_ptx_sreg_nctaid_y>;
1268 def INT_PTX_SREG_NCTAID_Z : F_SREG<"mov.u32 \t$dst, %nctaid.z;", Int32Regs,
1269   int_nvvm_read_ptx_sreg_nctaid_z>;
1270
1271 def INT_PTX_SREG_WARPSIZE : F_SREG<"mov.u32 \t$dst, WARP_SZ;", Int32Regs,
1272   int_nvvm_read_ptx_sreg_warpsize>;
1273
1274
1275 //-----------------------------------
1276 // Support for ldu on sm_20 or later
1277 //-----------------------------------
1278
1279 def ldu_i8 : PatFrag<(ops node:$ptr), (int_nvvm_ldu_global_i node:$ptr), [{
1280   MemIntrinsicSDNode *M = cast<MemIntrinsicSDNode>(N);
1281   return M->getMemoryVT() == MVT::i8;
1282 }]>;
1283
1284 // Scalar
1285 // @TODO: Revisit this, Changed imemAny to imem
1286 multiclass LDU_G<string TyStr, NVPTXRegClass regclass, Intrinsic IntOp> {
1287   def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1288                !strconcat("ldu.global.", TyStr),
1289          [(set regclass:$result, (IntOp Int32Regs:$src))]>, Requires<[hasLDU]>;
1290   def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1291                !strconcat("ldu.global.", TyStr),
1292          [(set regclass:$result, (IntOp Int64Regs:$src))]>, Requires<[hasLDU]>;
1293  def avar:  NVPTXInst<(outs regclass:$result), (ins imem:$src),
1294                !strconcat("ldu.global.", TyStr),
1295                 [(set regclass:$result, (IntOp (Wrapper tglobaladdr:$src)))]>,
1296                 Requires<[hasLDU]>;
1297  def ari :  NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1298                !strconcat("ldu.global.", TyStr),
1299          [(set regclass:$result, (IntOp ADDRri:$src))]>, Requires<[hasLDU]>;
1300  def ari64 :  NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1301                !strconcat("ldu.global.", TyStr),
1302          [(set regclass:$result, (IntOp ADDRri64:$src))]>, Requires<[hasLDU]>;
1303 }
1304
1305 multiclass LDU_G_NOINTRIN<string TyStr, NVPTXRegClass regclass, PatFrag IntOp> {
1306   def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1307                !strconcat("ldu.global.", TyStr),
1308          [(set regclass:$result, (IntOp Int32Regs:$src))]>, Requires<[hasLDU]>;
1309   def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1310                !strconcat("ldu.global.", TyStr),
1311          [(set regclass:$result, (IntOp Int64Regs:$src))]>, Requires<[hasLDU]>;
1312  def avar:  NVPTXInst<(outs regclass:$result), (ins imem:$src),
1313                !strconcat("ldu.global.", TyStr),
1314          [(set regclass:$result, (IntOp (Wrapper tglobaladdr:$src)))]>,
1315          Requires<[hasLDU]>;
1316  def ari :  NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1317                !strconcat("ldu.global.", TyStr),
1318          [(set regclass:$result, (IntOp ADDRri:$src))]>, Requires<[hasLDU]>;
1319  def ari64 :  NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1320                !strconcat("ldu.global.", TyStr),
1321          [(set regclass:$result, (IntOp ADDRri64:$src))]>, Requires<[hasLDU]>;
1322 }
1323
1324 defm INT_PTX_LDU_GLOBAL_i8  : LDU_G_NOINTRIN<"u8 \t$result, [$src];", Int16Regs,
1325                                              ldu_i8>;
1326 defm INT_PTX_LDU_GLOBAL_i16 : LDU_G<"u16 \t$result, [$src];", Int16Regs,
1327 int_nvvm_ldu_global_i>;
1328 defm INT_PTX_LDU_GLOBAL_i32 : LDU_G<"u32 \t$result, [$src];", Int32Regs,
1329 int_nvvm_ldu_global_i>;
1330 defm INT_PTX_LDU_GLOBAL_i64 : LDU_G<"u64 \t$result, [$src];", Int64Regs,
1331 int_nvvm_ldu_global_i>;
1332 defm INT_PTX_LDU_GLOBAL_f32 : LDU_G<"f32 \t$result, [$src];", Float32Regs,
1333 int_nvvm_ldu_global_f>;
1334 defm INT_PTX_LDU_GLOBAL_f64 : LDU_G<"f64 \t$result, [$src];", Float64Regs,
1335 int_nvvm_ldu_global_f>;
1336 defm INT_PTX_LDU_GLOBAL_p32 : LDU_G<"u32 \t$result, [$src];", Int32Regs,
1337 int_nvvm_ldu_global_p>;
1338 defm INT_PTX_LDU_GLOBAL_p64 : LDU_G<"u64 \t$result, [$src];", Int64Regs,
1339 int_nvvm_ldu_global_p>;
1340
1341 // vector
1342
1343 // Elementized vector ldu
1344 multiclass VLDU_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1345  def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1346                      (ins Int32Regs:$src),
1347                      !strconcat("ldu.global.", TyStr), []>;
1348  def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1349                      (ins Int64Regs:$src),
1350                      !strconcat("ldu.global.", TyStr), []>;
1351  def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1352                      (ins MEMri:$src),
1353                      !strconcat("ldu.global.", TyStr), []>;
1354  def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1355                      (ins MEMri64:$src),
1356                      !strconcat("ldu.global.", TyStr), []>;
1357  def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1358                      (ins imemAny:$src),
1359                      !strconcat("ldu.global.", TyStr), []>;
1360 }
1361
1362 multiclass VLDU_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1363  def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1364                             regclass:$dst4), (ins Int32Regs:$src),
1365                !strconcat("ldu.global.", TyStr), []>;
1366  def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1367                             regclass:$dst4), (ins Int64Regs:$src),
1368                !strconcat("ldu.global.", TyStr), []>;
1369  def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1370                             regclass:$dst4), (ins MEMri:$src),
1371                !strconcat("ldu.global.", TyStr), []>;
1372  def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1373                             regclass:$dst4), (ins MEMri64:$src),
1374                !strconcat("ldu.global.", TyStr), []>;
1375  def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1376                             regclass:$dst4), (ins imemAny:$src),
1377                !strconcat("ldu.global.", TyStr), []>;
1378 }
1379
1380 defm INT_PTX_LDU_G_v2i8_ELE
1381   : VLDU_G_ELE_V2<"v2.u8 \t{{$dst1, $dst2}}, [$src];",  Int16Regs>;
1382 defm INT_PTX_LDU_G_v2i16_ELE
1383   : VLDU_G_ELE_V2<"v2.u16 \t{{$dst1, $dst2}}, [$src];", Int16Regs>;
1384 defm INT_PTX_LDU_G_v2i32_ELE
1385   : VLDU_G_ELE_V2<"v2.u32 \t{{$dst1, $dst2}}, [$src];", Int32Regs>;
1386 defm INT_PTX_LDU_G_v2f32_ELE
1387   : VLDU_G_ELE_V2<"v2.f32 \t{{$dst1, $dst2}}, [$src];", Float32Regs>;
1388 defm INT_PTX_LDU_G_v2i64_ELE
1389   : VLDU_G_ELE_V2<"v2.u64 \t{{$dst1, $dst2}}, [$src];", Int64Regs>;
1390 defm INT_PTX_LDU_G_v2f64_ELE
1391   : VLDU_G_ELE_V2<"v2.f64 \t{{$dst1, $dst2}}, [$src];", Float64Regs>;
1392 defm INT_PTX_LDU_G_v4i8_ELE
1393   : VLDU_G_ELE_V4<"v4.u8 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
1394 defm INT_PTX_LDU_G_v4i16_ELE
1395   : VLDU_G_ELE_V4<"v4.u16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
1396     Int16Regs>;
1397 defm INT_PTX_LDU_G_v4i32_ELE
1398   : VLDU_G_ELE_V4<"v4.u32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
1399     Int32Regs>;
1400 defm INT_PTX_LDU_G_v4f32_ELE
1401   : VLDU_G_ELE_V4<"v4.f32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
1402     Float32Regs>;
1403
1404
1405 //-----------------------------------
1406 // Support for ldg on sm_35 or later
1407 //-----------------------------------
1408
1409 def ldg_i8 : PatFrag<(ops node:$ptr), (int_nvvm_ldg_global_i node:$ptr), [{
1410   MemIntrinsicSDNode *M = cast<MemIntrinsicSDNode>(N);
1411   return M->getMemoryVT() == MVT::i8;
1412 }]>;
1413
1414 multiclass LDG_G<string TyStr, NVPTXRegClass regclass, Intrinsic IntOp> {
1415   def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1416                !strconcat("ld.global.nc.", TyStr),
1417          [(set regclass:$result, (IntOp Int32Regs:$src))]>, Requires<[hasLDG]>;
1418   def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1419                !strconcat("ld.global.nc.", TyStr),
1420          [(set regclass:$result, (IntOp Int64Regs:$src))]>, Requires<[hasLDG]>;
1421  def avar:  NVPTXInst<(outs regclass:$result), (ins imem:$src),
1422                !strconcat("ld.global.nc.", TyStr),
1423          [(set regclass:$result, (IntOp (Wrapper tglobaladdr:$src)))]>,
1424          Requires<[hasLDG]>;
1425  def ari :  NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1426                !strconcat("ld.global.nc.", TyStr),
1427          [(set regclass:$result, (IntOp ADDRri:$src))]>, Requires<[hasLDG]>;
1428  def ari64 :  NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1429                !strconcat("ld.global.nc.", TyStr),
1430          [(set regclass:$result, (IntOp ADDRri64:$src))]>, Requires<[hasLDG]>;
1431 }
1432
1433 multiclass LDG_G_NOINTRIN<string TyStr, NVPTXRegClass regclass, PatFrag IntOp> {
1434   def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1435                !strconcat("ld.global.nc.", TyStr),
1436          [(set regclass:$result, (IntOp Int32Regs:$src))]>, Requires<[hasLDG]>;
1437   def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1438                !strconcat("ld.global.nc.", TyStr),
1439          [(set regclass:$result, (IntOp Int64Regs:$src))]>, Requires<[hasLDG]>;
1440  def avar:  NVPTXInst<(outs regclass:$result), (ins imem:$src),
1441                !strconcat("ld.global.nc.", TyStr),
1442          [(set regclass:$result, (IntOp (Wrapper tglobaladdr:$src)))]>,
1443         Requires<[hasLDG]>;
1444  def ari :  NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1445                !strconcat("ld.global.nc.", TyStr),
1446          [(set regclass:$result, (IntOp ADDRri:$src))]>, Requires<[hasLDG]>;
1447  def ari64 :  NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1448                !strconcat("ld.global.nc.", TyStr),
1449          [(set regclass:$result, (IntOp ADDRri64:$src))]>, Requires<[hasLDG]>;
1450 }
1451
1452 defm INT_PTX_LDG_GLOBAL_i8
1453   : LDG_G_NOINTRIN<"u8 \t$result, [$src];",  Int16Regs, ldg_i8>;
1454 defm INT_PTX_LDG_GLOBAL_i16
1455   : LDG_G<"u16 \t$result, [$src];", Int16Regs,   int_nvvm_ldg_global_i>;
1456 defm INT_PTX_LDG_GLOBAL_i32
1457   : LDG_G<"u32 \t$result, [$src];", Int32Regs,   int_nvvm_ldg_global_i>;
1458 defm INT_PTX_LDG_GLOBAL_i64
1459   : LDG_G<"u64 \t$result, [$src];", Int64Regs,   int_nvvm_ldg_global_i>;
1460 defm INT_PTX_LDG_GLOBAL_f32
1461   : LDG_G<"f32 \t$result, [$src];", Float32Regs, int_nvvm_ldg_global_f>;
1462 defm INT_PTX_LDG_GLOBAL_f64
1463   : LDG_G<"f64 \t$result, [$src];", Float64Regs, int_nvvm_ldg_global_f>;
1464 defm INT_PTX_LDG_GLOBAL_p32
1465   : LDG_G<"u32 \t$result, [$src];", Int32Regs,   int_nvvm_ldg_global_p>;
1466 defm INT_PTX_LDG_GLOBAL_p64
1467   : LDG_G<"u64 \t$result, [$src];", Int64Regs,   int_nvvm_ldg_global_p>;
1468
1469 // vector
1470
1471 // Elementized vector ldg
1472 multiclass VLDG_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1473  def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1474                      (ins Int32Regs:$src),
1475                      !strconcat("ld.global.nc.", TyStr), []>;
1476  def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1477                      (ins Int64Regs:$src),
1478                      !strconcat("ld.global.nc.", TyStr), []>;
1479  def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1480                      (ins MEMri:$src),
1481                      !strconcat("ld.global.nc.", TyStr), []>;
1482  def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1483                      (ins MEMri64:$src),
1484                      !strconcat("ld.global.nc.", TyStr), []>;
1485  def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1486                      (ins imemAny:$src),
1487                      !strconcat("ld.global.nc.", TyStr), []>;
1488 }
1489
1490 multiclass VLDG_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1491   def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1492                               regclass:$dst4), (ins Int32Regs:$src),
1493                !strconcat("ld.global.nc.", TyStr), []>;
1494   def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1495                                regclass:$dst4), (ins Int64Regs:$src),
1496                !strconcat("ld.global.nc.", TyStr), []>;
1497   def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1498                               regclass:$dst4), (ins MEMri:$src),
1499                !strconcat("ld.global.nc.", TyStr), []>;
1500   def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1501                               regclass:$dst4), (ins MEMri64:$src),
1502                !strconcat("ld.global.nc.", TyStr), []>;
1503   def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1504                              regclass:$dst4), (ins imemAny:$src),
1505                !strconcat("ld.global.nc.", TyStr), []>;
1506 }
1507
1508 // FIXME: 8-bit LDG should be fixed once LDG/LDU nodes are made into proper loads.
1509 defm INT_PTX_LDG_G_v2i8_ELE
1510   : VLDG_G_ELE_V2<"v2.u8 \t{{$dst1, $dst2}}, [$src];",  Int16Regs>;
1511 defm INT_PTX_LDG_G_v2i16_ELE
1512   : VLDG_G_ELE_V2<"v2.u16 \t{{$dst1, $dst2}}, [$src];", Int16Regs>;
1513 defm INT_PTX_LDG_G_v2i32_ELE
1514   : VLDG_G_ELE_V2<"v2.u32 \t{{$dst1, $dst2}}, [$src];", Int32Regs>;
1515 defm INT_PTX_LDG_G_v2f32_ELE
1516   : VLDG_G_ELE_V2<"v2.f32 \t{{$dst1, $dst2}}, [$src];", Float32Regs>;
1517 defm INT_PTX_LDG_G_v2i64_ELE
1518   : VLDG_G_ELE_V2<"v2.u64 \t{{$dst1, $dst2}}, [$src];", Int64Regs>;
1519 defm INT_PTX_LDG_G_v2f64_ELE
1520   : VLDG_G_ELE_V2<"v2.f64 \t{{$dst1, $dst2}}, [$src];", Float64Regs>;
1521 defm INT_PTX_LDG_G_v4i8_ELE
1522   : VLDG_G_ELE_V4<"v4.u8 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
1523 defm INT_PTX_LDG_G_v4i16_ELE
1524   : VLDG_G_ELE_V4<"v4.u16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
1525 defm INT_PTX_LDG_G_v4i32_ELE
1526   : VLDG_G_ELE_V4<"v4.u32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int32Regs>;
1527 defm INT_PTX_LDG_G_v4f32_ELE
1528   : VLDG_G_ELE_V4<"v4.f32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Float32Regs>;
1529
1530
1531 multiclass NG_TO_G<string Str, Intrinsic Intrin> {
1532    def _yes : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
1533           !strconcat("cvta.", !strconcat(Str, ".u32 \t$result, $src;")),
1534       [(set Int32Regs:$result, (Intrin Int32Regs:$src))]>,
1535    Requires<[hasGenericLdSt]>;
1536    def _yes_64 : NVPTXInst<(outs Int64Regs:$result), (ins Int64Regs:$src),
1537           !strconcat("cvta.", !strconcat(Str, ".u64 \t$result, $src;")),
1538       [(set Int64Regs:$result, (Intrin Int64Regs:$src))]>,
1539    Requires<[hasGenericLdSt]>;
1540
1541 // @TODO: Are these actually needed?  I believe global addresses will be copied
1542 // to register values anyway.
1543    /*def __addr_yes : NVPTXInst<(outs Int32Regs:$result), (ins imemAny:$src),
1544           !strconcat("cvta.", !strconcat(Str, ".u32 \t$result, $src;")),
1545       [(set Int32Regs:$result, (Intrin (Wrapper tglobaladdr:$src)))]>,
1546       Requires<[hasGenericLdSt]>;
1547    def __addr_yes_64 : NVPTXInst<(outs Int64Regs:$result), (ins imemAny:$src),
1548           !strconcat("cvta.", !strconcat(Str, ".u64 \t$result, $src;")),
1549       [(set Int64Regs:$result, (Intrin (Wrapper tglobaladdr:$src)))]>,
1550       Requires<[hasGenericLdSt]>;*/
1551
1552    def _no : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
1553           "mov.u32 \t$result, $src;",
1554       [(set Int32Regs:$result, (Intrin Int32Regs:$src))]>;
1555    def _no_64 : NVPTXInst<(outs Int64Regs:$result), (ins Int64Regs:$src),
1556           "mov.u64 \t$result, $src;",
1557       [(set Int64Regs:$result, (Intrin Int64Regs:$src))]>;
1558
1559 // @TODO: Are these actually needed?  I believe global addresses will be copied
1560 // to register values anyway.
1561    /*def _addr_no : NVPTXInst<(outs Int32Regs:$result), (ins imem:$src),
1562           "mov.u32 \t$result, $src;",
1563       [(set Int32Regs:$result, (Intrin (Wrapper tglobaladdr:$src)))]>;
1564    def _addr_no_64 : NVPTXInst<(outs Int64Regs:$result), (ins imem:$src),
1565           "mov.u64 \t$result, $src;",
1566       [(set Int64Regs:$result, (Intrin (Wrapper tglobaladdr:$src)))]>;*/
1567 }
1568
1569 multiclass G_TO_NG<string Str, Intrinsic Intrin> {
1570    def _yes : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
1571           !strconcat("cvta.to.", !strconcat(Str, ".u32 \t$result, $src;")),
1572       [(set Int32Regs:$result, (Intrin Int32Regs:$src))]>,
1573    Requires<[hasGenericLdSt]>;
1574    def _yes_64 : NVPTXInst<(outs Int64Regs:$result), (ins Int64Regs:$src),
1575           !strconcat("cvta.to.", !strconcat(Str, ".u64 \t$result, $src;")),
1576       [(set Int64Regs:$result, (Intrin Int64Regs:$src))]>,
1577    Requires<[hasGenericLdSt]>;
1578    def _no : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
1579           "mov.u32 \t$result, $src;",
1580       [(set Int32Regs:$result, (Intrin Int32Regs:$src))]>;
1581    def _no_64 : NVPTXInst<(outs Int64Regs:$result), (ins Int64Regs:$src),
1582           "mov.u64 \t$result, $src;",
1583       [(set Int64Regs:$result, (Intrin Int64Regs:$src))]>;
1584 }
1585
1586 defm cvta_local  : NG_TO_G<"local", int_nvvm_ptr_local_to_gen>;
1587 defm cvta_shared : NG_TO_G<"shared", int_nvvm_ptr_shared_to_gen>;
1588 defm cvta_global : NG_TO_G<"global", int_nvvm_ptr_global_to_gen>;
1589 defm cvta_const  : NG_TO_G<"const", int_nvvm_ptr_constant_to_gen>;
1590
1591 defm cvta_to_local   : G_TO_NG<"local", int_nvvm_ptr_gen_to_local>;
1592 defm cvta_to_shared : G_TO_NG<"shared", int_nvvm_ptr_gen_to_shared>;
1593 defm cvta_to_global : G_TO_NG<"global", int_nvvm_ptr_gen_to_global>;
1594 defm cvta_to_const  : G_TO_NG<"const", int_nvvm_ptr_gen_to_constant>;
1595
1596
1597 // nvvm.ptr.gen.to.param
1598 def nvvm_ptr_gen_to_param : NVPTXInst<(outs Int32Regs:$result),
1599   (ins Int32Regs:$src),
1600                         "mov.u32 \t$result, $src;",
1601                               [(set Int32Regs:$result,
1602                                 (int_nvvm_ptr_gen_to_param Int32Regs:$src))]>;
1603 def nvvm_ptr_gen_to_param_64 : NVPTXInst<(outs Int64Regs:$result),
1604   (ins Int64Regs:$src),
1605                         "mov.u64 \t$result, $src;",
1606                               [(set Int64Regs:$result,
1607                                 (int_nvvm_ptr_gen_to_param Int64Regs:$src))]>;
1608
1609
1610 // nvvm.move intrinsicc
1611 def nvvm_move_i16 : NVPTXInst<(outs Int16Regs:$r), (ins Int16Regs:$s),
1612                              "mov.b16 \t$r, $s;",
1613                              [(set Int16Regs:$r,
1614                                (int_nvvm_move_i16 Int16Regs:$s))]>;
1615 def nvvm_move_i32 : NVPTXInst<(outs Int32Regs:$r), (ins Int32Regs:$s),
1616                              "mov.b32 \t$r, $s;",
1617                              [(set Int32Regs:$r,
1618                                (int_nvvm_move_i32 Int32Regs:$s))]>;
1619 def nvvm_move_i64 : NVPTXInst<(outs Int64Regs:$r), (ins Int64Regs:$s),
1620                              "mov.b64 \t$r, $s;",
1621                              [(set Int64Regs:$r,
1622                                (int_nvvm_move_i64 Int64Regs:$s))]>;
1623 def nvvm_move_float : NVPTXInst<(outs Float32Regs:$r), (ins Float32Regs:$s),
1624                              "mov.f32 \t$r, $s;",
1625                              [(set Float32Regs:$r,
1626                                (int_nvvm_move_float Float32Regs:$s))]>;
1627 def nvvm_move_double : NVPTXInst<(outs Float64Regs:$r), (ins Float64Regs:$s),
1628                              "mov.f64 \t$r, $s;",
1629                              [(set Float64Regs:$r,
1630                                (int_nvvm_move_double Float64Regs:$s))]>;
1631 def nvvm_move_ptr32 : NVPTXInst<(outs Int32Regs:$r), (ins Int32Regs:$s),
1632                              "mov.u32 \t$r, $s;",
1633                              [(set Int32Regs:$r,
1634                                (int_nvvm_move_ptr Int32Regs:$s))]>;
1635 def nvvm_move_ptr64 : NVPTXInst<(outs Int64Regs:$r), (ins Int64Regs:$s),
1636                              "mov.u64 \t$r, $s;",
1637                              [(set Int64Regs:$r,
1638                                (int_nvvm_move_ptr Int64Regs:$s))]>;
1639
1640 // @TODO: Are these actually needed, or will we always just see symbols
1641 // copied to registers first?
1642 /*def nvvm_move_sym32 : NVPTXInst<(outs Int32Regs:$r), (ins imem:$s),
1643                              "mov.u32 \t$r, $s;",
1644                              [(set Int32Regs:$r,
1645                              (int_nvvm_move_ptr texternalsym:$s))]>;
1646 def nvvm_move_sym64 : NVPTXInst<(outs Int64Regs:$r), (ins imem:$s),
1647                              "mov.u64 \t$r, $s;",
1648                              [(set Int64Regs:$r,
1649                              (int_nvvm_move_ptr texternalsym:$s))]>;*/
1650
1651
1652 // MoveParam        %r1, param
1653 // ptr_local_to_gen %r2, %r1
1654 // ptr_gen_to_local %r3, %r2
1655 // ->
1656 // mov %r1, param
1657
1658 // @TODO: Revisit this.  There is a type
1659 // contradiction between iPTRAny and iPTR for the addr defs, so the move_sym
1660 // instructions are not currently defined. However, we can use the ptr
1661 // variants and the asm printer will do the right thing.
1662 def : Pat<(i64 (int_nvvm_ptr_gen_to_local (int_nvvm_ptr_local_to_gen
1663                 (MoveParam texternalsym:$src)))),
1664                (nvvm_move_ptr64  texternalsym:$src)>;
1665 def : Pat<(i32 (int_nvvm_ptr_gen_to_local (int_nvvm_ptr_local_to_gen
1666                 (MoveParam texternalsym:$src)))),
1667                (nvvm_move_ptr32  texternalsym:$src)>;
1668
1669 def texsurf_handles
1670   : NVPTXInst<(outs Int64Regs:$result), (ins imem:$src),
1671               "mov.u64 \t$result, $src;", []>;
1672
1673 //-----------------------------------
1674 // Compiler Error Warn
1675 // - Just ignore them in codegen
1676 //-----------------------------------
1677
1678 def INT_NVVM_COMPILER_WARN_32 : NVPTXInst<(outs), (ins Int32Regs:$a),
1679                 "// llvm.nvvm.compiler.warn()",
1680                 [(int_nvvm_compiler_warn Int32Regs:$a)]>;
1681 def INT_NVVM_COMPILER_WARN_64 : NVPTXInst<(outs), (ins Int64Regs:$a),
1682                 "// llvm.nvvm.compiler.warn()",
1683                 [(int_nvvm_compiler_warn Int64Regs:$a)]>;
1684 def INT_NVVM_COMPILER_ERROR_32 : NVPTXInst<(outs), (ins Int32Regs:$a),
1685                 "// llvm.nvvm.compiler.error()",
1686                 [(int_nvvm_compiler_error Int32Regs:$a)]>;
1687 def INT_NVVM_COMPILER_ERROR_64 : NVPTXInst<(outs), (ins Int64Regs:$a),
1688                 "// llvm.nvvm.compiler.error()",
1689                 [(int_nvvm_compiler_error Int64Regs:$a)]>;
1690
1691
1692 // Special register reads
1693 def MOV_SPECIAL : NVPTXInst<(outs Int32Regs:$d),
1694                             (ins SpecialRegs:$r),
1695                             "mov.b32\t$d, $r;", []>;
1696
1697 def : Pat<(int_nvvm_read_ptx_sreg_envreg0), (MOV_SPECIAL ENVREG0)>;
1698 def : Pat<(int_nvvm_read_ptx_sreg_envreg1), (MOV_SPECIAL ENVREG1)>;
1699 def : Pat<(int_nvvm_read_ptx_sreg_envreg2), (MOV_SPECIAL ENVREG2)>;
1700 def : Pat<(int_nvvm_read_ptx_sreg_envreg3), (MOV_SPECIAL ENVREG3)>;
1701 def : Pat<(int_nvvm_read_ptx_sreg_envreg4), (MOV_SPECIAL ENVREG4)>;
1702 def : Pat<(int_nvvm_read_ptx_sreg_envreg5), (MOV_SPECIAL ENVREG5)>;
1703 def : Pat<(int_nvvm_read_ptx_sreg_envreg6), (MOV_SPECIAL ENVREG6)>;
1704 def : Pat<(int_nvvm_read_ptx_sreg_envreg7), (MOV_SPECIAL ENVREG7)>;
1705 def : Pat<(int_nvvm_read_ptx_sreg_envreg8), (MOV_SPECIAL ENVREG8)>;
1706 def : Pat<(int_nvvm_read_ptx_sreg_envreg9), (MOV_SPECIAL ENVREG9)>;
1707 def : Pat<(int_nvvm_read_ptx_sreg_envreg10), (MOV_SPECIAL ENVREG10)>;
1708 def : Pat<(int_nvvm_read_ptx_sreg_envreg11), (MOV_SPECIAL ENVREG11)>;
1709 def : Pat<(int_nvvm_read_ptx_sreg_envreg12), (MOV_SPECIAL ENVREG12)>;
1710 def : Pat<(int_nvvm_read_ptx_sreg_envreg13), (MOV_SPECIAL ENVREG13)>;
1711 def : Pat<(int_nvvm_read_ptx_sreg_envreg14), (MOV_SPECIAL ENVREG14)>;
1712 def : Pat<(int_nvvm_read_ptx_sreg_envreg15), (MOV_SPECIAL ENVREG15)>;
1713 def : Pat<(int_nvvm_read_ptx_sreg_envreg16), (MOV_SPECIAL ENVREG16)>;
1714 def : Pat<(int_nvvm_read_ptx_sreg_envreg17), (MOV_SPECIAL ENVREG17)>;
1715 def : Pat<(int_nvvm_read_ptx_sreg_envreg18), (MOV_SPECIAL ENVREG18)>;
1716 def : Pat<(int_nvvm_read_ptx_sreg_envreg19), (MOV_SPECIAL ENVREG19)>;
1717 def : Pat<(int_nvvm_read_ptx_sreg_envreg20), (MOV_SPECIAL ENVREG20)>;
1718 def : Pat<(int_nvvm_read_ptx_sreg_envreg21), (MOV_SPECIAL ENVREG21)>;
1719 def : Pat<(int_nvvm_read_ptx_sreg_envreg22), (MOV_SPECIAL ENVREG22)>;
1720 def : Pat<(int_nvvm_read_ptx_sreg_envreg23), (MOV_SPECIAL ENVREG23)>;
1721 def : Pat<(int_nvvm_read_ptx_sreg_envreg24), (MOV_SPECIAL ENVREG24)>;
1722 def : Pat<(int_nvvm_read_ptx_sreg_envreg25), (MOV_SPECIAL ENVREG25)>;
1723 def : Pat<(int_nvvm_read_ptx_sreg_envreg26), (MOV_SPECIAL ENVREG26)>;
1724 def : Pat<(int_nvvm_read_ptx_sreg_envreg27), (MOV_SPECIAL ENVREG27)>;
1725 def : Pat<(int_nvvm_read_ptx_sreg_envreg28), (MOV_SPECIAL ENVREG28)>;
1726 def : Pat<(int_nvvm_read_ptx_sreg_envreg29), (MOV_SPECIAL ENVREG29)>;
1727 def : Pat<(int_nvvm_read_ptx_sreg_envreg30), (MOV_SPECIAL ENVREG30)>;
1728 def : Pat<(int_nvvm_read_ptx_sreg_envreg31), (MOV_SPECIAL ENVREG31)>;
1729
1730
1731 //-----------------------------------
1732 // Texture Intrinsics
1733 //-----------------------------------
1734
1735 // NOTE: For Fermi support, any new texture/surface/sampler intrinsics must be
1736 // also defined in NVPTXReplaceImageHandles.cpp
1737
1738
1739 // Texture fetch instructions using handles
1740 def TEX_1D_F32_I32
1741   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1742                     Float32Regs:$b, Float32Regs:$a),
1743               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x),
1744               "tex.1d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
1745               []>;
1746 def TEX_1D_F32_F32
1747   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1748                     Float32Regs:$b, Float32Regs:$a),
1749               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x),
1750               "tex.1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
1751               []>;
1752 def TEX_1D_F32_F32_LEVEL
1753   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1754                     Float32Regs:$b, Float32Regs:$a),
1755               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$lod),
1756               "tex.level.1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1757               "[$t, $s, \\{$x\\}], $lod;",
1758               []>;
1759 def TEX_1D_F32_F32_GRAD
1760   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1761                     Float32Regs:$b, Float32Regs:$a),
1762               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x,
1763                    Float32Regs:$gradx, Float32Regs:$grady),
1764               "tex.grad.1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1765               "[$t, $s, \\{$x\\}], \\{$gradx\\}, \\{$grady\\};",
1766               []>;
1767 def TEX_1D_I32_I32
1768   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1769                     Int32Regs:$b, Int32Regs:$a),
1770               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x),
1771               "tex.1d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
1772               []>;
1773 def TEX_1D_I32_F32
1774   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1775                     Int32Regs:$b, Int32Regs:$a),
1776               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x),
1777               "tex.1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
1778               []>;
1779 def TEX_1D_I32_F32_LEVEL
1780   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1781                     Int32Regs:$b, Int32Regs:$a),
1782               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x,
1783                    Float32Regs:$lod),
1784               "tex.level.1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1785               "[$t, $s, \\{$x\\}], $lod;",
1786               []>;
1787 def TEX_1D_I32_F32_GRAD
1788   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1789                     Int32Regs:$b, Int32Regs:$a),
1790               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x,
1791                    Float32Regs:$gradx, Float32Regs:$grady),
1792               "tex.grad.1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1793               "[$t, $s, \\{$x\\}], \\{$gradx\\}, \\{$grady\\};",
1794               []>;
1795
1796 def TEX_1D_ARRAY_F32_I32
1797   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1798                     Float32Regs:$b, Float32Regs:$a),
1799               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
1800               "tex.a1d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, "
1801               "[$t, $s, \\{$l, $x\\}];",
1802               []>;
1803 def TEX_1D_ARRAY_F32_F32
1804   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1805                     Float32Regs:$b, Float32Regs:$a),
1806               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x),
1807               "tex.a1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1808               "[$t, $s, \\{$l, $x\\}];",
1809               []>;
1810 def TEX_1D_ARRAY_F32_F32_LEVEL
1811   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1812                     Float32Regs:$b, Float32Regs:$a),
1813               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1814                    Float32Regs:$lod),
1815               "tex.level.a1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1816               "[$t, $s, \\{$l, $x\\}], $lod;",
1817               []>;
1818 def TEX_1D_ARRAY_F32_F32_GRAD
1819   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1820                     Float32Regs:$b, Float32Regs:$a),
1821               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1822                    Float32Regs:$gradx, Float32Regs:$grady),
1823               "tex.grad.a1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1824               "[$t, $s, \\{$l, $x\\}], \\{$gradx\\}, \\{$grady\\};",
1825               []>;
1826 def TEX_1D_ARRAY_I32_I32
1827   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1828                     Int32Regs:$b, Int32Regs:$a),
1829               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
1830               "tex.a1d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, "
1831               "[$t, $s, \\{$l, $x\\}];",
1832               []>;
1833 def TEX_1D_ARRAY_I32_F32
1834   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1835                     Int32Regs:$b, Int32Regs:$a),
1836               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x),
1837               "tex.a1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1838               "[$t, $s, \\{$l, $x\\}];",
1839               []>;
1840 def TEX_1D_ARRAY_I32_F32_LEVEL
1841   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1842                     Int32Regs:$b, Int32Regs:$a),
1843               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1844                    Float32Regs:$lod),
1845               "tex.level.a1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1846               "[$t, $s, \\{$l, $x\\}], $lod;",
1847               []>;
1848 def TEX_1D_ARRAY_I32_F32_GRAD
1849   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1850                     Int32Regs:$b, Int32Regs:$a),
1851               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1852                    Float32Regs:$gradx, Float32Regs:$grady),
1853               "tex.grad.a1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1854               "[$t, $s, \\{$l, $x\\}], \\{$gradx\\}, \\{$grady\\};",
1855               []>;
1856
1857 def TEX_2D_F32_I32
1858   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1859                     Float32Regs:$b, Float32Regs:$a),
1860               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
1861               "tex.2d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, "
1862               "[$t, $s, \\{$x, $y\\}];",
1863               []>;
1864 def TEX_2D_F32_F32
1865   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1866                     Float32Regs:$b, Float32Regs:$a),
1867               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y),
1868               "tex.2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1869               "[$t, $s, \\{$x, $y\\}];",
1870               []>;
1871 def TEX_2D_F32_F32_LEVEL
1872   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1873                     Float32Regs:$b, Float32Regs:$a),
1874               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1875                    Float32Regs:$lod),
1876               "tex.level.2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1877               "[$t, $s, \\{$x, $y\\}], $lod;",
1878               []>;
1879 def TEX_2D_F32_F32_GRAD
1880   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1881                     Float32Regs:$b, Float32Regs:$a),
1882               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1883                    Float32Regs:$gradx0, Float32Regs:$gradx1,
1884                    Float32Regs:$grady0, Float32Regs:$grady1),
1885               "tex.grad.2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1886               "[$t, $s, \\{$x, $y\\}], \\{$gradx0, $gradx1\\}, "
1887               "\\{$grady0, $grady1\\};",
1888               []>;
1889 def TEX_2D_I32_I32
1890   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1891                     Int32Regs:$b, Int32Regs:$a),
1892               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
1893               "tex.2d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, "
1894               "[$t, $s, \\{$x, $y\\}];",
1895               []>;
1896 def TEX_2D_I32_F32
1897   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1898                     Int32Regs:$b, Int32Regs:$a),
1899               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y),
1900               "tex.2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1901               "[$t, $s, \\{$x, $y\\}];",
1902               []>;
1903 def TEX_2D_I32_F32_LEVEL
1904   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1905                     Int32Regs:$b, Int32Regs:$a),
1906               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1907                    Float32Regs:$lod),
1908               "tex.level.2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1909               "[$t, $s, \\{$x, $y\\}], $lod;",
1910               []>;
1911 def TEX_2D_I32_F32_GRAD
1912   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1913                     Int32Regs:$b, Int32Regs:$a),
1914               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1915                    Float32Regs:$gradx0, Float32Regs:$gradx1,
1916                    Float32Regs:$grady0, Float32Regs:$grady1),
1917               "tex.grad.2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1918               "[$t, $s, \\{$x, $y\\}], \\{$gradx0, $gradx1\\}, "
1919               "\\{$grady0, $grady1\\};",
1920               []>;
1921
1922 def TEX_2D_ARRAY_F32_I32
1923   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1924                     Float32Regs:$b, Float32Regs:$a),
1925               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
1926                    Int32Regs:$y),
1927               "tex.a2d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, "
1928               "[$t, $s, \\{$l, $x, $y, $y\\}];",
1929               []>;
1930 def TEX_2D_ARRAY_F32_F32
1931   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1932                     Float32Regs:$b, Float32Regs:$a),
1933               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1934                    Float32Regs:$y),
1935               "tex.a2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1936               "[$t, $s, \\{$l, $x, $y, $y\\}];",
1937               []>;
1938 def TEX_2D_ARRAY_F32_F32_LEVEL
1939   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1940                     Float32Regs:$b, Float32Regs:$a),
1941               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1942                    Float32Regs:$y, Float32Regs:$lod),
1943               "tex.level.a2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1944               "[$t, $s, \\{$l, $x, $y, $y\\}], $lod;",
1945               []>;
1946 def TEX_2D_ARRAY_F32_F32_GRAD
1947   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1948                     Float32Regs:$b, Float32Regs:$a),
1949               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1950                    Float32Regs:$y, Float32Regs:$gradx0, Float32Regs:$gradx1,
1951                    Float32Regs:$grady0, Float32Regs:$grady1),
1952               "tex.grad.a2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1953               "[$t, $s, \\{$l, $x, $y, $y\\}], \\{$gradx0, $gradx1\\}, "
1954               "\\{$grady0, $grady1\\};",
1955               []>;
1956 def TEX_2D_ARRAY_I32_I32
1957   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1958                     Int32Regs:$b, Int32Regs:$a),
1959               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
1960                    Int32Regs:$y),
1961               "tex.a2d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, "
1962               "[$t, $s, \\{$l, $x, $y, $y\\}];",
1963               []>;
1964 def TEX_2D_ARRAY_I32_F32
1965   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1966                     Int32Regs:$b, Int32Regs:$a),
1967               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1968                    Float32Regs:$y),
1969               "tex.a2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1970               "[$t, $s, \\{$l, $x, $y, $y\\}];",
1971               []>;
1972 def TEX_2D_ARRAY_I32_F32_LEVEL
1973   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1974                     Int32Regs:$b, Int32Regs:$a),
1975               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1976                    Float32Regs:$y, Float32Regs:$lod),
1977               "tex.level.a2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1978               "[$t, $s, \\{$l, $x, $y, $y\\}], $lod;",
1979               []>;
1980 def TEX_2D_ARRAY_I32_F32_GRAD
1981   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1982                     Int32Regs:$b, Int32Regs:$a),
1983               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1984                    Float32Regs:$y,
1985                    Float32Regs:$gradx0, Float32Regs:$gradx1,
1986                    Float32Regs:$grady0, Float32Regs:$grady1),
1987               "tex.grad.a2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1988               "[$t, $s, \\{$l, $x, $y, $y\\}], \\{$gradx0, $gradx1\\}, "
1989               "\\{$grady0, $grady1\\};",
1990               []>;
1991
1992 def TEX_3D_F32_I32
1993   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1994                     Float32Regs:$b, Float32Regs:$a),
1995               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
1996                    Int32Regs:$z),
1997               "tex.3d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, "
1998               "[$t, $s, \\{$x, $y, $z, $z\\}];",
1999               []>;
2000 def TEX_3D_F32_F32
2001   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
2002                     Float32Regs:$b, Float32Regs:$a),
2003               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2004                    Float32Regs:$z),
2005               "tex.3d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
2006               "[$t, $s, \\{$x, $y, $z, $z\\}];",
2007               []>;
2008 def TEX_3D_F32_F32_LEVEL
2009   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
2010                     Float32Regs:$b, Float32Regs:$a),
2011               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2012                    Float32Regs:$z, Float32Regs:$lod),
2013               "tex.level.3d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
2014               "[$t, $s, \\{$x, $y, $z, $z\\}], $lod;",
2015               []>;
2016 def TEX_3D_F32_F32_GRAD
2017   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
2018                     Float32Regs:$b, Float32Regs:$a),
2019               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2020                    Float32Regs:$z,
2021                    Float32Regs:$gradx0, Float32Regs:$gradx1,
2022                    Float32Regs:$gradx2, Float32Regs:$grady0,
2023                    Float32Regs:$grady1, Float32Regs:$grady2),
2024               "tex.grad.3d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
2025               "[$t, $s, \\{$x, $y, $z, $z\\}], "
2026               "\\{$gradx0, $gradx1, $gradx2, $gradx2\\}, "
2027               "\\{$grady0, $grady1, $grady2, $grady2\\};",
2028               []>;
2029 def TEX_3D_I32_I32
2030   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
2031                     Int32Regs:$b, Int32Regs:$a),
2032               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
2033                    Int32Regs:$z),
2034               "tex.3d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, "
2035               "[$t, $s, \\{$x, $y, $z, $z\\}];",
2036               []>;
2037 def TEX_3D_I32_F32
2038   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
2039                     Int32Regs:$b, Int32Regs:$a),
2040               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2041                    Float32Regs:$z),
2042               "tex.3d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
2043               "[$t, $s, \\{$x, $y, $z, $z\\}];",
2044               []>;
2045 def TEX_3D_I32_F32_LEVEL
2046   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
2047                     Int32Regs:$b, Int32Regs:$a),
2048               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2049                    Float32Regs:$z, Float32Regs:$lod),
2050               "tex.level.3d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
2051               "[$t, $s, \\{$x, $y, $z, $z\\}], $lod;",
2052               []>;
2053 def TEX_3D_I32_F32_GRAD
2054   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
2055                     Int32Regs:$b, Int32Regs:$a),
2056               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2057                    Float32Regs:$z,
2058                    Float32Regs:$gradx0, Float32Regs:$gradx1,
2059                    Float32Regs:$gradx2, Float32Regs:$grady0,
2060                    Float32Regs:$grady1, Float32Regs:$grady2),
2061               "tex.grad.3d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
2062               "[$t, $s, \\{$x, $y, $z, $z\\}], "
2063               "\\{$gradx0, $gradx1, $gradx2, $gradx2\\}, "
2064               "\\{$grady0, $grady1, $grady2, $grady2\\};",
2065               []>;
2066
2067
2068 // Surface load instructions
2069 def SULD_1D_I8_TRAP
2070   : NVPTXInst<(outs Int16Regs:$r),
2071               (ins Int64Regs:$s, Int32Regs:$x),
2072               "suld.b.1d.b8.trap \\{$r\\}, [$s, \\{$x\\}];",
2073               []>;
2074 def SULD_1D_I16_TRAP
2075   : NVPTXInst<(outs Int16Regs:$r),
2076               (ins Int64Regs:$s, Int32Regs:$x),
2077               "suld.b.1d.b16.trap \\{$r\\}, [$s, \\{$x\\}];",
2078               []>;
2079 def SULD_1D_I32_TRAP
2080   : NVPTXInst<(outs Int32Regs:$r),
2081               (ins Int64Regs:$s, Int32Regs:$x),
2082               "suld.b.1d.b32.trap \\{$r\\}, [$s, \\{$x\\}];",
2083               []>;
2084 def SULD_1D_V2I8_TRAP
2085   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2086               (ins Int64Regs:$s, Int32Regs:$x),
2087               "suld.b.1d.v2.b8.trap \\{$r, $g\\}, [$s, \\{$x\\}];",
2088               []>;
2089 def SULD_1D_V2I16_TRAP
2090   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2091               (ins Int64Regs:$s, Int32Regs:$x),
2092               "suld.b.1d.v2.b16.trap \\{$r, $g\\}, [$s, \\{$x\\}];",
2093               []>;
2094 def SULD_1D_V2I32_TRAP
2095   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2096               (ins Int64Regs:$s, Int32Regs:$x),
2097               "suld.b.1d.v2.b32.trap \\{$r, $g\\}, [$s, \\{$x\\}];",
2098               []>;
2099 def SULD_1D_V4I8_TRAP
2100   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2101               (ins Int64Regs:$s, Int32Regs:$x),
2102               "suld.b.1d.v4.b8.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x\\}];",
2103               []>;
2104 def SULD_1D_V4I16_TRAP
2105   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2106               (ins Int64Regs:$s, Int32Regs:$x),
2107               "suld.b.1d.v4.b16.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x\\}];",
2108               []>;
2109 def SULD_1D_V4I32_TRAP
2110   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2111               (ins Int64Regs:$s, Int32Regs:$x),
2112               "suld.b.1d.v4.b32.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x\\}];",
2113               []>;
2114
2115 def SULD_1D_ARRAY_I8_TRAP
2116   : NVPTXInst<(outs Int16Regs:$r),
2117               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2118               "suld.b.a1d.b8.trap \\{$r\\}, [$s, \\{$l, $x\\}];",
2119               []>;
2120 def SULD_1D_ARRAY_I16_TRAP
2121   : NVPTXInst<(outs Int16Regs:$r),
2122               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2123               "suld.b.a1d.b16.trap \\{$r\\}, [$s, \\{$l, $x\\}];",
2124               []>;
2125 def SULD_1D_ARRAY_I32_TRAP
2126   : NVPTXInst<(outs Int32Regs:$r),
2127               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2128               "suld.b.a1d.b32.trap \\{$r\\}, [$s, \\{$l, $x\\}];",
2129               []>;
2130 def SULD_1D_ARRAY_V2I8_TRAP
2131   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2132               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2133               "suld.b.a1d.v2.b8.trap \\{$r, $g\\}, [$s, \\{$l, $x\\}];",
2134               []>;
2135 def SULD_1D_ARRAY_V2I16_TRAP
2136   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2137               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2138               "suld.b.a1d.v2.b16.trap \\{$r, $g\\}, [$s, \\{$l, $x\\}];",
2139               []>;
2140 def SULD_1D_ARRAY_V2I32_TRAP
2141   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2142               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2143               "suld.b.a1d.v2.b32.trap \\{$r, $g\\}, [$s, \\{$l, $x\\}];",
2144               []>;
2145 def SULD_1D_ARRAY_V4I8_TRAP
2146   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2147               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2148               "suld.b.a1d.v4.b8.trap \\{$r, $g, $b, $a\\}, "
2149               "[$s, \\{$l, $x\\}];",
2150               []>;
2151 def SULD_1D_ARRAY_V4I16_TRAP
2152   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2153               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2154               "suld.b.a1d.v4.b16.trap \\{$r, $g, $b, $a\\}, "
2155               "[$s, \\{$l, $x\\}];",
2156               []>;
2157 def SULD_1D_ARRAY_V4I32_TRAP
2158   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2159               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2160               "suld.b.a1d.v4.b32.trap \\{$r, $g, $b, $a\\}, "
2161               "[$s, \\{$l, $x\\}];",
2162               []>;
2163
2164 def SULD_2D_I8_TRAP
2165   : NVPTXInst<(outs Int16Regs:$r),
2166               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2167               "suld.b.2d.b8.trap \\{$r\\}, [$s, \\{$x, $y\\}];",
2168               []>;
2169 def SULD_2D_I16_TRAP
2170   : NVPTXInst<(outs Int16Regs:$r),
2171               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2172               "suld.b.2d.b16.trap \\{$r\\}, [$s, \\{$x, $y\\}];",
2173               []>;
2174 def SULD_2D_I32_TRAP
2175   : NVPTXInst<(outs Int32Regs:$r),
2176               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2177               "suld.b.2d.b32.trap \\{$r\\}, [$s, \\{$x, $y\\}];",
2178               []>;
2179 def SULD_2D_V2I8_TRAP
2180   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2181               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2182               "suld.b.2d.v2.b8.trap \\{$r, $g\\}, [$s, \\{$x, $y\\}];",
2183               []>;
2184 def SULD_2D_V2I16_TRAP
2185   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2186               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2187               "suld.b.2d.v2.b16.trap \\{$r, $g\\}, [$s, \\{$x, $y\\}];",
2188               []>;
2189 def SULD_2D_V2I32_TRAP
2190   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2191               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2192               "suld.b.2d.v2.b32.trap \\{$r, $g\\}, [$s, \\{$x, $y\\}];",
2193               []>;
2194 def SULD_2D_V4I8_TRAP
2195   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2196               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2197               "suld.b.2d.v4.b8.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x, $y\\}];",
2198               []>;
2199 def SULD_2D_V4I16_TRAP
2200   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2201               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2202               "suld.b.2d.v4.b16.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x, $y\\}];",
2203               []>;
2204 def SULD_2D_V4I32_TRAP
2205   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2206               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2207               "suld.b.2d.v4.b32.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x, $y\\}];",
2208               []>;
2209
2210 def SULD_2D_ARRAY_I8_TRAP
2211   : NVPTXInst<(outs Int16Regs:$r),
2212               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2213               "suld.b.a2d.b8.trap \\{$r\\}, [$s, \\{$l, $x, $y, $y\\}];",
2214               []>;
2215 def SULD_2D_ARRAY_I16_TRAP
2216   : NVPTXInst<(outs Int16Regs:$r),
2217               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2218               "suld.b.a2d.b16.trap \\{$r\\}, [$s, \\{$l, $x, $y, $y\\}];",
2219               []>;
2220 def SULD_2D_ARRAY_I32_TRAP
2221   : NVPTXInst<(outs Int32Regs:$r),
2222               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2223               "suld.b.a2d.b32.trap \\{$r\\}, [$s, \\{$l, $x, $y, $y\\}];",
2224               []>;
2225 def SULD_2D_ARRAY_V2I8_TRAP
2226   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2227               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2228               "suld.b.a2d.v2.b8.trap \\{$r, $g\\}, "
2229               "[$s, \\{$l, $x, $y, $y\\}];",
2230               []>;
2231 def SULD_2D_ARRAY_V2I16_TRAP
2232   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2233               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2234               "suld.b.a2d.v2.b16.trap \\{$r, $g\\}, "
2235               "[$s, \\{$l, $x, $y, $y\\}];",
2236               []>;
2237 def SULD_2D_ARRAY_V2I32_TRAP
2238   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2239               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2240               "suld.b.a2d.v2.b32.trap \\{$r, $g\\}, "
2241               "[$s, \\{$l, $x, $y, $y\\}];",
2242               []>;
2243 def SULD_2D_ARRAY_V4I8_TRAP
2244   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2245               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2246               "suld.b.a2d.v4.b8.trap \\{$r, $g, $b, $a\\}, "
2247               "[$s, \\{$l, $x, $y, $y\\}];",
2248               []>;
2249 def SULD_2D_ARRAY_V4I16_TRAP
2250   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2251               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2252               "suld.b.a2d.v4.b16.trap \\{$r, $g, $b, $a\\}, "
2253               "[$s, \\{$l, $x, $y, $y\\}];",
2254               []>;
2255 def SULD_2D_ARRAY_V4I32_TRAP
2256   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2257               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2258               "suld.b.a2d.v4.b32.trap \\{$r, $g, $b, $a\\}, "
2259               "[$s, \\{$l, $x, $y, $y\\}];",
2260               []>;
2261
2262 def SULD_3D_I8_TRAP
2263   : NVPTXInst<(outs Int16Regs:$r),
2264               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2265               "suld.b.3d.b8.trap \\{$r\\}, [$s, \\{$x, $y, $z, $z\\}];",
2266               []>;
2267 def SULD_3D_I16_TRAP
2268   : NVPTXInst<(outs Int16Regs:$r),
2269               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2270               "suld.b.3d.b16.trap \\{$r\\}, [$s, \\{$x, $y, $z, $z\\}];",
2271               []>;
2272 def SULD_3D_I32_TRAP
2273   : NVPTXInst<(outs Int32Regs:$r),
2274               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2275               "suld.b.3d.b32.trap \\{$r\\}, [$s, \\{$x, $y, $z, $z\\}];",
2276               []>;
2277 def SULD_3D_V2I8_TRAP
2278   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2279               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2280               "suld.b.3d.v2.b8.trap \\{$r, $g\\}, [$s, \\{$x, $y, $z, $z\\}];",
2281               []>;
2282 def SULD_3D_V2I16_TRAP
2283   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2284               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2285               "suld.b.3d.v2.b16.trap \\{$r, $g\\}, [$s, \\{$x, $y, $z, $z\\}];",
2286               []>;
2287 def SULD_3D_V2I32_TRAP
2288   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2289               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2290               "suld.b.3d.v2.b32.trap \\{$r, $g\\}, [$s, \\{$x, $y, $z, $z\\}];",
2291               []>;
2292 def SULD_3D_V4I8_TRAP
2293   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2294               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2295               "suld.b.3d.v4.b8.trap \\{$r, $g, $b, $a\\}, "
2296               "[$s, \\{$x, $y, $z, $z\\}];",
2297               []>;
2298 def SULD_3D_V4I16_TRAP
2299   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2300               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2301               "suld.b.3d.v4.b16.trap \\{$r, $g, $b, $a\\}, "
2302               "[$s, \\{$x, $y, $z, $z\\}];",
2303               []>;
2304 def SULD_3D_V4I32_TRAP
2305   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2306               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2307               "suld.b.3d.v4.b32.trap \\{$r, $g, $b, $a\\}, "
2308               "[$s, \\{$x, $y, $z, $z\\}];",
2309               []>;
2310
2311
2312 //-----------------------------------
2313 // Texture Query Intrinsics
2314 //-----------------------------------
2315 def TXQ_CHANNEL_ORDER
2316   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2317               "txq.channel_order.b32 \t$d, [$a];",
2318               []>;
2319 def TXQ_CHANNEL_DATA_TYPE
2320   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2321               "txq.channel_data_type.b32 \t$d, [$a];",
2322               []>;
2323 def TXQ_WIDTH
2324   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2325               "txq.width.b32 \t$d, [$a];",
2326               []>;
2327 def TXQ_HEIGHT
2328   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2329               "txq.height.b32 \t$d, [$a];",
2330               []>;
2331 def TXQ_DEPTH
2332   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2333               "txq.depth.b32 \t$d, [$a];",
2334               []>;
2335 def TXQ_ARRAY_SIZE
2336   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2337               "txq.array_size.b32 \t$d, [$a];",
2338               []>;
2339 def TXQ_NUM_SAMPLES
2340   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2341               "txq.num_samples.b32 \t$d, [$a];",
2342               []>;
2343 def TXQ_NUM_MIPMAP_LEVELS
2344   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2345               "txq.num_mipmap_levels.b32 \t$d, [$a];",
2346               []>;
2347
2348 def : Pat<(int_nvvm_txq_channel_order Int64Regs:$a),
2349           (TXQ_CHANNEL_ORDER Int64Regs:$a)>;
2350 def : Pat<(int_nvvm_txq_channel_data_type Int64Regs:$a),
2351           (TXQ_CHANNEL_DATA_TYPE Int64Regs:$a)>;
2352 def : Pat<(int_nvvm_txq_width Int64Regs:$a),
2353           (TXQ_WIDTH Int64Regs:$a)>;
2354 def : Pat<(int_nvvm_txq_height Int64Regs:$a),
2355           (TXQ_HEIGHT Int64Regs:$a)>;
2356 def : Pat<(int_nvvm_txq_depth Int64Regs:$a),
2357           (TXQ_DEPTH Int64Regs:$a)>;
2358 def : Pat<(int_nvvm_txq_array_size Int64Regs:$a),
2359           (TXQ_ARRAY_SIZE Int64Regs:$a)>;
2360 def : Pat<(int_nvvm_txq_num_samples Int64Regs:$a),
2361           (TXQ_NUM_SAMPLES Int64Regs:$a)>;
2362 def : Pat<(int_nvvm_txq_num_mipmap_levels Int64Regs:$a),
2363           (TXQ_NUM_MIPMAP_LEVELS Int64Regs:$a)>;
2364
2365
2366 //-----------------------------------
2367 // Surface Query Intrinsics
2368 //-----------------------------------
2369 def SUQ_CHANNEL_ORDER
2370   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2371               "suq.channel_order.b32 \t$d, [$a];",
2372               []>;
2373 def SUQ_CHANNEL_DATA_TYPE
2374   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2375               "suq.channel_data_type.b32 \t$d, [$a];",
2376               []>;
2377 def SUQ_WIDTH
2378   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2379               "suq.width.b32 \t$d, [$a];",
2380               []>;
2381 def SUQ_HEIGHT
2382   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2383               "suq.height.b32 \t$d, [$a];",
2384               []>;
2385 def SUQ_DEPTH
2386   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2387               "suq.depth.b32 \t$d, [$a];",
2388               []>;
2389 def SUQ_ARRAY_SIZE
2390   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2391               "suq.array_size.b32 \t$d, [$a];",
2392               []>;
2393
2394 def : Pat<(int_nvvm_suq_channel_order Int64Regs:$a),
2395           (SUQ_CHANNEL_ORDER Int64Regs:$a)>;
2396 def : Pat<(int_nvvm_suq_channel_data_type Int64Regs:$a),
2397           (SUQ_CHANNEL_DATA_TYPE Int64Regs:$a)>;
2398 def : Pat<(int_nvvm_suq_width Int64Regs:$a),
2399           (SUQ_WIDTH Int64Regs:$a)>;
2400 def : Pat<(int_nvvm_suq_height Int64Regs:$a),
2401           (SUQ_HEIGHT Int64Regs:$a)>;
2402 def : Pat<(int_nvvm_suq_depth Int64Regs:$a),
2403           (SUQ_DEPTH Int64Regs:$a)>;
2404 def : Pat<(int_nvvm_suq_array_size Int64Regs:$a),
2405           (SUQ_ARRAY_SIZE Int64Regs:$a)>;
2406
2407
2408 //===- Handle Query -------------------------------------------------------===//
2409
2410 // TODO: These intrinsics are not yet finalized, pending PTX ISA design work
2411 def ISTYPEP_SAMPLER
2412   : NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
2413               "istypep.samplerref \t$d, $a;",
2414               [(set Int1Regs:$d, (int_nvvm_istypep_sampler Int64Regs:$a))]>;
2415 def ISTYPEP_SURFACE
2416   : NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
2417               "istypep.surfref \t$d, $a;",
2418               [(set Int1Regs:$d, (int_nvvm_istypep_surface Int64Regs:$a))]>;
2419 def ISTYPEP_TEXTURE
2420   : NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
2421               "istypep.texref \t$d, $a;",
2422               [(set Int1Regs:$d, (int_nvvm_istypep_texture Int64Regs:$a))]>;
2423
2424 //===- Surface Stores -----------------------------------------------------===//
2425
2426 // Unformatted
2427
2428 def SUST_B_1D_B8_TRAP
2429   : NVPTXInst<(outs),
2430               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2431               "sust.b.1d.b8.trap \t[$s, \\{$x\\}], \\{$r\\};",
2432               []>;
2433 def SUST_B_1D_B16_TRAP
2434   : NVPTXInst<(outs),
2435               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2436               "sust.b.1d.b16.trap \t[$s, \\{$x\\}], \\{$r\\};",
2437               []>;
2438 def SUST_B_1D_B32_TRAP
2439   : NVPTXInst<(outs),
2440               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r),
2441               "sust.b.1d.b32.trap \t[$s, \\{$x\\}], \\{$r\\};",
2442               []>;
2443 def SUST_B_1D_V2B8_TRAP
2444   : NVPTXInst<(outs),
2445               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2446               "sust.b.1d.v2.b8.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2447               []>;
2448 def SUST_B_1D_V2B16_TRAP
2449   : NVPTXInst<(outs),
2450               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2451               "sust.b.1d.v2.b16.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2452               []>;
2453 def SUST_B_1D_V2B32_TRAP
2454   : NVPTXInst<(outs),
2455               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
2456               "sust.b.1d.v2.b32.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2457               []>;
2458 def SUST_B_1D_V4B8_TRAP
2459   : NVPTXInst<(outs),
2460               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g,
2461                    Int16Regs:$b, Int16Regs:$a),
2462               "sust.b.1d.v4.b8.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2463               []>;
2464 def SUST_B_1D_V4B16_TRAP
2465   : NVPTXInst<(outs),
2466               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g,
2467                    Int16Regs:$b, Int16Regs:$a),
2468               "sust.b.1d.v4.b16.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2469               []>;
2470 def SUST_B_1D_V4B32_TRAP
2471   : NVPTXInst<(outs),
2472               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g,
2473                    Int32Regs:$b, Int32Regs:$a),
2474               "sust.b.1d.v4.b32.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2475               []>;
2476
2477
2478 def SUST_B_1D_ARRAY_B8_TRAP
2479   : NVPTXInst<(outs),
2480               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r),
2481               "sust.b.a1d.b8.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2482               []>;
2483 def SUST_B_1D_ARRAY_B16_TRAP
2484   : NVPTXInst<(outs),
2485               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r),
2486               "sust.b.a1d.b16.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2487               []>;
2488 def SUST_B_1D_ARRAY_B32_TRAP
2489   : NVPTXInst<(outs),
2490               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r),
2491               "sust.b.a1d.b32.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2492               []>;
2493 def SUST_B_1D_ARRAY_V2B8_TRAP
2494   : NVPTXInst<(outs),
2495               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2496                    Int16Regs:$g),
2497               "sust.b.a1d.v2.b8.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2498               []>;
2499 def SUST_B_1D_ARRAY_V2B16_TRAP
2500   : NVPTXInst<(outs),
2501               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2502                    Int16Regs:$g),
2503               "sust.b.a1d.v2.b16.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2504               []>;
2505 def SUST_B_1D_ARRAY_V2B32_TRAP
2506   : NVPTXInst<(outs),
2507               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r,
2508                    Int32Regs:$g),
2509               "sust.b.a1d.v2.b32.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2510               []>;
2511 def SUST_B_1D_ARRAY_V4B8_TRAP
2512   : NVPTXInst<(outs),
2513               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2514                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2515               "sust.b.a1d.v4.b8.trap \t[$s, \\{$idx, $x\\}], "
2516               "\\{$r, $g, $b, $a\\};",
2517               []>;
2518 def SUST_B_1D_ARRAY_V4B16_TRAP
2519   : NVPTXInst<(outs),
2520               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2521                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2522              "sust.b.a1d.v4.b16.trap \t[$s, \\{$idx, $x\\}], "
2523              "\\{$r, $g, $b, $a\\};",
2524               []>;
2525 def SUST_B_1D_ARRAY_V4B32_TRAP
2526   : NVPTXInst<(outs),
2527               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r,
2528                    Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2529              "sust.b.a1d.v4.b32.trap \t[$s, \\{$idx, $x\\}], "
2530              "\\{$r, $g, $b, $a\\};",
2531               []>;
2532
2533
2534 def SUST_B_2D_B8_TRAP
2535   : NVPTXInst<(outs),
2536               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
2537               "sust.b.2d.b8.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2538               []>;
2539 def SUST_B_2D_B16_TRAP
2540   : NVPTXInst<(outs),
2541               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
2542               "sust.b.2d.b16.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2543               []>;
2544 def SUST_B_2D_B32_TRAP
2545   : NVPTXInst<(outs),
2546               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
2547               "sust.b.2d.b32.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2548               []>;
2549 def SUST_B_2D_V2B8_TRAP
2550   : NVPTXInst<(outs),
2551               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2552                    Int16Regs:$g),
2553               "sust.b.2d.v2.b8.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2554               []>;
2555 def SUST_B_2D_V2B16_TRAP
2556   : NVPTXInst<(outs),
2557               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2558                    Int16Regs:$g),
2559               "sust.b.2d.v2.b16.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2560               []>;
2561 def SUST_B_2D_V2B32_TRAP
2562   : NVPTXInst<(outs),
2563               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
2564                    Int32Regs:$g),
2565               "sust.b.2d.v2.b32.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2566               []>;
2567 def SUST_B_2D_V4B8_TRAP
2568   : NVPTXInst<(outs),
2569               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2570                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2571               "sust.b.2d.v4.b8.trap \t[$s, \\{$x, $y\\}], "
2572               "\\{$r, $g, $b, $a\\};",
2573               []>;
2574 def SUST_B_2D_V4B16_TRAP
2575   : NVPTXInst<(outs),
2576               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2577                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2578              "sust.b.2d.v4.b16.trap \t[$s, \\{$x, $y\\}], "
2579              "\\{$r, $g, $b, $a\\};",
2580               []>;
2581 def SUST_B_2D_V4B32_TRAP
2582   : NVPTXInst<(outs),
2583               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
2584                    Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2585              "sust.b.2d.v4.b32.trap \t[$s, \\{$x, $y\\}], "
2586              "\\{$r, $g, $b, $a\\};",
2587               []>;
2588
2589
2590 def SUST_B_2D_ARRAY_B8_TRAP
2591   : NVPTXInst<(outs),
2592               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2593                    Int16Regs:$r),
2594               "sust.b.a2d.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2595               []>;
2596 def SUST_B_2D_ARRAY_B16_TRAP
2597   : NVPTXInst<(outs),
2598               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2599                    Int16Regs:$r),
2600               "sust.b.a2d.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2601               []>;
2602 def SUST_B_2D_ARRAY_B32_TRAP
2603   : NVPTXInst<(outs),
2604               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2605                    Int32Regs:$r),
2606               "sust.b.a2d.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2607               []>;
2608 def SUST_B_2D_ARRAY_V2B8_TRAP
2609   : NVPTXInst<(outs),
2610               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2611                    Int16Regs:$r, Int16Regs:$g),
2612               "sust.b.a2d.v2.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2613               "\\{$r, $g\\};",
2614               []>;
2615 def SUST_B_2D_ARRAY_V2B16_TRAP
2616   : NVPTXInst<(outs),
2617               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2618                    Int16Regs:$r, Int16Regs:$g),
2619              "sust.b.a2d.v2.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2620              "\\{$r, $g\\};",
2621               []>;
2622 def SUST_B_2D_ARRAY_V2B32_TRAP
2623   : NVPTXInst<(outs),
2624               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2625                    Int32Regs:$r, Int32Regs:$g),
2626              "sust.b.a2d.v2.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2627              "\\{$r, $g\\};",
2628               []>;
2629 def SUST_B_2D_ARRAY_V4B8_TRAP
2630   : NVPTXInst<(outs),
2631               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2632                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2633       "sust.b.a2d.v4.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2634       "\\{$r, $g, $b, $a\\};",
2635               []>;
2636 def SUST_B_2D_ARRAY_V4B16_TRAP
2637   : NVPTXInst<(outs),
2638               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2639                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2640      "sust.b.a2d.v4.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2641      "\\{$r, $g, $b, $a\\};",
2642               []>;
2643 def SUST_B_2D_ARRAY_V4B32_TRAP
2644   : NVPTXInst<(outs),
2645               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2646                    Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2647      "sust.b.a2d.v4.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2648      "\\{$r, $g, $b, $a\\};",
2649               []>;
2650
2651
2652 def SUST_B_3D_B8_TRAP
2653   : NVPTXInst<(outs),
2654               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2655                    Int16Regs:$r),
2656               "sust.b.3d.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2657               []>;
2658 def SUST_B_3D_B16_TRAP
2659   : NVPTXInst<(outs),
2660               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2661                    Int16Regs:$r),
2662               "sust.b.3d.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2663               []>;
2664 def SUST_B_3D_B32_TRAP
2665   : NVPTXInst<(outs),
2666               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2667                    Int32Regs:$r),
2668               "sust.b.3d.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2669               []>;
2670 def SUST_B_3D_V2B8_TRAP
2671   : NVPTXInst<(outs),
2672               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2673                    Int16Regs:$r, Int16Regs:$g),
2674               "sust.b.3d.v2.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2675               "\\{$r, $g\\};",
2676               []>;
2677 def SUST_B_3D_V2B16_TRAP
2678   : NVPTXInst<(outs),
2679               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2680                    Int16Regs:$r, Int16Regs:$g),
2681               "sust.b.3d.v2.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2682               "\\{$r, $g\\};",
2683               []>;
2684 def SUST_B_3D_V2B32_TRAP
2685   : NVPTXInst<(outs),
2686               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2687                    Int32Regs:$r, Int32Regs:$g),
2688               "sust.b.3d.v2.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2689               "\\{$r, $g\\};",
2690               []>;
2691 def SUST_B_3D_V4B8_TRAP
2692   : NVPTXInst<(outs),
2693               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2694                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2695          "sust.b.3d.v4.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2696          "\\{$r, $g, $b, $a\\};",
2697               []>;
2698 def SUST_B_3D_V4B16_TRAP
2699   : NVPTXInst<(outs),
2700               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2701                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2702         "sust.b.3d.v4.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2703         "\\{$r, $g, $b, $a\\};",
2704               []>;
2705 def SUST_B_3D_V4B32_TRAP
2706   : NVPTXInst<(outs),
2707               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2708                    Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2709         "sust.b.3d.v4.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2710         "\\{$r, $g, $b, $a\\};",
2711               []>;
2712
2713 // Formatted
2714
2715 def SUST_P_1D_B8_TRAP
2716   : NVPTXInst<(outs),
2717               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2718               "sust.p.1d.b8.trap \t[$s, \\{$x\\}], \\{$r\\};",
2719               []>;
2720 def SUST_P_1D_B16_TRAP
2721   : NVPTXInst<(outs),
2722               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2723               "sust.p.1d.b16.trap \t[$s, \\{$x\\}], \\{$r\\};",
2724               []>;
2725 def SUST_P_1D_B32_TRAP
2726   : NVPTXInst<(outs),
2727               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r),
2728               "sust.p.1d.b32.trap \t[$s, \\{$x\\}], \\{$r\\};",
2729               []>;
2730 def SUST_P_1D_V2B8_TRAP
2731   : NVPTXInst<(outs),
2732               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2733               "sust.p.1d.v2.b8.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2734               []>;
2735 def SUST_P_1D_V2B16_TRAP
2736   : NVPTXInst<(outs),
2737               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2738               "sust.p.1d.v2.b16.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2739               []>;
2740 def SUST_P_1D_V2B32_TRAP
2741   : NVPTXInst<(outs),
2742               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
2743               "sust.p.1d.v2.b32.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2744               []>;
2745 def SUST_P_1D_V4B8_TRAP
2746   : NVPTXInst<(outs),
2747               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g,
2748                    Int16Regs:$b, Int16Regs:$a),
2749               "sust.p.1d.v4.b8.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2750               []>;
2751 def SUST_P_1D_V4B16_TRAP
2752   : NVPTXInst<(outs),
2753               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g,
2754                    Int16Regs:$b, Int16Regs:$a),
2755               "sust.p.1d.v4.b16.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2756               []>;
2757 def SUST_P_1D_V4B32_TRAP
2758   : NVPTXInst<(outs),
2759               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g,
2760                    Int32Regs:$b, Int32Regs:$a),
2761               "sust.p.1d.v4.b32.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2762               []>;
2763
2764
2765 def SUST_P_1D_ARRAY_B8_TRAP
2766   : NVPTXInst<(outs),
2767               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r),
2768               "sust.p.a1d.b8.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2769               []>;
2770 def SUST_P_1D_ARRAY_B16_TRAP
2771   : NVPTXInst<(outs),
2772               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r),
2773               "sust.p.a1d.b16.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2774               []>;
2775 def SUST_P_1D_ARRAY_B32_TRAP
2776   : NVPTXInst<(outs),
2777               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r),
2778               "sust.p.a1d.b32.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2779               []>;
2780 def SUST_P_1D_ARRAY_V2B8_TRAP
2781   : NVPTXInst<(outs),
2782               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2783                    Int16Regs:$g),
2784               "sust.p.a1d.v2.b8.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2785               []>;
2786 def SUST_P_1D_ARRAY_V2B16_TRAP
2787   : NVPTXInst<(outs),
2788               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2789                    Int16Regs:$g),
2790               "sust.p.a1d.v2.b16.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2791               []>;
2792 def SUST_P_1D_ARRAY_V2B32_TRAP
2793   : NVPTXInst<(outs),
2794               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r,
2795                    Int32Regs:$g),
2796               "sust.p.a1d.v2.b32.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2797               []>;
2798 def SUST_P_1D_ARRAY_V4B8_TRAP
2799   : NVPTXInst<(outs),
2800               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2801                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2802               "sust.p.a1d.v4.b8.trap \t[$s, \\{$idx, $x\\}], "
2803               "\\{$r, $g, $b, $a\\};",
2804               []>;
2805 def SUST_P_1D_ARRAY_V4B16_TRAP
2806   : NVPTXInst<(outs),
2807               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2808                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2809              "sust.p.a1d.v4.b16.trap \t[$s, \\{$idx, $x\\}], "
2810              "\\{$r, $g, $b, $a\\};",
2811               []>;
2812 def SUST_P_1D_ARRAY_V4B32_TRAP
2813   : NVPTXInst<(outs),
2814               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r,
2815                    Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2816              "sust.p.a1d.v4.b32.trap \t[$s, \\{$idx, $x\\}], "
2817              "\\{$r, $g, $b, $a\\};",
2818               []>;
2819
2820
2821 def SUST_P_2D_B8_TRAP
2822   : NVPTXInst<(outs),
2823               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
2824               "sust.p.2d.b8.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2825               []>;
2826 def SUST_P_2D_B16_TRAP
2827   : NVPTXInst<(outs),
2828               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
2829               "sust.p.2d.b16.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2830               []>;
2831 def SUST_P_2D_B32_TRAP
2832   : NVPTXInst<(outs),
2833               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
2834               "sust.p.2d.b32.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2835               []>;
2836 def SUST_P_2D_V2B8_TRAP
2837   : NVPTXInst<(outs),
2838               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2839                    Int16Regs:$g),
2840               "sust.p.2d.v2.b8.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2841               []>;
2842 def SUST_P_2D_V2B16_TRAP
2843   : NVPTXInst<(outs),
2844               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2845                    Int16Regs:$g),
2846               "sust.p.2d.v2.b16.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2847               []>;
2848 def SUST_P_2D_V2B32_TRAP
2849   : NVPTXInst<(outs),
2850               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
2851                    Int32Regs:$g),
2852               "sust.p.2d.v2.b32.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2853               []>;
2854 def SUST_P_2D_V4B8_TRAP
2855   : NVPTXInst<(outs),
2856               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2857                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2858               "sust.p.2d.v4.b8.trap \t[$s, \\{$x, $y\\}], "
2859               "\\{$r, $g, $b, $a\\};",
2860               []>;
2861 def SUST_P_2D_V4B16_TRAP
2862   : NVPTXInst<(outs),
2863               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2864                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2865              "sust.p.2d.v4.b16.trap \t[$s, \\{$x, $y\\}], "
2866              "\\{$r, $g, $b, $a\\};",
2867               []>;
2868 def SUST_P_2D_V4B32_TRAP
2869   : NVPTXInst<(outs),
2870               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
2871                    Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2872              "sust.p.2d.v4.b32.trap \t[$s, \\{$x, $y\\}], "
2873              "\\{$r, $g, $b, $a\\};",
2874               []>;
2875
2876
2877 def SUST_P_2D_ARRAY_B8_TRAP
2878   : NVPTXInst<(outs),
2879               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2880                    Int16Regs:$r),
2881               "sust.p.a2d.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2882               []>;
2883 def SUST_P_2D_ARRAY_B16_TRAP
2884   : NVPTXInst<(outs),
2885               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2886                    Int16Regs:$r),
2887               "sust.p.a2d.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2888               []>;
2889 def SUST_P_2D_ARRAY_B32_TRAP
2890   : NVPTXInst<(outs),
2891               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2892                    Int32Regs:$r),
2893               "sust.p.a2d.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2894               []>;
2895 def SUST_P_2D_ARRAY_V2B8_TRAP
2896   : NVPTXInst<(outs),
2897               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2898                    Int16Regs:$r, Int16Regs:$g),
2899               "sust.p.a2d.v2.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2900               "\\{$r, $g\\};",
2901               []>;
2902 def SUST_P_2D_ARRAY_V2B16_TRAP
2903   : NVPTXInst<(outs),
2904               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2905                    Int16Regs:$r, Int16Regs:$g),
2906              "sust.p.a2d.v2.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2907              "\\{$r, $g\\};",
2908               []>;
2909 def SUST_P_2D_ARRAY_V2B32_TRAP
2910   : NVPTXInst<(outs),
2911               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2912                    Int32Regs:$r, Int32Regs:$g),
2913              "sust.p.a2d.v2.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2914              "\\{$r, $g\\};",
2915               []>;
2916 def SUST_P_2D_ARRAY_V4B8_TRAP
2917   : NVPTXInst<(outs),
2918               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2919                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2920       "sust.p.a2d.v4.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2921       "\\{$r, $g, $b, $a\\};",
2922               []>;
2923 def SUST_P_2D_ARRAY_V4B16_TRAP
2924   : NVPTXInst<(outs),
2925               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2926                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2927      "sust.p.a2d.v4.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2928      "\\{$r, $g, $b, $a\\};",
2929               []>;
2930 def SUST_P_2D_ARRAY_V4B32_TRAP
2931   : NVPTXInst<(outs),
2932               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2933                    Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2934      "sust.p.a2d.v4.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2935      "\\{$r, $g, $b, $a\\};",
2936               []>;
2937
2938
2939 def SUST_P_3D_B8_TRAP
2940   : NVPTXInst<(outs),
2941               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2942                    Int16Regs:$r),
2943               "sust.p.3d.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2944               []>;
2945 def SUST_P_3D_B16_TRAP
2946   : NVPTXInst<(outs),
2947               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2948                    Int16Regs:$r),
2949               "sust.p.3d.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2950               []>;
2951 def SUST_P_3D_B32_TRAP
2952   : NVPTXInst<(outs),
2953               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2954                    Int32Regs:$r),
2955               "sust.p.3d.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2956               []>;
2957 def SUST_P_3D_V2B8_TRAP
2958   : NVPTXInst<(outs),
2959               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2960                    Int16Regs:$r, Int16Regs:$g),
2961               "sust.p.3d.v2.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2962               "\\{$r, $g\\};",
2963               []>;
2964 def SUST_P_3D_V2B16_TRAP
2965   : NVPTXInst<(outs),
2966               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2967                    Int16Regs:$r, Int16Regs:$g),
2968               "sust.p.3d.v2.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2969               "\\{$r, $g\\};",
2970               []>;
2971 def SUST_P_3D_V2B32_TRAP
2972   : NVPTXInst<(outs),
2973               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2974                    Int32Regs:$r, Int32Regs:$g),
2975               "sust.p.3d.v2.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2976               "\\{$r, $g\\};",
2977               []>;
2978 def SUST_P_3D_V4B8_TRAP
2979   : NVPTXInst<(outs),
2980               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2981                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2982          "sust.p.3d.v4.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2983          "\\{$r, $g, $b, $a\\};",
2984               []>;
2985 def SUST_P_3D_V4B16_TRAP
2986   : NVPTXInst<(outs),
2987               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2988                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2989         "sust.p.3d.v4.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2990         "\\{$r, $g, $b, $a\\};",
2991               []>;
2992 def SUST_P_3D_V4B32_TRAP
2993   : NVPTXInst<(outs),
2994               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2995                    Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2996         "sust.p.3d.v4.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2997         "\\{$r, $g, $b, $a\\};",
2998               []>;
2999
3000
3001 // Surface store instruction patterns
3002 // I'm not sure why we can't just include these in the instruction definitions,
3003 // but TableGen complains of type errors :(
3004
3005 def : Pat<(int_nvvm_sust_b_1d_i8_trap
3006            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
3007           (SUST_B_1D_B8_TRAP Int64Regs:$s, Int32Regs:$x, Int16Regs:$r)>;
3008
3009 def : Pat<(int_nvvm_sust_b_1d_i16_trap
3010            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
3011           (SUST_B_1D_B16_TRAP Int64Regs:$s, Int32Regs:$x, Int16Regs:$r)>;
3012
3013 def : Pat<(int_nvvm_sust_b_1d_i32_trap
3014            Int64Regs:$s, Int32Regs:$x, Int32Regs:$r),
3015           (SUST_B_1D_B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$r)>;
3016
3017 def : Pat<(int_nvvm_sust_b_1d_v2i8_trap
3018            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3019           (SUST_B_1D_V2B8_TRAP Int64Regs:$s, Int32Regs:$x,
3020            Int16Regs:$r, Int16Regs:$g)>;
3021
3022 def : Pat<(int_nvvm_sust_b_1d_v2i16_trap
3023            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3024           (SUST_B_1D_V2B16_TRAP Int64Regs:$s, Int32Regs:$x,
3025            Int16Regs:$r, Int16Regs:$g)>;
3026
3027 def : Pat<(int_nvvm_sust_b_1d_v2i32_trap
3028            Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
3029           (SUST_B_1D_V2B32_TRAP Int64Regs:$s, Int32Regs:$x,
3030            Int32Regs:$r, Int32Regs:$g)>;
3031
3032 def : Pat<(int_nvvm_sust_b_1d_v4i8_trap
3033            Int64Regs:$s, Int32Regs:$x,
3034            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3035           (SUST_B_1D_V4B8_TRAP Int64Regs:$s, Int32Regs:$x,
3036            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3037
3038 def : Pat<(int_nvvm_sust_b_1d_v4i16_trap
3039            Int64Regs:$s, Int32Regs:$x,
3040            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3041           (SUST_B_1D_V4B16_TRAP Int64Regs:$s, Int32Regs:$x,
3042            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3043
3044 def : Pat<(int_nvvm_sust_b_1d_v4i32_trap
3045            Int64Regs:$s, Int32Regs:$x,
3046            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3047           (SUST_B_1D_V4B32_TRAP Int64Regs:$s, Int32Regs:$x,
3048            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3049
3050
3051
3052 def : Pat<(int_nvvm_sust_b_1d_array_i8_trap
3053            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r),
3054           (SUST_B_1D_ARRAY_B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3055            Int16Regs:$r)>;
3056
3057 def : Pat<(int_nvvm_sust_b_1d_array_i16_trap
3058            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r),
3059           (SUST_B_1D_ARRAY_B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3060            Int16Regs:$r)>;
3061
3062 def : Pat<(int_nvvm_sust_b_1d_array_i32_trap
3063            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$r),
3064           (SUST_B_1D_ARRAY_B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3065            Int32Regs:$r)>;
3066
3067 def : Pat<(int_nvvm_sust_b_1d_array_v2i8_trap
3068           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3069           (SUST_B_1D_ARRAY_V2B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3070            Int16Regs:$r, Int16Regs:$g)>;
3071
3072 def : Pat<(int_nvvm_sust_b_1d_array_v2i16_trap
3073           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3074           (SUST_B_1D_ARRAY_V2B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3075            Int16Regs:$r, Int16Regs:$g)>;
3076
3077 def : Pat<(int_nvvm_sust_b_1d_array_v2i32_trap
3078           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
3079           (SUST_B_1D_ARRAY_V2B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3080            Int32Regs:$r, Int32Regs:$g)>;
3081
3082 def : Pat<(int_nvvm_sust_b_1d_array_v4i8_trap
3083            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3084            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3085           (SUST_B_1D_ARRAY_V4B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3086            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3087
3088 def : Pat<(int_nvvm_sust_b_1d_array_v4i16_trap
3089            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3090            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3091           (SUST_B_1D_ARRAY_V4B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3092            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3093
3094 def : Pat<(int_nvvm_sust_b_1d_array_v4i32_trap
3095            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3096            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3097           (SUST_B_1D_ARRAY_V4B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3098            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3099
3100
3101
3102 def : Pat<(int_nvvm_sust_b_2d_i8_trap
3103            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3104           (SUST_B_2D_B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3105            Int16Regs:$r)>;
3106
3107 def : Pat<(int_nvvm_sust_b_2d_i16_trap
3108            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3109           (SUST_B_2D_B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3110            Int16Regs:$r)>;
3111
3112 def : Pat<(int_nvvm_sust_b_2d_i32_trap
3113            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
3114           (SUST_B_2D_B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3115            Int32Regs:$r)>;
3116
3117 def : Pat<(int_nvvm_sust_b_2d_v2i8_trap
3118           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r, Int16Regs:$g),
3119           (SUST_B_2D_V2B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3120            Int16Regs:$r, Int16Regs:$g)>;
3121
3122 def : Pat<(int_nvvm_sust_b_2d_v2i16_trap
3123           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r, Int16Regs:$g),
3124           (SUST_B_2D_V2B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3125            Int16Regs:$r, Int16Regs:$g)>;
3126
3127 def : Pat<(int_nvvm_sust_b_2d_v2i32_trap
3128           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r, Int32Regs:$g),
3129           (SUST_B_2D_V2B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3130            Int32Regs:$r, Int32Regs:$g)>;
3131
3132 def : Pat<(int_nvvm_sust_b_2d_v4i8_trap
3133            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3134            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3135           (SUST_B_2D_V4B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3136            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3137
3138 def : Pat<(int_nvvm_sust_b_2d_v4i16_trap
3139            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3140            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3141           (SUST_B_2D_V4B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3142            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3143
3144 def : Pat<(int_nvvm_sust_b_2d_v4i32_trap
3145            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3146            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3147           (SUST_B_2D_V4B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3148            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3149
3150
3151
3152 def : Pat<(int_nvvm_sust_b_2d_array_i8_trap
3153           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3154           (SUST_B_2D_ARRAY_B8_TRAP Int64Regs:$s,
3155            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3156            Int16Regs:$r)>;
3157
3158 def : Pat<(int_nvvm_sust_b_2d_array_i16_trap
3159           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3160           (SUST_B_2D_ARRAY_B16_TRAP Int64Regs:$s,
3161            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3162            Int16Regs:$r)>;
3163
3164 def : Pat<(int_nvvm_sust_b_2d_array_i32_trap
3165           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
3166           (SUST_B_2D_ARRAY_B32_TRAP Int64Regs:$s,
3167            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3168            Int32Regs:$r)>;
3169
3170 def : Pat<(int_nvvm_sust_b_2d_array_v2i8_trap
3171            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3172            Int16Regs:$r, Int16Regs:$g),
3173           (SUST_B_2D_ARRAY_V2B8_TRAP Int64Regs:$s, Int32Regs:$l,
3174            Int32Regs:$x, Int32Regs:$y,
3175            Int16Regs:$r, Int16Regs:$g)>;
3176
3177 def : Pat<(int_nvvm_sust_b_2d_array_v2i16_trap
3178            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3179            Int16Regs:$r, Int16Regs:$g),
3180           (SUST_B_2D_ARRAY_V2B16_TRAP Int64Regs:$s, Int32Regs:$l,
3181            Int32Regs:$x, Int32Regs:$y,
3182            Int16Regs:$r, Int16Regs:$g)>;
3183
3184 def : Pat<(int_nvvm_sust_b_2d_array_v2i32_trap
3185            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
3186            Int32Regs:$g),
3187           (SUST_B_2D_ARRAY_V2B32_TRAP Int64Regs:$s, Int32Regs:$l,
3188            Int32Regs:$x, Int32Regs:$y, Int32Regs:$r, Int32Regs:$g)>;
3189
3190 def : Pat<(int_nvvm_sust_b_2d_array_v4i8_trap
3191            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3192            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3193           (SUST_B_2D_ARRAY_V4B8_TRAP Int64Regs:$s,
3194            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3195            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3196
3197 def : Pat<(int_nvvm_sust_b_2d_array_v4i16_trap
3198            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3199            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3200           (SUST_B_2D_ARRAY_V4B16_TRAP Int64Regs:$s,
3201            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3202            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3203
3204 def : Pat<(int_nvvm_sust_b_2d_array_v4i32_trap
3205            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3206            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3207           (SUST_B_2D_ARRAY_V4B32_TRAP Int64Regs:$s, Int32Regs:$l,
3208            Int32Regs:$x, Int32Regs:$y,
3209            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3210
3211
3212
3213 def : Pat<(int_nvvm_sust_b_3d_i8_trap
3214            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3215            Int16Regs:$r),
3216           (SUST_B_3D_B8_TRAP Int64Regs:$s,
3217            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3218            Int16Regs:$r)>;
3219
3220 def : Pat<(int_nvvm_sust_b_3d_i16_trap
3221            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3222            Int16Regs:$r),
3223           (SUST_B_3D_B16_TRAP Int64Regs:$s,
3224            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3225            Int16Regs:$r)>;
3226
3227 def : Pat<(int_nvvm_sust_b_3d_i32_trap
3228            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3229            Int32Regs:$r),
3230           (SUST_B_3D_B32_TRAP Int64Regs:$s,
3231            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3232            Int32Regs:$r)>;
3233
3234 def : Pat<(int_nvvm_sust_b_3d_v2i8_trap
3235            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3236            Int16Regs:$r, Int16Regs:$g),
3237           (SUST_B_3D_V2B8_TRAP Int64Regs:$s,
3238            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3239            Int16Regs:$r, Int16Regs:$g)>;
3240
3241 def : Pat<(int_nvvm_sust_b_3d_v2i16_trap
3242            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3243            Int16Regs:$r, Int16Regs:$g),
3244           (SUST_B_3D_V2B16_TRAP Int64Regs:$s,
3245            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3246            Int16Regs:$r, Int16Regs:$g)>;
3247
3248 def : Pat<(int_nvvm_sust_b_3d_v2i32_trap
3249            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3250            Int32Regs:$r, Int32Regs:$g),
3251           (SUST_B_3D_V2B32_TRAP Int64Regs:$s,
3252            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3253            Int32Regs:$r, Int32Regs:$g)>;
3254
3255 def : Pat<(int_nvvm_sust_b_3d_v4i8_trap
3256            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3257            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3258           (SUST_B_3D_V4B8_TRAP Int64Regs:$s,
3259            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3260            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3261
3262 def : Pat<(int_nvvm_sust_b_3d_v4i16_trap
3263            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3264            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3265           (SUST_B_3D_V4B16_TRAP Int64Regs:$s,
3266            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3267            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3268
3269 def : Pat<(int_nvvm_sust_b_3d_v4i32_trap
3270            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3271            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3272           (SUST_B_3D_V4B32_TRAP Int64Regs:$s,
3273            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3274            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3275
3276
3277
3278
3279 def : Pat<(int_nvvm_sust_p_1d_i8_trap
3280            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
3281           (SUST_P_1D_B8_TRAP Int64Regs:$s, Int32Regs:$x, Int16Regs:$r)>;
3282
3283 def : Pat<(int_nvvm_sust_p_1d_i16_trap
3284            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
3285           (SUST_P_1D_B16_TRAP Int64Regs:$s, Int32Regs:$x, Int16Regs:$r)>;
3286
3287 def : Pat<(int_nvvm_sust_p_1d_i32_trap
3288            Int64Regs:$s, Int32Regs:$x, Int32Regs:$r),
3289           (SUST_P_1D_B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$r)>;
3290
3291 def : Pat<(int_nvvm_sust_p_1d_v2i8_trap
3292            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3293           (SUST_P_1D_V2B8_TRAP Int64Regs:$s, Int32Regs:$x,
3294            Int16Regs:$r, Int16Regs:$g)>;
3295
3296 def : Pat<(int_nvvm_sust_p_1d_v2i16_trap
3297            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3298           (SUST_P_1D_V2B16_TRAP Int64Regs:$s, Int32Regs:$x,
3299            Int16Regs:$r, Int16Regs:$g)>;
3300
3301 def : Pat<(int_nvvm_sust_p_1d_v2i32_trap
3302            Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
3303           (SUST_P_1D_V2B32_TRAP Int64Regs:$s, Int32Regs:$x,
3304            Int32Regs:$r, Int32Regs:$g)>;
3305
3306 def : Pat<(int_nvvm_sust_p_1d_v4i8_trap
3307            Int64Regs:$s, Int32Regs:$x,
3308            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3309           (SUST_P_1D_V4B8_TRAP Int64Regs:$s, Int32Regs:$x,
3310            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3311
3312 def : Pat<(int_nvvm_sust_p_1d_v4i16_trap
3313            Int64Regs:$s, Int32Regs:$x,
3314            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3315           (SUST_P_1D_V4B16_TRAP Int64Regs:$s, Int32Regs:$x,
3316            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3317
3318 def : Pat<(int_nvvm_sust_p_1d_v4i32_trap
3319            Int64Regs:$s, Int32Regs:$x,
3320            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3321           (SUST_P_1D_V4B32_TRAP Int64Regs:$s, Int32Regs:$x,
3322            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3323
3324
3325
3326 def : Pat<(int_nvvm_sust_p_1d_array_i8_trap
3327            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r),
3328           (SUST_P_1D_ARRAY_B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3329            Int16Regs:$r)>;
3330
3331 def : Pat<(int_nvvm_sust_p_1d_array_i16_trap
3332            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r),
3333           (SUST_P_1D_ARRAY_B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3334            Int16Regs:$r)>;
3335
3336 def : Pat<(int_nvvm_sust_p_1d_array_i32_trap
3337            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$r),
3338           (SUST_P_1D_ARRAY_B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3339            Int32Regs:$r)>;
3340
3341 def : Pat<(int_nvvm_sust_p_1d_array_v2i8_trap
3342           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3343           (SUST_P_1D_ARRAY_V2B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3344            Int16Regs:$r, Int16Regs:$g)>;
3345
3346 def : Pat<(int_nvvm_sust_p_1d_array_v2i16_trap
3347           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3348           (SUST_P_1D_ARRAY_V2B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3349            Int16Regs:$r, Int16Regs:$g)>;
3350
3351 def : Pat<(int_nvvm_sust_p_1d_array_v2i32_trap
3352           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
3353           (SUST_P_1D_ARRAY_V2B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3354            Int32Regs:$r, Int32Regs:$g)>;
3355
3356 def : Pat<(int_nvvm_sust_p_1d_array_v4i8_trap
3357            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3358            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3359           (SUST_P_1D_ARRAY_V4B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3360            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3361
3362 def : Pat<(int_nvvm_sust_p_1d_array_v4i16_trap
3363            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3364            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3365           (SUST_P_1D_ARRAY_V4B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3366            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3367
3368 def : Pat<(int_nvvm_sust_p_1d_array_v4i32_trap
3369            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3370            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3371           (SUST_P_1D_ARRAY_V4B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3372            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3373
3374
3375
3376 def : Pat<(int_nvvm_sust_p_2d_i8_trap
3377            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3378           (SUST_P_2D_B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3379            Int16Regs:$r)>;
3380
3381 def : Pat<(int_nvvm_sust_p_2d_i16_trap
3382            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3383           (SUST_P_2D_B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3384            Int16Regs:$r)>;
3385
3386 def : Pat<(int_nvvm_sust_p_2d_i32_trap
3387            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
3388           (SUST_P_2D_B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3389            Int32Regs:$r)>;
3390
3391 def : Pat<(int_nvvm_sust_p_2d_v2i8_trap
3392           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r, Int16Regs:$g),
3393           (SUST_P_2D_V2B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3394            Int16Regs:$r, Int16Regs:$g)>;
3395
3396 def : Pat<(int_nvvm_sust_p_2d_v2i16_trap
3397           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r, Int16Regs:$g),
3398           (SUST_P_2D_V2B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3399            Int16Regs:$r, Int16Regs:$g)>;
3400
3401 def : Pat<(int_nvvm_sust_p_2d_v2i32_trap
3402           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r, Int32Regs:$g),
3403           (SUST_P_2D_V2B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3404            Int32Regs:$r, Int32Regs:$g)>;
3405
3406 def : Pat<(int_nvvm_sust_p_2d_v4i8_trap
3407            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3408            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3409           (SUST_P_2D_V4B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3410            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3411
3412 def : Pat<(int_nvvm_sust_p_2d_v4i16_trap
3413            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3414            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3415           (SUST_P_2D_V4B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3416            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3417
3418 def : Pat<(int_nvvm_sust_p_2d_v4i32_trap
3419            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3420            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3421           (SUST_P_2D_V4B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3422            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3423
3424
3425
3426 def : Pat<(int_nvvm_sust_p_2d_array_i8_trap
3427           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3428           (SUST_P_2D_ARRAY_B8_TRAP Int64Regs:$s,
3429            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3430            Int16Regs:$r)>;
3431
3432 def : Pat<(int_nvvm_sust_p_2d_array_i16_trap
3433           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3434           (SUST_P_2D_ARRAY_B16_TRAP Int64Regs:$s,
3435            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3436            Int16Regs:$r)>;
3437
3438 def : Pat<(int_nvvm_sust_p_2d_array_i32_trap
3439           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
3440           (SUST_P_2D_ARRAY_B32_TRAP Int64Regs:$s,
3441            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3442            Int32Regs:$r)>;
3443
3444 def : Pat<(int_nvvm_sust_p_2d_array_v2i8_trap
3445            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3446            Int16Regs:$r, Int16Regs:$g),
3447           (SUST_P_2D_ARRAY_V2B8_TRAP Int64Regs:$s, Int32Regs:$l,
3448            Int32Regs:$x, Int32Regs:$y,
3449            Int16Regs:$r, Int16Regs:$g)>;
3450
3451 def : Pat<(int_nvvm_sust_p_2d_array_v2i16_trap
3452            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3453            Int16Regs:$r, Int16Regs:$g),
3454           (SUST_P_2D_ARRAY_V2B16_TRAP Int64Regs:$s, Int32Regs:$l,
3455            Int32Regs:$x, Int32Regs:$y,
3456            Int16Regs:$r, Int16Regs:$g)>;
3457
3458 def : Pat<(int_nvvm_sust_p_2d_array_v2i32_trap
3459            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
3460            Int32Regs:$g),
3461           (SUST_P_2D_ARRAY_V2B32_TRAP Int64Regs:$s, Int32Regs:$l,
3462            Int32Regs:$x, Int32Regs:$y, Int32Regs:$r, Int32Regs:$g)>;
3463
3464 def : Pat<(int_nvvm_sust_p_2d_array_v4i8_trap
3465            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3466            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3467           (SUST_P_2D_ARRAY_V4B8_TRAP Int64Regs:$s,
3468            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3469            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3470
3471 def : Pat<(int_nvvm_sust_p_2d_array_v4i16_trap
3472            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3473            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3474           (SUST_P_2D_ARRAY_V4B16_TRAP Int64Regs:$s,
3475            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3476            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3477
3478 def : Pat<(int_nvvm_sust_p_2d_array_v4i32_trap
3479            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3480            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3481           (SUST_P_2D_ARRAY_V4B32_TRAP Int64Regs:$s, Int32Regs:$l,
3482            Int32Regs:$x, Int32Regs:$y,
3483            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3484
3485
3486
3487 def : Pat<(int_nvvm_sust_p_3d_i8_trap
3488            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3489            Int16Regs:$r),
3490           (SUST_P_3D_B8_TRAP Int64Regs:$s,
3491            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3492            Int16Regs:$r)>;
3493
3494 def : Pat<(int_nvvm_sust_p_3d_i16_trap
3495            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3496            Int16Regs:$r),
3497           (SUST_P_3D_B16_TRAP Int64Regs:$s,
3498            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3499            Int16Regs:$r)>;
3500
3501 def : Pat<(int_nvvm_sust_p_3d_i32_trap
3502            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3503            Int32Regs:$r),
3504           (SUST_P_3D_B32_TRAP Int64Regs:$s,
3505            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3506            Int32Regs:$r)>;
3507
3508 def : Pat<(int_nvvm_sust_p_3d_v2i8_trap
3509            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3510            Int16Regs:$r, Int16Regs:$g),
3511           (SUST_P_3D_V2B8_TRAP Int64Regs:$s,
3512            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3513            Int16Regs:$r, Int16Regs:$g)>;
3514
3515 def : Pat<(int_nvvm_sust_p_3d_v2i16_trap
3516            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3517            Int16Regs:$r, Int16Regs:$g),
3518           (SUST_P_3D_V2B16_TRAP Int64Regs:$s,
3519            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3520            Int16Regs:$r, Int16Regs:$g)>;
3521
3522 def : Pat<(int_nvvm_sust_p_3d_v2i32_trap
3523            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3524            Int32Regs:$r, Int32Regs:$g),
3525           (SUST_P_3D_V2B32_TRAP Int64Regs:$s,
3526            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3527            Int32Regs:$r, Int32Regs:$g)>;
3528
3529 def : Pat<(int_nvvm_sust_p_3d_v4i8_trap
3530            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3531            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3532           (SUST_P_3D_V4B8_TRAP Int64Regs:$s,
3533            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3534            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3535
3536 def : Pat<(int_nvvm_sust_p_3d_v4i16_trap
3537            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3538            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3539           (SUST_P_3D_V4B16_TRAP Int64Regs:$s,
3540            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3541            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3542
3543 def : Pat<(int_nvvm_sust_p_3d_v4i32_trap
3544            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3545            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3546           (SUST_P_3D_V4B32_TRAP Int64Regs:$s,
3547            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3548            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3549
3550
3551
3552 //===-- Old PTX Back-end Intrinsics ---------------------------------------===//
3553
3554 // These intrinsics are handled to retain compatibility with the old backend.
3555
3556 // PTX Special Purpose Register Accessor Intrinsics
3557
3558 class PTX_READ_SPECIAL_REGISTER_R64<string regname, Intrinsic intop>
3559   : NVPTXInst<(outs Int64Regs:$d), (ins),
3560               !strconcat(!strconcat("mov.u64\t$d, %", regname), ";"),
3561               [(set Int64Regs:$d, (intop))]>;
3562
3563 class PTX_READ_SPECIAL_REGISTER_R32<string regname, Intrinsic intop>
3564   : NVPTXInst<(outs Int32Regs:$d), (ins),
3565               !strconcat(!strconcat("mov.u32\t$d, %", regname), ";"),
3566               [(set Int32Regs:$d, (intop))]>;
3567
3568 // TODO Add read vector-version of special registers
3569
3570 def PTX_READ_TID_X   : PTX_READ_SPECIAL_REGISTER_R32<"tid.x",
3571                                                      int_ptx_read_tid_x>;
3572 def PTX_READ_TID_Y   : PTX_READ_SPECIAL_REGISTER_R32<"tid.y",
3573                                                      int_ptx_read_tid_y>;
3574 def PTX_READ_TID_Z   : PTX_READ_SPECIAL_REGISTER_R32<"tid.z",
3575                                                      int_ptx_read_tid_z>;
3576 def PTX_READ_TID_W   : PTX_READ_SPECIAL_REGISTER_R32<"tid.w",
3577                                                      int_ptx_read_tid_w>;
3578
3579 def PTX_READ_NTID_X   : PTX_READ_SPECIAL_REGISTER_R32<"ntid.x",
3580                                                       int_ptx_read_ntid_x>;
3581 def PTX_READ_NTID_Y   : PTX_READ_SPECIAL_REGISTER_R32<"ntid.y",
3582                                                       int_ptx_read_ntid_y>;
3583 def PTX_READ_NTID_Z   : PTX_READ_SPECIAL_REGISTER_R32<"ntid.z",
3584                                                       int_ptx_read_ntid_z>;
3585 def PTX_READ_NTID_W   : PTX_READ_SPECIAL_REGISTER_R32<"ntid.w",
3586                                                       int_ptx_read_ntid_w>;
3587
3588 def PTX_READ_LANEID  : PTX_READ_SPECIAL_REGISTER_R32<"laneid",
3589                                                      int_ptx_read_laneid>;
3590 def PTX_READ_WARPID  : PTX_READ_SPECIAL_REGISTER_R32<"warpid",
3591                                                      int_ptx_read_warpid>;
3592 def PTX_READ_NWARPID : PTX_READ_SPECIAL_REGISTER_R32<"nwarpid",
3593                                                      int_ptx_read_nwarpid>;
3594
3595 def PTX_READ_CTAID_X   : PTX_READ_SPECIAL_REGISTER_R32<"ctaid.x",
3596                                                        int_ptx_read_ctaid_x>;
3597 def PTX_READ_CTAID_Y   : PTX_READ_SPECIAL_REGISTER_R32<"ctaid.y",
3598                                                        int_ptx_read_ctaid_y>;
3599 def PTX_READ_CTAID_Z   : PTX_READ_SPECIAL_REGISTER_R32<"ctaid.z",
3600                                                        int_ptx_read_ctaid_z>;
3601 def PTX_READ_CTAID_W   : PTX_READ_SPECIAL_REGISTER_R32<"ctaid.w",
3602                                                        int_ptx_read_ctaid_w>;
3603
3604 def PTX_READ_NCTAID_X   : PTX_READ_SPECIAL_REGISTER_R32<"nctaid.x",
3605                                                         int_ptx_read_nctaid_x>;
3606 def PTX_READ_NCTAID_Y   : PTX_READ_SPECIAL_REGISTER_R32<"nctaid.y",
3607                                                         int_ptx_read_nctaid_y>;
3608 def PTX_READ_NCTAID_Z   : PTX_READ_SPECIAL_REGISTER_R32<"nctaid.z",
3609                                                         int_ptx_read_nctaid_z>;
3610 def PTX_READ_NCTAID_W   : PTX_READ_SPECIAL_REGISTER_R32<"nctaid.w",
3611                                                         int_ptx_read_nctaid_w>;
3612
3613 def PTX_READ_SMID  : PTX_READ_SPECIAL_REGISTER_R32<"smid",
3614                                                    int_ptx_read_smid>;
3615 def PTX_READ_NSMID  : PTX_READ_SPECIAL_REGISTER_R32<"nsmid",
3616                                                     int_ptx_read_nsmid>;
3617 def PTX_READ_GRIDID  : PTX_READ_SPECIAL_REGISTER_R32<"gridid",
3618                                                      int_ptx_read_gridid>;
3619
3620 def PTX_READ_LANEMASK_EQ
3621   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_eq", int_ptx_read_lanemask_eq>;
3622 def PTX_READ_LANEMASK_LE
3623   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_le", int_ptx_read_lanemask_le>;
3624 def PTX_READ_LANEMASK_LT
3625   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_lt", int_ptx_read_lanemask_lt>;
3626 def PTX_READ_LANEMASK_GE
3627   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_ge", int_ptx_read_lanemask_ge>;
3628 def PTX_READ_LANEMASK_GT
3629   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_gt", int_ptx_read_lanemask_gt>;
3630
3631 def PTX_READ_CLOCK
3632   : PTX_READ_SPECIAL_REGISTER_R32<"clock", int_ptx_read_clock>;
3633 def PTX_READ_CLOCK64
3634   : PTX_READ_SPECIAL_REGISTER_R64<"clock64", int_ptx_read_clock64>;
3635
3636 def PTX_READ_PM0 : PTX_READ_SPECIAL_REGISTER_R32<"pm0", int_ptx_read_pm0>;
3637 def PTX_READ_PM1 : PTX_READ_SPECIAL_REGISTER_R32<"pm1", int_ptx_read_pm1>;
3638 def PTX_READ_PM2 : PTX_READ_SPECIAL_REGISTER_R32<"pm2", int_ptx_read_pm2>;
3639 def PTX_READ_PM3 : PTX_READ_SPECIAL_REGISTER_R32<"pm3", int_ptx_read_pm3>;
3640
3641 // PTX Parallel Synchronization and Communication Intrinsics
3642
3643 def PTX_BAR_SYNC : NVPTXInst<(outs), (ins i32imm:$i), "bar.sync\t$i;",
3644                              [(int_ptx_bar_sync imm:$i)]>;