1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16HardFloat.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "Mips16ISelLowering.h"
20 #include "Mips16InstrInfo.h"
21 #include "MipsFrameLowering.h"
22 #include "MipsInstrInfo.h"
23 #include "MipsModuleISelDAGToDAG.h"
25 #include "MipsSEFrameLowering.h"
26 #include "MipsSEISelDAGToDAG.h"
27 #include "MipsSEISelLowering.h"
28 #include "MipsSEInstrInfo.h"
29 #include "llvm/Analysis/TargetTransformInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/PassManager.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Transforms/Scalar.h"
38 #define DEBUG_TYPE "mips"
40 extern "C" void LLVMInitializeMipsTarget() {
41 // Register the target.
42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
48 // On function prologue, the stack is created by decrementing
49 // its pointer. Once decremented, all references are done with positive
50 // offset from the stack/frame pointer, using StackGrowsUp enables
51 // an easier handling.
52 // Using CodeModel::Large enables different CALL behavior.
53 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
54 StringRef CPU, StringRef FS,
55 const TargetOptions &Options,
56 Reloc::Model RM, CodeModel::Model CM,
57 CodeGenOpt::Level OL, bool isLittle)
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 Subtarget(TT, CPU, FS, isLittle, RM, this),
60 InstrInfo(MipsInstrInfo::create(*this)),
61 FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
62 TLInfo(MipsTargetLowering::create(*this)) {
67 void MipsTargetMachine::setHelperClassesMips16() {
68 InstrInfoSE.swap(InstrInfo);
69 FrameLoweringSE.swap(FrameLowering);
70 TLInfoSE.swap(TLInfo);
72 InstrInfo.reset(MipsInstrInfo::create(*this));
73 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
74 TLInfo.reset(MipsTargetLowering::create(*this));
76 InstrInfo16.swap(InstrInfo);
77 FrameLowering16.swap(FrameLowering);
78 TLInfo16.swap(TLInfo);
80 assert(TLInfo && "null target lowering 16");
81 assert(InstrInfo && "null instr info 16");
82 assert(FrameLowering && "null frame lowering 16");
85 void MipsTargetMachine::setHelperClassesMipsSE() {
86 InstrInfo16.swap(InstrInfo);
87 FrameLowering16.swap(FrameLowering);
88 TLInfo16.swap(TLInfo);
90 InstrInfo.reset(MipsInstrInfo::create(*this));
91 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
92 TLInfo.reset(MipsTargetLowering::create(*this));
94 InstrInfoSE.swap(InstrInfo);
95 FrameLoweringSE.swap(FrameLowering);
96 TLInfoSE.swap(TLInfo);
98 assert(TLInfo && "null target lowering in SE");
99 assert(InstrInfo && "null instr info SE");
100 assert(FrameLowering && "null frame lowering SE");
102 void MipsebTargetMachine::anchor() { }
104 MipsebTargetMachine::
105 MipsebTargetMachine(const Target &T, StringRef TT,
106 StringRef CPU, StringRef FS, const TargetOptions &Options,
107 Reloc::Model RM, CodeModel::Model CM,
108 CodeGenOpt::Level OL)
109 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
111 void MipselTargetMachine::anchor() { }
113 MipselTargetMachine::
114 MipselTargetMachine(const Target &T, StringRef TT,
115 StringRef CPU, StringRef FS, const TargetOptions &Options,
116 Reloc::Model RM, CodeModel::Model CM,
117 CodeGenOpt::Level OL)
118 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
121 /// Mips Code Generator Pass Configuration Options.
122 class MipsPassConfig : public TargetPassConfig {
124 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
125 : TargetPassConfig(TM, PM) {
126 // The current implementation of long branch pass requires a scratch
127 // register ($at) to be available before branch instructions. Tail merging
128 // can break this requirement, so disable it when long branch pass is
130 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
133 MipsTargetMachine &getMipsTargetMachine() const {
134 return getTM<MipsTargetMachine>();
137 const MipsSubtarget &getMipsSubtarget() const {
138 return *getMipsTargetMachine().getSubtargetImpl();
141 void addIRPasses() override;
142 bool addInstSelector() override;
143 void addMachineSSAOptimization() override;
144 bool addPreEmitPass() override;
146 bool addPreRegAlloc() override;
151 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
152 return new MipsPassConfig(this, PM);
155 void MipsPassConfig::addIRPasses() {
156 TargetPassConfig::addIRPasses();
157 if (getMipsSubtarget().os16())
158 addPass(createMipsOs16(getMipsTargetMachine()));
159 if (getMipsSubtarget().inMips16HardFloat())
160 addPass(createMips16HardFloat(getMipsTargetMachine()));
161 addPass(createPartiallyInlineLibCallsPass());
163 // Install an instruction selector pass using
164 // the ISelDag to gen Mips code.
165 bool MipsPassConfig::addInstSelector() {
166 if (getMipsSubtarget().allowMixed16_32()) {
167 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
168 addPass(createMips16ISelDag(getMipsTargetMachine()));
169 addPass(createMipsSEISelDag(getMipsTargetMachine()));
171 addPass(createMipsISelDag(getMipsTargetMachine()));
176 void MipsPassConfig::addMachineSSAOptimization() {
177 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
178 TargetPassConfig::addMachineSSAOptimization();
181 bool MipsPassConfig::addPreRegAlloc() {
182 if (getOptLevel() == CodeGenOpt::None) {
183 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
190 void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
191 if (Subtarget.allowMixed16_32()) {
192 DEBUG(errs() << "No ");
193 //FIXME: The Basic Target Transform Info
194 // pass needs to become a function pass instead of
195 // being an immutable pass and then this method as it exists now
196 // would be unnecessary.
197 PM.add(createNoTargetTransformInfoPass());
199 LLVMTargetMachine::addAnalysisPasses(PM);
200 DEBUG(errs() << "Target Transform Info Pass Added\n");
203 // Implemented by targets that want to run passes immediately before
204 // machine code is emitted. return true if -print-machineinstrs should
205 // print out the code after the passes.
206 bool MipsPassConfig::addPreEmitPass() {
207 MipsTargetMachine &TM = getMipsTargetMachine();
208 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
209 addPass(createMipsDelaySlotFillerPass(TM));
211 if (Subtarget.enableLongBranchPass())
212 addPass(createMipsLongBranchPass(TM));
213 if (Subtarget.inMips16Mode() ||
214 Subtarget.allowMixed16_32())
215 addPass(createMipsConstantIslandPass(TM));
220 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
221 JITCodeEmitter &JCE) {
222 // Machine code emitter pass for Mips.
223 PM.add(createMipsJITCodeEmitterPass(*this, JCE));