1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
36 static cl::opt<bool> Mixed16_32(
39 cl::desc("Allow for a mixture of Mips16 "
40 "and Mips32 code in a single source file"),
43 static cl::opt<bool> Mips_Os16(
46 cl::desc("Compile all functions that don' use "
47 "floating point as Mips 16"),
51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
52 cl::desc("MIPS: mips16 hard float enable."),
56 Mips16ConstantIslands(
57 "mips16-constant-islands", cl::NotHidden,
58 cl::desc("MIPS: mips16 constant islands enable."),
62 GPOpt("mgpopt", cl::Hidden,
63 cl::desc("MIPS: Enable gp-relative addressing of small data items"));
65 void MipsSubtarget::anchor() { }
67 static std::string computeDataLayout(const MipsSubtarget &ST) {
70 // There are both little and big endian mips.
78 // Pointers are 32 bit on some ABIs.
82 // 8 and 16 bit integers only need no have natural alignment, but try to
83 // align them to 32 bits. 64 bit integers have natural alignment.
84 Ret += "-i8:8:32-i16:16:32-i64:64";
86 // 32 bit registers are always available and the stack is at least 64 bit
87 // aligned. On N64 64 bit registers are also available and the stack is
89 if (ST.isABI_N64() || ST.isABI_N32())
90 Ret += "-n32:64-S128";
97 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
98 const std::string &FS, bool little,
99 const MipsTargetMachine &TM)
100 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
101 IsLittle(little), IsSingleFloat(false), IsFPXX(false), NoABICalls(false),
102 IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
103 IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasMips3_32(false),
104 HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false),
105 HasMips5_32r2(false), InMips16Mode(false),
106 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
107 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
108 HasMSA(false), TM(TM), TargetTriple(TT),
109 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
110 TSInfo(DL), InstrInfo(MipsInstrInfo::create(*this)),
111 FrameLowering(MipsFrameLowering::create(*this)),
112 TLInfo(MipsTargetLowering::create(TM, *this)) {
114 PreviousInMips16Mode = InMips16Mode;
116 if (MipsArchVersion == MipsDefault)
117 MipsArchVersion = Mips32;
119 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
120 // been tested and currently exist for the integrated assembler only.
121 if (MipsArchVersion == Mips1)
122 report_fatal_error("Code generation for MIPS-I is not implemented", false);
123 if (MipsArchVersion == Mips5)
124 report_fatal_error("Code generation for MIPS-V is not implemented", false);
126 // Check if Architecture and ABI are compatible.
127 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
128 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
129 "Invalid Arch & ABI pair.");
131 if (hasMSA() && !isFP64bit())
132 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
136 if (!isABI_O32() && !useOddSPReg())
137 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
139 if (IsFPXX && (isABI_N32() || isABI_N64()))
140 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
143 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
148 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
151 if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
152 report_fatal_error("position-independent code requires '-mabicalls'");
154 // Set UseSmallSection.
155 UseSmallSection = GPOpt;
156 if (!NoABICalls && GPOpt) {
157 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
159 UseSmallSection = false;
163 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
164 bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
166 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
167 CriticalPathRCs.clear();
168 CriticalPathRCs.push_back(isGP64bit() ?
169 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
172 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
173 return CodeGenOpt::Aggressive;
176 /// Select the Mips CPU for the given triple and cpu name.
177 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
178 static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
179 if (CPU.empty() || CPU == "generic") {
180 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
189 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
190 const TargetMachine &TM) {
191 std::string CPUName = selectMipsCPU(TargetTriple, CPU);
193 // Parse features string.
194 ParseSubtargetFeatures(CPUName, FS);
195 // Initialize scheduling itinerary for the specified CPU.
196 InstrItins = getInstrItineraryForCPU(CPUName);
198 if (InMips16Mode && !TM.Options.UseSoftFloat)
199 InMips16HardFloat = true;
204 bool MipsSubtarget::abiUsesSoftFloat() const {
205 return TM.Options.UseSoftFloat && !InMips16HardFloat;
208 bool MipsSubtarget::useConstantIslands() {
209 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
210 return Mips16ConstantIslands;
213 Reloc::Model MipsSubtarget::getRelocationModel() const {
214 return TM.getRelocationModel();
217 bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); }
218 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
219 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
220 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
221 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }