1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
170 AssemblerPredicate<"FeatureGP64Bit">;
171 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
172 AssemblerPredicate<"!FeatureGP64Bit">;
173 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
174 AssemblerPredicate<"FeatureMips64">;
175 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
176 AssemblerPredicate<"FeatureMips64r2">;
177 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
178 AssemblerPredicate<"FeatureMips64r6">;
179 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
180 AssemblerPredicate<"FeatureN64">;
181 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
182 AssemblerPredicate<"FeatureMips16">;
183 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
184 AssemblerPredicate<"FeatureCnMips">;
185 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
186 AssemblerPredicate<"FeatureMips32">;
187 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
188 AssemblerPredicate<"FeatureMips32">;
189 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
190 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
191 AssemblerPredicate<"!FeatureMips16">;
192 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
193 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
194 AssemblerPredicate<"FeatureMicroMips">;
195 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
196 AssemblerPredicate<"!FeatureMicroMips">;
197 def IsLE : Predicate<"Subtarget.isLittle()">;
198 def IsBE : Predicate<"!Subtarget.isLittle()">;
199 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
201 //===----------------------------------------------------------------------===//
202 // Mips GPR size adjectives.
203 // They are mutually exclusive.
204 //===----------------------------------------------------------------------===//
206 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
207 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
209 //===----------------------------------------------------------------------===//
210 // Mips ISA/ASE membership and instruction group membership adjectives.
211 // They are mutually exclusive.
212 //===----------------------------------------------------------------------===//
214 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
215 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
216 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
217 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
218 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
219 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
220 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
221 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
223 // The portions of MIPS-III that were also added to MIPS32
224 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
226 // The portions of MIPS-III that were also added to MIPS32
227 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
229 // The portions of MIPS-IV that were also added to MIPS32
230 class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
232 // The portions of MIPS-IV that were also added to MIPS32R2
233 class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
235 // The portions of MIPS-V that were also added to MIPS32R2
236 class INSN_MIPS5_32R2 { list<Predicate> InsnPredicates = [HasMips5_32r2]; }
238 //===----------------------------------------------------------------------===//
240 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
241 let EncodingPredicates = [HasStdEnc];
244 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
245 InstAlias<Asm, Result, Emit>, PredicateControl;
248 bit isCommutable = 1;
265 bit isTerminator = 1;
268 bit hasExtraSrcRegAllocReq = 1;
269 bit isCodeGenOnly = 1;
272 class IsAsCheapAsAMove {
273 bit isAsCheapAsAMove = 1;
276 class NeverHasSideEffects {
277 bit neverHasSideEffects = 1;
280 //===----------------------------------------------------------------------===//
281 // Instruction format superclass
282 //===----------------------------------------------------------------------===//
284 include "MipsInstrFormats.td"
286 //===----------------------------------------------------------------------===//
287 // Mips Operand, Complex Patterns and Transformations Definitions.
288 //===----------------------------------------------------------------------===//
290 def MipsJumpTargetAsmOperand : AsmOperandClass {
291 let Name = "JumpTarget";
292 let ParserMethod = "ParseJumpTarget";
293 let PredicateMethod = "isImm";
294 let RenderMethod = "addImmOperands";
297 // Instruction operand types
298 def jmptarget : Operand<OtherVT> {
299 let EncoderMethod = "getJumpTargetOpValue";
300 let ParserMatchClass = MipsJumpTargetAsmOperand;
302 def brtarget : Operand<OtherVT> {
303 let EncoderMethod = "getBranchTargetOpValue";
304 let OperandType = "OPERAND_PCREL";
305 let DecoderMethod = "DecodeBranchTarget";
306 let ParserMatchClass = MipsJumpTargetAsmOperand;
308 def calltarget : Operand<iPTR> {
309 let EncoderMethod = "getJumpTargetOpValue";
310 let ParserMatchClass = MipsJumpTargetAsmOperand;
313 def simm10 : Operand<i32>;
315 def simm16 : Operand<i32> {
316 let DecoderMethod= "DecodeSimm16";
319 def simm19_lsl2 : Operand<i32> {
320 let EncoderMethod = "getSimm19Lsl2Encoding";
321 let DecoderMethod = "DecodeSimm19Lsl2";
324 def simm20 : Operand<i32> {
327 def uimm20 : Operand<i32> {
330 def uimm10 : Operand<i32> {
333 def simm16_64 : Operand<i64> {
334 let DecoderMethod = "DecodeSimm16";
338 def uimmz : Operand<i32> {
339 let PrintMethod = "printUnsignedImm";
343 def uimm2 : Operand<i32> {
344 let PrintMethod = "printUnsignedImm";
347 def uimm3 : Operand<i32> {
348 let PrintMethod = "printUnsignedImm";
351 def uimm5 : Operand<i32> {
352 let PrintMethod = "printUnsignedImm";
355 def uimm6 : Operand<i32> {
356 let PrintMethod = "printUnsignedImm";
359 def uimm16 : Operand<i32> {
360 let PrintMethod = "printUnsignedImm";
363 def pcrel16 : Operand<i32> {
366 def MipsMemAsmOperand : AsmOperandClass {
368 let ParserMethod = "parseMemOperand";
371 def MipsInvertedImmoperand : AsmOperandClass {
373 let RenderMethod = "addImmOperands";
374 let ParserMethod = "parseInvNum";
377 def InvertedImOperand : Operand<i32> {
378 let ParserMatchClass = MipsInvertedImmoperand;
381 def InvertedImOperand64 : Operand<i64> {
382 let ParserMatchClass = MipsInvertedImmoperand;
385 class mem_generic : Operand<iPTR> {
386 let PrintMethod = "printMemOperand";
387 let MIOperandInfo = (ops ptr_rc, simm16);
388 let EncoderMethod = "getMemEncoding";
389 let ParserMatchClass = MipsMemAsmOperand;
390 let OperandType = "OPERAND_MEMORY";
394 def mem : mem_generic;
396 // MSA specific address operand
397 def mem_msa : mem_generic {
398 let MIOperandInfo = (ops ptr_rc, simm10);
399 let EncoderMethod = "getMSAMemEncoding";
402 def mem_ea : Operand<iPTR> {
403 let PrintMethod = "printMemOperandEA";
404 let MIOperandInfo = (ops ptr_rc, simm16);
405 let EncoderMethod = "getMemEncoding";
406 let OperandType = "OPERAND_MEMORY";
409 def PtrRC : Operand<iPTR> {
410 let MIOperandInfo = (ops ptr_rc);
411 let DecoderMethod = "DecodePtrRegisterClass";
412 let ParserMatchClass = GPR32AsmOperand;
415 // size operand of ext instruction
416 def size_ext : Operand<i32> {
417 let EncoderMethod = "getSizeExtEncoding";
418 let DecoderMethod = "DecodeExtSize";
421 // size operand of ins instruction
422 def size_ins : Operand<i32> {
423 let EncoderMethod = "getSizeInsEncoding";
424 let DecoderMethod = "DecodeInsSize";
427 // Transformation Function - get the lower 16 bits.
428 def LO16 : SDNodeXForm<imm, [{
429 return getImm(N, N->getZExtValue() & 0xFFFF);
432 // Transformation Function - get the higher 16 bits.
433 def HI16 : SDNodeXForm<imm, [{
434 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
438 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
440 // Node immediate is zero (e.g. insve.d)
441 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
443 // Node immediate fits as 16-bit sign extended on target immediate.
445 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
447 // Node immediate fits as 16-bit sign extended on target immediate.
449 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
451 // Node immediate fits as 15-bit sign extended on target immediate.
453 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
455 // Node immediate fits as 16-bit zero extended on target immediate.
456 // The LO16 param means that only the lower 16 bits of the node
457 // immediate are caught.
459 def immZExt16 : PatLeaf<(imm), [{
460 if (N->getValueType(0) == MVT::i32)
461 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
463 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
466 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
467 def immLow16Zero : PatLeaf<(imm), [{
468 int64_t Val = N->getSExtValue();
469 return isInt<32>(Val) && !(Val & 0xffff);
472 // shamt field must fit in 5 bits.
473 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
475 // True if (N + 1) fits in 16-bit field.
476 def immSExt16Plus1 : PatLeaf<(imm), [{
477 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
480 // Mips Address Mode! SDNode frameindex could possibily be a match
481 // since load and store instructions from stack used it.
483 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
486 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
489 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
492 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
494 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
496 //===----------------------------------------------------------------------===//
497 // Instructions specific format
498 //===----------------------------------------------------------------------===//
500 // Arithmetic and logical instructions with 3 register operands.
501 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
502 InstrItinClass Itin = NoItinerary,
503 SDPatternOperator OpNode = null_frag>:
504 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
505 !strconcat(opstr, "\t$rd, $rs, $rt"),
506 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
507 let isCommutable = isComm;
508 let isReMaterializable = 1;
509 let TwoOperandAliasConstraint = "$rd = $rs";
512 // Arithmetic and logical instructions with 2 register operands.
513 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
514 InstrItinClass Itin = NoItinerary,
515 SDPatternOperator imm_type = null_frag,
516 SDPatternOperator OpNode = null_frag> :
517 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
518 !strconcat(opstr, "\t$rt, $rs, $imm16"),
519 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
521 let isReMaterializable = 1;
522 let TwoOperandAliasConstraint = "$rs = $rt";
525 // Arithmetic Multiply ADD/SUB
526 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
527 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
528 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
529 let Defs = [HI0, LO0];
530 let Uses = [HI0, LO0];
531 let isCommutable = isComm;
535 class LogicNOR<string opstr, RegisterOperand RO>:
536 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
537 !strconcat(opstr, "\t$rd, $rs, $rt"),
538 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
539 let isCommutable = 1;
543 class shift_rotate_imm<string opstr, Operand ImmOpnd,
544 RegisterOperand RO, InstrItinClass itin,
545 SDPatternOperator OpNode = null_frag,
546 SDPatternOperator PF = null_frag> :
547 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
548 !strconcat(opstr, "\t$rd, $rt, $shamt"),
549 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
550 let TwoOperandAliasConstraint = "$rt = $rd";
553 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
554 SDPatternOperator OpNode = null_frag>:
555 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
556 !strconcat(opstr, "\t$rd, $rt, $rs"),
557 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
560 // Load Upper Imediate
561 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
562 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
563 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
564 let neverHasSideEffects = 1;
565 let isReMaterializable = 1;
569 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
570 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
571 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
572 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
573 let DecoderMethod = "DecodeMem";
574 let canFoldAsLoad = 1;
578 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
579 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
580 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
581 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
582 let DecoderMethod = "DecodeMem";
586 // Load/Store Left/Right
587 let canFoldAsLoad = 1 in
588 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
589 InstrItinClass Itin> :
590 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
591 !strconcat(opstr, "\t$rt, $addr"),
592 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
593 let DecoderMethod = "DecodeMem";
594 string Constraints = "$src = $rt";
597 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
598 InstrItinClass Itin> :
599 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
600 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
601 let DecoderMethod = "DecodeMem";
604 // Conditional Branch
605 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
606 RegisterOperand RO> :
607 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
608 !strconcat(opstr, "\t$rs, $rt, $offset"),
609 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
612 let isTerminator = 1;
613 let hasDelaySlot = 1;
617 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
618 RegisterOperand RO> :
619 InstSE<(outs), (ins RO:$rs, opnd:$offset),
620 !strconcat(opstr, "\t$rs, $offset"),
621 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
624 let isTerminator = 1;
625 let hasDelaySlot = 1;
630 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
631 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
632 !strconcat(opstr, "\t$rd, $rs, $rt"),
633 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
634 II_SLT_SLTU, FrmR, opstr>;
636 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
638 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
639 !strconcat(opstr, "\t$rt, $rs, $imm16"),
640 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
641 II_SLTI_SLTIU, FrmI, opstr>;
644 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
645 SDPatternOperator targetoperator, string bopstr> :
646 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
647 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
650 let hasDelaySlot = 1;
651 let DecoderMethod = "DecodeJumpTarget";
655 // Unconditional branch
656 class UncondBranch<Instruction BEQInst> :
657 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
658 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
660 let isTerminator = 1;
662 let hasDelaySlot = 1;
663 let AdditionalPredicates = [RelocPIC];
667 // Base class for indirect branch and return instruction classes.
668 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
669 class JumpFR<string opstr, RegisterOperand RO,
670 SDPatternOperator operator = null_frag>:
671 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
675 class IndirectBranch<string opstr, RegisterOperand RO> :
676 JumpFR<opstr, RO, brind> {
678 let isIndirectBranch = 1;
681 // Return instruction
682 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
684 let isCodeGenOnly = 1;
686 let hasExtraSrcRegAllocReq = 1;
689 // Jump and Link (Call)
690 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
691 class JumpLink<string opstr, DAGOperand opnd> :
692 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
693 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
694 let DecoderMethod = "DecodeJumpTarget";
697 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
698 Register RetReg, RegisterOperand ResRO = RO>:
699 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
700 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
702 class JumpLinkReg<string opstr, RegisterOperand RO>:
703 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
706 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
707 InstSE<(outs), (ins RO:$rs, opnd:$offset),
708 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
712 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
713 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
714 class TailCall<Instruction JumpInst> :
715 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
716 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
718 class TailCallReg<RegisterOperand RO, Instruction JRInst,
719 RegisterOperand ResRO = RO> :
720 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
721 PseudoInstExpansion<(JRInst ResRO:$rs)>;
724 class BAL_BR_Pseudo<Instruction RealInst> :
725 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
726 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
728 let isTerminator = 1;
730 let hasDelaySlot = 1;
735 class SYS_FT<string opstr> :
736 InstSE<(outs), (ins uimm20:$code_),
737 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
739 class BRK_FT<string opstr> :
740 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
741 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
745 class ER_FT<string opstr> :
746 InstSE<(outs), (ins),
747 opstr, [], NoItinerary, FrmOther, opstr>;
750 class DEI_FT<string opstr, RegisterOperand RO> :
751 InstSE<(outs RO:$rt), (ins),
752 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
755 class WAIT_FT<string opstr> :
756 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
759 let hasSideEffects = 1 in
760 class SYNC_FT<string opstr> :
761 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
762 NoItinerary, FrmOther, opstr>;
764 let hasSideEffects = 1 in
765 class TEQ_FT<string opstr, RegisterOperand RO> :
766 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
767 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
770 class TEQI_FT<string opstr, RegisterOperand RO> :
771 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
772 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
774 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
775 list<Register> DefRegs> :
776 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
778 let isCommutable = 1;
780 let neverHasSideEffects = 1;
783 // Pseudo multiply/divide instruction with explicit accumulator register
785 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
786 SDPatternOperator OpNode, InstrItinClass Itin,
787 bit IsComm = 1, bit HasSideEffects = 0,
788 bit UsesCustomInserter = 0> :
789 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
790 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
791 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
792 let isCommutable = IsComm;
793 let hasSideEffects = HasSideEffects;
794 let usesCustomInserter = UsesCustomInserter;
797 // Pseudo multiply add/sub instruction with explicit accumulator register
799 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
801 : PseudoSE<(outs ACC64:$ac),
802 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
804 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
806 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
807 string Constraints = "$acin = $ac";
810 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
811 list<Register> DefRegs> :
812 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
813 [], itin, FrmR, opstr> {
818 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
819 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
820 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
822 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
823 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
826 let neverHasSideEffects = 1;
829 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
830 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
831 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
834 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
835 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
838 let neverHasSideEffects = 1;
841 class EffectiveAddress<string opstr, RegisterOperand RO> :
842 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
843 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
844 !strconcat(opstr, "_lea")> {
845 let isCodeGenOnly = 1;
846 let DecoderMethod = "DecodeMem";
849 // Count Leading Ones/Zeros in Word
850 class CountLeading0<string opstr, RegisterOperand RO>:
851 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
852 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
854 class CountLeading1<string opstr, RegisterOperand RO>:
855 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
856 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
858 // Sign Extend in Register.
859 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
860 InstrItinClass itin> :
861 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
862 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
865 class SubwordSwap<string opstr, RegisterOperand RO>:
866 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
867 NoItinerary, FrmR, opstr> {
868 let neverHasSideEffects = 1;
872 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
873 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
877 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
878 SDPatternOperator Op = null_frag>:
879 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
880 !strconcat(opstr, " $rt, $rs, $pos, $size"),
881 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
882 FrmR, opstr>, ISA_MIPS32R2;
884 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
885 SDPatternOperator Op = null_frag>:
886 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
887 !strconcat(opstr, " $rt, $rs, $pos, $size"),
888 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
889 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
890 let Constraints = "$src = $rt";
893 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
894 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
895 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
896 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
898 // Atomic Compare & Swap.
899 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
900 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
901 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
903 class LLBase<string opstr, RegisterOperand RO> :
904 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
905 [], NoItinerary, FrmI> {
906 let DecoderMethod = "DecodeMem";
910 class SCBase<string opstr, RegisterOperand RO> :
911 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
912 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
913 let DecoderMethod = "DecodeMem";
915 let Constraints = "$rt = $dst";
918 class MFC3OP<string asmstr, RegisterOperand RO> :
919 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
920 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
922 class TrapBase<Instruction RealInst>
923 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
924 PseudoInstExpansion<(RealInst 0, 0)> {
926 let isTerminator = 1;
927 let isCodeGenOnly = 1;
930 //===----------------------------------------------------------------------===//
931 // Pseudo instructions
932 //===----------------------------------------------------------------------===//
935 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
936 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
938 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
939 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
940 [(callseq_start timm:$amt)]>;
941 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
942 [(callseq_end timm:$amt1, timm:$amt2)]>;
945 let usesCustomInserter = 1 in {
946 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
947 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
948 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
949 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
950 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
951 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
952 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
953 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
954 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
955 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
956 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
957 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
958 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
959 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
960 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
961 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
962 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
963 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
965 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
966 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
967 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
969 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
970 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
971 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
974 /// Pseudo instructions for loading and storing accumulator registers.
975 let isPseudo = 1, isCodeGenOnly = 1 in {
976 def LOAD_ACC64 : Load<"", ACC64>;
977 def STORE_ACC64 : Store<"", ACC64>;
980 // We need these two pseudo instructions to avoid offset calculation for long
981 // branches. See the comment in file MipsLongBranch.cpp for detailed
984 // Expands to: lui $dst, %hi($tgt - $baltgt)
985 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
986 (ins brtarget:$tgt, brtarget:$baltgt), []>;
988 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
989 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
990 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
992 //===----------------------------------------------------------------------===//
993 // Instruction definition
994 //===----------------------------------------------------------------------===//
995 //===----------------------------------------------------------------------===//
996 // MipsI Instructions
997 //===----------------------------------------------------------------------===//
999 /// Arithmetic Instructions (ALU Immediate)
1000 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1002 ADDI_FM<0x9>, IsAsCheapAsAMove;
1003 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
1004 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1006 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1008 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1011 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1014 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1017 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1019 /// Arithmetic Instructions (3-Operand, R-Type)
1020 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1022 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1024 let Defs = [HI0, LO0] in
1025 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1026 ADD_FM<0x1c, 2>, ISA_MIPS32;
1027 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1028 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1029 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1030 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1031 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1033 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1035 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1037 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1039 /// Shift Instructions
1040 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1041 immZExt5>, SRA_FM<0, 0>;
1042 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1043 immZExt5>, SRA_FM<2, 0>;
1044 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1045 immZExt5>, SRA_FM<3, 0>;
1046 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1048 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1050 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1053 // Rotate Instructions
1054 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1056 SRA_FM<2, 1>, ISA_MIPS32R2;
1057 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1058 SRLV_FM<6, 1>, ISA_MIPS32R2;
1060 /// Load and Store Instructions
1062 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1063 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1065 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1067 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1068 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1070 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1071 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1072 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1074 /// load/store left/right
1075 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1076 AdditionalPredicates = [NotInMicroMips] in {
1077 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1078 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1079 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1080 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1083 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1084 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1085 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1086 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1087 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1088 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1089 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1091 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, ISA_MIPS2;
1092 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, ISA_MIPS2;
1093 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, ISA_MIPS2;
1094 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, ISA_MIPS2;
1095 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, ISA_MIPS2;
1096 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, ISA_MIPS2;
1098 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1099 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1100 def TRAP : TrapBase<BREAK>;
1102 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1103 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1105 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1106 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1108 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1109 AdditionalPredicates = [NotInMicroMips] in {
1110 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1112 /// Load-linked, Store-conditional
1113 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1114 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1117 /// Jump and Branch Instructions
1118 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1119 AdditionalRequires<[RelocStatic]>, IsBranch;
1120 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1121 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1122 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1123 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1125 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1127 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1129 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1131 def B : UncondBranch<BEQ>;
1133 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1134 let AdditionalPredicates = [NotInMicroMips] in {
1135 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1136 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1138 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1139 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1140 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1141 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1142 def TAILCALL : TailCall<J>;
1143 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1145 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1147 // Exception handling related node and instructions.
1148 // The conversion sequence is:
1149 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1150 // MIPSeh_return -> (stack change + indirect branch)
1152 // MIPSeh_return takes the place of regular return instruction
1153 // but takes two arguments (V1, V0) which are used for storing
1154 // the offset and return address respectively.
1155 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1157 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1160 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1161 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1162 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1163 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1165 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1168 /// Multiply and Divide Instructions.
1169 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1171 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1173 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1175 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1178 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1179 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1180 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1181 AdditionalPredicates = [NotInMicroMips] in {
1182 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1183 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1186 /// Sign Ext In Register Instructions.
1187 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1188 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1189 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1190 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1193 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1194 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1196 /// Word Swap Bytes Within Halfwords
1197 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1200 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1202 // FrameIndexes are legalized when they are operands from load/store
1203 // instructions. The same not happens for stack address copies, so an
1204 // add op with mem ComplexPattern is used and the stack address copy
1205 // can be matched. It's similar to Sparc LEA_ADDRi
1206 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1209 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, ISA_MIPS32;
1210 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, ISA_MIPS32;
1211 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, ISA_MIPS32;
1212 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, ISA_MIPS32;
1214 let AdditionalPredicates = [NotDSP] in {
1215 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1216 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1217 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1218 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1219 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1220 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1221 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1222 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1223 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1226 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1228 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1231 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1233 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1234 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1236 /// Move Control Registers From/To CPU Registers
1237 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1238 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1239 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1240 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1242 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1244 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1245 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1246 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1248 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1250 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1251 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1252 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1253 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1255 //===----------------------------------------------------------------------===//
1256 // Instruction aliases
1257 //===----------------------------------------------------------------------===//
1258 def : MipsInstAlias<"move $dst, $src",
1259 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1261 let AdditionalPredicates = [NotInMicroMips];
1263 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1264 def : MipsInstAlias<"addu $rs, $rt, $imm",
1265 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1266 def : MipsInstAlias<"add $rs, $rt, $imm",
1267 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1268 def : MipsInstAlias<"and $rs, $rt, $imm",
1269 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1270 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1271 let Predicates = [NotInMicroMips] in {
1272 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1274 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1275 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1276 def : MipsInstAlias<"not $rt, $rs",
1277 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1278 def : MipsInstAlias<"neg $rt, $rs",
1279 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1280 def : MipsInstAlias<"negu $rt",
1281 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1282 def : MipsInstAlias<"negu $rt, $rs",
1283 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1284 def : MipsInstAlias<"slt $rs, $rt, $imm",
1285 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1286 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1287 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1288 def : MipsInstAlias<"xor $rs, $rt, $imm",
1289 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1290 def : MipsInstAlias<"or $rs, $rt, $imm",
1291 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1292 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1293 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1294 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1295 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1296 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1297 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1298 def : MipsInstAlias<"bnez $rs,$offset",
1299 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1300 def : MipsInstAlias<"beqz $rs,$offset",
1301 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1302 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1304 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1305 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1306 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1307 def : MipsInstAlias<"di", (DI ZERO), 1>;
1309 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1310 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1311 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1313 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1314 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1316 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1317 def : MipsInstAlias<"sll $rd, $rt, $rs",
1318 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1319 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1320 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1321 InvertedImOperand:$imm), 0>;
1322 def : MipsInstAlias<"sub $rs, $imm",
1323 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1325 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1326 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1327 InvertedImOperand:$imm), 0>;
1328 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1329 InvertedImOperand:$imm), 0>;
1330 def : MipsInstAlias<"sra $rd, $rt, $rs",
1331 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1332 def : MipsInstAlias<"srl $rd, $rt, $rs",
1333 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1334 //===----------------------------------------------------------------------===//
1335 // Assembler Pseudo Instructions
1336 //===----------------------------------------------------------------------===//
1338 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1339 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1340 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1341 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1343 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1344 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1345 !strconcat(instr_asm, "\t$rt, $addr")> ;
1346 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1348 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1349 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1350 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1351 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1353 //===----------------------------------------------------------------------===//
1354 // Arbitrary patterns that map to one or more instructions
1355 //===----------------------------------------------------------------------===//
1357 // Load/store pattern templates.
1358 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1359 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1361 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1362 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1365 def : MipsPat<(i32 immSExt16:$in),
1366 (ADDiu ZERO, imm:$in)>;
1367 def : MipsPat<(i32 immZExt16:$in),
1368 (ORi ZERO, imm:$in)>;
1369 def : MipsPat<(i32 immLow16Zero:$in),
1370 (LUi (HI16 imm:$in))>;
1372 // Arbitrary immediates
1373 def : MipsPat<(i32 imm:$imm),
1374 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1376 // Carry MipsPatterns
1377 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1378 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1379 let AdditionalPredicates = [NotDSP] in {
1380 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1381 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1382 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1383 (ADDiu GPR32:$src, imm:$imm)>;
1387 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1388 (JAL tglobaladdr:$dst)>;
1389 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1390 (JAL texternalsym:$dst)>;
1391 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1392 // (JALR GPR32:$dst)>;
1395 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1396 (TAILCALL tglobaladdr:$dst)>;
1397 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1398 (TAILCALL texternalsym:$dst)>;
1400 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1401 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1402 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1403 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1404 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1405 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1407 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1408 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1409 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1410 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1411 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1412 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1414 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1415 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1416 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1417 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1418 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1419 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1420 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1421 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1422 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1423 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1426 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1427 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1428 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1429 (ADDiu GPR32:$gp, tconstpool:$in)>;
1432 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1433 MipsPat<(MipsWrapper RC:$gp, node:$in),
1434 (ADDiuOp RC:$gp, node:$in)>;
1436 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1437 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1438 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1439 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1440 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1441 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1443 // Mips does not have "not", so we expand our way
1444 def : MipsPat<(not GPR32:$in),
1445 (NOR GPR32Opnd:$in, ZERO)>;
1448 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1449 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1450 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1453 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1456 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1457 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1458 Instruction SLTiuOp, Register ZEROReg> {
1459 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1460 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1461 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1462 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1464 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1465 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1466 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1467 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1468 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1469 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1470 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1471 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1472 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1473 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1474 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1475 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1477 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1478 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1479 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1480 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1482 def : MipsPat<(brcond RC:$cond, bb:$dst),
1483 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1486 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1488 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1489 (BLEZ i32:$lhs, bb:$dst)>;
1490 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1491 (BGEZ i32:$lhs, bb:$dst)>;
1494 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1495 Instruction SLTuOp, Register ZEROReg> {
1496 def : MipsPat<(seteq RC:$lhs, 0),
1497 (SLTiuOp RC:$lhs, 1)>;
1498 def : MipsPat<(setne RC:$lhs, 0),
1499 (SLTuOp ZEROReg, RC:$lhs)>;
1500 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1501 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1502 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1503 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1506 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1507 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1508 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1509 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1510 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1513 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1514 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1515 (SLTOp RC:$rhs, RC:$lhs)>;
1516 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1517 (SLTuOp RC:$rhs, RC:$lhs)>;
1520 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1521 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1522 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1523 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1524 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1527 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1528 Instruction SLTiuOp> {
1529 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1530 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1531 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1532 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1535 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1536 defm : SetlePats<GPR32, SLT, SLTu>;
1537 defm : SetgtPats<GPR32, SLT, SLTu>;
1538 defm : SetgePats<GPR32, SLT, SLTu>;
1539 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1542 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1544 // Load halfword/word patterns.
1545 let AddedComplexity = 40 in {
1546 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1547 def : LoadRegImmPat<LH, i32, sextloadi16>;
1548 def : LoadRegImmPat<LW, i32, load>;
1551 //===----------------------------------------------------------------------===//
1552 // Floating Point Support
1553 //===----------------------------------------------------------------------===//
1555 include "MipsInstrFPU.td"
1556 include "Mips64InstrInfo.td"
1557 include "MipsCondMov.td"
1559 include "Mips32r6InstrInfo.td"
1560 include "Mips64r6InstrInfo.td"
1565 include "Mips16InstrFormats.td"
1566 include "Mips16InstrInfo.td"
1569 include "MipsDSPInstrFormats.td"
1570 include "MipsDSPInstrInfo.td"
1573 include "MipsMSAInstrFormats.td"
1574 include "MipsMSAInstrInfo.td"
1577 include "MicroMipsInstrFormats.td"
1578 include "MicroMipsInstrInfo.td"
1579 include "MicroMipsInstrFPU.td"