1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
68 // Node used to extract integer from accumulator.
71 // Node used to insert integers to accumulator.
102 // EXTR.W instrinsic nodes.
112 // DPA.W intrinsic nodes.
148 // DSP setcc and select_cc nodes.
152 // Load/Store Left/Right nodes.
153 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
164 //===--------------------------------------------------------------------===//
165 // TargetLowering Implementation
166 //===--------------------------------------------------------------------===//
167 class MipsFunctionInfo;
169 class MipsTargetLowering : public TargetLowering {
171 explicit MipsTargetLowering(MipsTargetMachine &TM);
173 static const MipsTargetLowering *create(MipsTargetMachine &TM);
175 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
177 virtual void LowerOperationWrapper(SDNode *N,
178 SmallVectorImpl<SDValue> &Results,
179 SelectionDAG &DAG) const;
181 /// LowerOperation - Provide custom lowering hooks for some operations.
182 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
184 /// ReplaceNodeResults - Replace the results of node with an illegal result
185 /// type with new values built out of custom code.
187 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
188 SelectionDAG &DAG) const;
190 /// getTargetNodeName - This method returns the name of a target specific
192 virtual const char *getTargetNodeName(unsigned Opcode) const;
194 /// getSetCCResultType - get the ISD::SETCC result ValueType
195 EVT getSetCCResultType(EVT VT) const;
197 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
199 virtual MachineBasicBlock *
200 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
203 bool operator()(const char *S1, const char *S2) const {
204 return strcmp(S1, S2) < 0;
209 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
211 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
213 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
215 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
216 unsigned HiFlag, unsigned LoFlag) const;
218 /// This function fills Ops, which is the list of operands that will later
219 /// be used when a function call node is created. It also generates
220 /// copyToReg nodes to set up argument registers.
222 getOpndList(SmallVectorImpl<SDValue> &Ops,
223 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
224 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
225 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
227 /// ByValArgInfo - Byval argument information.
228 struct ByValArgInfo {
229 unsigned FirstIdx; // Index of the first register used.
230 unsigned NumRegs; // Number of registers used for this argument.
231 unsigned Address; // Offset of the stack area used to pass this argument.
233 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
236 /// MipsCC - This class provides methods used to analyze formal and call
237 /// arguments and inquire about calling convention information.
240 enum SpecialCallingConvType {
241 Mips16RetHelperConv, NoSpecialCallingConv
245 CallingConv::ID CallConv, bool IsO32, CCState &Info,
246 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
249 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
250 bool IsVarArg, bool IsSoftFloat,
251 const SDNode *CallNode,
252 std::vector<ArgListEntry> &FuncArgs);
253 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
255 Function::const_arg_iterator FuncArg);
257 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
258 bool IsSoftFloat, const SDNode *CallNode,
259 const Type *RetTy) const;
261 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
262 bool IsSoftFloat, const Type *RetTy) const;
264 const CCState &getCCInfo() const { return CCInfo; }
266 /// hasByValArg - Returns true if function has byval arguments.
267 bool hasByValArg() const { return !ByValArgs.empty(); }
269 /// regSize - Size (in number of bits) of integer registers.
270 unsigned regSize() const { return IsO32 ? 4 : 8; }
272 /// numIntArgRegs - Number of integer registers available for calls.
273 unsigned numIntArgRegs() const;
275 /// reservedArgArea - The size of the area the caller reserves for
276 /// register arguments. This is 16-byte if ABI is O32.
277 unsigned reservedArgArea() const;
279 /// Return pointer to array of integer argument registers.
280 const uint16_t *intArgRegs() const;
282 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
283 byval_iterator byval_begin() const { return ByValArgs.begin(); }
284 byval_iterator byval_end() const { return ByValArgs.end(); }
287 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
288 CCValAssign::LocInfo LocInfo,
289 ISD::ArgFlagsTy ArgFlags);
291 /// useRegsForByval - Returns true if the calling convention allows the
292 /// use of registers to pass byval arguments.
293 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
295 /// Return the function that analyzes fixed argument list functions.
296 llvm::CCAssignFn *fixedArgFn() const;
298 /// Return the function that analyzes variable argument list functions.
299 llvm::CCAssignFn *varArgFn() const;
301 const uint16_t *shadowRegs() const;
303 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
306 /// Return the type of the register which is used to pass an argument or
307 /// return a value. This function returns f64 if the argument is an i64
308 /// value which has been generated as a result of softening an f128 value.
309 /// Otherwise, it just returns VT.
310 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
311 bool IsSoftFloat) const;
313 template<typename Ty>
314 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
315 const SDNode *CallNode, const Type *RetTy) const;
318 CallingConv::ID CallConv;
320 SpecialCallingConvType SpecialCallingConv;
321 SmallVector<ByValArgInfo, 2> ByValArgs;
325 const MipsSubtarget *Subtarget;
327 bool HasMips64, IsN64, IsO32;
331 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
332 // Lower Operand helpers
333 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
334 CallingConv::ID CallConv, bool isVarArg,
335 const SmallVectorImpl<ISD::InputArg> &Ins,
336 DebugLoc dl, SelectionDAG &DAG,
337 SmallVectorImpl<SDValue> &InVals,
338 const SDNode *CallNode, const Type *RetTy) const;
340 // Lower Operand specifics
341 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
342 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
343 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
344 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
345 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
346 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
347 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
348 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
349 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
350 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
351 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
352 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
353 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
354 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
355 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
356 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
357 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
358 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
359 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
361 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
362 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
363 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
365 /// isEligibleForTailCallOptimization - Check whether the call is eligible
366 /// for tail call optimization.
368 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
369 unsigned NextStackOffset,
370 const MipsFunctionInfo& FI) const = 0;
372 /// copyByValArg - Copy argument registers which were used to pass a byval
373 /// argument to the stack. Create a stack frame object for the byval
375 void copyByValRegs(SDValue Chain, DebugLoc DL,
376 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
377 const ISD::ArgFlagsTy &Flags,
378 SmallVectorImpl<SDValue> &InVals,
379 const Argument *FuncArg,
380 const MipsCC &CC, const ByValArgInfo &ByVal) const;
382 /// passByValArg - Pass a byval argument in registers or on stack.
383 void passByValArg(SDValue Chain, DebugLoc DL,
384 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
385 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
386 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
387 const MipsCC &CC, const ByValArgInfo &ByVal,
388 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
390 /// writeVarArgRegs - Write variable function arguments passed in registers
391 /// to the stack. Also create a stack frame object for the first variable
393 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
394 SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
397 LowerFormalArguments(SDValue Chain,
398 CallingConv::ID CallConv, bool isVarArg,
399 const SmallVectorImpl<ISD::InputArg> &Ins,
400 DebugLoc dl, SelectionDAG &DAG,
401 SmallVectorImpl<SDValue> &InVals) const;
403 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
404 SDValue Arg, DebugLoc DL, bool IsTailCall,
405 SelectionDAG &DAG) const;
408 LowerCall(TargetLowering::CallLoweringInfo &CLI,
409 SmallVectorImpl<SDValue> &InVals) const;
412 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
414 const SmallVectorImpl<ISD::OutputArg> &Outs,
415 LLVMContext &Context) const;
418 LowerReturn(SDValue Chain,
419 CallingConv::ID CallConv, bool isVarArg,
420 const SmallVectorImpl<ISD::OutputArg> &Outs,
421 const SmallVectorImpl<SDValue> &OutVals,
422 DebugLoc dl, SelectionDAG &DAG) const;
424 // Inline asm support
425 ConstraintType getConstraintType(const std::string &Constraint) const;
427 /// Examine constraint string and operand type and determine a weight value.
428 /// The operand object must already have been set up with the operand type.
429 ConstraintWeight getSingleConstraintMatchWeight(
430 AsmOperandInfo &info, const char *constraint) const;
432 std::pair<unsigned, const TargetRegisterClass*>
433 getRegForInlineAsmConstraint(const std::string &Constraint,
436 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
437 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
438 /// true it means one of the asm constraint of the inline asm instruction
439 /// being processed is 'm'.
440 virtual void LowerAsmOperandForConstraint(SDValue Op,
441 std::string &Constraint,
442 std::vector<SDValue> &Ops,
443 SelectionDAG &DAG) const;
445 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
447 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
449 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
451 bool IsMemset, bool ZeroMemset,
453 MachineFunction &MF) const;
455 /// isFPImmLegal - Returns true if the target can instruction select the
456 /// specified FP immediate natively. If false, the legalizer will
457 /// materialize the FP immediate as a load from a constant pool.
458 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
460 virtual unsigned getJumpTableEncoding() const;
462 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
463 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
464 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
465 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
466 bool Nand = false) const;
467 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
468 MachineBasicBlock *BB, unsigned Size) const;
469 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
470 MachineBasicBlock *BB, unsigned Size) const;
473 /// Create MipsTargetLowering objects.
474 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
475 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
478 #endif // MipsISELLOWERING_H