1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
75 // Node used to insert integers to accumulator.
106 // EXTR.W instrinsic nodes.
116 // DPA.W intrinsic nodes.
152 // DSP setcc and select_cc nodes.
156 // Vector comparisons.
157 // These take a vector and return a boolean.
163 // These take a vector and return a vector bitmask.
170 // Element-wise vector max/min.
176 // Vector Shuffle with mask as an operand
177 VSHF, // Generic shuffle
178 SHF, // 4-element set shuffle.
179 ILVEV, // Interleave even elements
180 ILVOD, // Interleave odd elements
181 ILVL, // Interleave left elements
182 ILVR, // Interleave right elements
183 PCKEV, // Pack even elements
184 PCKOD, // Pack odd elements
187 INSVE, // Copy element from one vector to another
189 // Combined (XOR (OR $a, $b), -1)
192 // Extended vector element extraction
196 // Load/Store Left/Right nodes.
197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
208 //===--------------------------------------------------------------------===//
209 // TargetLowering Implementation
210 //===--------------------------------------------------------------------===//
211 class MipsFunctionInfo;
214 class MipsTargetLowering : public TargetLowering {
217 explicit MipsTargetLowering(MipsTargetMachine &TM);
219 static const MipsTargetLowering *create(MipsTargetMachine &TM);
221 /// createFastISel - This method returns a target specific FastISel object,
222 /// or null if the target does not support "fast" ISel.
223 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
224 const TargetLibraryInfo *libInfo) const override;
226 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
228 void LowerOperationWrapper(SDNode *N,
229 SmallVectorImpl<SDValue> &Results,
230 SelectionDAG &DAG) const override;
232 /// LowerOperation - Provide custom lowering hooks for some operations.
233 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
235 /// ReplaceNodeResults - Replace the results of node with an illegal result
236 /// type with new values built out of custom code.
238 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
239 SelectionDAG &DAG) const override;
241 /// getTargetNodeName - This method returns the name of a target specific
243 const char *getTargetNodeName(unsigned Opcode) const override;
245 /// getSetCCResultType - get the ISD::SETCC result ValueType
246 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
248 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
251 EmitInstrWithCustomInserter(MachineInstr *MI,
252 MachineBasicBlock *MBB) const override;
255 bool operator()(const char *S1, const char *S2) const {
256 return strcmp(S1, S2) < 0;
261 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
263 // This method creates the following nodes, which are necessary for
264 // computing a local symbol's address:
266 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
267 template <class NodeTy>
268 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
269 bool IsN32OrN64) const {
271 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
272 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
273 getTargetNode(N, Ty, DAG, GOTFlag));
274 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
275 MachinePointerInfo::getGOT(), false, false,
277 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
278 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
279 getTargetNode(N, Ty, DAG, LoFlag));
280 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
283 // This method creates the following nodes, which are necessary for
284 // computing a global symbol's address:
286 // (load (wrapper $gp, %got(sym)))
287 template<class NodeTy>
288 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
289 unsigned Flag, SDValue Chain,
290 const MachinePointerInfo &PtrInfo) const {
292 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
293 getTargetNode(N, Ty, DAG, Flag));
294 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
297 // This method creates the following nodes, which are necessary for
298 // computing a global symbol's address in large-GOT mode:
300 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
301 template<class NodeTy>
302 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
303 unsigned HiFlag, unsigned LoFlag,
305 const MachinePointerInfo &PtrInfo) const {
307 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
308 getTargetNode(N, Ty, DAG, HiFlag));
309 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
310 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
311 getTargetNode(N, Ty, DAG, LoFlag));
312 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
316 // This method creates the following nodes, which are necessary for
317 // computing a symbol's address in non-PIC mode:
319 // (add %hi(sym), %lo(sym))
320 template<class NodeTy>
321 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
323 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
324 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
325 return DAG.getNode(ISD::ADD, DL, Ty,
326 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
327 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
330 /// This function fills Ops, which is the list of operands that will later
331 /// be used when a function call node is created. It also generates
332 /// copyToReg nodes to set up argument registers.
334 getOpndList(SmallVectorImpl<SDValue> &Ops,
335 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
336 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
337 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
339 /// ByValArgInfo - Byval argument information.
340 struct ByValArgInfo {
341 unsigned FirstIdx; // Index of the first register used.
342 unsigned NumRegs; // Number of registers used for this argument.
343 unsigned Address; // Offset of the stack area used to pass this argument.
345 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
348 /// MipsCC - This class provides methods used to analyze formal and call
349 /// arguments and inquire about calling convention information.
352 enum SpecialCallingConvType {
353 Mips16RetHelperConv, NoSpecialCallingConv
356 MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info,
357 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv);
360 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
361 bool IsVarArg, bool IsSoftFloat,
362 const SDNode *CallNode,
363 std::vector<ArgListEntry> &FuncArgs);
364 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
366 Function::const_arg_iterator FuncArg);
368 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
369 bool IsSoftFloat, const SDNode *CallNode,
370 const Type *RetTy) const;
372 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
373 bool IsSoftFloat, const Type *RetTy) const;
375 const CCState &getCCInfo() const { return CCInfo; }
377 /// hasByValArg - Returns true if function has byval arguments.
378 bool hasByValArg() const { return !ByValArgs.empty(); }
380 /// regSize - Size (in number of bits) of integer registers.
381 unsigned regSize() const { return IsO32 ? 4 : 8; }
383 /// numIntArgRegs - Number of integer registers available for calls.
384 unsigned numIntArgRegs() const;
386 /// reservedArgArea - The size of the area the caller reserves for
387 /// register arguments. This is 16-byte if ABI is O32.
388 unsigned reservedArgArea() const;
390 /// Return pointer to array of integer argument registers.
391 const MCPhysReg *intArgRegs() const;
393 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
394 byval_iterator byval_begin() const { return ByValArgs.begin(); }
395 byval_iterator byval_end() const { return ByValArgs.end(); }
398 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
399 CCValAssign::LocInfo LocInfo,
400 ISD::ArgFlagsTy ArgFlags);
402 /// useRegsForByval - Returns true if the calling convention allows the
403 /// use of registers to pass byval arguments.
404 bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
406 /// Return the function that analyzes fixed argument list functions.
407 llvm::CCAssignFn *fixedArgFn() const;
409 /// Return the function that analyzes variable argument list functions.
410 llvm::CCAssignFn *varArgFn() const;
412 const MCPhysReg *shadowRegs() const;
414 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
417 /// Return the type of the register which is used to pass an argument or
418 /// return a value. This function returns f64 if the argument is an i64
419 /// value which has been generated as a result of softening an f128 value.
420 /// Otherwise, it just returns VT.
421 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
422 bool IsSoftFloat) const;
424 template<typename Ty>
425 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
426 const SDNode *CallNode, const Type *RetTy) const;
429 CallingConv::ID CallConv;
431 SpecialCallingConvType SpecialCallingConv;
432 SmallVector<ByValArgInfo, 2> ByValArgs;
435 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
436 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
439 const MipsSubtarget &Subtarget;
442 // Create a TargetGlobalAddress node.
443 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
444 unsigned Flag) const;
446 // Create a TargetExternalSymbol node.
447 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
448 unsigned Flag) const;
450 // Create a TargetBlockAddress node.
451 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
452 unsigned Flag) const;
454 // Create a TargetJumpTable node.
455 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
456 unsigned Flag) const;
458 // Create a TargetConstantPool node.
459 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
460 unsigned Flag) const;
462 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const;
463 // Lower Operand helpers
464 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
465 CallingConv::ID CallConv, bool isVarArg,
466 const SmallVectorImpl<ISD::InputArg> &Ins,
467 SDLoc dl, SelectionDAG &DAG,
468 SmallVectorImpl<SDValue> &InVals,
469 const SDNode *CallNode, const Type *RetTy) const;
471 // Lower Operand specifics
472 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
475 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
476 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
477 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
480 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
481 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
482 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
483 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
484 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
485 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
486 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
487 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
488 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
489 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
490 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
492 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
493 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
495 /// isEligibleForTailCallOptimization - Check whether the call is eligible
496 /// for tail call optimization.
498 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
499 unsigned NextStackOffset,
500 const MipsFunctionInfo& FI) const = 0;
502 /// copyByValArg - Copy argument registers which were used to pass a byval
503 /// argument to the stack. Create a stack frame object for the byval
505 void copyByValRegs(SDValue Chain, SDLoc DL,
506 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
507 const ISD::ArgFlagsTy &Flags,
508 SmallVectorImpl<SDValue> &InVals,
509 const Argument *FuncArg,
510 const MipsCC &CC, const ByValArgInfo &ByVal) const;
512 /// passByValArg - Pass a byval argument in registers or on stack.
513 void passByValArg(SDValue Chain, SDLoc DL,
514 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
515 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
516 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
517 const MipsCC &CC, const ByValArgInfo &ByVal,
518 const ISD::ArgFlagsTy &Flags, bool isLittle) const;
520 /// writeVarArgRegs - Write variable function arguments passed in registers
521 /// to the stack. Also create a stack frame object for the first variable
523 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
524 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
527 LowerFormalArguments(SDValue Chain,
528 CallingConv::ID CallConv, bool isVarArg,
529 const SmallVectorImpl<ISD::InputArg> &Ins,
530 SDLoc dl, SelectionDAG &DAG,
531 SmallVectorImpl<SDValue> &InVals) const override;
533 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
534 SDValue Arg, SDLoc DL, bool IsTailCall,
535 SelectionDAG &DAG) const;
537 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
538 SmallVectorImpl<SDValue> &InVals) const override;
540 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
542 const SmallVectorImpl<ISD::OutputArg> &Outs,
543 LLVMContext &Context) const override;
545 SDValue LowerReturn(SDValue Chain,
546 CallingConv::ID CallConv, bool isVarArg,
547 const SmallVectorImpl<ISD::OutputArg> &Outs,
548 const SmallVectorImpl<SDValue> &OutVals,
549 SDLoc dl, SelectionDAG &DAG) const override;
551 // Inline asm support
553 getConstraintType(const std::string &Constraint) const override;
555 /// Examine constraint string and operand type and determine a weight value.
556 /// The operand object must already have been set up with the operand type.
557 ConstraintWeight getSingleConstraintMatchWeight(
558 AsmOperandInfo &info, const char *constraint) const override;
560 /// This function parses registers that appear in inline-asm constraints.
561 /// It returns pair (0, 0) on failure.
562 std::pair<unsigned, const TargetRegisterClass *>
563 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const;
565 std::pair<unsigned, const TargetRegisterClass*>
566 getRegForInlineAsmConstraint(const std::string &Constraint,
567 MVT VT) const override;
569 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
570 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
571 /// true it means one of the asm constraint of the inline asm instruction
572 /// being processed is 'm'.
573 void LowerAsmOperandForConstraint(SDValue Op,
574 std::string &Constraint,
575 std::vector<SDValue> &Ops,
576 SelectionDAG &DAG) const override;
578 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
580 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
582 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
584 bool IsMemset, bool ZeroMemset,
586 MachineFunction &MF) const override;
588 /// isFPImmLegal - Returns true if the target can instruction select the
589 /// specified FP immediate natively. If false, the legalizer will
590 /// materialize the FP immediate as a load from a constant pool.
591 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
593 unsigned getJumpTableEncoding() const override;
595 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
596 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
597 MachineBasicBlock *BB,
598 unsigned Size, unsigned DstReg,
599 unsigned SrcRec) const;
601 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
602 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
603 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
604 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
605 bool Nand = false) const;
606 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
607 MachineBasicBlock *BB, unsigned Size) const;
608 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
609 MachineBasicBlock *BB, unsigned Size) const;
610 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
613 /// Create MipsTargetLowering objects.
614 const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
615 const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
618 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
619 const TargetLibraryInfo *libInfo);
623 #endif // MipsISELLOWERING_H