lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
  16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  19 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  20 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  21 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  22
  23 // Mips-specific dsp nodes
  24 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  25                                         SDTCisVT<2, untyped>]>;
  26 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  27                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  28 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  29                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  30 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  31                                              SDTCisVT<2, i32>]>;
  32
  33 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  35
  36 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  37   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  38
  39 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  40 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  41 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  45
  46 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  47 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  48
  49 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  53 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  54
  55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  56 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  58 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  59 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  61 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  62 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  63
  64 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  65 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  72 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  73
  74 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  76 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  77 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  78 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  79 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  80 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  83 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  84 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  85
  86 // Flags.
  87 class Uses<list<Register> Regs> {
  88   list<Register> Uses = Regs;
  89 }
  90
  91 class Defs<list<Register> Regs> {
  92   list<Register> Defs = Regs;
  93 }
  94
  95 // Instruction encoding.
  96 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  97 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  98 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  99 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 100 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 101 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 102 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 103 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 104 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 105 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 106 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 107 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 108 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 109 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 110 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 111 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 112 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 113 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 114 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 115 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 116 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 117 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 118 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 119 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 120 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 121 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 122 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 123 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 124 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 125 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 126 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 127 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 128 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 129 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 130 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 131 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 132 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 133 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 134 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 135 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 136 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 137 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 138 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 139 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 140 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 141 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 142 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 143 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 144 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 145 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 146 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 147 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 148 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 149 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 150 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 151 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 152 class MFHI_ENC : MFHI_FMT<0b010000>;
 153 class MFLO_ENC : MFHI_FMT<0b010010>;
 154 class MTHI_ENC : MTHI_FMT<0b010001>;
 155 class MTLO_ENC : MTHI_FMT<0b010011>;
 156 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 157 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 158 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 159 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 160 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 161 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 162 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 163 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 164 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 165 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 166 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 167 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 168 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 169 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 170 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 171 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 172 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 173 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 174 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 175 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 176 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 177 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 178 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 179 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 180 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 181 class REPL_QB_ENC : REPL_FMT<0b00010>;
 182 class REPL_PH_ENC : REPL_FMT<0b01010>;
 183 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 184 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 185 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 186 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 187 class LWX_ENC : LX_FMT<0b00000>;
 188 class LHX_ENC : LX_FMT<0b00100>;
 189 class LBUX_ENC : LX_FMT<0b00110>;
 190 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 191 class INSV_ENC : INSV_FMT<0b001100>;
 192
 193 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 194 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 195 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 196 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 197 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 198 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 199 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 200 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 201 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 202 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 203 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 204 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 205 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 206 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 207 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 208
 209 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 210 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 211 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 212 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 213 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 214 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 215 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 216 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 217 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 218 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 219 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 220 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 221 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 222 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 223 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 224 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 225 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 226 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 227 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 228 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 229 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 230 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 231 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 232 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 233 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 234 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 235 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 236 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 237 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 238 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 239 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 240 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 241 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 242 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 243 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 244 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 245 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 246 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 247 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 248 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 249 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 250 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 251 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 252 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 253 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 254 class APPEND_ENC : APPEND_FMT<0b00000>;
 255 class BALIGN_ENC : APPEND_FMT<0b10000>;
 256 class PREPEND_ENC : APPEND_FMT<0b00001>;
 257
 258 // Instruction desc.
 259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 260                         InstrItinClass itin, RegisterOperand ROD,
 261                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 262   dag OutOperandList = (outs ROD:$rd);
 263   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 264   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 265   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 266   InstrItinClass Itinerary = itin;
 267   string BaseOpcode = instr_asm;
 268 }
 269
 270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 271                            InstrItinClass itin, RegisterOperand ROD,
 272                            RegisterOperand ROS = ROD> {
 273   dag OutOperandList = (outs ROD:$rd);
 274   dag InOperandList = (ins ROS:$rs);
 275   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 276   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 277   InstrItinClass Itinerary = itin;
 278 }
 279
 280 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 281                              InstrItinClass itin, RegisterOperand ROS,
 282                              RegisterOperand ROT = ROS> {
 283   dag OutOperandList = (outs);
 284   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 285   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 286   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 287   InstrItinClass Itinerary = itin;
 288 }
 289
 290 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 291                              InstrItinClass itin, RegisterOperand ROD,
 292                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 293   dag OutOperandList = (outs ROD:$rd);
 294   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 295   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 296   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 297   InstrItinClass Itinerary = itin;
 298   string BaseOpcode = instr_asm;
 299 }
 300
 301 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 302                                InstrItinClass itin, RegisterOperand ROT,
 303                                RegisterOperand ROS = ROT> {
 304   dag OutOperandList = (outs ROT:$rt);
 305   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 306   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 307   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 308   InstrItinClass Itinerary = itin;
 309   string Constraints = "$src = $rt";
 310   string BaseOpcode = instr_asm;
 311 }
 312
 313 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 314                              InstrItinClass itin, RegisterOperand ROD,
 315                              RegisterOperand ROT = ROD> {
 316   dag OutOperandList = (outs ROD:$rd);
 317   dag InOperandList = (ins ROT:$rt);
 318   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 319   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 320   InstrItinClass Itinerary = itin;
 321   string BaseOpcode = instr_asm;
 322 }
 323
 324 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 325                      ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
 326   dag OutOperandList = (outs RO:$rd);
 327   dag InOperandList = (ins uimm16:$imm);
 328   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 329   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 330   InstrItinClass Itinerary = itin;
 331 }
 332
 333 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 334                            InstrItinClass itin, RegisterOperand RO> {
 335   dag OutOperandList = (outs RO:$rd);
 336   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 337   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 338   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 339   InstrItinClass Itinerary = itin;
 340   string BaseOpcode = instr_asm;
 341 }
 342
 343 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 344                            SDPatternOperator ImmPat, InstrItinClass itin,
 345                            RegisterOperand RO, Operand ImmOpnd> {
 346   dag OutOperandList = (outs RO:$rd);
 347   dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
 348   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 349   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 350   InstrItinClass Itinerary = itin;
 351   bit hasSideEffects = 1;
 352   string BaseOpcode = instr_asm;
 353 }
 354
 355 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 356                    InstrItinClass itin> {
 357   dag OutOperandList = (outs GPR32Opnd:$rd);
 358   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 359   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 360   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 361   InstrItinClass Itinerary = itin;
 362   bit mayLoad = 1;
 363 }
 364
 365 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 366                          InstrItinClass itin, RegisterOperand ROD,
 367                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 368   dag OutOperandList = (outs ROD:$rd);
 369   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 370   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 371   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 372   InstrItinClass Itinerary = itin;
 373   string BaseOpcode = instr_asm;
 374 }
 375
 376 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 377                        Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
 378   dag OutOperandList = (outs GPR32Opnd:$rt);
 379   dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
 380   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 381   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 382                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
 383   InstrItinClass Itinerary = itin;
 384   string Constraints = "$src = $rt";
 385 }
 386
 387 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 388                               InstrItinClass itin> {
 389   dag OutOperandList = (outs GPR32Opnd:$rt);
 390   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 391   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 392   InstrItinClass Itinerary = itin;
 393   string BaseOpcode = instr_asm;
 394 }
 395
 396 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 397                               InstrItinClass itin> {
 398   dag OutOperandList = (outs GPR32Opnd:$rt);
 399   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
 400   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 401   InstrItinClass Itinerary = itin;
 402   string BaseOpcode = instr_asm;
 403 }
 404
 405 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 406   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 407   dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
 408   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 409   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 410                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 411   string Constraints = "$acin = $ac";
 412 }
 413
 414 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 415   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 416   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 417   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 418   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 419                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 420   string Constraints = "$acin = $ac";
 421 }
 422
 423 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 424   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 425   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 426   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 427   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 428                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 429   string Constraints = "$acin = $ac";
 430 }
 431
 432 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 433                       InstrItinClass itin> {
 434   dag OutOperandList = (outs GPR32Opnd:$rd);
 435   dag InOperandList = (ins uimm16:$mask);
 436   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 437   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 438   InstrItinClass Itinerary = itin;
 439 }
 440
 441 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 442                       InstrItinClass itin> {
 443   dag OutOperandList = (outs);
 444   dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
 445   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 446   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 447   InstrItinClass Itinerary = itin;
 448 }
 449
 450 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 451   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 452   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 453   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 454   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 455                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 456   string Constraints = "$acin = $ac";
 457   string BaseOpcode = instr_asm;
 458 }
 459
 460 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 461                      InstrItinClass itin> {
 462   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 463   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 464   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 465   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 466   InstrItinClass Itinerary = itin;
 467   bit isCommutable = 1;
 468   string BaseOpcode = instr_asm;
 469 }
 470
 471 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 472                      InstrItinClass itin> {
 473   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 474   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 475   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 476   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 477                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 478   InstrItinClass Itinerary = itin;
 479   string Constraints = "$acin = $ac";
 480   string BaseOpcode = instr_asm;
 481 }
 482
 483 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 484                      InstrItinClass itin> {
 485   dag OutOperandList = (outs GPR32Opnd:$rd);
 486   dag InOperandList = (ins RO:$ac);
 487   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 488   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 489   InstrItinClass Itinerary = itin;
 490 }
 491
 492 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 493   dag OutOperandList = (outs RO:$ac);
 494   dag InOperandList = (ins GPR32Opnd:$rs);
 495   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 496   InstrItinClass Itinerary = itin;
 497 }
 498
 499 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 500   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 501   bit usesCustomInserter = 1;
 502 }
 503
 504 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 505   dag OutOperandList = (outs);
 506   dag InOperandList = (ins brtarget:$offset);
 507   string AsmString = !strconcat(instr_asm, "\t$offset");
 508   InstrItinClass Itinerary = itin;
 509   bit isBranch = 1;
 510   bit isTerminator = 1;
 511   bit hasDelaySlot = 1;
 512 }
 513
 514 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 515                      InstrItinClass itin> {
 516   dag OutOperandList = (outs GPR32Opnd:$rt);
 517   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 518   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 519   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 520   InstrItinClass Itinerary = itin;
 521   string Constraints = "$src = $rt";
 522   string BaseOpcode = instr_asm;
 523 }
 524
 525 //===----------------------------------------------------------------------===//
 526 // MIPS DSP Rev 1
 527 //===----------------------------------------------------------------------===//
 528
 529 // Addition/subtraction
 530 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 531                                        DSPROpnd, DSPROpnd>, IsCommutable,
 532                      Defs<[DSPOutFlag20]>;
 533
 534 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 535                                          NoItinerary, DSPROpnd, DSPROpnd>,
 536                        IsCommutable, Defs<[DSPOutFlag20]>;
 537
 538 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 539                                        DSPROpnd, DSPROpnd>,
 540                      Defs<[DSPOutFlag20]>;
 541
 542 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 543                                          NoItinerary, DSPROpnd, DSPROpnd>,
 544                        Defs<[DSPOutFlag20]>;
 545
 546 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 547                                        DSPROpnd, DSPROpnd>, IsCommutable,
 548                      Defs<[DSPOutFlag20]>;
 549
 550 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 551                                          NoItinerary, DSPROpnd, DSPROpnd>,
 552                        IsCommutable, Defs<[DSPOutFlag20]>;
 553
 554 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 555                                        DSPROpnd, DSPROpnd>,
 556                      Defs<[DSPOutFlag20]>;
 557
 558 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 559                                          NoItinerary, DSPROpnd, DSPROpnd>,
 560                        Defs<[DSPOutFlag20]>;
 561
 562 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 563                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 564                       IsCommutable, Defs<[DSPOutFlag20]>;
 565
 566 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 567                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 568                       Defs<[DSPOutFlag20]>;
 569
 570 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 571                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 572                    Defs<[DSPCarry]>;
 573
 574 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 575                                      GPR32Opnd, GPR32Opnd>,
 576                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 577
 578 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 579                                       GPR32Opnd, GPR32Opnd>;
 580
 581 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 582                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 583
 584 // Absolute value
 585 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 586                                               NoItinerary, DSPROpnd>,
 587                        Defs<[DSPOutFlag20]>;
 588
 589 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 590                                              NoItinerary, GPR32Opnd>,
 591                       Defs<[DSPOutFlag20]>;
 592
 593 // Precision reduce/expand
 594 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 595                                                  int_mips_precrq_qb_ph,
 596                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 597
 598 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 599                                                 int_mips_precrq_ph_w,
 600                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 601
 602 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 603                                                    int_mips_precrq_rs_ph_w,
 604                                                    NoItinerary, DSPROpnd,
 605                                                    GPR32Opnd>,
 606                             Defs<[DSPOutFlag22]>;
 607
 608 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 609                                                     int_mips_precrqu_s_qb_ph,
 610                                                     NoItinerary, DSPROpnd,
 611                                                     DSPROpnd>,
 612                              Defs<[DSPOutFlag22]>;
 613
 614 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 615                                                  int_mips_preceq_w_phl,
 616                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 617
 618 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 619                                                  int_mips_preceq_w_phr,
 620                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 621
 622 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 623                                                    int_mips_precequ_ph_qbl,
 624                                                    NoItinerary, DSPROpnd>;
 625
 626 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 627                                                    int_mips_precequ_ph_qbr,
 628                                                    NoItinerary, DSPROpnd>;
 629
 630 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 631                                                     int_mips_precequ_ph_qbla,
 632                                                     NoItinerary, DSPROpnd>;
 633
 634 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 635                                                     int_mips_precequ_ph_qbra,
 636                                                     NoItinerary, DSPROpnd>;
 637
 638 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 639                                                   int_mips_preceu_ph_qbl,
 640                                                   NoItinerary, DSPROpnd>;
 641
 642 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 643                                                   int_mips_preceu_ph_qbr,
 644                                                   NoItinerary, DSPROpnd>;
 645
 646 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 647                                                    int_mips_preceu_ph_qbla,
 648                                                    NoItinerary, DSPROpnd>;
 649
 650 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 651                                                    int_mips_preceu_ph_qbra,
 652                                                    NoItinerary, DSPROpnd>;
 653
 654 // Shift
 655 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 656                                           NoItinerary, DSPROpnd, uimm3>,
 657                      Defs<[DSPOutFlag22]>;
 658
 659 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 660                                            NoItinerary, DSPROpnd>,
 661                       Defs<[DSPOutFlag22]>;
 662
 663 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 664                                           NoItinerary, DSPROpnd, uimm3>;
 665
 666 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 667                                            NoItinerary, DSPROpnd>;
 668
 669 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 670                                           NoItinerary, DSPROpnd, uimm4>,
 671                      Defs<[DSPOutFlag22]>;
 672
 673 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 674                                            NoItinerary, DSPROpnd>,
 675                       Defs<[DSPOutFlag22]>;
 676
 677 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 678                                             immZExt4, NoItinerary, DSPROpnd,
 679                                             uimm4>,
 680                        Defs<[DSPOutFlag22]>;
 681
 682 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 683                                              NoItinerary, DSPROpnd>,
 684                         Defs<[DSPOutFlag22]>;
 685
 686 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 687                                           NoItinerary, DSPROpnd, uimm4>;
 688
 689 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 690                                            NoItinerary, DSPROpnd>;
 691
 692 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 693                                             immZExt4, NoItinerary, DSPROpnd,
 694                                             uimm4>;
 695
 696 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 697                                              NoItinerary, DSPROpnd>;
 698
 699 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 700                                            immZExt5, NoItinerary, GPR32Opnd,
 701                                            uimm5>,
 702                       Defs<[DSPOutFlag22]>;
 703
 704 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 705                                             NoItinerary, GPR32Opnd>,
 706                        Defs<[DSPOutFlag22]>;
 707
 708 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 709                                            immZExt5, NoItinerary, GPR32Opnd,
 710                                            uimm5>;
 711
 712 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 713                                             NoItinerary, GPR32Opnd>;
 714
 715 // Multiplication
 716 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 717                                               int_mips_muleu_s_ph_qbl,
 718                                               NoItinerary, DSPROpnd, DSPROpnd>,
 719                             Defs<[DSPOutFlag21]>;
 720
 721 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 722                                               int_mips_muleu_s_ph_qbr,
 723                                               NoItinerary, DSPROpnd, DSPROpnd>,
 724                             Defs<[DSPOutFlag21]>;
 725
 726 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 727                                              int_mips_muleq_s_w_phl,
 728                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 729                            IsCommutable, Defs<[DSPOutFlag21]>;
 730
 731 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 732                                              int_mips_muleq_s_w_phr,
 733                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 734                            IsCommutable, Defs<[DSPOutFlag21]>;
 735
 736 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 737                                           NoItinerary, DSPROpnd, DSPROpnd>,
 738                         IsCommutable, Defs<[DSPOutFlag21]>;
 739
 740 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 741                                               MipsMULSAQ_S_W_PH>,
 742                            Defs<[DSPOutFlag16_19]>;
 743
 744 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 745                          Defs<[DSPOutFlag16_19]>;
 746
 747 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 748                          Defs<[DSPOutFlag16_19]>;
 749
 750 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 751                           Defs<[DSPOutFlag16_19]>;
 752
 753 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 754                           Defs<[DSPOutFlag16_19]>;
 755
 756 // Move from/to hi/lo.
 757 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 758 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 759 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 760 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 761
 762 // Dot product with accumulate/subtract
 763 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 764
 765 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 766
 767 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 768
 769 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 770
 771 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 772                          Defs<[DSPOutFlag16_19]>;
 773
 774 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 775                          Defs<[DSPOutFlag16_19]>;
 776
 777 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 778                          Defs<[DSPOutFlag16_19]>;
 779
 780 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 781                          Defs<[DSPOutFlag16_19]>;
 782
 783 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 784 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 785 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 786 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 787 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 788 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 789
 790 // Comparison
 791 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 792                                                int_mips_cmpu_eq_qb, NoItinerary,
 793                                                DSPROpnd>,
 794                         IsCommutable, Defs<[DSPCCond]>;
 795
 796 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 797                                                int_mips_cmpu_lt_qb, NoItinerary,
 798                                                DSPROpnd>, Defs<[DSPCCond]>;
 799
 800 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 801                                                int_mips_cmpu_le_qb, NoItinerary,
 802                                                DSPROpnd>, Defs<[DSPCCond]>;
 803
 804 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 805                                                 int_mips_cmpgu_eq_qb,
 806                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 807                          IsCommutable;
 808
 809 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 810                                                 int_mips_cmpgu_lt_qb,
 811                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 812
 813 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 814                                                 int_mips_cmpgu_le_qb,
 815                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 816
 817 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 818                                               NoItinerary, DSPROpnd>,
 819                        IsCommutable, Defs<[DSPCCond]>;
 820
 821 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 822                                               NoItinerary, DSPROpnd>,
 823                        Defs<[DSPCCond]>;
 824
 825 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 826                                               NoItinerary, DSPROpnd>,
 827                        Defs<[DSPCCond]>;
 828
 829 // Misc
 830 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 831                                            NoItinerary, GPR32Opnd>;
 832
 833 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 834                                               NoItinerary, DSPROpnd, DSPROpnd>;
 835
 836 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 837                                     NoItinerary, DSPROpnd>;
 838
 839 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 840                                     NoItinerary, DSPROpnd>;
 841
 842 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 843                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 844
 845 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 846                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 847
 848 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 849                                             NoItinerary, DSPROpnd, DSPROpnd>,
 850                      Uses<[DSPCCond]>;
 851
 852 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 853                                             NoItinerary, DSPROpnd, DSPROpnd>,
 854                      Uses<[DSPCCond]>;
 855
 856 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 857
 858 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 859
 860 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 861
 862 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 863
 864 // Extr
 865 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 866                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 867
 868 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 869                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 870
 871 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 872                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 873
 874 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 875                                              NoItinerary>,
 876                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 877
 878 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 879                     Defs<[DSPOutFlag23]>;
 880
 881 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 882                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 883
 884 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 885                                               NoItinerary>,
 886                       Defs<[DSPOutFlag23]>;
 887
 888 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 889                                                NoItinerary>,
 890                        Defs<[DSPOutFlag23]>;
 891
 892 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 893                                                NoItinerary>,
 894                        Defs<[DSPOutFlag23]>;
 895
 896 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 897                                                 NoItinerary>,
 898                         Defs<[DSPOutFlag23]>;
 899
 900 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 901                                               NoItinerary>,
 902                       Defs<[DSPOutFlag23]>;
 903
 904 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 905                                                NoItinerary>,
 906                        Defs<[DSPOutFlag23]>;
 907
 908 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 909
 910 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 911
 912 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 913
 914 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 915
 916 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 917
 918 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 919                   Uses<[DSPPos, DSPSCount]>;
 920
 921 //===----------------------------------------------------------------------===//
 922 // MIPS DSP Rev 2
 923 // Addition/subtraction
 924 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 925                                        DSPROpnd, DSPROpnd>, IsCommutable,
 926                      Defs<[DSPOutFlag20]>;
 927
 928 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 929                                          NoItinerary, DSPROpnd, DSPROpnd>,
 930                        IsCommutable, Defs<[DSPOutFlag20]>;
 931
 932 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 933                                        DSPROpnd, DSPROpnd>,
 934                      Defs<[DSPOutFlag20]>;
 935
 936 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 937                                          NoItinerary, DSPROpnd, DSPROpnd>,
 938                        Defs<[DSPOutFlag20]>;
 939
 940 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 941                                          NoItinerary, DSPROpnd>, IsCommutable;
 942
 943 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 944                                            NoItinerary, DSPROpnd>, IsCommutable;
 945
 946 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 947                                          NoItinerary, DSPROpnd>;
 948
 949 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 950                                            NoItinerary, DSPROpnd>;
 951
 952 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 953                                          NoItinerary, DSPROpnd>, IsCommutable;
 954
 955 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 956                                            NoItinerary, DSPROpnd>, IsCommutable;
 957
 958 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 959                                          NoItinerary, DSPROpnd>;
 960
 961 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 962                                            NoItinerary, DSPROpnd>;
 963
 964 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 965                                         NoItinerary, GPR32Opnd>, IsCommutable;
 966
 967 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 968                                           NoItinerary, GPR32Opnd>, IsCommutable;
 969
 970 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 971                                         NoItinerary, GPR32Opnd>;
 972
 973 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 974                                           NoItinerary, GPR32Opnd>;
 975
 976 // Comparison
 977 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 978                                                  int_mips_cmpgdu_eq_qb,
 979                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 980                           IsCommutable, Defs<[DSPCCond]>;
 981
 982 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 983                                                  int_mips_cmpgdu_lt_qb,
 984                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 985                           Defs<[DSPCCond]>;
 986
 987 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 988                                                  int_mips_cmpgdu_le_qb,
 989                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 990                           Defs<[DSPCCond]>;
 991
 992 // Absolute
 993 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 994                                               NoItinerary, DSPROpnd>,
 995                        Defs<[DSPOutFlag20]>;
 996
 997 // Multiplication
 998 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 999                                        DSPROpnd>, IsCommutable,
1000                     Defs<[DSPOutFlag21]>;
1001
1002 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1003                                          NoItinerary, DSPROpnd>, IsCommutable,
1004                       Defs<[DSPOutFlag21]>;
1005
1006 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1007                                          NoItinerary, GPR32Opnd>, IsCommutable,
1008                       Defs<[DSPOutFlag21]>;
1009
1010 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1011                                           NoItinerary, GPR32Opnd>, IsCommutable,
1012                        Defs<[DSPOutFlag21]>;
1013
1014 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1015                                          NoItinerary, DSPROpnd, DSPROpnd>,
1016                        IsCommutable, Defs<[DSPOutFlag21]>;
1017
1018 // Dot product with accumulate/subtract
1019 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1020
1021 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1022
1023 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1024                           Defs<[DSPOutFlag16_19]>;
1025
1026 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1027                                               MipsDPAQX_SA_W_PH>,
1028                            Defs<[DSPOutFlag16_19]>;
1029
1030 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1031
1032 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1033
1034 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1035                           Defs<[DSPOutFlag16_19]>;
1036
1037 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1038                                               MipsDPSQX_SA_W_PH>,
1039                            Defs<[DSPOutFlag16_19]>;
1040
1041 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1042
1043 // Precision reduce/expand
1044 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1045                                                 int_mips_precr_qb_ph,
1046                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1047
1048 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1049                                                      int_mips_precr_sra_ph_w,
1050                                                      NoItinerary, DSPROpnd,
1051                                                      GPR32Opnd>;
1052
1053 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1054                                                       int_mips_precr_sra_r_ph_w,
1055                                                        NoItinerary, DSPROpnd,
1056                                                        GPR32Opnd>;
1057
1058 // Shift
1059 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1060                                           NoItinerary, DSPROpnd, uimm3>;
1061
1062 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1063                                            NoItinerary, DSPROpnd>;
1064
1065 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1066                                             immZExt3, NoItinerary, DSPROpnd,
1067                                             uimm3>;
1068
1069 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1070                                              NoItinerary, DSPROpnd>;
1071
1072 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1073                                           NoItinerary, DSPROpnd, uimm4>;
1074
1075 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1076                                            NoItinerary, DSPROpnd>;
1077
1078 // Misc
1079 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, immZExt5,
1080                                      NoItinerary>;
1081
1082 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, immZExt2,
1083                                      NoItinerary>;
1084
1085 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
1086                                       immZExt5, NoItinerary>;
1087
1088 // Pseudos.
1089 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1090                                                 NoItinerary>, Uses<[DSPPos]>;
1091
1092 // Instruction defs.
1093 // MIPS DSP Rev 1
1094 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1095 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1096 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1097 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1098 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1099 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1100 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1101 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1102 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1103 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1104 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1105 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1106 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1107 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1108 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1109 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1110 def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1111 def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1112 def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1113 def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1114 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1115 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1116 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1117 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1118 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1119 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1120 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1121 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1122 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1123 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1124 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1125 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1126 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1127 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1128 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1129 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1130 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1131 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1132 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1133 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1134 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1135 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1136 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1137 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1138 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1139 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1140 def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1141 def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1142 def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1143 def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1144 def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1145 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1146 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1147 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1148 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1149 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1150 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1151 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1152 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1153 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1154 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1155 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1156 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1157 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1158 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1159 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1160 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1161 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1162 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1163 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1164 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1165 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1166 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1167 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1168 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1169 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1170 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1171 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1172 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1173 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1174 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1175 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1176 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1177 def BITREV : BITREV_ENC, BITREV_DESC;
1178 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1179 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1180 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1181 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1182 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1183 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1184 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1185 def LWX : LWX_ENC, LWX_DESC;
1186 def LHX : LHX_ENC, LHX_DESC;
1187 def LBUX : LBUX_ENC, LBUX_DESC;
1188 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1189 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1190 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1191 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1192 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1193 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1194 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1195 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1196 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1197 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1198 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1199 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1200 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1201 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1202 def SHILO : SHILO_ENC, SHILO_DESC;
1203 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1204 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1205 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1206 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1207
1208 // MIPS DSP Rev 2
1209 let Predicates = [HasDSPR2] in {
1210
1211 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
1212 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1213 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC;
1214 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1215 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1216 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1217 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1218 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1219 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
1220 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1221 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC;
1222 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1223 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
1224 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1225 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC;
1226 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1227 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
1228 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1229 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
1230 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1231 def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC;
1232 def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC;
1233 def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC;
1234 def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1235 def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1236 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
1237 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC;
1238 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1239 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1240 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1241 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1242 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1243 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1244 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1245 def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1246 def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1247 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1248 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
1249 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
1250 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1251 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1252 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
1253 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
1254 def APPEND : APPEND_ENC, APPEND_DESC;
1255 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1256 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1257
1258 }
1259
1260 // Pseudos.
1261 let isPseudo = 1, isCodeGenOnly = 1 in {
1262   // Pseudo instructions for loading and storing accumulator registers.
1263   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1264   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1265
1266   // Pseudos for loading and storing ccond field of DSP control register.
1267   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1268   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1269 }
1270
1271 // Pseudo CMP and PICK instructions.
1272 class PseudoCMP<Instruction RealInst> :
1273   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1274   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1275
1276 class PseudoPICK<Instruction RealInst> :
1277   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1278   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1279   NeverHasSideEffects;
1280
1281 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1282 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1283 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1284 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1285 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1286 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1287
1288 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1289 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1290
1291 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1292
1293 // Patterns.
1294 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1295   Pat<pattern, result>, Requires<[pred]>;
1296
1297 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1298                     RegisterClass SrcRC> :
1299    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1300           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1301
1302 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1303 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1304 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1305 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1306
1307 def : DSPPat<(v2i16 (load addr:$a)),
1308              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1309 def : DSPPat<(v4i8 (load addr:$a)),
1310              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1311 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1312              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1313 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1314              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1315
1316 // Binary operations.
1317 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1318                 Predicate Pred = HasDSP> :
1319   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1320
1321 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1322 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1323 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1324 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1325 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1326 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1327 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1328 def : DSPBinPat<ADDU_QB, v4i8, add>;
1329 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1330 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1331 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1332 def : DSPBinPat<ADDSC, i32, addc>;
1333 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1334 def : DSPBinPat<ADDWC, i32, adde>;
1335
1336 // Shift immediate patterns.
1337 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1338                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1339   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1340
1341 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1342 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1343 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1344 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1345 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1346 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1347 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1348 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1349 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1350 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1351 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1352 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1353
1354 // SETCC/SELECT_CC patterns.
1355 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1356                   CondCode CC> :
1357   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1358          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1359                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1360                       (ValTy ZERO)))>;
1361
1362 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1363                      CondCode CC> :
1364   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1365          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1366                       (ValTy ZERO),
1367                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1368
1369 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1370                      CondCode CC> :
1371   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1372          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1373
1374 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1375                         CondCode CC> :
1376   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1377          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1378
1379 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1380 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1381 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1382 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1383 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1384 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1385 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1386 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1387 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1388 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1389 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1390 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1391
1392 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1393 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1394 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1395 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1396 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1397 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1398 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1399 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1400 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1401 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1402 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1403 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1404
1405 // Extr patterns.
1406 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1407   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1408          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1409
1410 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1411   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1412          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1413
1414 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1415 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1416 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1417 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1418 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1419 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1420 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1421 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1422 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1423 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1424 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1425 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1426
1427 // Indexed load patterns.
1428 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1429   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1430          (Instr i32:$base, i32:$index)>;
1431
1432 let AddedComplexity = 20 in {
1433   def : IndexedLoadPat<zextloadi8, LBUX>;
1434   def : IndexedLoadPat<sextloadi16, LHX>;
1435   def : IndexedLoadPat<load, LWX>;
1436 }